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The following document contains information on Cypress products. Although the document is marked
with the name “Spansion”, the company that originally developed the specification, Cypress will
continue to offer these products to new and existing customers.
Continuity of Specifications
There is no change to this document as a result of offering the device as a Cypress product. Any
changes that have been made are the result of normal document improvements and are noted in the
document history page, where supported. Future revisions will occur when appropriate, and changes
will be noted in a document history page.
Continuity of Ordering Part Numbers
Cypress continues to support existing part numbers. To order these products, please use only the
Ordering Part Numbers listed in this document.
For More Information
Please contact your local sales office for additional information about Cypress products and solutions.
About Cypress
Cypress (NASDAQ: CY) delivers high-performance, high-quality solutions at the heart of today’s most
advanced embedded systems, from automotive, industrial and networking platforms to highly
interactive consumer and mobile devices. With a broad, differentiated product portfolio that includes
®
NOR flash memories, F-RAM™ and SRAM, Traveo™ microcontrollers, the industry’s only PSoC
®
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®
capacitive touch-sensing controllers, and Wireless BLE Bluetooth Low-Energy and USB connectivity
solutions, Cypress is committed to providing its customers worldwide with consistent innovation, bestin-class support and exceptional system value.
MB9AB40NB Series
®
32-bit ARM Cortex®-M3 based Microcontroller
MB9AFB41LB/MB/NB, MB9AFB42LB/MB/NB,
MB9AFB44LB/MB/NB
Data Sheet (Full Production)
Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may occur.
Publication Number MB9AB40NB_DS706-00034
CONFIDENTIAL
Revision 4.0
Issue Date June 10, 2015
D a t a S h e e t
Notice On Data Sheet Designations
Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers
of product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to
verify that they have the latest information before finalizing their design. The following descriptions of
Spansion data sheet designations are presented here to highlight their presence and definitions.
Advance Information
The Advance Information designation indicates that Spansion Inc. is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
designation is likely to change, and in some cases, development on the product may discontinue.
Spansion Inc. therefore places the following conditions upon Advance Information content:
“This document contains information on one or more products under development at Spansion
Inc. The information is intended to help you evaluate this product. Do not design in this product
without contacting the factory. Spansion Inc. reserves the right to change or discontinue work on
this proposed product without notice.”
Preliminary
The Preliminary designation indicates that the product development has progressed such that a
commitment to production has taken place. This designation covers several aspects of the product life
cycle, including product qualification, initial production, and the subsequent phases in the manufacturing
process that occur before full production is achieved. Changes to the technical specifications presented
in a Preliminary document should be expected while keeping these aspects of production under
consideration. Spansion places the following conditions upon Preliminary content:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. The Preliminary status of this document indicates that product qualification
has been completed, and that initial production has begun. Due to the phases of the
manufacturing process that require maintaining efficiency and quality, this document may be
revised by subsequent versions or modifications due to changes in technical specifications.”
Combination
Some data sheets contain a combination of products with different designations (Advance Information,
Preliminary, or Full Production). This type of document distinguishes these products and their
designations wherever necessary, typically on the first page, the ordering information page, and pages
with the DC Characteristics table and the AC Erase and Program table (in the table notes). The
disclaimer on the first page refers the reader to the notice on this page.
Full Production (No Designation on Document)
When a product has been in production for a period of time such that no changes or only nominal
changes are expected, the Preliminary designation is removed from the data sheet. Nominal changes
may include those affecting the number of ordering part numbers available, such as the addition or
deletion of a speed option, temperature range, package type, or VIO range. Changes may also include
those needed to clarify a description or to correct a typographical error or incorrect specification.
Spansion Inc. applies the following conditions to documents in this category:
“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion Inc. deems the products to have been in sufficient production
volume such that subsequent versions of this document are not expected to change. However,
typographical or specification corrections, or modifications to the valid combinations offered may
occur.”
Questions regarding these document designations may be directed to your local sales office.
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
CONFIDENTIAL
MB9AB40NB Series
32-bit ARM® Cortex®-M3 based Microcontroller
MB9AFB41LB/MB/NB, MB9AFB42LB/MB/NB,
MB9AFB44LB/MB/NB
Data Sheet (Full Production)
 Description
The MB9AB40NB Series are highly integrated 32-bit microcontrollers dedicated for embedded controllers
with low-power consumption mode and competitive cost.
These series are based on the ARM Cortex-M3 Processor with on-chip Flash memory and SRAM, and have
peripheral functions such as various timers, ADCs, LCDC and Communication Interfaces (USB, UART,
CSIO, I2C).
The products which are described in this data sheet are placed into TYPE6 product categories in FM3
Family Peripheral Manual.
Note: ARM and Cortex are the trademarks of ARM Limited in the EU and other countries.
Publication Number MB9AB40NB_DS706-00034
Revision 4.0
Issue Date June 10, 2015
This document states the current technical specifications regarding the Spansion product(s) described herein. Spansion Inc. deems the products to have been in sufficient
production volume such that subsequent versions of this document are not expected to change. However, typographical or specification corrections, or modifications to the
valid combinations offered may occur.
CONFIDENTIAL
D a t a S h e e t
 Features
 32-bit ARM Cortex-M3 Core
 Processor version: r2p1
 Up to 40 MHz Frequency Operation
 Integrated Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and
48 peripheral interrupts and 16 priority levels
 24-bit System timer (Sys Tick): System timer for OS task management
 On-chip Memories
[Flash memory]
 Dual operation Flash memory
 Dual Operation Flash memory has the upper bank and the lower bank.
So, this series could implement erase, write and read operations
for each bank simultaneously.
 Main area: Up to 256 Kbytes (Up to 240 Kbytes upper bank + 16 Kbytes lower bank)
 Work area: 32 Kbytes (lower bank)
 Read cycle: 0 wait-cycle
 Security function for code protection
[SRAM]
This Series on-chip SRAM is composed of two independent SRAM (SRAM0, SRAM1). SRAM0 is
connected to I-code bus and D-code bus of Cortex-M3 core. SRAM1 is connected to System bus.
 SRAM0: Up to 16 Kbytes
 SRAM1: Up to 16 Kbytes
 External Bus Interface*
 Supports SRAM, NOR Flash memory device
 Up to 8 chip selects
 8/16-bit Data width
 Up to 25-bit Address bit
 Maximum area size : Up to 256 Mbytes
 Supports Address/Data multiplex
 Supports external RDY function
* : MB9AFB41LB, FB42LB and FB44LB do not support External Bus Interface.
 USB Interface
The USB interface is composed of Function and Host.
PLL for USB is built-in, USB clock can be generated by multiplication of Main clock.
[USB function]
 USB2.0 Full-Speed supported
 Max 6 EndPoint supported
 EndPoint 0 is control transfer
 EndPoint 1, 2 can select Bulk-transfer, Interrupt-transfer or Isochronous-transfer
 EndPoint 3 to 5 can select Bulk-transfer or Interrupt-transfer
 EndPoint 1 to 5 is comprised of Double Buffers.
 The size of each endpoint is according to the follows.
- Endpoint 0, 2 to 5: 64 bytes
- Endpoint 1: 256 bytes
[USB host]
 USB2.0 Full/Low-speed supported
 Bulk-transfer, interrupt-transfer and Isochronous-transfer support
 USB Device connected/dis-connected automatical detection
 Automatic processing of the IN/OUT token handshake packet
 Max 256-byte packet-length supported
 Wake-up function supported
2
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 LCD Controller (LCDC)
 Up to 40 SEG × 8 COM
 8 COM or 4 COM mode can be selected.
 Built-in internal dividing resistor
 LCD drive power supply (bias) pin (VV4 to VV0)
 With blinking function
 Multi-function Serial Interface (Max 8channels)
 4 channels with 16steps×9-bit FIFO (ch.4 to ch.7), 4 channels without FIFO (ch.0 to ch.3)
 Operation mode is selectable from the followings for each channel.
 UART
 CSIO
 I 2C
[UART]
 Full-duplex double buffer
 Selection with or without parity supported
 Built-in dedicated baud rate generator
 External clock available as a serial clock
 Hardware Flow control* : Automatically control the transmission by CTS/RTS (only ch.4)
 Various error detection functions available (parity errors, framing errors, and overrun errors)
* : MB9AFB41LB, FB42LB and FB44LB do not support Hardware Flow control.
[CSIO]
 Full-duplex double buffer
 Built-in dedicated baud rate generator
 Overrun error detection function available
2
[I C]
Standard-mode (Max 100 kbps) / Fast-mode (Max 400 kbps) supported
 DMA Controller (8 channels)
The DMA Controller has an independent bus from the CPU, so CPU and DMA Controller can process
simultaneously.







8 independently configured and operated channels
Transfer can be started by software or request from the built-in peripherals
Transfer address area: 32-bit (4 Gbytes)
Transfer mode: Block transfer/Burst transfer/Demand transfer
Transfer data type: byte/half-word/word
Transfer block count: 1 to 16
Number of transfers: 1 to 65536
 A/D Converter (Max 24 channels)
[12-bit A/D Converter]
 Successive Approximation type
 Built-in 2units
 Conversion time: 2.0 μs @ 2.7 V to 3.6 V
 Priority conversion available (priority at 2levels)
 Scanning conversion mode
 Built-in FIFO for conversion data storage (for SCAN conversion: 16steps, for Priority conversion:
4 steps)
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
3
D a t a S h e e t
 Base Timer (Max 8 channels)
Operation mode is selectable from the followings for each channel.




16-bit PWM timer
16-bit PPG timer
16-/32-bit reload timer
16-/32-bit PWC timer
 General-Purpose I/O Port
This series can use its pins as general-purpose I/O ports when they are not used for external bus or
peripherals. Moreover, the port relocate function is built in. It can set which I/O port the peripheral function
can be allocated to.





Capable of pull-up control per pin
Capable of reading pin level directly
Built-in the port relocate function
Up to 83 fast general-purpose I/O [email protected] pin Package
Some ports are 5 V tolerant.
See Pin Description to confirm the corresponding pins.
 Dual Timer (32/16-bit Down Counter)
The Dual Timer consists of two programmable 32-/16-bit down counters.
Operation mode is selectable from the followings for each channel.
 Free-running
 Periodic (=Reload)
 One-shot
 HDMI-CEC/Remote Control Receiver (Up to 2 channels)
 HDMI-CEC transmitter
 Header block automatic transmission by judging Signal free
 Generating status interrupt by detecting Arbitration lost
 Generating START, EOM, ACK automatically to output CEC transmission by setting 1 byte data
 Generating transmission status interrupt when transmitting 1 block (1 byte data and EOM/ACK)
 HDMI-CEC receiver
 Automatic ACK reply function available
 Line error detection function available
 Remote control receiver
 4 bytes reception buffer
 Repeat code detection function available
 Real-time clock (RTC)
The Real-time clock can count Year/Month/Day/Hour/Minute/Second/A day of the week from 01 to 99.
 The interrupt function with specifying date and time (Year/Month/Day/Hour/Minute/Second/A day of
the week.) is available. This function is also available by specifying only Year, Month, Day, Hour or
Minute.
 Timer interrupt function after set time or each set time.
 Capable of rewriting the time with continuing the time count.
 Leap year automatic count is available.
 Watch Counter
The Watch counter is used for wake up from sleep and timer mode.
Interval timer: up to 64 s (Max) @ Sub Clock : 32.768 kHz
 External Interrupt Controller Unit
 Up to 16 external interrupt input pins
 Include one non-maskable interrupt (NMI) input pin
4
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Watchdog Timer (2 channels)
A watchdog timer can generate interrupts or a reset when a time-out value is reached.
This series consists of two different watchdogs, a Hardware watchdog and a Software watchdog.
The Hardware watchdog timer is clocked by the built-in low-speed CR oscillator. Therefore, the Hardware
watchdog is active in any low-power consumption modes except RTC, Stop, Deep Standby RTC, Deep
Standby Stop modes.
 CRC (Cyclic Redundancy Check) Accelerator
The CRC accelerator calculates the CRC which has a heavy software processing load, and achieves a
reduction of the integrity check processing load for reception data and storage.
CCITT CRC16 and IEEE-802.3 CRC32 are supported.
 CCITT CRC16 Generator Polynomial: 0x1021
 IEEE-802.3 CRC32 Generator Polynomial: 0x04C11DB7
 Clock and Reset
[Clocks]
Selectable from five clock sources (2 external oscillators, 2 built-in CR oscillator, and Main PLL).





Main Clock:
Sub Clock:
Built-in high-speed CR Clock:
Built-in low-speed CR Clock:
Main PLL Clock
4 MHz to 48 MHz
32.768 kHz
4 MHz
100 kHz
[Resets]
 Reset requests from INITX pin
 Power on reset
 Software reset
 Watchdog timers reset
 Low-voltage detection reset
 Clock Super Visor reset
 Clock Super Visor (CSV)
Clocks generated by built-in CR oscillators are used to supervise abnormality of the external clocks.
 External clock failure (clock stop) is detected, reset is asserted.
 External frequency anomaly is detected, interrupt or reset is asserted.
 Low-Voltage Consumption Detector (LVD)
This Series includes 2-stage monitoring of voltage on the VCC pins. When the voltage falls below the
voltage that has been set, Low-Voltage Detector generates an interrupt or reset.
 LVD1: error reporting via interrupt
 LVD2: auto-reset operation
 Low-Power Consumption Mode
Six low-power consumption modes supported.






Sleep
Timer
RTC
Stop
Deep Standby RTC (selectable between keeping the value of RAM and not)
Deep Standby Stop (selectable between keeping the value of RAM and not)
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
5
D a t a S h e e t
 Debug
 Serial Wire JTAG Debug Port (SWJ-DP)
 Embedded Trace Macrocells (ETM).*
*: MB9AFB41LB/MB, FB42LB/MB, FB44LB/MB support only SWJ-DP.
 Unique ID
Unique value of the device (41-bit) is set.
 Power Supply
Wide range voltage:
6
CONFIDENTIAL
VCC
VCC
VCC
= 1.65 V to 3.6 V
= 3.0 V to 3.6 V (when USB is used)
= 2.2 V to 3.6 V (when LCDC is used)
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Product Lineup
 Memory size
Product name
On-chip
Flash
memory
MB9AFB41LB/MB/NB
MB9AFB42LB/MB/NB
MB9AFB44LB/MB/NB
Main area
64 Kbytes
128 Kbytes
256 Kbytes
Work area
32 Kbytes
32 Kbytes
32 Kbytes
SRAM0
SRAM1
Total
8 Kbytes
8 Kbytes
16 Kbytes
8 Kbytes
8 Kbytes
16 Kbytes
16 Kbytes
16 Kbytes
32 Kbytes
On-chip
SRAM
 Function
Product name
Pin count
MB9AFB41LB
MB9AFB42LB
MB9AFB44LB
MB9AFB41MB
MB9AFB42MB
MB9AFB44MB
MB9AFB41NB
MB9AFB42NB
MB9AFB44NB
64
80/96
Cortex-M3
40 MHz
1.65 V to 3.6 V
1ch.
8ch.
Addr: 21-bit (Max)
R/W Data: 8-bit (Max)
CS: 4 (Max)
Support: SRAM,
NOR Flash memory
100/112
CPU
Freq.
Power supply voltage range
USB2.0 (Function/Host)
DMAC
External Bus Interface
LCD Controller
MF Serial Interface
(UART/CSIO/I2C)
Base Timer
(PWC/Reload timer/PWM/PPG)
Dual Timer
HDMI-CEC/ Remote Control
Receiver
Real-Time Clock
Watch Counter
CRC Accelerator
Watchdog timer
-
20 SEG × 8COM
(Max)
Addr: 25-bit (Max)
R/W Data: 8-/16-bit
(Max)
CS: 8 (Max)
Support: SRAM,
NOR Flash memory
40 SEG × 8COM
(Max)
33 SEG × 8COM
(Max)
8ch. (Max)
ch.4 to ch.7: FIFO (16steps × 9-bit)
ch.0 to ch.3: No FIFO
8ch. (Max)
1 unit
2ch. (Max)
1 unit
1 unit
Yes
1ch. (SW) + 1ch. (HW)
8pins (Max) +
11pins (Max) +
16pins (Max) +
External Interrupts
NMI × 1
NMI × 1
NMI × 1
I/O ports
51 pins (Max)
66 pins (Max)
83 pins (Max)
12-bit A/D converter
12ch. (2 units)
17ch. (2 units)
24ch. (2 units)
CSV (Clock Super Visor)
Yes
LVD (Low-Voltage Detector)
2ch.
High-speed
4 MHz
Built-in
CR
Low-speed
100 kHz
Debug Function
SWJ-DP
SWJ-DP/ETM
Unique ID
Yes
Note: All signals of the peripheral function in each product cannot be allocated by limiting the pins of package.
It is necessary to use the port relocate function of the I/O port according to your function use.
See  Electrical Characteristics 5.AC Characteristics (3)Built-in CR Oscillation Characteristics for
accuracy of built-in CR.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
7
D a t a S h e e t
 Packages
Product name
Package
LQFP: FPT-64P-M38 (0.5mm pitch)
LQFP: FPT-64P-M39 (0.65mm pitch)
QFN: LCC-64P-M24 (0.5mm pitch)
LQFP: FPT-80P-M37 (0.5mm pitch)
LQFP: FPT-80P-M40 (0.65mm pitch)
BGA: BGA-96P-M07 (0.5mm pitch)
LQFP: FPT-100P-M23 (0.5mm pitch)
QFP: FPT-100P-M36 (0.65mm pitch)
BGA: BGA-112P-M04 (0.8mm pitch)
: Supported
MB9AFB41LB
MB9AFB42LB
MB9AFB44LB
MB9AFB41MB
MB9AFB42MB
MB9AFB44MB



-
-
-
-



-
MB9AFB41NB
MB9AFB42NB
MB9AFB44NB
-



Note: See Package Dimensions for detailed information on each package.
8
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Pin Assignment
 FPT-100P-M23
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1
P61/SOT5_0/TIOB2_2/UHCONX/SEG00
P62/SCK5_0/ADTG_3/SEG01/MOEX_1
P63/INT03_0/SEG02/MWEX_1
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1
P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1
P0C/SCK4_0/TIOA6_1/MALE_1
P0B/SOT4_0/TIOB6_1/MCSX0_1
P0A/SIN4_0/INT00_2/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/SEG05/MCSX2_1
P08/AN23/TRACED3/TIOA0_2/CTS4_2/SEG06/MCSX3_1
P07/AN22/TRACED2/ADTG_0/SCK4_2/SEG07/MCLKOUT_1
P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/SEG08/MCSX4_1
P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/SEG09/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
(TOP VIEW)
VCC
1
75
VSS
P50/INT00_0/SIN3_1/VV4/MADATA00_1
2
74
P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1
P51/INT01_0/SOT3_1/VV3/MADATA01_1
3
73
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P52/INT02_0/SCK3_1/VV2/MADATA02_1
4
72
P22/AN17/SOT0_0/TIOB7_1/SEG12
P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1
5
71
P23/AN16/SCK0_0/TIOA7_1/SEG13
P54/SOT6_0/TIOB1_2/VV0/MADATA04_1
6
70
P1F/AN15/ADTG_5/MAD23_1
P55/SCK6_0/ADTG_1/SEG39/MADATA05_1
7
69
P1E/AN14/RTS4_1/SEG14/MAD22_1
P56/INT08_2/SEG38/MADATA06_1
8
68
P1D/AN13/CTS4_1/SEG15/MAD21_1
P30/TIOB0_1/INT03_2/COM7/MADATA07_1
9
67
P1C/AN12/SCK4_1/SEG16/MAD20_1
P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1
10
66
P1B/AN11/SOT4_1/SEG17/MAD19_1
P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1
11
65
P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1
12
64
P19/AN09/SCK2_2/SEG19/MAD17_1
LQFP - 100
P34/TIOB4_1/MADATA11_1
13
63
P18/AN08/SOT2_2/SEG20/MAD16_1
P35/TIOB5_1/INT08_1/MADATA12_1
14
62
AVSS
P36/SIN5_2/INT09_1/MADATA13_1
15
61
AVRH
P37/SOT5_2/INT10_1/MADATA14_1
16
60
AVCC
P38/SCK5_2/INT11_1/MADATA15_1
17
59
P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1
44
45
46
P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1
PE0/MD1
50
43
P4D/TIOB4_0/SOT7_1/MAD07_1
VSS
42
P4B/TIOB2_0/SEG29/MAD05_1
P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1
49
41
P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1
48
40
P49/TIOB0_0/SOT3_2/SEG31/MAD03_1
PE3/X1
39
P48/INT14_1/SIN3_2/SEG32/MAD02_1
47
38
INITX
MD0
37
P47/X1A
PE2/X0
36
P46/X0A
VCC
35
51
VCC
25
34
P10/AN00/SEG28
VSS
VSS
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1
52
33
53
24
32
23
P3F/TIOA5_1/SEG35
C
P12/AN02/SOT1_1/SEG26/MAD10_1
P3E/TIOA4_1/SEG36
P45/TIOA5_0/SEG33/MAD01_1
54
31
22
P44/TIOA4_0/SEG34/MAD00_1
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1
P3D/TIOA3_1/SEG37
30
55
P43/TIOA3_0/ADTG_7
21
29
P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1
P3C/TIOA2_1/COM0
P42/TIOA2_0
56
28
20
27
P15/AN05/SOT0_1/SEG23/MAD13_1
P3B/TIOA1_1/COM1
26
P16/AN06/SCK0_1/SEG22/MAD14_1
57
VCC
58
19
P41/TIOA1_0/INT13_1
18
P40/TIOA0_0/INT12_1
P39/ADTG_2/COM3
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
9
D a t a S h e e t
 FPT-100P-M36
P50/INT00_0/SIN3_1/VV4/MADATA00_1
VCC
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1
P61/SOT5_0/TIOB2_2/UHCONX/SEG00
P62/SCK5_0/ADTG_3/SEG01/MOEX_1
P63/INT03_0/SEG02/MWEX_1
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1
P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1
P0C/SCK4_0/TIOA6_1/MALE_1
P0B/SOT4_0/TIOB6_1/MCSX0_1
P0A/SIN4_0/INT00_2/MCSX1_1
P09/TRACECLK/TIOB0_2/RTS4_2/SEG05/MCSX2_1
P08/AN23/TRACED3/TIOA0_2/CTS4_2/SEG06/MCSX3_1
P07/AN22/TRACED2/ADTG_0/SCK4_2/SEG07/MCLKOUT_1
P06/AN21/TRACED1/TIOB5_2/SOT4_2/INT01_1/SEG08/MCSX4_1
P05/AN20/TRACED0/TIOA5_2/SIN4_2/INT00_1/SEG09/MCSX5_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
VCC
VSS
P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
(TOP VIEW)
P51/INT01_0/SOT3_1/VV3/MADATA01_1
81
50
P22/AN17/SOT0_0/TIOB7_1/SEG12
P52/INT02_0/SCK3_1/VV2/MADATA02_1
82
49
P23/AN16/SCK0_0/TIOA7_1/SEG13
P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1
83
48
P1F/AN15/ADTG_5/MAD23_1
P54/SOT6_0/TIOB1_2/VV0/MADATA04_1
84
47
P1E/AN14/RTS4_1/SEG14/MAD22_1
P55/SCK6_0/ADTG_1/SEG39/MADATA05_1
85
46
P1D/AN13/CTS4_1/SEG15/MAD21_1
P56/INT08_2/SEG38/MADATA06_1
86
45
P1C/AN12/SCK4_1/SEG16/MAD20_1
P30/TIOB0_1/INT03_2/COM7/MADATA07_1
87
44
P1B/AN11/SOT4_1/SEG17/MAD19_1
P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1
88
43
P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1
P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1
89
42
P19/AN09/SCK2_2/SEG19/MAD17_1
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1
90
41
P18/AN08/SOT2_2/SEG20/MAD16_1
P34/TIOB4_1/MADATA11_1
91
40
AVSS
P35/TIOB5_1/INT08_1/MADATA12_1
92
39
AVRH
QFP - 100
P36/SIN5_2/INT09_1/MADATA13_1
93
38
AVCC
P37/SOT5_2/INT10_1/MADATA14_1
94
37
P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1
P38/SCK5_2/INT11_1/MADATA15_1
95
36
P16/AN06/SCK0_1/SEG22/MAD14_1
28
29
30
P10/AN00/SEG28
24
PE0/MD1
VCC
23
VSS
22
P4D/TIOB4_0/SOT7_1/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1
27
21
P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1
PE3/X1
20
P4B/TIOB2_0/SEG29/MAD05_1
26
19
P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1
25
18
P49/TIOB0_0/SOT3_2/SEG31/MAD03_1
MD0
17
PE2/X0
16
INITX
P48/INT14_1/SIN3_2/SEG32/MAD02_1
15
12
VSS
P47/X1A
11
C
14
10
P45/TIOA5_0/SEG33/MAD01_1
13
9
VCC
8
P44/TIOA4_0/SEG34/MAD00_1
P46/X0A
7
P42/TIOA2_0
P43/TIOA3_0/ADTG_7
6
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1
5
P12/AN02/SOT1_1/SEG26/MAD10_1
31
P41/TIOA1_0/INT13_1
32
P40/TIOA0_0/INT12_1
99
100
4
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1
P3C/TIOA2_1/COM0
P3D/TIOA3_1/SEG37
VCC
33
3
98
2
P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1
P3B/TIOA1_1/COM1
1
P15/AN05/SOT0_1/SEG23/MAD13_1
34
VSS
35
97
P3F/TIOA5_1/SEG35
96
P3E/TIOA4_1/SEG36
P39/ADTG_2/COM3
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
10
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 FPT-80P-M37/M40
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1/MRDY_1
P61/SOT5_0/TIOB2_2/UHCONX/SEG00
P62/SCK5_0/ADTG_3/SEG01/MOEX_1
P63/INT03_0/SEG02/MWEX_1
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0E/CTS4_0/TIOB3_2/SEG03/MDQM1_1
P0D/RTS4_0/TIOA3_2/SEG04/MDQM0_1
P0C/SCK4_0/TIOA6_1/MALE_1
P0B/SOT4_0/TIOB6_1/MCSX0_1
P0A/SIN4_0/INT00_2/MCSX1_1
P07/AN22/ADTG_0/SEG07/MCLKOUT_1
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI/MCSX6_1
P01/TCK/SWCLK
P00/TRSTX/MCSX7_1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
(TOP VIEW)
VCC
1
60
P20/AN19/INT05_0/CROUT_0/SEG10/MAD24_1
P50/INT00_0/SIN3_1/VV4/MADATA00_1
2
59
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P51/INT01_0/SOT3_1/VV3/MADATA01_1
3
58
P22/AN17/SOT0_0/TIOB7_1/SEG12
P52/INT02_0/SCK3_1/VV2/MADATA02_1
4
57
P23/AN16/SCK0_0/TIOA7_1/SEG13
P53/SIN6_0/TIOA1_2/INT07_2/VV1/MADATA03_1
5
56
P1B/AN11/SOT4_1/SEG17/MAD19_1
P54/SOT6_0/TIOB1_2/VV0/MADATA04_1
6
55
P1A/AN10/SIN4_1/INT05_1/SEG18/MAD18_1
P55/SCK6_0/ADTG_1/SEG39/MADATA05_1
7
54
P19/AN09/SCK2_2/SEG19/MAD17_1
P56/INT08_2/SEG38/MADATA06_1
8
53
P18/AN08/SOT2_2/SEG20/MAD16_1
P30/TIOB0_1/INT03_2/COM7/MADATA07_1
9
52
AVSS
P31/TIOB1_1/SCK6_1/INT04_2/COM6/MADATA08_1
10
51
AVRH
P32/TIOB2_1/SOT6_1/INT05_2/COM5/MADATA09_1
11
50
AVCC
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4/MADATA10_1
12
49
P17/AN07/SIN2_2/INT04_1/SEG21/MAD15_1
P39/ADTG_2/COM3
13
48
P16/AN06/SCK0_1/SEG22/MAD14_1
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
14
47
P15/AN05/SOT0_1/SEG23/MAD13_1
P3B/TIOA1_1/COM1
15
46
P14/AN04/SIN0_1/INT03_1/SEG24/MAD12_1
P3C/TIOA2_1/COM0
16
45
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25/MAD11_1
P3D/TIOA3_1/SEG37
17
44
P12/AN02/SOT1_1/SEG26/MAD10_1
P3E/TIOA4_1/SEG36
18
43
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27/MAD09_1
P3F/TIOA5_1/SEG35
19
42
P10/AN00/SEG28
VSS
20
41
VCC
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P44/TIOA4_0/SEG34/MAD00_1
P45/TIOA5_0/SEG33/MAD01_1
C
VSS
VCC
P46/X0A
P47/X1A
INITX
P48/INT14_1/SIN3_2/SEG32/MAD02_1
P49/TIOB0_0/SOT3_2/SEG31/MAD03_1
P4A/TIOB1_0/SCK3_2/SEG30/MAD04_1
P4B/TIOB2_0/SEG29/MAD05_1
P4C/TIOB3_0/SCK7_1/CEC0/MAD06_1
P4D/TIOB4_0/SOT7_1/MAD07_1
P4E/TIOB5_0/INT06_2/SIN7_1/MAD08_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 80
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
11
D a t a S h e e t
 FPT-64P-M38/M39
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1
P61/SOT5_0/TIOB2_2/UHCONX/SEG00
P62/SCK5_0/ADTG_3/SEG01
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P50/INT00_0/SIN3_1/VV4
2
47
P22/AN17/SOT0_0/TIOB7_1/SEG12
P51/INT01_0/SOT3_1
3
46
P23/AN16/SCK0_0/TIOA7_1/SEG13
P52/INT02_0/SCK3_1
4
45
P19/AN09/SCK2_2/SEG19
P30/TIOB0_1/INT03_2/COM7
5
44
P18/AN08/SOT2_2/SEG20
P31/TIOB1_1/SCK6_1/INT04_2/COM6
6
43
AVSS
P32/TIOB2_1/SOT6_1/INT05_2/COM5
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4
8
41
AVCC
P39/ADTG_2/COM3
9
40
P17/AN07/SIN2_2/INT04_1/SEG21
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
10
39
P15/AN05/SEG23
P3B/TIOA1_1/COM1
11
38
P14/AN04/INT03_1/SEG24
P3C/TIOA2_1/COM0
12
37
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25
P3D/TIOA3_1/SEG37
13
36
P12/AN02/SOT1_1/SEG26
P3E/TIOA4_1/SEG36
14
35
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27
P3F/TIOA5_1/SEG35
15
34
P10/AN00/SEG28
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/SEG31
P4A/TIOB1_0/SEG30
P4B/TIOB2_0/SEG29
P4C/TIOB3_0/SCK7_1/CEC0
P4D/TIOB4_0/SOT7_1
P4E/TIOB5_0/INT06_2/SIN7_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
LQFP - 64
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
12
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 LCC-64P-M24
VSS
P81/UDP0
P80/UDM0
VCC
P60/SIN5_0/TIOA2_2/INT15_1/WKUP3/CEC1
P61/SOT5_0/TIOB2_2/UHCONX/SEG00
P62/SCK5_0/ADTG_3/SEG01
P0F/NMIX/CROUT_1/RTCCO_0/SUBOUT_0/WKUP0
P0C/SCK4_0/TIOA6_1
P0B/SOT4_0/TIOB6_1
P0A/SIN4_0/INT00_2
P04/TDO/SWO
P03/TMS/SWDIO
P02/TDI
P01/TCK/SWCLK
P00/TRSTX
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
(TOP VIEW)
VCC
1
48
P21/AN18/SIN0_0/INT06_1/WKUP2/SEG11
P50/INT00_0/SIN3_1/VV4
2
47
P22/AN17/SOT0_0/TIOB7_1/SEG12
P51/INT01_0/SOT3_1
3
46
P23/AN16/SCK0_0/TIOA7_1/SEG13
P52/INT02_0/SCK3_1
4
45
P19/AN09/SCK2_2/SEG19
P30/TIOB0_1/INT03_2/COM7
5
44
P18/AN08/SOT2_2/SEG20
P31/TIOB1_1/SCK6_1/INT04_2/COM6
6
43
AVSS
P32/TIOB2_1/SOT6_1/INT05_2/COM5
7
42
AVRH
P33/INT04_0/TIOB3_1/SIN6_1/ADTG_6/COM4
8
41
AVCC
P39/ADTG_2/COM3
9
40
P17/AN07/SIN2_2/INT04_1/SEG21
P3A/TIOA0_1/RTCCO_2/SUBOUT_2/COM2
10
39
P15/AN05/SEG23
P3B/TIOA1_1/COM1
11
38
P14/AN04/INT03_1/SEG24
P3C/TIOA2_1/COM0
12
37
P13/AN03/SCK1_1/RTCCO_1/SUBOUT_1/SEG25
P3D/TIOA3_1/SEG37
13
36
P12/AN02/SOT1_1/SEG26
P3E/TIOA4_1/SEG36
14
35
P11/AN01/SIN1_1/INT02_1/WKUP1/SEG27
P3F/TIOA5_1/SEG35
15
34
P10/AN00/SEG28
VSS
16
33
VCC
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C
VCC
P46/X0A
P47/X1A
INITX
P49/TIOB0_0/SEG31
P4A/TIOB1_0/SEG30
P4B/TIOB2_0/SEG29
P4C/TIOB3_0/SCK7_1/CEC0
P4D/TIOB4_0/SOT7_1
P4E/TIOB5_0/INT06_2/SIN7_1
PE0/MD1
MD0
PE2/X0
PE3/X1
VSS
QFN - 64
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
13
D a t a S h e e t
 BGA-112P-M04
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
VSS
UDP0
UDM0
VCC
P0E
P0B
AN22
TMS/
SWDIO
TRSTX
VCC
VSS
B
VCC
VSS
P52
P61
P0F
P0C
AN23
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
P50
P51
VSS
P60
P62
P0D
P09
AN20
VSS
AN19
AN18
D
P53
P54
P55
VSS
P56
P63
P0A
VSS
AN21
AN16
AN15
E
P30
P31
P32
P33
Index
AN17
AN14
AN12
AN11
F
P34
P35
P36
P39
AN13
AN10
AN09
AVRH
G
P37
P38
P3A
P3D
AN08
AN07
AN06
AVSS
H
P3B
P3C
P3E
VSS
P44
P4C
AN05
VSS
AN04
AN03
AVCC
J
VCC
P3F
VSS
P40
P43
P49
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P42
P48
P4B
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P41
P45
P4A
MD0
X0
X1
VSS
PFBGA - 112
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
14
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 BGA-96P-M07
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
A
VSS
UDP0
UDM0
VCC
VSS
P0F
VSS
AN22
TMS/
SWDIO
TRSTX
VSS
B
VCC
VSS
P52
P61
P63
P0D
P0C
TDO/
SWO
TCK/
SWCLK
VSS
TDI
C
P50
P51
VSS
P60
P62
P0E
P0B
P0A
VSS
AN19
AN18
D
P53
P54
P55
Index
AN17
AN16
VSS
E
P56
P30
P31
AN11
AN10
AN09
F
VSS
VSS
VSS
AN08
AN07
AVRH
G
P32
P33
P39
AN06
AN05
AVSS
H
P3A
P3B
P3C
AN04
AN03
AVCC
J
P3D
P3E
VSS
P3F
P48
P4A
P4D
AN02
VSS
AN01
AN00
K
VCC
VSS
X1A
INITX
P45
P49
P4C
P4E
MD1
VSS
VCC
L
VSS
C
X0A
VSS
P44
VSS
P4B
MD0
X0
X1
VSS
PFBGA - 96
<Note>
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
15
D a t a S h e e t
 List of Pin Functions
 List of Pin Numbers
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
1
79
B1
1
B1
1
2
80
C1
2
C1
2
-
3
81
C2
3
C2
-
-
-
-
-
-
3
4
82
B3
4
B3
-
-
-
-
-
-
4
5
83
D1
5
D1
-
6
84
D2
6
D2
-
16
CONFIDENTIAL
Pin Name
VCC
P50
INT00_0
SIN3_1
VV4
MADATA00_1
P51
INT01_0
SOT3_1
(SDA3_1)
VV3
MADATA01_1
P51
INT01_0
SOT3_1
(SDA3_1)
P52
INT02_0
SCK3_1
(SCL3_1)
VV2
MADATA02_1
P52
INT02_0
SCK3_1
(SCL3_1)
P53
SIN6_0
TIOA1_2
INT07_2
VV1
MADATA03_1
P54
SOT6_0
(SDA6_0)
TIOB1_2
VV0
MADATA04_1
I/O
Circuit
Type
Pin State
Type
-
J
Y
J
Y
E
L
J
Y
E
L
J
Y
J
X
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
7
85
D3
7
D3
-
8
86
D5
8
E1
-
9
87
E1
9
E2
5
-
10
88
E2
10
E3
6
-
11
89
E3
11
G1
7
-
12
90
E4
12
G2
8
13
91
F1
-
-
-
14
92
F2
-
-
-
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Pin Name
P55
SCK6_0
(SCL6_0)
ADTG_1
SEG39
MADATA05_1
P56
INT08_2
SEG38
MADATA06_1
P30
TIOB0_1
INT03_2
COM7
MADATA07_1
P31
TIOB1_1
SCK6_1
(SCL6_1)
INT04_2
COM6
MADATA08_1
P32
TIOB2_1
SOT6_1
(SDA6_1)
INT05_2
COM5
MADATA09_1
P33
INT04_0
TIOB3_1
SIN6_1
ADTG_6
COM4
MADATA10_1
P34
TIOB4_1
MADATA11_1
P35
TIOB5_1
INT08_1
MADATA12_1
I/O
Circuit
Type
Pin State
Type
K
U
K
V
K
V
K
V
K
V
K
V
E
K
E
L
17
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
15
93
F3
-
-
-
-
-
-
-
F1
F2
F3
-
16
94
G1
-
-
-
17
95
G2
-
-
-
18
96
F4
13
G3
9
19
97
G3
14
H1
10
20
98
H1
15
H2
11
21
99
H2
16
H3
12
22
100
G4
17
J1
13
-
-
B2
-
B2
-
23
1
H3
18
J2
14
24
2
J2
19
J4
15
25
26
3
4
L1
J1
20
-
L1
-
16
-
18
CONFIDENTIAL
Pin Name
P36
SIN5_2
INT09_1
MADATA13_1
VSS
VSS
VSS
P37
SOT5_2
(SDA5_2)
INT10_1
MADATA14_1
P38
SCK5_2
(SCL5_2)
INT11_1
MADATA15_1
P39
ADTG_2
COM3
P3A
TIOA0_1
RTCCO_2
SUBOUT_2
COM2
P3B
TIOA1_1
COM1
P3C
TIOA2_1
COM0
P3D
TIOA3_1
SEG37
VSS
P3E
TIOA4_1
SEG36
P3F
TIOA5_1
SEG35
VSS
VCC
I/O
Circuit
Type
Pin State
Type
E
L
-
E
L
E
L
K
U
K
U
K
U
K
U
K
U
-
K
U
K
U
-
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
27
5
J4
-
-
-
28
6
L5
-
-
-
29
7
K5
-
-
-
30
8
J5
-
-
-
31
9
H5
21
L5
-
32
10
L6
22
K5
-
33
34
35
11
12
13
K2
J3
H4
L2
L4
K1
23
24
25
K2
J3
L6
L2
L4
K1
17
18
36
14
L3
26
L3
19
37
15
K3
27
K3
20
38
16
K4
28
K4
21
39
17
K6
29
J5
-
22
40
18
J6
30
K6
-
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Pin Name
P40
TIOA0_0
INT12_1
P41
TIOA1_0
INT13_1
P42
TIOA2_0
P43
TIOA3_0
ADTG_7
P44
TIOA4_0
SEG34
MAD00_1
P45
TIOA5_0
SEG33
MAD01_1
VSS
VSS
VSS
VSS
C
VSS
VCC
P46
X0A
P47
X1A
INITX
P48
INT14_1
SIN3_2
SEG32
MAD02_1
P49
TIOB0_0
SEG31
SOT3_2
(SDA3_2)
MAD03_1
I/O Circuit Pin State
Type
Type
E
L
E
L
E
K
E
K
K
U
K
U
-
D
F
D
G
B
C
K
V
K
U
19
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
23
41
19
L7
31
J6
-
42
20
K7
32
L7
24
-
43
21
H6
33
K7
25
-
44
22
J7
34
J7
26
-
45
23
K8
35
K8
27
46
24
K9
36
K9
28
47
25
L8
37
L8
29
48
26
L9
38
L9
30
49
27
L10
39
L10
31
50
51
28
29
L11
K11
40
41
L11
K11
32
33
52
30
J11
42
J11
34
53
31
J10
43
J10
35
-
20
CONFIDENTIAL
Pin Name
P4A
TIOB1_0
SEG30
SCK3_2
(SCL3_2)
MAD04_1
P4B
TIOB2_0
SEG29
MAD05_1
P4C
TIOB3_0
SCK7_1
(SCL7_1)
CEC0
MAD06_1
P4D
TIOB4_0
SOT7_1
(SDA7_1)
MAD07_1
P4E
TIOB5_0
INT06_2
SIN7_1
MAD08_1
MD1
PE0
MD0
X0
PE2
X1
PE3
VSS
VCC
P10
AN00
SEG28
P11
AN01
SIN1_1
INT02_1
WKUP1
SEG27
MAD09_1
I/O Circuit Pin State
Type
Type
K
U
K
U
I*
S
I*
K
I*
L
C
E
G
D
A
A
A
B
-
L
W
L
R
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
54
32
J8
44
J8
-
-
K10
J9
-
K10
J9
55
33
H10
45
H10
36
-
37
-
38
56
34
H9
46
H9
-
39
57
35
H7
47
G10
-
58
36
G10
48
G9
59
37
G9
49
F10
60
61
62
38
39
40
H11
F11
G11
50
51
52
H11
F11
G11
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
-
40
41
42
43
Pin Name
P12
AN02
SOT1_1
(SDA1_1)
SEG26
MAD10_1
VSS
VSS
P13
AN03
SCK1_1
(SCL1_1)
RTCCO_1
SEG25
SUBOUT_1
MAD11_1
P14
AN04
INT03_1
SEG24
SIN0_1
MAD12_1
P15
AN05
SEG23
SOT0_1
(SDA0_1)
MAD13_1
P16
AN06
SCK0_1
(SCL0_1)
SEG22
MAD14_1
P17
AN07
SIN2_2
INT04_1
SEG21
MAD15_1
AVCC
AVRH
AVSS
I/O Circuit Pin State
Type
Type
L
W
-
L
W
L
N
L
W
L
W
L
N
-
21
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
63
41
G8
53
F9
44
-
45
64
42
F10
54
E11
-
-
H8
-
-
-
65
43
F9
55
E10
-
66
44
E11
56
E9
-
67
45
E10
-
-
-
68
46
F8
-
-
-
69
47
E9
-
-
-
70
48
D11
-
-
-
22
CONFIDENTIAL
Pin Name
P18
AN08
SOT2_2
(SDA2_2)
SEG20
MAD16_1
P19
AN09
SCK2_2
(SCL2_2)
SEG19
MAD17_1
VSS
P1A
AN10
SIN4_1
INT05_1
SEG18
MAD18_1
P1B
AN11
SOT4_1
(SDA4_1)
SEG17
MAD19_1
P1C
AN12
SCK4_1
(SCL4_1)
SEG16
MAD20_1
P1D
AN13
CTS4_1
SEG15
MAD21_1
P1E
AN14
RTS4_1
SEG14
MAD22_1
P1F
AN15
ADTG_5
MAD23_1
I/O Circuit pin state
Type
type
L
W
L
W
-
L
N
L
W
L
W
L
W
L
W
F
M
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
B10
B10
C9
C9
D11
-
71
49
D10
57
D10
46
72
50
E8
58
D9
47
73
51
C11
59
C11
48
74
52
C10
60
C10
-
75
76
53
54
A11
A10
-
A11
-
-
77
55
A9
61
A10
49
-
78
56
B9
62
B9
79
57
B11
63
B11
50
51
-
80
58
A8
64
A9
52
81
59
B8
65
B8
53
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Pin Name
VSS
VSS
VSS
P23
AN16
SCK0_0
(SCL0_0)
TIOA7_1
SEG13
P22
AN17
SOT0_0
(SDA0_0)
TIOB7_1
SEG12
P21
AN18
SIN0_0
INT06_1
WKUP2
SEG11
P20
AN19
INT05_0
CROUT_0
SEG10
MAD24_1
VSS
VCC
P00
TRSTX
MCSX7_1
P01
TCK
SWCLK
P02
TDI
MCSX6_1
P03
TMS
SWDIO
P04
TDO
SWO
I/O Circuit Pin State
Type
Type
-
L
W
L
W
L
R
L
N
E
J
E
J
E
J
E
J
E
J
23
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
82
60
C8
-
-
-
-
-
D8
-
-
-
83
61
D9
-
-
-
66
A8
84
62
A7
-
-
-
-
-
-
-
A7
-
85
63
B7
-
-
-
86
64
C7
-
-
-
87
65
D7
67
C8
54
-
24
CONFIDENTIAL
Pin Name
P05
AN20
TRACED0
TIOA5_2
SIN4_2
INT00_1
SEG09
MCSX5_1
VSS
P06
AN21
TRACED1
TIOB5_2
SOT4_2
(SDA4_2)
INT01_1
SEG08
MCSX4_1
P07
AN22
ADTG_0
SEG07
MCLKOUT_1
TRACED2
SCK4_2
(SCL4_2)
VSS
P08
AN23
TRACED3
TIOA0_2
CTS4_2
SEG06
MCSX3_1
P09
TRACECLK
TIOB0_2
RTS4_2
SEG05
MCSX2_1
P0A
SIN4_0
INT00_2
MCSX1_1
I/O Circuit Pin State
Type
Type
L
Q
-
L
Q
L
P
-
L
P
K
O
I*
L
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
88
66
A6
68
C7
55
-
56
89
67
B6
69
B7
-
-
D4
C3
-
C3
-
90
68
C6
70
B6
-
91
69
A5
71
C6
-
-
-
-
-
A5
-
92
70
B5
72
A6
57
93
71
D6
73
B5
-
94
72
C5
74
C5
58
-
95
73
B4
75
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
B4
59
Pin Name
P0B
SOT4_0
(SDA4_0)
TIOB6_1
MCSX0_1
P0C
SCK4_0
(SCL4_0)
TIOA6_1
MALE_1
VSS
VSS
P0D
RTS4_0
TIOA3_2
SEG04
MDQM0_1
P0E
CTS4_0
TIOB3_2
SEG03
MDQM1_1
VSS
P0F
NMIX
CROUT_1
RTCCO_0
SUBOUT_0
WKUP0
P63
INT03_0
SEG02
MWEX_1
P62
SCK5_0
(SCL5_0)
ADTG_3
SEG01
MOEX_1
P61
SOT5_0
(SDA5_0)
TIOB2_2
UHCONX
SEG00
I/O Circuit Pin State
Type
Type
I*
K
I*
K
-
K
U
K
U
-
E
I
K
V
K
U
K
U
25
D a t a S h e e t
Pin No
LQFP-64
LQFP-100 QFP-100 BGA-112 LQFP-80 BGA-96
QFN-64
96
74
C4
76
C4
60
97
75
A4
77
A4
61
98
76
A3
78
A3
62
99
77
A2
79
A2
63
100
78
*: 5 V tolerant I/O
A1
80
A1
64
26
CONFIDENTIAL
Pin Name
P60
SIN5_0
TIOA2_2
INT15_1
WKUP3
CEC1
MRDY_1
VCC
P80
UDM0
P81
UDP0
VSS
I/O Circuit Pin State
Type
Type
I*
T
H
H
H
H
-
-
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 List of Pin Functions
The number after the underscore ("_") in pin names such as XXX_1 and XXX_2 indicates the relocated
port number. For these pins, there are multiple pins that provide the same function for the same channel.
Use the extended port function register (EPFR) to select the pin.
Pin No
Pin
Pin Name
Function
ADC
ADTG_0
ADTG_1
ADTG_2
ADTG_3
ADTG_4
ADTG_5
ADTG_6
ADTG_7
ADTG_8
AN00
AN01
AN02
AN03
AN04
AN05
AN06
AN07
AN08
AN09
AN10
AN11
AN12
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN21
AN22
AN23
Function Description
A/D converter external trigger
input pin
A/D converter analog input pin.
ANxx describes ADC ch.xx.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
LQFP- QFP100
100
84
7
18
94
70
12
30
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
71
72
73
74
82
83
84
85
62
85
96
72
48
90
8
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
49
50
51
52
60
61
62
63
BGA- LQFP- BGA112
80
96
A7
D3
F4
C5
D11
E4
J5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
D10
E8
C11
C10
C8
D9
A7
B7
66
7
13
74
12
42
43
44
45
46
47
48
49
53
54
55
56
57
58
59
60
66
-
A8
D3
G3
C5
G2
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
D10
D9
C11
C10
A8
-
LQFP/
QFN64
9
58
8
34
35
36
37
38
39
40
44
45
46
47
48
-
27
D a t a S h e e t
Pin No
Pin
Pin Name
Function
Base
Timer
0
Base
Timer
1
Base
Timer
2
Base
Timer
3
Base
Timer
4
Base
Timer
5
Base
Timer
6
Base
Timer
7
28
CONFIDENTIAL
TIOA0_0
TIOA0_1
TIOA0_2
TIOB0_0
TIOB0_1
TIOB0_2
TIOA1_0
TIOA1_1
TIOA1_2
TIOB1_0
TIOB1_1
TIOB1_2
TIOA2_0
TIOA2_1
TIOA2_2
TIOB2_0
TIOB2_1
TIOB2_2
TIOA3_0
TIOA3_1
TIOA3_2
TIOB3_0
TIOB3_1
TIOB3_2
TIOA4_0
TIOA4_1
TIOA4_2
TIOB4_0
TIOB4_1
TIOB4_2
TIOA5_0
TIOA5_1
TIOA5_2
TIOB5_0
TIOB5_1
TIOB5_2
Function Description
Base timer ch.0 TIOA pin
Base timer ch.0 TIOB pin
Base timer ch.1 TIOA pin
Base timer ch.1 TIOB pin
Base timer ch.2 TIOA pin
Base timer ch.2 TIOB pin
Base timer ch.3 TIOA pin
Base timer ch.3 TIOB pin
Base timer ch.4 TIOA pin
Base timer ch.4 TIOB pin
Base timer ch.5 TIOA pin
Base timer ch.5 TIOB pin
27
19
85
40
9
86
28
20
5
41
10
6
29
21
96
42
11
95
30
22
90
43
12
91
31
23
44
13
32
24
82
45
14
83
5
97
63
18
87
64
6
98
83
19
88
84
7
99
74
20
89
73
8
100
68
21
90
69
9
1
22
91
10
2
60
23
92
61
J4
G3
B7
J6
E1
C7
L5
H1
D1
L7
E2
D2
K5
H2
C4
K7
E3
B4
J5
G4
C6
H6
E4
A5
H5
H3
J7
F1
L6
J2
C8
K8
F2
D9
14
30
9
15
5
31
10
6
16
76
32
11
75
17
70
33
12
71
21
18
34
22
19
35
-
H1
K6
E2
H2
D1
J6
E3
D2
H3
C4
L7
G1
B4
J1
B6
K7
G2
C6
L5
J2
J7
K5
J4
K8
-
LQFP/
QFN64
10
22
5
11
23
6
12
60
24
7
59
13
25
8
14
26
15
27
-
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
TIOA6_1
Base timer ch.6 TIOA pin
89
67
B6
69
B7
56
TIOB6_1
Base timer ch.6 TIOB pin
88
66
A6
68
C7
55
71
72
-
49
50
-
D10
E8
-
57
58
-
D10
D9
-
46
47
-
TIOA7_0
TIOA7_1
TIOA7_2
TIOB7_0
TIOB7_1
TIOB7_2
Base timer ch.7 TIOA pin
Base timer ch.7 TIOB pin
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
Debugger
External
Bus
Pin Name
Function Description
Serial wire debug interface
clock input pin
Serial wire debug interface
SWDIO
data input / output pin
SWO
Serial wire viewer output pin
TCK
J-TAG test clock input pin
TDI
J-TAG test data input pin
TDO
J-TAG debug data output pin
J-TAG test mode state
TMS
input/output pin
TRACECLK Trace CLK output pin of ETM
TRACED0
TRACED1
Trace data output pins of ETM
TRACED2
TRACED3
TRSTX
J-TAG test reset Input pin
MAD00_1
MAD01_1
MAD02_1
MAD03_1
MAD04_1
MAD05_1
MAD06_1
MAD07_1
MAD08_1
MAD09_1
MAD10_1
MAD11_1
External bus interface address
MAD12_1
bus
MAD13_1
MAD14_1
MAD15_1
MAD16_1
MAD17_1
MAD18_1
MAD19_1
MAD20_1
MAD21_1
MAD22_1
MAD23_1
MAD24_1
SWCLK
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
LQFP/
QFN64
78
56
B9
62
B9
50
80
58
A8
64
A9
52
81
78
79
81
59
56
57
59
B8
B9
B11
B8
65
62
63
65
B8
B9
B11
B8
53
50
51
53
80
58
A8
64
A9
52
86
82
83
84
85
77
31
32
39
40
41
42
43
44
45
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
64
60
61
62
63
55
9
10
17
18
19
20
21
22
23
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
C7
C8
D9
A7
B7
A9
H5
L6
K6
J6
L7
K7
H6
J7
K8
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
61
21
22
29
30
31
32
33
34
35
43
44
45
46
47
48
49
53
54
55
56
60
A10
L5
K5
J5
K6
J6
L7
K7
J7
K8
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
C10
49
-
29
D a t a S h e e t
Pin No
Pin
Function
External
Bus
Pin Name
MCSX0_1
MCSX1_1
MCSX2_1
MCSX3_1
MCSX4_1
MCSX5_1
MCSX6_1
MCSX7_1
MDQM0_1
MDQM1_1
MOEX_1
MWEX_1
Function Description
External bus interface chip
select output pin
External bus interface byte
mask signal output pin
External bus interface read
enable signal for SRAM
External bus interface write
enable signal for SRAM
MADATA00_1
MADATA01_1
MADATA02_1
MADATA03_1
MADATA04_1
MADATA05_1
MADATA06_1
MADATA07_1
External bus interface data bus
MADATA08_1
MADATA09_1
MADATA10_1
MADATA11_1
MADATA12_1
MADATA13_1
MADATA14_1
MADATA15_1
Address Latch enable signal
MALE_1
for multiplex
External bus RDY input
MRDY_1
signal
MCLKOUT_1 External bus clock output pin
30
CONFIDENTIAL
88
87
86
85
83
82
79
77
90
91
66
65
64
63
61
60
57
55
68
69
A6
D7
C7
B7
D9
C8
B11
A9
C6
A5
68
67
63
61
70
71
C7
C8
B11
A10
B6
C6
LQFP/
QFN64
-
94
72
C5
74
C5
-
93
71
D6
73
B5
-
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
C1
C2
B3
D1
D2
D3
D5
E1
E2
E3
E4
F1
F2
F3
G1
G2
2
3
4
5
6
7
8
9
10
11
12
-
C1
C2
B3
D1
D2
D3
E1
E2
E3
G1
G2
-
-
89
67
B6
69
B7
-
96
74
C4
76
C4
-
84
62
A7
66
A8
-
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
External
Interrupt
Pin Name
INT00_0
INT00_1
INT00_2
INT01_0
INT01_1
INT02_0
INT02_1
INT03_0
INT03_1
INT03_2
INT04_0
INT04_1
INT04_2
INT05_0
INT05_1
INT05_2
INT06_1
INT06_2
INT07_2
INT08_1
INT08_2
INT09_1
INT10_1
INT11_1
INT12_1
INT13_1
INT14_1
INT15_1
NMIX
Function Description
External interrupt request 00
input pin
External interrupt request 01
input pin
External interrupt request 02
input pin
External interrupt request 03
input pin
External interrupt request 04
input pin
External interrupt request 05
input pin
External interrupt request 06
input pin
External interrupt request 07
input pin
External interrupt request 08
input pin
External interrupt request 09
input pin
External interrupt request 10
input pin
External interrupt request 11
input pin
External interrupt request 12
input pin
External interrupt request 13
input pin
External interrupt request 14
input pin
External interrupt request 15
input pin
Non-Maskable Interrupt input
pin
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
2
82
87
3
83
4
53
93
56
9
12
59
10
74
65
11
73
45
80
60
65
81
61
82
31
71
34
87
90
37
88
52
43
89
51
23
C1
C8
D7
C2
D9
B3
J10
D6
H9
E1
E4
G9
E2
C10
F9
E3
C11
K8
2
67
3
4
43
73
46
9
12
49
10
60
55
11
59
35
C1
C8
C2
B3
J10
B5
H9
E2
G2
F10
E3
C10
E10
G1
C11
K8
LQFP/
QFN64
2
54
3
4
35
38
5
8
40
6
7
48
27
5
83
D1
5
D1
-
14
8
92
86
F2
D5
8
E1
-
15
93
F3
-
-
-
16
94
G1
-
-
-
17
95
G2
-
-
-
27
5
J4
-
-
-
28
6
L5
-
-
-
39
17
K6
29
J5
-
96
74
C4
76
C4
60
92
70
B5
72
A6
57
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
31
D a t a S h e e t
Pin No
Pin
Function
GPIO
32
CONFIDENTIAL
Pin Name
P00
P01
P02
P03
P04
P05
P06
P07
P08
P09
P0A
P0B
P0C
P0D
P0E
P0F
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P1A
P1B
P1C
P1D
P1E
P1F
P20
P21
P22
P23
Function Description
General-purpose I/O port 0
General-purpose I/O port 1
General-purpose I/O port 2
LQFP- QFP100
100
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
52
53
54
55
56
57
58
59
63
64
65
66
67
68
69
70
74
73
72
71
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
30
31
32
33
34
35
36
37
41
42
43
44
45
46
47
48
52
51
50
49
BGA- LQFP- BGA112
80
96
A9
B9
B11
A8
B8
C8
D9
A7
B7
C7
D7
A6
B6
C6
A5
B5
J11
J10
J8
H10
H9
H7
G10
G9
G8
F10
F9
E11
E10
F8
E9
D11
C10
C11
E8
D10
61
62
63
64
65
66
67
68
69
70
71
72
42
43
44
45
46
47
48
49
53
54
55
56
60
59
58
57
A10
B9
B11
A9
B8
A8
C8
C7
B7
B6
C6
A6
J11
J10
J8
H10
H9
G10
G9
F10
F9
E11
E10
E9
C10
C11
D9
D10
LQFP/
QFN64
49
50
51
52
53
54
55
56
57
34
35
36
37
38
39
40
44
45
48
47
46
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
GPIO
Pin Name
P30
P31
P32
P33
P34
P35
P36
P37
P38
P39
P3A
P3B
P3C
P3D
P3E
P3F
P40
P41
P42
P43
P44
P45
P46
P47
P48
P49
P4A
P4B
P4C
P4D
P4E
P50
P51
P52
P53
P54
P55
P56
P60
P61
P62
P63
P80
P81
PE0
PE2
PE3
Function Description
General-purpose I/O port 3
General-purpose I/O port 4
General-purpose I/O port 5
General-purpose I/O port 6
General-purpose I/O port 8
General-purpose I/O port E
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
LQFP- QFP100
100
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
27
28
29
30
31
32
36
37
39
40
41
42
43
44
45
2
3
4
5
6
7
8
96
95
94
93
98
99
46
48
49
87
88
89
90
91
92
93
94
95
96
97
98
99
100
1
2
5
6
7
8
9
10
14
15
17
18
19
20
21
22
23
80
81
82
83
84
85
86
74
73
72
71
76
77
24
26
27
BGA- LQFP- BGA112
80
96
E1
E2
E3
E4
F1
F2
F3
G1
G2
F4
G3
H1
H2
G4
H3
J2
J4
L5
K5
J5
H5
L6
L3
K3
K6
J6
L7
K7
H6
J7
K8
C1
C2
B3
D1
D2
D3
D5
C4
B4
C5
D6
A3
A2
K9
L9
L10
9
10
11
12
13
14
15
16
17
18
19
21
22
26
27
29
30
31
32
33
34
35
2
3
4
5
6
7
8
76
75
74
73
78
79
36
38
39
E2
E3
G1
G2
G3
H1
H2
H3
J1
J2
J4
L5
K5
L3
K3
J5
K6
J6
L7
K7
J7
K8
C1
C2
B3
D1
D2
D3
E1
C4
B4
C5
B5
A3
A2
K9
L9
L10
LQFP/
QFN64
5
6
7
8
9
10
11
12
13
14
15
19
20
22
23
24
25
26
27
2
3
4
60
59
58
62
63
28
30
31
33
D a t a S h e e t
Pin No
Pin
Function
Multifunction
Serial
0
Pin Name
Function Description
SIN0_0
SIN0_1
Multi-function serial interface
ch.0 input pin
Multi-function serial interface
ch.0 output pin.
This pin operates as SOT0
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA0
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.0 clock I/O pin.
This pin operates as SCK0
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL0
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.1 input pin
Multi-function serial interface
ch.1 output pin.
This pin operates as SOT1
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA1
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.1 clock I/O pin.
This pin operates as SCK1
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL1
when it is used in an I2C
(operation mode 4).
SOT0_0
(SDA0_0)
SOT0_1
(SDA0_1)
SCK0_0
(SCL0_0)
SCK0_1
(SCL0_1)
Multifunction
Serial
1
SIN1_1
SOT1_1
(SDA1_1)
SCK1_1
(SCL1_1)
34
CONFIDENTIAL
73
56
51
34
C11
H9
59
46
C11
H9
LQFP/
QFN64
48
-
72
50
E8
58
D9
47
57
35
H7
47
G10
-
71
49
D10
57
D10
46
58
36
G10
48
G9
-
53
31
J10
43
J10
35
54
32
J8
44
J8
36
55
33
H10
45
H10
37
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
Multifunction
Serial
2
Pin Name
SIN2_2
SOT2_2
(SDA2_2)
SCK2_2
(SCL2_2)
Multifunction
Serial
3
SIN3_1
SIN3_2
SOT3_1
(SDA3_1)
SOT3_2
(SDA3_2)
SCK3_1
(SCL3_1)
SCK3_2
(SCL3_2)
Function Description
Multi-function serial interface
ch.2 input pin
Multi-function serial interface
ch.2 output pin.
This pin operates as SOT2
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA2
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.2 clock I/O pin.
This pin operates as SCK2
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL2
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.3 input pin
Multi-function serial interface
ch.3 output pin.
This pin operates as SOT3
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA3
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.3 clock I/O pin.
This pin operates as SCK3
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL3
when it is used in an I2C
(operation mode 4).
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
LQFP/
QFN64
59
37
G9
49
F10
40
63
41
G8
53
F9
44
64
42
F10
54
E11
45
2
39
80
17
C1
K6
2
29
C1
J5
2
-
3
81
C2
3
C2
3
40
18
J6
30
K6
-
4
82
B3
4
B3
4
41
19
L7
31
J6
-
35
D a t a S h e e t
Pin No
Pin
Function
Pin Name
Function Description
Multifunction
Serial
4
SIN4_0
SIN4_1
SIN4_2
Multi-function serial interface
ch.4 input pin
SOT4_0
(SDA4_0)
SOT4_1
(SDA4_1)
SOT4_2
(SDA4_2)
SCK4_0
(SCL4_0)
SCK4_1
(SCL4_1)
SCK4_2
(SCL4_2)
Multifunction
Serial
5
RTS4_0
RTS4_1
RTS4_2
CTS4_0
CTS4_1
CTS4_2
SIN5_0
SIN5_2
SOT5_0
(SDA5_0)
SOT5_2
(SDA5_2)
SCK5_0
(SCL5_0)
SCK5_2
(SCL5_2)
36
CONFIDENTIAL
Multi-function serial interface
ch.4 output pin.
This pin operates as SOT4
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA4
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.4 clock I/O pin.
This pin operates as SCK4
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL4
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.4 RTS output pin
Multi-function serial interface
ch.4 CTS input pin
Multi-function serial interface
ch.5 input pin
Multi-function serial interface
ch.5 output pin.
This pin operates as SOT5
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA5
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.5 clock I/O pin.
This pin operates as SCK5
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL5
when it is used in an I2C
(operation mode 4).
87
65
82
65
43
60
D7
F9
C8
67
55
-
C8
E10
-
LQFP/
QFN64
54
-
88
66
A6
68
C7
55
66
44
E11
56
E9
-
83
61
D9
-
-
-
89
67
B6
69
B7
56
67
45
E10
-
-
-
84
62
A7
-
-
-
90
69
86
91
68
85
96
15
68
47
64
69
46
63
74
93
C6
E9
C7
A5
F8
B7
C4
F3
70
71
76
-
B6
C6
C4
-
60
-
95
73
B4
75
B4
59
16
94
G1
-
-
-
94
72
C5
74
C5
58
17
95
G2
-
-
-
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
Multifunction
Serial
6
Pin Name
Function Description
SIN6_0
SIN6_1
Multi-function serial interface
ch.6 input pin
Multi-function serial interface
ch.6 output pin.
This pin operates as SOT6
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA6
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.6 clock I/O pin.
This pin operates as SCK6
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL6
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.7 input pin
Multi-function serial interface
ch.7 output pin.
This pin operates as SOT7
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SDA7
when it is used in an I2C
(operation mode 4).
Multi-function serial interface
ch.7 clock I/O pin.
This pin operates as SCK7
when it is used in a
UART/CSIO (operation
modes 0 to 2) and as SCL7
when it is used in an I2C
(operation mode 4).
SOT6_0
(SDA6_0)
SOT6_1
(SDA6_1)
SCK6_0
(SCL6_0)
SCK6_1
(SCL6_1)
Multifunction
Serial
7
SIN7_1
SOT7_1
(SDA7_1)
SCK7_1
(SCL7_1)
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
5
12
83
90
D1
E4
5
12
D1
G2
LQFP/
QFN64
8
6
84
D2
6
D2
-
11
89
E3
11
G1
7
7
85
D3
7
D3
-
10
88
E2
10
E3
6
45
23
K8
35
K8
27
44
22
J7
34
J7
26
43
21
H6
33
K7
25
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
37
D a t a S h e e t
Pin No
Pin
Function
USB
98
99
76
77
A3
A2
78
79
A3
A2
LQFP/
QFN64
62
63
95
73
B4
75
B4
59
92
55
19
92
55
19
70
33
97
70
33
97
B5
H10
G3
B5
H10
G3
72
45
14
72
45
14
A6
H10
H1
A6
H10
H1
57
37
10
57
37
10
92
70
B5
72
A6
57
53
31
J10
43
J10
35
73
51
C11
59
C11
48
96
74
C4
76
C4
60
43
21
H6
33
K7
25
96
74
C4
76
C4
60
VV0
6
84
D2
6
D2
-
VV1
5
83
D1
5
D1
-
4
82
B3
4
B3
-
VV3
3
81
C2
3
C2
-
VV4
2
80
C1
2
C1
2
COM0
21
99
H2
16
H3
12
COM1
20
98
H1
15
H2
11
COM2
19
97
G3
14
H1
10
18
96
F4
13
G3
9
12
90
E4
12
G2
8
COM5
11
89
E3
11
G1
7
COM6
10
88
E2
10
E3
6
COM7
9
87
E1
9
E2
5
Pin Name
UDM0
UDP0
UHCONX
Real-time
clock
Low-Power
Consumption
Mode
RTCCO_0
RTCCO_1
RTCCO_2
SUBOUT_0
SUBOUT_1
SUBOUT_2
WKUP0
WKUP1
WKUP2
WKUP3
HDMICEC/
Remote
Control
Reception
LCDC
CEC0
CEC1
VV2
COM3
COM4
38
CONFIDENTIAL
Function Description
USB function/host D – pin
USB function/host D + pin
USB external pull-up control
pin
0.5 seconds pulse output pin
of Real-time clock
Sub clock output pin
Deep standby mode return
signal input pin 0
Deep standby mode return
signal input pin 1
Deep standby mode return
signal input pin 2
Deep standby mode return
signal input pin 3
HDMI-CEC/Remote Control
Reception ch.0 input/output
pin
HDMI-CEC/Remote Control
Reception ch.1 input/output
pin
LCD drive power supply pin
LCD common output pin
LQFP- QFP100
100
BGA- LQFP- BGA112
80
96
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
function
LCDC
Pin name
SEG00
SEG01
SEG02
SEG03
SEG04
SEG05
SEG06
SEG07
SEG08
SEG09
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
SEG24
SEG25
SEG26
SEG27
SEG28
SEG29
SEG30
SEG31
SEG32
SEG33
SEG34
SEG35
SEG36
SEG37
SEG38
SEG39
Function description
LCD segment output pin
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
LQFP- QFP100
100
95
94
93
91
90
86
85
84
83
82
74
73
72
71
69
68
67
66
65
64
63
59
58
57
56
55
54
53
52
42
41
40
39
32
31
24
23
22
8
7
73
72
71
69
68
64
63
62
61
60
52
51
50
49
47
46
45
44
43
42
41
37
36
35
34
33
32
31
30
20
19
18
17
10
9
2
1
100
86
85
BGA- LQFP- BGA112
80
96
B4
C5
D6
A5
C6
C7
B7
A7
D9
C8
C10
C11
E8
D10
E9
F8
E10
E11
F9
F10
G8
G9
G10
H7
H9
H10
J8
J10
J11
K7
L7
J6
K6
L6
H5
J2
H3
G4
D5
D3
75
74
73
71
70
66
60
59
58
57
56
55
54
53
49
48
47
46
45
44
43
42
32
31
30
29
22
21
19
18
17
8
7
B4
C5
B5
C6
B6
A8
C10
C11
D9
D10
E9
E10
E11
F9
F10
G9
G10
H9
H10
J8
J10
J11
L7
J6
K6
J5
K5
L5
J4
J2
J1
E1
D3
LQFP/
QFN64
59
58
48
47
46
45
44
40
39
38
37
36
35
34
24
23
22
15
14
13
-
39
D a t a S h e e t
Pin No
Pin
Function
Pin Name
Reset
INITX
Mode
MD0
MD1
Function Description
External Reset Input pin.
A reset is valid when
INITX=L.
Mode 0 pin.
During normal operation,
MD0=L must be input. During
serial programming to Flash
memory, MD0=H must be
input.
Mode 1 pin.
During serial programming to
Flash memory, MD1=L must
be input.
Power
VCC
Power supply Pin
VSS
GND Pin
GND
40
CONFIDENTIAL
LQFP100
LQFP/
QFP- BGA- LQFP- BGAQFN100
112
80
96
64
38
16
K4
28
K4
21
47
25
L8
37
L8
29
46
24
K9
36
K9
28
1
26
35
51
76
97
25
34
50
75
100
79
4
13
29
54
75
3
12
28
53
78
B1
J1
K1
K11
A10
A4
B2
L1
K2
J3
H4
L4
L11
K10
J9
H8
B10
C9
A11
D8
D4
C3
A1
1
25
41
77
20
24
40
80
B1
K1
K11
A4
F1
F2
F3
B2
L1
K2
J3
L6
L4
L11
K10
J9
B10
C9
D11
A11
A7
C3
A5
A1
1
18
33
61
16
32
64
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Pin No
Pin
Function
Clock
Pin Name
X0
X0A
X1
X1A
CROUT_0
CROUT_1
ADC
power
AVCC
AVRH
ADC
GND
C pin
AVSS
C
Function Description
Main clock (oscillation) input
pin
Sub clock (oscillation) input
pin
Main clock (oscillation) I/O
pin
Sub clock (oscillation) I/O pin
Built-in high-speed CR-osc
clock output port
A/D converter analog power
supply pin
A/D converter analog reference
voltage input pin
BGA- LQFP- BGA112
80
96
LQFP/
QFN64
48
26
L9
38
L9
30
36
14
L3
26
L3
19
49
27
L10
39
L10
31
37
74
92
15
52
70
K3
C10
B5
27
60
72
K3
C10
A6
20
57
60
38
H11
50
H11
41
61
39
F11
51
F11
42
A/D converter GND pin
62
40
G11
52
G11
43
Power supply stabilization
capacity pin
33
11
L2
23
L2
17
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
LQFP- QFP100
100
41
D a t a S h e e t
 I/O Circuit Type
Type
Circuit
Remarks
A
It is possible to select the main
oscillation / GPIO function
When the main oscillation is
selected.
 Oscillation feedback resistor
: Approximately 1 MΩ
 With Standby mode control
Pull-up
resistor
P-ch
P-ch
Digital output
X1
N-ch
Digital output
R
Pull-up resistor control
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis input
 With pull-up resistor control
 With standby mode control
 Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
Digital input
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0
Pull-up resistor control
 CMOS level hysteresis input
 Pull-up resistor
: Approximately 33 kΩ
B
Pull-up resistor
Digital input
42
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Type
Circuit
Remarks
C
Digital input
 Open drain output
 CMOS level hysteresis input
Digital output
N-ch
D
It is possible to select the sub
oscillation / GPIO function
Pull-up
resistor
P-ch
P-ch
Digital output
X1A
N-ch
Digital output
R
Pull-up resistor control
Digital input
When the sub oscillation is
selected.
 Oscillation feedback resistor
: Approximately 5 MΩ
 With Standby mode control
When the GPIO is selected.
 CMOS level output.
 CMOS level hysteresis input
 With pull-up resistor control
 With standby mode control
 Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
Standby mode control
Clock input
Feedback
resistor
Standby mode control
Digital input
Standby mode control
Pull-up
resistor
R
P-ch
P-ch
Digital output
N-ch
Digital output
X0A
Pull-up resistor control
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
43
D a t a S h e e t
Type
Circuit
Remarks





E
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
R
Pull-up resistor control
Digital input
Standby mode control







F
P-ch
P-ch
N-ch
R
CMOS level output
CMOS level hysteresis input
With input control
Analog input
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
G
CMOS level hysteresis input
Mode input
44
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Type
Circuit
Remarks
H
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
UDP output
UDP0/P81
USB Full-speed/Low-speed control
UDP input
Differential
It is possible to select the USB
I/O / GPIO function.
When the USB I/O is selected.
 Full-speed, Low-speed control
When the GPIO is selected.
 CMOS level output
 CMOS level hysteresis input
 With standby mode control
Differential input
USB/GPIO select
UDM0/P80
UDM input
UDM output
USB Digital input/output direction
GPIO Digital output
GPIO Digital input/output direction
GPIO Digital input
GPIO Digital input circuit control
I
P-ch
P-ch
N-ch
Digital output
Digital output
R






CMOS level output
CMOS level hysteresis input
5 V tolerant
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
 Available to control PZR
registers.
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
45
D a t a S h e e t
Type
Circuit
Remarks







J
P-ch
P-ch
N-ch
CMOS level output
CMOS level hysteresis input
With input control
LCD-VV input/output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
Pull-up resistor control
R
Digital input
Standby mode control
LCD VV
input/output
LCD VV control







K
P-ch
P-ch
N-ch
R
CMOS level output
CMOS level hysteresis input
With input control
LCD output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Digital output
Digital output
Pull-up resistor control
Digital input
Standby mode control
LCD output
LCD control
46
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
Type
Circuit
Remarks
L
P-ch
P-ch
N-ch
R
Digital output
Digital output







CMOS level output
CMOS level hysteresis input
With input control
LCD output
With pull-up resistor control
With standby mode control
Pull-up resistor
: Approximately 33 kΩ
 IOH= -4 mA, IOL= 4 mA
 When this pin is used as an
I2C pin, the digital output
P-ch transistor is always off
Pull-up resistor control
Digital input
Standby mode control
Analog input
Input control
LCD output
LCD control
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
47
D a t a S h e e t
 Handling Precautions
Any semiconductor devices have inherently a certain rate of failure. The possibility of failure is greatly
affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). This
page describes precautions that must be observed to minimize the chance of failure and to obtain higher
reliability from your Spansion semiconductor devices.
1. Precautions for Product Design
This section describes precautions when designing electronic equipment using semiconductor devices.
 Absolute Maximum Ratings
Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature,
etc.) in excess of certain established limits, called absolute maximum ratings. Do not exceed these ratings.
 Recommended Operating Conditions
Recommended operating conditions are normal operating ranges for the semiconductor device. All the
device's electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data
sheet. Users considering application outside the listed conditions are advised to contact their sales
representative beforehand.
 Processing and Protection of Pins
These precautions must be followed when handling the pins which connect semiconductor devices to power
supply and input/output functions.
(1) Preventing Over-Voltage and Over-Current Conditions
Exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause
deterioration within the device, and in extreme cases leads to permanent damage of the device. Try to
prevent such overvoltage or over-current conditions at the design stage.
(2) Protection of Output Pins
Shorting of output pins to supply pins or other output pins, or connection to large capacitance can
cause large current flows. Such conditions if present for extended periods of time can damage the
device.
Therefore, avoid this type of connection.
(3) Handling of Unused Input Pins
Unconnected input pins with very high impedance levels can adversely affect stability of operation.
Such pins should be connected through an appropriate resistance to a power supply pin or ground pin.
 Latch-up
Semiconductor devices are constructed by the formation of P-type and N-type areas on a substrate. When
subjected to abnormally high voltages, internal parasitic PNPN junctions (called thyristor structures) may
be formed, causing large current levels in excess of several hundred mA to flow continuously at the power
supply pin. This condition is called latch-up.
CAUTION: The occurrence of latch-up not only causes loss of reliability in the semiconductor device, but
can cause injury or damage from high heat, smoke or flame. To prevent this from happening, do the
following:
(1) Be sure that voltages applied to pins do not exceed the absolute maximum ratings. This should
include attention to abnormal noise, surge levels, etc.
(2) Be sure that abnormal current flows do not occur during the power-on sequence.
Code: DS00-00004-3E
48
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Observance of Safety Regulations and Standards
Most countries in the world have established standards and regulations regarding safety, protection from
electromagnetic interference, etc. Customers are requested to observe applicable regulations and standards
in the design of products.
 Fail-Safe Design
Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,
damage or loss from such failures by incorporating safety design measures into your facility and equipment
such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
 Precautions Related to Usage of Devices
Spansion semiconductor devices are intended for use in standard applications (computers, office automation
and other office equipment, industrial, communications, and measurement equipment, personal or
household devices, etc.).
CAUTION: Customers considering the use of our products in special applications where failure or
abnormal operation may directly affect human lives or cause physical injury or property damage, or where
extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea
floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult
with sales representatives before such use. The company will not be responsible for damages arising from
such use without prior approval.
2. Precautions for Package Mounting
Package mounting may be either lead insertion type or surface mount type. In either case, for heat resistance
during soldering, you should only mount under Spansion's recommended conditions. For detailed
information about mount conditions, contact your sales representative.
 Lead Insertion Type
Mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct
soldering on the board, or mounting by using a socket.
Direct mounting onto boards normally involves processes for inserting leads into through-holes on the
board and using the flow soldering (wave soldering) method of applying liquid solder. In this case, the
soldering process usually causes leads to be subjected to thermal stress in excess of the absolute ratings for
storage temperature. Mounting processes should conform to Spansion recommended mounting conditions.
If socket mounting is used, differences in surface treatment of the socket contacts and IC lead surfaces can
lead to contact deterioration after long periods. For this reason it is recommended that the surface treatment
of socket contacts and IC leads be verified before mounting.
 Surface Mount Type
Surface mount packaging has longer and thinner leads than lead-insertion packaging, and therefore leads are
more easily deformed or bent. The use of packages with higher pin counts and narrower pin pitch results in
increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges.
You must use appropriate mounting techniques. Spansion Inc. recommends the solder reflow method, and
has established a ranking of mounting conditions for each product. Users are advised to mount packages in
accordance with Spansion ranking of recommended conditions.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
49
D a t a S h e e t
 Lead-Free Packaging
CAUTION: When ball grid array (BGA) packages with Sn-Ag-Cu balls are mounted using Sn-Pb eutectic
soldering, junction strength may be reduced under some conditions of use.
 Storage of Semiconductor Devices
Because plastic chip packages are formed from plastic resins, exposure to natural environmental conditions
will cause absorption of moisture. During mounting, the application of heat to a package that has absorbed
moisture can cause surfaces to peel, reducing moisture resistance and causing packages to crack. To prevent,
do the following:
(1) Avoid exposure to rapid temperature changes, which cause moisture to condense inside the product.
Store products in locations where temperature changes are slight.
(2) Use dry boxes for product storage. Products should be stored below 70% relative humidity, and at
temperatures between 5°C and 30°C.
When you open Dry Package that recommends humidity 40% to 70% relative humidity.
(3) When necessary, Spansion Inc. packages semiconductor devices in highly moisture-resistant
aluminum laminate bags, with a silica gel desiccant. Devices should be sealed in their aluminum
laminate bags for storage.
(4) Avoid storing packages where they are exposed to corrosive gases or high levels of dust.
 Baking
Packages that have absorbed moisture may be de-moisturized by baking (heat drying). Follow the Spansion
recommended conditions for baking.
Condition: 125°C/24 h
 Static Electricity
Because semiconductor devices are particularly susceptible to damage by static electricity, you must take
the following precautions:
(1) Maintain relative humidity in the working environment between 40% and 70%. Use of an apparatus
for ion generation may be needed to remove electricity.
(2) Electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment.
(3) Eliminate static body electricity by the use of rings or bracelets connected to ground through high
resistance (on the level of 1 MΩ).
Wearing of conductive clothing and shoes, use of conductive floor mats and other measures to
minimize shock loads is recommended.
(4) Ground all fixtures and instruments, or protect with anti-static measures.
(5) Avoid the use of styrofoam or other highly static-prone materials for storage of completed board
assemblies.
50
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
3. Precautions for Use Environment
Reliability of semiconductor devices depends on ambient temperature and other conditions as described
above.
For reliable performance, do the following:
(1) Humidity
Prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. If high
humidity levels are anticipated, consider anti-humidity processing.
(2) Discharge of Static Electricity
When high-voltage charges exist close to semiconductor devices, discharges can cause abnormal
operation. In such cases, use anti-static measures or processing to prevent discharges.
(3) Corrosive Gases, Dust, or Oil
Exposure to corrosive gases or contact with dust or oil may lead to chemical reactions that will
adversely affect the device. If you use devices in such conditions, consider ways to prevent such
exposure or to protect the devices.
(4) Radiation, Including Cosmic Radiation
Most devices are not designed for environments involving exposure to radiation or cosmic radiation.
Users should provide shielding as appropriate.
(5) Smoke, Flame
CAUTION: Plastic molded devices are flammable, and therefore should not be used near combustible
substances. If devices begin to smoke or burn, there is danger of the release of toxic gases.
Customers considering the use of Spansion products in other special environmental conditions should
consult with sales representatives.
Please check the latest handling precautions at the following URL.
http://www.spansion.com/fjdocuments/fj/datasheet/e-ds/DS00-00004.pdf
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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51
D a t a S h e e t
 Handling Devices
 Power supply pins
In products with multiple VCC and VSS pins, respective pins at the same potential are interconnected
within the device in order to prevent malfunctions such as latch-up. However, all of these pins should be
connected externally to the power supply or ground lines in order to reduce electromagnetic emission levels,
to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total output current rating.
Moreover, connect the current supply source with each Power supply pin and GND pin of this device at low
impedance. It is also advisable that a ceramic capacitor of approximately 0.1 µF be connected as a bypass
capacitor between each Power supply pin and GND pin, between AVCC pin and AVSS pin near this device.
 Stabilizing supply voltage
A malfunction may occur when the power supply voltage fluctuates rapidly even though the fluctuation is
within the recommended operating conditions of the VCC power supply voltage. As a rule, with voltage
stabilization, suppress the voltage fluctuation so that the fluctuation in VCC ripple (peak-to-peak value) at
the commercial frequency (50 Hz/60 Hz) does not exceed 10% of the VCC value in the recommended
operating conditions, and the transient fluctuation rate does not exceed 0.1 V/μs when there is a momentary
fluctuation on switching the power supply.
 Crystal oscillator circuit
Noise near the X0/X1 and X0A/X1A pins may cause the device to malfunction. Design the printed circuit
board so that X0/X1, X0A/X1A pins, the crystal oscillator, and the bypass capacitor to ground are located as
close to the device as possible.
It is strongly recommended that the PC board artwork be designed such that the X0/X1 and X0A/X1A pins
are surrounded by ground plane as this is expected to produce stable operation.
Evaluate oscillation of your using crystal oscillator by your mount board.
 Sub crystal oscillator
This series sub oscillator circuit is low gain to keep the low current consumption.
The crystal oscillator to fill the following conditions is recommended for sub crystal oscillator to stabilize
the oscillation.
 Surface mount type
Size:
More than 3.2 mm × 1.5 mm
Load capacitance: Approximately 6 pF to 7 pF
 Lead type
Load capacitance: Approximately 6 pF to 7 pF
52
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Using an external clock
When using an external clock as an input of the main clock, set X0/X1 to the external clock input, and input
the clock to X0. X1(PE3) can be used as a general-purpose I/O port.
Similarly, when using an external clock as an input of the sub clock, set X0A/X1A to the external clock
input, and input the clock to X0A. X1A (P47) can be used as a general-purpose I/O port.
•
Example of Using an External Clock
Device
X0(X0A)
Can be used as
general-purpose
I/O ports.
Set as
External clock
input
X1(PE3),
X1A (P47)
2
 Handling when using Multi-function serial pin as I C pin
If it is using the multi-function serial pin as I2C pins, P-ch transistor of digital output is always disabled.
However, I2C pins need to keep the electrical characteristic like other pins and not to connect to the external
I2C bus system with power OFF.
 C Pin
This series contains the regulator. Be sure to connect a smoothing capacitor (C S) for the regulator between
the C pin and the GND pin. Please use a ceramic capacitor or a capacitor of equivalent frequency
characteristics as a smoothing capacitor.
However, some laminated ceramic capacitors have the characteristics of capacitance variation due to
thermal fluctuation (F characteristics and Y5V characteristics). Please select the capacitor that meets the
specifications in the operating conditions to use by evaluating the temperature characteristics of a capacitor.
A smoothing capacitor of about 4.7μF would be recommended for this series.
C
Device
CS
VSS
GND
 Mode pins (MD0)
Connect the MD pin (MD0) directly to VCC or VSS pins. Design the printed circuit board such that the
pull-up/down resistance stays low, as well as the distance between the mode pins and VCC pins or VSS pins
is as short as possible and the connection impedance is low, when the pins are pulled-up/down such as for
switching the pin level and rewriting the Flash memory data. It is because of preventing the device
erroneously switching to test mode due to noise.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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53
D a t a S h e e t
 Notes on power-on
Turn power on/off in the following order or at the same time.
If not using the A/D converter, connect AVCC = VCC and AVSS = VSS.
Turning on : VCC →AVCC → AVRH
Turning off : AVRH → AVCC → VCC
 Serial Communication
There is a possibility to receive wrong data due to the noise or other causes on the serial communication.
Therefore, design a printed circuit board so as to avoid noise.
Consider the case of receiving wrong data due to noise, perform error detection such as by applying a
checksum of data at the end. If an error is detected, retransmit the data.
 Differences in features among the products with different memory sizes and between Flash
memory products and MASK products
The electric characteristics including power consumption, ESD, latch-up, noise characteristics, and
oscillation characteristics among the products with different memory sizes and between Flash memory
products and MASK products are different because chip layout and memory structures are different.
If you are switching to use a different product of the same series, please make sure to evaluate the electric
characteristics.
 Pull-Up function of 5 V tolerant I/O
Please do not input the signal more than VCC voltage at the time of Pull-Up function use of 5 V tolerant
I/O.
54
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Block Diagram
TRSTX,TCK,
TDI,TMS
TDO
TRACEDx,
TRACECLK
ETM*1
SWJ-DP
TPIU*
SRAM0
8/16 Kbyte
ROM
Table
1
Multi-layer AHB (Max 40 MHz)
Cortex-M3 Core I
@40 MHz(Max)
D
NVIC
Sys
AHB-APB Bridge:
APB0(Max 40 MHz)
Dual-Timer
WatchDog Timer
(Software)
Clock Reset
Generator
INITX
WatchDog Timer
(Hardware)
SRAM1
8/16 Kbyte
On-Chip Flash
64+32 Kbyte/
128+32 Kbyte/
256+32 Kbyte
Flash I/F
Security
USB2.0
PHY
(Host/
Func)
UDP0/UDM0
UHCONX
DMAC
8ch.
CSV
X0
X1
X0A
X1A
CROUT
Main
Osc
Sub
Osc
PLL
CR
4 MHz
AHB-AHB
Bridge
CLK
Source Clock
CR
100 kHz
MADx
External Bus I/F*2
Unit 0
Unit 1
ADTGx
Base Timer
16-bit 8ch./
32-bit 4ch.
TIOAx
TIOBx
VVx
WKUPx
PLL
Power-On
Reset
LVD Ctrl
C
IRQ-Monitor
CRC
Accelerator
Watch Counter
External Interrupt
Controller
16-pin + NMI
INTx
NMIX
MODE-Ctrl
MD0,
MD1
P0x,
P1x,
GPIO
HDMI-CEC/
Remote Reciver Control
Real-Time Clock
MCSXx,
MOEX,
MWEX,
MALE,
MRDY,
MCLKOUT,
MDQMx
LVD
Regulator
LCDC
COMx,
SEGx
RTCCO,
SUBOUT
USB Clock Ctrl
AHB-APB Bridge : APB2 (Max 40 MHz)
ANxx
CEC0,CEC1
MADATAx
12-bit A/D Converter
AHB-APB Bridge : APB1 (Max 40 MHz)
AVCC,
AVSS,
AVRH
PIN-Function-Ctrl
.
.
.
PEx
Multi-Function Serial I/F
8ch.
(with FIFO ch.4 to ch.7)
HW flow control(ch.4)*2
Deep Standby Ctrl
SCKx
SINx
SOTx
CTS4
RTS4
*1: For the MB9AFB41LB/MB, MB9AFB42LB/MB, and MB9AFB44LB/MB, ETM is not available.
*2: For the MB9AFB41LB, MB9AFB42LB and MB9AFB44LB, the External Bus Interface is not available.
And the Multi-function Serial Interface does not support hardware flow control in these products.
 Memory Size
See Memory size in Product Lineup to confirm the memory size.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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55
D a t a S h e e t
 Memory Map
 Memory Map (1)
Peripherals Area
0x41FF_FFFF
Reserved
0xFFFF_FFFF
Reserved
0xE010_0000
0xE000_0000
Cortex-M3 Private
Peripherals
0x4006_1000
0x4006_0000
0x4005_0000
0x4004_0000
0x4003_F000
Reserved
0x4003_C000
0x4003_B000
0x4003_A000
0x7000_0000
0x6000_0000
External Device
Area
Reserved
0x4003_9000
0x4003_8000
0x4003_7000
0x4003_6000
0x4003_5000
0x4400_0000
0x4200_0000
0x4000_0000
32Mbytes
Bit band alias
Peripherals
Reserved
0x2400_0000
0x2200_0000
0x1FFF_0000
0x0020_8000
0x0020_0000
See the next page
"Memory Map (2)"
for the memory size
details.
0x0010_4000
0x0010_0000
0x4003_3000
0x4003_2000
0x4003_1000
0x4003_0000
0x4002_F000
0x4002_E000
32Mbytes
Bit band alias
Reserved
0x2008_0000
0x2000_0000
0x4003_4000
0x4002_8000
A/DC
0x4002_6000
Reserved
0x4002_5000
Base Timer
Reserved
0x4001_6000
0x4001_5000
0x0000_0000
0x4001_3000
0x4001_2000
0x4001_1000
0x4001_0000
0x4000_1000
0x4000_0000
CONFIDENTIAL
Reserved
0x4002_7000
SRAM1
SRAM0
Reserved
Flash(Work area)
Reserved
Security/CR Trim
Flash(Main area)
56
DMAC
Reserved
USB ch.0
EXT-bus I/F
Reserved
RTC
Watch Counter
CRC
MFS
Reserved
USB Clock Ctrl
LVD/DS mode
HDMI-CEC/
Remote Control Receiver
GPIO
LCDC
Int-Req.Read
EXTI
Reserved
CR Trim
Dual Timer
Reserved
SW WDT
HW WDT
Clock/Reset
Reserved
Flash I/F
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Memory Map (2)
MB9AFB44LB/MB/NB
MB9AFB42LB/MB/NB
0x2008_0000
MB9AFB41LB/MB/NB
0x2008_0000
Reserved
0x2008_0000
Reserved
Reserved
0x2000_4000
0x2000_2000
SRAM1
16Kbytes
0x2000_0000
0x2000_0000
SRAM0
16Kbytes
0x1FFF_E000
0x2000_2000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x2000_0000
0x1FFF_E000
SRAM1
8Kbytes
SRAM0
8Kbytes
0x1FFF_C000
Reserved
0x0010_4000
0x0010_2000
0x0010_0000
0x0020_8000
0x0020_0000
SA4-7 (8 KBx4)
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
0x0020_8000
0x0020_0000
SA4-7 (8 KBx4)
Reserved
Flash(Work area)
32 Kbytes
0x0020_0000
SA4-7 (8 KBx4)
Reserved
Flash(Work area)
32 Kbytes
0x0020_8000
Reserved
Flash(Work area)
32 Kbytes
Reserved
0x0010_4000
CR trimming
Security
0x0010_2000
0x0010_0000
CR trimming
Security
Reserved
Reserved
Reserved
0x0000_0000
SA2-3 (8 KBx2)
SA9 (64 KB)
SA8 (48 KB)
0x0000_0000
SA2-3 (8 KBx2)
0x0001_0000
SA8 (48 KB)
0x0000_0000
Flash(Main area)
64 Kbytes
SA8 (48 KB)
0x0002_0000
Flash(Main area)
128 Kbytes
SA9-11 (64 KBx3)
Flash(Main area)
256 Kbytes
0x0004_0000
SA2-3 (8 KBx2)
Refer to the programming manual for the detail of Flash main area.
MB9AB40N/A40N/340N/140N/150R,MB9B520M/320M/120M Series Flash Programming Manual
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
57
D a t a S h e e t
 Peripheral Address Map
Start address
End address
Bus
0x4000_0000
0x4000_0FFF
0x4000_1000
0x4000_FFFF
0x4001_0000
0x4001_0FFF
Clock/Reset Control
0x4001_1000
0x4001_1FFF
Hardware Watchdog timer
0x4001_2000
0x4001_2FFF
0x4001_3000
0x4001_4FFF
AHB
APB0
Peripherals
Flash memory I/F register
Reserved
Software Watchdog timer
Reserved
0x4001_5000
0x4001_5FFF
Dual Timer
0x4001_6000
0x4001_FFFF
Reserved
0x4002_0000
0x4002_4FFF
Reserved
0x4002_5000
0x4002_5FFF
Base Timer
0x4002_6000
0x4002_6FFF
Reserved
0x4002_7000
0x4002_7FFF
APB1
A/D Converter
0x4002_8000
0x4002_DFFF
Reserved
0x4002_E000
0x4002_EFFF
Built-in CR trimming
0x4002_F000
0x4002_FFFF
Reserved
0x4003_0000
0x4003_0FFF
External Interrupt
0x4003_1000
0x4003_1FFF
Interrupt source check register
0x4003_2000
0x4003_2FFF
LCDC
0x4003_3000
0x4003_3FFF
GPIO
0x4003_4000
0x4003_4FFF
HDMI-CEC/Remote control Receiver
0x4003_5000
0x4003_57FF
Low-Voltage Detector
0x4003_5800
0x4003_5FFF
Deep standby mode Controller
0x4003_6000
0x4003_6FFF
0x4003_7000
0x4003_7FFF
Reserved
0x4003_8000
0x4003_8FFF
Multi-function serial
0x4003_9000
0x4003_9FFF
CRC
0x4003_A000
0x4003_AFFF
Watch Counter
0x4003_B000
0x4003_BFFF
Real-time clock
0x4003_C000
0x4003_EFFF
Reserved
0x4003_F000
0x4003_FFFF
External Memory interface
0x4004_0000
0x4004_FFFF
USB ch.0
0x4005_0000
0x4005_FFFF
0x4006_0000
0x4006_0FFF
0x4006_1000
0x41FF_FFFF
58
CONFIDENTIAL
APB2
AHB
USB clock generator
Reserved
DMAC register
Reserved
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Pin Status in Each CPU State
The terms used for pin status have the following meanings.
 INITX=0
This is the period when the INITX pin is the L level.
 INITX=1
This is the period when the INITX pin is the H level.
 SPL=0
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 0.
 SPL=1
This is the status that the standby pin level setting bit (SPL) in the standby mode control register
(STB_CTL) is set to 1.
 Input enabled
Indicates that the input function can be used.
 Internal input fixed at 0
This is the status that the input function cannot be used. Internal input is fixed at L.
 Hi-Z
Indicates that the pin drive transistor is disabled and the pin is put in the Hi-Z state.
 Setting disabled
Indicates that the setting is disabled.
 Maintain previous state
Maintains the state that was immediately prior to entering the current mode.
If a built-in peripheral function is operating, the output follows the peripheral function.
If the pin is being used as a port, that output is maintained.
 Analog input is enabled
Indicates that the analog input is enabled.
 Trace output
Indicates that the trace function can be used.
 GPIO selected
In Deep standby mode, pins switch to the general-purpose I/O port.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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59
D a t a S h e e t
Pin status type
 List of Pin Status
A
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal
or Sleep
input state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Deep standby
RTC mode or Deep
standby Stop mode
state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
Return from
Deep
standby
mode state
Power
supply
stable
INITX = 1
-
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main crystal
oscillator input
pin/
External main
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External main
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Main crystal
oscillator output
pin
Hi-Z /
Internal
input
fixed at
0/
or Input
enabled
C
INITX
input pin
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
Pull-up /
Input
enabled
D
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Mode
input pin
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
GPIO
selected
B
CONFIDENTIAL
Hi-Z /
Internal
input fixed
at 0
Maintain
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
previous
state/When state/When state/When state/When state/When state/When
Hi-Z /
Hi-Z /
oscillation oscillation oscillation oscillation oscillation oscillation
Internal
Internal
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
stops*1,
input fixed input fixed
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
at 0
at 0
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed
at 0
at 0
at 0
at 0
at 0
at 0
E
60
Maintain
previous
state
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
Pin status type
D a t a S h e e t
F
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal
or Sleep
input state
detection
reset state mode state
state
Power
supply
unstable
-
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Deep standby
RTC mode or Deep
standby Stop mode
state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
Power
supply
stable
INITX = 1
-
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator input
pin /
External sub
clock input
selected
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Input
enabled
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
GPIO
selected
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
External sub
clock input
selected
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Sub crystal
oscillator output
pin
Hi-Z /
Internal
input
fixed at
0/
or Input
enable
Maintain
previous
state
Return from
Deep
standby
mode state
G
GPIO
selected
Hi-Z
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at 0
at 0
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
H
USB I/O pin
Setting
disabled
Setting
disabled
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Setting
disabled
Maintain
previous
state
Input
enabled
Input
enabled
Maintain
previous
state
Input
enabled
Hi-Z/
Internal
input fixed
at 0
GPIO
selected
Input
enabled
Maintain
Maintain
Maintain
Maintain
Maintain
previous
previous
previous
previous
previous
state/When state/When state/When state/When state/When
oscillation oscillation oscillation oscillation oscillation
stops*2,
stops*2,
stops*2,
stops*2,
stops*2,
Hi-Z /
Hi-Z /
Hi-Z/
Hi-Z/
Hi-Z/
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed
at 0
at 0
at 0
at 0
at 0
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
Hi-Z at
Hi-Z at
transtransmission/
mission/
Input
Input
enabled/
enabled/
Internal
Internal
input fixed input fixed
at 0 at
at 0 at
reception reception
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
GPIO
selected
Hi-Z /
Input
enabled
61
Pin status type
D a t a S h e e t
Function
group
Power
supply
unstable
NMIX selected
I
Power-on
reset or
Device Run mode
INITX
low-voltage
internal
or Sleep
input state
detection
reset state mode state
state
Resource other
than above
selected
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z
Pull-up /
Input
enabled
Pull-up /
Input
enabled
J
GPIO
selected
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Resource selected
K
GPIO
selected
External interrupt
enabled selected
L
Resource other
than above
selected
Hi-Z
GPIO
selected
Analog input
selected
Hi-Z
M
Resource other
than above
selected
GPIO
selected
62
CONFIDENTIAL
Setting
disabled
Hi-Z /
Input
enabled
Deep standby
RTC mode or Deep
standby Stop mode
state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Setting
disabled
Hi-Z /
Input
enabled
GPIO
selected
JTAG
selected
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Maintain
previous
state
Setting
disabled
Power
supply
stable
INITX = 1
-
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
GPIO
selected
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
selected
Internal
Internal
Hi-Z /
input fixed
Internal input fixed
at 0
at 0
input fixed
at 0
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Setting
disabled
Return from
Deep
standby
mode state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
GPIO
selected
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
GPIO
selected
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
Pin status type
D a t a S h e e t
Function
group
Power
supply
unstable
-
Analog input
selected
N
Power-on
reset or
Device Run mode
INITX
low-voltage
internal
or Sleep
input state
detection
reset state mode state
state
Hi-Z
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Deep standby
RTC mode or Deep
standby Stop mode
state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Maintain
previous
state
External interrupt
enabled selected
Resource other
than above
selected
O
Hi-Z
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at 0
at 0
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at 0
at 0
GPIO
selected
Internal
input fixed
at 0
Hi-Z
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
GPIO
selected
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Hi-Z /
Internal
input fixed
at 0
Trace
output
Trace selected
Setting
disabled
Setting
disabled
GPIO
selected
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Hi-Z /
Internal
input fixed
at 0
Trace
output
P
Resource other
than above
selected
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
GPIO
selected
Internal
input fixed
at 0
Resource other
than above
selected
Analog input
selected
Power
supply
stable
INITX = 1
-
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at 0
at 0
Maintain
previous
state
GPIO
selected
Trace selected
Return from
Deep
standby
mode state
Setting
disabled
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
selected
Internal
Hi-Z /
Internal
input fixed
Internal input fixed
at 0
input fixed
at 0
at 0
GPIO
selected
Internal
input fixed
at 0
63
Pin status type
D a t a S h e e t
Function
group
Power-on
reset or
Device Run mode
INITX
low-voltage
internal
or Sleep
input state
detection
reset state mode state
state
Power
supply
unstable
-
Analog input
selected
Hi-Z
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Deep standby
RTC mode or Deep
standby Stop mode
state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Q
Resource other
than above
selected
Setting
disabled
External interrupt
enabled selected
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
enabled
enabled
enabled
enabled
enabled
enabled
enabled
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
Setting
disabled
Setting
disabled
Hi-Z /
Internal
input fixed
at 0
Hi-Z
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Setting
disabled
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
Hi-Z
Hi-Z /
Input
enabled
Hi-Z /
Input
enabled
Maintain
previous
state
Maintain
previous
state
Resource other
than above
selected
Maintain
previous
state
GPIO
selected
CEC
enabled
S
Resource other
than above
selected
GPIO
selected
64
CONFIDENTIAL
Maintain
previous
state
GPIO
selected
Internal
input fixed
at 0
Maintain
previous
state
WKUP
enabled
R
Hi-Z /
Internal
input fixed
at 0 /
Analog
input
enabled
GPIO
Hi-Z /
selected
Internal
Internal
input fixed
input fixed
at 0
at 0
Maintain
previous
state
GPIO
selected
Analog input
selected
Power
supply
stable
INITX = 1
-
Trace
output
Trace selected
External interrupt
enabled selected
Return from
Deep
standby
mode state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
GPIO
Hi-Z /
selected
Internal
Internal
Hi-Z /
input fixed
Internal input fixed
at 0
at 0
input fixed
at 0
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Internal
Internal
Internal
input fixed
input fixed
input fixed
at 0
at 0
at 0
GPIO
selected
Internal
input fixed
at 0
Maintain
previous
state
GPIO
selected
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
Pin status type
D a t a S h e e t
Function
group
Power
supply
unstable
CEC
enabled
WKUP
enabled
T
Power-on
reset or
Device Run mode
INITX
low-voltage
internal
or Sleep
input state
detection
reset state mode state
state
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Setting
disabled
Hi-Z
GPIO
selected
resource
selected
U
GPIO
selected
External interrupt
enabled selected
Resource other
than above
selected
Hi-Z
Setting
disabled
GPIO
selected
Setting
disabled
Setting
disabled
Maintain
previous
state
Maintain
previous
state
WKUP
input
enabled
Hi-Z /
WKUP
input
enabled
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
selected
Internal
Hi-Z /
Internal
Internal input fixed input fixed
at 0
input fixed
at 0
at 0
Maintain
previous
state
GPIO
selected
GPIO
Hi-Z /
Hi-Z /
GPIO
selected
Internal
Internal
selected
Internal
input fixed
input fixed Internal input
input fixed
at 0
at 0
fixed at 0
at 0
Maintain
previous
state
Setting
disabled
Setting
disabled
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at 0
at 0
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Maintain
previous
state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
GPIO
selected
Internal
selected
Internal
Hi-Z /
input fixed Internal input
Internal input fixed
at 0
fixed at 0
at 0
input fixed
at 0
Hi-Z
Hi-Z
GPIO
selected
INITX = 1
SPL = 0
SPL = 1
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Hi-Z /
Internal
Internal
Internal
Internal
Internal
Internal
Internal
Internal
input fixed input fixed input fixed input fixed input fixed input fixed input fixed
input fixed
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
at 0 /
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
input
input
input
input
input
input
input
input enabled
enabled
enabled
enabled
enabled
enabled
enabled
enabled
resource selected
X
INITX = 1
SPL = 0
SPL = 1
Power
supply
stable
INITX = 1
-
Hi-Z
W
Resource other
than above
selected
Power supply stable
Hi-Z /
Input
enabled
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at 0
at 0
Setting
disabled
Power supply stable
Return from
Deep
standby
mode state
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at 0
at 0
GPIO
selected
Analog input
selected
Hi-Z /
Input
enabled
Maintain
previous
state
Deep standby
RTC mode or Deep
standby Stop mode
state
Setting
disabled
External interrupt
enabled selected
Resource other
than above
selected
V
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Timer mode,
RTC mode, or
Sleep mode state
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
GPIO
selected
Internal
Internal
selected
Internal
input fixed
input fixed Internal input
input fixed
at 0
at 0
fixed at 0
at 0
Maintain
previous
state
Maintain
previous
state
GPIO
Hi-Z /
Hi-Z /
selected
Hi-Z /
Internal
Internal
Internal
Internal input
input fixed
input fixed
input fixed
fixed at 0
at 0
at 0
at 0
65
Pin status type
D a t a S h e e t
Function
group
Power
supply
unstable
External interrupt
enabled selected
Y
Power-on
reset or
Device Run mode
INITX
low-voltage
internal
or Sleep
input state
detection
reset state mode state
state
Resource other
than above
selected
GPIO
selected
Setting
disabled
Hi-Z
Power
supply
stable
INITX = 0 INITX = 1 INITX = 1
Power supply stable
Setting
disabled
Timer mode,
RTC mode, or
Sleep mode state
Deep standby
RTC mode or Deep
standby Stop mode
state
Power supply stable
Power supply stable
INITX = 1
SPL = 0
SPL = 1
INITX = 1
SPL = 0
SPL = 1
Setting
disabled
Hi-Z /
Hi-Z /
Internal
Internal
input fixed input fixed
at 0
at 0
Maintain
previous
state
Maintain
previous
state
Return from
Deep
standby
mode state
Power
supply
stable
INITX = 1
-
Maintain
previous
state
GPIO
Hi-Z /
selected
Hi-Z /
Internal
Internal
Internal input
Hi-Z /
input fixed
fixed at 0
Internal input fixed
at 0
at 0
input fixed
at 0
*1: Oscillation is stopped at Sub Timer mode, Low-speed CR Timer mode, RTC mode, Stop mode, Deep
Standby RTC mode, and Deep Standby Stop mode.
*2: Oscillation is stopped at Stop mode and Deep Standby Stop mode.
66
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Electrical Characteristics
1. Absolute Maximum Ratings
Parameter
Power supply voltage*1, *2
Analog power supply voltage*1, *3
Analog reference voltage*1, *3
LCD input voltage *1, *3
Input voltage*1
Symbol
VCC
AVCC
AVRH
VV0 to
VV4
VI
Rating
Max
VSS - 0.5
VSS - 0.5
VSS - 0.5
VSS + 4.6
VSS + 4.6
VSS + 4.6
V
V
V
VSS - 0.5
VSS + 4.6
V
VSS - 0.5
VSS - 0.5
Analog pin input voltage*
1
VIA
VSS - 0.5
Output voltage*1
VO
VSS - 0.5
L level maximum output current*4
IOL
-
IOLAV
-
∑IOL
∑IOLAV
-
IOH
-
IOHAV
-
L level average output current*5
L level total maximum output current
L level total average output current*6
H level maximum output current*4
H level average output current*5
Unit
Min
VCC + 0.5
(≤ 4.6 V)
VSS + 6.5
AVCC + 0.5
(≤ 4.6 V)
VCC + 0.5
(≤ 4.6 V)
10
mA
39
mA
4
10.5
27
100
50
- 10
mA
mA
mA
mA
mA
mA
39
mA
-4
12
27
- 100
- 50
300
+ 150
mA
mA
mA
mA
mA
mW
°C
Remarks
V
V
5 V tolerant
V
V
P81/UDP0 ,
P80/UDM0 pins
*7
*8
P81/UDP0 ,
P80/UDM0 pins
*7
*8
H level total maximum output current
∑IOH
H level total average output current*6
∑IOHAV
Power consumption
PD
Storage temperature
TSTG
- 55
*1: These parameters are based on the condition that V SS = AVSS = 0V.
*2: VCC must not drop below VSS - 0.5V.
*3: Ensure that the voltage does not to exceed VCC + 0.5 V, for example, when the power is turned on.
*4: The maximum output current is defined as the value of the peak current flowing through any one of the
corresponding pins.
*5: The average output current is defined as the average current value flowing through any one of the
corresponding pins for a 100 ms period.
*6: The total average output current is defined as the average current value flowing through all of
corresponding pins for a 100ms.
*7: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*8: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
<WARNING>
Semiconductor devices may be permanently damaged by application of stress (including, without limitation,
voltage, current or temperature) in excess of absolute maximum ratings.
Do not exceed any of these ratings.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
67
D a t a S h e e t
2. Recommended Operating Conditions
(VSS = AVSS = 0.0V)
Parameter
Symbol
Conditions
Value
Min
Max
6
Unit
Remarks
1
1.65*
3.6
* , *4
6
Power supply voltage
VCC
3.0*
3.6
V
*2
2.2*6
3.6
*1, *3
LCD input voltage
VVV4
2.2
VCC
V
Analog power supply voltage
AVCC
1.65
3.6
V
AVCC = VCC
2.7
AVCC
V
AVCC ≥ 2.7 V
Analog reference voltage
AVRH
AVCC
AVCC
V
AVCC<2.7 V
Smoothing capacitor
CS
-1
10
µF For Regulator*5
Operating temperature
TA
- 40
+ 85
°C
*1: When P81/UDP0 and P80/UDM0 pins are used as GPIO (P81, P80).
*2: When P81/UDP0 and P80/UDM0 pins are used as USB (UDP0, UDM0).
*3: When LCD Controller is used.
*4: When LCD Controller is not used.
*5 : See  C Pin in  Handling Devices for the connection of the smoothing capacitor.
*6 : In between less than the minimum power supply voltage and low voltage reset/interrupt detection voltage
or more, instruction execution and low voltage detection function by built-in High-speed CR(including
Main PLL is used) or built-in Low-speed CR is possible to operate only.
<WARNING>
The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device's electrical characteristics are warranted when the device is
operated under these conditions.
Any use of semiconductor devices will be under their recommended operating condition.
Operation under any conditions other than these conditions may adversely affect reliability of device and
could result in device failure.
No warranty is made with respect to any use, operating conditions or combinations not represented on this
data sheet. If you are considering application under any conditions other than listed herein, please contact
sales representatives beforehand.
68
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
3. DC Characteristics
(1) Current rating
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter Symbol
Pin
name
Conditions
PLL
Rrun mode
ICC
Power
supply
current
VCC
ICCS
High-speed
CR
Rrun mode
Sub
Rrun mode
Low-speed
CR
Run mode
PLL
Sleep mode
High-speed
CR
Sleep mode
Sub
Sleep mode
Low-speed
CR
Sleep mode
CPU: 40 MHz,
Peripheral: 40 MHz
CPU: 40 MHz,
Peripheral: the clock stops
NOP operation
Value
Unit Remarks
Typ*3 Max*4
15.5
21
mA
*1, *5
8.7
12
mA
*1, *5
CPU/ Peripheral: 4 MHz*2
1.8
2.9
mA
*1
CPU/ Peripheral: 32 kHz
110
680
μA
*1, *6
CPU/ Peripheral: 100 kHz
125
700
μA
*1
Peripheral: 40 MHz
9
12.5
mA
*1, *5
Peripheral: 4 MHz*2
0.8
1.6
mA
*1
Peripheral: 32 kHz
96
670
μA
*1, *6
Peripheral: 100 kHz
110
680
μA
*1
*1: When all ports are fixed.
*2: When setting it to 4 MHz by trimming.
*3: TA=+25°C, VCC=3.6 V
*4: TA=+85°C, VCC=3.6 V
*5: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*6: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
69
D a t a S h e e t
Parameter Symbol
Pin
name
Conditions
Main Timer
mode
ICCT
Sub Timer
mode
ICCR
RTC mode
ICCH
Power
supply
current
Stop mode
VCC
ICCHD
ICCRD
Deep Standby
Stop mode
Deep Standby
RTC mode
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off
TA = + 85°C,
When LVD is off
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
TA = + 25°C,
When LVD is off,
When RAM is off
TA = + 25°C,
When LVD is off,
When RAM is on
TA = + 85°C,
When LVD is off,
When RAM is off
TA = + 85°C,
When LVD is off,
When RAM is on
Value
Unit Remarks
Typ*2 Max*2
2.1
2.5
mA *1, *3
-
3.4
mA *1, *3
12
35
μA *1, *4
-
330
μA *1, *4
9.8
29
μA *1, *4
-
280
μA *1, *4
9
28
μA *1
-
270
μA *1
1.25
7
μA
*1, *4, *5
5.3
18
μA
*1, *4, *5
70
μA
*1, *4, *5
100
μA
*1, *4, *5
1.9
9
μA
*1, *5
5.9
20
μA
*1, *5
75
μA
*1, *5
105
μA
*1, *5
-
-
*1: When all ports are fixed.
*2: VCC=3.6 V
*3: When using the crystal oscillator of 4 MHz(Including the current consumption of the oscillation circuit)
*4: When using the crystal oscillator of 32 kHz(Including the current consumption of the oscillation circuit)
*5: RAM on/off setting is on-chip SRAM only.
70
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
· Low-Voltage Detection Current
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Low-voltage
detection circuit
(LVD) power
supply current
Symbol
ICCLVD
Pin
name
Conditions
Value
Typ
Max
At operation
for reset
VCC = 3.6 V
0.13
0.3
μA
At not detect
At operation
for interrupt
VCC = 3.6 V
0.13
0.3
μA
At not detect
Unit
Remarks
VCC
· Flash Memory Current
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
name
Conditions
Flash memory
write/erase
current
ICCFLASH
VCC
At Write/Erase
Value
Typ
Max
Unit
9.5
mA
11.2
Remarks
*
*: The current at which to write or erase Flash memory, I CCFLASH is added to ICC.
· A/D Converter Current
(VCC = VCC28 = AVCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = AVSS = 0V, TA = - 40°C to +85°C)
Parameter
Power supply
current
Reference power
supply current
Symbol
ICCAD
ICCAVRH
Pin
name
AVCC
AVRH
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Value
Typ
Max
Unit
At 1unit
operation
0.27
0.42
mA
At stop
0.03
10
μA
At 1unit
operation
AVRH=3.6 V
0.72
1.29
mA
At stop
0.02
2.6
μA
Conditions
Remarks
71
D a t a S h e e t
(2) Pin Characteristics
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Parameter Symbol Pin name
Conditions
CMOS
hysteresis
input pin,
MD0, MD1
VCC ≥ 2.7 V
VCC × 0.8
VCC < 2.7 V
VCC × 0.7
VCC ≥ 2.7 V
VCC × 0.8
H level input
voltage
(hysteresis
input)
L level input
voltage
(hysteresis
input)
VIHS
5V tolerant
input pin
VILS
CMOS
hysteresis
input pin,
MD0, MD1
5V tolerant
input pin
4mA type
H level
output voltage
VOH
The pin
doubled as
USB I/O
4mA type
L level
output voltage
VOL
The pin
doubled as
USB I/O
-
Input leak
current
Pull-up
resistor value
Input
capacitance
72
CONFIDENTIAL
IIL
RPU
CIN
CEC0,
CEC1
VCC < 2.7 V
Min
Value
Typ
Max
-
VCC + 0.3
V
-
VSS + 5.5
V
VCC × 0.7
VCC ≥ 2.7 V
VCC × 0.2
VSS - 0.3
-
VCC < 2.7 V
V
VCC × 0.3
VCC ≥ 2.7 V
VCC × 0.2
VSS - 0.3
-
VCC < 2.7 V
VCC ≥ 2.7 V,
IOH = - 4 mA
VCC < 2.7 V,
IOH = - 2 mA
VCC ≥ 2.7 V,
IOH = - 12 mA
V
VCC × 0.3
VCC - 0.5
-
VCC
V
VCC - 0.4
-
VCC
V
VSS
-
0.4
V
VSS
-
0.4
V
-5
-
+5
μA
-
-
+1.8
μA
VCC ≥ 2.7 V
21
33
66
VCC < 2.7 V
-
-
134
-
-
5
15
VCC < 2.7 V,
IOH = - 6.5 mA
VCC ≥ 2.7 V,
IOL = 4 mA
VCC < 2.7 V,
IOL = 2 mA
VCC ≥ 2.7 V,
IOL = 10.5 mA
VCC < 2.7 V,
IOL = 5 mA
VCC = AVCC =
AVRH = VSS =
AVSS = 0.0 V
VCC - 0.45
Pull-up pin
Other than
VCC,
VSS,
AVCC,
AVSS,
AVRH
Unit Remarks
kΩ
pF
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
4. LCD Characteristics
(VCC = 2.2V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
VV0 to VV3
Output voltage
(1/4 bias)
VV0 to VV3
Output voltage
(1/3 bias)
VV0 to VV3
Output voltage
(1/2 bias)
VV4
Active current
(1/4 bias)
VV4
Active current
(1/3 bias)
VV4
Active current
(1/2 bias)
VV4
Static current
VV0
Output Voltage
in using
external resistor
Symbol
Pin
name
VVV0
VV0
VVV1
VV1
VVV2
VV2
VVV3
VV3
VVV0
VV0
VVV1
VV1
VVV2
VV2
VVV3
VV3
VVV0
VV0
VVV1
VV1
VVV2
VV2
VVV3
VV3
IR100K
VV4
IR10K
VV4
IR100K
VV4
IR10K
VV4
IR100K
VV4
IR10K
VV4
IOFF_VV4
VV4
VVV0E
VV0
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Conditions
When using
internal
dividing resistor
Min
Value
Typ
Max
0
-
VVV4 × 5%
VVV4 × 1/4
-10%
VVV4 × 1/2
-10%
VVV4 × 3/4
-10%
0
When using
internal
dividing resistor
VVV4 × 1/3
-10%
VVV4 × 2/3
-10%
VVV4 × 2/3
-10%
0
When using
internal
dividing resistor
When using
100 kΩ internal
dividing resistor
When using
10 kΩ internal
dividing resistor
When using
100 kΩ internal
dividing resistor
When using
10 kΩ internal
dividing resistor
When using
100 kΩ internal
dividing resistor
When using
10 kΩ internal
dividing resistor
VVV4 × 1/2
-10%
VVV4 × 1/2
-10%
VVV4 × 1/2
-10%
-
VVV4 × 1/4
+10%
VVV4 × 1/2
+10%
VVV4 × 3/4
+10%
Unit
Rem
arks
V
VVV4 × 5%
VVV4 × 1/3
+10%
VVV4 × 2/3
+10%
VVV4 × 2/3
+10%
V
VVV4 × 5%
VVV4 × 1/2
+10%
VVV4 × 1/2
+10%
VVV4 × 1/2
+10%
V
-
10
20
μA
-
100
160
μA
-
12
30
μA
-
120
180
μA
-
18
40
μA
-
180
270
μA
When LCD
stops
-
0.5
1.5
μA
IOL=1 mA
-
-
0.66
V
73
D a t a S h e e t
5. AC Characteristics
(1) Main Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Input clock cycle
Input clock pulse
width
Input clock rising
time and falling
time
Symbol
Pin
Conditions
name
Value
Min
Max
Unit
VCC ≥ 2.7 V
VCC < 2.7 V
4
4
48
20
MHz
-
4
48
MHz
-
20.83
250
ns
-
PWH/tCYLH,
PWL/tCYLH
45
55
%
tCF,
tCR
-
-
5
ns
-
-
40
MHz
fCH
tCYLH
fCM
X0,
X1
-
Remarks
When crystal oscillator
is connected
When using external
clock
When using external
clock
When using external
clock
When using external
clock
Master clock
Base clock
fCC
40
MHz
(HCLK/FCLK)
Internal operating
clock*1 frequency
fCP0
40
MHz APB0 bus clock*2
fCP1
40
MHz APB1 bus clock*2
fCP2
40
MHz APB2 bus clock*2
Base clock
tCYCC
25
ns
(HCLK/FCLK)
Internal operating
tCYCP0
25
ns
APB0 bus clock*2
1
clock* cycle time
tCYCP1
25
ns
APB1 bus clock*2
tCYCP2
25
ns
APB2 bus clock*2
*1: For more information about each internal operating clock, see Chapter 2-1: Clock in FM3 Family Peripheral
Manual.
*2: For about each APB bus which each peripheral is connected to, see  Block Diagram in this data
sheet.
X0
74
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
(2) Sub Clock Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input frequency
Symbol
Min
Value
Typ
Max
-
-
32.768
-
kHz
-
32
-
100
kHz
Pin
Conditions
name
Unit
fCL
X0A,
X1A
Input clock cycle
tCYLL
-
10
-
31.25
μs
Input clock pulse
width
-
PWH/tCYLL,
PWL/tCYLL
45
-
55
%
Remarks
When crystal
oscillator is
connected
When using
external clock
When using
external clock
When using
external clock
X0A
(3) Built-in CR Oscillation Characteristics
 Built-in High-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
fCRH
Min
Value
Typ
Max
TA = + 25°C
VCC ≥ 2.7V
3.96
4
4.04
TA = + 25°C
VCC < 2.7V
3.9
4
4.1
Conditions
TA =
- 40°C to + 85°C
TA =
- 40°C to + 85°C
Unit
Remarks
When trimming*1
MHz
3.84
4
4.16
2.8
-
5.2
When not trimming
Frequency
tCRWT
30
μs *2
stabilization time
*1: In the case of using the values in CR trimming area of Flash memory at shipment for frequency/temperature
trimming.
*2: This is the time to stabilize the frequency of High-speed CR clock after setting trimming value.
This period is able to use High-speed CR clock as source clock.
 Built-in Low-speed CR
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Clock frequency
Symbol
Conditions
fCRL
-
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Min
Value
Typ
Max
50
100
150
Unit
Remarks
kHz
75
D a t a S h e e t
(4-1) Operating Conditions of Main and USB PLL (In the case of using main clock for input of PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Min
Value
Typ
Max
tLOCK
100
-
-
μs
fPLLI
fPLLO
-
16
37
150
40
MHz
multiple
MHz
MHz
-
48
MHz
Symbol
PLL oscillation stabilization wait time*1
(LOCK UP time)
PLL input clock frequency
PLL multiple rate
PLL macro oscillation clock frequency
Main PLL clock frequency*2
fCLKPLL
4
5
75
-
USB clock frequency*3
fCLKSPLL
-
Unit
Remarks
After the M
frequency division
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family
Peripheral Manual.
*3: For more information about USB clock, see Chapter 2-2: USB Clock Generation in FM3 Family
Peripheral Manual Communication Macro Part.
(4-2) Operating Conditions of Main PLL (In the case of using the built-in High-speed CR for the input
clock of the Main PLL)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Typ
Min
Max
Unit
Remarks
PLL oscillation stabilization wait time*1
tLOCK
100
μs
(LOCK UP time)
PLL input clock frequency
fPLLI
3.8
4
4.2
MHz
PLL multiple rate
19
35 multiple
PLL macro oscillation clock frequency
fPLLO
72
150
MHz
Main PLL clock frequency*2
fCLKPLL
40
MHz
*1: Time from when the PLL starts operating until the oscillation stabilizes.
*2: For more information about Main PLL clock (CLKPLL), see Chapter 2-1: Clock in FM3 Family
Peripheral Manual.
Note: Make sure to input to the Main PLL source clock, the High-speed CR clock (CLKHC) that the
frequency/temperature has been trimmed.
When setting PLL multiple rate, please take the accuracy of the built-in High-speed CR clock into account
and prevent the master clock from exceeding the maximum frequency.
Main PLL connection
Main clock (CLKMO)
High-speed CR clock (CLKHC)
K
divider
PLL input
clock
Main
PLL
PLL macro
oscillation clock
M
divider
Main PLL
clock
(CLKPLL)
N
divider
USB PLL connection
Main clock (CLKMO)
PLL input
clock
K
divider
USB PLL
PLL macro
oscillation clock
M
divider
USB
clock
N
divider
76
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
(5) Reset Input Characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Reset input time
Symbol
tINITX
Value
Pin
Conditions
name
Min
Max
INITX
500
-
-
Unit Remarks
ns
(6) Power-on Reset Timing
(VCC= 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Power supply rising time
tVCCR
Power supply shut down time
Time until releasing
Power-on reset
tOFF
Pin
name
Value
Max
0
-
ms
1
-
ms
1.34
16.09
ms
VCC
tPRT
Unit
Min
Remarks
VCC_minimum
VCC
VDH_minimum
0.2V
0.2V
0.2V
tVCCR
tPRT
Internal reset
CPU Operation
Reset active
tOFF
Release
start
Glossary
・ VCC_minimum: Minimum VCC of recommended operating conditions
・ VDH_minimum: Minimum detection voltage (when SVHR=00000) of Low-Voltage detection reset
See 8. Low-Voltage Detection Characteristics
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
77
D a t a S h e e t
(7) External Bus Timing
 External bus clock output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
Max
Unit
VCC ≥ 2.7 V
40
MHz
VCC < 2.7 V
20
MHz
*: The external bus clock output (MCLKOUT) is a divided clock of HCLK.
For more information about setting of clock divider, see Chapter 12: External Bus Interface in FM3 Family
Peripheral Manual.
When external bus clock is not output, this characteristic does not give any effect on external bus operation.
Output frequency
tCYCLE
MCLKOUT*
MCLKOUT
 External bus signal input/output characteristics
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Signal input characteristics
Signal output characteristics
78
CONFIDENTIAL
Symbol
Conditions
VIH
VIL
VOH
-
VOL
Input signal
VIH
VIL
VIH
VIL
Output signal
VOH
VOL
VOH
VOL
Value
Unit
0.8 × VCC
V
0.2 × VCC
V
0.8 × VCC
V
0.2 × VCC
V
Remarks
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Separate Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 2.7 V
MOEX
tOEW
MOEX
MCLK×n-3
Min pulse width
VCC < 2.7 V
VCC ≥ 2.7 V
-9
MCSX ↓ → Address
MCSX[7:0],
tCSL – AV
output delay time
MAD[24:0]
VCC < 2.7 V
-12
VCC ≥ 2.7 V
MOEX ↑ →
MOEX,
tOEH - AX
0
Address hold time
MAD[24:0]
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×m-9
MCSX ↓ →
tCSL - OEL
MOEX ↓ delay time
VCC < 2.7 V MCLK×m-12
MOEX,
MCSX[7:0]
VCC ≥ 2.7 V
MOEX ↑ →
tOEH - CSH
0
MCSX ↑ time
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×m-9
MCSX ↓ →
MCSX,
tCSL - RDQML
MDQM ↓ delay time
MDQM[1:0]
VCC < 2.7 V MCLK×m-12
VCC ≥ 2.7 V
30
Data set up →
MOEX,
tDS - OE
MOEX ↑ time
MADATA[15:0]
VCC < 2.7 V
38
VCC ≥ 2.7 V
MOEX ↑ →
MOEX,
tDH - OE
0
Data hold time
MADATA[15:0]
VCC < 2.7 V
VCC ≥ 2.7 V
MWEX
tWEW
MWEX
MCLK×n-3
Min pulse width
VCC < 2.7 V
VCC ≥ 2.7 V
MWEX ↑ → Address
MWEX,
tWEH - AX
0
output delay time
MAD[24:0]
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×n-9
MCSX ↓ →
tCSL - WEL
MWEX ↓ delay time
VCC < 2.7 V MCLK×n-12
MWEX,
MCSX[7:0]
VCC ≥ 2.7 V
MWEX ↑ →
tWEH - CSH
0
MCSX ↑ delay time
VCC < 2.7 V
VCC ≥ 2.7 V
MCLK×n-9
MCSX ↓→
MCSX,
tCSL-WDQML
MDQM ↓ delay time
MDQM[1:0]
VCC < 2.7 V MCLK×n-12
VCC ≥ 2.7 V
MCLK-9
MWEX ↓→
MCSX,
tCSL - DV
Data output time
MADATA[15:0]
VCC < 2.7 V
MCLK-12
VCC ≥ 2.7 V
MWEX ↑ →
MWEX,
tWEH - DX
0
Data hold time
MADATA[15:0]
VCC < 2.7 V
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Max
+9
+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
MCLK×m+9
MCLK×m+12
-
Unit
ns
ns
ns
ns
ns
ns
ns
-
ns
-
ns
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK×m+9
MCLK×m+12
MCLK×n+9
MCLK×n+12
MCLK+9
MCLK+12
MCLK×m+9
MCLK×m+12
ns
ns
ns
ns
ns
ns
79
D a t a S h e e t
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
80
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Separate Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Address delay time
Symbol
Pin name
Conditions
tAV
MCLK,
MAD[24:0]
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC<2.7 V
VCC ≥ 2.7 V
VCC<2.7 V
tCSL
MCSX delay time
tCSH
tREL
MOEX delay time
tREH
Data set up →
MCLK ↑ time
MCLK ↑ →
Data hold time
tDS
tDH
tWEL
MWEX delay time
tWEH
MDQM[1:0]
delay time
tDQML
tDQMH
MCLK,
MCSX[7:0]
MCLK,
MOEX
MCLK,
MADATA[15:0]
MCLK,
MADATA[15:0]
MCLK,
MWEX
MCLK,
MDQM[1:0]
MCLK ↑ →
MCLK,
tODS
Data output time
MADATA[15:0]
MCLK ↑ →
MCLK,
tOD
Data hold time
MADATA[15:0]
Note: When the external load capacitance CL = 30 pF.
Value
Unit
Min
Max
1
12
13
ns
1
12
ns
1
12
ns
1
1
9
12
9
12
ns
ns
24
37
-
ns
0
-
ns
1
1
1
1
MCLK + 1
1
9
12
9
12
9
12
9
12
MCLK + 18
MCLK + 24
18
24
ns
ns
ns
ns
ns
ns
MCLK
MCSX[7:0]
MAD[24:0]
MOEX
MDQM[1:0]
MWEX
MADATA[15:0]
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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81
D a t a S h e e t
 Multiplexed Bus Access Asynchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin name
Conditions
Value
Min
VCC ≥ 2.7 V
Multiplexed
tALE-CHMADV
-2
address delay time
VCC < 2.7 V
MALE,
MADATA[15:0]
VCC ≥ 2.7 V MCLK×n+0
Multiplexed
tCHMADH
address hold time
VCC < 2.7 V MCLK×n+0
Note: When the external load capacitance CL = 30 pF (m = 0 to 15, n = 1 to 16).
Max
+10
+20
MCLK×n+10
MCLK×n+20
Unit
ns
ns
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
82
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Multiplexed Bus Access Synchronous SRAM Mode
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
tCHAL
MALE delay time
tCHAH
Pin name
Conditions
MCLK,
ALE
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
MCLK ↑ →
Multiplexed
tCHMADV
Address delay time
MCLK,
MADATA[15:0]
MCLK ↑ →
Multiplexed
tCHMADX
Data output time
Note: When the external load capacitance CL = 30 pF.
VCC ≥ 2.7 V
Min
VCC < 2.7 V
Unit Remarks
9
12
9
12
ns
ns
ns
ns
1
tOD
ns
1
tOD
ns
1
1
VCC < 2.7 V
VCC ≥ 2.7 V
Value
Max
MCLK
MCSX[7:0]
MALE
MAD [24:0]
MOEX
MDQM [1:0]
MWEX
MADATA[15:0]
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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D a t a S h e e t
 External Ready Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
MCLK ↑
MRDY input
setup time
Symbol
tRDYI
Pin name Conditions
MCLK,
MRDY
Value
Min
VCC ≥ 2.7 V
23
VCC < 2.7 V
37
Max
-
Unit
Remarks
ns
When RDY is input
···
MCLK
Over 2cycles
Original
MOEX
MWEX
tRDYI
MRDY
When RDY is released
MCLK
··· ···
2 cycles
Extended
MOEX
MWEX
tRDYI
0.5×VCC
MRDY
84
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
(8) Base Timer Input Timing
 Timer input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTIWH,
tTIWL
TIOAn/TIOBn
(when using as
ECK, TIN)
-
tTIWH
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTIWL
ECK
VIHS
TIN
VIHS
VILS
VILS
 Trigger input timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
Pin name
Conditions
tTRGH,
tTRGL
TIOAn/TIOBn
(when using as
TGIN)
-
tTRGH
TGIN
VIHS
Value
Min
Max
2tCYCP
-
Unit Remarks
ns
tTRGL
VIHS
VILS
VILS
Note: tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Base Timer is connected to, see Block Diagram in this data sheet.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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85
D a t a S h e e t
(9) CSIO/UART Timing
 CSIO (SPI = 0, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Pin
Symbol
Conditions
name
Serial clock cycle time
tSCYC
SCK ↓ → SOT delay time
tSLOVI
SIN → SCK ↑ setup time
tIVSHI
SCK ↑ → SIN hold time
tSHIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
VCC < 2.7 V
Min
Max
VCC ≥ 2.7 V
Min
Max
Unit
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
-
ns
-
ns
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to clock synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30 pF.
86
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
87
D a t a S h e e t
 CSIO (SPI = 0, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
VCC < 2.7 V
Min
Max
SCKx
SCKx,
SOTx
SCKx, Master mode
SINx
SCKx,
SINx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓ → SIN hold time
tSLIXI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓ → SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 2.7 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 10
tCYCP +
10
-
2tCYCP 10
tCYCP +
10
Unit
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to clock synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
 About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30 pF.
88
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
tSCYC
SCK
VOH
VOH
VOL
tSHOVI
VOH
VOL
SOT
tIVSLI
VIH
SIN
tSLIXI
VIH
VIL
VIL
Master mode
tSHSL
SCK
VIH
VIH
VIL
tR
SOT
tSLSH
tF
VIL
VIL
tSHOVE
VOH
VOL
tIVSLE
SIN
VIH
VIL
tSLIXE
VIH
VIL
Slave mode
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
89
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 0)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
VCC < 2.7 V
Min
Max
SCKx
SCKx,
SOTx
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
4tCYCP
-
4tCYCP
-
ns
- 30
+ 30
- 20
+ 20
ns
50
-
36
-
ns
0
-
0
-
ns
-
ns
-
ns
-
ns
Serial clock cycle time
tSCYC
SCK ↑ → SOT delay time
tSHOVI
SIN → SCK ↓ setup time
tIVSLI
SCK ↓→ SIN hold time
tSLIXI
SOT → SCK ↓ delay time
tSOVLI
Serial clock L pulse width
tSLSH
SCKx
Serial clock H pulse width
tSHSL
SCKx
SCK ↑ → SOT delay time
tSHOVE
SIN → SCK ↓ setup time
tIVSLE
SCK ↓→ SIN hold time
tSLIXE
SCK falling time
SCK rising time
tF
tR
VCC ≥ 2.7 V
Min
Max
Pin
Conditions
name
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 34
2tCYCP 10
tCYCP +
10
-
2tCYCP 34
2tCYCP 10
tCYCP +
10
Unit
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to clock synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
 About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30 pF.
90
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOL
tSOVLI
SOT
VOH
VOL
VOH
VOL
tIVSLI
tSLIXI
VIH
VIL
SIN
VOL
tSHOVI
VIH
VIL
Master mode
tSLSH
VIH
SCK
SOT
VIL
VIL
tF
*
VOH
VOL
tR
tIVSLE
SIN
tSHSL
VIH
VIH
tSHOVE
VOH
VOL
tSLIXE
VIH
VIL
VIH
VIL
Slave mode
*: Changes when writing to TDR register
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
91
D a t a S h e e t
 CSIO (SPI = 1, SCINV = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Pin
Conditions
name
VCC < 2.7 V
Min
Max
VCC ≥ 2.7 V
Min
Max
Unit
Serial clock cycle time
tSCYC
SCKx
4tCYCP
-
4tCYCP
-
ns
SCK ↓ → SOT delay time
tSLOVI
SCKx,
SOTx
- 30
+ 30
- 20
+ 20
ns
SIN → SCK ↑ setup time
tIVSHI
50
-
36
-
ns
SCK ↑ → SIN hold time
tSHIXI
0
-
0
-
ns
SOT → SCK ↑ delay time
tSOVHI
-
ns
Serial clock L pulse width
tSLSH
SCKx
-
ns
Serial clock H pulse width
tSHSL
SCKx
-
ns
SCK ↓ → SOT delay time
tSLOVE
SIN → SCK ↑ setup time
tIVSHE
SCK ↑ → SIN hold time
tSHIXE
SCK falling time
SCK rising time
tF
tR
SCKx,
SINx Master mode
SCKx,
SINx
SCKx,
SOTx
SCKx,
SOTx
SCKx,
SINx
SCKx,
SINx
SCKx
SCKx
2tCYCP 34
2tCYCP 10
tCYCP +
10
-
2tCYCP 34
2tCYCP 10
tCYCP +
10
-
50
-
33
ns
10
-
10
-
ns
20
-
20
-
ns
-
5
5
-
5
5
ns
ns
Slave mode
Notes:  The above characteristics apply to clock synchronous mode.
 tCYCP indicates the APB bus clock cycle time.
 About the APB bus number which Multi-function serial is connected to, see Block Diagram in
this data sheet.
 These characteristics only guarantee the same relocate port number.
For example, the combination of SCKx_0 and SOTx_1 is not guaranteed.
 When the external load capacitance CL = 30 pF.
92
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
tSCYC
VOH
SCK
VOH
VOL
tSOVHI
tSLOVI
VOH
VOL
SOT
VOH
VOL
tSHIXI
tIVSHI
VIH
VIL
SIN
VIH
VIL
Master mode
tR
SCK
tF
tSHSL
VIH
VIH
VIL
tSLSH
VIL
VIL
tSLOVE
VOH
VOL
SOT
VOH
VOL
tIVSHE
tSHIXE
VIH
VIL
SIN
VIH
VIL
Slave mode
 UART external clock input (EXT = 1)
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Serial clock L pulse width
Serial clock H pulse width
SCK falling time
SCK rising time
tSLSH
tSHSL
tF
tR
CL = 30 pF
Min
Max
tCYCP + 10
tCYCP + 10
-
5
5
Unit Remarks
ns
ns
ns
ns
tF
tR
t
t
SHSL
SCK
V IL
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Value
Symbol Conditions
V
IH
SLSH
V
IH
V IL
VIL
V
IH
93
D a t a S h e e t
(10) External Input Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Input pulse width
Symbol
tINH,
tINL
Value
Unit
Min
Max
Pin name
Conditions
ADTG
-
2tCYCP*1
-
ns
INTxx,
NMIX
*2
2tCYCP + 100*1
-
ns
*3
500
-
ns
WKUPx
*4
600
-
ns
Remarks
A/D converter
trigger input
External interrupt
NMI
Deep standby
wake up
*1 : tCYCP indicates the APB bus clock cycle time.
About the APB bus number which the Multi-function Timer is connected to, see Block Diagram in this
data sheet.
*2: When in Run mode, in Sleep mode.
*3: When in Stop mode, in Timer mode.
*4: When in Deep Standby RTC mode, in Deep Standby Stop mode.
94
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
2
(11) I C Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Standard-mode
Min
Max
Fast-mode
Unit Remarks
Min
Max
SCL clock frequency
fSCL
0
100
0
400 kHz
(Repeated) START
condition hold time
tHDSTA
4.0
0.6
μs
SDA ↓ → SCL ↓
SCL clock L width
tLOW
4.7
1.3
μs
SCL clock H width
tHIGH
4.0
0.6
μs
(Repeated) START
condition setup time
tSUSTA
4.7
0.6
μs
SCL ↑ → SDA ↓
CL = 30 pF,
R = (Vp/IOL)*1
Data hold time
tHDDAT
0
3.45*2
0
0.9*3 μs
SCL ↓ → SDA ↓ ↑
Data setup time
tSUDAT
250
100
ns
SDA ↓ ↑ → SCL ↑
STOP condition setup time
tSUSTO
4.0
0.6
μs
SCL ↑ → SDA ↑
Bus free time between
STOP condition and
tBUF
4.7
1.3
μs
START condition
Noise filter
tSP
2 tCYCP*4
2 tCYCP*4
ns
*1: R and C represent the pull-up resistor and load capacitance of the SCL and SDA lines, respectively.
Vp indicates the power supply voltage of the pull-up resistor and IOL indicates VOL guaranteed current.
*2: The maximum tHDDAT must satisfy that it does not extend at least L period (tLOW) of device's SCL signal.
*3: A Fast-mode I2C bus device can be used on a Standard-mode I2C bus system as long as the device satisfies
the requirement of tSUDAT ≥ 250 ns.
*4: tCYCP is the APB bus clock cycle time.
About the APB bus number that I2C is connected to, see Block Diagram in this data sheet.
To use Standard-mode, set the APB bus clock at 2 MHz or more.
To use Fast-mode, set the APB bus clock at 8 MHz or more.
SDA
SCL
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
95
D a t a S h e e t
(12) ETM Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Data hold
TRACECLK
frequency
Pin name
Conditions
tETMH
TRACECLK,
TRACED[3:0]
VCC ≥ 2.7 V
2
11
VCC < 2.7 V
2
15
VCC ≥ 2.7 V
-
40
MHz
VCC < 2.7 V
-
20
MHz
VCC ≥ 2.7 V
25
-
ns
VCC < 2.7 V
50
-
ns
1/ tTRACE
TRACECLK
TRACECLK
clock cycle
Value
Unit
Min Max
Symbol
tTRACE
Remarks
ns
Note: When the external load capacitance CL = 30 pF.
HCLK
TRACECLK
TRACED[3:0]
96
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
(13) JTAG Timing
(VCC = 1.65V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol Pin name
Conditions
TCK,
TMS, TDI
TCK,
TMS, TDI
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
VCC < 2.7 V
VCC ≥ 2.7 V
TMS, TDI setup
time
tJTAGS
TMS, TDI hold time
tJTAGH
TDO delay time
tJTAGD
TCK,
TDO
VCC < 2.7 V
Note: When the external load capacitance CL = 30 pF.
Value
Min
Max
Unit
15
-
ns
15
-
ns
-
25
-
45
Remarks
ns
TCK
TMS/TDI
TDO
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
97
D a t a S h e e t
6. 12-bit A/D Converter
 Electrical Characteristics for the A/D Converter
(VCC = AVCC = 1.65V to 3.6V, VSS = AVSS = 0V, TA = - 40°C to + 85°C)
Value
Typ
Max
-
±2
12
± 4.5
bit
LSB
-
-
± 2.2
± 2.5
LSB
VZT
ANxx
-
±6
± 15
mV
VFST
ANxx
-
Parameter
Symbol
Pin
name
Min
Resolution
Integral Nonlinearity
Differential
Nonlinearity
Zero transition voltage
Full-scale transition
voltage
-
-
-
Conversion time
-
-
Sampling time*2
tS
-
tCCK
-
tSTT
-
-
AVCC
-
AVRH
Compare clock
cycle*3
AVRH ± 6 AVRH ± 15
2.0*1
4.0*1
10*1
0.6
1.2
3.0
100
200
500
-
Unit
mV
-
μs
10
us
-
1000
ns
-
-
1.0
μs
-
0.27
0.03
0.42
10
mA
μA
-
0.72
1.29
mA
-
0.02
2.6
μA
pF
LSB
μA
State transition time to
operation permission
Power supply current
(analog + digital)
Reference power
supply current
(between AVRH to
AVSS)
Analog input capacity
CAIN
-
-
-
Analog input resistor
RAIN
-
-
-
Interchannel disparity
Analog port input
current
Analog input voltage
-
-
-
-
9.4
2.2
5.5
10.5
4
-
ANxx
-
-
5
-
ANxx
Remarks
kΩ
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65V< AVCC < 1.8V
AVCC ≥ 2.7 V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
A/D 1unit operation
When A/D stops
A/D 1unit operation
AVRH=3.6 V
When A/D stops
AVCC ≥ 2.7V
1.8 V< AVCC < 2.7 V
1.65 V< AVCC < 1.8 V
AVSS
AVRH
V
2.7
AVCC ≥ 2.7 V
Reference voltage
AVRH
AVCC
V
AVCC
AVCC < 2.7 V
*1: The conversion time is the value of sampling time (tS) + compare time (tC).
The condition of the minimum conversion time is the following.
AVCC ≥ 2.7 V, HCLK=40 MHz
sampling time: 0.6 μs, compare time: 1.4 μs
1.8 V < AVCC < 2.7 V, HCLK=40 MHz
sampling time: 1.2 μs, compare time: 2.8 μs
1.65 V < AVCC < 1.8 V, HCLK=40 MHz sampling time: 3 μs, compare time: 7 μs
Ensure that it satisfies the value of the sampling time (tS) and compare clock cycle (tCCK).
For setting of the sampling time and the compare clock cycle, see Chapter 1-1: A/D Converter in FM3
Family Peripheral Manual Analog Macro Port.
The register setting of the A/D Converter are reflected in the operation according to the APB bus clock
timing.
The sampling clock and compare clock is generated from the Base clock (HCLK).
About the APB bus number which the A/D Converter is connected to, see Block Diagram in this data
sheet.
*2: A necessary sampling time changes by external impedance.
Ensure that it set the sampling time to satisfy (Equation 1).
*3: The compare time (tC) is the value of (Equation 2).
98
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D a t a S h e e t
REXT
ANxx
Analog input pin
Comparator
RAIN
Analog
signal source
CAIN
(Equation 1) tS ≥ ( RAIN + REXT ) × CAIN × 9
tS:
RAIN:
CAIN:
REXT:
Sampling time[ns]
input resistor of A/D[kΩ] = 2.2 kΩ at 2.7 V < AVCC < 3.6 V
input resistor of A/D[kΩ] = 5.5 kΩ at 1.8 V < AVCC < 2.7 V
input resistor of A/D[kΩ] = 10.5 kΩ at 1.65 V < AVCC < 1.8 V
input capacity of A/D[pF] = 9.4 pF at 1.65 V < AVCC < 3.6 V
Output impedance of external circuit[kΩ]
(Equation 2) tC = tCCK × 14
tC:
tCCK:
Compare time
Compare clock cycle
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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 Definition of 12-bit A/D Converter Terms
 Resolution
 Integral Nonlinearity
 Differential Nonlinearity
: Analog variation that is recognized by an A/D converter.
: Deviation of the line between the zero-transition point
(0b000000000000 ←→ 0b000000000001) and the full-scale transition
point (0b111111111110 ←→ 0b111111111111) from the actual conversion
characteristics.
: Deviation from the ideal value of the input voltage that is required to
change the output code by 1 LSB.
Integral Nonlinearity
Differential Nonlinearity
0xFFF
Actual conversion
characteristics
0xFFE
0x(N+1)
{1 LSB(N-1) + VZT}
VFST
VNT
0x004
(Actuallymeasured
value)
(Actually-measured
value)
0x003
Digital output
Digital output
0xFFD
0xN
Actual conversion
characteristics
Ideal characteristics
V(N+1)T
0x(N-1)
(Actually-measured
value)
Actual conversion
characteristics
Ideal characteristics
0x002
VNT
(Actually-measured
value)
0x(N-2)
0x001
VZT (Actually-measured value)
AVSS
Actual conversion characteristics
AVRH
AVSS
AVRH
Analog input
Linearity error of digital output N =
Analog input
VNT - {1LSB × (N - 1) + VZT}
1LSB
Differential linearity error of digital output N =
1LSB =
V(N + 1) T - VNT
1LSB
[LSB]
- 1 [LSB]
VFST - VZT
4094
N:
A/D converter digital output value.
Voltage at which the digital output changes from 0x000 to 0x001.
VFST: Voltage at which the digital output changes from 0xFFE to 0xFFF.
VNT: Voltage at which the digital output changes from 0x(N − 1) to 0xN.
VZT:
100
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MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
7. USB Characteristics
(VCC = 3.0V to 3.6V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Input H level voltage
Input L level voltage
Input
charac- Differential input
teristics sensitivity
Different common mode
range
Pin
Conditions
name
Value
Min
Max
Unit Remarks
VIH
-
2.0
VCC + 0.3
V
*1
VIL
-
VSS - 0.3
0.8
V
*1
VDI
-
0.2
-
V
*2
VCM
-
0.8
2.5
V
*2
2.8
3.6
V
*3
0
0.3
V
*3
Output H level voltage
VOH
Output L level voltage
VOL
External
pull-down
resistor =
15kΩ
External
UDP0,
pull-up
UDM0 resistor =
1.5kΩ
Full-Speed
Full-Speed
Minimum differential input
sensitivity [V]
Output Crossover voltage
VCRS
1.3
2.0
V *4
characRising time
tFR
4
20
ns *5
teristics
Falling time
tFF
4
20
ns *5
Rising/falling time
tFRFM
Full-Speed
90
111.11
% *5
matching
Output impedance
ZDRV
Full-Speed
28
44
Ω *6
Rising time
tLR
Low-Speed
75
300
ns *7
Falling time
tLF
Low-Speed
75
300
ns *7
Rising/falling time
tLRFM
Low-Speed
80
125
% *7
matching
*1: The switching threshold voltage of Single-End-Receiver of USB I/O buffer is set as within VIL (Max) = 0.8V,
VIH (Min) = 2.0 V (TTL input standard).
There are some hysteresis to lower noise sensitivity.
*2: Use the differential-Receiver to receive the USB differential data signal.
The Differential-Receiver has 200 mV of differential input sensitivity when the differential data input is
within 0.8 V to 2.5 V to the local ground reference level.
Above voltage range is the common mode input voltage range.
Common mode input voltage [V]
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D a t a S h e e t
*3: The output drive capability of the driver is below 0.3 V at Low-State (VOL) (to 3.6 V and 1.5 kΩ load), and
2.8 V or above (to ground and 15 kΩ load) at High-State (VOH).
*4: The cross voltage of the external differential output signal (D + /D − ) of USB I/O buffer is within 1.3 V to
2.0 V.
VCRS specified range
*5: They indicate the rising time (Trise) and falling time (Tfall) of the full-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
For full-speed buffer, Tr/Tf ratio is regulated as within ± 10% to minimize RFI emission.
Rising time
102
CONFIDENTIAL
Falling time
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
*6: USB Full-speed connection is performed via twist pair cable shield with 90Ω ± 15% characteristic
impedance (Differential Mode).
USB standard defines that output impedance of USB driver must be in range from 28 Ω to 44 Ω. So, discrete
series resistor (Rs) addition is defined in order to satisfy the above definition and keep balance.
When using this USB I/O, use it with 25 Ω to 30 Ω (recommendation value 27 Ω) Series resistor Rs.
28Ω to 44Ω Equiv. Imped.
28Ω to 44Ω Equiv. Imped.
Mount it as external resistor.
Rs series resistor 25Ω to 30Ω
Series resistor of 27Ω (recommendation value) must be added.
And, use resistance with an uncertainty of 5% by E24 sequence.
*7: They indicate the rising time (Trise) and falling time (Tfall) of the low-speed differential data signal.
They are defined by the time between 10% and 90% of the output signal voltage.
Rising time
Falling time
See Figure  Low-Speed Load (Compliance Load) for conditions of the external load.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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D a t a S h e e t
 Low-Speed Load (Upstream Port Load) - Reference 1
CL = 50pF to 150pF
CL = 50pF to 150pF
 Low-Speed Load (Downstream Port Load) - Reference 2
CL =
200pF to 600pF
CL =
200pF to 600pF
 Low-Speed Load (Compliance Load)
CL = 200pF to 450pF
CL = 200pF to 450pF
104
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MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
8. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
(TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Min
Value
Typ
Max
Unit
Remarks
Detected voltage
VDL
1.38
1.50
1.60
V When voltage drops
SVHR*1 = 00000
Released voltage
VDH
1.43
1.55
1.65
V When voltage rises
Detected voltage
VDL
1.43
1.55
1.65
V When voltage drops
SVHR*1 = 00001
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.47
1.60
1.73
V When voltage drops
SVHR*1 = 00010
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.52
1.65
1.78
V When voltage drops
1
SVHR* = 00011
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.56
1.70
1.84
V When voltage drops
SVHR*1 = 00100
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.61
1.75
1.89
V When voltage drops
SVHR*1 = 00101
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.66
1.80
1.94
V When voltage drops
SVHR*1 = 00110
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.70
1.85
2.00
V When voltage drops
1
SVHR* = 00111
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.75
1.90
2.05
V When voltage drops
SVHR*1 = 01000
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.79
1.95
2.11
V When voltage drops
SVHR*1 = 01001
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.84
2.00
2.16
V When voltage drops
SVHR*1 = 01010
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
1.89
2.05
2.21
V When voltage drops
1
SVHR* = 01011
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.30
2.50
2.70
V When voltage drops
SVHR*1 = 01100
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.39
2.60
2.81
V When voltage drops
SVHR*1 = 01101
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.48
2.70
2.92
V When voltage drops
SVHR*1 = 01110
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.58
2.80
3.02
V When voltage drops
1
SVHR* = 01111
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.67
2.90
3.13
V When voltage drops
SVHR*1 = 10000
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.76
3.00
3.24
V When voltage drops
SVHR*1 = 10001
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.85
3.10
3.35
V When voltage drops
SVHR*1 = 10010
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
Detected voltage
VDL
2.94
3.20
3.46
V When voltage drops
1
SVHR* = 10011
Released voltage
VDH
Same as SVHR = 00000 value V When voltage rises
LVD stabilization
5200 ×
tLVDW
μs
wait time
tCYCP*2
LVD detection
tLVDDL
200
μs
delay time
*1: The SVHR bit of Low-Voltage Detection Voltage Control Register (LVD_CTL) is initialized to 00000 by
Low-Voltage Detection Reset.
*2: tCYCP indicates the APB2 bus clock cycle time.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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D a t a S h e e t
(2) Interrupt of Low-Voltage Detection
(TA = - 40°C to + 85°C)
Parameter
Symbol
Conditions
Detected voltage
VDL
SVHI = 00100
Released voltage
VDH
Detected voltage
VDL
SVHI = 00101
Released voltage
VDH
Detected voltage
VDL
SVHI = 00110
Released voltage
VDH
Detected voltage
VDL
SVHI = 00111
Released voltage
VDH
Detected voltage
VDL
SVHI = 01000
Released voltage
VDH
Detected voltage
VDL
SVHI = 01001
Released voltage
VDH
Detected voltage
VDL
SVHI = 01010
Released voltage
VDH
Detected voltage
VDL
SVHI = 01011
Released voltage
VDH
Detected voltage
VDL
SVHI = 01100
Released voltage
VDH
Detected voltage
VDL
SVHI = 01101
Released voltage
VDH
Detected voltage
VDL
SVHI = 01110
Released voltage
VDH
Detected voltage
VDL
SVHI = 01111
Released voltage
VDH
Detected voltage
VDL
SVHI = 10000
Released voltage
VDH
Detected voltage
VDL
SVHI = 10001
Released voltage
VDH
Detected voltage
VDL
SVHI = 10010
Released voltage
VDH
Detected voltage
VDL
SVHI = 10011
Released voltage
VDH
LVD stabilization
tLVDW
wait time
LVD detection delay
tLVDDL
time
*: tCYCP indicates the APB2 bus clock cycle time.
106
CONFIDENTIAL
Min
Value
Typ Max
1.56
1.61
1.61
1.66
1.66
1.70
1.70
1.75
1.75
1.79
1.79
1.84
1.84
1.89
1.89
1.93
2.30
2.39
2.39
2.48
2.48
2.58
2.58
2.67
2.67
2.76
2.76
2.85
2.85
2.94
2.94
3.04
1.70
1.75
1.75
1.80
1.80
1.85
1.85
1.90
1.90
1.95
1.95
2.00
2.00
2.05
2.05
2.10
2.50
2.60
2.60
2.70
2.70
2.80
2.80
2.90
2.90
3.00
3.00
3.10
3.10
3.20
3.20
3.30
-
-
-
-
1.84
1.89
1.89
1.94
1.94
2.00
2.00
2.05
2.05
2.11
2.11
2.16
2.16
2.21
2.21
2.27
2.70
2.81
2.81
2.92
2.92
3.02
3.02
3.13
3.13
3.24
3.24
3.35
3.35
3.46
3.46
3.56
5200 ×
tCYCP*
200
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Remarks
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
When voltage drops
When voltage rises
μs
μs
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
9. Flash Memory Write/Erase Characteristics
(1) Write / Erase time
(VCC = 1.65V to 3.6V, TA = - 40°C to + 85°C)
Parameter
Sector erase
time
Large Sector
Value
Typ*
Max*
1.1
2.7
Unit
s
Small Sector
0.3
Half word (16-bit)
write time
0.9
Remarks
Includes write time prior to internal
erase
Not including system-level overhead
time
Includes write time prior to internal
Chip erase time
6.8
18
s
erase
*: The typical value is immediately after shipment, the maximam value is guarantee value under 100,000 cycle
of erase/write.
30
528
μs
(2) Write cycles and data hold time
Erase/write cycles (cycle)
Data hold time (year)
1,000
20*
10,000
*: At average + 85C
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Remarks
10*
107
D a t a S h e e t
10. Return Time from Low-Power Consumption Mode
(1) Return Factor: Interrupt/WKUP
The return time from Low-Power consumption mode is indicated as follows. It is from receiving the
return factor to starting the program operation.
・ Return Count Time
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Max*
Low-speed CR Timer mode
tICNT
Unit
40
80
μs
350
700
μs
690
880
μs
523
μs
603
μs
μs
RTC mode,
278
Stop mode
318
Deep Standby RTC mode
Deep Standby Stop mode
278
*: The maximum value depends on the accuracy of built-in CR.
Remarks
μs
tCYCC
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Sub Timer mode
Value
Typ
523
When RAM is off
When RAM is on
・ Operation example of return from Low-Power consumption mode (by external interrupt*)
External
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: External interrupt is set to detecting fall edge.
108
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MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
・ Operation example of return from Low-Power consumption mode (by internal resource interrupt*)
Internal
resource
interrupt
Interrupt factor
accept
Active
tICNT
CPU
Operation
Interrupt factor
clear by CPU
Start
*: Internal resource interrupt is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・ The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・ When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3
Family Peripheral Manual.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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109
D a t a S h e e t
(2) Return Factor: Reset
The return time from Low-Power consumption mode is indicated as follows. It is from releasing reset to
starting the program operation.
・ Return Count Time
(VCC = 1.65V to 3.6V, VDDI = 1.1V to 1.3V, VSS = 0V, TA = - 40°C to + 85°C)
Parameter
Symbol
Value
Unit
Typ
Max*
148
263
μs
148
263
μs
258
483
μs
Sub Timer mode
322
516
μs
RTC/Stop mode
278
523
μs
603
523
μs
μs
Sleep mode
High-speed CR Timer mode,
Main Timer mode,
PLL Timer mode
Low-speed CR Timer mode
tRCNT
318
Deep Standby RTC mode
Deep Standby Stop mode
278
*: The maximum value depends on the accuracy of built-in CR.
Remarks
When RAM is off
When RAM is on
・ Operation example of return from Low-Power consumption mode (by INITX)
INITX
Internal reset
Reset active
Release
tRCNT
CPU
Operation
110
CONFIDENTIAL
Start
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
・ Operation example of return from low power consumption mode (by internal resource reset*)
Internal
resource
reset
Internal reset
Reset active
Release
tRCNT
CPU
Operation
Start
*: Internal resource reset is not included in return factor by the kind of Low-Power consumption mode.
Notes:
・ The return factor is different in each Low-Power consumption modes.
See Chapter 6: Low Power Consumption Mode and Operations of Standby Modes in FM3 Family
Peripheral Manual.
・ When interrupt recoveries, the operation mode that CPU recoveries depend on the state before the
Low-Power consumption mode transition. See Chapter 6: Low Power Consumption Mode in FM3
Family Peripheral Manual.
・ The time during the power-on reset/low-voltage detection reset is excluded. See (6) Power-on
Reset Timing in 4. AC Characteristics in Electrical Characteristics for the detail on the time
during the power-on reset/low-voltage detection reset.
・ When in recovery from reset, CPU changes to the High-speed CR Run mode. When using the
main clock or the PLL clock, it is necessary to add the main clock oscillation stabilization wait
time or the Main PLL clock stabilization wait time.
・ The internal resource reset means the watchdog reset and the CSV reset.
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
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D a t a S h e e t
 Ordering Information
Part number
On-chip
Flash
memory
On-chip
SRAM
MB9AFB41LBPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42LBPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44LBPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFB41LBPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42LBPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44LBPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFB41LBQN-G-AVE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42LBQN-G-AVE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44LBQN-G-AVE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFB41MBPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42MBPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44MBPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFB41MBPMC1-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42MBPMC1-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44MBPMC1-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFB41MBBGL-GE1
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42MBBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44MBBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFB41NBPMC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42NBPMC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44NBPMC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
112
CONFIDENTIAL
Package
Packing
Plastic  LQFP 64-pin
(0.5mm pitch),
(FPT-64P-M38)
Plastic  LQFP 64-pin
(0.65mm pitch),
(FPT-64P-M39)
Plastic  QFN 64-pin
(0.5mm pitch),
(LCC-64P-M24)
Plastic  LQFP 80-pin
(0.5mm pitch),
(FPT-80P-M37)
Tray
Plastic  LQFP 80-pin
(0.65mm pitch),
(FPT-80P-M40)
Plastic  PFBGA 96-pin
(0.5mm pitch),
(BGA-96P-M07)
Plastic  LQFP 100-pin
(0.5mm pitch),
(FPT-100P-M23)
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
On-chip
Flash
memory
On-chip
SRAM
MB9AFB41NBPQC-G-JNE2
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42NBPQC-G-JNE2
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44NBPQC-G-JNE2
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
MB9AFB41NBBGL-GE1
Main: 64 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB42NBBGL-GE1
Main: 128 Kbyte
Work: 32 Kbyte
16 Kbyte
MB9AFB44NBBGL-GE1
Main: 256 Kbyte
Work: 32 Kbyte
32 Kbyte
Part number
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Package
Packing
Plastic  QFP 100-pin
(0.65mm pitch),
(FPT-100P-M36)
Tray
Plastic  PFBGA 112-pin
(0.8mm pitch),
(BGA-112P-M04)
113
D a t a S h e e t
 Package Dimensions
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65 g
(FPT-100P-M23)
100-pin plastic LQFP
(FPT-100P-M23)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
1.50 +0.20
- 0.10
(.059+.008
-.004)
(Mounting height)
INDEX
100
26
"A"
1
C
0.22±0.05
(.009±.002)
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F100034S-c-3-4
114
CONFIDENTIAL
0.60±0.15
(.024±.006)
25
0.50(.020)
0°~8°
0.50±0.20
(.020±.008)
M
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
0.145±0.055
(.006±.002)
Dimensions in mm (inches).
Note:The values in parentheses are reference values.
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
100-pin plastic QFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference)
P-QFP100-14 × 20-0.65
(FPT-100P-M36)
100-pin plastic QFP
(FPT-100P-M36)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
23.90±0.40(.941±.016)
* 20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90± 0.40
(.705±.016)
*14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
0.32 ± 0.05
(.013±.002)
0.13(.005)
"A"
C
2011 FUJITSU SEMICONDUCTOR LIMITED HMbF100-36Sc-1-1
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
0.25(.010)
+0.35
3.00 –0.20
+.014
.118 –.008
(Mounting height)
0~8°
31
M
0.17 ± 0.06
(.007 ±. 002)
0.80 ± 0.20
(.031 ±. 008)
0.88 ± 0.15
(.035 ±. 006)
0.25 ± 0.20
(.010 ±. 008)
(Stand off)
Dimensions in mm (inches).
Note: The valuesin parentheses are reference values.
115
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-80P-M37)
80-pin plastic LQFP
(FPT-80P-M37)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
14.00± 0.20(.551 ± .008)SQ
*12.00± 0.10(.472 ± .004)SQ
60
0.145± 0.055
(.006 ± .002)
41
Details of "A" part
61
40
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
0.08(.003)
INDEX
80
0.50 ± 0.20
(.020 ± .008)
0.60 ± 0.15
(.024 ± .006)
0.10 ± 0.05
(.004 ± .002)
(Stand off)
21
"A"
1
20
0.50(.020)
0.22± 0.05
(.009± .002)
C
0.08(.003)
2009-2010 FUJITSU SEMICONDUCTOR LIMITED F80037S-c-1-2
116
CONFIDENTIAL
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
80-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
14.00 mm × 14.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.60 mm Max.
Code
(Reference)
P-LQFP80-14 × 14-0.65
(FPT-80P-M40)
80-pin plastic LQFP
(FPT-80P-M40)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include
16.00±0.20(.630±.008)SQ
*14.00±0.10(.551±.004)SQ
60
0.145±0.055
(.006±.002)
41
Details of "A" part
40
61
1.50±0.10
(.059±.004)
0.25(.010)
0.10(.004)
0˚~7˚
INDEX
0.50±0.20
(.020±.008)
21
80
0.65(.026)
C
0.60±0.15
(.024±.006)
20
1
0.32±0.06
(.013±.002)
0.13(.005)
M
2012 FUJITSU SEMICONDUCTOR LIMITED HMbF80-40Sc-1-1
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
0.10±0.05
(.004±.002)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
117
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
10.00 mm × 10.00 mm
Lead shape
Gullwing
Lead bend
direction
Normal bend
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.32 g
(FPT-64P-M38)
64-pin plastic LQFP
(FPT-64P-M38)
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
12.00±0.20(.472±.008)SQ
*10.00±0.10(.394±.004)SQ
48
0.145 ± 0.055
(.006 ± .002)
33
49
Details of "A" part
32
0.08(.003)
+0.20
1.50 –0.10
(Mounting height)
+.008
.059 –.004
0.25(.010)
0~8°
INDEX
64
17
1
0.22±0.05
(.009±.002)
0.08(.003)
2010 FUJITSU SEMICONDUCTOR LIMITED F64038S-c-1-2
118
CONFIDENTIAL
0.10 ± 0.10
(.004±.004)
(Stand off)
"A"
16
0.50(.020)
C
0.50±0.20
(.020±.008)
0.60 ± 0.15
(.024±.006)
M
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
64-pin plastic LQFP
Lead pitch
0.65 mm
Package width ×
package length
12.00 mm × 12.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.47 g
(FPT-64P-M39)
64-pin plastic LQFP
(FPT-64P-M39)
Note 1) Pins width and pins thickness include plating thickness.
14.00±0.20(.551±.008)SQ
12.00±0.10(.472±.004)SQ
48
0.145±0.055
(.006±.002)
33
Details of "A" part
32
49
+0.20
1.50 –0.10
+.008
.059 –.004
0.10(.004)
INDEX
1
16
0.65(.026)
C
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
17
64
0.32±0.05
(.013±.002)
CONFIDENTIAL
0.10±0.10
(.004±.004)
0.25(.010)BSC
"A"
0.13(.005)
M
2010-2011 FUJITSU SEMICONDUCTOR LIMITED HMbF64-39Sc-2-2
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
0~8˚
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
119
D a t a S h e e t
64-pin plastic QFN
Lead pitch
0.50 mm
Package width ×
package length
9.00 mm × 9.00 mm
Sealing method
Plastic mold
Mounting height
0.90 mm MAX
Weight
-
(LCC-64P-M24)
64-pin plastic QFN
(LCC-64P-M24)
9.00±0.10
(.354±.004)
6.00±0.10
(.236±.004)
9.00±0.10
(.354±.004)
0.25±0.05
(.010±.002)
6.00±0.10
(.236±.004)
INDEX AREA
0.45 (.018)
1PIN ID
(0.20R (.008R))
0.85±0.05
(.033±.002)
0.05 (.002) MAX
C
CONFIDENTIAL
0.40±0.05
(.016±.002)
(0.20 (.008))
2011 FUJITSU SEMICONDUCTOR LIMITED HMbC64-24Sc-2-1
120
0.50 (.020)
(TYP)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
112-ball plastic PFBGA
Ball pitch
0.80 mm
Package width ×
package length
10.00 × 10.00 mm
Lead shape
Soldering ball
Sealing method
Plastic mold
Ball size
Ф 0.45 mm
Mounting height
1.45 mm Max.
Weight
0.22 g
(BGA-112P-M04)
112-ball plastic PFBGA
(BGA-112P-M04)
10.00±0.10(.394±.004)
0.20(.008) S B
0.80(.031)
REF
B
11
10
9
8
7
6
5
4
3
2
0.80(.031)
REF
A
10.00±0.10
(.394±.004)
1
L K J H G F
(INDEX AREA)
0.35±0.10
(.014±.004)
(Stand off)
0.20(.008) S A
1.25±0.20
(.049±.008)
(Seated height)
ED C B A
INDEX
112-Ф0.45±010
(112-Ф0.18±.004)
Ф0.08(.003) M S A B
S
0.10(.004) S
C
2003-2010 FUJITSU SEMICONDUCTOR LIMITED B112004S-c-2-3
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
121
D a t a S h e e t
96-pin plastic FBGA
Lead pitch
0.5 mm
Package width ×
package length
6.00 mm × 6.00 mm
Lead shape
Ball
Sealing method
Plastic mold
Mounting height
1.30 mm MAX
Weight
0.08 g
(BGA-96P-M07)
96-pin plastic FBGA
(BGA-96P-M07)
6.00±0.10(.236±.004)
5.00(.197)
REF
B
0.20(.008) S B
0.50
(.020)
TYP
11
10
9
8
A
7
5.00(.197)
REF
6.00±0.10
(.236±.004)
6
5
0.50(.020)
TYP
4
3
2
1
L
K
J
H G F E D C B A
(INDEX AREA)
INDEX
0.20(.008) S A
96-ø0.30±0.10
(96-ø.012±.004)
ø0.05(.002)
M
S A B
S
0.08(.003) S
C
2012 FUJITSU SEMICONDUCTOR LIMITED B96007S-c-1-1
122
CONFIDENTIAL
1.15±0.15
(Seated height)
(.045±.006)
0.25±0.10
(Stand off)
(.010±.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
 Major Changes
Page
Section
Change Results
Revision 2.0
2
6
7
52
57
62
70
74
78, 79
80
85, 87,
89, 91
94
97
FEATURE
 On-chip Memories
 USB Interface
 Unique ID
PRODUCT LINEUP
 Function
HANDLING DEVICES
MEMORY MAP
 Memory Map (2)
PIN STATUS IN EACH CPU STATE
 List of Pin Status
ELECTRICAL CHARACTERISTICS
3.DC Characteristics
(1) Current rating
5.AC Characteristics
(3) Built-in CR Oscillation Characteristics
 Built-in high-speed CR
(7) External Bus Timing
 Separate Bus Access Asynchronous
SRAM Mode
 Separate Bus Access Synchronous SRAM
Mode
(9) CSIO Timing
(11) I2C Timing
6. 12-bit A/D Converter
 Electrical Characteristics for the A/D
Converter
99
 Definition of 12-bit A/D Converter Terms
104
8. Low-Voltage Detection Characteristics
(1) Low-Voltage Detection Reset
105
(2) Interrupt of Low-Voltage Detection
Revision 2.1
Revision 3.0
-
-
-
-
2
3
7
55
56
68
69,70
92
94
 FEATURES
•External Bus Interface
•Multi-function Serial Interface
PRODUCT LINEUP
•Function
BLOCK DIAGRAM
MEMORY MAP
•Memory Map (1)
 ELECTRICAL CHARACTERISTICS
2.Recommended Operating Conditions
3.DC Characteristics
(1)Current rating
(9)CSIO Timing
•Synchronous serial (SPI=1, SCINV=1)
(9) CSIO Timing
• External clock(EXT=1):asyntironous only
(12)I2C Timing
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
Revised the descriptions of [Flash memory].
Revised the descriptions of [USB function].
Added the descriptions of "Unique ID".
Added the descriptions.
Revised the Pin status type of "I".
 Revised the descriptions of Power supply current.
 Added the "Flash memory write/erase current".
 Added the footnote.
Revised the table and the footnote.
Revised the table and the figure.
 Revised the title to "CSIO Timing".
 Revised the note.
Revised the footnote.
• Revised the parameter.
• Revised the symbol.
• Corrected the value.
• Revised the parameter.
• Revised the symbol.
• Corrected "Conditions" and "Value" in the table.
• Added the Item.
• Added the footnote.
Added the Item.
Company name and layout design change
Corrected the Series name.
MB9AB40NA Series → MB9AB40NB Series
Corrected the Product name as follows.
MB9AFB44LB, MB9AFB42LB, MB9AFB41LB
MB9AFB44MB, MB9AFB42MB, MB9AFB41MB
MB9AFB44NB, MB9AFB42NB, MB9AFB41NB
Added the Item.
• Maximum area size : Up to 256 Mbytes
Corrected the description of "I2C"
Added the footnote
Corrected the figure
Corrected the address "External Device Area"
Add the footnote
•Corrected the Condition
•Delete the minmun value
•Corrected the remarks
•Add the footnote
Corrected the figure of "MS bit=1"
Corrected the figure
Corrected the description as follows.
•Typical mode → Standard-mode
•High-speed mode→ Fast-mode
123
D a t a S h e e t
Page
97
Section
5.12-bit A/D Converter
•Electrical Characteristics for
the A/D Converter
107
ORDERING INFORMATON
Revision 4.0
Features
2
USB Interface
Memory Map
57
· Memory map(2)
Electrical Characteristics
69 - 71
3. DC Characteristics
(1) Current rating
Electrical Characteristics
72
3. DC Characteristics
(2) Pin Characteristics
Electrical Characteristics
5. AC Characteristics
76
(4-1) Operating Conditions of Main and USB
PLL
(4-2) Operating Conditions of Main PLL
Electrical Characteristics
77
5. AC Characteristics
(6) Power-on Reset Timing
Electrical Characteristics
86 - 93
5. AC Characteristics
(9) CSIO/UART Timing
98
108 - 111
112, 113
124
CONFIDENTIAL
Electrical Characteristics
6. 12bit A/D Converter
Electrical Characteristics
10. Return Time from Low-Power Consumption
Mode
Ordering Information
Change Results
•Corrected the terminal name
AN00 ~ AN23 → ANxx
•Corrected the minmum value of "Sampling time"
•Corrected the max and min value of "State transition time to
oprerationpermission"
•Corrected the footnote
Corrected the "Part number"
Added the description of PLL for USB
Added the summary of Flash memory sector and the note
· Changed the table format
· Added Main Timer mode current
· Moved A/D Converter Current
Added input leak current of CEC pin at power off.
Added the figure of Main PLL connection and USB PLL connection
· Added Time until releasing Power-on reset
· Changed the figure of timing
· Modified from UART Timing to CSIO/UART Timing
· Changed from Internal shift clock operation to Master mode
· Changed from External shift clock operation to Slave mode
· Added the typical value of Integral Nonlinearity, Differential
Nonlinearity, Zero transition voltage and Full-scale transition voltage
· Added Conversion time at AVcc < 2.7V
Added Return Time from Low-Power Consumption Mode
Changed notation of part number
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015
D a t a S h e e t
June 10, 2015, MB9AB40NB_DS706-00034-4v0-E
CONFIDENTIAL
125
D a t a S h e e t
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use,
including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not
designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless
extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury,
severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use
where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not
be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the
products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss
from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire
protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in
this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and
Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the
prior authorization by the respective government entity will be required for export of those products.
Trademarks and Notice
The contents of this document are subject to change without notice. This document may contain information on a
Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any
product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to
its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party
rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind
arising out of the use of the information in this document.
Copyright © 2012-2015 Cypress All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® EclipseTM,
ORNANDTM, Easy DesignSimTM, TraveoTM and combinations thereof, are trademarks and registered trademarks of
Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be
trademarks of their respective owners.
126
CONFIDENTIAL
MB9AB40NB_DS706-00034-4v0-E, June 10, 2015