Migration from Micron® M25PE and M25PX Series to the Spansion® S25FL-K SPI Flash Family Application Note 1. Introduction This application note provides conversion guidelines for migrating from the Micron M25PE or M25PX SPI series to the Spansion S25FL-K SPI Flash Family. The application note is based on information available to date from data sheets and other applications notes publicly available from Spansion and Micron. Please refer also to the latest relevant specifications. The document discusses the specification differences when migrating from M25PE and M25PX to S25FL-K. 2. Feature Comparison Micron M25PE and M25PX products are well suited for migrations to Spansion FL-K products. Some of the reasons are compatible pinouts, packages, command set, and 4/64 kB block/sector structure. Spansion products support Dual I/O and Quad I/O modes, while Micron only has Dual I/O mode on the newer M25PX Family. The major differences are the Micron block protection scheme and different OTP handling, which requires some SW changes when features are in use. Another difference in M25PE Devices is the Page write feature, which makes a software change necessary when it is used. 2.1 Packaging — All Densities The most common packages for Micron and Spansion are the SOIC packages. The pinout is identical on the PX Family, while the PE Series has Reset functionality instead of a HOLD function. FL-K devices are not impacted in functionality when Reset is connected to the HOLD pin allowing a direct replacement without PCB redesign. Figure 2.1 shows those SOIC packages and pinouts, please refer to the data sheets for detailed package information. Figure 2.1 SOIC 150/208/300 mil Package and Pinout (16-pin and 8-pin Versions) HOLD#/IO3 1 16 SCK VCC 2 15 SI/IO0 NC 3 14 NC NC 4 13 NC NC 5 12 NC CS# 1 8 VCC NC 6 11 NC SO (IO1) 2 7 HOLD# (IO3) CS# 7 10 GND WP# (IO2) 3 6 CLK SO/IO1 8 9 GND 4 5 SI (IO0) W#/ACC/IO2 Note: On M25PE Reset is used instead of HOLD. Publication Number Migrate_Micron_M25PE_PX_to_S25FL-K_AN Revision 01 Issue Date July 17, 2012 A pplication Note Table 2.1 and Table 2.2 summarize the available packages from Micron and Spansion: Table 2.1 PX Family Package Comparison Micron M25PX PX80 PX16 SOIC8 150 mi x x SOIC8 208 mil x x SOIC16 300 mil PX32 x x USON 5x6 x BGA 6x8 Spansion S25FL PX64 x x x x FL004K FL008K FL016K x x x x x x FL032K FL064K x x x x x Table 2.2 PE Family Package Comparison Micron M25PE PE20 PE40 PE80 x x x x x SOIC8 150 mi SOIC8 208 mil Spansion S25FL PE16 x FL004K FL008K FL016K x x x x x x FL032K FL064K x x SOIC16 300 mil x USON 5x6 x x x x BGA 6x8 2.2 Sector Architecture The sector architecture between Micron and Spansion can be considered as identical, even Micron states 64 kB Sectors but sub-sectors of 4 kB are also offered. However, both Micron and Spansion support the same flexible erase architecture of 4 kB, 64 kB, and chip erase operations (see Table 3.1, Command Set of S25FL-K and M25PX / M25PE on page 5). PE Devices have additionally Page Erase function. Page programming size of 256 byte is also identical. Table 2.3 shows a summary of the erase and programming granularity. Table 2.3 Erase and Programming Granularity Micron M25P 2.3 Spansion S29FL-K Sector Size 4 kB, 64 kB 4 kB Erase Size 256 byte (PE only), 4 kB, 64 kB, chip erase 4 kB, 32 kB, 64 kB, chip erase Page Prog. Size 256 byte 256 byte Sector Protection Spansion's FL-K and Micron’s M25PE / M25PX offer Sector Protection based on Block Protect Bits (BP2, BP1, BP0), which is a similar approach. In addition, Micron offers a sector based Protection which makes software chances necessary when used. For Micron, every physical 64 kB sector of the device has a corresponding two-bit Sector Protection Register, “Write lock bit” and “Lock down bit”, that is used to control the software protection of a sector. Upon device power-up, each Sector Protection Register will default to the logical 0 state indicating that all sectors are unprotected and protection status is reversible. Issuing the Protect / Unprotect Sector command to a particular sector address will set/reset the corresponding Sector Protection Register to the logical “1”/”0” state. Once the lock down bit is set for a particular sector, protection status cannot be changed until the next power cycle (or a Reset for PE Series). All Spansion and Micron devices support a sector protection scheme, which is based on Block Protect Bits (BP2, BP1, BP0). All, none, or a portion of the memory array can be protected from Program and Erase instructions via the status register. The Block Protect Bits (BP2, BP1, BP0) are non-volatile read/write bits in the status register (S4, S3, and S2) that provide Write Protection control and status. The factory default 2 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 July 17, 2012 App l ic atio n No t e setting for the Block Protection Bits is 0 (none of the array is protected). Block Protect bits can be set using the Write Status Register Instruction. The non-volatile Top/Bottom bit (TB) controls if the Block Protect Bits (BP2, BP1, BP0) protect from the Top (TB=0) or the Bottom (TB=1) of the array. The TB Bit functionality is not available on PE Series devices. The non-volatile Sector/Block Protect bit (SEC) on FL-K devices controls if the Block Protect Bits (BP2, BP1, BP0) protect either 4 kB Sectors (SEC=1) or 64 kB Blocks (SEC=0) in the Top (TB=0) or the Bottom (TB=1) of the array. The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1, and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1, and BP0 will be reversed. Please refer to the Spansion data sheet for the valid combinations. Table 2.4 shows the Spansion sector protection. Please refer also to the status register handling. Table 2.4 Status Register Memory Protection (CMP = 0) Status Register S25FL008K (8 MBit) Memory Protection SEC TB BP2 BP1 BP0 Block(s) Addresses Density X X 0 0 0 None None None Portion None 0 0 0 0 1 15 0F0000h – 0FFFFFh 64 kB Upper 1/16 Upper 1/8 0 0 0 1 0 14 and 15 0E0000h – 0FFFFFh 128 kB 0 0 0 1 1 12 thru 15 0C0000h – 0FFFFFh 256 kB Upper 1/4 0 0 1 0 0 8 thru 15 080000h – 0FFFFFh 512 kB Upper 1/2 0 1 0 0 1 0 000000h – 00FFFFh 64 kB Lower 1/16 0 1 0 1 0 0 and 1 000000h – 01FFFFh 128 kB Lower 1/8 0 1 0 1 1 0 thru 3 000000h – 03FFFFh 256 kB Lower 1/4 0 1 1 0 0 0 thru 7 000000h – 07FFFFh 512 kB Lower 1/2 0 X 1 0 1 0 thru 15 000000h – 0FFFFFh 1 MB All X X 1 1 X 0 thru 15 000000h – 0FFFFFh 1 MB All 1 0 0 0 1 15 0FF000h – 0FFFFFh 4 kB Upper 1/256 1 0 0 1 0 15 0FE000h – 0FFFFFh 8 kB Upper 1/128 1 0 0 1 1 15 0FC000h – 0FFFFFh 16 kB Upper 1/64 1 0 1 0 X 15 0F8000h – 0FFFFFh 32 kB Upper 1/32 1 1 0 0 1 0 000000h – 000FFFh 4 kB Lower 1/256 1 1 0 1 0 0 000000h – 001FFFh 8 kB Lower 1/128 1 1 0 1 1 0 000000h – 003FFFh 16 kB Lower 1/64 1 1 1 0 X 0 000000h – 007FFFh 32 kB Lower 1/32 Note: The Complement Protect bit (CMP) is a non-volatile read/write bit in the status register (S14). It is used in conjunction with SEC, TB, BP2, BP1, and BP0 bits to provide more flexibility for the array protection. Once CMP is set to 1, previous array protection set by SEC, TB, BP2, BP1, and BP0 will be reversed. For instance, when CMP=0, a top 4 kB sector can be protected while the rest of the array is not; when CMP=1, the top 4 kB sector will become unprotected while the rest of the array become read-only. 2.4 Status Register The Status Register can be read to determine the device's ready/busy status as well as the status of many other functions such as Hardware Locking and Software Protection. Spansion's Status Register 1 provides the same information as Micron’s Status Register. The Status Register bits for functions that are not available on Micron Devices read 0. This is Bit 6, the setting for Sector protection granularity and Bit 5 the Top / Bottom selector on PE devices. Default settings of Bits 5 and 6 result in same device behavior as Micron Devices. Spansion FL-K devices have an additional Status Register 2, which can be used to provide status on additional device features. Spansion does not distinguish between the two bytes for writing. The Write Status Register instruction allows the Status Register to be written. Only non-volatile Status Register bits SRP0, SEC, TB, BP2, BP1, BP0 (bits 7 thru 2 of Status Register-1) and CMP, LB3, LB2, LB1, QE, SRP1 (bits 14 thru 8 of Status Register-2) can be written. All other Status Register bit locations are read-only and will not be affected by the Write Status Register instruction. July 17, 2012 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 3 A pplication Note Figure 2.2 Spansion Status Register 1 S7 S6 S5 S4 S3 S2 SRP0 SEC TB BP2 BP1 BP0 S1 S0 WEL BUSY Status Register Protect 0 (non-volatile) Sector Protect (non-volatile) Top/Bottom Protect (non-volatile) Block Protect Bits (non-volatile) Write Enable Latch Erase/Write In Progress Notes: S6 is “0” on Micron PE and PX. S5 is “0” on Micron PE. Figure 2.3 Spansion Status Register 2 S15 S14 S13 S12 S11 S10 S9 S8 SUS CMP LB3 LB2 LB1 (R) QE SRP1 Suspend Status Complement Protect (non-volatile) Security Register Lock Bits (non-volatile OTP) Reserved Quad Enable (non-volatile) Status Register Protect 1 ((non-volatile) 3. Software Considerations 3.1 Micron PE / PX versus S25FL-K Command Set Comparison M25PE / M25PX and S25FL-K have the same instructions (op-codes) in their command-set. While Spansion FL-K devices have numerous additional commands that are related to Dual and Quad IO functionality and Erase/Program Suspend/Resume, Micron Devices have additional commands for the Sector based Protection (WRLR, RDLR). A further difference is the “Dual Input fast program” command which is available only on PX devices and the “Page Write” and “Page Erase” command of PE devices. There is no need for a software change because the first byte of FL-K 2 byte Status Register can be written alone. CMP, QE, and SPR1 bits will be cleared to 0, which results in same device behavior as Micron Devices. Table 3.1 shows a comparison summary of the command set of a Spansion S25FL-K device with the corresponding M25PE / M25PX. 4 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 July 17, 2012 App l ic atio n No t e Table 3.1 Command Set of S25FL-K and M25PX / M25PE Name Description S25FL016K M25PX16 M25PE16 READ Read Data (Single output) 03H 03H 03H FAST_READ Fast Read (Single output) 0BH 0BH 0BH DOR Dual Output Fast Read 3BH 3BH N/A QOR Quad Output Fast Read 6BH N/A N/A DIOR Dual I/O Fast read BBH N/A N/A QIOR Quad I/O Fast read EBH N/A N/A RDID Word Read Quad I/O E7H N/A N/A Octal Word Read Quad I/O E3H N/A N/A Read Identification (JEDEC) 9FH 9FH (1) 9FH Read Mfg. ID and device ID 90H N/A N/A Read Mfg/Device ID Dual I/O 92H N/A N/A Read Mfg/Device ID Dual I/O 94H N/A N/A Set Burst with Wrap 77H N/A N/A Continuous Read Mode Reset FFH N/A N/A WREN Write Enable 06H 06H 06H WRDI Write Disable 04H 04H 04H Write Enable for volatile status Reg. 50H N/A N/A Write Lock Register N/A E5H E5H E8H WRLR RDLR Read Lock Register N/A E8H Page Erase N/A N/A N/A 4 kB (32 kB) Block Erase 20H (52H) 20H 20H SE 64 kB Block Erase D8H D8H D8H BE Bulk Erase C7H, 60H C7H C7H Erase/Program Suspend 75H N/A N/A PP Erase/Program Resume 7AH N/A N/A Page Program 02H 02H 02H Page Write N/A N/A N/A DIFP Dual Input fast program N/A A2H N/A QPP Quad Page Programming 32H N/A N/A DP Deep Power Down B9H B9H B9H Release from Deep Power Down ABH ABH ABH Release from Deep Power Down / Read Electronic Signature ABH N/A N/A Read Status Register 05H 05H 05H RCR Read Status Register 2 35H N/A N/A WRR Write Status Register 01H (2) 01H 01H Read SFDP Register 5AH N/A N/A RDSR Notes: 1. RDID 9Fh reads Bytes 1…20, while 9Eh reads Bytes 1…3. 2. FL-K Write Status Register writes 1 or 2 Bytes. 3.2 OTP related Commands The OTP (One Time Programmable Area) is a specific register that can be used to store a serial number or a security-oriented key. The M25PX Series has a 64 Byte OTP area that can be programmed by the user; the M25PE Series does not offer an OTP region at all. Spansion supports a 64-bit unique ID set by the factory, in addition to three times 256 Bytes of OTP. Each set of the 256 Bytes of the OTP area, called security register, can be locked individually by Security Register Lock Bits (LB3, LB2, LB1) in Status Register 2. July 17, 2012 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 5 A pplication Note Micron devices have two commands to manage the OTP area, as locking down is done with an additional byte during programming. To lock the OTP area, bits 0…3 of the additional 65th byte need to be programmed to a logic 0. Table 3.2 OTP Commands Name Description S25FL008K M25PX16 M25PE16 Erase security registers 44H N/A N/A Program security registers 42H N/A N/A Read security registers 48H N/A N/A OTPR Read Data in the OTP area 4BH (1) 4BH N/A OTPP Program Data in the OTP area 42H N/A Note: 1. Reads Unique ID Number. 4. Timing Considerations 4.1 Power-Up Timing One of the most sensitive electrical specifications is the power-up timing needed to correctly initialize the device. Table 4.1 and Figure 4.1 show the power-up characteristics of the S25FL-K family. Table 4.1 S25FL-K Power-Up Timing Requirements Parameter Symbol Min VCC (min) to CS# Low tVSL 10 Max Unit Time Delay Before Write Instruction tPUW 1 10 ms Write Inhibit Threshold Voltage VWI 1.0 2.0 V Read instructions allowed Device is fully accessible µs Figure 4.1 S25FL-K Power-Up Timing Diagram VCC VCC (max) Program, Erase, and Write instructions are ignored CS# must track VCC VCC (min) t VSL Reset State VWI t PUW Time On the Micron side, the parameters of the M25 family members are more restrictive. In particular, the delay before the system issues the first access (tVCSL) needs to be three times longer. Additionally, writes are inhibited already at 2.5V or 2.1V (PX80 and 16), while FL-K enables writing down to 2.0V. 6 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 July 17, 2012 App l ic atio n No t e Table 4.2 M25P Power-Up Timing Requirements M25PX80 Parameter M25PX16 M25PX32 M25PX64 M25PE40 M25PE80 M25PE16 Symbol Units Min Max Min Max Min Max Min Max Min Max Min Max Min Max VCC (min) to CS# Low tVCSL 30 Delay before Program or Erase tPUW 1 10 1 10 1 10 1 10 1 10 1 10 1 10 ms Write Inhibit Threshold Voltage VWI 1.5 2.1 1.5 2.1 1.5 2.5 1.5 2.5 1.5 2.1 1.5 2.5 1.5 2.5 V 4.2 30 30 30 30 30 30 µs Data In Hold Time Two AC timing parameters that are critical in SPI designs are Data In Setup Time and Data In Hold Time. They specify how long data needs to be valid before and after the raising edge of the clock signal, respectively. All Devices except FL032K have the same timing. The minor different requirement should not be an issue in the design but need to be verified. Table 4.3 S25FL-K Data In Hold Time Requirements Parameter Symbol S25FL04K S25FL08K S25FL16K S25FL32K S25FL64K Units Data In Setup Time (Min) tDVCH/tDSU 2 2 2 1.5 2 ns Data In Hold Time (Min) tCHDX/tDH 5 5 5 4 5 ns Table 4.4 M25P Data In Hold Time Requirements Parameter 4.3 Symbol M25PX80 M25PX16 M25PX32 M25PX64 M25PE40 M25PE80 M25PE16 Units Data In Setup Time (Min) tDS 2 2 2 2 2 2 2 ns Data In Hold Time (Min) tDH 5 5 5 5 5 5 5 ns Further Timing Comparison The timing characteristics between the families are almost identical with just a little deviation. The Spansion FL-K family has only a much faster CS# deselect time. Given the 100 ns of PE devices or 80 ns of PX, FL-K has 10 ns between Reads or 50 ns for Read after Writes. There is no need to do any changes, but performance of application can be increased here easily. July 17, 2012 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 7 A pplication Note 5. Revision History Section Description Revision 01 (July 17, 2012) Initial release 8 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 July 17, 2012 App l ic atio n No t e Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2012 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. July 17, 2012 Migrate_Micron_M25PE_PX_to_S25FL-K_AN_01 9