S29WS-N to S29WS-P Migration Migrating from the WS-N (110 nm) to the WS-P (90 nm) Application Note Introduction The S29WS-N and S29WS-P flash family architectures are quite similar; however, migration from the S29WS-N to S29WS-P may require both hardware and software changes. This application note illuminates the differences between these families and provides direction on how to successfully migrate to the S29WS-P flash family. Software Migration There are several changes that may be required when migrating software from the S29WS-N to S29WS-P. Device ID has changed from the S29WS-N to the S29WS-P. There are no array size driven software changes required when migrating from the S29WS-N to the S29WS-P due to the sector size, and block size being the same from the S29WS-N to the S29WS-P for the same density. If the customer is changing the density from the S29WS-N to the S29WS-P, then the appropriate density software changes need to be made. The page read size has doubled from 8-bytes to 16-bytes with migration from the S29WS-N to S29WS-P. Hardware Migration The S29WS-N and S29WS-P are offered in the exact same 84-ball FBGA package (11.6 mm x 8 mm), but the S29WS-P requires two additional VCC and VSS connections. Reference Package Migration on page 3 for Pinout compatibility requirements. Improvements from S29WS-N to S29WS-P Optional programmable output slew rate control, see Table 7.1. Publication Number WS-N_WS-P_Migrate_AN Revision 02 Issue Date September 17, 2010 A pplication 1. Note Key Features Comparison Table 1.1 Comparison of Key Features Feature Technology Process Technology VCC Max Density (monolithic) S29WS-N S29WS-P MirrorBit® MirrorBit® 90 nm 65 nm 1.70V to 1.95V 1.70V to 1.95 256 Mbit 512 Mbit Number of Banks 16 16 Large Sector size 64 Kword / 128 Kbyte 64 Kword / 128 Kbyte Small Sector Size 16 Kword / 128 Kbyte 16 Kword / 128 Kbyte Top, Bottom and Dual Boot Sector Configurable Yes Yes Simultaneous Read/Write Operation Yes Yes 4 Words / 8 bytes 8 Words / 16 bytes Full/Half drive output slew rate control No Yes 32 Word / 64 byte Write Buffer Yes Yes Programmable linear (8/16/32 words) with or without wrap around and continuous burst read Yes Yes Secure Silicon Sector of 256 words (128 Factory and 128 User programmable) Yes Yes 20 year data retention (typical) Yes Yes Operating Temperature Range -40/-25°C to +85 °C (1) -25°C to +85°C Hardware (WP#) protection of top and bottom sectors Yes Yes 100 K Cycles Per Sector (typical) Yes Yes Low VCC Write Inhibit Yes Yes Persistent and Password methods of Advanced Sector Protection Yes Yes Write Operation Status Bits for Program or Erase status Yes Yes Page Read Size Program Suspend/Resume Commands Yes Yes Erase Suspend/Resume Commands Yes Yes Unlock Bypass mode to reduce programming time Yes Yes Synchronous or Asynchronous program operation Yes Yes ACC input to reduce factory programming time Yes Yes Support for Common Flash Interface (CFI) JEDEC (JESD68 and JEP137) Yes Yes Notes 1. S29WS128N is offered in both the -40 to +85°C (Industrial) and the 25 to +85°C (Wireless) temperature ranges. S29WS256N and all S29WS-P devices are only offered in the -25 to +85°C (Wireless) temperature range. 2 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n 2. No t e Package Migration The S29WS-P requires two additional VSS pins (see solid rectangles in Figure 2.1) and two additional two VCC pins (see dashed rectangles in Figure 2.1). Figure 2.1 S29WS-N and S29WS-P Connection Diagrams for an 84-Ball Package A1 NC September 17, 2010 B2 B3 B4 B5 B6 B7 B8 B9 AVD# RFU CLK RFU RFU RFU RFU RFU C2 C3 C4 C5 C6 C7 C8 C9 WP# A7 RFU ACC WE# A8 A11 RFU D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 RFU RESET# RFU A19 A12 A15 E2 E3 E4 E5 E6 E7 E8 E9 A2 A5 A18 RDY A20 A9 A13 A21 F2 F3 F4 F5 F6 F7 F8 F9 A1 A4 A17 RFU A23 A10 A14 A22 G2 G3 G4 G5 G6 G7 G8 G9 A0 VSS DQ1 RFU RFU DQ6 RFU A16 H2 H3 H4 H5 H6 H7 H8 H9 CE#f1 OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU A10 A1 NC DNU A10 DNU B2 B3 B4 B5 B6 B7 B8 B9 AVD# VSS CLK RFU VCC RFU RFU RFU C2 C3 C4 C5 C6 C7 C8 C9 WP# A7 RFU ACC WE# A8 A11 RFU D2 D3 D4 D5 D6 D7 D8 D9 A3 A6 RFU RST# RFU A19 A12 A15 E2 E3 E4 A2 A5 A18 E5 E6 E7 E8 E9 RY/BY# A20 A9 A13 A21 F2 F3 F4 F5 F6 F7 F8 F9 A1 A4 A17 RFU A23 A10 A14 A22 G2 G3 G4 G5 G6 G7 G8 G9 A0 VSS DQ1 RFU RFU DQ6 A24 A16 H2 H3 H4 H5 H6 H7 H8 H2 F-CE# OE# DQ9 DQ3 DQ4 DQ13 DQ15 RFU J2 J3 J4 J5 J6 J7 J8 ?J9 J2 J3 J4 J5 J6 J7 J8 J9 RFU DQ0 DQ10 VCC RFU DQ12 DQ7 VSS RFU DQ0 DQ10 VCC RFU DQ12 DQ7 VSS K2 K3 K4 K5 K6 K7 K8 K9 K2 K3 K4 K5 K6 K7 K8 K9 RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RFU RFU DQ8 DQ2 DQ11 RFU DQ5 DQ14 RFU L2 L3 L4 L5 L6 L7 L8 L9 L2 L3 L4 L5 L6 L7 L8 L9 RFU RFU RFU VCC RFU RFU RFU RFU RFU RFU VSS VCC RFU RFU VCCQ RFU M1 M10 M1 M10 NC NC DNU DNU WS-N_WS-P_Migrate_AN_02 3 A pplication 3. Note Page Mode Read The S29WS-P has page mode read performance improvements. This is accomplished by an 8 word page mode read compared to the S29WS-N 4 word page mode. For the S29WS-N, the address bits Amax-A2 select the 4 word page and A1-A0 select the specific word within the page. For the S29WS-P, the address bits Amax-A3 select the 8 word page and A2-A0 select the specific word within the page. See Table 3.1 and 3.2. Table 3.1 S29WS-N Four word selection within a page Word A1 A0 Word0 0 0 Word1 0 1 Word2 1 0 Word3 1 1 Table 3.2 S29WS-P Eight word selection within a page Word A2 A1 A0 Word0 0 0 0 Word1 0 0 1 Word2 0 1 0 Word3 0 1 1 Word4 1 0 0 Word5 1 0 1 Word6 1 1 0 Word7 1 1 1 4. Synchronous (Burst) Read Mode Both the S29WS-N and S29WS-P have the same burst modes: Continuous Burst 8-, 16-, 32- word Burst with wrap around 8-, 16-, 32- word Burst without wrap around Important: The wait states between the two products are different; therefore, the configuration register needs to be updated to reflect the new wait states for the migration. Please reference the S29WS-N and S29WS-P data sheets for the respective wait state differences. 4 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n 5. No t e Configuration Register The S29WS-P adds an additional 16 configuration register bits. See Table 5.1. Table 5.1 Configuration Register Comparison S29WS-N S29WS-P CR 0 CR 0 CR 0.15 Asynch / Synchronous Read CR 0.14 Boundary Crossing (w and w/o latency) CR 0.13 CR 0.12 Asynch/ Synchronous Read CR 0.14 Reserved CR 0.13 Programmable Wait States CR 0.11 CR 1 CR 0.15 Programmable Wait States CR1.15 Reserved CR1.14 Output drive strength CR1.13 CR 0.12 CR1.12 CR 0.11 CR1.11 Reserved CR 0.10 RDY active low or high CR 0.10 RDY active low or high CR1.10 CR 0.9 Reserved CR 0.9 Reserved CR1.9 Reserved CR 0.8 RDY active prior or with data CR 0.8 RDY active prior or with data CR1.8 Reserved CR 0.7 Reserved CR 0.7 Reserved CR1.7 Reserved CR 0.6 Reserved CR 0.6 Mode of Operation CR1.6 Reserved CR 0.5 Reserved CR 0.5 Reserved CR1.5 Reserved CR 0.4 Reserved CR 0.4 RDY Function CR1.4 Reserved CR 0.3 Burst read w/wo Wrap around CR 0.3 Burst read w/wo Wrap around CR1.3 Reserved CR1.2 Reserved Burst length and Mode (8/16/32/ Continuous Word) CR 0.1 Burst length and Mode (8/16/32/ Continuous Word) CR1.1 Reserved CR1.0 Programmable Wait State CR 0.2 CR 0.1 CR 0.0 September 17, 2010 CR 0.2 CR 0.0 WS-N_WS-P_Migrate_AN_02 Reserved 5 A pplication 6. Note Autoselect The Autoselect information is very similar between the S29WS-N and S29WS-P and the differences are due to the device IDs and Indicator Bits. Please see Table 6.1 for details. Table 6.1 Autoselect Comparison Read Data Description Address Manufacturer ID (BA) + 00h 0001h S29WS-N 0001h S29WS-P Device ID (BA) + 01h 227Eh 227Eh Device ID (BA) + 0Eh 2230h (WS256N) 2231h (WS128N) 223Dh (WS512P)-1CE# 2242h (WS256P) 2244h (WS128P) Device ID (BA) + 0Fh 2200h 2200h DQ15-DQ8 = Reserved DQ7 (Factory Lock Bit): 1 = Locked DQ15-DQ8 = Reserved DQ7 (Factory Lock Bit): 1 = Locked 0 = Not Locked 0 = Not Locked DQ6 (Customer Lock Bit): 1 = Locked DQ6 (Customer Lock Bit): 1 = Locked 0 = Not Locked 0 = Not Locked DQ5 (Handshake Bit): 1 = Reserved DQ5 (Handshake Bit): 1 = Reserved 0 = Standard Handshake Indicator Bits (BA) + 03h 0 = Standard Handshake DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot sectors. 01, 10, 11 = Reserved DQ4, DQ3 (WP# Protection Boot Code): 00 = WP# Protects both Top Boot and Bottom Boot sectors. 01, 10, 11 = Reserved DQ2 = Reserved DQ1 (DYB Power up State [Lock Register DQ4]): 1 = Unlocked (user option) DQ2-DQ0 = Reserved 0 = Locked (default) DQ0 (PPB Eraseability [Lock Register DQ3]): 1 = Erase allowed 0 = Erase disabled Sector Block Lock/Unlock (SA) + 02h 0001h = Locked, 0000h = Unlocked 0001h = Locked, 0000h = Unlocked 7. Programmable Output Slew Rate Control This new feature allows the user to change the output slew rate (or drive strength) during a read operation by setting the configuration register bit CR1.4. It allows two programmable slew rates. This feature allows the user to tune the drive strength to match their system requirements. Table 7.1 Programmable Output Slew Rate 6 Mode Description IOL & IOH 1 Full Drive (Default) 100 µA 2 Half Drive 50 µA WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n 8. No t e DC Characteristics There are minor differences between the S29WS-N and S29WS-P DC Characteristics. These differences are outlined in Table 8.1 and must be individually reviewed for impact against existing application use conditions. Please refer to the respective data sheets for DC timing parameter definitions. Table 8.1 DC Specification Differences Param. Description VCC Active Async Read Current @ 10 MHz ICC1 VCC Active Async Read Current @ 5 MHz VCC Active Async Read Current @ 1 MHz ICC2 VCC Active Program / Erase Current ICC4 VCC Reset Current ICC5 VCC Active Read While Program / Erase Current ICC6 VCC Sleep Current ICC7 VCC Page Mode Read Current WS-N WS-P typ 34 mA 40 mA max 45 mA 80 mA typ 17 mA 20 mA max 26 mA 40 mA 10 mA typ 4 mA max 7 mA 20 mA typ 24 mA 20 mA max 52.5 mA 60 mA 30 µA typ 70 µA max 250 µA 60 µA typ 50 mA 40 mA max 60 mA 60 mA typ 2 µA 5 µA max 70 µA 40 µA typ VCC Active Burst Read Current @ 54 MHz, 8 word burst VCC Active Burst Read Current @ 54 MHz, 16 word burst VCC Active Burst Read Current @ 54 MHz, 32 word burst VCC Active Burst Read Current @ 54 MHz, continuous VCC Active Burst Read Current @ 66 MHz, 8 word burst VCC Active Burst Read Current @ 66 MHz, 16 word burst ICC8 VCC Active Burst Read Current @ 66 MHz, 32 word burst VCC Active Burst Read Current @ 66 MHz, continuous VCC Active Burst Read Current @ 80 MHz, 8 word burst VCC Active Burst Read Current @ 80 MHz, 16 word burst VCC Active Burst Read Current @ 80 MHz, 32 word burst VCC Active Burst Read Current @ 80 MHz, continuous September 17, 2010 max 10 mA 12 mA 15 mA typ 27 mA 32 mA max 54 mA 37 mA typ 28 mA 32 mA max 48 mA 37 mA typ 29 mA 33 mA max 42 mA 38 mA typ 32 mA 34 mA max 36 mA 39 mA typ 28 mA 35 mA max 60 mA 41 mA typ 30 mA 35 mA max 54 mA 41 mA typ 32 mA 36 mA max 48 mA 42 mA typ 35 mA 37 mA max 42 mA 43 mA typ 30 mA 39 mA max 66 mA 46 mA typ 32 mA 39 mA max 60 mA 46 mA typ 34 mA 40 mA max 54 mA 47 mA typ 38 mA 41 mA max 48 mA 48 mA VIL Input Low Voltage min -0.5 V -0.2 V VOH Output High Voltage min VCC VCC-0.1 V WS-N_WS-P_Migrate_AN_02 7 A pplication 9. Note AC Characteristics There are numerous differences between the S29WS-N and S29WS-P AC Characteristics. These differences are outlined in Table 9.1 for 54 MHz speed grade applications, Table 9.2 for 66 MHz speed grade applications and Table 9.3 for 80 MHz speed grade applications. Parameter differences must be individually reviewed for impact against existing application timing. Please refer to the respective data sheets for AC timing parameter definitions. Table 9.1 AC Parameter Differences - 54 MHz Speed Grade Mode: Async Read Mode: Sync Read Mode: Async Write Mode: Sync Write Param. tVCS Description VCC Setup Time min WS-N 54 MHz WS-P 54 MHz 1 ms 30 µs X tAAVDH Address Hold from AVD# High min 7 ns 4 ns X tAAVDS Address Setup to AVD# High min 4 ns 6 ns X tAVDP AVD# Low min 8 ns 7.5 ns X tCE Access from CE# Low min 80 ns 83 ns X tCEX Chip Enable to High-Z max 10 ns 7.6 ns X tOEH Output Enable Hold Time during Data Polling min 10 ns 4 ns X tOEZ Output Enable to High-Z max 10 ns 7.6 ns X fCLK CLK Frequency - 8 word Burst min 1 MHz 60 KHz X fCLK CLK Frequency - 16 word Burst min 1 MHz 120 KHz X fCLK CLK Frequency - 32 word Burst min 1 MHz 250 KHz X tACH Read Address Hold from CLK min 7 ns 6 ns X tADVH AVD# Hold from CLK min 3 ns n/s X tAVC ADV# Low to CLK min 4 ns 6 ns X tAVD AVD# Pulse Width min 7 ns tCLK X tCES Chip Enable Set-up to CLK min 4 ns 6 ns 7.4 ns 0.45 * tCLK X X tCH CLK High Period min X X tCH CLK High Period max n/s 0.55 * tCLK X X tCL CLK Low Period min 7.4 ns 0.45 * tCLK X X tCL CLK Low Period max n/s 0.55 * tCLK X tCR Chip Enable to RDY Valid max 13.5 ns n/s X tIACC Initial Access Time min 80 ns (WS-1) * tCLK * tBACC Output Enable to RDY Low max 13.5 ns 13.5 ns RDY Access Time from CLK max 13.5 ns 13.5 ns 10 ns X tOE X tRACC X tRDY Chip Enable to RDY Active max n/s X tRDYS RDY Setup to CLK min 5 ns n/s X tAH Address Hold Time min 20 ns 7 ns X tAS Address Setup Time min 0 ns 6 ns X tAH Address Hold Time min 9 ns 7 ns X tWC Write Cycle Time min 80 ns 60 ns X X tAVDP AVD# Low min 8 ns 6 ns X X tAVHW AVD# Hold from WE# min 5 ns 4 ns X X tAVSW AVD# Setup to WE# min 5 ns 4 ns X X tCS CE# setup to WE# min 5 ns 4 ns X X tDS Data Set Up min 45 ns 20 ns X X tESL Erase Suspend Latency max 20 µs 40 µs X X tPSL Program Suspend Latency max 20 µs 40 µs X X tWP Write Pulse Width min 30 ns 25 ns Note n/s = not specified 8 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n No t e Table 9.2 AC Parameter Differences - 66 MHz Speed Grade Mode: Async Read Mode: Sync Read Mode: Async Write Mode: Sync Write Param. tVCS Description WS-N 66 MHz WS-P 66 MHz VCC Setup Time min 1 ms 30 µs X tAAVDH Address Hold from AVD# High min 6 ns 4 ns X tAAVDS Address Setup to AVD# High min 4 ns 6 ns X tAVDP AVD# Low min 8 ns 7.5 ns X tCE Access from CE# Low min 80 ns 83 ns X tCEX Chip Enable to High-Z max 10 ns 7.6 ns X tOEH Output Enable Hold Time during Data Polling min 10 ns 4 ns tOEZ Output Enable to High-Z max 10 ns 7.6 ns X fCLK CLK Frequency - 8 word Burst min 1 MHz 60 KHz X fCLK CLK Frequency - 16 word Burst min 1 MHz 120 KHz X fCLK CLK Frequency - 32 word Burst min 1 MHz 250 KHz X tADVH AVD# Hold from CLK min 3 ns n/s X tAVC ADV# Low to CLK min 4 ns 6 ns X tAVD AVD# Pulse Width min 7 ns tCK X tCES Chip Enable Set Up to CLK min 4 ns 6 ns X X X tCH CLK High Period min 6.1 ns 0.45 * tCK X X tCH CLK High Period max n/s 0.55 * tCK X X tCL CLK Low Period min 6.1 ns 0.45 * tCK X X tCL CLK Low Period max n/s 0.55 * tCK tCR Chip Enable to RDY Valid max 11.2 ns n/s X X tIACC Initial Access Time min 80 ns (WS-1) * tCK * tBACC X tRDY Chip Enable to RDY Active max n/s 10 ns tRDYS RDY Setup to CLK min 4 ns n/s tAH Address Hold Time min 20 ns 7 ns X X X X tAS Address Setup Time min 0 ns 6 ns tAH Address Hold Time min 9 ns 7 ns X tWC Write Cycle Time min 80 ns 60 ns X X tAVDP AVD# Low min 8 ns 6 ns X X tAVHW AVD# Hold from WE# min 5 ns 4 ns X X tAVSW AVD# Setup to WE# min 5 ns 4 ns X X tCS CE# setup to WE# min 5 ns 4 ns X X tDS Data Set Up min 20 ns 20 ns X X tESL Erase Suspend Latency max 20 µs 40 µs X X tPSL Program Suspend Latency max 20 µs 40 µs X X tWP Write Pulse Width min 30 ns 25 ns Note n/s = not specified September 17, 2010 WS-N_WS-P_Migrate_AN_02 9 A pplication Note Table 9.3 AC Parameter Differences - 80 MHz Speed Grade Mode: Async Read Mode: Sync Read Mode: Async Write Mode: Sync Write Param. tVCS Description WS-N 80 MHz WS-P 80 MHz 30 µs VCC Setup Time min 1 ms X tAAVDH Address Hold from AVD# High min 6 ns 4 ns X tAAVDS Address Setup to AVD# High min 4 ns 6 ns X tAVDP AVD# Low min 8 ns 7.5 ns X tCE Access from CE# Low min 80 ns 83 ns X tCEX Chip Enable to High-Z max 10 ns 7.6 ns X tOEH Output Enable Hold Time during Data Polling min 10 ns 4 ns tOEZ Output Enable to High-Z max 10 ns 7.6 ns X fCLK CLK Frequency - 8 word Burst min 1 MHz 60 KHz X fCLK CLK Frequency - 16 word Burst min 1 MHz 120 KHz X fCLK CLK Frequency - 32 word Burst min 1 MHz 250 KHz X tACH Read Address Hold from CLK min 6 ns 5 ns X tADVH AVD# Hold from CLK min 3 ns n/s X tAVC ADV# Low to CLK min 4 ns 6 ns X tAVD AVD# Pulse Width min 7 ns tCK X X tCES Chip Enable Set Up to CLK min 4 ns 6 ns X X tCH CLK High Period min 5.0 ns 0.45 * tCK X X tCH CLK High Period max n/s 0.55 * tCK X X tCL CLK Low Period min 5.0 ns 0.45 * tCK X X tCL CLK Low Period max n/s 0.55 * tCK tCR Chip Enable to RDY Valid max 9 ns n/s X X tIACC Initial Access Time min 80 ns (WS-1) * tCK * tBACC Output Enable to RDY Low max 11.2 ns 9 ns RDY Access Time from CLK max 8.5 ns 9 ns X tOE X tRACC X tRDY Chip Enable to RDY Active max n/s 10 ns X tRDYS RDY Setup to CLK min 3.5 ns n/s X tAH Address Hold Time min 20 ns 6 ns X tAS Address Setup Time min 0 ns 6 ns X tAH Address Hold Time min 9 ns 6 ns X tWC Write Cycle Time min 80 ns 60 ns X X tAVDP AVD# Low min 8 ns 6 ns X X tAVHW AVD# Hold from WE# min 5 ns 4 ns X X tAVSW AVD# Setup to WE# min 5 ns 4 ns X X tCS CE# setup to WE# min 5 ns 4 ns X X tESL Erase Suspend Latency max 20 µs 40 µs X X tPSL Program Suspend Latency max 20 µs 40 µs X X tWP Write Pulse Width min 30 ns 25 ns Note n/s = not specified 10 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n No t e 10. Erase and Programming Performance There are Chip Erase and Chip Program performance improvements when migrating from the S29WS-N to the S29WS-P. Table 10.1 S29WS-N Erase and Programming Performance Parameter 64 Kword VCC 16 Kword VCC Sector Erase Time VCC Typ (Note 1) Max (Note 2) Units 0.6 3.5 s <0.15 2 153.6 (WS256N) 308 (WS256N) 77.4 (WS128N) 154 (WS128N) 130.6 (WS256N) 262 (WS256N) 65.8 (WS128N) 132 (WS128N) s Chip Erase Time ACC Single Word Programming Time (Note 7) Effective Word Programming Time utilizing Program Write Buffer Total 32-Word Buffer Programming Time VCC 40 400 ACC 24 240 VCC 9.4 94 6 60 VCC 300 3000 ACC 192 1920 157.3 (WS256N) 314.6 (WS256N) µs µs 78.6 (WS128N) 157.3 (WS128N) 100.7 (WS256N) 201.3 (WS256N) 50.3 (WS128N) 100.7 (WS128N) s Chip Programming Time (Note 3) ACC Excludes 00h programming prior to erasure (Note 4) µs ACC VCC Comments Excludes system level overhead (Note 5) Notes 1. Typical program and erase times assume the following conditions: 25°C, 1.8V VCC, 10,000 cycles; checkerboard data pattern. 2. Under worst case conditions of 90°C, VCC = 1.70V, 100,000 cycles. 3. Typical chip programming time is considerably less than the maximum chip programming time listed, and is based on utilizing the Write Buffer. 4. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. 6. Refer to Application Note “Erase Suspend/Resume Timing” for more details. 7. Word programming specification is based upon a single word programming operation not utilizing the write buffer. September 17, 2010 WS-N_WS-P_Migrate_AN_02 11 A pplication Note Table 10.2 S29WS-P Erase and Programming Performance Parameter Typ (Note 1) Max (Note 2) Units s 64 Kword VCC 0.6 3.0 16 Kword VCC 0.35 1.75 78.4 (WS128P) 154 (WS128P) VCC 155.2 (WS256P) 308 (WS256P) 308.8 (WS512P) 616 (WS512P) Sector Erase Time Chip Erase Time Single Word Programming Time Effective Word Programming Time utilizing Program Write Buffer VCC 40 400 ACC 24 240 94 VCC 9.4 6 60 VCC 300 3000 ACC 192 1920 50.4 (WS128P) 157.3 (WS128P) VCC 100.8 (WS256P) 314.6 (WS256P) 201.6 (WS512P) 1008 (WS512P) 33.6 (WS128P) 100.7 (WS128P) 67.2 (WS256P) 201.3 (WS256P) 134.4 (WS512P) 402.6 (WS512P) Excludes 00h programming prior to erasure (Note 3) s µs ACC Comments Excludes system level overhead (Note 4) µs Total 32-Word Buffer Programming Time Chip Programming Time (using 32 word buffer) s ACC Erase Suspend/Erase Resume (tERS) 20 µs Program Suspend/Program Resume (tPRS) 20 µs Excludes system level overhead (Note 4) Notes 1. Typical program and erase values are measured at TC = 25°C, 1.8V VCC, 10,000 cycles using checkerboard patterns. Sampled, but not 100% tested. 2. Under worst case conditions of 90°C, VCC = 1.70V, 100,000 cycles. 3. In the pre-programming step of the Embedded Erase algorithm, all words are programmed to 00h before erasure. 4. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. 11. Lock Register The Lock Register bit DQ3 assignment is different between the S29WS-N and S29WS-P. Table 11.1 Lock Register Device DQ15-05 S29WS256N 1's S29WS128N Undefined S29WS128P/ S29WS256P/ S29WS512P 1's 12 DQ4 DQ3 DQ2 DQ1 DQ0 Persistent Protection Mode Lock Bit Customer Secure Silicon Sector Protection Bit 1 1 Password Protection Mode Lock Bit DYB Lock Boot Bit 0 = sectors power up protected 1 = sectors power up unprotected PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit Customer Secure Silicon Sector Protection Bit Reserved (default = 1) PPB One-Time Programmable Bit 0 = All PPB erase command disabled 1 = All PPB Erase command enabled Password Protection Mode Lock Bit Persistent Protection Mode Lock Bit Customer Secure Silicon Sector Protection Bit WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n No t e 12. Memory Array Commands There are some minor differences between the S29WS-N and S29WS-P for the Memory Array Commands. Specifically, the S29WS-P family supports additional commands to read the new Autoselect Mode Sector Unlock/Lock Status Verify register as well as Unlock Bypass Mode Sector Erase and Chip Erase. The use of these new commands is optional and as should not impact migration from the S29WS-N to S29WS-P. There are some minor differences between the S29WS-N and S29WS-P for the Memory Array Commands. Both tables are reproduced below for your reference. Command Sequence (Notes) Cycles Table 12.1 S29WS-N Memory Array Commands Bus Cycles (1) (5) First Addr Data RD Asynchronous Read (6) 1 RA Reset (7) Autoselect(8) Second Addr Data Third Fourth Addr Data Addr Fifth Data 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 [BA]555 90 [BA]X00 0001 Device ID (9) 6 555 AA 2AA 55 [BA]555 90 [BA]X01 227E Indicator Bits (10) 4 555 AA 2AA 55 [BA]555 90 [BA]X03 Data Program 4 555 AA 2AA 55 555 A0 PA PD Write to Buffer (11) 6 555 AA 2AA 55 PA 25 PA WC Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (12) 3 555 AA 2AA 55 555 F0 Sixth Addr Data Addr Data BA+X0E Data BA+X0F 2200 PA PD WBL PD 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 Erase/Program Suspend (13) 1 BA B0 Erase/Program Resume (14) 1 BA 30 Set Configuration Register (18) 4 555 AA 2AA 55 555 D0 X00 CR Read Configuration Register 4 555 AA 2AA 55 555 C6 X00 CR CFI Query (15) 1 [BA]555 98 3 555 AA 2AA 55 555 20 Program (16) 2 XXX A0 PA PD CFI (16) 1 XXX 98 Unlock Bypass Mode 6 Sector Erase Entry Reset 2 XXX 90 XXX 00 Secured Silicon Sector Chip Erase Entry 3 555 AA 2AA 55 555 88 Program (17) 4 555 AA 2AA 55 555 A0 PA PD Read (17) 1 SA Data Exit (17) 4 555 AA 2AA 55 555 90 XXX 00 Legend: X = Don’t care RA = Read Address RD = Read Data PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address: WS256N = A23–A14; WS128N = A22–A14. BA = Bank Address: WS256N = A23–A20; WS128N = A22–A20. CR = Configuration Register data bits D15–D0 WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes: 1. See description of bus operations. 2. All values are in hexadecimal. 3. Shaded cells indicate read cycles. 4. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data). 5. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 6. No unlock or command cycles required when bank is reading array data. September 17, 2010 WS-N_WS-P_Migrate_AN_02 13 A pplication Note 7. Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. 8. The system must provide the bank address. 9. Data in cycle 5 is 2230 (WS256N) or 2231 (WS128N). 10. See indicator bit values. 11. Total number of cycles in the command sequence is determined by the number of words written to the write buffer. 12. Command sequence resets device for next command after write-to-buffer operation. 13. System may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Erase Suspend command is valid only during a sector erase operation, and requires the bank address. 14. Erase Resume command is valid only during the Erase Suspend mode, and requires the bank address. 15. Command is valid when device is ready to read array data or when device is in autoselect mode. Address equals 55h on all future devices, but 555h for WS256N/ 128N. 16. Requires Entry command sequence prior to execution. Unlock Bypass Reset command is required to return to reading array data. 17. Requires Entry command sequence prior to execution. Secured Silicon Sector Exit Reset command is required to exit this mode; device may otherwise be placed in an unknown state. 18. Requires reset command to configure the Configuration Register. 14 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n No t e Table 12.2 S29WS-P Memory Array Commands Command Sequence (Notes) Cycles Bus Cycles (Note 1 - 6) First Second Addr Data (19) Addr Data (19) Third Addr 1 RA RD Reset (8) 1 XXX F0 Manufacturer ID 4 555 AA 2AA 55 Device ID (10) 6 555 AA 2AA 55 Indicator Bits 4 555 AA 2AA 55 Sector Unlock/Lock Verify (11) 4 555 AA 2AA 55 Single word 4 555 AA 2AA 55 555 Write Buffer to Flash Program (17) 6 555 AA 2AA 55 Autoselect (9) Asynchronous Read (7) (BA) 555 (BA) 555 (BA) 555 (SA) Fourth Data (19) 90 90 90 Addr (BA) X00 (BA) X01 (BA) X03 Data (19) 227E Addr Data (19) (BA)X 0E (10) (BA) X0F (10) PD WBL PD (12) 0000/ X02 0001 A0 PA Data SA 25 SA WC 90 Addr Sixth Data (19) 0001 (SA) 555 Fifth PA (20) Program Buffer to Flash 1 SA 29 Write to Buffer Abort Reset (12) 3 555 AA 2AA 55 555 F0 Chip Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 Sector Erase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30 B0 2AA 55 555 D0 X00 CR0 X01 CR1 X0 (0 or 1) CR (0 or 1) Program/Erase Suspend (15) 1 BA Program/Erase Resume (16) 1 BA 30 Set Configuration Register (21) 5 555 AA Read Configuration Register 4 555 AA CFI Query (17) 1 (BA) 55 98 Unlock Bypass Entry (18) 3 555 Unlock Bypass Program (13, 14) 2 Unlock Bypass Sector Erase (13, 14) Unlock Bypass Erase (13, 14) Unlock Bypass Mode 2AA 55 555 C6 AA 2AA 55 555 20 XX A0 PA PD 2 XX 80 SA 30 2 XX 80 XXX 10 XXX 00 Unlock Bypass CFI (13, 14) 1 XX 98 Unlock Bypass Reset 2 XX 90 Legend X = Don’t care RA = Read Address RD = Read Data PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. Notes 1. See description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0. 5. Unless otherwise noted, address bits Amax–A14 are don’t cares. 6. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 7. No unlock or command cycles required when bank is reading array data. 8. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase Suspend) when a bank is in the autoselect mode, or if DQ5 goes high (while the bank is providing status information) or performing sector lock/unlock. September 17, 2010 WS-N_WS-P_Migrate_AN_02 15 A pplication Note 9. The fourth cycle of the autoselect address is a read cycle. The system must provide the bank address. 10. (BA) + 0Eh ----> For WS128 = 2244h, WS256 = 2242h, WS512 = 223Dh. (BA) + 0Fh ----> For WS064/128/256/512 = 2200h 11. The data is 0000h for an unlocked sector and 0001h for a locked sector 12. See Autoselect Addresses. 13. The Unlock Bypass command sequence is required prior to this command sequence. 14. The Unlock Bypass Reset command is required to return to reading array data when the bank is in the unlock bypass mode. 15. The system may read and program in non-erasing sectors, or enter the autoselect mode, when in the Erase Suspend mode. The Program/Erase Suspend command is valid only during a program/ erase operation, and requires the bank address. 16. The Program/Erase Resume command is valid only during the Program/Erase Suspend mode, and requires the bank address. 17. The total number of cycles in the command sequence is determined by the number of words written to the write buffer. The maximum number of cycles in the command sequence is 37. 18. Write Buffer Programming can be initiated after Unlock Bypass Entry. 19. Data is always output at the rising edge of clock. 20. Must be the lowest address. 21. Configuration Registers can not be programmed out of order. CR0 must be programmed prior to CR01 otherwise the configuration registers will retain their previous settings 16 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n No t e 13. Sector Protection Commands There are some minor differences between the S29WS-N and S29WS-P for the Sector Protection Commands. The significant changes that may impact migration from S29WS-N to S29WS-P include: The Lock Register Bits Program command second cycle must be written to address offset 0x00h for the S29WS-P, while the S29WS-N support writes to either offset 0x00 or 0x77. The Lock Register Bits Read command must be performed at address offset 0x00 for the S29WS-P, while the S29WS-N required the read at address offset 0x77. Both tables are reproduced below for your reference. Command Sequence (Notes) Lock Register Bits Password Protection Non-Volatile Sector Protection (PPB) Global Volatile Sector Protection Freeze (PPB Lock) Command Set Entry (5) Program (6) (12) Cycles Figure 13.1 S29WS-N Sector Protection Commands Bus Cycles (1) (4) First Second Third Fourth Addr Data Addr Data Addr Data 3 555 AA 2AA 55 555 40 2 XX A0 77/00 data 555 60 Addr Data Read (6) 1 77 data Command Set Exit (7) 2 XX 90 XX 00 Command Set Entry (5) 3 555 AA 2AA 55 Program [0-3] (8) 2 XX A0 00 PWD[03] Read (9) 4 0...00 PWD 0 0...01 PWD1 0...02 PWD 2 0...03 PWD 3 Unlock 7 00 25 00 03 00 PWD 0 01 PWD 1 Command Set Exit (7) 2 XX 90 XX 00 Command Set Entry (5) 3 555 AA 2AA 55 [BA]555 C0 PPB Program (10) 2 XX A0 SA 00 All PPB Erase (10) (11) 2 XX 80 00 30 [BA]555 50 [BA]555 E0 PPB Status Read 1 SA RD(0) Command Set Exit (7) 2 XX 90 XX 00 Command Set Entry (5) 3 555 AA 2AA 55 PPB Lock Bit Set 2 XX A0 XX 00 PPB Lock Bit Status Read 1 BA RD(0) Command Set Exit (7) 2 XX 90 XX 00 Command Set Entry (5) 3 555 AA 2AA 55 Volatile Sector DYB Set Protection DYB Clear (DYB) DYB Status Read Command Set Exit (7) 2 XX A0 SA 00 2 XX A0 SA 01 1 SA RD(0) 2 XX 90 XX 00 Fifth Sixth Addr Data Addr Data 02 PWD 2 03 PWD 3 Seventh Addr Data 00 29 Legend: X = Don’t care RA = Address of the memory location to be read PD(0) = Secured Silicon Sector Lock Bit. PD(0), or bit[0]. PD(1) = Persistent Protection Mode Lock Bit. PD(1), or bit[1], must be set to ‘0’ for protection while PD(2), bit[2] must be left as ‘1’. PD(2) = Password Protection Mode Lock Bit. PD(2), or bit[2], must be set to ‘0’ for protection while PD(1), bit[1] must be left as ‘1’. PD(3) = Protection Mode OTP Bit. PD(3) or bit[3]. SA = Sector Address. WS256N = A23–A14; WS128N = A22–A14. BA = Bank Address. WS256N = A23–A20; WS128N = A22–A20. PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password September 17, 2010 WS-N_WS-P_Migrate_AN_02 17 A pplication Note PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data. RD(0), RD(1), RD(2) = DQ0, DQ1, or DQ2 protection indicator bit. If protected, DQ0, DQ1, or DQ2 = 0. If unprotected, DQ0, DQ1, DQ2 = 1. Notes: 1. All values are in hexadecimal. 2. Shaded cells indicate read cycles. 3. Address and data bits not specified in table, legend, or notes are don’t cares (each hex digit implies 4 bits of data). 4. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. The system must write the reset command to return the device to reading array data. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the WS256N only. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. Entire two bus-cycle sequence must be entered for each portion of the password. 9. Full address range is required for reading password. 10. See PPB Program/Erase Algorithm for details. 11. “All PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure. 12. The second cycle address for the lock register program operation is 77 for S29WS256N; however, for WS128N this address is 00. 18 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n No t e Table 13.1 S29WS-P Sector Protection Commands (Sheet 1 of 2) Command Sequence (Notes) Cycles Bus Cycles (Note 1 - 6) First Second Addr Data (10) Third Fourth Addr Data( (10) Addr Data( (10) Addr Data( (10) AA 2AA 55 555 88 2AA 55 555 A0 PA PD XX 00 Entry (5) 3 555 Program Secured Silicon Sector Read 4 555 AA 1 SA data Exit (7) 4 555 AA 2AA 55 555 90 Register Command Set Entry (5) 3 555 AA 2AA 55 555 40 00 data 555 60 02 PWD 2 03 PWD 3 00 PWD 0 01 PWD 1 (BA) 555 C0 555 50 (BA) 555 E0 Register Bits Program (6) 2 XX A0 Register Bits Read 1 00 data Register Command Set Exit (7) 2 XX 90 XX 00 Protection Command Set Entry 3 555 AA 2AA 55 00/ PWD 0/ Fifth Addr Data( (10) Sixth Addr Data( (10) Seventh Addr Data( (10) 00 29 Lock Register Password Program (9) PPB 2 XX A0 01/ 02/ 03 1/ 2/ 3/ 01 PWD 1 Read Password (10) 4 00 PWD 0 Unlock (9) 7 00 25 00 03 Protection Command Set Exit 2 XX 90 XX 00 Non-Volatile Sector Protection Command Set Entry (5) 3 555 AA 2AA 55 Program 2 XX A0 (BA) SA 00 All Erase (8) 2 XX 80 XX 30 Status Read 1 (BA) SA RD(0) Non-Volatile Sector Protection Command Set Exit (7) 2 XX 90 XX 00 Global Volatile Sector Protection Freeze Command Set Entry (5) 3 555 AA 2AA 55 Set 2 XX A0 XX 00 Status Read 1 XX RD(0) Global Volatile Sector Protection Freeze Command Set Exit (7) 2 XX 90 XX 00 Volatile Sector Protection Command Set Entry (5) 3 555 AA 2AA 55 Set 2 XX A0 (BA) SA 00 Clear 2 XX A0 (BA) SA 01 Status Read 1 (BA) SA RD(0) Volatile Sector Protection Command Set Exit (7) 2 XX 90 XX 00 02 PWD 2 03 PWD 3 PPB Lock Bit DYB September 17, 2010 WS-N_WS-P_Migrate_AN_02 19 A pplication Note Table 13.1 S29WS-P Sector Protection Commands (Sheet 2 of 2) Command Sequence (Notes) Cycles Bus Cycles (Note 1 - 6) First Second Addr Data (10) Addr Data( (10) PA Data Program 2 555 A0 Sector Erase 2 555 80 SA 30 Chip Erase 2 555 80 555 10 Asynchronous Read 1 RA RD Write to Buffer 4 SA 25 SA WC Program Buffer to Flash 1 SA 29 Third Fourth Addr Data( (10) Addr Data( (10) PA PD WBL PD Fifth Addr Data( (10) Sixth Addr Data( (10) Seventh Addr Data( (10) Accelerated Legend X = Don’t care RA = Read Address RD = Read Data PA = Program Address. Addresses latch on the rising edge of the AVD# pulse or active edge of CLK, whichever occurs first. PD = Program Data. Data latches on the rising edge of WE# or CE# pulse, whichever occurs first. SA = Sector Address: WS128P = A22–A14, WS256P = 23–A14 BA = Bank Address: WS128P = A22-A20, and A19; WS256P = A23-A20 CR = Configuration Register data bits D15–D0 PWD3–PWD0 = Password Data. PD3–PD0 present four 16 bit combinations that represent the 64-bit Password. PWA = Password Address. Address bits A1 and A0 are used to select each 16-bit portion of the 64-bit entity. PWD = Password Data RD(0) = DQ0 protection indicator bit. If protected, DQ0 = 0, if unprotected, DQ0 = 1. WBL = Write Buffer Location. Address must be within the same write buffer page as PA. WC = Word Count. Number of write buffer locations to load minus 1. Notes 1. See description of bus operations. 2. All values are in hexadecimal. 3. Except for the following, all bus cycles are write cycle: read cycle, fourth through sixth cycles of the Autoselect commands, fourth cycle of the configuration register verify and password verify commands, and any cycle reading at RD(0) and RD(1). 4. Data bits DQ15–DQ8 are don’t care in command sequences, except for RD, PD, WD, PWD, and PWD3-PWD0. 5. Entry commands are required to enter a specific mode to enable instructions only available within that mode. 6. If both the Persistent Protection Mode Locking Bit and the Password Protection Mode Locking Bit are set at the same time, the command operation aborts and returns the device to the default Persistent Sector Protection Mode during 2nd bus cycle. Note that on all future devices, addresses equal 00h, but is currently 77h for the WS512P only. 7. Exit command must be issued to reset the device into read mode; device may otherwise be placed in an unknown state. 8. “All PPB Erase” command pre-programs all PPBs before erasure to prevent over-erasure. 9. Entire two bus-cycle sequence must be entered for each portion of the password. 10. Full address range is required for reading password. 20 WS-N_WS-P_Migrate_AN_02 September 17, 2010 App l ic atio n No t e 14. Revision History Section Description Revision 01 (April 13, 2007) Initial release Revision 02 (September 17, 2010) General updates, including WS128N temperature option and inclusion of DC & AC comparison tables. September 17, 2010 WS-N_WS-P_Migrate_AN_02 21 A pplication Note Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products. Trademarks and Notice The contents of this document are subject to change without notice. This document may contain information on a Spansion product under development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any damages of any kind arising out of the use of the information in this document. Copyright © 2007-2010 Spansion Inc. All rights reserved. Spansion®, the Spansion logo, MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. 22 WS-N_WS-P_Migrate_AN_02 September 17, 2010