ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] APPLICATION NOTE FOR PTRTC1010 CONTENTS 1. OVERVIEW……………………………………………………………………………………………………………………. 2 2. FEATURES……………………………………………………………………………………………………………………. 2 3. BLOCK DIAGRAM……………………………………………………………………………………………………………. 2 4. PAD DESCRIPTION…………………………………………………………………………………………………………. 3 5. ABSOLUTE MAXIMUM RATINGS…………………………………………………………………………………………. 4 6. RECOMMENDED OPERATING CONDITIONS ………………………………………………………………………….. 4 7. ELECTRICAL CHARACTERISTICS……………………………………………………………………………………….. 4 7.1. DC Characteristics ………………………………………………………………………………………………………… 4 7.2. AC Characteristics …………………………………………………………………………………………………………. 5 7.3. Crystal Characteristics …………………………………………………………………………………………………….. 6 7.4. Oscillator Characteristics ………………………………………………………………………………………………….. 7 7.5. Switching to and from Backup ……………………………………………………………………………………………. 7 8. REGISTERS…………………………………………………………………………………………………………………... 8 8.1. Register Table………………………………………………………………………………………………………………. 8 8.2. Register Description………………………………………………………………………………………………………... 9‐13 9. INTERRUPTS…………………………………………………………………………………………………………………. 14 9.1. Alarm Interrupts…………………………………………………………………………………………………………….. 14 9.2. Timer Interrupts…………………………………………………………………………………………………………….. 15 9.3. Time update Interrupts…………………………………………………………………………………………………….. 16 10. I2C-BUS SERIAL INTERFACE ……………………………………………………………………………………………. 17 2 10.1. I C-Bus Interface Characteristics ………………………………………………………………………………………. 17 10.2. Bit Transfer………………………………………………………………………………………………………………… 17 10.3. Start Condition and Stop Condition…………………………………………………………………………………….. 17 10.4. Slave Address…………………………………………………………………………………………………………….. 17 10.5. System Configuration…………………………………………………………………………………………………….. 18 10.6. Acknowledge Signal………………………………………………………………………………………………………. 18 2 10.7. I C-Bus Control …………………………………………………………………………………………………………... 19‐20 11. Package and PCB layout………………………………………………………………………………………………… CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 1 • May 2014 21 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] 1. OVERVIEW The PTRTC1010 is an I2C-Bus serial interface, high-precision real-time clock IC with built-in 32.768kHz temperture compensated crystal oscillator (DTCXO). It features a clock and calendar circuit that counts seconds through to years with automatic leap year correction,time alarm, interval timer, time update interrupts, 32.768kHz output, and other functions. 2. FEATURES Built-in high precision 32.768kHz temperature compensated crystal oscillator (DTCXO) I2C bus serial interface 400kHz fast mode compatible Clock output frequency select function (32.768kHz, 1024Hz, 1Hz) Clock (hour, minute, second), calendar (year, month, day, day of week) counter function Alarm, fixed-cycle timer Time update interrupt functions Frequency output function:32.768kHz(Enable function OE ) Automatic leap year correction function (year 2000 to 2099) Wide range operating supply voltage: 2.2 to 5.5V Wide time hold voltage：1.8V-5.5V Low current consumption: <1.8uA (typ) (VDD=3V) 3. BLOCK DIAGRAM CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 2 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 4. PAD DESCRIPTION PTRTC1010 1.T1(CE) 2. SCL 3. FOUT 4. N.C. 5.TEST 6.VDD 7. FOE 14.N.C. 13.SDA 12.T2(VPP) 11.GND 10./INT 9.N.C. 8.N.C. SOP-14pin 4.1 PAD FUNCTIONS Number/Name I/O Function 1：T1 In Manufacturer test pin(not used for normal operation) 2：SCL In In I2C bus interface mode, SCL serial clock input for communication. 3:FOUT Out Clock output (CMOS)with output control Output state is controlled by FO E input When the power supply is turned on,32.768kHz is selected by power-on reset function When no output, FOUT=H-Z(high impedance) 4/8/9/14:NC 5:TEST No connection with IC In Manufacturer test pin(not used for normal operation) Supply voltage positive connection. 6:VDD 7:FO E In Control input for controlling the output state of the FOUT output Fout is clock output when FO E is HIGH, and high impedance when FOE is LOW. 10:/IN T Out Alarm/timer /time update and other signal output. N-channel open drain output. 11:GN D Supply voltage negative(ground )connection 12：T2 Manufacturer test pin(not used for normal operation) 13:SDA I/O In I2C bus interface mode, SDA serial data input/output. Synchronized to the serial clock for address, data and acknowledge signal input/output. Connect an appropriate pull- up resistor according to the signal line capacitance. Notice: I:input O:output I/O:input/output A 0.1uF or larger bypass capacitor should be mounted between VDD and GND. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 3 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 5. ABSOLUTE MAXIMUM RATINGS Parameter Symbol Conditions Rating Unit Supply voltage VDD Between VDD and GND -0.3 — +6.5 V Input voltage1 Vin1 FOE -0.3 — VDD+0.3 V Input voltage2 Vin2 SCL, SDA -0.3 — +6.5 V Output voltage1 Vout1 FOUT -0.3 — VDD+0.3 V Output voltage2 Vout2 SDA, /INT -0.3 — +6.5 V Storage temperature TSTG -55 — +150 ℃ *1: Parameters must not exceed ratings, not even momentarily. If a rating is exceeded, there is a risk of IC failure, deterioration in characteristics, and decrease in reliability. *2: VDD value is the recommended operating voltage rating. 6. RECOMMENDED OPER ATING CONDITIONS Parameter Symbol Conditions MIN TYP MAX Unit Operating supply voltage VDD Serial interface operating 1.6 3.0 5.5 V Clock operating supply voltage VCLK Internal clock operating 1.4 3.0 5.5 V Temperature compensation VTEM Temperature 2.0 3.0 5.5 V -40 +25 +85 C operating supply voltage compensation operating Operating temperature Ta Operation outside the recommended operating conditions may adversely affect reliability. Use only within specified ratings. 7. ELECTRICAL CHARACTERISTICS 7.1 DC CHARACTERISTICS Parameter Current consumption1 Current consumption 2 Current consumption 3 Current consumption 4 Current consumption 5 Condition Sym bol IDD1 IDD2 IDD3 IDD4 /INT=VDD;FOE=GND FSCL=0Hz /INT,OE=VDD IDD5 FSCL=0Hz FOUT:32.768K,CL=0pF FSCL=0Hz Min Typ VDD=3V VDD=5V VDD=3V VDD=5V VDD=5V Max 0.75 0.60 2.5 1.5 7.5 Unit 3.4 2.1 6.0 3.0 μA 15.0 μA μA CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 4 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 Current consumption 6 I DD6 VDD=3V /INT,OE==VDD 4.5 9.0 FOUT:32.768K,CL=30pF H- level input voltage VIH1 FOE 0.8VDD 5.5 V VIH2 SCL&SDA 0.7VDD 5.5 V 0.0 0.3V V VDD=5V,I OH=-1mA 4.5 5.0 V VOH2 VDD=3V,IOH=-1mA 2.2 3.0 VOH3 VDD=3V,I OH=-100uA 2.9 3.0 VDD=5V,I OL=-1mA 0.0 0.5 VOL2 VDD=3V,I OL=1mA 0.0 0.8 VOL3 VDD=3V,I OL=100uA 0.0 0.1 VDD=5V,I OL=1mA 0.0 0.25 VDD=3V,I OL=-1mA 0.0 0.4 VDD≥2 V,I OL=3mA 0.0 0.4 -0.5 0.5 μA -0.5 0.5 μA L-level input voltage VIL H- level output voltage VOH1 L-level output voltage VOL1 VOL4 FOUT FOUT /INT VOL5 VOL6 SDA Input leakage current I LK VIN=VDD or GND Output leakage current I OZ /INT,SDA,FOUT, VIN=VDD or GND V V Unless specified,GND=0V, VDD=1.6-5.5V,Ta=-40--+85C;CL is the external load capacitance connected to FOUT. 7.2 AC CHARACTERISTICS Parameter Symbol SCL clock frequency fSCL Condition Min － Typ Max Unit 400 kHz Start condition setup time － 0.6 μs Start condition hold time － 0.6 μs Data setup time － 100 ns Data hold time － 0 Stop condition setup time － 0.6 μs － 1.3 μs － 1.3 μs － 0.6 μs Bus free time between Start tBUF 900 ns and Stop conditions SCL L- level pulse width SCL H- level pulse width SCL,SDA rise time tr － 0.3 μs CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 5 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 SCL,SDA fall time tf － 0.3 μs Allowable spike time on bus tSP － 50 ns Bus line load capacitance Cb VDD≥1.8V 400 pF 50 FOUT duty cycle VDD≤1.8V Duty 50% VDD 40 50 60 % Unless specified,GND=0V, VDD=1.6-5.5V,Ta=-40--+85C;CL is the external load capacitance connected to FOUT. Timing Diagram Note: Device access consists of a sequence of transmissions from the transfer of the Start condition until the transfer of the Stop condition, and which should be completed within 0.95 seconds. If the access exceeds 0.95 seconds, an internal monitor timer resets the RTC I2C-Bus interface. 7.3 CRYSTAL CHARACTERISTICS The crystal oscillator element must meet the following specifications to satisfy the oscillator characteristics. Parameter Symbol MIN TYP MAX Unit Equivalent series resistance R1 65 Frequency temperature coefficient B -0.04 10 -6/ °C Frequency accuracy ftol ±10 X10-6 Frequency turnover temperature Ti 30 °C 20 25 k CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 6 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 7.4 OSCILLATOR CHARACTERISTICS Par ameter Symbol Frequency tolerance Conditions Oscillation frequency fo Frequency-voltage f/V characteristic Oscillator start time tSTA tSTA MIN TYP Ta= -30 —70C VDD=3.0V Ta=+25 C, Ta=0-50C MAX Unit ±3.8*1 x10-6 VDD=3.0V ±5.0*2 32.768 kHz VDD=1.4 to 5.5V ±1.0 1.0 Ta=-40 to +85 C, 3.0 Ta=+25 C, x10-6/V VDD=2.0 to 5.5V, Ta=+25 C, VDD=1.6V S VDD=1.6 to 5.5V *1: Equivalent to an accuracy of within 8 seconds per month. *2: Equivalent to an accuracy of within 13 seconds per month. 7.5 SWITCHING TO AND FROM BACKUP Parameter Symbol Supply voltage de- Conditions MIN TYP MAX Unit VDET － 1.8 1.9 2.0 V VLOW － 1.3 1.4 1.5 V tr1 － 10 ms/V tf1 － 2 μs/V tr2 VCLK=1.4V→VDD≤3.6V 5 μs/V VCLK=1.4V→VDD>3.6V 15 μs/V tection / voltage 1*1 Supply voltage detection / voltage 1*2 Startup supply voltage rise time Supply fall voltage time when switching to backup CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 7 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 *1: If VDD falls below VDET, the internal detection circuit activates and disables the temperature compenstion. When this occurs, the value of the oscillator capacitance switching bits CL is maintained. When VDD rises above VDET again, the temperature compensation is enabled. *2: The device is equipped with a power-on reset circuit that initializes internal settings when power is first applied. En- 8. REGISTERS 8.1 REGISTER TABLE Address Function Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 0 SEC o 40 20 10 8 4 2 1 1 MIN o 40 20 10 8 4 2 1 2 HOUR o o 20 10 8 4 2 1 3 WEEK o 6 5 4 3 2 1 0 4 DAY o o 20 10 8 4 2 1 5 MONTH o o o 10 8 4 2 1 6 YEAR 80 40 20 10 8 4 2 1 7 RAM 8 MIN Alarm AE 40 20 10 8 4 2 1 9 HOUR Alarm AE 20 10 8 4 2 1 5 4 3 2 1 0 20 10 8 4 2 1 32 16 8 4 2 1 2048 1024 512 256 A WEEK Alarm DAY Alarm B Timer Counter 0 C Timer Counter 1 D AE 128 Extension TEST Register E Flag Register o F Control Register CSEL1 6 64 WAD A o CSEL 0 USEL TE FSEL1 FSEL0 TSEL1 TSEL0 UF TF AF o VLF VDET UIE TIE AIE o o RESET CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 8 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 *1: The register values are undefined when the power supply is turned on, so programming the registers is required before operation. When programming the registers, take care not to program the date and time with invalid values. Clock operation is not guaranteed if you fail to do so. *2: The TEST bit is for manufacturer testing only. Always set the TEST bit to “0” for normal operation. *3: Bits marked “○” are read-only bits with a read value of “0.” Bits marked “ ” are read/write bits that can be used as RAM bits. *4: Addresses 8 to A can be used as RAM if the alarms are not used (AIE set to “0”). *5: Reading a timer counter (Addresses B and C) allows you to read the specified preset data value.Also, Addresses B and C can be used as RAM if the timers are not used (TE and TIE set to “0”). *6: O nly data “0” can be written to the UF, TF, AF, VLF, and VDET bits. *7: When the power supply is turned on, the VLF and CSEL0 bits are set to “1”, and the TEST, FSEL1,FSEL0, CSEL1, UIE, TIE, and AIE bits are set to “0.” 8.2 REGISTER DESCRIPTION 8.2.1 TIME AND CALENDAR REGISTER TABLE Data format Data is in BCD format. So, for example, a register 0 (SEC) value of “0101 1001” represents 59 seconds. The clock time represents 24-hour mode (fixed). YEAR register and leap years The next value of register 6 (YEAR) after 99 is 00. A leap year is registered when the value of the two BCD digits divided by 4 has a remainder of 0. Year 00 is also processed as a leap year. The calendar is valid up to the year 2099. Day of week (WEEK) register Register 3 (WEEK) has 7 bits (bit 0 to bit 6), where each bit has been assigned the value shown in the following table. Do not set multiple bits to “1” simultaneously. Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 1 Day of Week Sunday 0 0 0 0 0 1 0 Monday 0 0 0 0 1 0 0 Tuesday 0 0 0 1 0 0 0 Wednesday 0 0 1 0 0 0 0 Thursday 0 1 0 0 0 0 0 Friday 1 0 0 0 0 0 0 Saturday 8.2.2 ALARM REGISTER s (REGISTER s 8 to A) Address Function Bit 7 8 MIN A larm AE 9 HOUR Ala rm AE A Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 40 20 10 8 4 2 1 20 10 8 4 2 1 5 4 3 2 1 0 20 10 8 4 2 1 . WEEK Ala rm DA Y A larm 6 AE . CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 9 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 The alarms can be specified by day of week, day of month, hour, and minute. The WADA bit in register D specifies which parameter (day of week or day of month) is used for the alarms. Each alarm register has an AE (Alarm Enable) bit (bit 7). Using these bits allows you to easily set hourly alarms and daily alarms. Alarms can be set for multiple days of the week. When an AE bit is set to “0,” the values of the corresponding register and clock register are compared. When the AE bit is set to “1,” the data is treated as “Don’t care” bits and the digits are always considered a match. When an alarm is triggered, the AF (Alarm Flag) bit in register E is set to “1.” At that time, a LOW-level interrupt signal is output on the IRQN output if the AIE (Alarm Interrupt Enable) bit in register F is set to “1.” If the AIE bit is set to “0,” the alarm interrupt output from IRQN is disabled. If alarm interrupts are not used, addresses 8 to A can be used as memory registers. Set the AIE bit to “0” to disable the alarm operation and the interrupt function. Day-of-week (WEEK) alarm bits Function Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Day of week Sat Fri Thu Wed Tue Mon Sun Bit 5 32 Bit 4 16 8.2.3 TIMER COUNTER Address B C Function Time r Counter 0 Bit 7 128 Bit 6 64 Time r Counter 1 Bit 3 8 Bit 2 4 Bit 1 2 Bit 0 1 2048 1024 512 256 These registers control a 12-bit, internal, preset table down-counter used for timer interrupts. The down-counter count cycle (source clock) is specified using the TSEL0 and TSEL1 bits in register D, and the down-counter preset value (frequency divider) is set using Timer Counters 0 and 1. When the TE bit in register D is set to “0,” the preset table down-counter is loaded with the contents specified by the Timer Counters and the count is stopped. Subsequently, the count starts when the TE bit is set to “1.” The down-counter counts down in sync with the source clock cycle until the data becomes zero, at which point the TF (Timer Flag) bit in register E is set to “1.” At that time, a LOW-level interrupt signal is output on the IRQN output if the TIE (Timer Interrupt Enable) bit in register F is set to “1.” If the TIE bit is set to “0,” the output from IRQN is disabled. Next, the Timer Counter register data is reloaded and the count down starts again in a continuous cycle. Timer interrupts are not output from the IRQN output when the TE bit in register D is set to “1” and theTimer Counters are set with “0” data. And both the TE and TIE bits must be set in order for expected timer operation. If timer interrupts are not used, addresses B and C can be used as memory registers. Set the TE and TIE bits to “0”to disable timer operation and the interrupt function. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 10 • May 2014 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ISO 9001:2008 ● Timer interrupt source clock selection TSEL1 0 TSEL0 0 Source clock 4096 Hz 0 1 64 Hz 1 0 1 Hz 1 1/60Hz (1-minute digit update) 1 * The register value is undefined when the power supply is turned on. ● Timer interrupt interval Timer- Source clock counter set value 4096Hz 64Hz Second update Minute update TSEL1,0=0,0 TSEL1,0=0,1 TSEL 1,0=1,0 TSEL 1,0=1,1 0 1 244.14 s 15.625 ms 1s 1 min 2 488.28 s 31.25 ms 2s 2 min ● ● ● ● ● ● ● ● ● ● 41 10.010 ms 640.63 ms 41 s 41 min 82 20.020 ms 1.281 s 82 s 82 min 128 31.250 ms 2.000 s 128 s 128 min 192 46.875 ms 3.000 s 192 s 192 min 205 50.049 ms 3.203 s 205 s 205 min 320 78.125 ms 5.000 s 320 s 320 min 410 100.10 ms 6.406 s 410 s 410 min 640 156.25 ms 10.000 s 640 s 640 min 820 200.20 ms 12.813 s 820 s 820 min 1229 300.05 ms 19.203 s 1229 s 1229 min 1280 312.50 ms 20.000 s 1280 s 1280 min 1920 468.75 ms 30.000 s 1920 s 1920 min 2048 500.00 ms 32.000 s 2048 s 2048 min 2560 625.00 ms 40.000 s 2560 s 2560 min 3200 0.7813 s 50.000 s 3200 s 3200 min 3840 0.9375 s 60.000 s 3840 s 3840 min ● ● ● ● 4095 0.9998 s ● ● 63.984 s ● ● 4095 s ● ● 4095 min CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 11 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] 8.2.4 CONTROL REGISTER AND FLAG REGISTER Address Function Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 D Extension Regis- TEST WAUSEL TE FSEL1 FSEL0 TSEL1 ter DA E Flag Register ○ ○ UF TF AF ○ VLF F Control Register CSEL1 CSEL0 UIE TIE AIE ○ ○ Bit 0 TSEL0 VDET RESET ●TEST bit Manufacturer’s test bit. Always set to “0” for normal operation. Take care not to accidentally write a value “1” to this bit when writing to the other bits in register D. If the bit is set to “1,” it is cleared when a Stop condition is received and at each repeated Start condition. ●WADA bit (Week Alarm/Day Alarm) Day-of-week/Day-of- month alarm bit. When this bit is set to “0,” the setting of register A is interpreted as a day-of-week alarm. When set to “1,” register A is interpreted as a day-of- month alarm. ●USEL bit (Update Interrupt Select) Specifies the timing for generating time update interrupts. The register value is undefined when the power supply is tuned on. If the UF flag in register is cleared when an interrupt is generated or within the automatic return time, then the interrupt line is also cleared. Time update interrupts are disabled when the RESET bit in register F is set to “1.” Interrupts generated in1Hz mode are not synchronized to the internal clock (they are generated independently using a 1Hz frequency divider circuit). [Time update interrupt timing selection] Auto return time USEL Timing 0 1Hz 500ms 1 1/60Hz (1-minute digit update) 7.81ms ●TE bit (Timer Enable) The presettable counter starts counting down when this bit is set to “1.” The counter stops counting when this bit is set to “0.” ●FSEL bit (FOUT Frequency Select) Specifies the output frequency of the FOUT output signal. The register value is set to “00” (32.768kHz) when the power supply is turned on. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 12 • May 2014 ISO 9001:2008 FSEL1 0 0 1 1 FSEL0 0 1 0 1 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] FOUT frequency 32.768kHz 1024Hz 1Hz 32.768kHz ● AF, TF, UF bits (Alarm Flag, Timer Flag, Update Flag) The AF bit in register is set to “1” when an alarm is generated. The TF bit is set to “1” when the down-counter for timer interrupts reaches zero. The UF bit is set to “1” after a time update ends. The data is maintained until “0” is written to these bits. A value of “1” cannot be written to these bits. ● AIE, TIE, UIE bits (Alarm, Timer, Update Interrupt Enable) AIE corresponds to alarm interrupts, TIE corresponds to timer interrupts, and UIE corresponds to time update interrupts. When AIE ,TIE,UIE are set to “1”,The interrupt signal on the /INT is the alarm, timer, and time update interrupts. When set to “0”,no interrupt occurs. The AIE, TIE, and UIE bits are cleared to “0” when the power supply is turned on. ● VLF bit (Voltage Low Flag) If a clock operating supply voltage drop occurs or a power-on reset event occurs, as detected by the voltage crossing the VLOW threshold (1.5V max.), the VLF bit changes from “0” to “1” and the value is maintained until a “0” is written to this bit. A value of “1” cannot be written to this bit. The VLOW supply voltage detection function runs in time-share with the temperature compensation operation interval timing in order to limit the current consumption. ● VDET (Voltage Detect Flag) If a temperature compensation operating supply voltage drop occurs, as detected by the voltage crossing the VDET threshold (2.0V max.), the VDET bit changes from “0” to “1” and the value is maintained until a “0” is written to this bit. A value of “1 ” cannot be written to this bit. ●CSEL bit Specifies the temperature compensation operation interval. CSEL1 CSEL0 Operation interval 0 0 0.5s 0 1 2s 1 0 10s 1 1 30s Note that temperature compensation operation and VLF/VDET supply voltage detection operation is disabled when the RESET bit is set to “1.” CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 13 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] ●RESET bit The counters stops operating and counter value inside RTC reset when the RESET bit is set to “1.” and hold to 1 second min, After writing “1” to this bit, the reset is cleared when a Stop condition is received, at repeated Start conditions, and after the 0.95s I2C-Bus interface reset time. Also, the VLF and VDET flags are cleared in order to initialize the supply voltage detection circuit. (Reset bit from “1” to “0”) 9. INTERRUPTS 9.1 ALARM INTERRUPTS (1) Alarms can be set by the day-of week or day-of- month, hour, and minute. The WADA specifies whether the day-ofweek or day-of-month is used for the alarm (2) First, the AIE bit be set to “0” in order to avoid unintended hardware (3) Next, set the alarm data and then clear the AF flag to initialize the alarm circuit. (4) AIE is set to “1” 1) when time update to interrupt, AF is set to ”1” 2) when AF bit is “1”,it keeps till AF is written to “0” 3) when AIE is “1”,if alarm interrupt occurs,/IN T output will be driven to low level. 4) when/INT is low level, if AIE is set from “1” to “0”, /INT will be changed to high impedance. 5) when alarm interrupt occurs, if AIE is “0”,/IN T will be kept in high impedance. interrupts while configuring an alarm. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 14 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] 9.2 TIME INTERRUPTS The timer interval can be set to a value in the range 1/4096 seconds (min) to 4095 minutes (max). Configuration method: 1) First, it is recommended that TIE be set to “0” in order to avoid unintended hardware interrupts while configuring the timer. 2) Set B/C register just to set initial value of down counter,then TF flag is zero. 3) Set TIE,TE to “1” (1) If TE bit is “1”, the timer starts counting from the falling edge of the clock (2) The timer starts counting down from the value set in the Timer Counters in sync with the source clock cycle spe- cified by TSEL0 and TSEL1 in register D. When the timer reaches zero, a LOW- level interrupt is generated . (3) when timer interrupts generates, TF changes to “1” (4) when TF bit is “1”,it will continue (5) When an interrupt is generated, the I/INT output goes LOW if the TIE bit is set to “1.” If TIE is “0,” the till it is written to “0” /INT output goes high impedance and the TF is maintained set to “1.” (6) In return time (tRTN) period,/IN T output maintain low level, after tRTN , it is high impedance.Before next inter- rupt,/IN T is set to low. (7) when TE is written “0”, timing stops and /INT is high impedance. when /INT is low level, timing stops.Max period for /INT in low is tRTN, then to high impedance. (8) If /INT is low, TF bit changes from “1” to “0”, /INT change from low level to high impedance. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 15 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] tRTN sheet: Source clock 4096Hz Auto retur n time (t RTN) 0.122ms 64Hz 7.81ms 1Hz 7.81ms 1/60Hz *1 7.81ms 9.3 TIME UPDATE INTERRUPTS Time update interrupts generate interrupt signal every second or every minute,same with internal clock. Configuration method follows: (1) (2) First, it is recommended that TIE be set to “0” in order to avoid unintended hardware interrupts while configuring the timer. then set USEL as second update or minute update, initialize UF flag to “0” (3) set UIE to “1” Time update interrupt diagram: （1）when internal clock time match with second update or minute update, time update interrupt occurs. （2）when time update interrupt generate, UP bit is “1” （3）when UF is set to “1”, it keeps maintained set till it is cleared to “0” （4）when time update interrupt generate, if UIE=“1”，/INT output is low level. If UIE=“0”， /INT is still high impedance. （5）when interrupt generate,/INT output is low, duration is tRTN（minute update interval is 7.8125ms， second update interval is 500ms）then it change to high impedance automatically. （6）when /INT is low, /INT pad state is not changed, even UF bit is set from “1” to “0”. （7）when /INT is low, and UIE is set from“1”to“0”，/INT pad state change from low level to high impedance. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 16 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] 10. I2C-BUS SERIAL INTERFACE 10.1 I2C-BUS INTERFACE CHARACTERISTICS The I2C-Bus is a 2-wire bidirectional communications interface. The signal lines consist of SDA (data line) and SCL (clock line), and both lines are connected to the VDD line through pull -up resistors. All ports connected to the I2C-Bus must be open-drain or open-collector to enable logical-AND connection of multiple devices. 10.2 BIT TRANSFER 1-bit data is transferred for every clock pulse on the SCL line. When transmitting, the data on the SDA line changes during the interval when the SCL is LOW. When receiving, the data is read during the interval when the SCL line is HIGH. 10.3 START CONDITION AND STOP CONDITION Both the SDA and SCL lines are held HIGH when there is no communication on the I2C-Bus. A HIGH to LOW transition on the SDA line while SCL is HIGH defines the “Start condition,” after which data is transferred. A LOW to HIGH transition on SDA while SCL is HIGH defines the “Stop condition.” 10.4 SLAVE ADDRESS I2C-Bus devices do not have the chip select input such as is found on ordinary logic devices. Instead, all I2C-Bus devices have a fixed, unique device number for each device type already stored internally. The I2C-Bus device chip select function is achieved by sending the device number at the start of communication as a slave address on the I2C-Bus. The receiving device, matching the slave address, can then respond to the communication. The slave address consists of seven bits (0110 010) CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 17 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] During communication, the slave address is appended with a R/W (read/write) bit and sent as 8-bit data. 10.5 SYSTEM CONFIGURATION The device that controls the transmission of messages is called the “master” and the device controlled by the master is called the “slave.” The device sending the message is called the “transmitter” and the device receiving the message is called the “receiver.” In a PTRTC1010 configuration, the CPU or other controller is the master and the PTRTC1010 is the slave. Both master and slave alternately become the transmitter and receiver. 10.6 ACKNOWLEDGE SIGNAL On the I2C Bus, there is no restriction on the number of bytes sent between the Start condition and Stop condition. After each byte is transferred, the receiver generates an acknowledge bit to confirm that the data from the transmitter was received. The acknowledge bit is an active-LOW signal, and to receive it the transmitter sets the SDA line HIGH and transmits a clock pulse for the acknowledge bit. If the receiver has successfully received the 8-bit data sent from the transmitter, the receiver sets the SDA line LOW when the clock pulse for the final bit ends. Since the I2C-Bus lines have pull-up resistors, the SDA line also goes LOW at the transmitter. The transmitter recognizes this as the acknowledge signal, and can then send the next data. The receiver sets the SDA line HIGH (open) when the clock pulse for the acknowledge bit ends in preparation to receive the next data. Transmission ends if the master is the transmitter and generates the Stop condition instead of sending more data after the acknowledge signal from the receiver is recognized. Transmission also ends if the master is the receiver and generates the Stop condition after sending a “1” as the acknowledge bit. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 18 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] 10.7 I2C-BUS CONTROL This section describes the communication sequence with the CPU as the master and the PTRTC1010 as the slave. 10.7.1 WRITE SEQUENCE FOR A SPECIFIED ADDRESS The CCRTC-11 has an address auto-increment function. The device address is specified once at the beginning, and afterward only data bytes are sent. After each byte, the PTRTC1010 address is automatically incremented. (1) CPU transmits the Start condition.(S) (2) CPU transmits the PTRTC1010 slave address and R/W bit set to write mode. (3) PTRTC1010 generates the acknowledge signal. (4) CPU transmits the address to write to the PTRTC1010. (5) PTRTC1010 generates the acknowledge signal. (6) CPU transmits data to the address specified in (4). (7) PTRTC1010 generates the acknowledge signal. (8) Steps (6) and (7) repeated as required. The address to write automatically increments in the PTRTC1010. (9) CPU transmits the Stop condition (P). 10.7.2 READ SEQUENCE FOR A SPECIFIED ADDRESS After writing to an address in write mode, the CPU can read the data back by setting the mode to read mode. (1) CPU transmits the Start condition. (2) CPU transmits the PTRTC1010 slave address and R/W bit set to write mode. (3) PTRTC1010 generates the acknowledge signal. (4) CPU transmits the address to read to the PTRTC1010. (5) PTRTC1010 generates the acknowledge signal. (6) CPU transmits the Start condition again, without sending the Stop condition. (7) CPU transmits the PTRTC1010 slave address and R/W bit set to read mode. (8) PTRTC1010 generates the acknowledge signal. From this point, the CPU is the receiver and the PTRTC1010 is the transmitter. (9) PTRTC1010 transmits the register data for the address specified in (4). (10) CPU transmits the acknowledge signal to the PTRTC1010. (11) Steps (9) and (10) repeated as required. The address to read automatically increments in the PTRTC1010. (12) CPU transmits the acknowledge signal to the PTRTC1010. (13) CPU transmits the Stop condition. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 19 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] 10.7.3 READ SEQUENCE FOR A SPECIFIED ADDRESS The master can read all data by setting the R/W bit to read mode at the beginning. The address to read is determined by incrementing the previously accessed address. (1) CPU transmits the Start condition. (2) CPU transmits the PTRTC1010 slave address and R/W bit set to read mode. (3) PTRTC1010 generates the acknowledge signal. From this point, the CPU is the receiver and the PTRTC1010 is the transmitter. (4) CF8591 increments the previously accessed address and transmits the register data. (5) CPU transmits the acknowledge signal to the PTRTC1010. (6) Steps (4) and (5) repeated as required. The address to read is automatically incremented in the PTRTC1010. (7) CPU transmits the acknowledge signal to the PTRTC1010. (8) CPU transmits the Stop condition. CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 20 • May 2014 ISO 9001:2008 PETERMANN-TECHNIK GmbH Lechwiesenstr. 13 D-86899 Landsberg am Lech Fon: +49/8191/305395 Fax: +49/8191/305397 www.petermann-technik.com [email protected] 11. PACKAGE AND PCB LAYOUT: CRYSTALS CERAMIC FILTERS OSCILLATORS SAW COMPONENTS CERAMIC RESONATORS PREMIUM QUALITY BY PETERMANN-TECHNIK Spec.01 • Page 21 • May 2014