PIC32MX575/675/695/775/795 Family Errata and Datasheet Clarification

PIC32MX575/675/695/775/795
PIC32MX575/675/695/775/795 Family
Silicon Errata and Data Sheet Clarification
The PIC32MX575/675/695/775/795 family devices that
you have received conform functionally to the current
Device Data Sheet (DS60001156H), except for the
anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in Table 1. The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the PIC32MX575/675/695/775/795
silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated in the last column of
Table 2 apply to the current silicon
revision (A5).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
5.
Data Sheet clarifications and corrections start on page
15, following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB® IDE and Microchip’s programmers, debuggers and emulation tools, which are
available at the Microchip corporate web site
(www.microchip.com).
TABLE 1:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
The Device and Revision ID values for the various
PIC32MX575/675/695/775/795 silicon revisions are
shown in Table 1.
SILICON DEVREV VALUES
Part Number
Device ID(1)
PIC32MX575F256H
0x4317053
PIC32MX675F256H
0x430B053
PIC32MX775F256H
0x4303053
PIC32MX575F512H
0x4309053
PIC32MX675F512H
0x430C053
PIC32MX695F512H
0x4325053
PIC32MX775F512H
0x430D053
PIC32MX795F512H
0x430E053
PIC32MX575F256L
0x4333053
PIC32MX675F256L
0x4305053
Note 1:
Note:
Using the appropriate interface, connect
the device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you
are using, do one of the following:
a) For MPLAB IDE 8, select Programmer >
Reconnect.
b) For MPLAB X IDE, select Window >
Dashboard, and then click the Refresh
Debug Tool Status icon (
).
Depending on the development tool used,
the part number and the Device and
Revision ID values appear in the Output
window.
Revision ID for Silicon Revision(1)
A0
A1
A3
A4
A5
0x0
0x1
0x3
0x4
0x5
Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001156H) for detailed information on Device and Revision IDs for your specific device.
 2009-2013 Microchip Technology Inc.
DS80000480N-page 1
PIC32MX575/675/695/775/795
TABLE 1:
SILICON DEVREV VALUES (CONTINUED)
Device ID(1)
Part Number
PIC32MX775F256L
0x4312053
PIC32MX575F512L
0x430F053
PIC32MX675F512L
0x4311053
PIC32MX695F512L
0x4341053
PIC32MX775F512L
0x4307053
PIC32MX795F512L
0x4307053
Note 1:
TABLE 2:
Module
Revision ID for Silicon Revision(1)
A0
A1
A3
A4
A5
0x0
0x1
0x3
0x4
0x5
Refer to the “Memory Organization” and “Special Features” chapters in the current Device Data Sheet
(DS60001156H) for detailed information on Device and Revision IDs for your specific device.
SILICON ISSUE SUMMARY
Feature
Item
#
Affected Revisions(1)
Issue Summary
A0
A1
A3
A4
A5
I2C™
—
1.
The SDA line state may not be detected correctly.
X
X
Ethernet
RMII 10 MB
2.
Pause frames are sent at 10 times the normal rate.
X
X
X
X
X
ADC
Interrupt
Generation
3.
The interrupt generated by the module cannot be
cleared when the module is disabled.
X
X
X
X
X
Parallel
Master
Port
Slave Mode
4.
A PMP interrupt used to wake the device will not be
reflected in the interrupt flag until the end of the write
strobe.
X
X
X
X
X
Output
Compare
Electrical
Specification
5.
Output Compare Fault detection is not
asynchronous.
X
X
X
X
X
SPI
—
6.
The SPIBUSY and SRMT bits assert 1 bit time
before the end of the transaction.
X
X
X
X
X
UART
—
7.
The UTXBF bit deasserts one Peripheral Bus (PB)
clock after the interrupt is generated.
X
X
X
X
X
USB
USB PLL
8.
The USBPLL does not automatically suspend in Idle
mode.
X
X
X
X
X
Output
Compare
PWM
9.
In PWM mode, the output waveform is one PB clock
longer than the expected value.
X
X
X
X
X
Output
Compare
PWM Fault Input
Mode
10.
A Fault interrupt will not be generated if firmware
clears the Fault while the Fault is still asserted.
X
X
X
X
X
DMA
Pattern Match
11.
In Pattern Match mode, the DMA module may not
append all of the CRC results to the result buffer.
X
X
X
X
X
Timers
External Clock
12.
In Synchronized External Clock mode, the first
period of the count is short.
X
X
X
X
X
SPI
Frame Slave
Mode
13.
Outgoing data corruption occurs when the frame
signal is coincident with the clock.
X
X
X
X
X
CAN
—
14.
TXABAT, TXLARB, and TXERR bits may
erroneously be cleared by an aborted read of the
CxFIFOCONn register.
X
X
X
X
X
CAN
—
15.
Requested aborts to a TX message via setting the
ABAT (CxCON<27>) bit or clearing the TXREQ
(CxFIFOCON<3>) bit may not complete.
X
X
X
X
X
Note 1:
2:
Only those issues indicated in the last column apply to the current silicon revision.
This issue has been corrected for this revision of silicon. Refer to the specific issue for details regarding the
correction.
DS80000480N-page 2
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
TABLE 2:
Module
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Item
#
Affected Revisions(1)
Issue Summary
A0
A1
A3
A4
A5
CAN
—
16.
The FRESET (CxFIFOCONn<14>) and UINC
(CxFIFOCONn<13>) bits are not settable via a
normal SFR write.
X
X
X
X
X
CAN
DeviceNet™
17.
DeviceNet™ filtering does not function.
X
X
X
X
X
Output
Compare
PWM Fault Input
Mode
18.
A Fault may be erroneously cleared due to an
aborted read.
X
X
X
X
X
SPI
Slave Mode
19.
In Slave mode with the STXISEL (SPIxCON<3:2>)
bits = 00, a TX buffer underrun condition will not
assert the TX interrupt flag.
X
X
X
X
X
USB
—
20.
The TOKBUSY bit does not correctly indicate status
when a transfer completes within the Start of Frame
(SOF) threshold.
X
X
X
X
X
USB
Host Mode
21.
In Host mode, the interval between the first two SOF
packets may be less than what is specified by the
USB specification.
X
X
X
X
X
Watchdog
Timer
—
22.
When code-protect is enabled, the WDT is not held
in Reset during the POR RAM Clear Sequence
(RCS).
X
X
X
X
X
Oscillator
Clock Switch
and Two -Speed
Start-Up
23.
Clock switching and Two-Speed Start-up may cause
a general exception when the reserved bit 8 of the
DDPCON register is ‘0’.
X
X
X
X
X
Oscillator
Clock Switch
24.
Clock source switching may cause a general
exception or POR when switching from a slow clock
to a fast clock.
X
X
X
X
X
SPI
Slave Mode
25.
A wake-up interrupt may not be clearable.
X
X
X
X
X
PORTS
—
26.
I/O pins do not tri-state immediately, if previously
driven high.
X
X
X
X
X
SPI
—
27.
Byte writes to the SPIxSTAT register are not
decoded correctly.
X
X
X
X
X
SPI
Frame Mode
28.
Recovery from an underrun requires multiple SPI
clock periods.
X
X
X
X
X
CAN
—
29.
The TXABAT bit status may be incorrect after an
abort.
X
X
X
X
X
UART
IrDA®
30.
The IrDA minimum bit time is not detected at all
baud rates.
X
X
X
X
X
UART
IrDA
31.
Transmit (TX) data is corrupted when BRG values
greater than 0x200 are used.
X
X
X
X
X
JTAG
—
32.
On 64-pin devices, the TMS pin requires an external
pull-up.
X
X
X
X
X
UART
—
33.
The TRMT (UxSTA<8>) bit is asserted before the
transmission is complete.
X
X
X
X
X
UART
UART Receive
Buffer Overrun
Error Status
34.
The OERR (UxSTA<1>) bit does not get cleared on
a module Reset. The OERR bit retains its value
even after the UART module is reinitialized.
X
X
X
X
X
ADC
Conversion
Trigger from
INT0 Interrupt
35.
The ADC module conversion triggers occur on the
rising edge of the INT0 signal even when INT0 is
configured to generate an interrupt on the falling
edge.
X
X
X
X
X
Note 1:
2:
Only those issues indicated in the last column apply to the current silicon revision.
This issue has been corrected for this revision of silicon. Refer to the specific issue for details regarding the
correction.
 2009-2013 Microchip Technology Inc.
DS80000480N-page 3
PIC32MX575/675/695/775/795
TABLE 2:
Module
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Item
#
Affected Revisions(1)
Issue Summary
A0
A1
A3
A4
A5
JTAG
Boundary Scan
36.
Pin 100 on 100-pin packages and pin A1 on 121pin packages do not respond to boundary scan
commands.
X
X
X
X
X
DMA
Suspend Status
37.
The DMABUSY status bit (DMACON<11>) may not
reflect the correct status if the DMA module is
suspended.
X
X
X
X
X
Voltage
Regulator
BOR
38.
Device may not exit BOR state if a BOR event
occurs.
X
X
Output
Compare
PWM Mode
39.
If the Output Compare module is configured for a 0%
duty cycle (OCxRS = 0), a glitch may occur on the
next cycle.
X
X
X
X
X
Oscillator
Clock Switch
40.
If a Fail-Safe Clock Monitor (FSCM) event occurs
when Primary Oscillator (POSC) mode is used,
firmware clock switch requests to switch from FRC
mode will fail.
X
X
X
X
X
I2C
Slave Mode
The I2C module does not respond to address 0x78
41. when the STRICT and A10M bits are cleared in the
I2CxCON register.
X
X
X
X
X
USB
Idle Interrupt
42.
X
X
X
X
X
CPU
Constant Data
Access from
Flash
A Data Bus Exception (DBE) may occur if an
43. interrupt is encountered by the CPU while it is
accessing constant data from Flash memory.
X
X
X
See See
Note Note
2
2
CPU
Data Write to a
Peripheral
A data write operation by the CPU to a peripheral
44. may be repeated if an interrupt occurs during initial
write operation.
X
X
X
See See
Note Note
2
2
Oscillator
Clock Out
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of the
45.
CLKO Enable Configuration bit, during a Power-on
Reset (POR) condition.
X
X
X
X
X
Input
Capture
Idle Mode and
Sleep Mode
All input capture modes selectable by the ICM<2:0>
(ICxCON<2:0>) bits, with the exception of Interrupt46.
only mode, will not work when the CPU enters Idle
mode or Sleep mode.
X
X
X
X
X
USB
Host
The USB bus might not be returned to the
47. J-state following an acknowledgment packet when
running low-speed through a hub.
X
X
X
X
X
Non-5V
Tolerant
Pins
Pull-ups
Internal pull-up resistors may not guarantee a logical
48. ‘1’ on non-5V tolerant pins when they are configured
as digital inputs.
X
X
X
X
X
5V Tolerant
Pins
Pull-ups
Internal pull-up resistors may not guarantee a logical
49. ‘1’ on 5V tolerant pins when they are configured as
digital inputs.
X
X
X
X
X
Note 1:
2:
Idle interrupts cease if the IDLEIF interrupt flag is
cleared.
Only those issues indicated in the last column apply to the current silicon revision.
This issue has been corrected for this revision of silicon. Refer to the specific issue for details regarding the
correction.
DS80000480N-page 4
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A5).
1. Module: I2C™
The I2C modules, with the exception of I2C1 and
I2C2, may not detect state of SDA line correctly:
Slave Mode:
The I2C master device on the bus must either pull
the SDA line low, and then high again, prior to
sending the first packet to the device, or must
resend the first packet.
Affected Silicon Revisions
A0
A1
X
X
A3
A4
A5
2. Module: Ethernet
• In Master mode, module may encounter a bus
collision when performing a Start condition.
• In Slave mode, module may not Acknowledge
the first packet sent after enabling the I2C
module. In this case, it will return a NACK
instead of an ACK.
In 10 MB RMII mode only, pause frames are sent
at 10 times the normal rate. This reduces the
available network bandwidth if the device is
connected to the network via a hub. This does not
reduce functionality or violate specifications.
Work around
If bandwidth is a concern, connect the PIC32
device to a network using an Ethernet switch.
Master Mode:
1.
2.
Use another I2C node on the bus to
sequence I2C bus transactions such as the
Start event.
Connect an unused general-purpose I/O
pin to the SDAx pin of the I2C module to be
used.
The user software must perform the following sequence of operations in order to
execute a Start condition on the I2C bus:
a) With the I2C module disabled, clear the
LAT bit of the general-purpose I/O pin
that is connected to the SDAx pin.
Then, clear the corresponding TRIS bit
to make sure the I/O pin is pulled low.
b) Enable the I2C module by setting the
ON (I2CxCON<15>) bit; but do not
configure the I2CxBRG register at this
time.
c) Execute a software delay loop of at
least 10 µs.
d) Set the TRIS bit of the I/O pin connected to the SDAx pin. This will make
it an input pin, thereby ensuring that it
goes to a high logic state.
e) Execute a software delay loop of at
least 10 µs.
f) Configure the I2CxBRG register with
the value required by the application.
g) Issue a Start condition by setting the
SEN (I2CxCON<0>) bit as needed. I2C
communications can now proceed
normally.
 2009-2013 Microchip Technology Inc.
Work around
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
3. Module: ADC
The interrupt generated by the ADC module
cannot be cleared when the ADC module is
disabled.
Work around
Ensure the interrupt is serviced and the interrupt
flag is cleared before turning off the ADC module.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 5
PIC32MX575/675/695/775/795
4. Module: Parallel Master Port
In Slave mode, a PMP interrupt will wake the
device; however, the interrupt source will not be
reflected in the interrupt flag until the end of the
write strobe.
Work arounds
There are two possible solutions to this issue:
1.
If multiple wake-up sources are to be used,
firmware can poll all of the configured wakeup source interrupt flags. If none are set,
assume the source was the PMP.
Firmware can wait for a period exceeding
the write strobe length, and then poll the
PMP interrupt flag.
2.
7. Module: UART
The UTXBF (UxSTA<9>) bit clears one PB clock
cycle after the interrupt is generated. When using
a PB bus divisor other than 1:1 and polling the
UART transmit interrupt flag with the next
instruction reading the UTXBF bit, the result may
not reflect the actual UTXBF status.
Work arounds
There are two possible solutions to this issue:
1.
2.
Only use a PB bus divisor of 1:1.
If firmware is polling the transmit interrupt
flag and the UTXBF flag, insert a read of the
UxSTA register between these operations
and discard the result. This read will ensure
the status of the UTXBF flag is correct when
the next read of this register occurs.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
5. Module: Output Compare
The Fault input detection is not asynchronous.
There is a one to two Peripheral Bus (PB) clock
delay between the Fault input assertion and the
shutdown of the appropriate Output Compare
output pin.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
8. Module: USB
When the USBSIDL (UxCNFG1<4>) bit is set, the
USBPLL does not automatically suspend in Idle
mode.
Work around
Work around
Ensure that the device driven by the Output
Compare module can tolerate this shutdown delay.
Use firmware to manually suspend the USB clock
before entering Sleep mode.
Affected Silicon Revisions
Affected Silicon Revisions
A0
A1
A3
A4
A5
A0
A1
A3
A4
A5
X
X
X
X
X
X
X
X
X
X
6. Module: SPI
9. Module: Output Compare
The SPIBUSY (SPIxCOn<11>) and SRMT
(SPIxCON<7>) bits assert one bit time before the
end of the transaction.
Note:
SPI operation with the DMA module
is not affected by this issue.
In PWM mode, the output waveform is one Peripheral Bus (PB) clock longer than the expected
value.
Work around
Work arounds
Load OCxRS with a value one less than the
number expected to achieve the desired output.
There are two possible solutions to this issue:
Affected Silicon Revisions
1.
Firmware must provide a one bit time delay
between the assertion of these bits and performing any operation that requires the
transaction to be complete.
Use DMA module to transfer data to/from
SPI module.
2.
A0
A1
A3
A4
A5
X
X
X
X
X
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 6
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
10. Module: Output Compare
In PWM mode, if firmware attempts to clear the
OCFLT (OCxCON<4>) bit while the Fault still
exists, a second interrupt will not be generated for
this Fault when firmware exits the Interrupt Service
Routine (ISR). The OCFLT bit will remain set while
a Fault is detected.
Work around
In the ISR, clear the OCFLT bit, and test the
OCFLT bit before exiting the ISR. If the bit is set,
set the OCx interrupt to generate a second
interrupt.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
11. Module: DMA
In Pattern Match mode, the DMA module may not
append all of the CRC results to the result buffer.
Work around
Use firmware to read the CRC result and append
it to the result buffer.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
12. Module: Timers
When the Timer module is first enabled and the
prescaler value is greater than one, the number of
input clocks required to increment the timer from
zero to one is one input clock, not the value stated
by the prescaler.
13. Module: SPI
Outgoing data will be corrupted when in Frame
Slave
mode
with
the
FRMCNT<2:0>
(SPIxCON<26:24>) bits greater than zero and the
Frame pulse is coincident with the clock.
Work around
1. There is no work around for operation when
the Frame pulse is coincident with the clock.
2. Provide a frame signal that precedes the clock
signal.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
14. Module: CAN
The TXABAT, TXLARB, and TXERR bits may
erroneously be cleared by an aborted read of the
CxFIFOCONn register. An aborted read occurs
when a load instruction in the CPU pipeline has
started execution, but is aborted due to an
interrupt.
Work around
Disable interrupts before reading the contents of
the CxFIFOCONn register, and then re-enable
interrupts after reading the register.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
Work around
None.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
 2009-2013 Microchip Technology Inc.
DS80000480N-page 7
PIC32MX575/675/695/775/795
15. Module: CAN
18. Module: Output Compare
Requested aborts to a TX message via setting the
ABAT (CxCON<27>) bit or clearing the TXREQ
(CxFIFOCON<3>) bit may not complete. The CAN
bus protocol is not violated.
Work around
1.
After a general abort request, firmware
should poll until the BUSY (CxCON<7>) bit
= 0, or wait two message times. If the ABAT
bit remains high, the message was
successfully aborted and the module must
be reset by clearing and setting the ON
(CxCON<15>) bit.
After a FIFO specific abort request,
firmware should poll until the BUSY
bit = 0, or wait two message times. If the
TXREQ bit remains high, the message
was successfully aborted and the FIFO
must be reset by setting the FRESET
(CxFIFOCONn<14>) bit and polling until
FRESET = 0.
2.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
16. Module: CAN
The FRESET (CxFIFOCONn<14>) bit and the
UINC (CxFIFOCONn<13>) bit are not settable via
a normal Special Function Register (SFR) write.
Work around
Use the SET register operations to change the
state of these bits.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
The Output Compare module may reinitialize or
clear a Fault on an aborted read of the OCxCON
register. An aborted read occurs when a read
instruction in the CPU pipeline has started
execution, but is aborted due to an interrupt.
Work around
Disable interrupts before reading the contents of
the OCxCON register, and then re-enable
interrupts after reading the register.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
19. Module: SPI
In Slave mode with the STXISEL<1:0>
(SPIxCON<3:2>) bits = 00, a TX buffer underrun
condition will not assert the TX interrupt flag.
Work around
Use any other legal value of STXISEL<1:0>
(i.e., ‘01’, ’10’, or ‘11’).
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
20. Module: USB
The TOKBUSY (UxCON<5>) bit does not correctly
indicate status when a transfer completes within
the Start of Frame (SOF) threshold.
Work around
Use a firmware semaphore to track when a token
is written to the UxTOK register. Firmware then
clears the semaphore when the transfer is
complete.
Affected Silicon Revisions
17. Module: CAN
The DeviceNet™ message filtering does not
function.
A0
A1
A3
A4
A5
X
X
X
X
X
Work around
Use hardware to filter the Standard Identifier (SID)
and use firmware to decode the DeviceNet™
identifier.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 8
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
21. Module: USB
24. Module: Oscillator
In Host mode, the interval between the first two
SOF packets may be less than what is specified by
the USB specification.
Clock source switching may cause a general
exception or POR when switching from a slow
clock to a fast clock.
Work around
Work around
None.
Clock source switches should be performed by
first switching to the FRC, and then switching to
the target clock source.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
22. Module: Watchdog Timer
When code-protect is enabled, the Watchdog
Timer (WDT) is not held in Reset during the POR
RAM Clear Sequence (RCS). If the WDT period
does not exceed the RCS period, the WDT will
reset the device and the RCS sequence will
restart.
Work around
Use WDT periods equal to or longer than 128 ms.
Since the RCS and WDT run concurrently,
firmware will have a reduced period in which to
service the WDT for the first time.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
23. Module: Oscillator
Clock switching and Two-Speed Start-up may
cause a general exception when the reserved bit 8
of the DDPCON register is ‘0’.
Work around
Ensure that the reserved bit 8 of the DDPCON
register to set to ‘1’. For example,
DDPCON |= 0x100;
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
Note:
If the peripheral library is being used,
clock
switching
is
performed
automatically through the FRC.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
25. Module: SPI
In Slave mode, when entering Sleep mode after a
SPI transfer with SPI interrupts enabled, a false
interrupt may be generated that wakes the device.
This interrupt can be cleared; however, entering
Sleep may cause the condition to occur again.
Work around
Do not use SPI in Slave mode as a wake-up
source from Sleep mode.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
26. Module: PORTS
When an I/O pin is set to output a logic high signal,
and is then changed to an input using the TRISx
registers, the I/O pin should immediately tri-state
and let the pin float. Instead, the pin will continue
to partially drive a logic high signal out for a period
of time.
Work around
The pin should be driven low, prior to being tristated, if it is desirable for the pin to tri-state
quickly.
Affected Silicon Revisions
 2009-2013 Microchip Technology Inc.
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 9
PIC32MX575/675/695/775/795
27. Module: SPI
30. Module: UART
Byte writes to the SPIxSTAT register are not
decoded correctly. A byte write to byte zero of
SPIxSTAT is actually performed on both byte zero
and byte one. A byte write to byte one of SPIxSTAT
is ignored.
The UART module is not fully IrDA® compliant.
The module does not detect the 1.6 µs minimum
bit width at all baud rates as defined in the IrDA®
specification. The module does detect the 3-/16-bit
width at all baud rates.
Work around
Work around
Only perform word operations on the SPIxSTAT
register.
None.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
28. Module: SPI
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
31. Module: UART
In Frame mode, the SPI module is not immediately
ready for further transfers after clearing the
SPITUR (SPIxSTAT<8>) bit. The SPITUR bit will
be cleared by hardware before the SPI state
machine is prepared for the next operation.
In IrDA® mode with baud clock output enabled, the
UART transmit (TX) data is corrupted when the
Baud Rate Generator (BRG) value is greater than
0x200.
Work around
Work around
Firmware must wait at least four bit times before
writing to the SPI registers after clearing the
SPITUR bit.
Affected Silicon Revisions
Use the Peripheral Bus (PB) divisor to lower the
PB frequency such that the required UART BRG
value is less than 0x201.
Affected Silicon Revisions
A0
A1
A3
A4
A5
A0
A1
A3
A4
A5
X
X
X
X
X
X
X
X
X
X
32. Module: JTAG
29. Module: CAN
When an abort request occurs concurrently with a
successful message transmission, and additional
messages remain in the FIFO, these remaining
messages are not transmitted and the TXABAT
(CxFIFOCONn<6>) bit does not reflect the abort.
On 64-pin devices an external pull-up resistor is
required on the TMS pin for proper JTAG.
Work around
Affected Silicon Revisions
The actual FIFO status can be determined by the
FIFO pointers, CxFIFOCIn and CxFIFOUAn.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 10
Work around
Connect a 100k to 200k pull-up to the TMS pin.
A0
A1
A3
A4
A5
X
X
X
X
X
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
33. Module: UART
36. Module: JTAG
The TRMT (UxSTA<8>) bit is asserted during the
Stop bit generation, not after the Stop bit has been
sent.
Pin 100 on 100-pin packages and pin A1 on
121-pin packages do not respond to boundary
scan commands.
Work around
Work around
If firmware needs to be aware when the transmission is complete, firmware should add a half bit
time delay after the TRMT bit is asserted.
None.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
34. Module: UART
The OERR (UxSTA<1>) bit does not get cleared
on a module Reset. If the OERR bit is set and the
module is disabled, the OERR bit retains its status
even after the UART module is reinitialized.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
37. Module: DMA
If the DMA module is suspended by setting the
DMA Suspend bit, SUSPEND (DMACON<12>),
the DMA Module Busy bit, DMABUSY
(DMACON<11>), may continue to show a Busy
status, when the DMA module completes
transaction.
Work around
Work around
The user software must check this bit in the UART
module initialization routine and clear it if it is set.
Use the Channel Busy bit, CHBUSY
(DCHxCON<15>), to check the status of the DMA
channel.
Affected Silicon Revisions
Affected Silicon Revisions
A0
A1
A3
A4
A5
A0
A1
A3
A4
A5
X
X
X
X
X
X
X
X
X
X
35. Module: ADC
38. Module: Voltage Regulator
When the ADC module is configured to start
conversion
on
an
external
interrupt
(SSRC<2:0> (ADxCON1<7:5> bits) = 001), the
start of conversion always occurs on a rising edge
detected at the INT0 pin, even when the INT0 pin
has been configured to generate an interrupt on a
falling edge (INT0EP (INTCON<0>) bit = 0).
Device may not exit BOR state if a BOR event
occurs.
Work around
2.
Generate ADC conversion triggers on the rising
edge of the INT0 signal.
Affected Silicon Revisions
Alternatively, use external circuitry to invert the
signal appearing at the INT0 pin, so that a falling
edge of the input signal is detected as a rising
edge by the INT0 pin.
Work arounds
1.
VDD must remain within the published
specification (see parameter DC10 of the
device data sheet).
Reset the device by providing a POR
condition.
A0
A1
X
X
A3
A4
A5
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
 2009-2013 Microchip Technology Inc.
DS80000480N-page 11
PIC32MX575/675/695/775/795
39. Module: Output Compare
If the Output Compare module is configured for a
0% duty cycle (OCxRS register = 0), a glitch may
occur on the next cycle.
Work around
The Output Compare module should be disabled
and then re-enabled to achieve a 0% duty cycle.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
42. Module: USB
If the bus has been idle for more than 3 ms, the
IDLEIF interrupt flag is set. If software clears the
interrupt flag, and the bus remains idle, the IDLEIF
interrupt flag will not be set again.
Work around
Software can leave the IDLEIF bit set until it has
received some indication of bus resumption.
(Resume, Reset, SOF, or Error).
Note:
40. Module: Oscillator
If the Primary Oscillator (POSC) mode is
implemented and a Fail-Safe Clock Monitor
(FSCM) event occurs (failure of the external
primary clock), the internal clock source will switch
to the FRC oscillator. Subsequent firmware clock
switch requests from the FRC oscillator to other
clock sources will fail and the device will continue
to execute on the FRC oscillator. Upon repair of
the external clock source and a power-on state,
the device will resume operation with the primary
oscillator clock source.
Resume and Reset are the only interrupts
that should be following IDLEIF assertion.
If the IDLEIF bit is set, it should be okay to
suspend the USB module. This will
require software to clear the IDLEIE
interrupt enable bit to exit the USB
Interrupt Service Routine (ISR) (if using
interrupt driven code).
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
Work around
None.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
41. Module: I2C
The slave address, 0x78, is one of a group of
reserved addresses. It is used as the upper byte of
a 10-bit address when 10-bit addressing is
enabled. The I2C module control register allows
the programmer to enable both 10-bit addressing
and strict enforcement of reserved addressing,
with the A10M (I2CxCON<10>) and STRICT
(I2CxCON<11>) bits, respectively. When both bits
are cleared, the device should respond to the
reserved address 0x78, but does not.
Work around
None.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 12
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
43. Module: CPU
44. Module: CPU
When both Prefetch and Instruction Cache are
enabled, a Data Bus Exception (DBE) may occur if
an interrupt is encountered by the CPU while it is
accessing constant data (not instructions) from
Flash memory.
Work arounds
To avoid a DBE, use one of the following two
solutions:
1.
Structure application code, such that interrupts are not used while the CPU is accessing
data from Flash memory.
Disable either the Prefetch module or CPU
cache functionality as follows (by default both
are disabled on a Power-on Reset (POR)):
a) To disable the Prefetch module, set the
Predictive Prefetch Enable bits, PREFEN<1:0>, in the Cache Control Register, CHECON<6:5>, to ‘00’.
b) To disable CPU cache, set the Kseg0
bits, K0<2:0>, in the CP0 Configuration
Register, Config<2:0>, to ‘010’.
2.
Note:
Disabling either the cache or Prefetch
module will have minimum performance
degradation, with a typical application
realizing 10 percent or less performance
impact.
During normal operation, if a CPU write operation
to a peripheral is interrupted by an incoming
interrupt, it should be aborted (not completed) and
resumed after the interrupt is serviced. However,
some of these write operations may not be
aborted, resulting in a double write to peripherals
by the CPU (the first write during the interrupt and
the second write after the interrupt is serviced).
Work around
Most peripherals are not affected by this issue, as
a double write will not have a negative impact.
However, the following communication peripherals
will double-send data if their respective transmit
buffers are written twice: SPI, I2C, UART, and
PMP. To avoid double transmission of data, utilize
DMA to transfer data to these peripherals or
disable interrupts while writing to these
peripherals.
Corrected Revisions
On corrected revisions, an interrupt occurring
during CPU write operation to a peripheral will be
delayed for up to two Peripheral Bus Clock
(PBCLK) cycles.
Affected Silicon Revisions
A0
A1
A3
X
X
X
A4
A5
Corrected Revisions
On corrected revisions, an interrupt occurring
during CPU access of constant data (not
instructions) from Flash memory will be delayed
for up to two System Clock (SYSCLK) cycles.
Affected Silicon Revisions
A0
A1
A3
X
X
X
A4
A5
45. Module: Oscillator
A clock signal is present on the CLKO pin,
regardless of the clock source and setting of the
CLKO Enable Configuration bit, OSCIOFNC
(DEVCFG1<10>), during a Power-on Reset
(POR) condition.
Work around
Do not connect the CLKO pin to a device that
would be adversely affected by rapid pin toggling
or a frequency other than that defined by the
oscillator configuration. Do not use the CLKO pin
as an input if the device connected to the CLKO
pin would be adversely affected by the pin driving
a signal out.
Affected Silicon Revisions
 2009-2013 Microchip Technology Inc.
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 13
PIC32MX575/675/695/775/795
46. Module: Input Capture
49. Module: 5V Tolerant Pins
All input capture modes selectable by the
ICM<2:0> (ICxCON<2:0>) bits, with the exception
of Interrupt-only mode, will not work when the CPU
enters Idle mode or Sleep mode.
Work around
Configure the Input Capture module for Interruptonly mode (ICM<2:0> = 111) when the CPU is in
Sleep mode or Idle mode.
Affected Silicon Revisions
When internal pull-ups are enabled on 5V tolerant
pins, the level as measured on the pin and
available to external device inputs, may not
exceed the minimum value of VIH, and therefore,
qualify as a logic “high”. However, with respect to
PIC32 devices, so long as the load does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the PIC32 device.
Work around
A0
A1
A3
A4
A5
It is recommend to only use external pull-ups:
X
X
X
X
X
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA
47. Module: USB
While operating in Host mode and attached to a
low-speed device through a full-speed USB hub,
the Host may persistently drive the bus to an SE0
state (both D+/D- as ‘0’), which would be
interpreted as a bus Reset condition by the hub; or
the host may persistently drive the bus to a J-state,
which would make the hub detach condition
undetectable by the host.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
Work around
Connect low-speed devices directly to the Host
USB port and not through a USB hub.
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
48. Module: Non-5V Tolerant Pins
When internal pull-ups are enabled on non-5V
tolerant pins, the level as measured on the pin and
available to external device inputs, may not
exceed the minimum value of VIH, and therefore,
qualify as a logic “high”. However, with respect to
PIC32 devices, so long as the load does not
exceed -50 µA, the internal pull-ups are
guaranteed to be recognized as a logic “high”
internally to the PIC32 device.
Work around
It is recommend to only use external pull-ups:
• To guarantee a logic “high” for external logic
input circuits outside of the PIC32 device
• For PIC32 device inputs, if the external load
exceeds -50 µA
Affected Silicon Revisions
A0
A1
A3
A4
A5
X
X
X
X
X
DS80000480N-page 14
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
Data Sheet Clarifications
The following typographic corrections and clarifications
are to be noted for the latest version of the device data
sheet (DS60001156H):
Note:
Corrections are shown in bold. Where
possible, the original bold text formatting
has been removed for clarity.
TABLE 31-8:
Param.
Symbol
No.
VIH
DI28
In the current version of the data sheet, the
revision history for changes to Table 31-8: DC
Characteristics: I/O Pin Input Specifications
was omitted.
The text in bold in the following table shows the
updates that were made.
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
DC CHARACTERISTICS
DI20
1. Module: DC Characteristics: I/O Pin Input
Specifications
Characteristics
Input High Voltage
I/O Pins not 5V-tolerant(5)
I/O Pins 5V-tolerant with
PMP(5)
I/O Pins 5V-tolerant(5)
SDAx, SCLx
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Min.
Typical(1)
Max.
Units
0.65 VDD
0.25 VDD + 0.8V
—
—
VDD
5.5
V
V
0.65 VDD
0.65 VDD
—
—
5.5
5.5
V
V
Conditions
(Note 4,6)
(Note 4,6)
SMBus disabled
(Note 4,6)
DI29
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled,
2.3V  VPIN  5.5
(Note 4,6)
DI30
ICNPU
Change Notification
—
—
-50
A VDD = 3.3V, VPIN = VSS
Pull-up Current
(Note 3,6)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Pin Diagrams” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-selectable pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pullups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate
any “positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source >
(VDD + 0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source
- (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) 
VSOURCE  (VDD + 0.3), injection current = 0.
 2009-2013 Microchip Technology Inc.
DS80000480N-page 15
PIC32MX575/675/695/775/795
TABLE 31-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Min.
Typical(1)
Max.
Units
Conditions
This parameter applies
to all pins, with the
exception of RB10.
(7,10)
DI60a IICL
Input Low Injection Current
0
—
-5
mA
Maximum IICH current
for this exception is
0 mA.
This parameter applies
to all pins, with the
exception of all 5V tolerDI60b IICH
Input High Injection Current
0
—
+5(8,9,10) mA ant pins, SOSCI, and
RB10. Maximum IICH
current for these
exceptions is 0 mA.
DI60c IICT
Total Input Injection Current
-20(11)
—
+20(11)
mA Absolute instantaneous
(sum of all I/O and control
sum of all ± input
pins)
injection currents from
all I/O pins
( | IICL + | IICH | )  IICT
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Pin Diagrams” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-selectable pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pullups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate
any “positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source >
(VDD + 0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source
- (VDD + 0.3)) / RS). RS = Resistance between input source voltage and device pin. If (VSS - 0.3) 
VSOURCE  (VDD + 0.3), injection current = 0.
DS80000480N-page 16
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
2. Module: DC Characteristics: Program
Memory
Certain specifications in Table 31-11 were stated
incorrectly in the data sheet. The correct values
are shown in bold type in the following table.
TABLE 31-11: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
—
E/W
—
Program Flash Memory(3)
D130
EP
Cell Endurance
1000
—
D130a EP
Cell Endurance
20,000
—
—
E/W
D131
VPR
VDD for Read
2.3
—
3.6
V
D132
See Note 4
—
VPEW
VDD for Erase or Write
3.0
—
3.6
V
D132a VPEW
VDD for Erase or Write
2.3
—
3.6
V
D134
TRETD
Characteristic Retention
20
—
—
Year
Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
—
TWW
Word Write Cycle Time
—
411
—
FRC Cycles See Note 4
Time(2)
—
See Note 4
D136
TRW
Row Write Cycle
—
26067
—
FRC Cycles See Note 4
D137
TPE
Page Erase Cycle Time
—
201060
—
FRC Cycles See Note 4
TCE
Chip Erase Cycle Time
—
804652
—
FRC Cycles See Note 4
Note 1:
2:
3:
4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
Refer to “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
This parameter depends on the FRC accuracy (see Table 31-19) and the FRC tuning values (see
Register 8-2).
 2009-2013 Microchip Technology Inc.
DS80000480N-page 17
PIC32MX575/675/695/775/795
3. Module: DC Characteristics: Operating
Current (IDD)
Note 4 in Table 31-5 was stated incorrectly in the
data sheet. The correct information is shown in
bold type in the following table.
Note:
All previous (Note 4) references listed in
the Conditions column were removed.
TABLE 31-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Param.
No.
Typical(3)
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Units
Conditions
Operating Current (IDD)(1,2,4) for PIC32MX575/675/695/775/795 Family Devices
-40ºC,
DC20
6
9
+25ºC,
Code executing from Flash
+85ºC
mA
—
4 MHz
DC20b
7
10
+105ºC
DC20a
4
—
Code executing from SRAM
—
DC21
37
40
Code executing from Flash
mA
—
—
25 MHz
DC21a
25
—
Code executing from SRAM
DC22
64
70
Code executing from Flash
mA
—
—
60 MHz
DC22a
61
—
Code executing from SRAM
-40ºC,
DC23
85
98
+25ºC,
Code executing from Flash
+85ºC
—
80 MHz
mA
DC23b
90
120
+105ºC
DC23a
85
—
Code executing from SRAM
—
DC25a
125
150
µA
—
+25°C
3.3V
LPRC (31 kHz)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested
at 3.3V in manufacturing.
DS80000480N-page 18
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
TABLE 31-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
DC CHARACTERISTICS
Param.
No.
Typical(3)
Max.
Units
Conditions
Operating Current (IDD)(1,2,4) for PIC32MX534/564/664/764 Family Devices
DC20c
6
9
mA
DC20d
DC20e
DC21b
DC21c
DC22b
DC22c
DC23c
DC23d
DC23e
DC25b
Note 1:
2:
3:
4:
7
2
19
14
31
29
10
—
32
—
50
—
mA
mA
Code executing from Flash
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
-40ºC,
+25ºC,
+85ºC
+105ºC
—
—
4 MHz
—
—
25 MHz
—
—
60 MHz
-40ºC,
+25ºC,
Code executing from Flash
+85ºC
mA
—
80 MHz
49
70
+105ºC
39
—
Code executing from SRAM
—
100
150
µA
—
+25°C
3.3V
LPRC (31 kHz)
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested
at 3.3V in manufacturing.
39
65
 2009-2013 Microchip Technology Inc.
DS80000480N-page 19
PIC32MX575/675/695/775/795
4. Module: DC Characteristics: Operating
Current (IIDLE)
Note 3 in Table 31-6 was stated incorrectly in the
data sheet. The correct references are shown in
bold type in the following table.
Note:
All previous (Note 3) references listed in
the Conditions column were removed.
TABLE 31-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
DC CHARACTERISTICS
Parameter No.
Typical(2)
Idle Current (IIDLE)
(1,3)
Max.
Units
Conditions
for PIC32MX575/675/695/775/795 Family Devices
DC30
4.5
6.5
DC30b
5
7
DC31
13
15
mA
DC32
28
30
mA
mA
-40ºC, +25ºC, +85ºC
—
4 MHz
-40ºC, +25ºC, +85ºC
—
25 MHz
-40ºC, +25ºC, +85ºC
—
60 MHz
—
80 MHz
+105°C
DC33
36
42
mA
-40ºC, +25ºC, +85ºC
DC33b
39
45
mA
+105°C
DC34
40
-40°C
DC34a
75
+25°C
—
DC34b
DC34c
800
µA
1000
+85°C
+105°C
DC35
35
-40°C
DC35a
65
+25°C
DC35b
600
DC35c
800
—
µA
+85°C
43
-40°C
DC36a
106
+25°C
—
DC36c
Note 1:
2:
3:
3.3V
LPRC (31 kHz)
+105°C
DC36
DC36b
2.3V
800
1000
µA
+85°C
3.6V
+105°C
The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested
at 3.3V in manufacturing.
DS80000480N-page 20
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
TABLE 31-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
DC CHARACTERISTICS
Parameter No.
Typical(2)
Idle Current (IIDLE)
(1,3)
Max.
Units
Conditions
for PIC32MX534/564/664/764 Family Devices
DC30a
1.5
5
DC30c
3.5
6
DC31a
7
11
DC32a
13
20
DC33a
17
25
DC33c
20
27
-40ºC, +25ºC, +85ºC
-40ºC, +25ºC, +85ºC
—
25 MHz
mA
-40ºC, +25ºC, +85ºC
—
60 MHz
—
80 MHz
mA
-40ºC, +25ºC, +85ºC
+105ºC
40
-40°C
DC34d
75
+25°C
—
DC34f
800
µA
1000
+85°C
30
-40°C
DC35d
55
+25°C
DC35e
230
DC35f
800
µA
+85°C
43
-40°C
DC36d
106
+25°C
DC36f
Note 1:
2:
3:
—
3.3V
LPRC (31 kHz)
+105ºC
DC36c
DC36e
2.3V
+105ºC
DC35c
—
4 MHz
+105ºC
DC34c
DC34e
—
mA
800
1000
µA
+85°C
3.6V
+105ºC
The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested
at 3.3V in manufacturing.
 2009-2013 Microchip Technology Inc.
DS80000480N-page 21
PIC32MX575/675/695/775/795
5. Module: DC Characteristics: Operating
Current (IPD)
Certain references to Note 6 in Table 31-7 were
omitted in the data sheet. These references are
shown in bold type in the following table.
TABLE 31-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Param.
Typical(2)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Units
Conditions
Power-Down Current (IPD)(1) for PIC32MX575/675/695/775/795 Family Devices
DC40
10
40
-40°C
DC40a
36
100
+25°C
2.3V Base Power-Down Current (Note 6)
DC40b
400
720
+85°C
DC40h
900
1800
+105°C
DC40c
41
120
+25°C
3.3V Base Power-Down Current
A
DC40d
22
80
-40°C
DC40e
42
120
+25°C
(5)
+70°C
DC40g
315
400
3.6V Base Power-Down Current (Note 6)
DC40f
410
800
+85°C
DC40i
1000
2000
+105°C
Module Differential Current for PIC32MX575/675/695/775/795 Family Devices
DC41
—
10
2.3V Watchdog Timer Current: IWDT (Notes 3,6)
DC41a
5
—
3.3V Watchdog Timer Current: IWDT (Note 3)
A
—
DC41b
—
20
3.6V Watchdog Timer Current: IWDT (Note 3,6)
DC42
—
40
2.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6)
DC42a
23
—
3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
A
—
DC42b
—
50
3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3,6)
DC43
—
1300
2.5V ADC: IADC (Notes 3,4,6)
DC43a
1100
—
3.3V ADC: IADC (Notes 3,4)
A
—
DC43b
—
1300
3.6V ADC: IADC (Notes 3,4,6)
Note 1: The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.
DS80000480N-page 22
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
TABLE 31-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
DC CHARACTERISTICS
Param.
Typical(2)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Units
Conditions
Power-Down Current (IPD)(1) for PIC32MX534/564/664/764 Family Devices
DC40g
12
40
-40°C
DC40h
20
120
+25°C
2.3V Base Power-Down Current (Note 6)
DC40i
210
600
+85°C
DC40o
400
1000
+105°C
DC40j
20
120
+25°C
3.3V Base Power-Down Current
A
DC40k
15
80
-40°C
DC40l
20
120
+25°C
+70°C
DC40m
113
350(5)
3.6V Base Power-Down Current (Note 6)
DC40n
220
650
+85°C
DC40p
500
1000
+105°C
Module Differential Current for PIC32MX534/564/664/764 Family Devices
DC41c
—
10
2.5V Watchdog Timer Current: IWDT (Notes 3,6)
DC41d
5
—
3.3V Watchdog Timer Current: IWDT (Note 3)
A
—
DC41e
—
20
3.6V Watchdog Timer Current: IWDT (Note 3,6)
DC42c
—
40
2.5V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6)
DC42d
23
—
3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
A
—
DC42e
—
50
3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3,6)
DC43c
—
1300
2.5V ADC: IADC (Notes 3,4,6)
DC43d
1100
—
3.3V ADC: IADC (Notes 3,4)
A
—
DC43e
—
1300
3.6V ADC: IADC (Notes 3,4,6)
Note 1: The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.
 2009-2013 Microchip Technology Inc.
DS80000480N-page 23
PIC32MX575/675/695/775/795
6. Module: Product Identification System
The Product Identification System information was
incorrectly specified in the current version of the
data sheet. The corrected information is shown in
bold type.
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MX 5XX F 512 H T - 80 I / PT - XXX
Example:
PIC32MX575F256H-80I/PT:
General purpose PIC32,
32-bit RISC MCU,
256 KB program memory,
64-pin, Industrial temperature,
TQFP package.
Microchip Brand
Architecture
Product Groups
Flash Memory Family
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed (see Note 1)
Temperature Range
Package
Pattern
Flash Memory Family
Architecture
MX = 32-bit RISC MCU core
Product Groups
5XX = General purpose microcontroller family
6XX = General purpose microcontroller family
7XX = General purpose microcontroller family
Flash Memory Family
F
= Flash program memory
Program Memory Size
64
128
256
512
=
=
=
=
Pin Count
H
L
= 64-pin
= 100-pin, 121-pin, 124-pin
Speed (see Note 1)
80
= 80 MHz
Temperature Range
I
V
= -40°C to +85°C (Industrial)
= -40°C to +105°C (V-Temp)
Package
PT
PT
PF
MR
BG
TL
=
=
=
=
=
=
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES = Engineering Sample
Note
1:
64K
128K
256K
512K
64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
121-Lead (10x10x1.1 mm) TFBGA (Plastic Thin Profile Ball Grid Array)
124-Lead (9x9x0.9 mm) VTLA (Very Thin Leadless Array)
This option is not available for PIC32MX534/564/664/774 devices.
DS80000480N-page 24
 2009-2013 Microchip Technology Inc.
PIC32MX575/675/695/775/795
APPENDIX A:
REVISION HISTORY
Rev A Document (8/2009)
Initial release of this document; issued for revision A0
silicon.
Rev G Document (10/2011)
Updated issue 19 (SPI).
Added silicon issues 40 (Oscillator), 41 (I2C), and
42 (USB).
Includes silicon issues 1 (I2C™), 2 (Ethernet), 3 (ADC),
4 (Parallel Master Port), 5 (Output Compare), 6 (SPI)
and 7 (UART).
Added data sheet clarification 2 (AC Characteristics:
Standard Operating Conditions).
Rev B Document (11/2009)
Updated the current silicon revision to A3 throughout
the document.
Added silicon issues 8 (USB), 9-10 (Output Compare),
11 (DMA), 12 (Timers), 13 (SPI), 14-17 (CAN), 18 (Output Compare), 19 (SPI), 20-21 (USB), 22 (Watchdog
Timer), 23 (Oscillator) and 24 (Oscillator).
Rev H Document (10/2011)
Rev J Document (2/2012)
Added silicon issues 43 (CPU), 44 (CPU), and
45 (Oscillator).
Rev C Document (9/2010)
Rev K Document (3/2012)
The document title was changed to PIC32MX575/675/
/695/775/795 Family Silicon Errata and Data Sheet
Clarification.
Updated silicon issue 43 (CPU) and 44 (CPU).
Added silicon issue 46 (Input Capture) and 47 (USB).
Added devices to Table 1: Silicon DEVREV Values.
Rev L Document (9/2012)
2C™).
Modified silicon issue 1 (I
Added silicon issues 25 (SPI), 26 (PORTS), 27-28 (SPI),
29 (CAN), 30-31 (UART), 32 (JTAG), 33 (UART) and 34
(UART), and added data sheet clarification issue 1 (DC
Characteristics: I/O Pin Input Specifications).
Updated the current silicon revision to A4 throughout
the document.
Updated silicon issue 6 (SPI), 43 (CPU), and 44 (CPU).
Updated the note in the Silicon DEVREV Values table
(see Table 1).
Rev D Document (11/2010)
Rev M Document (2/2013)
Removed data sheet clarification 1.
Updated the current silicon revision to A5 throughout
the document.
Added silicon issues 35 (ADC), 36 (JTAG) and 37
(DMA).
The Note in silicon issue 42 (USB) was updated.
Rev E Document (12/2010)
Rev N Document (5/2013)
Added silicon issue 38 (Voltage Regulator).
Added silicon issues 48 (Non-5V Tolerant Pins) and
49 (5V Tolerant Pins).
Rev F Document (3/2011)
Updated the current silicon revision to A1 throughout
the document. Added silicon issue 39 (Output
Compare) and data sheet clarification 1 (DC
Characteristics: I/O Pin Input Specifications).
 2009-2013 Microchip Technology Inc.
Removed data sheet clarifications 1 and 2.
Added data sheet clarifications 1 (DC Characteristics:
I/O Pin Input Specifications), 2 (DC Characteristics:
Program Memory), 3 (DC Characteristics: Operating
Current (IDD)), 4 (DC Characteristics: Operating
Current (IIDLE)), 5 (DC Characteristics: Operating
Current (IPD)) and 6 (Product Identification System).
DS80000480N-page 25
PIC32MX575/675/695/775/795
NOTES:
DS80000480N-page 26
 2009-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC32 logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. & KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2013, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62077-185-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
 2009-2013 Microchip Technology Inc.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS80000480N-page 27
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
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Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
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Tel: 91-11-4160-8631
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Austria - Wels
Tel: 43-7242-2244-39
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Denmark - Copenhagen
Tel: 45-4450-2828
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Tel: 91-20-2566-1512
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France - Paris
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Tel: 81-6-6152-7160
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Germany - Munich
Tel: 49-89-627-144-0
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Tel: 774-760-0087
Fax: 774-760-0088
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Tel: 630-285-0071
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Tel: 216-447-0464
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Canada
Tel: 905-673-0699
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Tel: 61-2-9868-6733
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Tel: 86-28-8665-5511
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Tel: 82-53-744-4301
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Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
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Tel: 852-2943-5100
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Tel: 63-2-634-9065
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Tel: 86-21-5407-5533
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Tel: 65-6334-8870
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Tel: 86-24-2334-2829
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Tel: 886-3-5778-366
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Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2508-8600
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China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS80000480N-page 28
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
11/29/12
 2009-2013 Microchip Technology Inc.