MICROCHIP PIC32MX695F512L-80I

PIC32MX5XX/6XX/7XX
Family Data Sheet
High-Performance, USB, CAN and Ethernet
32-bit Flash Microcontrollers
© 2009-2011 Microchip Technology Inc.
DS61156G
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-150-6
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS61156G-page 2
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
High-Performance, USB, CAN and Ethernet
32-bit Flash Microcontrollers
High-Performance 32-bit RISC CPU:
Peripheral Features (Continued):
• MIPS32® M4K® 32-bit core with 5-stage pipeline
• 80 MHz maximum frequency
• 1.56 DMIPS/MHz (Dhrystone 2.1) performance
at zero Wait state Flash access
• Single-cycle multiply and high-performance divide
unit
• MIPS16e® mode for up to 40% smaller code size
• Two sets of 32 core register files (32-bit) to reduce
interrupt latency
• Prefetch Cache module to speed execution from
Flash
• Internal 8 MHz and 32 kHz oscillators
• Six UART modules with:
- RS-232, RS-485 and LIN support
- IrDA® with on-chip hardware encoder and
decoder
• Up to four SPI modules
• Up to five I2C™ modules
• Separate PLLs for CPU and USB clocks
• Parallel Master and Slave Port (PMP/PSP) with
8-bit and 16-bit data, and up to 16 address lines
• Hardware Real-Time Clock and Calendar (RTCC)
• Five 16-bit Timers/Counters (two 16-bit pairs
combine to create two 32-bit timers)
• Five Capture inputs
• Five Compare/PWM outputs
• Five external interrupt pins
• High-speed I/O pins capable of toggling at up
to 80 MHz
• High-current sink/source (18 mA/18 mA) on
all I/O pins
• Configurable open-drain output on digital I/O pins
Microcontroller Features:
• Operating voltage range of 2.3V to 3.6V
• 64K to 512K Flash memory (plus an
additional 12 KB of Boot Flash)
• 16K to 128K SRAM memory
• Pin-compatible with most PIC24/dsPIC® DSC
devices
• Multiple power management modes
• Multiple interrupt vectors with individually
programmable priority
• Fail-Safe Clock Monitor mode
• Configurable Watchdog Timer with on-chip
Low-Power RC oscillator for reliable operation
Peripheral Features:
• Atomic SET, CLEAR and INVERT operation on
select peripheral registers
• Up to 8-channels of hardware DMA with automatic
data size detection
• USB 2.0-compliant full-speed device and
On-The-Go (OTG) controller:
- Dedicated DMA channels
• 10/100 Mbps Ethernet MAC with MII and RMII
interface:
- Dedicated DMA channels
• CAN module:
- 2.0B Active with DeviceNet™ addressing
support
- Dedicated DMA channels
• 3 MHz to 25 MHz crystal oscillator
© 2009-2011 Microchip Technology Inc.
Debug Features:
• Two programming and debugging Interfaces:
- 2-wire interface with unintrusive access and
real-time data exchange with application
- 4-wire MIPS® standard enhanced Joint Test
Action Group (JTAG) interface
• Unintrusive hardware-based instruction trace
• IEEE Standard 1149.2 compatible (JTAG)
boundary scan
Analog Features:
• Up to 16-channel, 10-bit Analog-to-Digital
Converter:
- 1 Msps conversion rate
- Conversion available during Sleep and Idle
• Two Analog Comparators
DS61156G-page 3
PIC32MX5XX/6XX/7XX
TABLE 1:
PIC32 USB AND CAN – FEATURES
Device
Pins
Program Memory (KB)
Data Memory (KB)
USB
CAN
Timers/Capture/Compare
DMA Channels
(Programmable/
Dedicated)
UART(2,3)
SPI(3)
I2C™(3)
10-bit 1 Msps ADC
(Channels)
Comparators
PMP/PSP
JTAG
Trace
Packages(4)
USB and CAN
PIC32MX534F064H
64
64 + 12(1)
16
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX564F064H
64
64 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX564F128H
64
128 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX575F256H
64
256 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX575F512H
64
512 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX534F064L
100
64 + 12(1)
16
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX564F064L
100
64 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX564F128L
100
128 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX575F256L
100
256 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX575F512L
100
512 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
Legend:
Note 1:
2:
3:
4:
PF, PT = TQFP
MR = QFN
BG = XBGA
This device features 12 KB boot Flash memory.
CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.
Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.
Refer to Section 32.0 “Packaging Information” for more information.
DS61156G-page 4
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 2:
PIC32 USB AND ETHERNET – FEATURES
Device
Pins
Program Memory (KB)
Data Memory (KB)
USB
Ethernet
Timers/Capture/Compare
DMA Channels
(Programmable/
Dedicated)
UART(2,3)
SPI(3)
I2C™(3)
10-bit 1 Msps ADC
(Channels)
Comparators
PMP/PSP
JTAG
Trace
Packages(4)
USB and Ethernet
PIC32MX664F064H
64
64 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX664F128H
64
128 + 12(1)
32
1
1
5/5/5
4/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX675F256H
64
256 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX675F512H
64
512 + 12(1)
64
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX695F512H
64
512 + 12(1)
128
1
1
5/5/5
8/4
6
3
4
16
2
Yes
Yes
No
PT,
MR
PIC32MX664F064L
100
64 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX664F128L
100
128 + 12(1)
32
1
1
5/5/5
4/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX675F256L
100
256 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX675F512L
100
512 + 12(1)
64
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
PIC32MX695F512L
100
128
1
1
5/5/5
8/4
6
4
5
16
2
Yes
Yes Yes
PT,
PF,
BG
Legend:
Note 1:
2:
3:
4:
512 + 12(1)
PF, PT = TQFP
MR = QFN
BG = XBGA
This device features 12 KB boot Flash memory.
CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.
Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.
Refer to Section 32.0 “Packaging Information” for more information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 5
PIC32MX5XX/6XX/7XX
TABLE 3:
PIC32 USB, ETHERNET AND CAN – FEATURES
Pins
Program Memory (KB)
Data Memory (KB)
USB
Ethernet
CAN
Timers/Capture/Compare
DMA Channels
(Programmable/
Dedicated)
UART(2,3)
SPI(3)
I2C™(3)
10-bit 1 Msps ADC
(Channels)
Comparators
JTAG
Trace
Packages(4)
PIC32MX764F128H
64
128 + 12(1)
32
1
1
1
5/5/5
4/6
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX775F256H
64
256 + 12(1)
64
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX775F512H
64
512 + 12(1)
64
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX795F512H
64
512 + 12(1) 128
1
1
2
5/5/5
8/8
6
3
4
16
2
Yes Yes
No
PT,
MR
PIC32MX764F128L
100 128 + 12(1)
32
1
1
1
5/5/5
4/6
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX775F256L
100 256 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX775F512L
100 512 + 12(1)
64
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
PIC32MX795F512L
100 512 + 12(1) 128
1
1
2
5/5/5
8/8
6
4
5
16
2
Yes Yes Yes
PT,
PF,
BG
Legend:
Note 1:
2:
3:
4:
PMP/PSP
Device
USB, Ethernet and CAN
PF, PT = TQFP
MR = QFN
BG = XBGA
This device features 12 KB boot Flash memory.
CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more
information.
Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more
information.
Refer to Section 32.0 “Packaging Information” for more information.
DS61156G-page 6
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams
64-Pin QFN(1)
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
C1TX/RF1
C1RX/RF0
VDD
VCAP/VCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RX/OC3/RD2
SCK3/U4TX/U1RTS/OC2/RD1
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC32MX534F064H
PIC32MX564F064H
PIC32MX564F128H
PIC32MX575F256H
PIC32MX575F512H
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
IC4/PMCS1/PMA14/INT4/RD11
SCL1/IC3/PMCS2/PMA15/INT3/RD10
SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
AN15/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 7
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN(1)
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AETXD0/ERXD2/RF1
AETXD1/ERXD3/RF0
VDD
VCAP/VCORE
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RX/OC3/RD2
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
ERXERR/PMD4/RE4
ERXCLK/EREFCLK/PMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
PIC32MX664F064H
42
41
PIC32MX664F128H
40
PIC32MX675F256H
39
PIC32MX675F512H
38
PIC32MX695F512H
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK4/U5TX/U2RTSU2RTS/PMALH/PMA1/RB14
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
SDA5/SDI4/U2RX/PMA9/CN17/RF4
SCL5/SDO4/U2TX/PMA8/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Note 1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
DS61156G-page 8
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN(1)
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
PIC32MX775F256H
8
40
PIC32MX775F512H
9
39
PIC32MX795F512H
10
38
11
37
12
36
13
35
14
34
15
33
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
C1TX/AETXD0/ERXD2/RF1
C1RX/AETXD1/ERXD3/RF0
VDD
VCAP/VCORE
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RX/OC3/RD2
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
ERXERR/PMD4/RE4
ERXCLK/EREFCLKPMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
= Pins are up to 5V tolerant
Note 1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 9
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin QFN(1)
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
1
47
2
46
3
45
4
44
5
43
6
42
7
41
PIC32MX764F128H
8
40
9
39
10
38
11
37
12
36
13
35
14
34
15
33
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
C1TX/AETXD0/ERXD2/RF1
C1RX/AETXD1/ERXD3/RF0
VDD
VCAP/VCORE
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RX/OC3/RD2
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
ERXERR/PMD4/RE4
ERXCLK/EREFCLKPMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
= Pins are up to 5V tolerant
Note 1:
The metal plane at the bottom of the device is not connected to any pins and is recommended to be
connected to VSS externally.
DS61156G-page 10
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
PMD4/RE4
PMD3/RE3
PMD2/RE2
PMD1/RE1
PMD0/RE0
C1TX/RF1
C1RX/RF0
VDD
VCAP/VCORE
CN16/RD7
CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RX/OC3/RD2
SCK3/U4TX/U1RTS/OC2/RD1
64-Pin TQFP
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
PMD5/RE5
PMD6/RE6
PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PIC32MX534F064H
PIC32MX564F064H
PIC32MX564F128H
PIC32MX575F256H
PIC32MX575F512H
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
IC4/PMCS1/PMA14/INT4/RD11
SCL1/IC3/PMCS2/PMA15/INT3/RD10
SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
AN15/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
© 2009-2011 Microchip Technology Inc.
DS61156G-page 11
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
AETXD0/ERXD2/RF1
AETXD1/ERXD3/RF0
VDD
VCAP/VCORE
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RX/OC3/RD2
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
ERXERR/PMD4/RE4
ERXCLK/EREFCLK/PMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
= Pins are up to 5V tolerant
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
SDA5/SDI4/U2RX/PMA9/CN17/RF4
SCL5/SDO4/U2TX/PMA8/CN18/RF5
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
1
2
3
4
5
6
PIC32MX664F064H
7
PIC32MX664F128H
8
PIC32MX675F256H
9
PIC32MX675F512H
10
PIC32MX695F512H
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DS61156G-page 12
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
PIC32MX775F256H
9
PIC32MX775F512H
10
PIC32MX795F512H
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
C1TX/AETXD0/ERXD2/RF1
C1RX/AETXD1/ERXD3/RF0
VDD
VCAP/VCORE
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RX/OC3/RD2
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
ERXERR/PMD4/RE4
ERXCLK/EREFCLK/PMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
= Pins are up to 5V tolerant
© 2009-2011 Microchip Technology Inc.
DS61156G-page 13
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
64-Pin TQFP
ETXEN/PMD5/RE5
ETXD0/PMD6/RE6
ETXD1/PMD7/RE7
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
1
2
3
4
5
6
7
8
PIC32MX764F128H
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
OC1/INT0/RD0
ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
RTCC/AERXD1/ETXD3/IC1/INT1/RD8
Vss
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
D+/RG2
D-/RG3
VUSB
VBUS
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
AVDD
AVSS
AN8/SS4/U5RX/U2CTS/C1OUT/RB8
AN9/C2OUT/PMA7/RB9
TMS/AN10/CVREFOUT/PMA13/RB10
TDO/AN11/PMA12/RB11
VSS
VDD
TCK/AN12/PMA11/RB12
TDI/AN13/PMA10/RB13
AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14
AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15
AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4
AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/VREF-/CVREF-/CN3/RB1
PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0
C1TX/AETXD0/ERXD2/RF1
C1RX/AETXD1/ERXD3/RF0
VDD
VCAP/VCORE
ETXCLK/AERXERR/CN16/RD7
AETXEN/ETXERR/CN15/RD6
PMRD/CN14/RD5
OC5/IC5/PMWR/CN13/RD4
SCL3/SDO3/U1TX/OC4/RD3
SDA3/SDI3/U1RXU1RX/OC3/RD2
EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
ERXERR/PMD4/RE4
ERXCLK/EREFCLK/PMD3/RE3
ERXDV/ECRSDV/PMD2/RE2
ERXD0/PMD1/RE1
ERXD1/PMD0/RE0
= Pins are up to 5V tolerant
DS61156G-page 14
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
= Pins are up to 5V tolerant
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F512L
PIC32MX575F256L
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
IC4/PMCS1/PMA14/RD11
SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
RTCC/IC1/RD8
SDA1/INT4/RA15
SCL1/INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
D-/RG3
VUSB
VBUS
SCL3/SDO3/U1TX/RF8
SDA3/SDI3/U1RX/RF2
USBID/RF3
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
VREF-/CVREF-/PMA7/RA9
VREF+/CVREF+/PMA6/RA10
AVDD
AVSS
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN10/CVREFOUT/PMA13/RB10
AN11/PMA12/RB11
VSS
VDD
TCK/RA1
AC1TX/SCK4/U5TX/U2RTS/RF13
AC1RX/SS4/U5RX/U2CTS/RF12
AN12/PMA11/RB12
AN13/PMA10/RB13
AN14/PMALH/PMA1/RB14
AN15/OCFB/PMALL/PMA0/CN12/RB15
VSS
VDD
SS3/U4RX/U1CTS/CN20/RD14
SCK3/U4TX/U1RTS/CN21/RD15
SDA5/SDI4/U2RX/PMA9/CN17/RF4
SCL5/SDO4/U2TX/PMA8/CN18/RF5
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/SDI1/RC4
SCK2/U6TX/U3RTS/PMA5/CN8/RG6
SDA4/SDI2/U3RX/PMA4/CN9/RG7
SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
TMS/RA0
INT1/RE8
INT2/RE9
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
PMD8/RG0
PMD9/RG1
C1TX/PMD10/RF1
C1RX/PMD11/RF0
VDD
VCAP/VCORE
PMD15/CN16/RD7
PMD14/CN15/RD6
PMRD/CN14/RD5
OC5/PMWR/CN13/RD4
PMD13/CN19/RD13
IC5/PMD12/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
© 2009-2011 Microchip Technology Inc.
DS61156G-page 15
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
PMD8/RG0
ETXERR/PMD9/RG1
ETXD0/PMD10/RF1
ETXD1/PMD11/RF0
VDD
VCAP/VDDCORE
ETXCLK/PMD15/CN16/RD7
ETXEN/PMD14/CN15/RD6
PMRD/CN14/RD5
OC5/PMWR/CN13/RD4
ETXD3/PMD13/CN19/RD13
ETXD2/IC5/PMD12/RD12
OC4/RD3
OC3/RD2
OC2/RD1
PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
= Pins are up to 5V tolerant
© 2009-2011 Microchip Technology Inc.
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
VREF-/CVREF-/AERXD2/PMA7/RA9
VREF+/CVREF+/AERXD3/PMA6/RA10
AVDD
AVSS
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN10/CVREFOUT/PMA13/RB10
AN11/ERXERR/AETXERR/PMA12/RB11
VSS
VDD
TCK/RA1
SCK4/U5TX/U2RTS/RF13
SS4/U5RX/U2CTS/RF12
AN12/ERXD0/AECRS/PMA11/RB12
AN13/ERXD1/AECOL/PMA10/RB13
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
VSS
VDD
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
SDA5/SDI4/U2RX/PMA9/CN17/RF4
SCL5/SDO4/U2TX/PMA8/CN18/RF5
AERXERR/RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/SDI1/RC4
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
TMS/RA0
AERXD0/INT1/RE8
AERXD1/INT2/RE9
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100-Pin TQFP
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
RTCC/EMDIO/AEMDIO/IC1/RD8
AETXEN/SDA1/INT4/RA15
AETXCLK/SCL1/INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
D-/RG3
VUSB
VBUS
SCL3/SDO3/U1TX/RF8
SDA3/SDI3/U1RX/RF2
USBID/RF3
PIC32MX5XX/6XX/7XX
DS61156G-page 16
Pin Diagrams (Continued)
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DS61156G-page 17
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
VREF-/CVREF-/AERXD2/PMA7/RA9
VREF+/CVREF+/AERXD3/PMA6/RA10
AVDD
AVSS
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN10/CVREFOUT/PMA13/RB10
AN11/ERXERR/AETXERR/PMA12/RB11
VSS
VDD
TCK/RA1
AC1TX/SCK4/U5TX/U2RTS/RF13
AC1RX/SS4/U5RX/U2CTS/RF12
AN12/ERXD0/AECRS/PMA11/RB12
AN13/ERXD1/AECOL/PMA10/RB13
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
VSS
VDD
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
SDA5/SDI4/U2RX/PMA9/CN17/RF4
SCL5/SDO4/U2TX/PMA8/CN18/RF5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
= Pins are up to 5V tolerant
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
EMDC/AEMDC/IC4/PMCS1/PMA14/RD1
SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
RTCC/EMDIO/AEMDIO/IC1/RD8
AETXEN/SDA1/INT4/RA15
AETXCLK/SCL1/INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
D-/RG3
VUSB
VBUS
SCL3/SDO3/U1TX/RF8
SDA3/SDI3/U1RX/RF2
USBID/RF3
PIC32MX5XX/6XX/7XX
AERXERR/RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/AC2TX/RC2
T4CK/AC2RX/RC3
T5CK/SDI1/RC4
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
TMS/RA0
AERXD0/INT1/RE8
AERXD1/INT2/RE9
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
C2RX/PMD8/RG0
C2TX/ETXERR/PMD9/RG1
C1TX/ETXD0/PMD10/RF1
C1RX/ETXD1/PMD11/RF0
VDD
VCAP/VDDCORE
ETXCLK/PMD15/CN16/RD7
ETXEN/PMD14/CN15/RD6
PMRD/CN14/RD5
OC5/PMWR/CN13/RD4
ETXD3/PMD13/CN19/RD13
ETXD2/IC5/PMD12/RD12
OC4/RD3
OC3/RD2
OC2/RD1
100-Pin TQFP
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
© 2009-2011 Microchip Technology Inc.
Pin Diagrams (Continued)
PMD4/RE4
PMD3/RE3
PMD2/RE2
TRD0/RG13
TRD1/RG12
TRD2/RG14
PMD1/RE1
PMD0/RE0
TRD3/RA7
TRCLK/RA6
PMD8/RG0
ETXERR/PMD9/RG1
C1TX/ETXD0/PMD10/RF1
C1RX/ETXD1/PMD11/RF0
VDD
VCAP/VDDCORE
ETXCLK/PMD15/CN16/RD7
ETXEN/PMD14/CN15/RD6
PMRD/CN14/RD5
OC5/PMWR/CN13/RD4
ETXD3/PMD13/CN19/RD13
ETXD2/IC5/PMD12/RD12
OC4/RD3
OC3/RD2
OC2/RD1
PIC32MX764F128L
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
= Pins are up to 5V tolerant
PGEC2/AN6/OCFA/RB6
PGED2/AN7/RB7
VREF-/CVREF-/AERXD2/PMA7/RA9
VREF+/CVREF+/AERXD3/PMA6/RA10
AVDD
AVSS
AN8/C1OUT/RB8
AN9/C2OUT/RB9
AN10/CVREFOUT/PMA13/RB10
AN11/ERXERR/AETXERR/PMA12/RB11
VSS
VDD
TCK/RA1
AC1TX/SCK4/U5TX/U2RTS/RF13
AC1RX/SS4/U5RX/U2CTS/RF12
AN12/ERXD0/AECRS/PMA11/RB12
AN13/ERXD1/AECOL/PMA10/RB13
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
VSS
VDD
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
SDA5/SDI4/U2RX/PMA9/CN17/RF4
SCL5/SDO4/U2TX/PMA8/CN18/RF5
© 2009-2011 Microchip Technology Inc.
AERXERR/RG15
VDD
PMD5/RE5
PMD6/RE6
PMD7/RE7
T2CK/RC1
T3CK/RC2
T4CK/RC3
T5CK/SDI1/RC4
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
MCLR
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
VSS
VDD
TMS/RA0
AERXD0/INT1/RE8
AERXD1/INT2/RE9
AN5/C1IN+/VBUSON/CN7/RB5
AN4/C1IN-/CN6/RB4
AN3/C2IN+/CN5/RB3
AN2/C2IN-/CN4/RB2
PGEC1/AN1/CN3/RB1
PGED1/AN0/CN2/RB0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
100-Pin TQFP
VSS
SOSCO/T1CK/CN0/RC14
SOSCI/CN1/RC13
SDO1/OC1/INT0/RD0
EMDC/AEMDC/IC4/PMCS1/PMA14/RD1
SCK1/IC3/PMCS2/PMA15/RD10
SS1/IC2/RD9
RTCC/EMDIO/AEMDIO/IC1/RD8
AETXEN/SDA1/INT4/RA15
AETXCLK/SCL1/INT3/RA14
VSS
OSC2/CLKO/RC15
OSC1/CLKI/RC12
VDD
TDO/RA5
TDI/RA4
SDA2/RA3
SCL2/RA2
D+/RG2
D-/RG3
VUSB
VBUS
SCL3/SDO3/U1TX/RF8
SDA3/SDI3/U1RX/RF2
USBID/RF3
PIC32MX5XX/6XX/7XX
DS61156G-page 18
Pin Diagrams (Continued)
PIC32MX5XX/6XX/7XX
Pin Diagrams (Continued)
121-Pin XBGA(1)
= Pins are up to 5V tolerant
PIC32MX534F064L
PIC32MX564F064L
PIC32MX664F064L
PIC32MX564F128L
PIC32MX664F128L
PIC32MX764F128L
PIC32MX575F256L
PIC32MX675F256L
PIC32MX775F256L
PIC32MX575F512L
PIC32MX675F512L
PIC32MX695F512L
PIC32MX775F512L
PIC32MX795F512L
A
B
C
D
E
F
G
H
J
K
L
1
2
3
4
5
6
7
8
9
10
11
RE4
RE3
RG13
RE0
RG0
RF1
VDD
VSS
RD12
RD2
RD1
NC
RG15
RE2
RE1
RA7
RF0
VCAP/
VCORE
RD5
RD3
VSS
RC14
RE6
VDD
RG12
RG14
RA6
NC
RD7
RD4
VDD
RC13
RD11
RC1
RE7
RE5
VSS
VSS
NC
RD6
RD13
RD0
NC
RD10
RC4
RC3
RG6
RC2
VDD
RG1
VSS
RA15
RD8
RD9
RA14
MCLR
RG8
RG9
RG7
VSS
NC
NC
VDD
RC12
VSS
RC15
RE8
RE9
RA0
NC
VDD
VSS
VSS
NC
RA5
RA3
RA4
RB5
RB4
VSS
VDD
NC
VDD
NC
VBUS
VUSB
RG2
RA2
RB3
RB2
RB7
AVDD
RB11
RA1
RB12
NC
NC
RF8
RG3
RB1
RB0
RA10
RB8
NC
RF12
RB14
VDD
RD15
RF3
RF2
RB6
RA9
AVSS
RB9
RB10
RF13
RB13
RB15
RD14
RF4
RF5
Note 1: Refer to Table 4, Table 5 and Table 6 for full pin names.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 19
PIC32MX5XX/6XX/7XX
TABLE 4:
PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,
PIC32MX575F256L AND PIC32MX575F512L DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
A1
PMD4/RE4
E8
SDA1/INT4/RA15
A2
PMD3/RE3
E9
RTCC/IC1/RD8
A3
TRD0/RG13
E10
SS1/IC2/RD9
A4
PMD0/RE0
E11
SCL1/INT3/RA14
A5
PMD8/RG0
F1
MCLR
A6
C1TX/PMD10/RF1
F2
SCL4/SDO2/U3TX/PMA3/CN10/RG8
A7
VDD
F3
SS2/U6RX/U3CTS/PMA2/CN11/RG9
A8
VSS
F4
SDA4/SDI2/U3RX/PMA4/CN9/RG7
A9
IC5/PMD12/RD12
F5
VSS
A10
OC3/RD2
F6
No Connect (NC)
A11
OC2/RD1
F7
No Connect (NC)
B1
No Connect (NC)
F8
VDD
B2
RG15
F9
OSC1/CLKI/RC12
B3
PMD2/RE2
F10
VSS
B4
PMD1/RE1
F11
OSC2/CLKO/RC15
B5
TRD3/RA7
G1
INT1/RE8
B6
C1RX/PMD11/RF0
G2
INT2/RE9
B7
VCAP/VCORE
G3
TMS/RA0
B8
PMRD/CN14/RD5
G4
No Connect (NC)
B9
OC4/RD3
G5
VDD
B10
VSS
G6
VSS
B11
SOSCO/T1CK/CN0/RC14
G7
VSS
C1
PMD6/RE6
G8
No Connect (NC)
C2
VDD
G9
TDO/RA5
C3
TRD1/RG12
G10
SDA2/RA3
C4
TRD2/RG14
G11
TDI/RA4
AN5/C1IN+/VBUSON/CN7/RB5
C5
TRCLK/RA6
H1
C6
No Connect (NC)
H2
AN4/C1IN-/CN6/RB4
C7
PMD15/CN16/RD7
H3
VSS
C8
OC5/PMWR/CN13/RD4
H4
VDD
C9
VDD
H5
No Connect (NC)
C10
SOSCI/CN1/RC13
H6
VDD
C11
IC4/PMCS1/PMA14/RD11
H7
No Connect (NC)
D1
T2CK/RC1
H8
VBUS
D2
PMD7/RE7
H9
VUSB
D3
PMD5/RE5
H10
D+/RG2
D4
VSS
H11
SCL2/RA2
D5
VSS
J1
AN3/C2IN+/CN5/RB3
D6
No Connect (NC)
J2
AN2/C2IN-/CN4/RB2
D7
PMD14/CN15/RD6
J3
PGED2/AN7/RB7
D8
PMD13/CN19/RD13
J4
AVDD
D9
SDO1/OC1/INT0/RD0
J5
AN11/PMA12/RB11
D10
No Connect (NC)
J6
TCK/RA1
D11
SCK1/IC3/PMCS2/PMA15/RD10
J7
AN12/PMA11/RB12
E1
T5CK/SDI1/RC4
J8
No Connect (NC)
E2
T4CK/RC3
J9
No Connect (NC)
E3
SCK2/U6TXU6TX/U3RTS/PMA5/CN8/RG6
J10
SCL3/SDO3/U1TX/RF8
E4
T3CK/RC2
J11
D-/RG3
E5
VDD
K1
PGEC1/AN1/CN3/RB1
E6
PMD9/RG1
K2
PGED1/AN0/CN2/RB0
E7
VSS
K3
VREF+/CVREF+/PMA6/RA10
DS61156G-page 20
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 4:
PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,
PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED)
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
K4
AN8/C1OUT/RB8
L3
AVSS
K5
No Connect (NC)
L4
AN9/C2OUT/RB9
K6
AC1RX/SS4/U5RX/U2CTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
AN14/PMALH/PMA1/RB14
L6
AC1TX/SCK4/U5TX/U2RTS/RF13
K8
VDD
L7
AN13/PMA10/RB13
K9
SCK3/U4TX/U1RTS/CN21/RD15
L8
AN15/OCFB/PMALL/PMA0/CN12/RB15
K10
USBID/RF3
L9
SS3/U4RX/U1CTS/CN20/RD14
K11
SDA3/SDI3/U1RX/RF2
L10
SDA5/SDI4/U2RX/PMA9/CN17/RF4
L1
PGEC2/AN6/OCFA/RB6
L11
SCL5/SDO4/U2TX/PMA8/CN18/RF5
L2
VREF-/CVREF-/PMA7/RA9
© 2009-2011 Microchip Technology Inc.
DS61156G-page 21
PIC32MX5XX/6XX/7XX
TABLE 5:
PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L,
PIC32MX675F512L AND PIC32MX695F512L DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
A1
PMD4/RE4
E8
A2
PMD3/RE3
E9
AETXEN/SDA1/INT4/RA15
RTCC/EMDIO/AEMDIO/IC1/RD8
A3
TRD0/RG13
E10
SS1/IC2/RD9
A4
PMD0/RE0
E11
AETXCLK/SCL1/INT3/RA14
A5
PMD8/RG0
F1
MCLR
A6
ETXD0/PMD10/RF1
F2
ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/
U3TX/PMA3/CN10/RG8
A7
VDD
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2/U6RX/
U3CTS/PMA2/CN11/RG9
A8
VSS
F4
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
A9
ETXD2/IC5/PMD12/RD12
F5
VSS
A10
OC3/RD2
F6
No Connect (NC)
A11
OC2/RD1
F7
No Connect (NC)
B1
No Connect (NC)
F8
VDD
B2
AERXERR/RG15
F9
OSC1/CLKI/RC12
B3
PMD2/RE2
F10
VSS
B4
PMD1/RE1
F11
OSC2/CLKO/RC15
B5
TRD3/RA7
G1
AERXD0/INT1/RE8
B6
ETXD1/PMD11/RF0
G2
AERXD1/INT2/RE9
B7
VCAP/VCORE
G3
TMS/RA0
B8
PMRD/CN14/RD5
G4
No Connect (NC)
B9
OC4/RD3
G5
VDD
B10
VSS
G6
VSS
B11
SOSCO/T1CK/CN0/RC14
G7
VSS
C1
PMD6/RE6
G8
No Connect (NC)
C2
VDD
G9
TDO/RA5
C3
TRD1/RG12
G10
SDA2/RA3
C4
TRD2/RG14
G11
TDI/RA4
C5
TRCLK/RA6
H1
AN5/C1IN+/VBUSON/CN7/RB5
C6
No Connect (NC)
H2
AN4/C1IN-/CN6/RB4
C7
ETXCLK/PMD15/CN16/RD7
H3
VSS
C8
OC5/PMWR/CN13/RD4
H4
VDD
C9
VDD
H5
No Connect (NC)
C10
SOSCI/CN1/RC13
H6
VDD
C11
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
H7
No Connect (NC)
D1
T2CK/RC1
H8
VBUS
D2
PMD7/RE7
H9
VUSB
D3
PMD5/RE5
H10
D+/RG2
SCL2/RA2
D4
VSS
H11
D5
VSS
J1
D6
No Connect (NC)
J2
AN2/C2IN-/CN4/RB2
D7
ETXEN/PMD14/CN15/RD6
J3
PGED2/AN7/RB7
AN3/C2IN+/CN5/RB3
D8
ETXD3/PMD13/CN19/RD13
J4
AVDD
D9
SDO1/OC1/INT0/RD0
J5
AN11/ERXERR/AETXERR/PMA12/RB11
D10
No Connect (NC)
J6
TCK/RA1
D11
SCK1/IC3/PMCS2/PMA15/RD10
J7
AN12/ERXD0/AECRS/PMA11/RB12
E1
T5CK/SDI1/RC4
J8
No Connect (NC)
E2
T4CK/RC3
J9
No Connect (NC)
E3
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
J10
SCL3/SDO3/U1TX/RF8
E4
T3CK/RC2
J11
D-/RG3
E5
VDD
K1
PGEC1/AN1/CN3/RB1
E6
ETXERR/PMD9/RG1
K2
PGED1/AN0/CN2/RB0
E7
VSS
K3
VREF+/CVREF+/AERXD3/PMA6/RA10
DS61156G-page 22
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 5:
PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L,
PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED)
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
K4
AN8/C1OUT/RB8
L3
AVSS
K5
No Connect (NC)
L4
AN9/C2OUT/RB9
K6
SS4/U5RX/U2CTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
L6
SCK4/U5TX/U2RTS/RF13
K8
VDD
L7
AN13/ERXD1/AECOL/PMA10/RB13
K9
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
L8
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K10
USBID/RF3
L9
K11
SDA3/SDI3/U1RX/RF2
L10
SDA5/SDI4/U2RX/PMA9/CN17/RF4
L1
PGEC2/AN6/OCFA/RB6
L11
SCL5/SDO4/U2TX/PMA8/CN18/RF5
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
© 2009-2011 Microchip Technology Inc.
DS61156G-page 23
PIC32MX5XX/6XX/7XX
TABLE 6:
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
A1
PMD4/RE4
E8
AETXEN/SDA1/INT4/RA15
A2
PMD3/RE3
E9
RTCC/EMDIO/AEMDIO/IC1/RD8
A3
TRD0/RG13
E10
SS1/IC2/RD9
A4
PMD0/RE0
E11
AETXCLK/SCL1/INT3/RA14
A5
C2RX/PMD8/RG0
F1
MCLR
A6
C1TX/ETXD0/PMD10/RF1
F2
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/
U3TX/PMA3/CN10/RG8
A7
VDD
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/
U3CTS/PMA2/CN11/RG9
A8
VSS
F4
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
A9
ETXD2/IC5/PMD12/RD12
F5
VSS
A10
OC3/RD2
F6
No Connect (NC)
A11
OC2/RD1
F7
No Connect (NC)
B1
No Connect (NC)
F8
VDD
B2
AERXERR/RG15
F9
OSC1/CLKI/RC12
B3
PMD2/RE2
F10
VSS
B4
PMD1/RE1
F11
OSC2/CLKO/RC15
B5
TRD3/RA7
G1
AERXD0/INT1/RE8
B6
C1RX/ETXD1/PMD11/RF0
G2
AERXD1/INT2/RE9
B7
VCAP/VCORE
G3
TMS/RA0
B8
PMRD/CN14/RD5
G4
No Connect (NC)
B9
OC4/RD3
G5
VDD
B10
VSS
G6
VSS
B11
SOSCO/T1CK/CN0/RC14
G7
VSS
C1
PMD6/RE6
G8
No Connect (NC)
TDO/RA5
C2
VDD
G9
C3
TRD1/RG12
G10
SDA2/RA3
C4
TRD2/RG14
G11
TDI/RA4
C5
TRCLK/RA6
H1
AN5/C1IN+/VBUSON/CN7/RB5
C6
No Connect (NC)
H2
AN4/C1IN-/CN6/RB4
C7
ETXCLK/PMD15/CN16/RD7
H3
VSS
C8
OC5/PMWR/CN13/RD4
H4
VDD
C9
VDD
H5
No Connect (NC)
C10
SOSCI/CN1/RC13
H6
VDD
C11
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
H7
No Connect (NC)
D1
T2CK/RC1
H8
VBUS
D2
PMD7/RE7
H9
VUSB
D3
PMD5/RE5
H10
D+/RG2
D4
VSS
H11
SCL2/RA2
D5
VSS
J1
AN3/C2IN+/CN5/RB3
D6
No Connect (NC)
J2
AN2/C2IN-/CN4/RB2
D7
ETXEN/PMD14/CN15/RD6
J3
PGED2/AN7/RB7
D8
ETXD3/PMD13/CN19/RD13
J4
AVDD
AN11/ERXERR/AETXERR/PMA12/RB11
D9
SDO1/OC1/INT0/RD0
J5
D10
No Connect (NC)
J6
TCK/RA1
D11
SCK1/IC3/PMCS2/PMA15/RD10
J7
AN12/ERXD0/AECRS/PMA11/RB12
E1
T5CK/SDI1/RC4
J8
No Connect (NC)
E2
T4CK/AC2RX/RC3
J9
No Connect (NC)
E3
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
J10
SCL3/SDO3/U1TX/RF8
E4
T3CK/AC2TX/RC2
J11
D-/RG3
E5
VDD
K1
PGEC1/AN1/CN3/RB1
E6
C2TX/ETXERR/PMD9/RG1
K2
PGED1/AN0/CN2/RB0
E7
VSS
K3
VREF+/CVREF+/AERXD3/PMA6/RA10
DS61156G-page 24
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 6:
PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES (CONTINUED)
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
K4
AN8/C1OUT/RB8
L3
K5
No Connect (NC)
L4
AVSS
AN9/C2OUT/RB9
K6
AC1RX/SS4/U5RX/U2CTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
L6
AC1TX/SCK4/U5TX/U2RTS/RF13
K8
VDD
L7
AN13/ERXD1/AECOL/PMA10/RB13
K9
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
L8
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K10
USBID/RF3
L9
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K11
SDA3/SDI3/U1RX/RF2
L10
SDA5/SDI4/U2RX/PMA9/CN17/RF4
L1
PGEC2/AN6/OCFA/RB6
L11
SCL5/SDO4/U2TX/PMA8/CN18/RF5
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
© 2009-2011 Microchip Technology Inc.
DS61156G-page 25
PIC32MX5XX/6XX/7XX
TABLE 7:
PIN NAME: PIC32MX764F128L DEVICE
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
A1
PMD4/RE4
E8
AETXEN/SDA1/INT4/RA15
A2
PMD3/RE3
E9
RTCC/EMDIO/AEMDIO/IC1/RD8
A3
TRD0/RG13
E10
SS1/IC2/RD9
A4
PMD0/RE0
E11
AETXCLK/SCL1/INT3/RA14
A5
PMD8/RG0
F1
MCLR
A6
C1TX/ETXD0/PMD10/RF1
F2
ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/
U3TX/PMA3/CN10/RG8
A7
VDD
F3
ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/
U3CTS/PMA2/CN11/RG9
A8
VSS
F4
ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
A9
ETXD2/IC5/PMD12/RD12
F5
VSS
A10
OC3/RD2
F6
No Connect (NC)
A11
OC2/RD1
F7
No Connect (NC)
B1
No Connect (NC)
F8
VDD
B2
AERXERR/RG15
F9
OSC1/CLKI/RC12
B3
PMD2/RE2
F10
VSS
B4
PMD1/RE1
F11
OSC2/CLKO/RC15
B5
TRD3/RA7
G1
AERXD0/INT1/RE8
B6
C1RX/ETXD1/PMD11/RF0
G2
AERXD1/INT2/RE9
B7
VCAP/VCORE
G3
TMS/RA0
B8
PMRD/CN14/RD5
G4
No Connect (NC)
B9
OC4/RD3
G5
VDD
B10
VSS
G6
VSS
B11
SOSCO/T1CK/CN0/RC14
G7
VSS
C1
PMD6/RE6
G8
No Connect (NC)
TDO/RA5
C2
VDD
G9
C3
TRD1/RG12
G10
SDA2/RA3
C4
TRD2/RG14
G11
TDI/RA4
C5
TRCLK/RA6
H1
AN5/C1IN+/VBUSON/CN7/RB5
C6
No Connect (NC)
H2
AN4/C1IN-/CN6/RB4
C7
ETXCLK/PMD15/CN16/RD7
H3
VSS
C8
OC5/PMWR/CN13/RD4
H4
VDD
C9
VDD
H5
No Connect (NC)
C10
SOSCI/CN1/RC13
H6
VDD
C11
EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
H7
No Connect (NC)
D1
T2CK/RC1
H8
VBUS
D2
PMD7/RE7
H9
VUSB
D3
PMD5/RE5
H10
D+/RG2
D4
VSS
H11
SCL2/RA2
D5
VSS
J1
AN3/C2IN+/CN5/RB3
D6
No Connect (NC)
J2
AN2/C2IN-/CN4/RB2
D7
ETXEN/PMD14/CN15/RD6
J3
PGED2/AN7/RB7
D8
ETXD3/PMD13/CN19/RD13
J4
AVDD
AN11/ERXERR/AETXERR/PMA12/RB11
D9
SDO1/OC1/INT0/RD0
J5
D10
No Connect (NC)
J6
TCK/RA1
D11
SCK1/IC3/PMCS2/PMA15/RD10
J7
AN12/ERXD0/AECRS/PMA11/RB12
E1
T5CK/SDI1/RC4
J8
No Connect (NC)
E2
T4CK/RC3
J9
No Connect (NC)
E3
ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
J10
SCL3/SDO3/U1TX/RF8
E4
T3CK/RC2
J11
D-/RG3
E5
VDD
K1
PGEC1/AN1/CN3/RB1
E6
ETXERR/PMD9/RG1
K2
PGED1/AN0/CN2/RB0
E7
VSS
K3
VREF+/CVREF+/AERXD3/PMA6/RA10
DS61156G-page 26
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 7:
PIN NAME: PIC32MX764F128L DEVICE (CONTINUED)
Pin
Number
Full Pin Name
Pin
Number
Full Pin Name
K4
AN8/C1OUT/RB8
L3
K5
No Connect (NC)
L4
AVSS
AN9/C2OUT/RB9
K6
AC1RX/SS4/U5RX/U2CTS/RF12
L5
AN10/CVREFOUT/PMA13/RB10
K7
AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
L6
AC1TX/SCK4/U5TX/U2RTS/RF13
K8
VDD
L7
AN13/ERXD1/AECOL/PMA10/RB13
K9
AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
L8
AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K10
USBID/RF3
L9
AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K11
SDA3/SDI3/U1RX/RF2
L10
SDA5/SDI4/U2RX/PMA9/CN17/RF4
L1
PGEC2/AN6/OCFA/RB6
L11
SCL5/SDO4/U2TX/PMA8/CN18/RF5
L2
VREF-/CVREF-/AERXD2/PMA7/RA9
© 2009-2011 Microchip Technology Inc.
DS61156G-page 27
PIC32MX5XX/6XX/7XX
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 31
2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 43
3.0 CPU............................................................................................................................................................................................ 49
4.0 Memory Organization ................................................................................................................................................................. 55
5.0 Flash Program Memory ............................................................................................................................................................ 117
6.0 Resets ...................................................................................................................................................................................... 119
7.0 Interrupt Controller ................................................................................................................................................................... 121
8.0 Oscillator Configuration ............................................................................................................................................................ 125
9.0 Prefetch Cache......................................................................................................................................................................... 127
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 129
11.0 USB On-The-Go (OTG)............................................................................................................................................................ 131
12.0 I/O Ports ................................................................................................................................................................................... 133
13.0 Timer1 ...................................................................................................................................................................................... 135
14.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 137
15.0 Input Capture............................................................................................................................................................................ 139
16.0 Output Compare....................................................................................................................................................................... 141
17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 143
18.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 145
19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 147
20.0 Parallel Master Port (PMP)....................................................................................................................................................... 149
21.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 151
22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 153
23.0 Controller Area Network (CAN) ................................................................................................................................................ 155
24.0 Ethernet Controller ................................................................................................................................................................... 157
25.0 Comparator .............................................................................................................................................................................. 159
26.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 161
27.0 Power-Saving Features ........................................................................................................................................................... 163
28.0 Special Features ...................................................................................................................................................................... 165
29.0 Instruction Set .......................................................................................................................................................................... 177
30.0 Development Support............................................................................................................................................................... 179
31.0 Electrical Characteristics .......................................................................................................................................................... 183
32.0 Packaging Information.............................................................................................................................................................. 225
The Microchip Web Site ..................................................................................................................................................................... 253
Customer Change Notification Service .............................................................................................................................................. 253
Customer Support .............................................................................................................................................................................. 253
Reader Response .............................................................................................................................................................................. 254
Product Identification System............................................................................................................................................................. 255
DS61156G-page 28
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of
your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications
Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data
sheet to (480) 792-4150. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner
of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may
exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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© 2009-2011 Microchip Technology Inc.
DS61156G-page 29
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 30
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
1.0
DEVICE OVERVIEW
This document contains device-specific information for
PIC32MX5XX/6XX/7XX devices.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
Figure 1-1 illustrates a general block diagram of the
core
and
peripheral
modules
in
the
PIC32MX5XX/6XX/7XX family of devices.
Table 1-1 lists the functions of the various pins shown
in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
BLOCK DIAGRAM(1,2)
FIGURE 1-1:
OSC2/CLKO
OSC1/CLKI
VCAP/VCORE
OSC/SOSC
Oscillators
Power-up
Timer
FRC/LPRC
Oscillators
Voltage
Regulator
PLL
Oscillator
Start-up Timer
PLL-USB
Watchdog
Timer
USBCLK
SYSCLK
PBCLK
Timing
Generation
Brown-out
Reset
Peripheral Bus Clocked by SYSCLK
CN1-22
PORTA
USB
M4K®
32
CPU Core
PORTC
IS
32
DS
32
32
32
32
32
32
32
PORTD
Bus Matrix
32
32
IC1-5
SPI1-4
I2C1-5
32
PORTE
Prefetch
Module
PWM
OC1-5
Peripheral Bus Clocked by PBCLK
MIPS32®
ICD
INT
PORTB
DMAC
EJTAG
Timer1-5
ETHERNET
Priority
Interrupt
Controller
CAN1, CAN2
JTAG
BSCAN
MCLR
Power-on
Reset
Precision
Band Gap
Reference
Dividers
VDD, VSS
32
Data RAM
Peripheral Bridge
PMP
10-bit ADC
PORTF
PORTG
128-bit Wide
Program Flash Memory
Flash
Controller
128
UART1-6
RTCC
Comparators
Note
1:
2:
Some features are not available on all device variants.
BOR functionality is provided when the on-board voltage regulator is enabled.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 31
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS
Pin Number(1)
Pin
Type
Buffer
Type
K2
K1
J2
J1
H2
H1
L1
J3
K4
L4
L5
I
I
I
I
I
I
I
I
I
I
I
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
Analog
35
41
42
43
44
63
J5
J7
L7
K7
L8
F9
I
I
I
I
I
I
40
64
F11
O
OSC1
39
63
F9
I
OSC2
40
64
F11
I/O
SOSCI
47
73
C10
I
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN10
16
15
14
13
12
11
17
18
21
22
23
25
24
23
22
21
20
26
27
32
33
34
AN11
AN12
AN13
AN14
AN15
CLKI
24
27
28
29
30
39
CLKO
Description
Analog input channels.
Analog
Analog
Analog
Analog
Analog
ST/CMOS External clock source input. Always associated
with OSC1 pin function.
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
ST/CMOS Oscillator crystal input. ST buffer when
configured in RC mode; CMOS otherwise.
—
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode. Optionally
functions as CLKO in RC and EC modes.
ST/CMOS 32.768 kHz low-power oscillator crystal input;
CMOS otherwise.
—
32.768 kHz low-power oscillator crystal output.
Analog = Analog input
P = Power
O = Output
I = Input
SOSCO
48
74
B11
O
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156G-page 32
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
CN0
CN1
CN2
CN3
CN4
CN5
CN6
CN7
CN8
CN9
CN10
CN11
CN12
CN13
CN14
CN15
CN16
CN17
CN18
CN19
CN20
CN21
IC1
IC2
IC3
IC4
IC5
OCFA
OC1
OC2
OC3
OC4
OC5
OCFB
INT0
INT1
INT2
INT3
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
48
47
16
15
14
13
12
11
4
5
6
8
30
52
53
54
55
31
32
—
—
—
42
43
44
45
52
17
46
49
50
51
52
30
46
42
43
44
74
73
25
24
23
22
21
20
10
11
12
14
44
81
82
83
84
49
50
80
47
48
68
69
70
71
79
26
72
76
77
78
81
44
72
18
19
66
B11
C10
K2
K1
J2
J1
H2
H1
E3
F4
F2
F3
L8
C8
B8
D7
C7
L10
L11
D8
L9
K9
E9
E10
D11
C11
A9
L1
D9
A11
A10
B9
C8
L8
D9
G1
G2
E11
Pin
Type
Buffer
Type
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
—
—
—
ST
ST
ST
ST
ST
Description
Change notification inputs.
Can be software programmed for internal weak
pull-ups on all inputs.
Capture Inputs 1-5
Output Compare Fault A Input
Output Compare Output 1
Output Compare Output 2
Output Compare Output 3
Output Compare Output 4
Output Compare Output 5
Output Compare Fault B Input
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
INT4
45
67
E8
I
ST
External Interrupt 4
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 33
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Pin
Type
Buffer
Type
Description
RA0
—
17
G3
I/O
ST
PORTA is a bidirectional I/O port
RA1
—
38
J6
I/O
ST
RA2
—
58
H11
I/O
ST
RA3
—
59
G10
I/O
ST
RA4
—
60
G11
I/O
ST
RA5
—
61
G9
I/O
ST
RA6
—
91
C5
I/O
ST
RA7
—
92
B5
I/O
ST
RA9
—
28
L2
I/O
ST
RA10
—
29
K3
I/O
ST
RA14
—
66
E11
I/O
ST
RA15
—
67
E8
I/O
ST
RB0
16
25
K2
I/O
ST
PORTB is a bidirectional I/O port
RB1
15
24
K1
I/O
ST
RB2
14
23
J2
I/O
ST
RB3
13
22
J1
I/O
ST
RB4
12
21
H2
I/O
ST
RB5
11
20
H1
I/O
ST
RB6
17
26
L1
I/O
ST
RB7
18
27
J3
I/O
ST
RB8
21
32
K4
I/O
ST
RB9
22
33
L4
I/O
ST
RB10
23
34
L5
I/O
ST
RB11
24
35
J5
I/O
ST
RB12
27
41
J7
I/O
ST
RB13
28
42
L7
I/O
ST
RB14
29
43
K7
I/O
ST
RB15
30
44
L8
I/O
ST
RC1
—
6
D1
I/O
ST
PORTC is a bidirectional I/O port
RC2
—
7
E4
I/O
ST
RC3
—
8
E2
I/O
ST
RC4
—
9
E1
I/O
ST
RC12
39
63
F9
I/O
ST
RC13
47
73
C10
I/O
ST
RC14
48
74
B11
I/O
ST
RC15
40
64
F11
I/O
ST
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156G-page 34
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
Pin
Type
Buffer
Type
Description
RD0
46
72
D9
I/O
ST
PORTD is a bidirectional I/O port
RD1
49
76
A11
I/O
ST
RD2
50
77
A10
I/O
ST
RD3
51
78
B9
I/O
ST
RD4
52
81
C8
I/O
ST
RD5
53
82
B8
I/O
ST
RD6
54
83
D7
I/O
ST
RD7
55
84
C7
I/O
ST
RD8
42
68
E9
I/O
ST
RD9
43
69
E10
I/O
ST
RD10
44
70
D11
I/O
ST
RD11
45
71
C11
I/O
ST
RD12
—
79
A9
I/O
ST
RD13
—
80
D8
I/O
ST
RD14
—
47
L9
I/O
ST
RD15
—
48
K9
I/O
ST
RE0
60
93
A4
I/O
ST
PORTE is a bidirectional I/O port
RE1
61
94
B4
I/O
ST
RE2
62
98
B3
I/O
ST
RE3
63
99
A2
I/O
ST
RE4
64
100
A1
I/O
ST
RE5
1
3
D3
I/O
ST
RE6
2
4
C1
I/O
ST
RE7
3
5
D2
I/O
ST
RE8
—
18
G1
I/O
ST
RE9
—
19
G2
I/O
ST
RF0
58
87
B6
I/O
ST
PORTF is a bidirectional I/O port
RF1
59
88
A6
I/O
ST
RF2
—
52
K11
I/O
ST
RF3
33
51
K10
I/O
ST
RF4
31
49
L10
I/O
ST
RF5
32
50
L11
I/O
ST
RF8
—
53
J10
I/O
ST
RF12
—
40
K6
I/O
ST
RF13
—
39
L6
I/O
ST
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 35
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
I
I
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
L9
I
ST
UART1 clear to send
K9
K11
O
—
UART1 ready to send
I
ST
UART1 receive
O
—
UART1 transmit
I
ST
UART3 clear to send
E3
F4
O
—
UART3 ready to send
I
ST
UART3 receive
12
F2
O
—
UART3 transmit
21
40
K6
I
ST
UART2 clear to send
39
49
L6
L10
O
—
UART2 ready to send
U2RX
29
31
I
ST
UART2 receive
U2TX
32
50
L11
O
—
UART2 transmit
U4RX
43
47
L9
I
ST
UART4 receive
U4TX
49
48
K9
O
—
UART4 transmit
U6RX
8
14
F3
I
ST
UART6 receive
U6TX
4
10
E3
O
—
UART6 transmit
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
RG0
RG1
RG6
RG7
RG8
RG9
RG12
RG13
RG14
RG15
RG2
RG3
T1CK
T2CK
T3CK
T4CK
T5CK
—
—
4
5
6
8
—
—
—
—
37
36
48
—
—
—
—
90
89
10
11
12
14
96
97
95
1
57
56
74
6
7
8
9
A5
E6
E3
F4
F2
F3
C3
A3
C4
B2
H10
J11
B11
D1
E4
E2
E1
U1CTS
43
47
U1RTS
U1RX
49
50
48
52
U1TX
51
53
J10
U3CTS
8
14
F3
U3RTS
U3RX
4
5
10
11
U3TX
6
U2CTS
U2RTS
Description
PORTG is a bidirectional I/O port
PORTG input pins
Timer1 external clock input
Timer2 external clock input
Timer3 external clock input
Timer4 external clock input
Timer5 external clock input
U5RX
21
40
K6
I
ST
UART5 receive
U5TX
SCK1
SDI1
29
39
L6
—
—
70
9
D11
E1
O
I/O
I
—
ST
ST
UART5 transmit
Synchronous serial clock input/output for SPI1
SPI1 data in
SDO1
—
72
D9
O
—
SPI1 data out
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156G-page 36
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
Description
E10
K9
K11
J10
I/O
I/O
I
O
ST
ST
ST
—
SPI1 slave synchronization or frame pulse I/O
Synchronous serial clock input/output for SPI3
SPI3 data in
SPI3 data out
47
10
11
12
L9
E3
F4
F2
I/O
I/O
I
O
ST
ST
ST
—
SPI3 slave synchronization or frame pulse I/O
Synchronous serial clock input/output for SPI2
SPI2 data in
SPI2 data out
8
29
31
32
14
39
49
50
F3
L6
L10
L11
I/O
I/O
I
O
ST
ST
ST
—
SPI2 slave synchronization or frame pulse I/O
Synchronous serial clock input/output for SPI4
SPI4 data in
SPI4 data out
SS4
SCL1
SDA1
SCL3
SDA3
SCL2
SDA2
SCL4
SDA4
SCL5
SDA5
TMS
TCK
TDI
TDO
RTCC
21
44
43
51
50
—
—
6
5
32
31
23
27
28
24
42
40
66
67
53
52
58
59
12
11
50
49
17
38
60
61
68
K6
E11
E8
J10
K11
H11
G10
F2
F4
L11
L10
G3
J6
G11
G9
E9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
O
O
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
—
—
SPI4 slave synchronization or frame pulse I/O
Synchronous serial clock input/output for I2C1
Synchronous serial data input/output for I2C1
Synchronous serial clock input/output for I2C3
Synchronous serial data input/output for I2C3
Synchronous serial clock input/output for I2C2
Synchronous serial data input/output for I2C2
Synchronous serial clock input/output for I2C4
Synchronous serial data input/output for I2C4
Synchronous serial clock input/output for I2C5
Synchronous serial data input/output for I2C5
JTAG Test mode select pin
JTAG test clock input pin
JTAG test data input pin
JTAG test data output pin
Real-Time Clock alarm output
CVREFCVREF+
CVREFOUT
15
16
28
29
L2
K3
I
I
Analog
Analog
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
SS1
SCK3
SDI3
SDO3
—
49
50
51
69
48
52
53
SS3
43
4
5
6
SCK4
SDI4
SDO4
SCK2
SDI2
SDO2
SS2
Comparator Voltage Reference (low)
Comparator Voltage Reference (high)
23
34
L5
O
Analog Comparator Voltage Reference output
C1IN12
21
H2
I
Analog Comparator 1 negative input
C1IN+
11
20
H1
I
Analog Comparator 1 positive input
C1OUT
21
32
K4
O
—
Comparator 1 output
C2IN14
23
J2
I
Analog Comparator 2 negative input
C2IN+
13
22
J1
I
Analog Comparator 2 positive input
C2OUT
22
33
L4
O
—
Comparator 2 output
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 37
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
Pin
Type
Buffer
Type
L8
I/O
TTL/ST
43
K7
I/O
TTL/ST
14
12
11
10
29
28
50
49
42
41
35
34
71
70
71
70
F3
F2
F4
E3
K3
L2
L11
L10
L7
J7
J5
L5
C11
D11
C11
D11
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
PMA0
30
44
PMA1
29
PMA2
PMA3
PMA4
PMA5
PMA6
PMA7
PMA8
PMA9
PMA10
PMA11
PMA12
PMA13
PMA14
PMA15
PMCS1
PMCS2
8
6
5
4
16
22
32
31
28
27
24
23
45
44
45
44
Description
Parallel Master Port Address bit 0 input
(Buffered Slave modes) and output (Master
modes)
Parallel Master Port Address bit 1 input
(Buffered Slave modes) and output (Master
modes)
Parallel Master Port address (Demultiplexed
Master modes)
Parallel Master Port Chip Select 1 strobe
Parallel Master Port Chip Select 2 strobe
PMD0
60
93
A4
I/O
TTL/ST Parallel Master Port data (Demultiplexed
PMD1
61
94
B4
I/O
TTL/ST Master mode) or address/data (Multiplexed
Master modes)
PMD2
62
98
B3
I/O
TTL/ST
PMD3
63
99
A2
I/O
TTL/ST
PMD4
64
100
A1
I/O
TTL/ST
PMD5
1
3
D3
I/O
TTL/ST
PMD6
2
4
C1
I/O
TTL/ST
PMD7
3
5
D2
I/O
TTL/ST
PMD8
—
90
A5
I/O
TTL/ST
PMD9
—
89
E6
I/O
TTL/ST
PMD10
—
88
A6
I/O
TTL/ST
PMD11
—
87
B6
I/O
TTL/ST
PMD12
—
79
A9
I/O
TTL/ST
PMD13
—
80
D8
I/O
TTL/ST
PMD14
—
83
D7
I/O
TTL/ST
PMD15
—
84
C7
I/O
TTL/ST
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156G-page 38
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
L8
O
—
43
K7
O
—
53
52
34
35
82
81
54
55
B8
C8
H8
H9
O
O
I
P
—
—
Analog
—
VBUSON
D+
DUSBID
C1RX
C1TX
AC1RX
AC1TX
C2RX
C2TX
AC2RX
AC2TX
ERXD0
ERXD1
ERXD2
11
37
36
33
58
59
32
31
29
21
—
—
61
60
59
20
57
56
51
87
88
40
39
90
89
8
7
41
42
43
H1
H10
J11
K10
B6
A6
K6
L6
A5
E6
E2
E4
J7
L7
K7
O
I/O
I/O
I
I
O
I
O
I
O
1
O
I
I
I
—
Analog
Analog
ST
ST
—
ST
—
ST
—
ST
—
ST
ST
ST
ERXD3
ERXERR
ERXDV
ECRSDV
ERXCLK
EREFCLK
ETXD0
ETXD1
ETXD2
ETXD3
ETXERR
ETXEN
ETXCLK
58
64
62
62
63
63
2
3
43
42
54
1
55
44
35
12
12
14
14
88
87
79
80
89
83
84
L8
J5
F2
F2
F3
F3
A6
B6
A9
D8
E6
D7
C7
I
I
I
I
I
I
O
O
O
O
O
O
I
ST
ST
ST
ST
ST
ST
—
—
—
—
—
—
ST
Ethernet Receive Data 3(2)
Ethernet receive error input(2)
Ethernet receive data valid(2)
Ethernet carrier sense data valid(2)
Ethernet receive clock(2)
Ethernet reference clock(2)
Ethernet Transmit Data 0(2)
Ethernet Transmit Data 1(2)
Ethernet Transmit Data 2(2)
Ethernet Transmit Data 3(2)
Ethernet transmit error(2)
Ethernet transmit enable(2)
Ethernet transmit clock(2)
ECOL
ECRS
44
45
10
11
E3
F4
I
I
ST
ST
Ethernet collision detect(2)
Ethernet carrier sense(2)
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
PMALL
30
44
PMALH
29
PMRD
PMWR
VBUS
VUSB
Description
Parallel Master Port address latch enable
low byte (Multiplexed Master modes)
Parallel Master Port address latch enable
high byte (Multiplexed Master modes)
Parallel Master Port read strobe
Parallel Master Port write strobe
USB bus power monitor
USB internal transceiver supply. If the USB
module is not used, this pin must be connected
to VDD.
USB Host and OTG bus power control output
USB D+
USB DUSB OTG ID detect
CAN1 bus receive pin
CAN1 bus transmit pin
Alternate CAN1 bus receive pin
Alternate CAN1 bus transmit pin
CAN2 bus receive pin
CAN2 bus transmit pin
Alternate CAN2 bus receive pin
Alternate CAN2 bus transmit pin
Ethernet Receive Data 0(2)
Ethernet Receive Data 1(2)
Ethernet Receive Data 2(2)
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 39
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin
Type
Buffer
Type
C11
O
—
Ethernet management data clock(2)
68
18
19
28
29
1
12
12
14
14
E9
G1
G2
L2
K3
B2
F2
F2
F3
F3
I/O
I
I
I
I
I
I
I
I
I
—
ST
ST
ST
ST
ST
ST
ST
ST
ST
Ethernet management data(2)
Alternate Ethernet Receive Data 0(2)
Alternate Ethernet Receive Data 1(2)
Alternate Ethernet Receive Data 2(2)
Alternate Ethernet Receive Data 3(2)
Alternate Ethernet receive error input(2)
Alternate Ethernet receive data valid(2)
Alternate Ethernet carrier sense data valid(2)
Alternate Ethernet receive clock(2)
Alternate Ethernet reference clock(2)
59
58
—
—
—
54
—
—
—
30
49
—
47
48
44
43
35
67
66
42
41
71
68
91
L9
K9
L8
K7
J5
E8
E11
L7
J7
C11
E9
C5
O
O
O
O
O
O
I
I
I
O
I/O
O
—
—
—
—
—
—
ST
ST
ST
—
—
—
Alternate Ethernet Transmit Data 0(2)
Alternate Ethernet Transmit Data 1(2)
Alternate Ethernet Transmit Data 2(2)
Alternate Ethernet Transmit Data 3(2)
Alternate Ethernet transmit error(2)
Alternate Ethernet transmit enable(2)
Alternate Ethernet transmit clock(2)
Alternate Ethernet collision detect(2)
Alternate Ethernet carrier sense(2)
Alternate Ethernet Management Data clock(2)
Alternate Ethernet Management Data(2)
Trace clock
TRD0
TRD1
TRD2
TRD3
PGED1
—
—
—
—
16
97
96
95
92
25
A3
C3
C4
B5
K2
O
O
O
O
I/O
—
—
—
—
ST
Trace Data bits 0-3
PGEC1
15
24
K1
I
ST
PGED2
18
27
J3
I/O
ST
PGEC2
17
26
L1
I
ST
MCLR
7
13
F1
I/P
ST
Pin Name
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
EMDC
30
71
EMDIO
AERXD0
AERXD1
AERXD2
AERXD3
AERXERR
AERXDV
AECRSDV
AERXCLK
AEREFCLK
49
43
42
—
—
55
—
44
—
45
AETXD0
AETXD1
AETXD2
AETXD3
AETXERR
AETXEN
AETXCLK
AECOL
AECRS
AEMDC
AEMDIO
TRCLK
Description
Data I/O pin for Programming/Debugging
Communication Channel 1
Clock input pin for Programming/Debugging
Communication Channel 1
Data I/O pin for Programming/Debugging
Communication Channel 2
Clock input pin for Programming/Debugging
Communication Channel 2
Master Clear (Reset) input. This pin is an
active-low Reset to the device.
Analog = Analog input
P = Power
O = Output
I = Input
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
DS61156G-page 40
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 1-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Name
AVDD
64-Pin
QFN/TQFP
100-Pin
TQFP
121-Pin
XBGA
19
30
J4
Buffer
Type
P
P
Description
Positive supply for analog modules. This pin
must be connected at all times.
Ground reference for analog modules
Positive supply for peripheral logic and I/O pins
L3
P
P
A7, C2,
P
—
C9, E5,
K8, F8,
G5, H4, H6
56
85
B7
P
—
Capacitor for Internal Voltage Regulator
VCAP/VCORE
VSS
9, 25, 41 15, 36, 45, A8, B10,
P
—
Ground reference for logic and I/O pins. This
65, 75
D4, D5,
pin must be connected at all times.
E7, F5,
F10, G6,
G7, H3
16
29
K3
I
Analog Analog voltage reference (high) input
VREF+
VREF15
28
L2
I
Analog Analog voltage reference (low) input
Legend: CMOS = CMOS compatible input or output
Analog = Analog input
P = Power
ST = Schmitt Trigger input with CMOS levels
O = Output
I = Input
TTL = TTL input buffer
Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability.
2: See Section 24.0 “Ethernet Controller” for more information.
AVSS
VDD
20
31
10, 26, 38, 2, 16, 37,
57
46, 62, 86
Pin
Type
© 2009-2011 Microchip Technology Inc.
DS61156G-page 41
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 42
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.0
GUIDELINES FOR GETTING
STARTED WITH 32-BIT
MICROCONTROLLERS
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
Getting started with the PIC32MX5XX/6XX/7XX family
of 32-bit Microcontrollers (MCUs) requires attention to
a minimal set of device pin connections before proceeding with development. The following is a list of pin
names, which must always be connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins even if the ADC module is
not used
(see Section 2.2 “Decoupling Capacitors”)
• VCAP/VCORE pin
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP/VCORE)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging
purposes
2.2
Decoupling Capacitors
The use of decoupling capacitors on power supply
pins, such as VDD, VSS, AVDD and AVSS is required.
See Figure 2-1.
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: A value of 0.1 µF
(100 nF), 10-20V is recommended. The capacitor
should be a low Equivalent Series Resistance
(low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is
further recommended to use ceramic capacitors.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended that
the capacitors be placed on the same side of
the board as the device. If space is constricted,
the capacitor can be placed on another layer on
the PCB using a via; however, ensure that the
trace length from the pin to the capacitor is
within one-quarter inch (6 mm) in length.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.8 “External Oscillator Pins”)
The following pin may be required, as well:
VREF+/VREF- pins used when external voltage reference
for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected, regardless of the ADC use
and the ADC voltage reference source.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 43
PIC32MX5XX/6XX/7XX
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
CBP
R1
MCLR
C
VSS
VCAP/VCORE
R
VDD
CEFC
VDD
PIC32
VSS
10 Ω
2.2.1
VDD
0.1 µF
Ceramic
CBP
VSS
VDD
AVSS
VDD
AVDD
0.1 µF
Ceramic
CBP
VSS
0.1 µF
Ceramic
CBP
0.1 µF
Ceramic
CBP
BULK CAPACITORS
The use of a bulk capacitor is recommended to improve
power supply stability. Typical values range from 4.7 µF
to 47 µF. This capacitor should be located as close to
the device as possible.
2.3
2.3.1
2.4
Master Clear (MCLR) Pin
The MCLR
functions:
pin
specific
device
Pulling The MCLR pin low generates a device Reset.
Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
not be adversely affected. Therefore, specific values
of R and C will need to be adjusted based on the
application and PCB requirements.
For example, as illustrated in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
Place the components illustrated in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
VDD
R
R1
INTERNAL REGULATOR MODE
DS61156G-page 44
two
• Device Reset
• Device Programming and Debugging
Capacitor on Internal Voltage
Regulator (VCAP/VCORE)
A low-ESR (1 ohm) capacitor is required on the
VCAP/VCORE pin, which is used to stabilize the internal
voltage regulator output. The VCAP/VCORE pin must not
be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The
type can be ceramic or tantalum. Refer to Section 31.0
“Electrical Characteristics” for additional information
on CEFC specifications.
provides
JP
MCLR
PIC32
C
Note 1:
R ≤10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin
VIH and VIL specifications are met.
2:
R1 ≤ 470Ω will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
3:
The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend
the device Reset period during the POR.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.5
ICSP Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communications to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB® ICD 3 or MPLAB® REAL
ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip web
site.
• “MPLAB® ICD 2 In-Circuit Debugger User’s
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3” (poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
• “Using MPLAB® REAL ICE™ Emulator” (poster)
DS51749
© 2009-2011 Microchip Technology Inc.
2.6
JTAG
The TMS, TDO, TDI and TCK pins are used for testing
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete components are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.
2.7
Trace
The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time
instruction trace. When used for trace the TRD3,
TRD2, TRD1, TRD0 and TRCLK pins should be
dedicated for this use. The trace hardware requires
a 22Ω series resistor between the trace pins and the
trace connector.
DS61156G-page 45
PIC32MX5XX/6XX/7XX
2.8
External Oscillator Pins
Many MCUs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator. Refer to Section 8.0 “Oscillator
Configuration” for details.
The oscillator circuit should be placed on the same side
of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The
load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
copper pour around the oscillator circuit to isolate them
from surrounding circuits. The grounded copper pour
should be routed directly to the MCU ground. Do not
run any signal traces or power traces inside the ground
pour. Also, if using a two-sided board, avoid any traces
on the other side of the board where the crystal is
placed. A suggested layout is illustrated in Figure 2-3.
FIGURE 2-3:
SUGGESTED OSCILLATOR
CIRCUIT PLACEMENT
Oscillator
Secondary
Guard Trace
Guard Ring
Main Oscillator
DS61156G-page 46
2.9
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as
a debugger, it automatically initializes all of the
Analog-to-Digital input pins (ANx) as “digital” pins by
setting all bits in the ADPCFG register.
The bits in this register that correspond to the Analogto-Digital pins that are initialized by MPLAB ICD 2, ICD
3 or REAL ICE, must not be cleared by the user
application firmware; otherwise, communication errors
will result between the debugger and the device.
If your application needs to use certain ADC pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
ADPCFG register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a
programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger
operation. Failure to correctly configure the register(s)
will result in all ADC pins being recognized as analog
input pins, resulting in the port value being read as a
logic ‘0’, which may affect user application functionality.
2.10
Unused I/Os
Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
2.11
Referenced Sources
This device data sheet is based on the following
individual chapters of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the PIC32MX795F512L product page on
the
Microchip
web
site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Section 1. “Introduction” (DS61127)
Section 2. “CPU” (DS61113)
Section 4. “Prefetch Cache” (DS61119)
Section 3. “Memory Organization” (DS61115)
Section 5. “Flash Program Memory” (DS61121)
Section 6. “Oscillator Configuration” (DS61112)
Section 7. “Resets” (DS61118)
Section 8. “Interrupt Controller” (DS61108)
Section 9. “Watchdog Timer and Power-up Timer (DS61114)
Section 10. “Power-Saving Features” (DS61130)
Section 12. “I/O Ports” (DS61120)
Section 13. “Parallel Master Port (PMP)” (DS61128)
Section 14. “Timers” (DS61105)
Section 15. “Input Capture” (DS61122)
Section 16. “Output Capture” (DS61111)
Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104)
Section 19. “Comparator” (DS61110)
Section 20. “Comparator Voltage Reference (CVREF)” (DS61109)
Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107)
Section 23. “Serial Peripheral Interface (SPI)” (DS61106)
Section 24. “Inter-Integrated Circuit (I2C™)” (DS61116)
Section 27. “USB On-The-Go (OTG)” (DS61126)
Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125)
Section 31. “Direct Memory Access (DMA) Controller” (DS61117)
Section 32. “Configuration” (DS61124)
Section 33. “Programming and Diagnostics” (DS61129)
Section 34. “Controller Area Network (CAN)” (DS61154)
Section 35. “Ethernet Controller” (DS61155)
© 2009-2011 Microchip Technology Inc.
DS61156G-page 47
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 48
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
CPU
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 2. “CPU”
(DS61113) in the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site (www.microchip.com/PIC32). Resources for the
MIPS32® M4K® Processor Core are
available at http://www.mips.com.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The MIPS32® M4K® Processor core is the heart of the
PIC32MX5XX/6XX/7XX family processor. The CPU
fetches instructions, decodes each instruction, fetches
source operands, executes each instruction and writes
the results of instruction execution to the proper
destinations.
3.1
•
•
•
•
Features
• 5-stage pipeline
• 32-bit address and data paths
• MIPS32 Enhanced Architecture (Release 2)
- Multiply-accumulate and multiply-subtract
instructions
- Targeted multiply instruction
- Zero/One detect instructions
- WAIT instruction
- Conditional move instructions (MOVN, MOVZ)
- Vectored interrupts
- Programmable exception vector base
FIGURE 3-1:
•
•
- Atomic interrupt enable/disable
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions
MIPS16e® code compression
- 16-bit encoding of 32-bit instructions to
improve code density
- Special PC-relative instructions for efficient
loading of addresses and constants
- SAVE and RESTORE macro instructions for
setting up and tearing down stack frames
within subroutines
- Improved support for handling 8 and 16-bit
data types
Simple Fixed Mapping Translation (FMT)
mechanism
Simple dual bus interface
- Independent 32-bit address and data busses
- Transactions can be aborted to improve
interrupt latency
Autonomous multiply/divide unit
- Maximum issue rate of one 32x16 multiply
per clock
- Maximum issue rate of one 32x32 multiply
every other clock
- Early-in iterative divide. Minimum 11 and
maximum 33 clock latency (dividend (rs) sign
extension-dependent)
Power control
- Minimum frequency: 0 MHz
- Low-Power mode (triggered by WAIT
instruction)
- Extensive use of local gated clocks
EJTAG debug and instruction trace
- Support for single stepping
- Virtual instruction and data address/value
- Breakpoints
- PC tracing with trace compression
MIPS® M4K® PROCESSOR CORE BLOCK DIAGRAM
CPU
EJTAG
MDU
Execution
Core
(RF/ALU/Shift)
System
Coprocessor
© 2009-2011 Microchip Technology Inc.
Trace
TAP
FMT
Bus Interface
Trace I/F
Off-Chip
Debug I/F
Dual Bus I/F
Bus Matrix
3.0
Power
Management
DS61156G-page 49
PIC32MX5XX/6XX/7XX
3.2
Architecture Overview
The MIPS® M4K® processor core contains several
logic blocks working together in parallel, providing an
efficient high-performance computing engine. The
following blocks are included with the core:
•
•
•
•
•
•
•
•
Execution Unit
Multiply/Divide Unit (MDU)
System Control Coprocessor (CP0)
Fixed Mapping Translation (FMT)
Dual Internal Bus interfaces
Power Management
MIPS16e Support
Enhanced JTAG (EJTAG) Controller
3.2.1
EXECUTION UNIT
The MIPS M4K processor core execution unit implements a load/store architecture with single-cycle ALU
operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two
32-bit General Purpose Registers (GPRs) used for
integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead
during interrupt/exception processing. The register file
consists of two read ports and one write port and is fully
bypassed to minimize operation latency in the pipeline.
The execution unit includes:
• 32-bit adder used for calculating the data address
• Address unit for calculating the next instruction
address
• Logic for branch determination and branch target
address calculation
• Load aligner
• Bypass multiplexers used to avoid stalls when
executing instruction streams where data
producing instructions are followed closely by
consumers of their results
• Leading Zero/One detect unit for implementing
the CLZ and CLO instructions
• Arithmetic Logic Unit (ALU) for performing bitwise
logical operations
• Shifter and store aligner
DS61156G-page 50
3.2.2
MULTIPLY/DIVIDE UNIT (MDU)
MIPS M4K processor core includes a Multiply/Divide
Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall
when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or
other integer unit instructions.
The high-performance MDU consists of a 32x16 booth
recoded multiplier, result/accumulation registers (HI
and LO), a divide state machine, and the necessary
multiplexers and control logic. The first number shown
(‘32’ of 32x16) represents the rs operand. The second
number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt)
operand to determine how many times the operation
must pass through the multiplier. The 16x16 and 32x16
operations pass through the multiplier once. A 32x32
operation passes through the multiplier twice.
The MDU supports execution of one 16x16 or 32x16
multiply operation every clock cycle; 32x32 multiply
operations can be issued every other clock cycle.
Appropriate interlocks are implemented to stall the
issuance of back-to-back 32x32 multiply operations.
The multiply operand size is automatically determined
by logic built into the MDU.
Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
checks the sign extension of the dividend (rs) operand.
If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit
wide rs, 15 iterations are skipped and for a 24 bit wide rs,
7 iterations are skipped. Any attempt to issue a
subsequent MDU instruction while a divide is still active
causes an IU pipeline stall until the divide operation is
completed.
Table 3-1 lists the repeat rate (peak issue rate of cycles
until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32
core multiply and divide instructions. The approximate
latency and repeat rates are listed in terms of pipeline
clocks.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 3-1:
MIPS® M4K® CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT
LATENCIES AND REPEAT RATES
Opcode
Operand Size (mul rt) (div rs)
Latency
Repeat Rate
MULT/MULTU, MADD/MADDU,
MSUB/MSUBU
16 bits
1
1
32 bits
2
2
MUL
16 bits
2
1
DIV/DIVU
32 bits
3
2
8 bits
12
11
16 bits
19
18
24 bits
26
25
32 bits
33
32
The MIPS architecture defines that the result of a
multiply or divide operation be placed in the HI and LO
registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be
transferred to the General Purpose Register file.
In addition to the HI/LO targeted operations, the
MIPS32 architecture also defines a multiply instruction,
MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By
avoiding the explicit MFLO instruction required when
using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive
operations is increased.
3.2.3
SYSTEM CONTROL
COPROCESSOR (CP0)
In the MIPS architecture, CP0 is responsible for the
virtual-to-physical address translation, the exception
control system, the processor’s diagnostics capability,
the operating modes (Kernel, User and Debug) and
whether interrupts are enabled or disabled. Configuration information, such as presence of options like
MIPS16e, is also available by accessing the CP0
registers, listed in Table 3-2.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 51
PIC32MX5XX/6XX/7XX
TABLE 3-2:
Register
Number
0-6
COPROCESSOR 0 REGISTERS
Register
Name
Reserved
Function
Reserved.
7
HWREna
Enables access via the RDHWR instruction to selected hardware registers.
8
BadVAddr(1)
Reports the address for the most recent address-related exception.
9
Count(1)
Processor cycle count.
10
Reserved
(1)
Reserved.
11
Compare
12
Status(1)
Timer interrupt control.
Processor status and control.
12
IntCtl(1)
Interrupt system status and control.
12
SRSCtl(1)
Shadow register set status and control.
12
SRSMap(1)
Provides mapping from vectored interrupt to a shadow set.
13
Cause(1)
Cause of last general exception.
14
EPC(1)
Program counter at last exception.
15
PRId
Processor identification and revision.
15
EBASE
Exception vector base register.
16
Config
Configuration register.
16
Config1
Configuration Register 1.
16
Config2
Configuration Register 2.
Config3
Configuration Register 3.
17-22
16
Reserved
Reserved.
23
Debug(2)
Debug control and exception status.
24
DEPC(2)
Program counter at last debug exception.
25-29
Reserved
Reserved.
30
ErrorEPC(1)
Program counter at last error.
31
DESAVE(2)
Debug handler scratchpad register.
Note 1:
2:
Registers used in exception processing.
Registers used during debug.
DS61156G-page 52
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.
TABLE 3-3:
PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES
Exception
Reset
Description
Assertion MCLR or a Power-on Reset (POR).
DSS
EJTAG debug single step.
DINT
EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI
Assertion of NMI signal.
Interrupt
Assertion of unmasked hardware or software interrupt signal.
DIB
EJTAG debug hardware instruction break matched.
AdEL
Fetch address alignment error.
Fetch reference to protected address.
IBE
Instruction fetch bus error.
DBp
EJTAG breakpoint (execution of SDBBP instruction).
Sys
Execution of SYSCALL instruction.
Bp
Execution of BREAK instruction.
RI
Execution of a reserved instruction.
CpU
Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU
Execution of a CorExtend instruction when CorExtend is not enabled.
Ov
Execution of an arithmetic instruction that overflowed.
Tr
Execution of a trap (when trap condition is true).
DDBL/DDBS
EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL
Load address alignment error.
Load reference to protected address.
AdES
Store address alignment error.
Store to protected address.
DBE
Load or store bus error.
DDBL
EJTAG data hardware breakpoint matched in load data compare.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 53
PIC32MX5XX/6XX/7XX
3.3
Power Management
The MIPS M4K Processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or Halting the clocks, which reduces
system power consumption during Idle periods.
3.3.1
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see Section 27.0
“Power-Saving Features”.
3.3.2
LOCAL CLOCK GATING
The majority of the power consumed by the
PIC32MX5XX/6XX/7XX family core is in the clock tree
and clocking registers. The PIC32 family uses extensive use of local gated clocks to reduce this dynamic
power consumption.
DS61156G-page 54
3.4
EJTAG Debug Support
The MIPS M4K Processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition
to standard User mode and Kernel modes of operation,
the MIPS M4K core provides a Debug mode that is
entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken
and continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for transferring test data in and out of the MIPS M4K processor
core. In addition to the standard JTAG instructions,
special instructions defined in the EJTAG specification
define which registers are selected and how they are
used.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
4.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. For
detailed information, refer to Section 3.
“Memory Organization” (DS61115) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB
of unified virtual memory address space. All memory
regions, including program, data memory, SFRs and
Configuration registers, reside in this address space at
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel
(KSEG0/KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions
© 2009-2011 Microchip Technology Inc.
4.1
PIC32MX5XX/6XX/7XX Memory
Layout
PIC32MX5XX/6XX/7XX microcontrollers implement
two address schemes: virtual and physical. All
hardware resources, such as program memory, data
memory and peripherals, are located at their respective
physical addresses. Virtual addresses are exclusively
used by the CPU to fetch and execute instructions as
well as access peripherals. Physical addresses are
used by bus master peripherals, such as DMA and the
Flash controller, that access memory independently of
the CPU.
The memory maps for the PIC32MX5XX/6XX/7XX
devices are illustrated in Figure 4-1 through Figure 4-6.
4.1.1
PERIPHERAL REGISTERS
LOCATIONS
Table 4-1 through Table 4-44 contain the peripheral
address maps for the PIC32MX5XX/6XX/7XX
devices. Peripherals located on the PB bus are
mapped to 512-byte boundaries. Peripherals on the
FPB bus are mapped to 4-Kbyte boundaries.
DS61156G-page 55
PIC32MX5XX/6XX/7XX
FIGURE 4-1:
MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L,
PIC32MX664F064H AND PIC32MX664F064L DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD010000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD00FFFF
Program Flash(2)
0xBD000000
0xA0008000
Reserved
0xA0007FFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D010000
0x9D00FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D010000
Reserved
0x1D00FFFF
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS61156G-page 56
Reserved
Reserved
RAM(2)
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-2:
MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L
DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD010000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD00FFFF
Program Flash(2)
0xBD000000
0xA0004000
Reserved
0xA0003FFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D010000
0x9D00FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80004000
0x1D010000
Reserved
0x1D00FFFF
Program Flash(2)
0x1D000000
0x80003FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM
(2)
0x00004000
0x00003FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
© 2009-2011 Microchip Technology Inc.
DS61156G-page 57
PIC32MX5XX/6XX/7XX
FIGURE 4-3:
MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L,
PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND
PIC32MX764F128L DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD020000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD01FFFF
Program Flash(2)
0xBD000000
0xA0008000
Reserved
0xA0007FFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D020000
0x9D01FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D020000
Reserved
0x1D01FFFF
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS61156G-page 58
Reserved
Reserved
RAM(2)
0x00008000
0x00007FFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-4:
MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,
PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND
PIC32MX775F256L DEVICES(1)
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD040000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD03FFFF
Program Flash(2)
0xBD000000
0xA0010000
Reserved
0xA000FFFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D040000
0x9D03FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80008000
0x1D040000
Reserved
0x1D03FFFF
Program Flash(2)
0x1D000000
0x80007FFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM
(2)
0x00010000
0x0000FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
© 2009-2011 Microchip Technology Inc.
DS61156G-page 59
PIC32MX5XX/6XX/7XX
FIGURE 4-5:
MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,
PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND
PIC32MX775F512L DEVICES
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD080000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD07FFFF
Program Flash(2)
0xBD000000
0xA0010000
Reserved
0xA000FFFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D080000
0x9D07FFFF
Program Flash(2)
KSEG0
0x1F8FFFFF
Reserved
SFRs
0x1F800000
Reserved
0x9D000000
0x80010000
0x1D080000
Reserved
0x1D07FFFF
Program Flash(2)
0x1D000000
0x8000FFFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
DS61156G-page 60
Reserved
Reserved
RAM
(2)
0x00010000
0x0000FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 4-6:
MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,
PIC32MX795F512H AND PIC32MX795F512L DEVICES
Virtual
Memory Map
0xFFFFFFFF
0xBFC03000
0xBFC02FFF
0xBFC02FF0
Physical
Memory Map
0xFFFFFFFF
Reserved
Device
Configuration
Registers
0xBFC02FEF
Boot Flash
0xBFC00000
0xBF900000
Reserved
SFRs
0xBF800000
0xBD080000
Reserved
KSEG1
0xBF8FFFFF
Reserved
0xBD07FFFF
Program Flash(2)
0xBD000000
0xA0020000
Reserved
0xA001FFFF
RAM(2)
0xA0000000
0x9FC03000
0x9FC02FFF
0x9FC02FF0
0x1FC03000
Device
Configuration
Registers
Reserved
Device
Configuration
Registers
0x1FC02FFF
0x1FC02FF0
0x1FC02FEF
Boot Flash
0x9FC02FEF
0x1FC00000
Boot Flash
Reserved
0x9FC00000
0x1F900000
0x9D080000
0x9D07FFFF
KSEG0
0x1F8FFFFF
Reserved
Program Flash(2)
SFRs
0x1F800000
Reserved
0x9D000000
0x80020000
0x1D080000
Reserved
0x1D07FFFF
Program Flash(2)
0x1D000000
0x8001FFFF
RAM(2)
0x80000000
0x00000000
Note 1:
2:
Reserved
Reserved
RAM(2)
0x00020000
0x0001FFFF
0x00000000
Memory areas are not shown to scale.
The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS61115)) and can be changed by initialization code provided by end user development
tools (refer to the specific development tool documentation for information).
© 2009-2011 Microchip Technology Inc.
DS61156G-page 61
Bits
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
31:16
—
—
—
—
—
BMXCHEDMA
—
—
15:0
—
—
—
—
—
—
—
—
31:16
2010 BMXDKPBA(1)
15:0
—
—
—
—
—
—
—
—
31:16
2020 BMXDUDBA(1)
15:0
—
—
—
—
—
—
—
—
31:16
2030 BMXDUPBA(1)
15:0
—
—
—
—
—
—
—
—
2040 BMXDRMSZ
2060
BMXPFMSZ
2070 BMXBOOTSZ
15:0
31:16
15:0
21/5
19/3
18/2
17/1
16/0
—
—
—
—
BMXWSDRM
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
—
—
—
—
—
—
0000
BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F
BMXARB<2:0>
0041
—
—
0000
BMXDUDBA<15:0>
—
—
0000
BMXDUPBA<15:0>
0000
xxxx
BMXDRMSZ<31:0>
15:0
31:16
22/6
BMXDKPBA<15:0>
31:16
31:16
2050 BMXPUPBA(1)
15:0
20/4
—
—
—
—
—
—
—
—
All
Resets
Register
Name
BMXCON(1)
Bit Range
Virtual Address
(BF88_#)
2000
BUS MATRIX REGISTER MAP
—
—
BMXPUPBA<15:0>
BMXPFMSZ<31:0>
BMXBOOTSZ<31:0>
xxxx
—
—
BMXPUPBA<19:16>
0000
0000
xxxx
xxxx
0000
3000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX5XX/6XX/7XX
DS61156G-page 62
TABLE 4-1:
© 2009-2011 Microchip Technology Inc.
INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES(1)
INTCON
1010 INTSTAT(3)
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
DS61156G-page 63
10A0
IPC1
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
INT4EP
—
—
—
—
—
—
TPC<2:0>
—
—
—
SRIPL<2:0>
31:16
31:16 I2C1MIF
17/1
16/0
—
—
—
SS0
INT3EP INT2EP INT1EP INT0EP
—
—
—
—
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
—
—
0000
—
OC5IF
IC5IF
T5IF
INT4IF
OC4IF
IC4IF
T4IF
0000
INT1IF
OC1IF
IC1IF
T1IF
INT0IF
CS1IF
CS0IF
CTIF
0000
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
IC2EIF
IC1EIF
—
—
CAN1IF
USBIF
FCEIF
U2TXIF
U2RXIF
U2EIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4BIF
FSCMIF
—
—
—
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF
U3TXIF
U3RXIF
I2C4SIF
CMP2IF
CMP1IF
PMPIF
AD1IF
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
U1TXIE
U1RXIE
U1EIE
SPI3TXIE
SPI3RXIE
SPI3EIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
I2C3MIE
I2C3SIE
I2C3BIE
INT1IE
OC1IE
IC1IE
T1IE
INT0IE
CS1IE
I2C1BIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
—
—
CAN1IE
USBIE
FCEIE
U2TXIE
U2RXIE
U2EIE
SPI4TXIE
SPI4RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5SIE
I2C5BIE
I2C4MIE
I2C4BIE
RTCCIE
FSCMIE
—
—
—
U3RXIE
I2C4SIE
CMP2IE
CMP1IE
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
31:16
—
—
—
—
—
—
INT0IS<1:0>
0000
—
0000
IC4EIF
0000
IC4IE
T4IE
0000
CS0IE
CTIE
0000
PMPEIF IC5EIF
0000
U3EIE
31:16
INT0IP<2:0>
CNIF
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE
U3TXIE
0000
U3EIF
—
31:16 I2C1MIE I2C1SIE
0000
0000
IC3EIF
RTCCIF
0000
0000
0000
15:0
15:0
18/2
VEC<5:0>
31:16
31:16
15:0
19/3
IPTMR<31:0>
15:0
15:0
20/4
CS1IP<2:0>
PMPIE
AD1IE
—
—
PMPEIE IC5EIE
CNIE
0000
—
0000
IC4EIE
0000
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
These bits are not available on PIC32MX534/564/664/764 devices.
This register does not have associated CLR, SET, and INV registers.
1:
2:
3:
PIC32MX5XX/6XX/7XX
1060
31/15
All
Resets
1000
Bit Range
Register
Name
Bits
Virtual Address
(BF88_#)
© 2009-2011 Microchip Technology Inc.
TABLE 4-2:
INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES(1) (CONTINUED)
IPC2
10C0
IPC3
10D0
IPC4
10E0
IPC5
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
© 2009-2011 Microchip Technology Inc.
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
23/7
22/6
21/5
31:16
—
—
—
INT2IP<2:0>
15:0
—
—
—
IC2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
15:0
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
31:16
—
—
0000
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
15:0
—
0000
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
31:16
0000
—
—
—
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1IP<2:0>
U1IS<1:0>
SPI3IP<2:0>
SPI3IS<1:0>
I2C3IP<2:0>
I2C3IS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
15:0
31:16
—
—
—
—
28/12
—
—
27/11
—
26/10
—
I2C1IP<2:0>
—
25/9
—
24/8
—
I2C1IS<1:0>
U3IP<2:0>
U3IS<1:0>
SPI2IP<2:0>
SPI2IS<1:0>
I2C4IP<2:0>
I2C4IS<1:0>
—
—
20/4
—
—
—
—
19/3
18/2
17/1
16/0
All
Resets
Register
Name
10B0
Bit Range
Virtual Address
(BF88_#)
Bits
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U2IP<2:0>
U2IS<1:0>
SPI4IP<2:0>
SPI4IS<1:0>
I2C5IP<2:0>
I2C5IS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>(2)
DMA7IS<1:0>(2)
—
—
—
DMA6IP<2:0>(2)
DMA6IS<1:0>(2)
0000
DMA5IS<1:0>(2)
—
—
—
DMA4IP<2:0>(2)
DMA4IS<1:0>(2)
0000
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
0000
DMA5IP<2:0>(2)
0000
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
31:16
—
—
—
U5IP<2:0>
U5IS<1:0>
—
—
—
U6IP<2:0>
U6IS<1:0>
0000
15:0
—
—
—
U4IP<2:0>
U4IS<1:0>
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
These bits are not available on PIC32MX534/564/664/764 devices.
This register does not have associated CLR, SET, and INV registers.
1:
2:
3:
PIC32MX5XX/6XX/7XX
DS61156G-page 64
TABLE 4-2:
Virtual Address
(BF88_#)
Register
Name
1000
INTCON
1010
INTSTAT(3)
INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1)
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
10A0
IPC1
10B0
IPC2
DS61156G-page 65
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC<2:0>
—
—
SRIPL<2:0>
31:16
18/2
17/1
16/0
VEC<5:0>
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
—
—
0000
0000
—
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
IC3EIF
IC2EIF
IC1EIF
ETHIF
—
—
USBIF
FCEIF
U2TXIF
U2RXIF
U2EIF
U3TXIF
U3RXIF
U3EIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
RTCCIF
FSCMIF
31:16
—
—
15:0
—
—
31:16 I2C1MIE
I2C1SIE
—
—
I2C1BIE
—
—
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
0000
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3SIE
I2C3BIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
—
—
USBIE
FCEIE
U2TXIE
U2RXIE
15:0
RTCCIE
FSCMIE
—
—
—
U2EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U3TXIE
U3RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
U3EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
0000
31:16
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does not have associated CLR, SET, and INV registers.
1:
2:
3:
0000
0000
31:16
15:0
19/3
IPTMR<31:0>
15:0
31:16
—
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-3:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
10E0
IPC5
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
Legend:
31/15
30/14
29/13
31:16
—
—
—
INT4IP<2:0>
15:0
—
—
—
IC4IP<2:0>
31:16
—
—
—
15:0
—
—
—
IC5IP<2:0>
31:16
—
—
—
AD1IP<2:0>
15:0
31:16
—
—
—
—
28/12
—
—
27/11
—
26/10
—
I2C1IP<2:0>
—
25/9
23/7
22/6
21/5
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1IP<2:0>
U1IS<1:0>
SPI3IP<2:0>
SPI3IS<1:0>
I2C3IP<2:0>
I2C3IS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
—
24/8
—
I2C1IS<1:0>
U3IP<2:0>
U3IS<1:0>
SPI2IP<2:0>
SPI2IS<1:0>
I2C4IP<2:0>
I2C4IS<1:0>
—
—
20/4
—
—
—
—
19/3
18/2
17/1
16/0
© 2009-2011 Microchip Technology Inc.
2:
3:
0000
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
31:16
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U2IP<2:0>
U2IS<1:0>
SPI4IP<2:0>
SPI4IS<1:0>
I2C5IP<2:0>
I2C5IS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>(2)
DMA7IS<1:0>(2)
—
—
—
DMA6IP<2:0>(2)
DMA6IS<1:0>(2)
0000
DMA5IS<1:0>(2)
—
—
—
—
—
—
15:0
—
—
—
31:16
—
—
—
DMA5IP<2:0>(2)
—
—
—
—
—
DMA4IP<2:0>(2)
—
—
DMA4IS<1:0>(2)
—
—
—
0000
0000
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U5IP<2:0>
U5IS<1:0>
—
—
—
U6IP<2:0>
U6IS<1:0>
0000
15:0
—
—
—
U4IP<2:0>
U4IS<1:0>
—
—
—
ETHIP<2:0>
ETHIS<1:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
1:
All Resets
Bit Range
Bits
10F0
Note
INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
PIC32MX695F512H DEVICES(1) (CONTINUED)
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does not have associated CLR, SET, and INV registers.
PIC32MX5XX/6XX/7XX
DS61156G-page 66
TABLE 4-3:
Virtual Address
(BF88_#)
Register
Name
1000
INTCON
INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1)
1010 INTSTAT(3)
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
10A0
IPC1
DS61156G-page 67
10B0
IPC2
IPC3
10C0
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
0000
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC<2:0>
—
—
31:16
18/2
17/1
16/0
VEC<5:0>
0000
0000
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
—
—
0000
—
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
CAN2IF(2)
CAN1IF
USBIF
FCEIF
U2TXIF
U2RXIF
U2EIF
U3TXIF
U3RXIF
U3EIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
15:0
19/3
IPTMR<31:0>
15:0
31:16
—
SRIPL<2:0>
20/4
RTCCIF
FSCMIF
—
—
—
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
0000
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
—
—
—
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
U1EIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3BIE
I2C3SIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
CAN2IE(2)
CAN1IE
USBIE
FCEIE
U2TXIE
U2RXIE
15:0
RTCCIE
FSCMIE
—
—
—
U2EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U3TXIE
U3RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
U3EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
0000
31:16
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128H device.
This register does not have associated CLR, SET, and INV registers.
1:
2:
3:
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-4:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
10E0
IPC5
INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
PIC32MX795F512H DEVICES(1) (CONTINUED)
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
15:0
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
31:16
—
—
—
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1IP<2:0>
U1IS<1:0>
SPI3IP<2:0>
SPI3IS<1:0>
I2C3IP<2:0>
I2C3IS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
15:0
31:16
—
—
—
—
—
—
—
—
I2C1IP<2:0>
—
—
—
I2C1IS<1:0>
U3IP<2:0>
U3IS<1:0>
SPI2IP<2:0>
SPI2IS<1:0>
I2C4IP<2:0>
I2C4IS<1:0>
—
—
—
—
—
—
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U2IP<2:0>
U2IS<1:0>
SPI4IP<2:0>
SPI4IS<1:0>
I2C5IP<2:0>
I2C5IS<1:0>
15:0
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>(2)
DMA7IS<1:0>(2)
—
—
—
DMA6IP<2:0>(2)
DMA6IS<1:0>(2)
0000
15:0
—
—
—
DMA5IP<2:0>(2)
DMA5IS<1:0>(2)
—
—
—
DMA4IP<2:0>(2)
DMA4IS<1:0>(2)
0000
31:16
—
—
—
CAN2IP<2:0>(2)
CAN2IS<1:0>(2)
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U5IP<2:0>
U5IS<1:0>
—
—
—
U6IP<2:0>
U6IS<1:0>
0000
15:0
—
—
—
U4IP<2:0>
U4IS<1:0>
—
—
—
ETHIP<2:0>
ETHIS<1:0>
0000
© 2009-2011 Microchip Technology Inc.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128H device.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS61156G-page 68
TABLE 4-4:
Virtual Address
(BF88_#)
Register
Name
1000
INTCON
1010
INTSTAT(3)
INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND
PIC32MX575F256L DEVICES(1)
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
10A0
IPC1
DS61156G-page 69
10B0
IPC2
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC<2:0>
—
—
—
SRIPL<2:0>
31:16
18/2
17/1
16/0
VEC<5:0>
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
SPI1TXIF
SPI1RXIF
0000
0000
SPI1EIF
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
IC3EIF
IC2EIF
IC1EIF
—
—
CAN1IF
USBIF
FCEIF
U2TXIF
U2RXIF
U2EIF
U3TXIF
U3RXIF
U3EIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
0000
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3SIE
I2C3BIE
SPI1TXIE SPI1RXIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
—
—
CAN1IE
USBIE
FCEIE
U2TXIE
U2RXIE
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
U2EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U3TXIE
U3RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
U3EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS<1:0>
—
—
—
INT0IP<2:0>
CS1IP<2:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX534/564 devices.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
CS1IS<1:0>
Legend:
1:
0000
0000
31:16
15:0
19/3
IPTMR<31:0>
15:0
31:16
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-5:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND
PIC32MX575F256L DEVICES(1) (CONTINUED)
10E0
IPC5
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
31:16
—
—
—
INT4IP<2:0>
15:0
—
—
—
IC4IP<2:0>
31:16
—
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
—
—
28/12
23/7
22/6
21/5
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
SPI1IP<2:0>
SPI1IS<1:0>
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1IP<2:0>
U1IS<1:0>
SPI3IP<2:0>
SPI3IS<1:0>
I2C3IP<2:0>
I2C3IS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
—
27/11
26/10
I2C1IP<2:0>
—
25/9
24/8
I2C1IS<1:0>
U3IP<2:0>
U3IS<1:0>
SPI2IP<2:0>
SPI2IS<1:0>
I2C4IP<2:0>
I2C4IS<1:0>
—
—
20/4
—
—
—
—
19/3
18/2
17/1
16/0
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U2IP<2:0>
U2IS<1:0>
SPI4IP<2:0>
SPI4IS<1:0>
I2C5IP<2:0>
I2C5IS<1:0>
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>(2)
DMA7IS<1:0>(2)
—
—
—
DMA6IP<2:0>(2)
DMA6IS<1:0>(2)
0000
DMA5IS<1:0>(2)
—
—
—
DMA4IP<2:0>(2)
DMA4IS<1:0>(2)
0000
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
0000
DMA5IP<2:0>(2)
15:0
—
—
—
31:16
—
—
—
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
31:16
—
—
—
U5IP<2:0>
U5IS<1:0>
—
—
—
U6IP<2:0>
U6IS<1:0>
15:0
—
—
—
U4IP<2:0>
U4IS<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
© 2009-2011 Microchip Technology Inc.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX534/564 devices.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 70
TABLE 4-5:
Virtual Address
(BF88_#)
Register
Name
1000
INTCON
1010
INTSTAT(3)
INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES(1)
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
10A0
IPC1
DS61156G-page 71
10B0
IPC2
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC<2:0>
—
—
SRIPL<2:0>
31:16
19/3
18/2
17/1
16/0
VEC<5:0>
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
SPI1TXIF
SPI1RXIF
0000
0000
SPI1EIF
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
31:16
IC3EIF
IC2EIF
IC1EIF
ETHIF
—
—
USBIF
FCEIF
U2TXIF
U2RXIF
U2EIF
U3TXIF
U3RXIF
U3EIF
15:0
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
U1EIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3SIE
I2C3BIE
SPI1TXIE SPI1RXIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
—
—
USBIE
FCEIE
U2TXIE
U2RXIE
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
U2EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U3TXIE
U3RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
U3EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
0000
31:16
—
—
—
INT0IP<2:0>
INT0IS<1:0>
—
—
—
CS1IP<2:0>
CS1IS<1:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does note have associated CLR, SET, and INV registers.
2:
3:
0000
DMA3IF
Legend:
1:
0000
0000
IPTMR<31:0>
15:0
31:16
—
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-6:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
10E0
IPC5
INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
PIC32MX695F512L DEVICES(1) (CONTINUED)
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
INT4IP<2:0>
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
15:0
—
—
—
IC4IP<2:0>
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
31:16
—
—
—
SPI1IP<2:0>
SPI1IS<1:0>
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
15:0
—
—
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
31:16
—
—
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1IP<2:0>
U1IS<1:0>
SPI3IP<2:0>
SPI3IS<1:0>
I2C3IP<2:0>
I2C3IS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
15:0
31:16
—
—
—
—
—
I2C1IP<2:0>
—
I2C1IS<1:0>
U3IP<2:0>
U3IS<1:0>
SPI2IP<2:0>
SPI2IS<1:0>
I2C4IP<2:0>
I2C4IS<1:0>
—
—
—
—
—
—
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U2IP<2:0>
U2IS<1:0>
SPI4IP<2:0>
SPI4IS<1:0>
I2C5IP<2:0>
I2C5IS<1:0>
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>(2)
DMA7IS<1:0>(2)
—
—
—
DMA6IP<2:0>(2)
DMA6IS<1:0>(2)
0000
DMA5IS<1:0>(2)
—
—
—
—
—
—
15:0
—
—
—
31:16
—
—
—
DMA5IP<2:0>(2)
—
—
—
—
—
DMA4IP<2:0>(2)
—
—
DMA4IS<1:0>(2)
—
—
—
0000
0000
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U5IP<2:0>
U5IS<1:0>
—
—
—
U6IP<2:0>
U6IS<1:0>
0000
15:0
—
—
—
U4IP<2:0>
U4IS<1:0>
—
—
—
ETHIP<2:0>
ETHIS<1:0>
0000
© 2009-2011 Microchip Technology Inc.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
These bits are not available on PIC32MX664 devices.
This register does note have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS61156G-page 72
TABLE 4-6:
Virtual Address
(BF88_#)
Register
Name
1000
INTCON
1010
INTSTAT(3)
INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES(1)
1020
IPTMR
1030
IFS0
1040
IFS1
1050
IFS2
IEC0
1070
IEC1
1080
IEC2
1090
IPC0
10A0
IPC1
DS61156G-page 73
10B0
IPC2
10C0
IPC3
30/14
29/13
28/12
27/11
26/10
—
31:16
—
—
—
—
—
15:0
—
FRZ
—
MVEC
—
31:16
—
—
—
—
—
15:0
—
—
—
—
—
25/9
24/8
23/7
22/6
21/5
—
—
—
—
—
—
—
—
—
SS0
—
—
—
INT4EP
INT3EP
INT2EP
INT1EP
INT0EP
0000
—
—
—
—
—
—
—
—
0000
—
—
TPC<2:0>
—
—
SRIPL<2:0>
31:16
18/2
17/1
16/0
VEC<5:0>
I2C1MIF
I2C1SIF
I2C1BIF
U1TXIF
U1RXIF
U1EIF
SPI3TXIF
SPI3RXIF
SPI3EIF
I2C3MIF
I2C3SIF
I2C3BIF
SPI1TXIF
SPI1RXIF
0000
0000
SPI1EIF
OC5IF
IC5IF
T5IF
INT1IF
OC1IF
IC1IF
T1IF
15:0
INT3IF
OC3IF
IC3IF
T3IF
INT2IF
OC2IF
IC2IF
T2IF
IC3EIF
IC2EIF
IC1EIF
ETHIF
CAN2IF(2)
CAN1IF
USBIF
FCEIF
U2TXIF
U2RXIF
U2EIF
U3TXIF
U3RXIF
U3EIF
SPI4TXIF
SPI4RXIF
SPI4EIF
SPI2TXIF
SPI2RXIF
SPI2EIF
I2C5MIF
I2C5SIF
I2C5BIF
I2C4MIF
I2C4SIF
I2C4BIF
RTCCIF
FSCMIF
I2C2MIF
I2C2SIF
I2C2BIF
DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2)
CMP2IF
INT4IF
OC4IF
IC4IF
T4IF
0000
INT0IF
CS1IF
CS0IF
CTIF
0000
DMA3IF
DMA2IF
DMA1IF
DMA0IF
0000
CMP1IF
PMPIF
AD1IF
CNIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
U5TXIF
U5RXIF
U5EIF
U6TXIF
U6RXIF
U6EIF
U4TXIF
U4RXIF
U4EIF
PMPEIF
IC5EIF
IC4EIF
0000
U1TXIE
U1RXIE
U1EIE
SPI1EIE
OC5IE
IC5IE
T5IE
INT4IE
OC4IE
IC4IE
T4IE
0000
INT1IE
OC1IE
IC1IE
T1IE
31:16
I2C1MIE
I2C1SIE
I2C1BIE
SPI3TXIE SPI3RXIE
SPI3EIE
I2C3MIE
I2C3BIE
I2C3SIE
SPI1TXIE SPI1RXIE
15:0
INT3IE
OC3IE
IC3IE
T3IE
INT2IE
OC2IE
IC2IE
T2IE
31:16
IC3EIE
IC2EIE
IC1EIE
ETHIE
CAN2IE(2)
CAN1IE
USBIE
FCEIE
U2TXIE
U2RXIE
15:0
RTCCIE
FSCMIE
I2C2MIE
I2C2SIE
I2C2BIE
U2EIE
DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2)
U3TXIE
U3RXIE
SPI4EIE
SPI2TXIE SPI2RXIE
SPI2EIE
I2C5MIE
I2C5BIE
I2C4MIE
I2C4BIE
I2C4SIE
CS1IE
CS0IE
CTIE
0000
DMA2IE
DMA1IE
DMA0IE
0000
CMP1IE
PMPIE
AD1IE
CNIE
0000
0000
U3EIE
SPI4TXIE SPI4RXIE
I2C5SIE
INT0IE
DMA3IE
CMP2IE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
U5TXIE
U5RXIE
U5EIE
U6TXIE
U6RXIE
U6EIE
U4TXIE
U4RXIE
U4EIE
PMPEIE
IC5EIE
IC4EIE
31:16
—
—
—
INT0IS<1:0>
—
—
—
INT0IP<2:0>
CS1IP<2:0>
0000
15:0
—
—
—
CS0IP<2:0>
CS0IS<1:0>
—
—
—
CTIP<2:0>
CTIS<1:0>
0000
31:16
—
—
—
INT1IP<2:0>
INT1IS<1:0>
—
—
—
OC1IP<2:0>
OC1IS<1:0>
0000
15:0
—
—
—
IC1IP<2:0>
IC1IS<1:0>
—
—
—
T1IP<2:0>
T1IS<1:0>
0000
31:16
—
—
—
INT2IP<2:0>
INT2IS<1:0>
—
—
—
OC2IP<2:0>
OC2IS<1:0>
0000
15:0
—
—
—
IC2IP<2:0>
IC2IS<1:0>
—
—
—
T2IP<2:0>
T2IS<1:0>
0000
31:16
—
—
—
INT3IP<2:0>
INT3IS<1:0>
—
—
—
OC3IP<2:0>
OC3IS<1:0>
0000
15:0
—
—
—
IC3IP<2:0>
IC3IS<1:0>
—
—
—
T3IP<2:0>
T3IS<1:0>
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128L device.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
CS1IS<1:0>
Legend:
1:
0000
0000
31:16
15:0
19/3
IPTMR<31:0>
15:0
31:16
—
20/4
PIC32MX5XX/6XX/7XX
1060
31/15
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-7:
Virtual Address
(BF88_#)
Register
Name
10D0
IPC4
10E0
IPC5
INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
PIC32MX795F512L DEVICES(1) (CONTINUED)
10F0
IPC6
1100
IPC7
1110
IPC8
1120
IPC9
1130
IPC10
1140
IPC11
1150
IPC12
31/15
30/14
29/13
31:16
—
—
—
INT4IP<2:0>
15:0
—
—
—
IC4IP<2:0>
31:16
—
—
—
15:0
—
—
31:16
—
—
15:0
31:16
—
—
—
—
23/7
22/6
21/5
INT4IS<1:0>
—
—
—
OC4IP<2:0>
OC4IS<1:0>
0000
IC4IS<1:0>
—
—
—
T4IP<2:0>
T4IS<1:0>
0000
SPI1IP<2:0>
SPI1IS<1:0>
—
—
—
OC5IP<2:0>
OC5IS<1:0>
0000
—
IC5IP<2:0>
IC5IS<1:0>
—
—
—
T5IP<2:0>
T5IS<1:0>
0000
—
AD1IP<2:0>
AD1IS<1:0>
—
—
—
CNIP<2:0>
CNIS<1:0>
0000
U1IP<2:0>
U1IS<1:0>
SPI3IP<2:0>
SPI3IS<1:0>
I2C3IP<2:0>
I2C3IS<1:0>
CMP2IP<2:0>
CMP2IS<1:0>
0000
—
—
28/12
27/11
I2C1IP<2:0>
26/10
25/9
24/8
I2C1IS<1:0>
U3IP<2:0>
U3IS<1:0>
SPI2IP<2:0>
SPI2IS<1:0>
I2C4IP<2:0>
I2C4IS<1:0>
—
—
—
—
—
—
20/4
19/3
18/2
17/1
16/0
15:0
—
—
—
CMP1IP<2:0>
CMP1IS<1:0>
—
—
—
PMPIP<2:0>
PMPIS<1:0>
0000
—
—
—
RTCCIP<2:0>
RTCCIS<1:0>
—
—
—
FSCMIP<2:0>
FSCMIS<1:0>
0000
U2IP<2:0>
U2IS<1:0>
SPI4IP<2:0>
SPI4IS<1:0>
I2C5IP<2:0>
I2C5IS<1:0>
15:0
—
—
—
I2C2IP<2:0>
I2C2IS<1:0>
—
—
—
0000
31:16
—
—
—
DMA3IP<2:0>
DMA3IS<1:0>
—
—
—
DMA2IP<2:0>
DMA2IS<1:0>
0000
15:0
—
—
—
DMA1IP<2:0>
DMA1IS<1:0>
—
—
—
DMA0IP<2:0>
DMA0IS<1:0>
0000
31:16
—
—
—
DMA7IP<2:0>(2)
DMA7IS<1:0>(2)
—
—
—
DMA6IP<2:0>(2)
DMA6IS<1:0>(2)
0000
15:0
—
—
—
DMA5IP<2:0>(2)
DMA5IS<1:0>(2)
—
—
—
DMA4IP<2:0>(2)
DMA4IS<1:0>(2)
0000
31:16
—
—
—
CAN2IP<2:0>(2)
CAN2IS<1:0>(2)
—
—
—
CAN1IP<2:0>
CAN1IS<1:0>
0000
15:0
—
—
—
USBIP<2:0>
USBIS<1:0>
—
—
—
FCEIP<2:0>
FCEIS<1:0>
0000
31:16
—
—
—
U5IP<2:0>
U5IS<1:0>
—
—
—
U6IP<2:0>
U6IS<1:0>
0000
15:0
—
—
—
U4IP<2:0>
U4IS<1:0>
—
—
—
ETHIP<2:0>
ETHIS<1:0>
0000
© 2009-2011 Microchip Technology Inc.
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
This bit is unimplemented on PIC32MX764F128L device.
This register does not have associated CLR, SET, and INV registers.
2:
3:
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS61156G-page 74
TABLE 4-7:
Virtual Address
(BF80_#)
0600 T1CON
0610
TMR1
0620
TMR2
0820
TMR3
TMR5
PR5
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
FRZ
SIDL
TWDIS
TWIP
—
—
—
TGATE
—
TCKPS<1:0>
—
TSYNC
TCS
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
15:0
TMR1<15:0>
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
T32
—
TCS(2)
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
TCKPS<2:0>
—
0000
PR2<15:0>
15:0
FFFF
—
—
TCS(2)
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
TCKPS<2:0>
TMR3<15:0>
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
—
0000
PR3<15:0>
15:0
FFFF
T32
—
TCS(2)
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
TCKPS<2:0>
TMR4<15:0>
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
TGATE
31:16
—
—
—
—
—
—
—
—
—
—
0000
PR4<15:0>
15:0
15:0
FFFF
TMR2<15:0>
—
31:16
0000
PR1<15:0>
15:0
0E00 T5CON
23/7
—
31:16
PR4
0E20
24/8
FFFF
—
—
TCS(2)
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
TCKPS<2:0>
TMR5<15:0>
—
—
—
—
—
—
—
—
—
0000
PR5<15:0>
DS61156G-page 75
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
These bits are not available on 64-pin devices.
1:
2:
FFFF
PIC32MX5XX/6XX/7XX
TMR4
0E10
25/9
15:0
0C00 T4CON
0C20
26/10
ON
31:16
PR3
0C10
27/11
15:0
0A00 T3CON
0A20
28/12
15:0
31:16
PR2
0A10
29/13
15:0
0800 T2CON
0810
30/14
31:16
31:16
PR1
31/15
All Resets
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TIMER1-TIMER5 REGISTER MAP(1)
TABLE 4-8:
Virtual Address
(BF80_#)
Register
Name
2000
IC1CON(1)
2010
IC1BUF
2200
IC2CON(1)
2210
IC2BUF
2400
IC3CON(1)
2410
IC3BUF
2600
IC4CON(1)
2610
IC4BUF
2800
IC5CON(1)
2810
IC5BUF
INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
15:0
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
18/2
—
—
—
ICOV
ICBNE
17/1
16/0
—
—
ICM<2:0>
15:0
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
0000
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
15:0
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
31:16
0000
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
15:0
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
FEDGE
C32
ICTMR
0000
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
0000
0000
xxxx
xxxx
—
—
ICI<1:0>
—
—
ICOV
ICBNE
—
—
—
ICM<2:0>
IC5BUF<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
xxxx
IC4BUF<31:0>
31:16
0000
xxxx
IC3BUF<31:0>
31:16
0000
xxxx
IC2BUF<31:0>
31:16
15:0
19/3
IC1BUF<31:0>
31:16
31:16
ICI<1:0>
20/4
All Resets
Bit Range
Bits
0000
0000
xxxx
xxxx
PIC32MX5XX/6XX/7XX
DS61156G-page 76
TABLE 4-9:
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF80_#)
3000 OC1CON
3010
OC1R
3020
OC1RS
3200 OC2CON
3210
OC2R
3220
OC2RS
3400 OC3CON
3410
OC3R
3420
OC3RS
3610
OC4R
3620
OC4RS
3800 OC5CON
3810
OC5R
3820
OC5RS
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
31:16
xxxx
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
31:16
xxxx
xxxx
xxxx
OC2RS<31:0>
15:0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
31:16
15:0
xxxx
xxxx
xxxx
OC3RS<31:0>
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
31:16
—
—
—
OCM<2:0>
31:16
15:0
xxxx
xxxx
xxxx
OC4RS<31:0>
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
OC32
OCFLT
OCTSEL
—
—
—
OCM<2:0>
OC5R<31:0>
OC5RS<31:0>
DS61156G-page 77
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
0000
0000
OC4R<31:0>
15:0
0000
0000
OC3R<31:0>
15:0
0000
0000
OC2R<31:0>
15:0
0000
0000
xxxx
—
15:0
—
xxxx
31:16
31:16
—
OCM<2:0>
OC1RS<31:0>
15:0
15:0
16/0
OC1R<31:0>
15:0
31:16
17/1
All Resets
31/15
0000
0000
xxxx
xxxx
xxxx
xxxx
PIC32MX5XX/6XX/7XX
3600 OC4CON
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1)
TABLE 4-10:
Virtual Address
(BF80_#)
Register
Name
5000
I2C3CON
I2C3STAT
5020
I2C5DD
5030
I2C3MSK
5040
I2C3BRG
5050
I2C3TRN
5060
I2C3RCV
5100
I2C4CON
© 2009-2011 Microchip Technology Inc.
5110
I2C4STAT
5120
I2C4ADD
5130
I2C4MSK
5140
I2C4BRG
5150
I2C4TRN
5160
I2C4RCV
5200
I2C5CON
I2C5STAT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Bits
5010
5210
I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP(1)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
Transmit Register
—
0000
0000
Baud Rate Generator Register
—
0000
0000
—
—
0000
0000
—
—
—
Receive Register
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
Transmit Register
—
0000
0000
Baud Rate Generator Register
—
0000
0000
—
—
0000
0000
—
—
—
Receive Register
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
1:
PIC32MX5XX/6XX/7XX
DS61156G-page 78
TABLE 4-11:
Virtual Address
(BF80_#)
Register
Name
5220
I2C5ADD
5230
I2C5MSK
5240
I2C5BRG
5250
I2C5TRN
5260
I2C5RCV
5300
I2C1CON
I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP(1) (CONTINUED)
I2C1STAT
5320
I2C3DD
5330
I2C1MSK
5340
I2C1BRG
5350
I2C1TRN
5360
I2C1RCV
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
Transmit Register
—
0000
0000
Baud Rate Generator Register
—
0000
0000
—
—
0000
0000
—
—
—
Receive Register
0000
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
ADD<9:0>
—
—
—
—
—
—
—
—
—
—
MSK<9:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
Transmit Register
—
0000
0000
Baud Rate Generator Register
—
0000
0000
—
—
Receive Register
0000
0000
—
—
—
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
1:
DS61156G-page 79
PIC32MX5XX/6XX/7XX
5310
31/15
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-11:
Virtual Address
(BF80_#)
5410 I2C2STAT
I2C4DD
5430 I2C2MSK
5440 I2C2BRG
5450 I2C2TRN
5460 I2C2RCV
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
All Resets
Bit Range
Register
Name
Bits
5400 I2C2CON
5420
I2C2 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ON
FRZ
SIDL
SCLREL
STRICT
A10M
DISSLW
SMEN
GCEN
STREN
ACKDT
ACKEN
RCEN
PEN
RSEN
SEN
1000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ACKSTAT
TRSTAT
—
—
—
BCL
GCSTAT
ADD10
IWCOL
I2COV
D/A
P
S
R/W
RBF
TBF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
0000
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
ADD<9:0>
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
MSK<9:0>
15:0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
0000
Baud Rate Generator Register
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
0000
Transmit Register
—
—
Receive Register
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
1:
PIC32MX5XX/6XX/7XX
DS61156G-page 80
TABLE 4-12:
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF80_#)
U1STA(1)
6010
U1TXREG
6030
U1RXREG
6040
U1BRG(1)
6200 U4MODE
U4STA(1)
6210
6220
(1)
U4TXREG
U4RXREG
6240
U4BRG(1)
6400
U3MODE(1)
6410
U3STA(1)
6420
U3TXREG
6430
U3RXREG
6440
(1)
U3BRG
DS61156G-page 81
6600
U6MODE(1)
6610
U6STA(1)
6620
U6TXREG
30/14
29/13
28/12
27/11
26/10
25/9
24/8
—
—
31:16
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
31:16
—
—
15:0
UTXISEL<1:0>
31:16
—
UEN<1:0>
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
23/7
22/6
21/5
20/4
19/3
18/2
17/1
—
—
16/0
—
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
PDSEL<1:0>
—
0000
STSEL
0000
ADDR<7:0>
URXISEL<1:0>
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
STSEL
0000
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
0000
31:16
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
ON
FRZ
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
31:16
—
—
15:0
UTXISEL<1:0>
31:16
—
15:0
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
UEN<1:0>
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
0000
ADDR<7:0>
URXISEL<1:0>
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
STSEL
0000
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
TX8
15:0
PDSEL<1:0>
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
0000
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
—
—
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
—
0000
Transmit Register
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
PIC32MX5XX/6XX/7XX
6230
31/15
All Resets
Bit Range
6000 U1MODE(1)
6020
UART1 THROUGH UART6 REGISTER MAP
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-13:
Virtual Address
(BF80_#)
Register
Name
6630
U6RXREG
6640
U6BRG(1)
UART1 THROUGH UART6 REGISTER MAP (CONTINUED)
6800 U2MODE(1)
6810
U2STA(1)
6820
U2TXREG
6830
U2RXREG
6840
U2BRG(1)
6A00 U5MODE(1)
6A10
U5STA(1)
6A20
U5TXREG
6A30
U5RXREG
6A40
U5BRG(1)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
RTSMD
—
31:16
—
—
15:0
UTXISEL<1:0>
31:16
—
15:0
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
0000
0000
Receive Register
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
WAKE
LPBACK
ABAUD
RXINV
BRGH
STSEL
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
0000
BRG<15:0>
UEN<1:0>
—
—
—
—
—
ADM_EN
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
—
—
—
—
—
—
—
0000
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
STSEL
0000
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
IREN
—
—
—
—
WAKE
LPBACK
ABAUD
RXINV
BRGH
31:16
—
—
—
—
—
—
—
ADM_EN
15:0
UTXISEL<1:0>
UTXINV
URXEN
UTXBRK
UTXEN
UTXBF
TRMT
31:16
—
—
—
—
—
—
—
—
15:0
Transmit Register
—
—
0000
Receive Register
0000
BRG<15:0>
15:0
—
—
—
—
—
—
—
TX8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
RX8
31:16
—
—
—
—
—
—
—
—
15:0
0000
PDSEL<1:0>
ADDR<7:0>
URXISEL<1:0>
0000
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
0110
—
—
—
—
—
0000
—
—
—
0000
—
—
—
0000
—
—
—
—
—
—
—
—
—
Transmit Register
—
—
0000
Receive Register
—
—
0000
BRG<15:0>
© 2009-2011 Microchip Technology Inc.
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
All Resets
Bit Range
Bits
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 82
TABLE 4-13:
Virtual Address
(BF80_#)
5800 SPI3CON
5810 SPI3STAT
5820
SPI3BUF
5830
SPI3BRG
5A00 SPI2CON
5A10 SPI2STAT
5A20
SPI2BUF
5A30 SPI2BRG
5C00 SPI4CON
5C20
SPI4BUF
5C30 SPI4BRG
30/14
29/13
31:16
FRMEN
15:0
ON
FRMSYNC FRMPOL
FRZ
SIDL
31:16
—
—
—
15:0
—
—
—
28/12
27/11
26/10
MSSEN
FRMSYPW
DISSDO
MODE32
25/9
24/8
23/7
—
CKE
SSEN
—
—
—
SRMT
SPIROV
SPIRBE
FRMCNT<2:0>
MODE16
SMP
RXBUFELM<4:0>
—
SPIBUSY
—
—
31:16
SPITUR
22/6
21/5
20/4
19/3
18/2
17/1
—
—
CKP
MSTEN
—
—
—
SPIFE
—
STXISEL<1:0>
16/0
ENHBUF 0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
SPITBE
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
FRMEN
MSSEN
FRMSYPW
15:0
ON
FRZ
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
FRMSYNC FRMPOL
—
SPITBF
SPIRBF
SMP
CKE
RXBUFELM<4:0>
—
SPIBUSY
—
—
31:16
SPITUR
0000
—
—
—
—
—
—
—
—
—
—
—
—
SSEN
CKP
MSTEN
—
STXISEL<1:0>
—
—
—
—
SRMT
SPIROV
SPIRBE
SPIFE
ENHBUF 0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
FRMEN
MSSEN
FRMSYPW
15:0
ON
FRZ
SIDL
DISSDO
MODE32
31:16
—
—
—
15:0
—
—
—
FRMSYNC FRMPOL
—
SPITBE
—
SMP
CKE
RXBUFELM<4:0>
—
SPIBUSY
—
—
31:16
SPITUR
SPITBF
SPIRBF
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
CKP
MSTEN
—
STXISEL<1:0>
—
—
—
—
SRMT
SPIROV
SPIRBE
SPIFE
ENHBUF 0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
0000
0000
SSEN
—
0008
0000
SPITBE
—
0000
0000
SPITBF
SPIRBF
0008
0000
DATA<31:0>
15:0
0000
0000
BRG<8:0>
FRMCNT<2:0>
MODE16
—
0000
0000
DATA<31:0>
15:0
0008
0000
BRG<8:0>
FRMCNT<2:0>
MODE16
—
0000
0000
DATA<31:0>
15:0
All Resets
31/15
0000
—
—
—
BRG<8:0>
—
—
—
—
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
1:
DS61156G-page 83
PIC32MX5XX/6XX/7XX
5C10 SPI4STAT
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
SPI2, SPI3 AND SPI4 REGISTER MAP(1)
TABLE 4-14:
5E10 SPI1STAT
SPI1BUF
5E30 SPI1BRG
31/15
30/14
29/13
31:16
FRMEN
15:0
ON
FRMSYNC FRMPOL
FRZ
SIDL
31:16
—
—
—
15:0
—
—
—
28/12
27/11
26/10
MSSEN
FRMSYPW
DISSDO
MODE32
25/9
24/8
23/7
—
CKE
SSEN
—
—
—
SRMT
SPIROV
SPIRBE
FRMCNT<2:0>
MODE16
SMP
RXBUFELM<4:0>
—
SPIBUSY
—
—
31:16
SPITUR
22/6
21/5
20/4
19/3
18/2
17/1
—
—
CKP
MSTEN
—
—
—
SPIFE
—
STXISEL<1:0>
16/0
ENHBUF 0000
SRXISEL<1:0>
TXBUFELM<4:0>
—
SPITBE
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
SPITBF
SPIRBF
0008
0000
DATA<31:0>
15:0
All Resets
Register
Name
Bit Range
Virtual Address
(BF80_#)
Bits
5E00 SPI1CON
5E20
SPI1 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
0000
—
—
—
BRG<8:0>
—
—
—
—
0000
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
1:
PIC32MX5XX/6XX/7XX
DS61156G-page 84
TABLE 4-15:
© 2009-2011 Microchip Technology Inc.
ADC REGISTER MAP
Register
Name
9000 AD1CON1(1)
9010
AD1CON2(1)
9020
AD1CON3(1)
9040 AD1CHS(1)
9060 AD1PCFG(1)
9050 AD1CSSL
(1)
9070 ADC1BUF0
9080 ADC1BUF1
9090 ADC1BUF2
90B0 ADC1BUF4
90C0 ADC1BUF5
90D0 ADC1BUF6
90E0 ADC1BUF7
90F0 ADC1BUF8
9100 ADC1BUF9
DS61156G-page 85
9110 ADC1BUFA
9120 ADC1BUFB
30/14
29/13
28/12
27/11
26/10
—
25/9
24/8
23/7
—
—
—
22/6
21/5
—
—
31:16
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
31:16
—
—
—
—
—
—
—
—
—
—
FORM<2:0>
15:0
VCFG2
VCFG1
VCFG0
OFFCAL
—
CSCNA
—
—
BUFS
—
—
—
—
—
—
—
—
—
—
—
15:0
ADRC
—
—
31:16
CH0NB
—
—
—
15:0
—
—
—
—
17/1
16/0
—
—
—
—
—
ASAM
SAMP
DONE
0000
—
—
—
—
—
—
0000
BUFM
ALTS
0000
—
—
—
—
SMPI<3:0>
—
—
ADCS<7:0>
CH0SB<3:0>
—
18/2
—
SAMC<4:0>
—
19/3
CLRASAM
SSRC<2:0>
31:16
20/4
—
—
CH0NA
—
—
—
—
—
—
—
—
—
0000
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
PCFG15
PCFG14
PCFG13
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
CSSL15
CSSL14
CSSL13
CSSL12
CSSL11
CSSL10
CSSL9
CSSL8
CSSL7
CSSL6
CSSL5
CSSL4
CSSL3
CSSL2
CSSL1
CSSL0
0000
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
ADC Result Word 0 (ADC1BUF0<31:0>)
ADC Result Word 1 (ADC1BUF1<31:0>)
ADC Result Word 2 (ADC1BUF2<31:0>)
ADC Result Word 3 (ADC1BUF3<31:0>)
ADC Result Word 4 (ADC1BUF4<31:0>)
ADC Result Word 5 (ADC1BUF5<31:0>)
ADC Result Word 6 (ADC1BUF6<31:0>)
ADC Result Word 7 (ADC1BUF7<31:0>)
ADC Result Word 8 (ADC1BUF8<31:0>)
ADC Result Word 9 (ADC1BUF9<31:0>)
ADC Result Word A (ADC1BUFA<31:0>)
ADC Result Word B (ADC1BUFB<31:0>)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
0000
0000
CH0SA<3:0>
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
90A0 ADC1BUF3
31/15
All Resets
Bits
Bit Range
Virtual Address
(BF80_#)
© 2009-2011 Microchip Technology Inc.
TABLE 4-16:
Register
Name
9130 ADC1BUFC
9140 ADC1BUFD
9150 ADC1BUFE
9160 ADC1BUFF
31:16
15:0
31:16
15:0
31:16
15:0
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
ADC Result Word C (ADC1BUFC<31:0>)
ADC Result Word D (ADC1BUFD<31:0>)
ADC Result Word E (ADC1BUFE<31:0>)
ADC Result Word F (ADC1BUFF<31:0>)
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
All Resets
Bits
Bit Range
Virtual Address
(BF80_#)
ADC REGISTER MAP (CONTINUED)
0000
0000
0000
0000
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 86
TABLE 4-16:
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF88_#)
3000 DMACON(1)
DMASTAT
3020 DMAADDR
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
31:16
—
—
—
15:0
ON
FRZ
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
RDWR
SUSPEND DMABUSY
31:16
DMACH<2:0>(2)
0000
DMAADDR<31:0>
15:0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DMACH<3> bit is not available on PIC32MX534/564/664/764 devices.
Virtual Address
(BF88_#)
TABLE 4-18:
0000
0000
Legend:
1:
2:
All Resets
Bit Range
31/15
DMA CRC REGISTER MAP(1)
3040 DCRCDATA
3050 DCRCXOR
31/15
30/14
31:16
—
—
15:0
—
—
31:16
15:0
31:16
15:0
29/13
28/12
BYTO<1:0>
—
27/11
WBO
26/10
25/9
24/8
—
—
BITO
PLEN<4:0>
23/7
22/6
21/5
20/4
19/3
18/2
—
—
—
—
—
—
CRCEN
CRCAPP
CRCTYP
—
—
17/1
16/0
—
—
CRCCH<2:0>
DCRCDATA<31:0>
DCRCXOR<31:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
0000
0000
0000
0000
0000
0000
DS61156G-page 87
PIC32MX5XX/6XX/7XX
3030 DCRCCON
Bit Range
Register
Name
Bits
All Resets
3010
DMA GLOBAL REGISTER MAP
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-17:
Virtual Address
(BF88_#)
3070 DCH0ECON
3080
DCH0INT
3090
DCH0SSA
30A0 DCH0DSA
30B0 DCH0SSIZ
30C0 DCH0DSIZ
30D0 DCH0SPTR
30E0 DCH0DPTR
30F0 DCH0CSIZ
3100 DCH0CPTR
DCH0DAT
3120 DCH1CON
© 2009-2011 Microchip Technology Inc.
3130 DCH1ECON
3140
DCH1INT
3150
DCH1SSA
3160 DCH1DSA
3170 DCH1SSIZ
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
15:0
CHSIRQ<7:0>
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
18/2
17/1
16/0
—
—
CHCHN
CHAEN
—
—
—
—
—
CHEDET
CHPRI<1:0>
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ<7:0>
15:0
31:16
31:16
CHPRI<1:0>
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
—
0000
0000
00FF
FF00
0000
0000
0000
CHDSA<31:0>
15:0
15:0
0000
CHSSA<31:0>
15:0
31:16
CHPDAT<7:0>
0000
—
—
—
—
—
—
—
CHSSIZ<15:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
2:
0000
0000
Legend:
1:
FF00
0000
CHCPTR<15:0>
31:16
0000
0000
CHCSIZ<15:0>
—
0000
00FF
CHDPTR<15:0>
15:0
31:16
19/3
CHSPTR<15:0>
15:0
31:16
20/4
CHDSIZ<15:0>
15:0
31:16
21/5
CHSSIZ<15:0>
15:0
31:16
22/6
CHDSA<31:0>
15:0
31:16
23/7
CHSSA<31:0>
15:0
31:16
24/8
All Resets
Bit Range
Register
Name
Bits
3060 DCH0CON
3110
DMA CHANNELS 0-7 REGISTER MAP(1,2)
0000
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 88
TABLE 4-19:
Virtual Address
(BF88_#)
DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED)
3180 DCH1DSIZ
3190 DCH1SPTR
31A0 DCH1DPTR
31B0 DCH1CSIZ
31C0 DCH1CPTR
31D0 DCH1DAT
31E0 DCH2CON
31F0 DCH2ECON
DCH2INT
3210
DCH2SSA
3220 DCH2DSA
3230 DCH2SSIZ
3240 DCH2DSIZ
3250 DCH2SPTR
3260 DCH2DPTR
3270 DCH2CSIZ
DS61156G-page 89
3280 DCH2CPTR
31:16
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
0000
0000
CHCPTR<15:0>
31:16
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ<7:0>
15:0
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
CHCPTR<15:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
2:
0000
0000
CHCSIZ<15:0>
—
FF00
0000
CHDPTR<15:0>
15:0
31:16
—
0000
0000
CHSPTR<15:0>
15:0
31:16
—
0000
00FF
CHDSIZ<15:0>
15:0
31:16
CHAIRQ<7:0>
CHSSIZ<15:0>
15:0
31:16
CHPRI<1:0>
CHDSA<31:0>
15:0
31:16
0000
CHSSA<31:0>
15:0
31:16
CHPDAT<7:0>
Legend:
1:
0000
0000
CHCSIZ<15:0>
—
0000
0000
CHDPTR<15:0>
15:0
31:16
23/7
CHSPTR<15:0>
15:0
31:16
24/8
CHDSIZ<15:0>
—
All Resets
31/15
0000
0000
PIC32MX5XX/6XX/7XX
3200
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-19:
Virtual Address
(BF88_#)
Register
Name
3290
DCH2DAT
32B0 DCH3ECON
DCH3INT
32D0 DCH3SSA
32E0 DCH3DSA
32F0 DCH3SSIZ
3300 DCH3DSIZ
3310 DCH3SPTR
3320 DCH3DPTR
3330 DCH3CSIZ
3340 DCH3CPTR
3350
DCH3DAT
© 2009-2011 Microchip Technology Inc.
3360 DCH4CON
3370 DCH4ECON
3380
DCH4INT
3390
DCH4SSA
33A0 DCH4DSA
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ<7:0>
15:0
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPRI<1:0>
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ<7:0>
15:0
31:16
15:0
31:16
15:0
CHPDAT<7:0>
0000
CHPRI<1:0>
CHAIRQ<7:0>
0000
0000
00FF
CHSSA<31:0>
CHDSA<31:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
2:
FF00
0000
Legend:
1:
0000
0000
CHCPTR<15:0>
31:16
0000
00FF
CHCSIZ<15:0>
—
0000
0000
CHDPTR<15:0>
15:0
31:16
—
CHPDAT<7:0>
CHSPTR<15:0>
15:0
31:16
16/0
CHDSIZ<15:0>
15:0
31:16
17/1
CHSSIZ<15:0>
15:0
31:16
18/2
CHDSA<31:0>
15:0
31:16
19/3
CHSSA<31:0>
15:0
31:16
20/4
All Resets
Bit Range
Bits
32A0 DCH3CON
32C0
DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED)
FF00
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 90
TABLE 4-19:
Virtual Address
(BF88_#)
33B0 DCH4SSIZ
33C0 DCH4DSIZ
33D0 DCH4SPTR
33E0 DCH4DPTR
33F0 DCH4CSIZ
3400 DCH4CPTR
3410
DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED)
DCH4DAT
3420 DCH5CON
3430 DCH5ECON
DCH5INT
3450
DCH5SSA
3460 DCH5DSA
3470 DCH5SSIZ
3480 DCH5DSIZ
3490 DCH5SPTR
34A0 DCH5DPTR
DS61156G-page 91
34B0 DCH5CSIZ
34C0 DCH5CPTR
31:16
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
15:0
31:16
CHSSIZ15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
0000
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CHCSIZ<15:0>
15:0
—
—
0000
CHCPTR<15:0>
31:16
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ<7:0>
15:0
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
CHCPTR<15:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
2:
0000
0000
CHCSIZ<15:0>
—
FF00
0000
CHDPTR<15:0>
15:0
31:16
—
0000
0000
CHSPTR<15:0>
15:0
31:16
—
0000
00FF
CHDSIZ<15:0>
15:0
31:16
CHAIRQ<7:0>
CHSSIZ<15:0>
15:0
31:16
CHPRI<1:0>
CHDSA<31:0>
15:0
31:16
0000
CHSSA<31:0>
15:0
31:16
CHPDAT<7:0>
Legend:
1:
0000
0000
CHDPTR<15:0>
15:0
31:16
—
CHSPTR<15:0>
15:0
31:16
—
CHDSIZ<15:0>
15:0
31:16
All Resets
31/15
0000
0000
PIC32MX5XX/6XX/7XX
3440
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-19:
Virtual Address
(BF88_#)
34E0 DCH6CON
34F0 DCH6ECON
3500
DCH6INT
3510
DCH6SSA
3520 DCH6DSA
3530 DCH6SSIZ
3540 DCH6DSIZ
3550 DCH6SPTR
3560 DCH6DPTR
3570 DCH6CSIZ
3580 DCH6CPTR
DCH6DAT
© 2009-2011 Microchip Technology Inc.
35A0 DCH7CON
35B0 DCH7ECON
35C0
DCH7INT
35D0 DCH7SSA
35E0 DCH7DSA
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ<7:0>
15:0
31:16
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CHPRI<1:0>
CHAIRQ<7:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
0000
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
CHBUSY
—
—
—
—
—
—
CHCHNS
CHEN
CHAED
CHCHN
CHAEN
—
CHEDET
31:16
—
—
—
—
—
—
—
—
CFORCE
CABORT
PATEN
SIRQEN
AIRQEN
—
—
—
31:16
—
—
—
—
—
—
—
—
CHSDIE
CHSHIE
CHDDIE
CHDHIE
CHBCIE
CHCCIE
CHTAIE
CHERIE
0000
15:0
—
—
—
—
—
—
—
—
CHSDIF
CHSHIF
CHDDIF
CHDHIF
CHBCIF
CHCCIF
CHTAIF
CHERIF
0000
CHSIRQ<7:0>
15:0
31:16
15:0
31:16
15:0
CHPDAT<7:0>
0000
CHPRI<1:0>
CHAIRQ<7:0>
0000
0000
00FF
CHSSA<31:0>
CHDSA<31:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
2:
FF00
0000
Legend:
1:
0000
0000
CHCPTR<15:0>
31:16
0000
00FF
CHCSIZ<15:0>
—
0000
0000
CHDPTR<15:0>
15:0
31:16
—
CHPDAT<7:0>
CHSPTR<15:0>
15:0
31:16
16/0
CHDSIZ<15:0>
15:0
31:16
17/1
CHSSIZ<15:0>
15:0
31:16
18/2
CHDSA<31:0>
15:0
31:16
19/3
CHSSA<31:0>
15:0
31:16
20/4
All Resets
Bit Range
Register
Name
Bits
34D0 DCH5DAT
3590
DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED)
FF00
0000
0000
0000
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 92
TABLE 4-19:
Virtual Address
(BF88_#)
35F0 DCH7SSIZ
3600 DCH7DSIZ
3610 DCH7SPTR
3620 DCH7DPTR
3630 DCH7CSIZ
3640 DCH7CPTR
3650
DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED)
DCH7DAT
31:16
31/15
30/14
29/13
28/12
27/11
26/10
25/9
—
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
15:0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
0000
0000
0000
CHPDAT<7:0>
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices.
1:
2:
0000
0000
CHCPTR<15:0>
31:16
0000
0000
CHCSIZ<15:0>
—
0000
0000
CHDPTR<15:0>
15:0
31:16
22/6
CHSPTR<15:0>
15:0
31:16
23/7
CHDSIZ<15:0>
15:0
31:16
24/8
CHSSIZ<15:0>
—
All Resets
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-19:
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 93
Virtual Address
(BF80_#)
A000 CM1CON
A010 CM2CON
A060 CMSTAT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
—
31:16
—
—
—
—
—
—
—
—
15:0
ON
COE
CPOL
—
—
—
—
COUT
31:16
—
—
—
—
—
—
—
—
15:0
ON
COE
CPOL
—
—
—
—
COUT
31:16
—
—
—
—
—
—
—
15:0
—
FRZ
SIDL
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
EVPOL<1:0>
—
CREF
—
—
—
CCH<1:0>
—
—
All Resets
Register
Name
Bit Range
Bits
0000
00C3
—
—
—
—
—
EVPOL<1:0>
—
CREF
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
C2OUT
C1OUT
0000
CCH<1:0>
0000
00C3
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1)
Virtual Address
(BF80_#)
TABLE 4-21:
9800 CVRCON
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
—
15:0
ON
—
—
—
—
VREFSEL(2)
25/9
24/8
23/7
—
—
—
—
—
CVROE
BGSEL<1:0>(2)
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
CVRR
CVRSS
CVR<3:0>
All Resets
Register
Name
Bit Range
Bits
0000
0100
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
These bits are not available on PIC32MX575/675/695/775 devices. On these devices, reset value for CVRCON is 0000.
1:
2:
PIC32MX5XX/6XX/7XX
DS61156G-page 94
COMPARATOR REGISTER MAP(1)
TABLE 4-20:
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF80_#)
FLASH CONTROLLER REGISTER MAP
F410
NVMKEY
F420
NVMADDR(1)
F430
NVMDATA
F440
NVMSRC
ADDR
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
WR
WREN
WRERR
LVDERR
LVDSTAT
—
—
—
—
—
—
—
31:16
NVMOP<3:0>
0000
0000
NVMKEY<31:0>
15:0
31:16
0000
0000
NVMADDR<31:0>
15:0
31:16
0000
0000
NVMDATA<31:0>
15:0
31:16
0000
0000
NVMSRCADDR<31:0>
15:0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
1:
SYSTEM CONTROL REGISTER MAP(1,2)
F010
OSCTUN
0000 WDTCON
F600
RCON
F610 RSWRST
DS61156G-page 95
F230
SYSKEY
Bit Range
Register
Name
Bits
31/15
30/14
31:16
—
—
15:0
—
31:16
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
31:16
—
—
—
—
—
15:0
ON
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
CMR
VREGS
EXTR
SWR
—
WDTO
SLEEP
IDLE
BOR
POR
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SWRST
0000
31:16
15:0
29/13
28/12
27/11
26/10
23/7
22/6
FRCDIV<2:0>
—
SOSCRDY
—
NOSC<2:0>
CLKLOCK
ULOCK
SLOCK
SLPEN
CF
UFRCEN
SOSCEN
OSWEN
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PLLODIV<2:0>
COSC<2:0>
—
25/9
24/8
21/5
20/4
19/3
18/2
PBDIV<1:0>
17/1
16/0
PLLMULT<2:0>
0000
TUN<5:0>
—
—
—
—
SWDTPS<4:0>
—
—
0000
—
WDTCLR
0000
SYSKEY<31:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
2:
0000
0000
Legend:
1:
0000
0000
0000
PIC32MX5XX/6XX/7XX
Virtual Address
(BF80_#)
TABLE 4-23:
F000 OSCCON
0000
All Resets(2)
F400 NVMCON(1)
31/15
All Resets
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-22:
Virtual Address
(BF88_#)
Register
Name
6000
TRISA
6010
PORTA
6020
LATA
6030
ODCA
PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISA15
TRISA14
—
—
—
TRISA10
TRISA9
—
TRISA7
TRISA6
TRISA5
TRISA4
TRISA3
TRISA2
TRISA1
TRISA0
C6FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RA15
RA14
—
—
—
RA10
RA9
—
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATA15
LATA14
—
—
—
LATA10
LATA9
—
LATA7
LATA6
LATA5
LATA4
LATA3
LATA2
LATA1
LATA0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCA15
ODCA14
—
—
—
ODCA10
ODCA9
—
ODCA7
ODCA6
ODCA5
ODCA4
ODCA3
ODCA2
ODCA1
ODCA0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
Virtual Address
(BF88_#)
Register
Name
TABLE 4-25:
6040
TRISB
© 2009-2011 Microchip Technology Inc.
6050
All Resets
Bit Range
Bits
PORTB REGISTER MAP(1)
PORTB
6060
LATB
6070
ODCB
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISB15
TRISB14
TRISB13
TRISB12
TRISB11
TRISB10
TRISB9
TRISB8
TRISB7
TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RB15
RB14
RB13
RB12
RB11
RB10
RB9
RB8
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATB15
LATB14
LATB13
LATB12
LATB11
LATB10
LATB9
LATB8
LATB7
LATB6
LATB5
LATB4
LATB3
LATB2
LATB1
LATB0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCB15
ODCB14
ODCB13
ODCB12
ODCB11
ODCB10
ODCB9
ODCB8
ODCB7
ODCB6
ODCB5
ODCB4
ODCB3
ODCB2
ODCB1
ODCB0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS61156G-page 96
TABLE 4-24:
Virtual Address
(BF88_#)
Register
Name
6080
TRISC
PORTC
60A0
LATC
60B0
ODCC
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISC15
TRISC14
TRISC13
TRISC12
—
—
—
—
—
—
—
—
—
—
—
—
F000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
—
—
—
—
—
—
—
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
—
—
—
—
—
—
—
—
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
Register
Name
TRISC
PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bit Range
Bits
6090 PORTC
60A0
LATC
60B0
ODCC
DS61156G-page 97
Legend:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISC15
TRISC14
TRISC13
TRISC12
—
—
—
—
—
—
—
TRISC4
TRISC3
TRISC2
TRISC1
—
F00F
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RC15
RC14
RC13
RC12
—
—
—
—
—
—
—
RC4
RC3
RC2
RC1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATC15
LATC14
LATC13
LATC12
—
—
—
—
—
—
—
LATC4
LATC3
LATC2
LATC1
—
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCC15
ODCC14
ODCC13
ODCC12
—
—
—
—
—
—
—
ODCC4
ODCC3
ODCC2
ODCC1
—
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
PIC32MX5XX/6XX/7XX
Virtual Address
(BF88_#)
TABLE 4-27:
6080
All Resets
31/15
All Resets
6090
PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-26:
Virtual Address
(BF88_#)
Register
Name
60C0
TRISD
60D0
PORTD
60E0
LATD
60F0
ODCD
PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
0FFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
Register
Name
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF88_#)
TABLE 4-29:
60C0
TRISD
All Resets
Bit Range
Bits
PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
60D0 PORTD
60E0
LATD
60F0
ODCD
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
TRISD15
TRISD14
TRISD13
TRISD12
TRISD11
TRISD10
TRISD9
TRISD8
TRISD7
TRISD6
TRISD5
TRISD4
TRISD3
TRISD2
TRISD1
TRISD0
FFFF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RD15
RD14
RD13
RD12
RD11
RD10
RD9
RD8
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LAT15
LAT14
LAT13
LAT12
LATD11
LATD10
LATD9
LATD8
LATD7
LATD6
LATD5
LATD4
LATD3
LATD2
LATD1
LATD0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCD15
ODCD14
ODCD13
ODCD12
ODCD11
ODCD10
ODCD9
ODCD8
ODCD7
ODCD6
ODCD5
ODCD4
ODCD3
ODCD2
ODCD1
ODCD0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS61156G-page 98
TABLE 4-28:
Virtual Address
(BF88_#)
Register
Name
6100
TRISE
PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
6110
PORTE
6120
LATE
6130
ODCE
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
00FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
15:0
—
—
—
—
—
—
—
—
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Register
Name
TRISE
6110
PORTE
6120
LATE
6130
ODCE
PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31/15
30/14
29/13
28/12
27/11
26/10
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
TRISE9
TRISE8
TRISE7
TRISE6
TRISE5
TRISE4
TRISE3
TRISE2
TRISE1
TRISE0
03FF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
0000
15:0
—
—
—
—
—
—
RE9
RE8
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
xxxx
DS61156G-page 99
15:0
—
—
—
—
—
—
LATE9
LATE8
LATE7
LATE6
LATE5
LATE4
LATE3
LATE2
LATE1
LATE0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
ODCE9
ODCE8
ODCE7
0DCE6
ODCE5
ODCE4
ODCE3
ODCE2
ODCE1
ODCE0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
Virtual Address
(BF88_#)
TABLE 4-31:
6100
0000
31:16
Legend:
1:
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-30:
Virtual Address
(BF88_#)
Register
Name
6140
TRISF
PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
6150 PORTF
6160
LATF
6170
ODCF
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
TRISF5
31:16
—
—
—
—
—
—
—
—
—
—
—
20/4
17/1
16/0
19/3
18/2
—
—
—
—
—
TRISF4
TRISF3
—
TRISF1
TRISF0
003B
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
RF5
RF4
RF3
—
RF1
RF0
xxxx
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
LATF5
LATF4
LATF3
—
LATF1
LATF0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
ODCF5
ODCF4
ODCF3
—
ODCF1
ODCF0
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Register
Name
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF88_#)
TABLE 4-33:
6140
TRISF
6150
PORTF
6160
LATF
6170
ODCF
0000
31:16
Legend:
1:
All Resets
Bit Range
Bits
PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L,
PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L,
PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
31/15
30/14
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
31:16
—
—
15:0
—
—
29/13
28/12
27/11
26/10
25/9
—
—
—
—
TRISF13
TRISF12
—
—
—
—
—
—
RF13
RF12
—
—
—
—
—
—
LATF13
LATF12
—
—
—
—
—
—
ODCF13
ODCF12
—
—
21/5
20/4
19/3
18/2
17/1
16/0
24/8
23/7
22/6
—
—
—
—
—
—
—
—
—
—
0000
—
TRISF8
—
—
TRISF5
TRISF4
TRISF3
TRISF2
TRISF1
TRISF0
313F
—
—
—
—
—
—
—
—
—
—
0000
—
RF8
—
—
RF5
RF4
RF3
RF2
RF1
RF0
xxxx
—
—
—
—
—
—
—
—
—
—
0000
—
LATF8
—
—
LATF5
LATF4
LATF3
LATF2
LATF1
LATF0
xxxx
—
—
—
—
—
—
—
—
—
—
0000
—
ODCF8
—
—
ODCF5
ODCF4
ODCF3
ODCF2
ODCF1
ODCF0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Bits
PIC32MX5XX/6XX/7XX
DS61156G-page 100
TABLE 4-32:
Virtual Address
(BF88_#)
Register
Name
6180
TRISG
6190 PORTG
61A0
LATG
ODCG
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
TRISG9
TRISG8
—
—
—
—
TRISG7
TRISG6
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
RG9
RG8
RG7
RG6
—
31:16
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
LATG9
LATG8
LATG7
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
ODCG9
ODCG8
19/3
18/2
17/1
16/0
—
—
—
—
0000
TRISG3
TRISG2
—
—
03CC
—
—
—
—
0000
—
RG3
RG2
—
—
xxxx
—
—
—
—
—
—
0000
LATG6
—
—
LATG3
LATG2
—
—
xxxx
—
—
—
—
—
—
—
—
0000
ODCG7
ODCG6
—
—
ODCG3
ODCG2
—
—
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
Register
Name
6180
TRISG
PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
Bit Range
Bits
6190 PORTG
DS61156G-page 101
61A0
LATG
61B0
ODCG
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
TRISG15
TRISG14
TRISG13
TRISG12
—
—
TRISG9
TRISG8
TRISG7
TRISG6
—
—
TRISG3
TRISG2
TRISG1
TRISG0
F3CF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
RG15
RG14
RG13
RG12
—
—
RG9
RG8
RG7
RG6
—
—
RG3
RG2
RG1
RG0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
LATG15
LATG14
LATG13
LATG12
—
—
LATG9
LATG8
LATG7
LATG6
—
—
LATG3
LATG2
LATG1
LATG0
xxxx
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
ODCG15
ODCG14
ODCG13
ODCG12
—
—
ODCG9
ODCG8
ODCG7
ODCG6
—
—
ODCG3
ODCG2
ODCG1
ODCG0
0000
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
0000
PIC32MX5XX/6XX/7XX
Virtual Address
(BF88_#)
TABLE 4-35:
All Resets
31/15
All Resets
61B0
PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-34:
Virtual Address
(BF88_#)
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,
PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1)
61C0 CNCON
61D0
CNEN
61E0
CNPUE
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
CNEN21
CNEN20
CNEN19
CNEN18
CNEN17
CNEN16
0000
15:0
CNEN15
CNEN14
CNEN13
CNEN12
CNEN11
CNEN10
CNEN9
CNEN8
CNEN7
CNEN6
CNEN5
CNEN4
CNEN3
CNEN2
CNEN1
CNEN0
0000
31:16
—
—
—
—
—
—
—
—
—
—
CNPUE21
CNPUE20
CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
CNPUE9
CNPUE8
CNPUE7
CNPUE6
CNPUE5
CNPUE4
CNPUE3
15:0
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
CNPUE2
CNPUE1
CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
TABLE 4-37:
Virtual Address
(BF88_#)
All Resets
Register
Name
Bit Range
Bits
0000
0000
CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1)
61C0 CNCON
61D0
CNEN
© 2009-2011 Microchip Technology Inc.
61E0
CNPUE
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
CNEN18
CNEN17
CNEN16
0000
15:0
CNEN15
CNEN14
CNEN13
CNEN12
CNEN11
CNEN10
CNEN9
CNEN8
CNEN7
CNEN6
CNEN5
CNEN4
CNEN3
CNEN2
CNEN1
CNEN0
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
CNPUE9
CNPUE8
CNPUE7
CNPUE6
CNPUE5
CNPUE4
CNPUE3
15:0
CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10
0000
CNPUE18 CNPUE17 CNPUE16 0000
CNPUE2
CNPUE1
CNPUE0
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
1:
All Resets
Bit Range
Register
Name
Bits
0000
PIC32MX5XX/6XX/7XX
DS61156G-page 102
TABLE 4-36:
Virtual Address
(BF80_#)
Register
Name
7000
PMCON
7010 PMMODE
7020 PMADDR
7030 PMDOUT
PMDIN
7050
PMAEN
7060
PMSTAT
30/14
29/13
31:16
—
—
—
15:0
ON
FRZ
SIDL
31:16
—
—
—
15:0
BUSY
31:16
—
IRQM<1:0>
—
—
28/12
27/11
—
—
ADRMUX<1:0>
—
—
INCM<1:0>
—
—
26/10
25/9
24/8
23/7
22/6
—
—
—
—
—
PMPTTL
PTWREN
PTRDEN
—
—
—
MODE16
—
—
MODE<1:0>
—
—
—
—
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
ALP
CS2P
CS1P
—
WRSP
RDSP
0000
—
—
—
—
—
—
0000
—
—
—
—
WAITB<1:0>
—
15:0 CS2EN/A15 CS1EN/A14
WAITM<3:0>
—
WAITE<1:0>
—
ADDR<13:0>
31:16
31:16
—
—
—
—
—
—
—
15:0
—
—
0000
0000
—
—
—
—
—
—
—
0000
PTEN<15:0>
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
IBF
IBOV
—
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
—
OB3E
OB2E
OB1E
OB0E
008F
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
F200 DDPCON
Bit Range
Bits
Register
Name
Virtual Address
(BF80_#)
PROGRAMMING AND DIAGNOSTICS REGISTER MAP
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
19/3
18/2
17/1
16/0
—
—
—
—
0000
JTAGEN
TROEN
—
TDOEN
0008
DS61156G-page 103
PIC32MX5XX/6XX/7XX
TABLE 4-39:
Legend:
0000
0000
Legend:
1:
0000
0000
DATAIN<31:0>
15:0
0000
0000
DATAOUT<31:0>
15:0
31:16
CSF<1:0>
21/5
All Resets
7040
31/15
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
PARALLEL MASTER PORT REGISTER MAP(1)
TABLE 4-38:
Virtual Address
(BF88_#)
4010 CHEACC(1)
CHETAG(1)
4030 CHEMSK(1)
4040
CHEW0
4050
CHEW1
4060
CHEW2
4070
CHEW3
4080
CHELRU
4090
CHEHIT
40A0
CHEMIS
40C0 CHEPFABT
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16 CHEWEN
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16 LTAGBOOT
15:0
31:16
DCSZ<1:0>
—
15:0
15:0
31:16
15:0
15:0
—
—
—
PREFEN<1:0>
—
—
—
—
—
—
—
—
—
—
—
—
CHECOH 0000
PFMWS<2:0>
—
—
0007
—
CHEIDX<3:0>
—
—
—
—
—
—
—
—
—
—
00xx
LVALID
LLOCK
LTYPE
—
xxx2
—
—
—
—
—
0000
—
—
—
—
—
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
CHELRU<24:16>
CHELRU<15:0>
CHEHIT<31:0>
CHEMIS<31:0>
CHEPFABT<31:0>
© 2009-2011 Microchip Technology Inc.
Legend:
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
Reset value is dependent on DEVCFGx configuration.
1:
2:
0000
0000
LTAG<23:16>
CHEW3<31:0>
15:0
31:16
—
—
16/0
CHEW2<31:0>
15:0
15:0
—
17/1
CHEW1<31:0>
31:16
31:16
18/2
CHEW0<31:0>
31:16
15:0
19/3
LMASK<15:5>
31:16
31:16
20/4
LTAG<15:4>
—
15:0
31:16
21/5
All Resets
Bit Range
Register
Name
Bits
4000 CHECON(1,2)
4020
PREFETCH REGISTER MAP
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
PIC32MX5XX/6XX/7XX
DS61156G-page 104
TABLE 4-40:
Virtual Address
(BF80_#)
Register
Name
0200
RTCCON
0210 RTCALRM
0220
RTCTIME
0230 RTCDATE
0240 ALRMTIME
0250 ALRMDATE
Legend:
Note
1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
15:0
ON
FRZ
SIDL
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
15:0
ALRMEN
CHIME
PIV
ALRMSYNC
HR01<3:0>
15:0
SEC10<3:0>
SEC01<3:0>
31:16
YEAR10<3:0>
YEAR01<3:0>
15:0
DAY10<3:0>
DAY01<3:0>
31:16
HR10<3:0>
HR01<3:0>
15:0
SEC10<3:0>
—
—
—
DAY10<3:0>
—
—
20/4
19/3
18/2
17/1
16/0
RTSECSEL RTCCLKON
—
—
—
DAY01<3:0>
0000
—
—
—
—
RTCWREN RTCSYNC HALFSEC
—
—
—
RTCOE
0000
—
0000
ARPT<7:0>
MIN10<3:0>
—
—
—
—
—
—
—
—
—
—
—
MONTH10<3:0>
—
—
—
—
—
xxxx
—
MONTH01<3:0>
—
MIN10<3:0>
—
0000
MIN01<3:0>
MONTH10<3:0>
—
SEC01<3:0>
—
21/5
AMASK<3:0>
HR10<3:0>
15:0
22/6
CAL<9:0>
31:16
31:16
23/7
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
RTCC REGISTER MAP(1)
TABLE 4-41:
—
—
xx00
xxxx
WDAY01<3:0>
xx00
MIN01<3:0>
xxxx
—
—
—
xx00
MONTH01<3:0>
00xx
WDAY01<3:0>
xx0x
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS61156G-page 105
2FF0 DEVCFG3
2FF4 DEVCFG2
2FF8 DEVCFG1
2FFC DEVCFG0
Legend:
31/15
30/14
31:16 FVBUSIO FUSBIDIO
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
—
—
—
FCANIO
FETHIO
FMIIEN
—
—
—
—
—
FSRSSEL<2:0>
—
—
—
—
FPLLODIV<2:0>
xxxx
—
FPLLIDIV<2:0>
xxxx
15:0
18/2
17/1
16/0
xxxx
USERID<15:0>
31:16
—
—
—
—
—
15:0
UPLLEN
—
—
—
—
31:16
—
—
—
—
—
—
15:0
FCKSM<1:0>
FPBDIV<1:0>
—
OSCIOFNC
31:16
—
—
—
—
—
—
—
—
15:0
—
All Resets
Bit Range
Bits
Register
Name
CP
PWP<3:0>
—
—
—
—
UPLLIDIV<2:0>
—
xxxx
—
—
FPLLMUL<2:0>
FWDTEN
—
—
IESO
—
FSOSCEN
—
BWP
—
—
—
—
—
—
—
—
—
23/7
22/6
21/5
20/4
POSCMOD<1:0>
WDTPS<4:0>
—
xxxx
FNOSC<2:0>
xxxx
PWP<7:4>
ICESEL
—
xxxx
DEBUG<1:0>
xxxx
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Virtual Address
(BF80_#)
Register
Name
TABLE 4-43:
F220
DEVID
DEVICE AND REVISION ID SUMMARY(1)
Legend:
Note
1:
31:16
15:0
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
VER<3:0>
19/3
DEVID<27:16>
DEVID<15:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Reset values are dependent on the device variant. Refer to “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80480) for more information.
18/2
17/1
16/0
All Resets
Bits
Bit Range
Virtual Address
(BFC0_#)
DEVCFG: DEVICE CONFIGURATION WORD SUMMARY
xxxx
xxxx
PIC32MX5XX/6XX/7XX
DS61156G-page 106
TABLE 4-42:
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF88_#)
Register
Name
5040
U1OTGIR(2)
5050
U1OTGIE
5070
U1OTGCON
5080
U1PWRC
5200
U1IR(2)
5210
U1IE
U1EIR(2)
5240
U1EIE
U1STAT
5250
(3)
U1CON
DS61156G-page 107
5260
U1ADDR
5270
U1BDTP1
5280
(3)
U1FRML
Legend:
Note
1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
22/6
21/5
—
—
20/4
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
IDIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
ID
—
LSTATE
—
SESVD
SESEND
—
VBUSVD
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
DPPULUP
31:16
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
UACTPND(4)
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
STALLIF
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
STALLIE
—
—
—
—
—
—
—
—
—
ACTVIF
—
—
—
SESVDIF SESENDIF
—
ACTVIE
—
SESVDIE SESENDIE
DMPULUP DPPULDWN DMPULDWN VBUSON
—
—
—
ATTACHIE RESUMEIE
—
—
—
—
—
—
0000
VBUSVDIF 0000
—
0000
VBUSVDIE 0000
—
—
—
0000
VBUSCHG
VBUSDIS
0000
—
—
—
—
—
16/0
OTGEN
—
USLPGRD USBBUSY
ATTACHIF RESUMEIF
—
31:16
17/1
—
T1MSECIE LSTATEIE
15:0
18/2
—
T1MSECIF LSTATEIF
—
19/3
—
USUSPEND USBPWR
—
IDLEIF
TRNIF
SOFIF
UERRIF
—
—
—
—
IDLEIE
TRNIE
SOFIE
UERRIE
—
—
—
—
CRC5EF
0000
0000
—
0000
URSTIF
0000
DETACHIF 0000
—
0000
URSTIE
0000
DETACHIE 0000
—
0000
0000
15:0
—
—
—
—
—
—
—
—
BTSEF
BMXEF
DMAEF
BTOEF
DFN8EF
CRC16EF
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
BTSEE
BMXEE
DMAEE
BTOEE
DFN8EE
CRC16EE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
DIR
PPBI
—
—
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
0000
USBEN
0000
SOFEN
0000
ENDPT<3:0>(4)
—
—
(4)
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
LSPDEN
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
JSTATE
(4)
SE0
—
—
—
PKTDIS
TOKBUSY
—
EOFEF
—
CRC5EE
EOFEE
USBRST
HOSTEN
RESUME
PPBRST
—
—
—
—
—
PIDEE
—
DEVADDR<6:0>
—
—
—
—
—
—
—
FRML<7:0>
—
0000
0000
0000
0000
0000
0000
—
—
BDTPTRL<7:1>
—
PIDEF
—
—
—
0000
—
0000
—
0000
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
PIC32MX5XX/6XX/7XX
5230
23/7
All Resets
Bits
5060 U1OTGSTAT(3)
5220
USB REGISTER MAP(1)
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-44:
Virtual Address
(BF88_#)
Register
Name
5290
U1FRMH(3)
USB REGISTER MAP(1) (CONTINUED)
52A0
U1TOK
© 2009-2011 Microchip Technology Inc.
52B0
U1SOF
52C0
U1BDTP2
52D0
U1BDTP3
52E0
U1CNFG1
5300
U1EP0
5310
U1EP1
5320
U1EP2
5330
U1EP3
5340
U1EP4
5350
U1EP5
5360
U1EP6
5370
U1EP7
5380
U1EP8
5390
U1EP9
53A0
U1EP10
Legend:
Note
1:
2:
3:
4:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
17/1
16/0
—
—
0000
—
—
0000
—
—
FRMH<2:0>
PID<3:0>
All Resets
Bit Range
Bits
0000
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
EP<3:0>
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
UTEYE
UOEMON
USBFRZ
USBSIDL
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
LSPD
RETRYDIS
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
0000
CNT<7:0>
—
—
—
—
—
—
—
—
BDTPTRH<7:0>
—
—
—
—
0000
0000
—
0000
0000
—
—
—
BDTPTRU<7:0>
0000
0000
—
0000
UASUSPND 0001
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
PIC32MX5XX/6XX/7XX
DS61156G-page 108
TABLE 4-44:
Virtual Address
(BF88_#)
Register
Name
53B0
U1EP11
53C0
U1EP12
53D0
U1EP13
53E0
U1EP14
53F0
U1EP15
USB REGISTER MAP(1) (CONTINUED)
Legend:
Note
1:
2:
3:
4:
20/4
19/3
18/2
17/1
16/0
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-44:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
EPCONDIS
EPRXEN
EPTXEN
EPSTALL
EPHSHK
0000
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
This register does not have associated SET and INV registers.
This register does not have associated CLR, SET and INV registers.
Reset value for this bit is undefined.
PIC32MX5XX/6XX/7XX
DS61156G-page 109
Virtual Address
(BF88_#)
Register
Name
B000
C1CON
C1CFG
B020
C1INT
B030
B050
B060
C1VEC
C1TREC
C1FSTAT
C1RXOVF
B070
C1TMR
B080
C1RXM0
B090
C1RXM1
B0A0
© 2009-2011 Microchip Technology Inc.
B0B0
C1RXM2
C1RXM3
B0C0 C1FLTCON0
B0D0 C1FLTCON1
B0E0 C1FLTCON2
B0F0 C1FLTCON3
Legend:
Note
1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
CANCAP
—
31:16
—
—
—
—
ABAT
15:0
ON
FRZ
SIDLE
—
CANBUSY
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
WAKFIL
—
—
—
15:0 SEG2PHTS
SAM
REQOP<2:0>
SEG1PH<2:0>
OPMOD<2:0>
PRSEG<2:0>
18/2
17/1
16/0
—
—
—
DNCNT<4:0>
SJW<1:0>
All Resets
Bit Range
Bits
B010
B040
CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
0480
0000
SEG2PH<2:0>
0000
BRP<5:0>
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
TXBO
TXBP
FIFOIP24
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18 FIFOIP17 FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
15:0
FILHIT<4:0>
—
ICODE<6:0>
TERRCNT<7:0>
0040
TXWARN RXWARN
EWARN 0000
RERRCNT<7:0>
31:16 FIFOIP31
FIFOIP30
FIFOIP29 FIFOIP28 FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14
FIFOIP13 FIFOIP12 FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
RXBP
FIFOIP8
0000
0000
FIFOIP1
FIFOIP0 0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0 0000
CANTS<15:0>
15:0
0000
CANTSPRE<15:0>
31:16
0000
SID<10:0>
15:0
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
xxxx
31:16
FLTEN3
MSEL3<1:0>
FSEL3<4:0>
FLTEN2
MSEL2<1:0>
FSEL2<4:0>
0000
15:0
FLTEN1
MSEL1<1:0>
FSEL1<4:0>
FLTEN0
MSEL0<1:0>
FSEL0<4:0>
0000
31:16
FLTEN7
MSEL7<1:0>
FSEL7<4:0>
FLTEN6
MSEL6<1:0>
FSEL6<4:0>
0000
15:0
FLTEN5
MSEL5<1:0>
FSEL5<4:0>
FLTEN4
MSEL4<1:0>
FSEL4<4:0>
0000
31:16 FLTEN11
MSEL11<1:0>
FSEL11<4:0>
FLTEN10
MSEL10<1:0>
FSEL10<4:0>
0000
15:0
FLTEN9
MSEL9<1:0>
FSEL9<4:0>
FLTEN8
MSEL8<1:0>
FSEL8<4:0>
0000
31:16 FLTEN15
MSEL15<1:0>
FSEL15<4:0>
FLTEN14
MSEL14<1:0>
FSEL14<4:0>
0000
15:0
MSEL13<1:0>
FSEL13<4:0>
FLTEN12
MSEL12<1:0>
FSEL12<4:0>
0000
FLTEN13
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS61156G-page 110
TABLE 4-45:
Virtual Address
(BF88_#)
B100 C1FLTCON4
B110 C1FLTCON5
B120 C1FLTCON6
B130 C1FLTCON7
B140
B340
CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
C1RXFn
(n = 0-31)
C1FIFOBA
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
MSEL19<1:0>
FSEL19<4:0>
FLTEN18
MSEL18<1:0>
FSEL18<4:0>
0000
15:0
FLTEN17
MSEL17<1:0>
FSEL17<4:0>
FLTEN16
MSEL16<1:0>
FSEL16<4:0>
0000
31:16 FLTEN23
MSEL23<1:0>
FSEL23<4:0>
FLTEN22
MSEL22<1:0>
FSEL22<4:0>
0000
15:0
FLTEN21
MSEL21<1:0>
FSEL21<4:0>
FLTEN20
MSEL20<1:0>
FSEL20<4:0>
0000
31:16 FLTEN27
MSEL27<1:0>
FSEL27<4:0>
FLTEN26
MSEL26<1:0>
FSEL26<4:0>
0000
15:0
FLTEN25
MSEL25<1:0>
FSEL25<4:0>
FLTEN24
MSEL24<1:0>
FSEL24<4:0>
0000
31:16 FLTEN31
MSEL31<1:0>
FSEL31<4:0>
FLTEN30
MSEL30<1:0>
FSEL30<4:0>
0000
15:0
MSEL29<1:0>
FSEL29<4:0>
FLTEN28
MSEL28<1:0>
FSEL28<4:0>
FLTEN29
31:16
SID<10:0>
-—
15:0
EXID
—
0000
EID<17:16>
EID<15:0>
31:16
xxxx
xxxx
0000
C1FIFOBA<31:0>
15:0
0000
—
—
—
—
—
—
—
—
—
—
—
—
FRESET
UINC
DONLY
—
—
—
—
TXEN
TXABAT
TXLARB
FSIZE<4:0>
TXERR
TXREQ
RTREN
0000
TXPRI<1:0>
0000
31:16
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
—
—
—
—
RXN
RXOVFLIE RXFULLIE RXHALFIE
0000
EMPTYIE
15:0
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
B370
C1FIFOUAn 31:16
(n = 0-31)
15:0
B380
C1FIFOCIn 31:16
(n = 0-31)
15:0
Legend:
Note
1:
29/13
RXN
0000
EMPTYIF
0000
C1FIFOUA<31:0>
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C1FIFOCI<4:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
0000
0000
DS61156G-page 111
PIC32MX5XX/6XX/7XX
C1FIFOINTn
(n = 0-31)
30/14
31:16 FLTEN19
C1FIFOCONn 31:16
B350
(n = 0-31)
15:0
B360
31/15
All Resets
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-45:
Virtual Address
(BF88_#)
Register
Name
C000
C2CON
C010
C2CFG
C040
C050
C060
C070
C080
C0A0
C0B0
© 2009-2011 Microchip Technology Inc.
C0B0
C2INT
C2VEC
C2TREC
C2FSTAT
C2RXOVF
C2TMR
C2RXM0
C2RXM1
C2RXM2
C2RXM3
C0C0 C2FLTCON0
C0D0 C2FLTCON1
C0E0 C2FLTCON2
C0F0 C2FLTCON3
Legend:
Note
1:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
23/7
21/5
31:16
—
—
—
—
ABAT
15:0
ON
FRZ
SIDLE
—
CANBUSY
—
—
—
—
—
—
31:16
—
—
—
—
—
—
—
—
—
WAKFIL
—
15:0 SEG2PHTS
SAM
REQOP<2:0>
22/6
SEG1PH<2:0>
OPMOD<2:0>
PRSEG<2:0>
20/4
19/3
CANCAP
—
18/2
17/1
16/0
—
—
—
DNCNT<4:0>
—
SJW<1:0>
—
All Resets
Bit Range
Bits
C020
C030
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
0480
0000
SEG2PH<2:0>
0000
BRP<5:0>
0000
31:16
IVRIE
WAKIE
CERRIE
SERRIE
RBOVIE
—
—
—
—
—
—
—
MODIE
CTMRIE
RBIE
TBIE
0000
15:0
IVRIF
WAKIF
CERRIF
SERRIF
RBOVIF
—
—
—
—
—
—
—
MODIF
CTMRIF
RBIF
TBIF
0000
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
31:16
—
—
—
—
—
—
—
—
TXBO
TXBP
TXWARN
RXWARN
EWARN
15:0
FILHIT<4:0>
—
—
—
ICODE<6:0>
TERRCNT<7:0>
0040
RERRCNT<7:0>
31:16 FIFOIP31
FIFOIP30 FIFOIP29 FIFOIP28
FIFOIP27
FIFOIP26
FIFOIP25
15:0
FIFOIP14 FIFOIP13 FIFOIP12
FIFOIP11
FIFOIP10
FIFOIP9
FIFOIP15
RXBP
FIFOIP24
FIFOIP8
0000
0000
FIFOIP23
FIFOIP22
FIFOIP21
FIFOIP20
FIFOIP19
FIFOIP18
FIFOIP17
FIFOIP16 0000
FIFOIP7
FIFOIP6
FIFOIP5
FIFOIP4
FIFOIP3
FIFOIP2
FIFOIP1
FIFOIP0
0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25
RXOVF24
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10
RXOVF8
RXOVF7
31:16
RXOVF9
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
CANTS<15:0>
15:0
0000
CANTSPRE<15:0>
31:16
0000
SID<10:0>
15:0
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
-—
MIDE
—
EID<17:16>
xxxx
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
EID<15:0>
31:16
xxxx
SID<10:0>
15:0
0000
EID<15:0>
xxxx
31:16
FLTEN3
MSEL3<1:0>
FSEL3<4:0>
FLTEN2
MSEL2<1:0>
FSEL2<4:0>
0000
15:0
FLTEN1
MSEL1<1:0>
FSEL1<4:0>
FLTEN0
MSEL0<1:0>
FSEL0<4:0>
0000
31:16
FLTEN7
MSEL7<1:0>
FSEL7<4:0>
FLTEN6
MSEL6<1:0>
FSEL6<4:0>
0000
15:0
FLTEN5
MSEL5<1:0>
FSEL5<4:0>
FLTEN4
MSEL4<1:0>
FSEL4<4:0>
0000
31:16 FLTEN11
MSEL11<1:0>
FSEL11<4:0>
FLTEN10
MSEL10<1:0>
FSEL10<4:0>
0000
15:0
FLTEN9
MSEL9<1:0>
FSEL9<4:0>
FLTEN8
MSEL8<1:0>
FSEL8<4:0>
0000
31:16 FLTEN15
MSEL15<1:0>
FSEL15<4:0>
FLTEN14
MSEL14<1:0>
FSEL14<4:0>
0000
15:0
MSEL13<1:0>
FSEL13<4:0>
FLTEN12
MSEL12<1:0>
FSEL12<4:0>
0000
FLTEN13
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
PIC32MX5XX/6XX/7XX
DS61156G-page 112
TABLE 4-46:
Virtual Address
(BF88_#)
C100 C2FLTCON4
C110 C2FLTCON5
C120 C2FLTCON6
C130 C2FLTCON7
C140
C340
CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
C2RXFn
(n = 0-31)
C2FIFOBA
C2FIFOINTn
(n = 0-31)
29/13
28/12
27/11
26/10
25/9
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
MSEL19<1:0>
FSEL19<4:0>
FLTEN18
MSEL18<1:0>
FSEL18<4:0>
0000
15:0
FLTEN17
MSEL17<1:0>
FSEL17<4:0>
FLTEN16
MSEL16<1:0>
FSEL16<4:0:
0000
31:16 FLTEN23
MSEL23<1:0>
FSEL23<4:0>
FLTEN22
MSEL22<1:0>
FSEL22<4:0>
0000
15:0
FLTEN21
MSEL21<1:0>
FSEL21<4:0>
FLTEN20
MSEL20<1:0>
FSEL20<4:0>
0000
31:16 FLTEN27
MSEL27<1:0>
FSEL27<4:0>
FLTEN26
MSEL26<1:0>
FSEL26<4:0>
0000
15:0
FLTEN25
MSEL25<1:0>
FSEL25<4:0>
FLTEN24
MSEL24<1:0>
FSEL24<4:0>
0000
31:16 FLTEN31
MSEL31<1:0>
FSEL31<4:0>
FLTEN30
MSEL30<1:0>
FSEL30<4:0>
0000
15:0
MSEL29<1:0>
FSEL29<4:0>
FLTEN28
MSEL28<1:0>
FSEL28<4:0>
FLTEN29
31:16
-—
SID<10:0>
15:0
EXID
—
0000
EID<17:16>
EID<15:0>
31:16
xxxx
xxxx
0000
C2FIFOBA<31:0>
15:0
0000
—
—
—
—
—
—
—
—
—
—
—
—
FRESET
UINC
DONLY
—
—
—
—
TXEN
TXABAT
TXLARB
FSIZE<4:0>
TXERR
TXREQ
RTREN
0000
TXPRI<1:0>
0000
—
—
—
—
—
TXNFULLIE TXHALFIE TXEMPTYIE
—
—
—
—
15:0
—
—
—
—
—
TXNFULLIF TXHALFIF TXEMPTYIF
—
—
—
—
RXOVFLIF RXFULLIF RXHALFIF
C2FIFOUAn 31:16
(n = 0-31)
15:0
C380
C2FIFOCIn 31:16
(n = 0-31)
15:0
RXN
0000
EMPTYIF
0000
C2FIFOUA<31:0>
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
C2FIFOCI<4:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
0000
0000
DS61156G-page 113
PIC32MX5XX/6XX/7XX
31:16
RXN
0000
RXOVFLIE RXFULLIE RXHALFIE
EMPTYIE
C370
Legend:
Note
1:
30/14
31:16 FLTEN19
C2FIFOCONn 31:16
C350
(n = 0-31)
15:0
C360
31/15
All Resets
Bit Range
Bits
Register
Name
© 2009-2011 Microchip Technology Inc.
TABLE 4-46:
Virtual Address
(BF88_#)
Register
Name
9000
ETHCON1
9010
ETHCON2
9020
9030
9040
9050
9060
9070
9080
9090
90A0
ETHTXST
ETHRXST
ETHHT0
ETHHT1
ETHPMM0
ETHPMM1
ETHPMCS
ETHPMO
ETHRXFC
© 2009-2011 Microchip Technology Inc.
90D0
ETHIEN
ETHIRQ
Legend:
Note
1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
15:0
ON
FRZ
SIDL
—
—
—
TXRTS
RXEN
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
31:16
21/5
20/4
19/3
18/2
17/1
AUTOFC
—
—
MANFC
—
—
—
16/0
—
—
—
—
—
—
—
—
0000
—
—
—
—
0000
—
—
—
—
0000
RXBUFSZ<6:0>
BUFCDEC 0000
TXSTADDR<31:16>
15:0
0000
TXSTADDR<15:2>
31:16
RXSTADDR<31:16>
15:0
31:16
0000
0000
HT<63:32>
15:0
31:16
0000
0000
PMM<31:0>
15:0
31:16
0000
0000
PMM<63:32>
15:0
—
—
—
—
—
—
—
15:0
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
CRC
ERREN
CRC
OKEN
RUNT
ERREN
RUNTEN
UCEN
NOT
MEEN
MCEN
BCEN
0000
PMCS<15:0>
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
15:0
HTEN
MPEN
—
NOTPM
31:16
—
—
—
—
—
—
—
—
RXFWM<7:0>
15:0
—
—
—
—
—
—
—
—
RXEWM<7:0>
31:16
—
—
—
—
—
—
—
—
—
—
—
RX
BUSEIE
FW
MARKIE
RX
DONEIE
PK
TPENDIE
0000
0000
—
—
—
—
RX
ACTIE
—
TX
DONEIE
TX
ABORTIE
RX
BUFNAIE
15:0
—
TX
BUSEIE
—
—
—
EW
MARKIE
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
TXBUSE
RXBUSE
—
—
—
EWMARK
FWMARK
RXDONE
PKTPEND
RXACT
—
TXDONE
TXABORT
RXBUFNA
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
0000
0000
31:16
PMMODE<3:0>
0000
0000
PMO<15:0>
—
0000
0000
HT<31:0>
15:0
0000
0000
RXSTADDR<15:2>
31:16
31:16
22/6
PTV<15:0>
31:16
31:16
23/7
All Resets
Bit Range
Bits
90B0 ETHRXWM
90C0
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1)
—
0000
RX
0000
OVFLWIE
—
0000
RXOVFLW 0000
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
DS61156G-page 114
TABLE 4-47:
Virtual Address
(BF88_#)
Register
Name
90E0
ETHSTAT
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
31/15
30/14
29/13
28/12
27/11
26/10
25/9
24/8
31:16
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
31:16
ETH
9100
RXOVFLOW 15:0
—
—
—
—
—
—
—
9110
31:16
ETH
FRMTXOK 15:0
—
9120
31:16
ETH
SCOLFRM 15:0
—
9130
31:16
ETH
MCOLFRM 15:0
—
9140
31:16
ETH
FRMRXOK 15:0
—
31:16
—
9150
9160
ETH
FCSERR
23/7
22/6
21/5
20/4
—
BUSY
TXBUSY
RXBUSY
—
—
—
—
—
—
18/2
17/1
16/0
—
—
—
—
0000
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RXPAUSE
PASSALL
—
—
BUFCNT<7:0>
—
—
—
—
—
—
—
—
0000
FRMTXOKCNT<15:0>
—
—
—
—
—
—
—
—
SCOLFRMCNT<15:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
SOFT
RESET
SIM
RESET
—
—
RESET
RMCS
RESET
RFUN
RESET
TMCS
RESET
TFUN
—
—
—
31:16
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
EXCESS
DFR
BP
NOBKOFF
NOBKOFF
—
—
LONGPRE
PUREPRE
AUTOPAD
VLANPAD
PAD
ENABLE
CRC
ENABLE
—
—
—
DS61156G-page 115
EMAC1
CFG2
9220
EMAC1
IPGT
31:16
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
9230
EMAC1
IPGR
31:16
—
—
—
—
—
—
—
—
—
15:0
—
9240
EMAC1
CLRT
31:16
—
—
15:0
—
—
9250
EMAC1
MAXF
31:16
—
—
1:
2:
NB2BIPKTGP1<6:0>
—
—
—
—
—
CWINDOW<5:0>
—
—
—
0000
LOOPBACK TXPAUSE
—
—
15:0
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
—
—
—
—
—
—
—
—
—
—
—
—
0000
0C12
RETX<3:0>
—
0000
0012
NB2BIPKTGP2<6:0>
—
MACMAXF<15:0>
—
0000
RXENABLE 800D
B2BIPKTGP<6:0>
—
—
0000
—
—
0000
370F
—
0000
05EE
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
31:16
ALGNERRCNT<15:0>
9210
0000
0000
—
EMAC1
CFG1
0000
0000
FCSERRCNT<15:0>
—
0000
0000
FRMRXOKCNT<15:0>
—
0000
0000
MCOLFRMCNT<15:0>
—
0000
0000
31:16
ETH
ALGNERR 15:0
Legend:
0000
RXOVFLWCNT<15:0>
9200
Note
19/3
All Resets
Bits
Bit Range
© 2009-2011 Microchip Technology Inc.
TABLE 4-47:
Register
Name
© 2009-2011 Microchip Technology Inc.
Virtual Address
(BF88_#)
ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED)
9260
EMAC1
SUPP
9270
EMAC1
TEST
9280
EMAC1
MCFG
9290
EMAC1
MCMD
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SCAN
READ
0000
92A0
EMAC1
MADR
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0000
15:0
—
—
—
—
—
—
92B0
EMAC1
MWTD
31:16
—
—
—
—
—
—
—
—
—
—
—
92C0
EMAC1
MRDD
31:16
—
—
—
—
—
—
—
92D0
EMAC1
MIND
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15:0
—
—
—
—
—
—
—
—
—
—
—
—
LINKFAIL
NOTVALID
SCAN
9300
EMAC1
SA0(2)
31:16
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
9310
EMAC1
SA1(2)
31:16
—
—
—
9320
EMAC1
SA2(2)
31:16
—
—
—
Legend:
Note
1:
2:
31/15
30/14
29/13
28/12
27/11
26/10
25/9
31:16
—
—
—
15:0
—
—
—
—
—
—
—
RESET
RMII
—
31:16
—
—
15:0
—
—
—
—
—
—
—
—
31:16
—
15:0
RESET
MGMT
—
—
—
—
—
—
24/8
23/7
22/6
21/5
20/4
19/3
18/2
17/1
16/0
—
—
—
—
—
—
—
—
—
—
0000
—
SPEED
RMII
—
—
—
—
—
—
—
—
1000
—
—
—
—
—
—
—
—
—
—
—
0000
—
—
—
—
—
—
—
—
TESTBP
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PHYADDR<4:0>
—
—
—
—
15:0
—
—
—
—
—
—
15:0
CLKSEL<3:0>
—
NOPRE
—
—
—
REGADDR<4:0>
0100
—
—
15:0
—
—
—
—
—
—
—
STNADDR4<7:0>
—
—
—
—
—
—
—
—
STNADDR2<7:0>
x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
—
—
—
—
—
STNADDR1<7:0>
0000
MIIMBUSY 0000
xxxx
xxxx
STNADDR3<7:0>
—
0000
0000
STNADDR5<7:0>
—
0000
0000
STNADDR6<7:0>
—
0000
SCANINC 0020
MRDD<15:0>
15:0
15:0
—
TESTPAUSE SHRTQNTA 0000
MWTD<15:0>
—
All Resets
Bit Range
Bits
xxxx
xxxx
xxxx
xxxx
All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
Reset values default to the factory programmed value.
PIC32MX5XX/6XX/7XX
DS61156G-page 116
TABLE 4-47:
PIC32MX5XX/6XX/7XX
5.0
FLASH PROGRAM MEMORY
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 5. “Flash
Program Memory” (DS61121) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
PIC32MX5XX/6XX/7XX devices contain an internal
Flash program memory for executing user code. There
are three methods by which the user can program this
memory:
1.
2.
3.
Run-Time Self-Programming (RTSP)
EJTAG Programming
In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by software executing from either
Flash or RAM memory. Information about RTSP
techniques is available in Section 5. “Flash Program
Memory” (DS61121) in the “PIC32 Family Reference
Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32 Flash Programming Specification” (DS61145),
which can be downloaded from the Microchip web site.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 117
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 118
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
6.0
RESETS
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 7. “Resets”
(DS61118) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 6-1:
The Reset module combines all Reset sources and
controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:
•
•
•
•
•
•
POR: Power-on Reset
MCLR: Master Clear Reset pin
SWR: Software Reset
WDTR: Watchdog Timer Reset
BOR: Brown-out Reset
CMR: Configuration Mismatch Reset
A simplified block diagram of the Reset module is
illustrated in Figure 6-1.
SYSTEM RESET BLOCK DIAGRAM
MCLR
Glitch Filter
Sleep or Idle
WDTR
WDT
Time-out
Voltage
Regulator
Enabled
VDD
MCLR
Power-up
Timer
POR
Brown-out
Reset
BOR
SYSRST
VDD Rise
Detect
Configuration
Mismatch
Reset
Software Reset
© 2009-2011 Microchip Technology Inc.
CMR
SWR
DS61156G-page 119
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 120
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Interrupts”
(DS61108) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
PIC32MX5XX/6XX/7XX devices generate interrupt
requests in response to interrupt events from peripheral
modules. The interrupt control module exists externally
to the CPU logic and prioritizes the interrupt events
before presenting them to the CPU.
•
•
•
•
•
•
•
•
•
•
•
•
Up to 96 interrupt sources
Up to 64 interrupt vectors
Single and multi-vector mode operations
Five external interrupts with edge polarity control
Interrupt proximity timer
Module freeze in Debug mode
Seven user-selectable priority levels for each
vector
Four user-selectable subpriority levels within each
priority
Dedicated shadow set for user-selectable priority
level
Software can generate any interrupt
User-configurable interrupt vector table location
User-configurable interrupt vector spacing
A simplified block diagram of the Interrupt Controller
module is illustrated in Figure 7-1.
INTERRUPT CONTROLLER MODULE
Interrupt Requests
FIGURE 7-1:
The PIC32MX5XX/6XX/7XX interrupt module includes
the following features:
Vector Number
Interrupt Controller
Priority Level
CPU Core
Shadow Set Number
© 2009-2011 Microchip Technology Inc.
DS61156G-page 121
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION
Interrupt Source(1)
IRQ
Vector
Number
Interrupt Bit Location
Flag
Enable
Priority
Sub-Priority
Highest Natural Order Priority
CT – Core Timer Interrupt
0
0
IFS0<0>
IEC0<0>
IPC0<4:2>
IPC0<1:0>
CS0 – Core Software Interrupt 0
1
1
IFS0<1>
IEC0<1>
IPC0<12:10>
IPC0<9:8>
CS1 – Core Software Interrupt 1
2
2
IFS0<2>
IEC0<2>
IPC0<20:18>
IPC0<17:16>
INT0 – External Interrupt 0
3
3
IFS0<3>
IEC0<3>
IPC0<28:26>
IPC0<25:24>
T1 – Timer1
4
4
IFS0<4>
IEC0<4>
IPC1<4:2>
IPC1<1:0>
IC1 – Input Capture 1
5
5
IFS0<5>
IEC0<5>
IPC1<12:10>
IPC1<9:8>
OC1 – Output Compare 1
6
6
IFS0<6>
IEC0<6>
IPC1<20:18>
IPC1<17:16>
INT1 – External Interrupt 1
7
7
IFS0<7>
IEC0<7>
IPC1<28:26>
IPC1<25:24>
T2 – Timer2
8
8
IFS0<8>
IEC0<8>
IPC2<4:2>
IPC2<1:0>
IC2 – Input Capture 2
9
9
IFS0<9>
IEC0<9>
IPC2<12:10>
IPC2<9:8>
OC2 – Output Compare 2
10
10
IFS0<10>
IEC0<10>
IPC2<20:18>
IPC2<17:16>
INT2 – External Interrupt 2
11
11
IFS0<11>
IEC0<11>
IPC2<28:26>
IPC2<25:24>
T3 – Timer3
12
12
IFS0<12>
IEC0<12>
IPC3<4:2>
IPC3<1:0>
IC3 – Input Capture 3
13
13
IFS0<13>
IEC0<13>
IPC3<12:10>
IPC3<9:8>
OC3 – Output Compare 3
14
14
IFS0<14>
IEC0<14>
IPC3<20:18>
IPC3<17:16>
INT3 – External Interrupt 3
15
15
IFS0<15>
IEC0<15>
IPC3<28:26>
IPC3<25:24>
T4 – Timer4
16
16
IFS0<16>
IEC0<16>
IPC4<4:2>
IPC4<1:0>
IC4 – Input Capture 4
17
17
IFS0<17>
IEC0<17>
IPC4<12:10>
IPC4<9:8>
OC4 – Output Compare 4
18
18
IFS0<18>
IEC0<18>
IPC4<20:18>
IPC4<17:16>
INT4 – External Interrupt 4
19
19
IFS0<19>
IEC0<19>
IPC4<28:26>
IPC4<25:24>
T5 – Timer5
20
20
IFS0<20>
IEC0<20>
IPC5<4:2>
IPC5<1:0>
IC5 – Input Capture 5
21
21
IFS0<21>
IEC0<21>
IPC5<12:10>
IPC5<9:8>
OC5 – Output Compare 5
22
22
IFS0<22>
IEC0<22>
IPC5<20:18>
IPC5<17:16>
SPI1E – SPI1 Fault
23
23
IFS0<23>
IEC0<23>
IPC5<28:26>
IPC5<25:24>
SPI1RX – SPI1 Receive Done
24
23
IFS0<24>
IEC0<24>
IPC5<28:26>
IPC5<25:24>
SPI1TX – SPI1 Transfer Done
25
23
IFS0<25>
IEC0<25>
IPC5<28:26>
IPC5<25:24>
26
24
IFS0<26>
IEC0<26>
IPC6<4:2>
IPC6<1:0>
27
24
IFS0<27>
IEC0<27>
IPC6<4:2>
IPC6<1:0>
28
24
IFS0<28>
IEC0<28>
IPC6<4:2>
IPC6<1:0>
I2C1B – I2C1 Bus Collision Event
29
25
IFS0<29>
IEC0<29>
IPC6<12:10>
IPC6<9:8>
I2C1S – I2C1 Slave Event
30
25
IFS0<30>
IEC0<30>
IPC6<12:10>
IPC6<9:8>
I2C1M – I2C1 Master Event
31
25
IFS0<31>
IEC0<31>
IPC6<12:10>
IPC6<9:8>
U1E – UART1 Error
SPI3E – SPI3 Fault
I2C3B – I2C3 Bus Collision Event
U1RX – UART1 Receiver
SPI3RX – SPI3 Receive Done
I2C3S – I2C3 Slave Event
U1TX – UART1 Transmitter
SPI3TX – SPI3 Transfer Done
I2C3M – I2C3 Master Event
CN – Input Change Interrupt
32
26
IFS1<0>
IEC1<0>
IPC6<20:18>
IPC6<17:16>
AD1 – ADC1 Convert Done
33
27
IFS1<1>
IEC1<1>
IPC6<28:26>
IPC6<25:24>
Note 1:
Not all interrupt sources are available on all devices. See Table 1, Table 2 and Table 3 for the list of
available peripherals.
DS61156G-page 122
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Bit Location
IRQ
Vector
Number
Flag
Enable
Priority
Sub-Priority
PMP – Parallel Master Port
34
28
IFS1<2>
IEC1<2>
IPC7<4:2>
IPC7<1:0>
CMP1 – Comparator Interrupt
35
29
IFS1<3>
IEC1<3>
IPC7<12:10>
IPC7<9:8>
CMP2 – Comparator Interrupt
36
30
IFS1<4>
IEC1<4>
IPC7<20:18>
IPC7<17:16>
U3E – UART2A Error
SPI2E – SPI2 Fault
I2C4B – I2C4 Bus Collision Event
37
31
IFS1<5>
IEC1<5>
IPC7<28:26>
IPC7<25:24>
U3RX – UART2A Receiver
SPI2RX – SPI2 Receive Done
I2C4S – I2C4 Slave Event
38
31
IFS1<6>
IEC1<6>
IPC7<28:26>
IPC7<25:24>
U3TX – UART2A Transmitter
SPI2TX – SPI2 Transfer Done
IC4M – I2C4 Master Event
39
31
IFS1<7>
IEC1<7>
IPC7<28:26>
IPC7<25:24>
U2E – UART3A Error
SPI4E – SPI4 Fault
I2C5B – I2C5 Bus Collision Event
40
32
IFS1<8>
IEC1<8>
IPC8<4:2>
IPC8<1:0>
U2RX – UART3A Receiver
SPI4RX – SPI4 Receive Done
I2C5S – I2C5 Slave Event
41
32
IFS1<9>
IEC1<9>
IPC8<4:2>
IPC8<1:0>
U2TX – UART3A Transmitter
SPI4TX – SPI4 Transfer Done
IC5M – I2C5 Master Event
42
32
IFS1<10>
IEC1<10>
IPC8<4:2>
IPC8<1:0>
I2C2B – I2C2 Bus Collision Event
43
33
IFS1<11>
IEC1<11>
IPC8<12:10>
IPC8<9:8>
I2C2S – I2C2 Slave Event
44
33
IFS1<12>
IEC1<12>
IPC8<12:10>
IPC8<9:8>
Interrupt Source(1)
I2C2M – I2C2 Master Event
45
33
IFS1<13>
IEC1<13>
IPC8<12:10>
IPC8<9:8>
FSCM – Fail-Safe Clock Monitor
46
34
IFS1<14>
IEC1<14>
IPC8<20:18>
IPC8<17:16>
RTCC – Real-Time Clock and
Calendar
47
35
IFS1<15>
IEC1<15>
IPC8<28:26>
IPC8<25:24>
DMA0 – DMA Channel 0
48
36
IFS1<16>
IEC1<16>
IPC9<4:2>
IPC9<1:0>
DMA1 – DMA Channel 1
49
37
IFS1<17>
IEC1<17>
IPC9<12:10>
IPC9<9:8>
DMA2 – DMA Channel 2
50
38
IFS1<18>
IEC1<18>
IPC9<20:18>
IPC9<17:16>
DMA3 – DMA Channel 3
51
39
IFS1<19>
IEC1<19>
IPC9<28:26>
IPC9<25:24>
DMA4 – DMA Channel 4
52
40
IFS1<20>
IEC1<20>
IPC10<4:2>
IPC10<1:0>
DMA5 – DMA Channel 5
53
41
IFS1<21>
IEC1<21> IPC10<12:10>
DMA6 – DMA Channel 6
54
42
IFS1<22>
IEC1<22> IPC10<20:18> IPC10<17:16>
IPC10<9:8>
DMA7 – DMA Channel 7
55
43
IFS1<23>
IEC1<23> IPC10<28:26> IPC10<25:24>
FCE – Flash Control Event
56
44
IFS1<24>
IEC1<24>
USB – USB Interrupt
57
45
IFS1<25>
IEC1<25> IPC11<12:10>
CAN1 – Control Area Network 1
58
46
IFS1<26>
IEC1<26> IPC11<20:18> IPC11<17:16>
CAN2 – Control Area Network 2
59
47
IFS1<27>
IEC1<27> IPC11<28:26> IPC11<25:24>
ETH – Ethernet Interrupt
60
48
IFS1<28>
IEC1<28>
IPC12<4:2>
IPC12<1:0>
IC1E – Input Capture 1 Error
61
5
IFS1<29>
IEC1<29>
IPC1<12:10>
IPC1<9:8>
IC2E – Input Capture 2 Error
62
9
IFS1<30>
IEC1<30>
IPC2<12:10>
IPC2<9:8>
IC3E – Input Capture 3 Error
63
13
IFS1<31>
IEC1<31>
IPC3<12:10>
IPC3<9:8>
IC4E – Input Capture 4 Error
64
17
IFS2<0>
IEC2<0>
IPC4<12:10>
IPC4<9:8>
Note 1:
IPC11<4:2>
IPC11<1:0>
IPC11<9:8>
Not all interrupt sources are available on all devices. See Table 1, Table 2 and Table 3 for the list of
available peripherals.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 123
PIC32MX5XX/6XX/7XX
TABLE 7-1:
INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
Interrupt Bit Location
IRQ
Vector
Number
Flag
Enable
Priority
Sub-Priority
IC4E – Input Capture 5 Error
65
21
IFS2<1>
IEC2<1>
IPC5<12:10>
IPC5<9:8>
PMPE – Parallel Master Port Error
66
28
IFS2<2>
IEC2<2>
IPC7<4:2>
IPC7<1:0>
U4E – UART4 Error
67
49
IFS2<3>
IEC2<3>
IPC12<12:10>
IPC12<9:8>
U4RX – UART4 Receiver
68
49
IFS2<4>
IEC2<4>
IPC12<12:10>
IPC12<9:8>
U4TX – UART4 Transmitter
69
49
IFS2<5>
IEC2<5>
IPC12<12:10>
IPC12<9:8>
U6E – UART6 Error
70
50
IFS2<6>
IEC2<6>
IPC12<20:18> IPC12<17:16>
U6RX – UART6 Receiver
71
50
IFS2<7>
IEC2<7>
IPC12<20:18> IPC12<17:16>
U6TX – UART6 Transmitter
72
50
IFS2<8>
IEC2<8>
IPC12<20:18> IPC12<17:16>
IPC12<28:26> IPC12<25:24>
Interrupt Source(1)
U5E – UART5 Error
73
51
IFS2<9>
IEC2<9>
U5RX – UART5 Receiver
74
51
IFS2<10>
IEC2<10> IPC12<28:26> IPC12<25:24>
U5TX – UART5 Transmitter
75
51
IFS2<11>
IEC2<11> IPC12<28:26> IPC12<25:24>
(Reserved)
—
—
—
—
—
—
Lowest Natural Order Priority
Note 1:
Not all interrupt sources are available on all devices. See Table 1, Table 2 and Table 3 for the list of
available peripherals.
DS61156G-page 124
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
8.0
OSCILLATOR
CONFIGURATION
The PIC32MX5XX/6XX/7XX oscillator system has the
following modules and features:
• A total of four external and internal oscillator
options as clock sources
• On-Chip PLL with user-selectable input divider,
multiplier and output divider to boost operating
frequency on select internal and external
oscillator sources
• On-Chip user-selectable divisor postscaler on
select oscillator sources
• Software-controllable switching between
various clock sources
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and permits safe application recovery
or shutdown
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 6. “Oscillator”
(DS61112) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 8-1:
• Dedicated On-Chip PLL for USB peripheral
Figure 8-1shows the Oscillator module block diagram.
PIC32MX5XX/6XX/7XX FAMILY OSCILLATOR BLOCK DIAGRAM
USB PLL
UFIN
div x
OSC1
C1(3)
XTAL
C2(3)
XT, HS, EC
To Internal
Logic
4 MHz ≤FIN ≤5 MHz
FIN
div x
PLL
Enable
RS(1)
OSC2(4)
UFRCEN
UPLLEN
UFIN = 4 MHz
UPLLIDIV<2:0>
Primary Oscillator
(POSC)
RF(2)
USB Clock (48 MHz)
div 2
PLL x24
div 2
PLL Input Divider
FPLLIDIV<2:0>
ADC
FRC
Oscillator
8 MHz typical
COSC<2:0>
div y
div 16
Postscaler
LPRC
Oscillator
FRCDIV<2:0>
Peripherals
Postscaler
div x
PBCLK
PBDIV<1:0>
PLL Output Divider
PLLODIV<2:0>
PLL Multiplier
PLLMULT<2:0>
TUN<5:0>
XTPLL, HSPLL,
ECPLL, FRCPLL
FRC
CPU and Select Peripherals
SYSCLK
FRC/16
FRCDIV
LPRC
31.25 kHz typical
Secondary Oscillator (SOSC)
SOSCO
32.768 kHz
SOSCEN and FSOSCEN
1.
2.
3.
4.
Clock Control Logic
Fail-Safe
Clock
Monitor
SOSCI
Notes:
SOSC
A series resistor, RS, may be required for AT strip cut crystals.
The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ.
Refer to Section 6. “Oscillator ” (DS61112) in the “PIC32 Family
Reference Manual” for help in determining the best oscillator components.
The PBCLK out is available on the OSC2 pin in certain clock modes.
© 2009-2011 Microchip Technology Inc.
FSCM INT
FSCM Event
NOSC<2:0>
COSC<2:0>
FSCMEN<1:0>
OSWEN
WDT, PWRT
Timer1, RTCC
DS61156G-page 125
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 126
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PREFETCH CACHE
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 9-1:
BMX/CPU
9.1
•
•
•
•
•
•
•
•
Features
16 fully associative lockable cache lines
16-byte cache lines
Up to four cache lines allocated to data
Two cache lines with address mask to hold
repeated instructions
Pseudo LRU replacement policy
All cache lines are software writable
16-byte parallel memory fetch
Predictive instruction prefetch
A simplified block diagram of the Prefetch Cache
module is illustrated in Figure 9-1.
PREFETCH CACHE MODULE BLOCK DIAGRAM
FSM
CTRL
Tag Logic
CTRL
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
Cache Line
Bus Ctrl
BMX/CPU
9.0
Cache Ctrl
Prefetch Ctrl
Cache
Line
Address
Encode
Hit LRU
Miss LRU
RDATA
Hit Logic
PreFetch
Prefetch
Pre-Fetch
CTRL
RDATA
PreFetch
Prefetch
Pre-Fetch
Tag
PFM
© 2009-2011 Microchip Technology Inc.
DS61156G-page 127
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 128
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
10.0
DIRECT MEMORY ACCESS
(DMA) CONTROLLER
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 31. “Direct
Memory Access (DMA) Controller”
(DS61117) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC32 Direct Memory Access (DMA) controller is a
bus master module useful for data transfers between
different devices without CPU intervention. The source
and destination of a DMA transfer can be any of the
memory mapped modules existent in the PIC32 (such
as Peripheral Bus (PBUS) devices: SPI, UART, PMP,
etc.) or memory itself.
Following are some of the key features of the DMA
controller module:
• Four identical channels, each featuring:
- Auto-increment source and destination
address registers
- Source and destination pointers
- Memory to memory and memory to
peripheral transfers
FIGURE 10-1:
INT Controller
Peripheral Bus
• Automatic word-size detection:
- Transfer granularity, down to byte level
- Bytes need not be word-aligned at source
and destination
• Fixed priority channel arbitration
• Flexible DMA channel operating modes:
- Manual (software) or automatic (interrupt)
DMA requests
- One-Shot or Auto-Repeat Block Transfer
modes
- Channel-to-channel chaining
• Flexible DMA requests:
- A DMA request can be selected from any of
the peripheral interrupt sources
- Each channel can select any (appropriate)
observable interrupt as its DMA request
source
- A DMA transfer abort can be selected from
any of the peripheral interrupt sources
- Pattern (data) match transfer termination
• Multiple DMA channel status interrupts:
- DMA channel block transfer complete
- Source empty or half empty
- Destination full or half full
- DMA transfer aborted due to an external
event
- Invalid DMA address generated
• DMA debug support features:
- Most recent address accessed by a DMA
channel
- Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable
DMA BLOCK DIAGRAM
System IRQ
Address Decoder
SE
Channel 0 Control
I0
Channel 1 Control
I1
L
Y
Bus Interface
Device Bus + Bus Arbitration
I2
Global Control
(DMACON)
Channel n Control
In
SE
L
Channel Priority
Arbitration
© 2009-2011 Microchip Technology Inc.
DS61156G-page 129
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 130
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
11.0
USB ON-THE-GO (OTG)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS61126) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Universal Serial Bus (USB) module contains
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded host, full-speed
device or OTG implementation with a minimum of
external components. This module in Host mode is
intended for use as an embedded host and therefore
does not implement a UHCI or OHCI controller.
The USB module consists of the clock generator, the
USB voltage comparators, the transceiver, the Serial
Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32 USB OTG
module is presented in Figure 11-1.
© 2009-2011 Microchip Technology Inc.
The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on
the VBUS pin to determine the state of the bus. The
transceiver provides the analog translation between
the USB bus and the digital logic. The SIE is a state
machine that transfers data to and from the endpoint
buffers and generates the hardware protocol for data
transfers. The USB DMA controller transfers data
between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the
need for external signaling components. The register
interface allows the CPU to configure and
communicate with the module.
The PIC32 USB module includes the following
features:
•
•
•
•
•
•
•
•
•
USB Full-speed support for host and device
Low-speed host support
USB OTG support
Integrated signaling resistors
Integrated analog comparators for VBUS
monitoring
Integrated USB transceiver
Transaction handshaking performed by hardware
Endpoint buffering anywhere in system RAM
Integrated DMA to access system RAM and Flash
Note:
The implementation and use of the USB
specifications, as well as other third party
specifications or technologies, may
require licensing; including, but not limited
to, USB Implementers Forum, Inc. (also
referred to as USB-IF). The user is fully
responsible
for
investigating
and
satisfying any applicable licensing
obligations.
DS61156G-page 131
PIC32MX5XX/6XX/7XX
FIGURE 11-1:
PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM
USBEN
FRC
Oscillator
8 MHz Typical
USB Suspend
CPU Clock Not POSC
Sleep
TUN<5:0>(4)
Primary Oscillator
(POSC)
Div x
OSC1
UFIN(5)
PLL
UPLLEN(6)
UPLLIDIV(6)
USB Suspend
OSC2
(PB Out)(1)
Div 2
UFRCEN(3)
To Clock Generator for Core and Peripherals
Sleep or Idle
USB Module
SRP Charge
Bus
SRP Discharge
USB
Voltage
Comparators
48 MHz USB Clock(7)
Full Speed Pull-up
D+(2)
Registers
and
Control
Interface
Host Pull-down
SIE
Transceiver
Low Speed Pull-up
D-(2)
DMA
System
RAM
Host Pull-down
ID Pull-up
ID(8)
VBUSON(8)
Transceiver Power 3.3V
VUSB
Note 1:
2:
3:
4:
5:
6:
7:
8:
PB clock is only available on this pin for select EC modes.
Pins can be used as digital inputs when USB is not enabled.
This bit field is contained in the OSCCON register.
This bit field is contained in the OSCTRM register.
USB PLL UFIN requirements: 4 MHz.
This bit field is contained in the DEVCFG2 register.
A 48 MHz clock is required for proper USB operation.
Pins can be used as GPIO when the USB module is disabled.
DS61156G-page 132
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
12.0
I/O PORTS
General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 12. “I/O Ports”
(DS61120) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
• Individual input pin weak pull-up enable/disable
• Monitor selective inputs and generate interrupt
when change in pin state is detected
• Operation during CPU Sleep and Idle modes
• Fast bit manipulation using CLR, SET and INV
registers
Figure 12-1 illustrates a block diagram of a typical
multiplexed I/O port.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 12-1:
BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE
Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC
Data Bus
D
SYSCLK
Q
ODC
CK
EN Q
WR ODC
1
RD TRIS
0
0
I/O Cell
1
D
Q
1
TRIS
CK
EN Q
WR TRIS
0
Output Multiplexers
D
Q
I/O Pin
LAT
CK
EN Q
WR LAT
WR PORT
RD LAT
1
RD PORT
0
Sleep
Q
Q
D
CK
Q
Q
D
CK
SYSCLK
Synchronization
Peripheral Input
Legend:
Note:
R
Peripheral Input Buffer
R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure
for any specific port/peripheral combination may be different than it is shown here.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 133
PIC32MX5XX/6XX/7XX
12.1
Parallel I/O (PIO) Ports
All port pins have three registers (TRIS, LAT and
PORT) that are directly associated with their operation.
TRIS is a Data Direction or Tri-State Control register
that determines whether a digital pin is an input or an
output. Setting a TRISx register bit = 1, configures the
corresponding I/O pin as an input; setting a TRISx
register bit = 0, configures the corresponding I/O pin as
an output. All port I/O pins are defined as inputs after a
device Reset. Certain I/O pins are shared with analog
peripherals and default to analog inputs after a device
Reset.
PORT is a register used to read the current state of the
signal applied to the port I/O pins. Writing to a PORTx
register performs a write to the port’s latch, LATx
register, latching the data to the port’s I/O pins.
LAT is a register used to write data to the port I/O pins.
The LATx Latch register holds the data written to either
the LATx or PORTx registers. Reading the LATx Latch
register reads the last value written to the
corresponding PORT or Latch register.
Not all port I/O pins are implemented on some devices,
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros.
12.1.1
CLR, SET AND INV REGISTERS
Every I/O module register has a corresponding CLR
(clear), SET (set) and INV (invert) register designed to
provide fast atomic bit manipulations. As the name of
the register implies, a value written to a SET, CLR or
INV register effectively performs the implied operation,
but only on the corresponding base register and only
bits specified as ‘1’ are modified. Bits specified as ‘0’
are not modified.
Reading SET, CLR and INV registers returns undefined
values. To see the affects of a write operation to a SET,
CLR or INV register, the base register must be read.
Note:
12.1.2
The maximum input voltage allowed on the input pins
is the same as the maximum VIH specification. Refer to
Section 31.0 “Electrical Characteristics” for VIH
specification details.
Note:
12.1.3
12.1.4
DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the
corresponding TRIS register bits = 0. When configured
as digital outputs, these pins are CMOS drivers or can
be configured as open-drain outputs by setting the
corresponding bits in the Open-Drain Configuration
(ODCx) register.
The open-drain feature allows generation of outputs
higher than VDD (e.g., 5V) on any desired 5V tolerant
pins by using external pull-up resistors. The maximum
open-drain voltage allowed is the same as the
maximum VIH specification.
See the “Pin Diagrams” section for the available pins
and their functionality.
12.1.5
DIGITAL INPUTS
12.1.6
DS61156G-page 134
ANALOG INPUTS
Certain pins can be configured as analog inputs used
by the ADC and comparator modules. Setting the
corresponding bits in the AD1PCFG register = 0
enables the pin as an analog input pin and must have
the corresponding TRIS bit set = 1 (input). If the TRIS
bit is cleared = 0 (output), the digital output level (VOH
or VOL) will be converted. Any time a port I/O pin is
configured as analog, its digital input is disabled and
the corresponding PORTx register bit will read ‘0’. The
AD1PCFG register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
Using a PORTxINV register to toggle a bit
is recommended because the operation is
performed in hardware atomically, using
fewer instructions, as compared to the
traditional read-modify-write method
shown below:
PORTC ^ = 0x0001;
Pins are configured as digital inputs by setting the
corresponding TRIS register bits = 1. When configured
as inputs, they are either TTL buffers or Schmitt
Triggers. Several digital pins share functionality with
analog inputs and default to the analog inputs at POR.
Setting the corresponding bit in the AD1PCFG
register = 1 enables the pin as a digital pin.
Analog levels on any pin that is defined as
a digital input (including the ANx pins)
may cause the input buffer to consume
current that exceeds the device
specifications.
ANALOG OUTPUTS
Certain pins can be configured as analog outputs, such
as the CVREF output voltage used by the comparator
module. Configuring the comparator reference module
to provide this output will present the analog output
voltage on the pin, independent of the TRIS register
setting for the corresponding pin.
INPUT CHANGE NOTIFICATION
The input change notification function of the I/O ports
(CNx) allows devices to generate interrupt requests in
response to change-of-state on selected pin.
Each CNx pin also has a weak pull-up, which acts as a
current source connected to the pin. The pull-ups are
enabled by setting the corresponding bit in the CNPUE
register.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
13.0
TIMER1
This family of PIC32 devices features one
synchronous/asynchronous 16-bit timer that can operate
as a free-running interval timer for various timing applications and counting external events. This timer can also
be used with the Low-Power Secondary Oscillator
(SOSC) for Real-Time Clock (RTC) applications. The
following modes are supported:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
•
•
•
•
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
13.1
Additional Supported Features
• Selectable clock prescaler
• Timer operation during CPU Idle and Sleep mode
• Fast bit manipulation using CLR, SET and INV
registers
• Asynchronous mode can be used with the SOSC
to function as a Real-Time Clock (RTC)
A simplified block diagram of the Timer1 module is
illustrated in Figure 13-1.
TIMER1 BLOCK DIAGRAM(1)
FIGURE 13-1:
PR1
Equal
16-bit Comparator
TSYNC (T1CON<2>)
1
Reset
T1IF
Event Flag
Sync
TMR1
0
0
1
Q
TGATE (T1CON<7>)
D
Q
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
SOSCO/T1CK
x1
SOSCEN
SOSCI
Gate
Sync
PBCLK
10
00
Prescaler
1, 8, 64, 256
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 135
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 136
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
14.0
TIMER2/3, TIMER4/5
Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
The 32-bit timers can operate in three modes:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 14. “Timers”
(DS61105) of the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
• Synchronous internal 32-bit timer
• Synchronous internal 32-bit gated timer
• Synchronous external 32-bit timer
Note:
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
14.1
In this chapter, references to registers,
TxCON, TMRx and PRx, use ‘x’ to represent Timer2 through 5 in 16-bit modes. In
32-bit modes, ‘x’ represents Timer2 or 4;
‘y’ represents Timer3 or 5.
Additional Supported Features
• Selectable clock prescaler
• Timers operational during CPU idle
• Time base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• ADC event trigger (Timer3 only)
• Fast bit manipulation using CLR, SET and INV
registers
This family of PIC32 devices features four synchronous
16-bit timers (default) that can operate as a freerunning interval timer for various timing applications
and counting external events. The following modes are
supported:
• Synchronous internal 16-bit timer
• Synchronous internal 16-bit gated timer
• Synchronous external 16-bit timer
FIGURE 14-1:
TIMER2/3, 4/5 BLOCK DIAGRAM (16-BIT)
Sync
TMRx
ADC Event
Trigger(1)
Equal
Comparator x 16
PRx
Reset
TxIF
Event Flag
0
1
TGATE (TxCON<7>)
Q
TGATE (TxCON<7>)
D
Q
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
Note 1: ADC event trigger is available on Timer3 only.
2: TxCK pins are not available on 64-pin devices.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 137
PIC32MX5XX/6XX/7XX
FIGURE 14-2:
TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1)
Reset
TMRy
MS Half Word
ADC Event
Trigger(3)
Equal
Sync
LS Half Word
32-bit Comparator
PRy
TyIF Event
Flag
TMRx
PRx
0
1
TGATE (TxCON<7>)
Q
D
TGATE (TxCON<7>)
Q
TCS (TxCON<1>)
ON (TxCON<15>)
TxCK(2)
x1
Gate
Sync
PBCLK
10
00
Prescaler
1, 2, 4, 8, 16,
32, 64, 256
3
TCKPS (TxCON<6:4>)
Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use
of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is available only on the Timer2/3 pair.
DS61156G-page 138
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
15.0
INPUT CAPTURE
1.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 15. “Input
Capture” (DS61122) of the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2.
3.
4.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Input Capture module is useful in applications
requiring frequency (period) and pulse measurement.
The Input Capture module captures the 16-bit or 32-bit
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause
capture events:
FIGURE 15-1:
Simple capture event modes
- Capture timer value on every falling edge of
input at ICx pin
- Capture timer value on every rising edge of
input at ICx pin
Capture timer value on every edge (rising and
falling)
Capture timer value on every edge (rising and
falling), specified edge first.
Prescaler capture event modes
- Capture timer value on every 4th rising
edge of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select between one of
two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
form a 32-bit timer. The selected timer can use either
an internal or external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
Interrupt optionally generated after 1, 2, 3 or 4
buffer locations are filled
• Input capture can also be used to provide
additional sources of external interrupts
INPUT CAPTURE BLOCK DIAGRAM
ICx Input
Timer3 Timer2
ICTMR
0
1
C32
FIFO Control
ICxBUF<31:16>
Prescaler
1, 4, 16
ICM<2:0>
ICxBUF<15:0>
Edge Detect
ICM<2:0>
FEDGE
ICBNE
ICOV
ICxCON
ICI<1:0>
Interrupt
Event
Generation
Data Space Interface
Interrupt
© 2009-2011 Microchip Technology Inc.
Peripheral Data Bus
DS61156G-page 139
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 140
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
16.0
OUTPUT COMPARE
The Output Compare module (OCMP) is used to
generate a single pulse or a train of pulses in response
to selected time base events. For all modes of
operation, the OCMP module compares the values
stored in the OCxR and/or the OCxRS registers to the
value in the selected timer. When a match occurs, the
OCMP module generates an event based on the
selected mode of operation.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 16. “Output
Compare” (DS61111) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
The following are some of the key features:
• Multiple Output Compare Modules in a device
• Programmable interrupt generation on compare
event
• Single and Dual Compare modes
• Single and continuous output pulse generation
• Pulse-Width Modulation (PWM) mode
• Hardware-based PWM Fault detection and
automatic output disable
• Programmable selection of 16-bit or 32-bit time
bases
• Can operate from either of two available 16-bit
time bases or a single 32-bit time base
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 16-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF(1)
OCxRS(1)
Output
Logic
OCxR(1)
3
OCM<2:0>
Mode Select
Comparator
0
16
OCTSEL
1
0
S
R
Output
Enable
Q
OCx(1)
Output Enable
Logic
OCFA or OCFB(2)
1
16
TMR Register Inputs
from Time Bases(3)
Period Match Signals
from Time Bases(3)
Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 141
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 142
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
17.0
SERIAL PERIPHERAL
INTERFACE (SPI)
The SPI module is a synchronous serial interface that
is useful for communicating with external peripherals
and other microcontroller devices. These peripheral
devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters, etc. The
PIC32 SPI module is compatible with Motorola® SPI
and SIOP interfaces.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 23. “Serial
Peripheral Interface (SPI)” (DS61106) in
the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
Following are some of the key features of this module:
•
•
•
•
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
•
•
•
•
FIGURE 17-1:
Master and Slave modes support
Four different clock formats
Enhanced Framed SPI protocol support
User-configurable 8-bit, 16-bit and 32-bit data
width
Separate SPI FIFO buffers for receive and
transmit
- FIFO buffers act as 4/8/16-level deep FIFOs
based on 32/16/8-bit data width
Programmable interrupt event on every 8-bit,
16-bit and 32-bit data transfer
Operation during CPU Sleep and Idle mode
Fast bit manipulation using CLR, SET and INV
registers
SPI MODULE BLOCK DIAGRAM
Internal
Data Bus
SPIxBUF
Read
Write
SPIxRXB FIFO
FIFOs Share Address SPIxBUF
SPIxTXB FIFO
Transmit
Receive
SPIxSR
SDIx
bit 0
SDOx
SSx/FSYNC
Slave Select
and Frame
Sync Control
Shift
Control
Clock
Control
Edge
Select
SCKx
Baud Rate
Generator
PBCLK
Enable Master Clock
Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 143
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 144
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
18.0
INTER-INTEGRATED
CIRCUIT™ (I2C™)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 24. “InterIntegrated Circuit™ (I2C™)” (DS61116)
in the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
© 2009-2011 Microchip Technology Inc.
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard. Figure 18-1 illustrates the
I2C module block diagram.
Each I2C module has a 2-pin interface: the SCLx pin is
clock and the SDAx pin is data.
Each I2C module offers the following key features:
• I2C interface supporting both master and slave
operation
• I2C Slave mode supports 7-bit and 10-bit addressing
• I2C Master mode supports 7-bit and 10-bit
addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I2C port can
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus
collision and arbitrates accordingly
• Provides support for address bit masking
DS61156G-page 145
PIC32MX5XX/6XX/7XX
FIGURE 18-1:
I2C™ BLOCK DIAGRAM
Internal
Data Bus
I2CxRCV
SCLx
Read
Shift
Clock
I2CxRSR
LSB
SDAx
Address Match
Match Detect
Write
I2CxMSK
Write
Read
I2CxADD
Read
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
Control Logic
I2CxSTAT
Collision
Detect
Read
Write
I2CxCON
Acknowledge
Generation
Read
Clock
Stretching
Write
I2CxTRN
LSB
Read
Shift Clock
Reload
Control
BRG Down Counter
Write
I2CxBRG
Read
PBCLK
DS61156G-page 146
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
19.0
UNIVERSAL ASYNCHRONOUS
RECEIVER TRANSMITTER
(UART)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 21. “Universal
Asynchronous Receiver Transmitter
(UART)” (DS61107) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The UART module is one of the serial I/O modules
available in PIC32MX5XX/6XX/7XX family devices.
The UART is a full-duplex, asynchronous communication channel that communicates with peripheral
devices and personal computers through protocols,
such as RS-232, RS-485, LIN 1.2 and IrDA®. The
module also supports the hardware flow control option,
with UxCTS and UxRTS pins, and also includes an
IrDA encoder and decoder.
FIGURE 19-1:
The primary features of the UART module are:
•
•
•
•
•
•
•
•
•
•
•
•
•
Full-duplex, 8-bit or 9-bit data transmission
Even, Odd or No Parity options (for 8-bit data)
One or two Stop bits
Hardware auto-baud feature
Hardware flow control option
Fully integrated Baud Rate Generator (BRG) with
16-bit prescaler
Baud rates ranging from 76 bps to 20 Mbps at 80
MHz
8-level deep First-In-First-Out (FIFO) transmit
data buffer
8-level deep FIFO receive data buffer
Parity, framing and buffer overrun error detection
Support for interrupt-only on address detect
(9th bit = 1)
Separate transmit and receive interrupts
Loopback mode for diagnostic support
• LIN 1.2 Protocol support
• IrDA encoder and decoder with 16x baud clock
output for external IrDA encoder/decoder support
Figure 19-1 illustrates a simplified block diagram of the
UART.
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
Hardware Flow Control
Note:
BCLKx
UxRTS
UxCTS
UARTx Receiver
UxRX
UARTx Transmitter
UxTX
Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 147
PIC32MX5XX/6XX/7XX
Figure 19-2 and Figure 19-3 illustrate typical receive
and transmit timing for the UART module.
FIGURE 19-2:
UART RECEPTION
Char 1
Char 2-4
Char 5-10
Char 11-13
Read to
UxRXREG
UxRX
Start 1
Stop
Start 2
Start 5
Stop 4
Stop 10 Start 11
Stop 13
RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software
UxRXIF
URXISEL = 01
UxRXIF
URXISEL = 10
FIGURE 19-3:
TRANSMISSION (8-BIT OR 9-BIT DATA)
8 into TxBUF
Write to
UxTXREG
TSR
Pull from Buffer
BCLK/16
(Shift Clock)
UxTX
Start
Bit 0
Bit 1
Stop
Start
Bit 1
UxTXIF
UTXISEL = 00
UxTXIF
UTXISEL = 01
UxTXIF
UTXISEL = 10
DS61156G-page 148
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
20.0
PARALLEL MASTER PORT
(PMP)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 13. “Parallel
Master Port (PMP)” (DS61128) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PMP is a parallel 8-bit/16-bit input/output module
specifically designed to communicate with a wide
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and
microcontrollers. Because the interface to parallel
peripherals varies significantly, the PMP module is
highly configurable. Figure 20-1 shows the PMP
module pinout and its connections to external devices.
FIGURE 20-1:
Key features of the PMP module include:
•
•
•
•
•
•
•
•
•
•
•
•
8-bit, 16-bit interface
Up to 16 programmable address lines
Up to two Chip Select lines
Programmable strobe options
- Individual read and write strobes, or
- Read/write strobe with enable strobe
Address auto-increment/auto-decrement
Programmable address/data multiplexing
Programmable polarity on control signals
Parallel Slave Port support
- Legacy addressable
- Address support
- 4-byte deep auto-incrementing buffer
Programmable wait states
Operates during CPU Sleep and Idle modes
Fast bit manipulation using CLR, SET and INV
registers
Freeze option for in-circuit debugging
Note:
On 64-pin devices, the PMD<15:8> data
pins are not available.
PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES
Address Bus
Data Bus
PIC32MX5XX/6XX/7XX
Parallel
Master Port
Control Lines
PMA<0>
PMALL
PMA<1>
PMALH
Flash
EEPROM
SRAM
Up to 16-bit Address
PMA<13:2>
PMA<14>
PMCS1
PMA<15>
PMCS2
PMRD
PMRD/PMWR
PMWR
PMENB
PMD<7:0>
PMD<15:8>(1)
Note 1:
Microcontroller
LCD
FIFO
Buffer
16/8-bit Data (with or without multiplexed addressing)
On 64-pin devices, data pins, PMD<15:8>, are not available in 16-bit Master modes.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 149
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 150
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
21.0
REAL-TIME CLOCK AND
CALENDAR (RTCC)
Following are some of the key features of this module:
•
•
•
•
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 29. “Real-Time
Clock
and
Calendar
(RTCC)”
(DS61125) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
•
•
•
•
•
•
•
•
•
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC32 RTCC module is intended for applications
in which accurate time must be maintained for
extended periods of time with minimal or no CPU
intervention.
Low-power
optimization
provides
extended battery lifetime while keeping track of time.
A simplified block diagram of the RTCC module is
illustrated in Figure 21-1.
FIGURE 21-1:
•
•
•
•
Time: hours, minutes and seconds
24-hour format (military time)
Visibility of one-half second period
Provides calendar: Weekday, date, month and
year
Alarm intervals are configurable for half of a
second, one second, 10 seconds, one minute, 10
minutes, one hour, one day, one week, one month
and one year
Alarm repeat with decrementing counter
Alarm with indefinite repeat: Chime
Year range: 2000 to 2099
Leap year correction
BCD format for smaller firmware overhead
Optimized for long-term battery operation
Fractional second synchronization
User calibration of the clock crystal frequency with
auto-adjust
Calibration range: ±0.66 seconds error per month
Calibrates up to 260 ppm of crystal error
Requirements: External 32.768 kHz clock crystal
Alarm pulse or seconds clock output on
RTCC pin
RTCC BLOCK DIAGRAM
32.768 kHz Input
from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s
YEAR, MTH, DAY
RTCVAL
RTCC Timer
Alarm
Event
WKDAY
HR, MIN, SEC
Comparator
MTH, DAY
Compare Registers
with Masks
ALRMVAL
WKDAY
HR, MIN, SEC
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin
RTCOE
© 2009-2011 Microchip Technology Inc.
DS61156G-page 151
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 152
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
22.0
10-BIT ANALOG-TO-DIGITAL
CONVERTER (ADC)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 17. “10-bit
Analog-to-Digital Converter (ADC)”
(DS61104) in the “PIC32 Family
Reference Manual”, which is available
from
the
Microchip
web
site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital
Converter (ADC) includes the following features:
• Successive Approximation Register (SAR)
conversion
• Up to 1 Msps conversion speed
• Up to 16 analog input pins
• External voltage reference input pins
FIGURE 22-1:
• One unipolar, differential Sample and Hold
Amplifier (SHA)
• Automatic Channel Scan mode
• Selectable conversion trigger source
• 16-word conversion result buffer
• Selectable buffer fill modes
• Eight conversion result format options
• Operation during CPU Sleep and Idle modes
A block diagram of the 10-bit ADC is illustrated in
Figure 22-1. The 10-bit ADC has up to 16 analog input
pins, designated AN0-AN15. In addition, there are two
analog input pins for external voltage reference
connections. These voltage reference inputs may be
shared with other analog input pins and may be
common to other analog module references.
The analog inputs are connected through two multiplexers (MUXs) to one SHA. The analog input MUXs
can be switched between two sets of analog inputs
between conversions. Unipolar differential conversions
are possible on all channels, other than the pin used as
the reference, using a reference input pin (see
Figure 22-1).
The Analog Input Scan mode sequentially converts
user-specified channels. A control register specifies
which analog input channels will be included in the
scanning sequence.
The 10-bit ADC is connected to a 16-word result buffer.
Each 10-bit result is converted to one of eight 32-bit
output formats when it is read from the result buffer.
ADC1 MODULE BLOCK DIAGRAM
VREF+(1)
AVDD
VREF-(1)
AVSS
VCFG<2:0>
AN0
ADC1BUF0
ADC1BUF1
AN15
S/H
Channel
Scan
VREFH
VREFL
ADC1BUF2
+
CH0SB<4:0>
CH0SA<4:0>
-
SAR ADC
CSCNA
AN1
ADC1BUFE
VREFL
ADC1BUFF
CH0NA
CH0NB
Alternate
Input Selection
Note
1:
VREF+ and VREF- inputs can be multiplexed with other analog inputs.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 153
PIC32MX5XX/6XX/7XX
FIGURE 22-2:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
ADRC
FRC
Div 2
1
TAD
ADCS<7:0>
0
8
TPB
ADC Conversion
Clock Multiplier
2, 4,..., 512
DS61156G-page 154
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
23.0
CONTROLLER AREA
NETWORK (CAN)
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 34. “Controller
Area Network (CAN)” (DS61154) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Controller Area Network (CAN) module supports
the following key features:
• Standards Compliance:
- Full CAN 2.0B compliance
- Programmable bit rate up to 1 Mbps
• Message Reception and Transmission:
- 32 message FIFOs
- Each FIFO can have up to 32 messages for a
total of 1024 messages
- FIFO can be a transmit message FIFO or a
receive message FIFO
- User-defined priority levels for message
FIFOs used for transmission
- 32 acceptance filters for message filtering
- Four acceptance filter mask registers for
message filtering
- Automatic response to remote transmit request
- DeviceNet™ addressing support
• Additional Features:
- Loopback, Listen All Messages and Listen
Only modes for self-test, system diagnostics
and bus monitoring
- Low-power operating modes
- CAN module is a bus master on the PIC32
system bus
- Use of DMA is not required
- Dedicated time-stamp timer
- Dedicated DMA channels
- Data-only Message Reception mode
Figure 23-1 illustrates the general structure of the CAN
module.
FIGURE 23-1:
PIC32 CAN MODULE BLOCK DIAGRAM
CxTX
32 Filters
4 Masks
CPU
CxRX
CAN Module
Up to 32 Message Buffers
System Bus
Message
Buffer Size
2 or 4 Words
System RAM
Message Buffer 31
Message Buffer 31
Message Buffer 31
Message Buffer 1
Message Buffer 1
Message Buffer 1
Message Buffer 0
Message Buffer 0
Message Buffer 0
FIFO1
FIFO31
FIFO0
CAN Message FIFO (up to 32 FIFOs)
© 2009-2011 Microchip Technology Inc.
DS61156G-page 155
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 156
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
24.0
ETHERNET CONTROLLER
Following are some of the key features of this module:
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 35. “Ethernet
Controller” (DS61155) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
•
•
•
•
•
•
•
•
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Ethernet controller is a bus master module that
interfaces with an off-chip Physical Layer (PHY) to
implement a complete Ethernet node in a system.
Figure 24-1 illustrates a block diagram of the Ethernet
controller.
ETHERNET CONTROLLER BLOCK DIAGRAM
TX
FIFO
FIGURE 24-1:
•
•
Supports 10/100 Mbps data transfer rates
Supports full-duplex and half-duplex operation
Supports RMII and MII PHY interface
Supports MIIM PHY management interface
Supports both manual and automatic flow control
RAM descriptor-based DMA operation for both
receive and transmit path
Fully configurable interrupts
Configurable receive packet filtering
- CRC check
- 64-byte pattern match
- Broadcast, multicast and unicast packets
- Magic Packet™
- 64-bit hash table
- Runt packet
Supports packet payload checksum calculation
Supports various hardware statistics counters
TX DMA
TX BM
TX Bus
Master
TX Function
TX Flow Control
System Bus
RX DMA
RX
FIFO
MII/RMII
IF
RX Flow
Control
RX BM
External
PHY
MAC
RX Bus
Master
RX Filter
RX Function
Checksum
Fast Peripheral
Bus
DMA
Control
Registers
Ethernet DMA
MIIM
IF
MAC Control
and
Configuration
Registers
Host IF
Ethernet Controller
© 2009-2011 Microchip Technology Inc.
DS61156G-page 157
PIC32MX5XX/6XX/7XX
Table 24-1, Table 24-2, Table 24-3 and Table 24-4
show four interfaces and the associated pins that can
be used with the Ethernet Controller.
TABLE 24-1:
MII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 1)
Pin Name
EMDC
Description
TABLE 24-3:
Pin Name
MII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 1, FETHIO = 0)(1)
Description
AEMDC
Management Clock
AEMDIO
Management I/O
AETXCLK
Transmit Clock
Management Clock
AETXEN
Transmit Enable
Transmit Data
Management I/O
AETXD0
ETXCLK
Transmit Clock
AETXD1
Transmit Data
ETXEN
Transmit Enable
AETXD2
Transmit Data
ETXD0
Transmit Data
AETXD3
Transmit Data
ETXD1
Transmit Data
AETXERR
Transmit Error
ETXD2
Transmit Data
AERXCLK
Receive Clock
ETXD3
Transmit Data
AERXDV
Receive Data Valid
ETXERR
Transmit Error
AERXD0
Receive Data
ERXCLK
Receive Clock
AERXD1
Receive Data
ERXDV
Receive Data Valid
AERXD2
Receive Data
ERXD0
Receive Data
AERXD3
Receive Data
ERXD1
Receive Data
AERXERR
Receive Error
ERXD2
Receive Data
AECRS
Carrier Sense
ERXD3
Receive Data
AECOL
ERXERR
Receive Error
Note 1:
ECRS
Carrier Sense
ECOL
Collision Indication
EMDIO
TABLE 24-2:
RMII MODE DEFAULT
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 1)
Pin Name
Description
EMDC
Management Clock
EMDIO
Management I/O
ETXEN
Transmit Enable
ETXD0
Transmit Data
ETXD1
Transmit Data
EREFCLK
Reference Clock
ECRSDV
Carrier Sense – Receive Data Valid
ERXD0
Receive Data
ERXD1
Receive Data
ERXERR
Receive Error
Note:
Collision Indication
MII Alternate Interface is not available on
64-pin devices.
TABLE 24-4:
Pin Name
RMII MODE ALTERNATE
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 0)
Description
AEMDC
Management Clock
AEMDIO
Management I/O
AETXEN
Transmit Enable
AETXD0
Transmit Data
AETXD1
Transmit Data
AEREFCLK
Reference Clock
AECRSDV
Carrier Sense – Receive Data Valid
AERXD0
Receive Data
AERXD1
Receive Data
AERXERR
Receive Error
Ethernet controller pins that are not used
by selected interface can be used by other
peripherals.
DS61156G-page 158
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
25.0
COMPARATOR
The Analog Comparator module contains two comparators that can be configured in a variety of ways.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this
data sheet, refer to Section 19.
“Comparator” (DS61110) in the “PIC32
Family Reference Manual”, which is
available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 25-1:
Following are some of the key features of this module:
• Selectable inputs available include:
- Analog inputs multiplexed with I/O pins
- On-chip internal absolute voltage reference
(IVREF)
- Comparator voltage reference (CVREF)
• Outputs can be Inverted
• Selectable interrupt generation
A block diagram of the Comparator module is
illustrated in Figure 25-1.
COMPARATOR BLOCK DIAGRAM
Comparator 1
CREF
ON
C1IN+(1)
CPOL
COUT (CM1CON<8>)
C1OUT (CMSTAT<0>)
CVREF(2)
C1OUT
CCH<1:0>
C1
C1IN-
COE
C1IN+
C2IN+
IVREF(2)
Comparator 2
CREF
ON
C2IN+
CPOL
COUT (CM2CON<8>)
C2OUT (CMSTAT<1>)
CVREF(2)
C2OUT
CCH<1:0>
C2
C2IN-
COE
C2IN+
C1IN+
IVREF(2)
Note 1:
2:
On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module,
and therefore, is not available as a comparator input.
Internally connected. See Section 26.0 “Comparator Voltage Reference (CVREF)”.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 159
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 160
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
26.0
COMPARATOR VOLTAGE
REFERENCE (CVREF)
The CVREF module is a 16-tap, resistor ladder network
that provides a selectable reference voltage. Although
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 20. “Comparator
Voltage Reference (CVREF)” (DS61109)
in the “PIC32 Family Reference Manual”,
which is available from the Microchip web
site (www.microchip.com/PIC32).
A block diagram of the module is illustrated in
Figure 26-1. The resistor ladder is segmented to
provide two ranges of voltage reference values and has
a power-down function to conserve power when the
reference is not being used. The module’s supply reference can be provided from either device VDD/VSS or an
external voltage reference. The CVREF output is available for the comparators and typically available for pin
output.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
FIGURE 26-1:
The comparator voltage reference has the following
features:
• High and low range selection
• Sixteen output levels available for each range
• Internally connected to comparators to conserve
device pins
• Output can be connected to a pin
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
BGSEL<1:0>(1)
1.2V
IVREF
0.6V
VREFSEL(1)
VREF+
AVDD
CVRSS = 1
CVRSRC
CVREF
8R
CVRSS = 0
CVR<3:0>
R
CVREN
R
R
16-to-1 MUX
R
16 Steps
R
CVREFOUT
CVROE (CVRCON<6>)
R
R
CVRR
VREFAVSS
8R
CVRSS = 1
CVRSS = 0
Note 1: This bit is not available on PIC32MX575/675/695/775 devices. On these devices CVREF is generated by the Register
network and IVREF is connected to 0.6V.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 161
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 162
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
27.0
POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 10. “PowerSaving Features” (DS61130) in the
“PIC32 Family Reference Manual”, which
is available from the Microchip web site
(www.microchip.com/PIC32).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
This section describes power-saving features for the
PIC32MX5XX/6XX/7XX family of devices. These
devices offer a total of nine methods and modes,
organized into two categories, that allow the user to
balance power consumption with device performance.
In all of the methods and modes described in this
section, power-saving is controlled by software.
27.1
Power-Saving with CPU Running
When the CPU is running, power consumption can be
controlled by reducing the CPU clock frequency,
lowering the PBCLK and by individually disabling
modules. These methods are grouped into the
following categories:
• FRC Run mode: the CPU is clocked from the FRC
clock source with or without postscalers.
• LPRC Run mode: the CPU is clocked from the
LPRC clock source.
• SOSC Run mode: the CPU is clocked from the
SOSC clock source.
In addition, the Peripheral Bus Scaling mode is available
where peripherals are clocked at the programmable
fraction of the CPU clock (SYSCLK).
27.2
CPU Halted Methods
The device supports two power-saving modes, Sleep
and Idle, both of which Halt the clock to the CPU. These
modes operate with all clock sources, as listed below:
• POSC Idle mode: the system clock is derived from
the POSC. The system clock source continues to
operate. Peripherals continue to operate, but can
optionally be individually disabled.
• FRC Idle mode: the system clock is derived from
the FRC with or without postscalers. Peripherals
continue to operate, but can optionally be
individually disabled.
• SOSC Idle mode: the system clock is derived from
the SOSC. Peripherals continue to operate, but
can optionally be individually disabled.
© 2009-2011 Microchip Technology Inc.
• LPRC Idle mode: the system clock is derived from
the LPRC. Peripherals continue to operate, but
can optionally be individually disabled. This is the
lowest power mode for the device with a clock
running.
• Sleep mode: the CPU, the system clock source
and any peripherals that operate from the system
clock source are Halted. Some peripherals can
operate in Sleep using specific clock sources.
This is the lowest power mode for the device.
27.3
Power-Saving Operation
Peripherals and the CPU can be halted or disabled to
further reduce power consumption.
27.3.1
SLEEP MODE
Sleep mode has the lowest power consumption of the
device power-saving operating modes. The CPU and
most peripherals are halted. Select peripherals can
continue to operate in Sleep mode and can be used to
wake the device from Sleep. See the individual
peripheral module sections for descriptions of
behavior in Sleep.
Sleep mode includes the following characteristics:
• The CPU is halted
• The system clock source is typically shutdown.
See Section 27.3.3 “Peripheral Bus Scaling
Method” for specific information.
• There can be a wake-up delay based on the
oscillator selection
• The Fail-Safe Clock Monitor (FSCM) does not
operate during Sleep mode
• The BOR circuit, if enabled, remains operative
during Sleep mode
• The WDT, if enabled, is not automatically cleared
prior to entering Sleep mode
• Some peripherals can continue to operate at
limited functionality in Sleep mode. These
peripherals include I/O pins that detect a change
in the input signal, WDT, ADC, UART and
peripherals that use an external clock input or the
internal LPRC oscillator (e.g., RTCC, Timer1 and
Input Capture).
• I/O pins continue to sink or source current in the
same manner as they do when the device is not in
Sleep
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption
DS61156G-page 163
PIC32MX5XX/6XX/7XX
The processor will exit, or ‘wake-up’, from Sleep on one
of the following events:
The processor will wake or exit from Idle mode on the
following events:
• On any interrupt from an enabled source that is
operating in Sleep. The interrupt priority must be
greater than the current CPU priority.
• On any form of device Reset
• On a WDT time-out
If the interrupt priority is lower than or equal to the
current priority, the CPU will remain Halted, but the
PBCLK will start running and the device will enter into
Idle mode.
• On any interrupt event for which the interrupt
source is enabled. The priority of the interrupt
event must be greater than the current priority of
the CPU. If the priority of the interrupt event is
lower than or equal to current priority of the CPU,
the CPU will remain Halted and the device will
remain in Idle mode.
• On any form of device Reset
• On a WDT time-out interrupt
27.3.2
27.3.3
IDLE MODE
In Idle mode, the CPU is Halted but the System Clock
(SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted.
Peripherals can be individually configured to Halt when
entering Idle by setting their respective SIDL bit.
Latency, when exiting Idle mode, is very low due to the
CPU oscillator source remaining active.
Note 1: Changing the PBCLK divider ratio
requires recalculation of peripheral timing. For example, assume the UART is
configured for 9600 baud with a PB clock
ratio of 1:1 and a POSC of 8 MHz. When
the PB clock divisor of 1:2 is used, the
input frequency to the baud clock is cut in
half; therefore, the baud rate is reduced
to 1/2 its former value. Due to numeric
truncation in calculations (such as the
baud rate divisor), the actual baud rate
may be a tiny percentage different than
expected. For this reason, any timing calculation required for a peripheral should
be performed with the new PB clock frequency instead of scaling the previous
value based on a change in the PB divisor
ratio.
2: Oscillator start-up and PLL lock delays
are applied when switching to a clock
source that was disabled and that uses a
crystal and/or the PLL. For example,
assume the clock source is switched from
POSC to LPRC just prior to entering Sleep
in order to save power. No oscillator startup delay would be applied when exiting
Idle. However, when switching back to
POSC, the appropriate PLL and/or
oscillator start-up/lock delays would be
applied.
PERIPHERAL BUS SCALING
METHOD
Most of the peripherals on the device are clocked using
the PBCLK. The peripheral bus can be scaled relative to
the SYSCLK to minimize the dynamic power consumed
by the peripherals. The PBCLK divisor is controlled by
PBDIV<1:0> (OSCCON<20:19>), allowing SYSCLK to
PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals
using PBCLK are affected when the divisor is changed.
Peripherals such as USB, interrupt controller, DMA, bus
matrix and prefetch cache are clocked directly from
SYSCLK. As a result, they are not affected by PBCLK
divisor changes.
Changing the PBCLK divisor affects:
• The CPU to peripheral access latency. The CPU
has to wait for next PBCLK edge for a read to
complete. In 1:8 mode, this results in a latency of
one to seven SYSCLKs.
• The power consumption of the peripherals. Power
consumption is directly proportional to the frequency at which the peripherals are clocked. The
greater the divisor, the lower the power consumed
by the peripherals.
To minimize dynamic power, the PB divisor should be
chosen to run the peripherals at the lowest frequency
that provides acceptable system performance. When
selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken
into account. For example, the UART peripheral may
not be able to achieve all baud rate values at some
PBCLK divider depending on the SYSCLK value.
The device enters Idle mode when the SLPEN bit
(OSCCON<4>) is clear and a WAIT instruction is
executed.
DS61156G-page 164
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
28.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 8. “Watchdog
Timer and Power-up Timer” (DS61114),
Section 24. “Configuration” (DS61124)
and Section 33. “Programming and
Diagnostics” (DS61129) in the “PIC32
Family Reference Manual” (DS61132),
which is available from the Microchip web
site (www.microchip.com/PIC32).
PIC32MX5XX/6XX/7XX devices include several
features intended to maximize application flexibility and
reliability and minimize cost through elimination of
external components. These are:
•
•
•
•
Flexible device configuration
Watchdog Timer (WDT)
Joint Test Action Group (JTAG) interface
In-Circuit Serial Programming™ (ICSP™)
28.1
Configuration Bits
The Configuration bits can be programmed using the
following registers to select various device
configurations.
•
•
•
•
•
DEVCFG0: Device Configuration Word 0
DEVCFG1: Device Configuration Word 1
DEVCFG2: Device Configuration Word 2
DEVCFG3: Device Configuration Word 3
DEVID: Device and Revision ID Register
© 2009-2011 Microchip Technology Inc.
DS61156G-page 165
PIC32MX5XX/6XX/7XX
REGISTER 28-1:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-0
r-1
r-1
R/P
r-1
r-1
r-1
R/P
—
—
—
CP
—
—
—
BWP
R/P
R/P
R/P
R/P
r-1
r-1
r-1
r-1
—
—
—
—
R/P
R/P
R/P
R/P
PWP<3:0>
PWP<7:4>
r-1
r-1
r-1
r-1
—
—
—
—
R/P
R/P
r-1
r-1
r-1
r-1
R/P
r-1
—
—
—
—
ICESEL
—
DEBUG<1:0>
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31
Reserved: Write ‘0’
bit 30-29 Reserved: Write ‘1’
bit 28
CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-25 Reserved: Write ‘1’
bit 24
BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-20 Reserved: Write ‘1’
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution. The PWP bits
represent the 1’s complement of the number of write-protected program Flash memory pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
•
•
•
01111111 = 0xBD07_FFFF
DS61156G-page 166
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-1:
DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 11-4
Reserved: Write ‘1’
bit 3
ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC2/PGED2 pair is used
0 = PGEC1/PGED1 pair is used
bit 2
Reserved: Write ‘1’
bit 1-0
DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled
10 = Debugger is enabled
01 = Reserved (same as ‘11’ setting)
00 = Reserved (same as ‘11’ setting)
© 2009-2011 Microchip Technology Inc.
DS61156G-page 167
PIC32MX5XX/6XX/7XX
REGISTER 28-2:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
R/P
R/P
R/P
R/P
R/P
R/P
R/P
r-1
r-1
FWDTEN
—
—
R/P
R/P
R/P
FCKSM<1:0>
WDTPS<4:0>
R/P
FPBDIV<1:0>
r-1
R/P
—
OSCIOFNC
R/P
R/P
r-1
R/P
r-1
r-1
IESO
—
FSOSCEN
—
—
POSCMOD<1:0>
R/P
R/P
FNOSC<2:0>
Legend:
R = Readable bit
W = Writable bit
P = Programmable bit
r = Reserved bit
U = Unimplemented bit
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-24 Reserved: Write ‘1’
bit 23
FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 22-21 Reserved: Write ‘1’
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled
Note 1:
Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
DS61156G-page 168
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-2:
DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
bit 11
Reserved: Write ‘1’
bit 10
OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output disabled
0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the
External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)
bit 9-8
POSCMOD<1:0>: Primary Oscillator Configuration bits
11 = Primary Oscillator disabled
10 = HS Oscillator mode selected
01 = XT Oscillator mode selected
00 = External Clock mode selected
bit 7
IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6
Reserved: Write ‘1’
bit 5
FSOSCEN: Secondary Oscillator Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 4-3
Reserved: Write ‘1’
bit 2-0
FNOSC<2:0>: Oscillator Selection bits
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
000 = Fast RC Oscillator (FRC)
Note 1:
Do not disable the POSC (POSCMOD = 11) when using this oscillator source.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 169
PIC32MX5XX/6XX/7XX
REGISTER 28-3:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG2: DEVICE CONFIGURATION WORD 2
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
—
—
—
R/P
R/P
R/P
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P
r-1
r-1
r-1
r-1
UPLLEN
—
—
—
—
r-1
R/P-1
R/P
R/P-1
—
Legend:
R = Readable bit
U = Unimplemented bit
FPLLMUL<2:0>
W = Writable bit
‘1’ = Bit is set
r-1
FPLLODIV<2:0>
R/P
R/P
R/P
UPLLIDIV<2:0>
R/P
—
R/P
R/P
FPLLIDIV<2:0>
P = Programmable bit
‘0’ = Bit is cleared
r = Reserved bit
x = Bit is unknown
bit 31-19 Reserved: Write ‘1’
bit 18-16 FPLLODIV<2:0>: Default Postscaler for PLL bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 15
UPLLEN: USB PLL Enable bit
1 = Disable and bypass USB PLL
0 = Enable USB PLL
bit 14-11 Reserved: Write ‘1’
bit 10-8 UPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
Reserved: Write ‘1’
bit 7
bit 6-4
FPLLMUL<2:0>: PLL Multiplier bits
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
bit 3
Reserved: Write ‘1’
FPLLIDIV<2:0>: PLL Input Divider bits
bit 2-0
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
DS61156G-page 170
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
REGISTER 28-4:
Bit
Range
31:24
23:16
15:8
7:0
DEVCFG3: DEVICE CONFIGURATION WORD 3
Bit
31/23/15/7
Bit
30/22/14/6
R/P
R/P
FVBUSONIO FUSBIDIO
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
r-1
r-1
r-1
R/P
R/P
R/P
—
—
—
FCANIO(1)
FETHIO(2)
FMIIEN(2)
R/P
R/P
R/P
r-1
r-1
r-1
r-1
r-1
—
—
—
—
—
R/P
R/P
R/P
R/P
R/P
FSRSSEL<2:0>
R/P
R/P
R/P
R/P
R/P
R/P
USERID<15:8>
R/P
R/P
R/P
R/P
R/P
USERID<7:0>
Legend:
R = Readable bit
U = Unimplemented bit
W = Writable bit
‘1’ = Bit is set
P = Programmable bit
‘0’ = Bit is cleared
r = Reserved bit
x = Bit is unknown
bit 31
FVBUSONIO: USB VBUS_ON Selection bit
1 = VBUSON pin is controlled by the USB module
0 = VBUSON pin is controlled by the port function
FUSBIDIO: USB USBID Selection bit
bit 30
1 = USBID pin is controlled by the USB module
0 = USBID pin is controlled by the port function
bit 29-27 Reserved: Write ‘1’
FCANIO: CAN I/O Pin Selection bit(1)
bit 26
1 = Default CAN I/O Pins
0 = Alternate CAN I/O Pins
FETHIO: Ethernet I/O Pin Selection bit(2)
bit 25
1 = Default Ethernet I/O Pins
0 = Alternate Ethernet I/O Pins
FMIIEN: Ethernet MII Enable bit(2)
bit 24
1 = MII is enabled
0 = RMII is enabled
bit 23-19 Reserved: Write ‘1’
bit 18-16 FSRSSEL<2:0>: SRS Select bits
111 = Assign Interrupt Priority 7 to a shadow register set
110 = Assign Interrupt Priority 6 to a shadow register set
•
•
•
001 = Assign Interrupt Priority 1 to a shadow register set
000 = All interrupt priorities are assigned to a shadow register set
bit 15-0 USERID<15:0>: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG
Note 1:
2:
This bit is Reserved and reads ‘1’ on PIC32MX664/675/695 devices.
This bit is Reserved and reads ‘1’ on PIC32MX534/564/575 devices.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 171
PIC32MX5XX/6XX/7XX
REGISTER 28-5:
Bit
Range
31:24
23:16
15:8
7:0
DEVID: DEVICE AND REVISION ID REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
R
R
R
R
R
VER<3:0>(1)
R
R
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
R
R
R
DEVID<27:24>(1)
R
R
R
R
R
R
R
R
R
R
R
R
DEVID<23:16>(1)
R
R
R
R
R
DEVID<15:8>(1)
R
R
R
R
R
DEVID<7:0>(1)
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-28 VER<3:0>: Revision Identifier bits(1)
bit 27-0
DEVID<27:0>: Device ID(1)
Note 1:
See the “PIC32 Flash Programming Specification” (DS61145) for a list of Revision and Device ID values.
DS61156G-page 172
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
28.2
Watchdog Timer (WDT)
This section describes the operation of the WDT and
Power-up Timer of the PIC32MX5XX/6XX/7XX.
The WDT, when enabled, operates from the internal
Low-Power Oscillator (LPRC) clock source and can be
used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in
software. Various WDT time-out periods can be
selected using the WDT postscaler. The WDT can also
be used to wake the device from Sleep or Idle mode.
FIGURE 28-1:
The following are some of the key features of the WDT
module:
• Configuration or software controlled
• User-configurable time-out period
• Can wake the device from Sleep or Idle
WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM
PWRT Enable
WDT Enable
LPRC
Control
PWRT Enable
1:64 Output
LPRC
Oscillator
PWRT
1
Clock
25-bit Counter
WDTCLR = 1
WDT Enable
Wake
WDT Enable
Reset Event
25
0
1
WDT Counter Reset
Device Reset
NMI (Wake-up)
Power Save
Decoder
FWDTPS<4:0> (DEVCFG1<20:16>)
© 2009-2011 Microchip Technology Inc.
DS61156G-page 173
PIC32MX5XX/6XX/7XX
28.3
On-Chip Voltage Regulator
28.3.3
POWER-UP REQUIREMENTS
All PIC32MX5XX/6XX/7XX devices’ core and digital
logic are designed to operate at a nominal 1.8V. To
simplify system designs, most devices in the
PIC32MX5XX/6XX/7XX family incorporate an on-chip
regulator providing the required core logic voltage from
VDD.
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, strict power-up conditions must be
adhered to. While powering up, VCORE must never
exceed VDD by 0.3V.
A low-ESR capacitor (such as tantalum) must be
connected to the VCAP/VCORE pin (see Figure 28-2).
This helps to maintain the stability of the regulator.
The recommended value for the filter capacitor is
provided in Section 31.1 “DC Characteristics”.
FIGURE 28-2:
Note:
CONNECTIONS FOR THE
ON-CHIP REGULATOR
3.3V(1)
PIC32
VDD
It is important that the low-ESR capacitor
is placed as close as possible to the
VCAP/VCORE pin.
VCAP/VCORE
28.3.1
ON-CHIP REGULATOR AND POR
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code
execution is disabled. TPU is applied every time the
device resumes operation after any power-down,
including Sleep mode.
28.3.2
ON-CHIP REGULATOR AND BOR
PIC32MX5XX/6XX/7XX devices also have a simple
brown-out capability. If the voltage supplied to the
regulator is inadequate to maintain a regulated level,
the regulator Reset circuitry will generate a Brown-out
Reset. This event is captured by the BOR flag bit
(RCON<1>). The brown-out voltage levels are
specified in Section 31.1 “DC Characteristics”.
DS61156G-page 174
CEFC(2)
(10 μF typ)
Note 1:
2:
VSS
These are typical operating voltages. Refer
to Section 31.1 “DC Characteristics” for
the full operating ranges of VDD and
VCORE.
It is important that the low-ESR capacitor
is placed as close as possible to the
VCAP/VCORE pin.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
28.4
Programming and Diagnostics
PIC32MX5XX/6XX/7XX devices provide a complete
range of programming and diagnostic features that can
increase the flexibility of any application using them.
These features allow system designers to include:
• Simplified field programmability using two-wire
In-Circuit Serial Programming™ (ICSP™)
interfaces
• Debugging using ICSP
• Programming and debugging capabilities using
the EJTAG extension of JTAG
• JTAG boundary scan testing for device and board
diagnostics
FIGURE 28-3:
PIC32 devices incorporate two programming and diagnostic modules, and a trace controller, that provide a
range of functions to the application developer.
BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS
PGEC1
PGED1
ICSP™
Controller
PGEC2
PGED2
ICESEL
TDI
TDO
JTAG
Controller
TCK
Core
TMS
JTAGEN
DEBUG<1:0>
TRCLK
TRD0
TRD1
Instruction Trace
Controller
TRD2
TRD3
DEBUG<1:0>
© 2009-2011 Microchip Technology Inc.
DS61156G-page 175
PIC32MX5XX/6XX/7XX
REGISTER 28-6:
Bit
Range
31:24
23:16
15:8
7:0
DDPCON: DEBUG DATA PORT CONTROL REGISTER
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
U-0
U-0
U-0
U-0
R/W-1
R/W-0
U-0
R/W-0
—
—
—
—
JTAGEN
TROEN
—
TDOEN
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 31-4 Unimplemented: Read as ‘0’
bit 3
JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2
TROEN: Trace Output Enable bit
1 = Enable the trace port
0 = Disable the trace port
bit 1
Unimplemented: Read as ‘0’
bit 0
TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO
DS61156G-page 176
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
29.0
INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set
complies with the MIPS32 Release 2 instruction set
architecture. The PIC32 device family does not support
the following features:
• Core extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions
Note:
Refer to “MIPS32® Architecture for
Programmers Volume II: The MIPS32®
Instruction Set” at www.mips.com for
more information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 177
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 178
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
30.0
DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
30.1
MPLAB Integrated Development
Environment Software
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• A single graphical interface to all debugging tools
- Simulator
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
• Customizable data windows with direct edit of
contents
• High-level source code debugging
• Mouse over variable inspection
• Drag and drop variables from source to watch
windows
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 179
PIC32MX5XX/6XX/7XX
30.2
MPLAB C Compilers for Various
Device Families
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
30.3
HI-TECH C for Various Device
Families
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple
platforms.
30.4
MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
The MPASM Assembler features include:
30.5
MPLINK Object Linker/
MPLIB Object Librarian
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
30.6
MPLAB Assembler, Linker and
Librarian for Various Device
Families
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB C Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
•
•
•
•
•
•
Support for the entire device instruction set
Support for fixed-point and floating-point data
Command line interface
Rich directive set
Flexible macro language
MPLAB IDE compatibility
• Integration into MPLAB IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS61156G-page 180
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
30.7
MPLAB SIM Software Simulator
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and
debug code outside of the hardware laboratory environment, making it an excellent, economical software
development tool.
30.8
MPLAB REAL ICE In-Circuit
Emulator System
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers
significant advantages over competitive emulators
including low-cost, full-speed emulation, run-time
variable watches, trace analysis, complex breakpoints, a
ruggedized probe interface and long (up to three meters)
interconnection cables.
© 2009-2011 Microchip Technology Inc.
30.9
MPLAB ICD 3 In-Circuit Debugger
System
MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
30.10 PICkit 3 In-Circuit Debugger/
Programmer and
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and
programming
of
PIC®
and
dsPIC®
Flash
microcontrollers at a most affordable price point using
the powerful graphical user interface of the MPLAB
Integrated Development Environment (IDE). The
MPLAB PICkit 3 is connected to the design engineer's
PC using a full speed USB interface and can be
connected to the target via an Microchip debug (RJ-11)
connector (compatible with MPLAB ICD 3 and MPLAB
REAL ICE). The connector uses two device I/O pins
and the reset line to implement in-circuit debugging and
In-Circuit Serial Programming™.
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
DS61156G-page 181
PIC32MX5XX/6XX/7XX
30.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
30.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use
interface for programming and debugging Microchip’s
Flash families of microcontrollers. The full featured
Windows® programming interface supports baseline
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
Development Environment (IDE) the PICkit™ 2
enables in-circuit debugging on most PIC®
microcontrollers. In-Circuit-Debugging runs, halts and
single steps the program while the PIC microcontroller
is embedded in the application. When halted at a
breakpoint, the file registers can be examined and
modified.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
30.12 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modular, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
DS61156G-page 182
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
for analog filter design, KEELOQ® security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
31.0
ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions, above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings
(Note 1)
Ambient temperature under bias.............................................................................................................-40°C to +105°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3) ......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3) ........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3) ........................................ -0.3V to +3.6V
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Voltage on VCORE with respect to VSS ....................................................................................................... -0.3V to 2.0V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2) ....................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 183
PIC32MX5XX/6XX/7XX
31.1
DC Characteristics
TABLE 31-1:
OPERATING MIPS VS. VOLTAGE
Max. Frequency
VDD Range
(in Volts)
Temp. Range
(in °C)
PIC32MX5XX/6XX/7XX
DC5
2.3-3.6V
-40°C to +85°C
80 MHz
DC5b
2.3-3.6V
-40°C to +105°C
80 MHz
Characteristic
TABLE 31-2:
THERMAL OPERATING CONDITIONS
Rating
Symbol
Min.
Typical
Max.
Unit
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
TJ
TA
-40
-40
—
—
+140
+105
°C
°C
Industrial Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
V-Temp Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
I/O Pin Power Dissipation:
I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation
TABLE 31-3:
PD
PINT + PI/O
W
PDMAX
(TJ – TA)/θJA
W
THERMAL PACKAGING CHARACTERISTICS
Characteristics
Symbol Typical
Max.
Unit
See
Note
Package Thermal Resistance, 121-Pin XBGA (10x10x1.1 mm)
θJA
40
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm)
θJA
43
—
°C/W
1
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm)
θJA
43
—
°C/W
1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm)
θJA
47
—
°C/W
1
Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm)
θJA
28
—
°C/W
1
Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
TABLE 31-4:
DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Operating Voltage
DC10 VDD
Supply Voltage
RAM Data Retention Voltage(1)
DC12 VDR
DC16 VPOR
VDD Start Voltage to Ensure
Internal Power-on Reset Signal
VDD Rise Rate to Ensure
DC17 SVDD
Internal Power-on Reset Signal
Note 1:
Min.
Typical
Max.
Units
Conditions
2.3
1.75
1.75
—
—
—
3.6
—
2.1
V
V
V
—
—
—
0.00005
—
0.115
V/μs
—
This is the limit to which VDD can be lowered without losing RAM data.
DS61156G-page 184
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-5:
DC CHARACTERISTICS: OPERATING CURRENT (IDD)
DC CHARACTERISTICS
Param.
Typical(3)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Units
Conditions
Operating Current (IDD)(1,2) for PIC32MX575/675/695/775 Family Devices
DC20
6
9
mA
DC20b
7
Code executing from Flash
10
4
—
Code executing from SRAM
DC21
37
40
Code executing from Flash
DC21a
25
—
DC22
64
70
DC22a
61
—
DC23
85
98
mA
mA
mA
90
120
DC23a
85
—
DC25a
125
150
—
4 MHz
—
—
25 MHz
(Note 4)
—
—
60 MHz
(Note 4)
-40ºC,
+25ºC,
+85ºC
—
80 MHz
3.3V
LPRC (31 kHz)
(Note 4)
+105ºC
DC20a
DC23b
-40ºC,
+25ºC,
+85ºC
Code executing from SRAM
Code executing from Flash
Code executing from SRAM
Code executing from Flash
—
+105ºC
µA
Code executing from SRAM
—
—
+25°C
Operating Current (IDD)(1,2,5) for PIC32MX534/564/664/764 Family Devices
DC20b
6
9
mA
Code executing from Flash
—
—
DC20c
2
—
mA
Code executing from SRAM
—
—
DC21b
19
40
mA
Code executing from Flash
—
—
DC21c
14
—
mA
Code executing from SRAM
—
—
DC22b
31
70
mA
Code executing from Flash
—
—
DC22c
29
—
mA
Code executing from SRAM
—
—
DC23b
39
98
mA
Code executing from Flash
—
—
DC23c
39
—
mA
Code executing from SRAM
—
—
DC25b
100
150
µA
—
+25°C
3.3V
Note 1:
2:
3:
4:
5:
4 MHz
25 MHz
(Note 4)
60 MHz
(Note 4)
80 MHz
LPRC (31 kHz)
(Note 4)
A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
The test conditions for IDD measurements are as follows: Oscillator mode = EC+PLL with OSC1 driven by
external square wave from rail-to-rail and PBCLK divisor = 1:8. CPU, Program Flash and SRAM data
memory are operational, program Flash memory Wait states = 7, program cache and prefetch are disabled and SRAM data memory Wait states = 1. All peripheral modules are disabled (ON bit = 0). WDT
and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD.
Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
This parameter is characterized, but not tested in manufacturing.
This information is preliminary.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 185
PIC32MX5XX/6XX/7XX
TABLE 31-6:
DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Parameter
No.
Typical(2)
Max.
Units
Conditions
Idle Current (IIDLE): Core Off, Clock on Base Current(1) for PIC32MX575/675/695/775 Family Devices
DC30
4.5
6.5
mA
-40ºC, +25ºC, +85ºC
DC30b
5
7
mA
+105°C
DC31
13
15
mA
DC32
28
30
mA
—
4 MHz
-40ºC, +25ºC, +85ºC
—
25 MHz (Note 3)
-40ºC, +25ºC, +85ºC
—
60 MHz (Note 3)
—
80 MHz
DC33
36
42
mA
-40ºC, +25ºC, +85ºC
DC33b
39
45
mA
+105°C
DC34
—
40
µA
-40°C
DC34a
—
75
µA
+25°C
DC34b
—
800
µA
+85°C
DC34c
—
1000
µA
+105°C
DC35
35
—
µA
-40°C
DC35a
65
—
µA
+25°C
DC35b
600
—
µA
+85°C
DC35c
800
—
µA
+105°C
DC36
—
43
µA
-40°C
DC36a
—
106
µA
+25°C
DC36b
—
800
µA
+85°C
DC36c
—
1000
µA
+105°C
Idle Current (IIDLE): Core Off, Clock on Base
DC30a
Current(1,4)
2.3V
3.3V
LPRC (31 kHz)
(Note 3)
3.6V
for PIC32MX534/564/664/764 Family Devices
1.5
6.5
mA
-40ºC, +25ºC, +85ºC
DC31a
7
15
mA
-40ºC, +25ºC, +85ºC
—
25 MHz (Note 3)
DC32a
13
30
mA
-40ºC, +25ºC, +85ºC
—
60 MHz (Note 3)
DC33a
17
42
mA
-40ºC, +25ºC, +85ºC
—
80 MHz
DC34c
—
40
µA
-40°C
DC34d
—
75
µA
+25°C
DC34e
—
800
µA
+85°C
DC35c
30
—
µA
-40°C
DC35d
55
—
µA
+25°C
DC35e
230
—
µA
+85°C
DC36c
—
43
µA
-40°C
DC36d
—
106
µA
+25°C
DC36e
—
800
µA
+85°C
Note 1:
2:
3:
4:
—
4 MHz
2.3V
3.3V
LPRC (31 kHz)
(Note 3)
3.6V
The test conditions for base IDLE current measurements are as follows: System clock is enabled and
PBCLK divisor = 1:8. CPU in Idle mode (CPU core Halted). Only digital peripheral modules are enabled
(ON bit = 1) and being clocked. WDT and FSCM are disabled. All I/O pins are configured as inputs and
pulled to VSS. MCLR = VDD.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
This parameter is characterized, but not tested in manufacturing.
This information is preliminary.
DS61156G-page 186
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
DC CHARACTERISTICS
Param.
Typical(2)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Units
Conditions
Power-Down Current (IPD)(1) for PIC32MX575/675/695/775 Family Devices
DC40
10
40
μA
-40°C
DC40a
36
100
μA
+25°C
DC40b
400
720
μA
+85°C
DC40h
900
1800
µA
+105°C
DC40c
41
120
μA
+25°C
DC40d
22
80
μA
-40°C
DC40e
42
120
μA
+25°C
DC40g
315
400(5)
μA
+70°C
DC40f
410
800
μA
+85°C
DC40i
1000
2000
µA
+105°C
2.3V
Base Power-Down Current (Note 6)
3.3V
Base Power-Down Current
3.6V
Base Power-Down Current
Module Differential Current for PIC32MX575/675/695/775 Family Devices
DC41
—
10
μA
—
2.3V
Watchdog Timer Current: ΔIWDT (Notes 3,6)
DC41a
5
—
μA
—
3.3V
Watchdog Timer Current: ΔIWDT (Note 3)
DC41b
—
20
μA
—
3.6V
Watchdog Timer Current: ΔIWDT (Note 3)
DC42
—
40
μA
—
2.3V
RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Notes 3,6)
DC42a
23
—
μA
—
3.3V
RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)
DC42b
—
50
μA
—
3.6V
RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)
DC43
—
1300
μA
—
2.5V
ADC: ΔIADC (Notes 3,4,6)
DC43a
1100
—
μA
—
3.3V
ADC: ΔIADC (Notes 3,4)
DC43b
—
1300
μA
—
3.6V
ADC: ΔIADC (Notes 3,4)
PD)(1,7)
Power-Down Current (I
DC40g
12
for PIC32MX534/564/664/764 Family Devices
40
μA
-40°C
DC40h
20
100
μA
+25°C
DC40i
210
720
μA
+85°C
DC40j
20
120
μA
+25°C
DC40k
15
80
μA
-40°C
DC40l
20
120
μA
+25°C
DC40m
113
400(5)
μA
+70°C
210
800
μA
+85°C
DC40n
Note 1:
2:
3:
4:
5:
6:
7:
2.3V
Base Power-Down Current (Note 6)
3.3V
Base Power-Down Current
3.6V
Base Power-Down Current
Base IPD is measured with all digital peripheral modules and being clocked, CPU clock is disabled. All I/Os
are configured as inputs and pulled low. WDT and FSCM are disabled.
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
Data is characterized at +70°C and not tested. Parameter is for design guidance only.
This parameter is characterized, but not tested in manufacturing.
This information is preliminary.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 187
PIC32MX5XX/6XX/7XX
TABLE 31-7:
DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
DC CHARACTERISTICS
Param.
Typical(2)
No.
Max.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Units
Conditions
Module Differential Current(7) for PIC32MX534/564/664/764 Family Devices
DC41c
—
10
μA
—
2.5V
Watchdog Timer Current: ΔIWDT (Notes 3,6)
DC41d
5
—
μA
—
3.3V
Watchdog Timer Current: ΔIWDT (Note 3)
DC41e
—
20
μA
—
3.6V
Watchdog Timer Current: ΔIWDT (Note 3)
DC42c
—
40
μA
—
2.5V
RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Notes 3,6)
DC42d
23
—
μA
—
3.3V
RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)
DC42e
—
50
μA
—
3.6V
RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3)
DC43c
—
1300
μA
—
2.5V
ADC: ΔIADC (Notes 3,4,6)
DC43d
1100
—
μA
—
3.3V
ADC: ΔIADC (Notes 3,4)
—
1300
μA
—
3.6V
ADC: ΔIADC (Notes 3,4)
DC43e
Note 1:
2:
3:
4:
5:
6:
7:
Base IPD is measured with all digital peripheral modules and being clocked, CPU clock is disabled. All I/Os
are configured as inputs and pulled low. WDT and FSCM are disabled.
Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The Δ current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
Data is characterized at +70°C and not tested. Parameter is for design guidance only.
This parameter is characterized, but not tested in manufacturing.
This information is preliminary.
DS61156G-page 188
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-8:
DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
VIL
DI10
Characteristics
Min.
Typical(1
)
Max.
Units
Conditions
Input Low Voltage
I/O Pins:
with TTL Buffer
VSS
—
0.15 VDD
V
with Schmitt Trigger Buffer
VSS
—
0.2 VDD
V
MCLR
VSS
—
0.2 VDD
V
(2)
DI15
DI16
OSC1 (XT mode)
VSS
—
0.2 VDD
V
(Note 4)
DI17
OSC1 (HS mode)
VSS
—
0.2 VDD
V
(Note 4)
DI18
SDAx, SCLx
VSS
—
0.3 VDD
V
SMBus disabled
(Note 4)
DI19
SDAx, SCLx
VSS
—
0.8
V
SMBus enabled
(Note 4)
0.8 VDD
—
VDD
V
(Note 4)
VIH
DI20
Input High Voltage
I/O Pins:
with Analog Functions
Digital Only
with TTL Buffer
with Schmitt Trigger Buffer
(2)
0.8 VDD
—
0.25 VDD + 0.8V
—
5.5
V
V
0.8 VDD
—
5.5
V
(Note 4)
DI25
MCLR
0.8 VDD
—
VDD
V
DI26
OSC1 (XT mode)
0.7 VDD
—
VDD
V
DI27
OSC1 (HS mode)
0.7 VDD
—
VDD
V
(Note 4)
DI28
SDAx, SCLx
0.7 VDD
—
5.5
V
SMBus disabled
(Note 4)
DI29
SDAx, SCLx
2.1
—
5.5
V
SMBus enabled,
2.3V ≤VPIN ≤5.5
(Note 4)
50
250
400
μA
VDD = 3.3V, VPIN = VSS
DI30
ICNPU
IIL
CNxx Pull up Current
Input Leakage
(Note 4)
Current(3)
DI50
I/O Ports
—
—
+1
μA
VSS ≤VPIN ≤VDD,
Pin at high-impedance
DI51
Analog Input Pins
—
—
+1
μA
VSS ≤VPIN ≤VDD,
Pin at high-impedance
DI55
MCLR(2)
—
—
+1
μA
VSS ≤VPIN ≤VDD
DI56
OSC1
—
—
+1
μA
VSS ≤VPIN ≤VDD,
XT and HS modes
Note 1:
2:
3:
4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
Negative current is defined as current sourced by the pin.
This parameter is characterized, but not tested in manufacturing.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 189
PIC32MX5XX/6XX/7XX
TABLE 31-9:
DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
VOL
DO10
Characteristics
Min.
Typical
Max.
Units
—
—
0.4
V
IOL = 7 mA, VDD = 3.6V
—
—
0.4
V
IOL = 6 mA, VDD = 2.3V
—
—
0.4
V
IOL = 3.5 mA, VDD = 3.6V
—
—
0.4
V
IOL = 2.5 mA, VDD = 2.3V
—
—
V
IOH = -12 mA, VDD = 3.6V
Output Low Voltage
I/O Ports
DO16
OSC2/CLKO
VOH
Conditions
Output High Voltage
DO20
I/O Ports
2.4
1.4
—
—
V
IOH = -12 mA, VDD = 2.3V
DO26
OSC2/CLKO
2.4
—
—
V
IOH = -12 mA, VDD = 3.6V
1.4
—
—
V
IOH = -12 mA, VDD = 2.3V
TABLE 31-10: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Min.(1)
Typical
Max.
Units
Conditions
BOR Event on VDD transition
high-to-low
2.0
—
2.3
V
—
BO10
VBOR
Note 1:
Parameters are for design guidance only and are not tested in manufacturing.
DS61156G-page 190
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-11: DC CHARACTERISTICS: PROGRAM MEMORY(3)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical(1)
Max.
Units
Conditions
—
E/W
—
E/W See Note 4
Program Flash Memory
D130
EP
Cell Endurance
1000
—
D130a
EP
Cell Endurance
20,000
—
—
D131
VPR
VDD for Read
2.3
—
3.6
V
D132
VPEW
VDD for Erase or Write
3.0
—
3.6
V
D132a
VPEW
VDD for Erase or Write
2.3
—
3.6
V
D134
TRETD
Characteristic Retention
20
—
—
Year Provided no other specifications
are violated
D135
IDDP
Supply Current during
Programming
—
10
—
mA
—
TWW
Word Write Cycle Time
20
—
40
μs
—
3
4.5
—
ms
—
Time(2)
—
—
See Note 4
D136
TRW
Row Write Cycle
(128 words per row)
D137
TPE
Page Erase Cycle Time
20
—
—
ms
—
TCE
Chip Erase Cycle Time
80
—
—
ms
—
Note 1:
2:
3:
4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
Refer to “PIC32 Flash Programming Specification” (DS61145) for operating conditions during
programming and erase cycles.
This parameter applies to PIC32MX534/564/664/764 devices only. This information is preliminary.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 191
PIC32MX5XX/6XX/7XX
TABLE 31-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS
DC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Required Flash Wait States
SYSCLK
Units
Comments
0 Wait State
0 to 30
MHz
—
1 Wait State
31 to 60
2 Wait States
61 to 80
TABLE 31-13: COMPARATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical
Max.
Units
Comments
D300
VIOFF
Input Offset Voltage
—
±7.5
±25
mV
AVDD = VDD,
AVSS = VSS
D301
VICM
Input Common Mode Voltage
0
—
VDD
V
AVDD = VDD,
AVSS = VSS
(Note 2)
D302
CMRR
Common Mode Rejection Ratio
55
—
—
dB
Max VICM = (VDD - 1)V
(Note 2)
D303
TRESP
Response Time
—
150
400
ns
AVDD = VDD,
AVSS = VSS
(Notes 1, 2)
D304
ON2OV
Comparator Enabled to Output
Valid
—
—
10
μs
Comparator module is
configured before setting
the comparator ON bit
(Note 2)
D305
IVREF
Internal Voltage Reference
0.57
0.6
0.63
V
For devices without
BGSEL<1:0>
1.14
1.2
1.26
V
BGSEL<1:0> = 00
0.57
0.6
0.63
V
BGSEL<1:0> = 01
Note 1:
2:
Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
These parameters are characterized but not tested.
DS61156G-page 192
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-14: VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
Symbol
No.
D310
Characteristics
VRES
Resolution
Min.
Typical
Max.
Units
Comments
VDD/24
—
VDD/32
LSb
—
D311
VRAA
Absolute Accuracy
—
—
1/2
LSb
—
D312
TSET
Settling Time(1)
—
—
10
μs
—
D313
VIREF
Internal Voltage Reference
—
0.6
—
V
—
Note 1:
Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter is
characterized, but not tested in manufacturing.
TABLE 31-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
DC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Min.
Typical
Max.
Units
Comments
D320
VCORE
Regulator Output Voltage
1.62
1.80
1.98
V
—
D321
CEFC
External Filter Capacitor Value
8
10
—
μF
Capacitor must be low series
resistance (1 ohm)
D322
TPWRT
Power-up Timer Period
—
64
—
ms
—
© 2009-2011 Microchip Technology Inc.
DS61156G-page 193
PIC32MX5XX/6XX/7XX
31.2
AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX5XX/6XX/7XX AC characteristics and timing
parameters.
FIGURE 31-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
Load Condition 2 – for OSC2
VDD/2
RL
CL
Pin
VSS
CL
Pin
RL = 464Ω
CL = 50 pF for all pins
50 pF for OSC2 pin (EC mode)
VSS
TABLE 31-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
AC CHARACTERISTICS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Param.
Symbol
No.
Min.
Typical(1)
Max.
Units
Characteristics
Conditions
DO56
CIO
All I/O pins and OSC2
—
—
50
pF
EC mode
DO58
CB
SCLx, SDAx
—
—
400
pF
In I2C™ mode
Note 1:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 31-2:
EXTERNAL CLOCK TIMING
OS20
OS30
OS31
OSC1
OS30
DS61156G-page 194
OS31
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
OS10
FOSC
OS11
Min.
Typical(1)
Max.
Units
Conditions
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
4
—
—
50
50
MHz
MHz
EC (Note 4)
ECPLL (Note 3)
Oscillator Crystal Frequency
Characteristics
3
—
10
MHz
XT (Note 4)
OS12
4
—
10
MHz
XTPLL
(Notes 3,4)
OS13
10
—
25
MHz
HS (Note 5)
OS14
10
—
25
MHz
HSPLL
(Notes 3,4)
32
32.768
100
kHz
SOSC (Note 4)
—
—
—
—
See parameter
OS10 for FOSC
value
OS15
TCY(2)
OS20
TOSC
TOSC = 1/FOSC =
OS30
TOSL,
TOSH
External Clock In (OSC1)
High or Low Time
0.45 x TOSC
—
—
ns
EC (Note 4)
OS31
TOSR,
TOSF
External Clock In (OSC1)
Rise or Fall Time
—
—
0.05 x TOSC
ns
EC (Note 4)
OS40
TOST
Oscillator Start-up Timer Period
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
—
1024
—
TOSC
(Note 4)
OS41
TFSCM
Primary Clock Fail Safe
Time-out Period
—
2
—
ms
(Note 4)
OS42
GM
External Oscillator
Transconductance
—
12
—
Note 1:
2:
3:
4:
mA/V VDD = 3.3V,
TA = +25°C
(Note 4)
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are
not tested.
Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
PLL input requirements: 4 MHZ ≤ FPLLIN ≤ 5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but tested at 10 MHz only at manufacturing.
This parameter is characterized, but not tested in manufacturing.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 195
PIC32MX5XX/6XX/7XX
TABLE 31-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
4
—
5
MHz
OS51
FSYS
On-Chip VCO System
Frequency
60
—
120
MHz
—
OS52
TLOCK
PLL Start-up Time (Lock Time)
—
—
2
ms
—
(2)
-0.25
—
+0.25
%
OS53
Note 1:
2:
DCLK
CLKO Stability
(Period Jitter or Cumulative)
ECPLL, HSPLL, XTPLL,
FRCPLL modes
Measured over 100 ms
period
These parameters are characterized, but not tested in manufacturing.
This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
D CLK
EffectiveJitter = -------------------------------------------------------------SYSCLK
--------------------------------------------------------CommunicationClock
For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
D CLK
D CLK
EffectiveJitter = ------------- = ------------2
80
-----20
TABLE 31-19:
INTERNAL FRC ACCURACY
AC CHARACTERISTICS
Param.
No.
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature
-40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Min.
Typical
Max.
Units
Conditions
Internal FRC Accuracy @ 8.00 MHz(1) for PIC32MX575/675/695/775 Family Devices
F20a
FRC
Internal FRC Accuracy @ 8.00
F20b
Note 1:
2:
FRC
-2
MHz(1,2)
—
+2
%
—
for PIC32MX534/564/664/764 Family Devices
-0.9
—
+0.9
%
—
Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.
This information is preliminary.
DS61156G-page 196
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-20: INTERNAL RC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Characteristics
Min.
Typical
Max.
Units
Conditions
-15
—
+15
%
—
LPRC @ 31.25 kHz(1)
F21
LPRC
Note 1:
Change of LPRC frequency as VDD changes.
FIGURE 31-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Note: Refer to Figure 31-1 for load conditions.
DO31
DO32
TABLE 31-21: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
DO31
DO32
Symbol
TIOR
TIOF
Characteristics(2)
Port Output Rise Time
Port Output Fall Time
Min.
Typical(1)
Max.
Units
—
5
15
ns
VDD < 2.5V
—
5
10
ns
VDD > 2.5V
—
5
15
ns
VDD < 2.5V
—
5
10
ns
VDD > 2.5V
Conditions
DI35
TINP
INTx Pin High or Low Time
10
—
—
ns
—
DI40
TRBP
CNx High or Low Time (input)
2
—
—
TSYSCLK
—
Note 1:
2:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
This parameter is characterized, but not tested in manufacturing.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 197
PIC32MX5XX/6XX/7XX
FIGURE 31-4:
POWER-ON RESET TIMING CHARACTERISTICS
Internal Voltage Regulator Enabled
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
CPU Starts Fetching Code
SY00
(TPU)
(Note 1)
Internal Voltage Regulator Enabled
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD
VPOR
(TSYSDLY)
SY02
Power-up Sequence
(Note 2)
SY00
(TPU)
(Note 1)
Note 1:
2:
SY10
(TOST)
CPU Starts Fetching Code
The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
Includes interval voltage regulator stabilization delay.
DS61156G-page 198
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-5:
EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)
MCLR
TMCLR
(SY20)
BOR
TBOR
(SY30)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
(TSYSDLY)
SY02
Reset Sequence
CPU Starts Fetching Code
TOST
(SY10)
TABLE 31-22: RESETS TIMING
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SY00
TPU
Power-up Period
Internal Voltage Regulator Enabled
—
400
600
μs
-40°C to +85°C
SY01
TPWRT
Power-up Period
External VCORE Applied
(Power-up timer active)
48
64
80
ms
-40°C to +85°C
SY02
TSYSDLY System Delay Period:
Time Required to Reload Device
Configuration Fuses plus SYSCLK
Delay before First instruction is
Fetched.
—
1 μs +
8 SYSCLK
cycles
—
—
-40°C to +85°C
SY20
TMCLR
MCLR Pulse Width (low)
—
2
—
μs
-40°C to +85°C
SY30
TBOR
BOR Pulse Width (low)
—
1
—
μs
-40°C to +85°C
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 199
PIC32MX5XX/6XX/7XX
FIGURE 31-6:
TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
TA10
TA11
TA15
Symbol
TTXH
TTXL
TTXP
Characteristics(2)
TxCK
High Time
TxCK
Low Time
Typical Max. Units
Conditions
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Must also meet
parameter TA15
Asynchronous,
with prescaler
10
—
—
ns
—
Synchronous,
with prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
—
ns
Must also meet
parameter TA15
Asynchronous,
with prescaler
10
—
—
ns
—
[(Greater of 25 ns or
2 TPB)/N] + 30 ns
—
—
ns
VDD > 2.7V
[(Greater of 25 ns or
2 TPB)/N] + 50 ns
—
—
ns
VDD < 2.7V
20
—
—
ns
VDD > 2.7V
(Note 3)
50
—
—
ns
VDD < 2.7V
(Note 3)
32
—
100
kHz
—
1
TPB
—
TxCK
Synchronous,
Input Period with prescaler
Asynchronous,
with prescaler
OS60
FT1
TA20
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer
Increment
Note 1:
2:
3:
Min.
SOSC1/T1CK Oscillator
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
—
Timer1 is a Type A.
This parameter is characterized, but not tested in manufacturing.
N = Prescale Value (1, 8, 64, 256).
DS61156G-page 200
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Max. Units
Conditions
TB10
TTXH
TxCK
Synchronous, with
High Time prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also meet N = prescale
parameter
value
TB15
(1, 2, 4, 8,
Must also meet 16, 32, 64,
256)
parameter
TB11
TTXL
TxCK
Synchronous, with
Low Time prescaler
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
TB15
TTXP
TxCK
Input
Period
[(Greater of [(25 ns or
2 TPB)/N] + 30 ns
—
ns
VDD > 2.7V
[(Greater of [(25 ns or
2 TPB)/N] + 50 ns
—
ns
VDD < 2.7V
—
1
TPB
TB15
TB20
Synchronous, with
prescaler
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
Note 1:
—
These parameters are characterized, but not tested in manufacturing.
FIGURE 31-7:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS
AC CHARACTERISTICS
Param.
Symbol
No.
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
ICx Input Low Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC11
TCCH
ICx Input High Time
[(12.5 ns or 1 TPB)/N]
+ 25 ns
—
ns
Must also
meet
parameter
IC15.
IC15
TCCP
ICx Input Period
[(25 ns or 2 TPB)/N]
+ 50 ns
—
ns
Note 1:
These parameters are characterized, but not tested in manufacturing.
© 2009-2011 Microchip Technology Inc.
N = prescale
value (1, 4, 16)
—
DS61156G-page 201
PIC32MX5XX/6XX/7XX
FIGURE 31-8:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM mode)
OC10
OC11
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
OC10
TCCF
OCx Output Fall Time
—
—
—
ns
See parameter DO32
OC11
TCCR
OCx Output Rise Time
—
—
—
ns
See parameter DO31
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
FIGURE 31-9:
OCx/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA/OCFB
OC15
OCx
OCx is tri-stated
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics(1)
Min
Typical(2)
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse Width
50
—
—
ns
—
Note 1:
2:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS61156G-page 202
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-10:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
SP31
SDIx
LSb
SP30
MSb In
LSb In
Bit 14 - - - -1
SP40 SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2
)
Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time(3)
TSCK/2
—
—
ns
—
SP11
TSCH
SCKx Output High Time(3)
TSCK/2
—
—
ns
—
—
—
—
ns
See parameter DO32
—
ns
See parameter DO31
See parameter DO32
Time(4)
SP20
TSCF
SCKx Output Fall
SP21
TSCR
SCKx Output Rise Time(4)
—
SP30
TDOF
SDOx Data Output Fall Time(4)
—
—
—
ns
SP31
TDOR
SDOx Data Output Rise
Time(4)
—
—
—
ns
See parameter DO31
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
ns
VDD > 2.7V
—
—
20
ns
VDD < 2.7V
SP40
TDIV2SCH,
TDIV2SCL
Setup Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
—
SP41
TSCH2DIL,
TSCL2DIL
Hold Time of SDIx Data Input
to SCKx Edge
10
—
—
ns
—
Note 1:
2:
3:
4:
—
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 203
PIC32MX5XX/6XX/7XX
FIGURE 31-11:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SCKX
(CKP = 1)
SP10
SP21
SP20
SP20
SP21
SP35
LSb
Bit 14 - - - - - -1
MSb
SDOX
SP30,SP31
SDIX
Bit 14 - - - -1
MSb In
SP40
LSb In
SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typ.(2)
Max.
Units
Conditions
SP10
TSCL
SCKx Output Low Time(3)
TSCK/2
—
—
ns
—
SP11
TSCH
SCKx Output High Time(3)
TSCK/2
—
—
ns
—
—
—
—
ns
See parameter DO32
—
—
—
ns
See parameter DO31
—
—
—
ns
See parameter DO32
—
—
—
ns
See parameter DO31
Time(4)
SP20
TSCF
SCKx Output Fall
SP21
TSCR
SCKx Output Rise Time(4)
Time(4)
SP30
TDOF
SDOx Data Output Fall
SP31
TDOR
SDOx Data Output Rise Time(4)
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
15
ns
VDD > 2.7V
—
—
20
ns
VDD < 2.7V
SP36
TDOV2SC, SDOx Data Output Setup to
TDOV2SCL First SCKx Edge
15
—
—
ns
SP40
TDIV2SCH, Setup Time of SDIx Data Input to
TDIV2SCL SCKx Edge
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
15
—
—
ns
VDD > 2.7V
20
—
—
ns
VDD < 2.7V
TSCH2DIL,
TSCL2DIL
SP41
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
—
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
Assumes 50 pF load on all SPIx pins.
DS61156G-page 204
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-12:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKX
(CKP = 1)
SP35
MSb
SDOX
LSb
Bit 14 - - - - - -1
SP51
SP30,SP31
SDIX
MSb In
SP40
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for
Industrial
-40°C ≤TA ≤+105°C for VTemp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
SP70
SP71
SP72
SP73
SP30
SP31
SP35
TSCL
TSCH
TSCF
TSCR
TDOF
TDOR
TSCH2DOV,
TSCL2DOV
SCKx Input Low Time(3)
SCKx Input High Time(3)
SCKx Input Fall Time
SCKx Input Rise Time
SDOx Data Output Fall Time(4)
SDOx Data Output Rise Time(4)
SDOx Data Output Valid after
SCKx Edge
SP40
TDIV2SCH,
TDIV2SCL
TSCH2DIL,
TSCL2DIL
Setup Time of SDIx Data Input
to SCKx Edge
Hold Time of SDIx Data Input
to SCKx Edge
SP41
Min.
Typ.(2)
Max.
Units
Conditions
TSCK/2
TSCK/2
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
15
20
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
—
See parameter DO32
See parameter DO31
See parameter DO32
See parameter DO31
VDD > 2.7V
VDD < 2.7V
—
10
—
—
ns
—
175
—
—
ns
—
5
—
25
ns
—
SP50
TSSL2SCH, SSx ↓ to SCKx ↑ or SCKx Input
TSSL2SCL
SP51
TSSH2DOZ SSx ↑ to SDOx Output
High-Impedance(3)
SP52
TSCH2SSH SSx after SCKx Edge
TSCK + 20
—
—
ns
—
TSCL2SSH
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
Note 1:
2:
3:
4:
© 2009-2011 Microchip Technology Inc.
DS61156G-page 205
PIC32MX5XX/6XX/7XX
FIGURE 31-13:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35
MSb
SDOx
Bit 14 - - - - - -1
LSb
SP30,SP31
SDIx
SDI
MSb In
SP40
SP51
Bit 14 - - - -1
LSb In
SP41
Note: Refer to Figure 31-1 for load conditions.
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP70
TSCL
SCKx Input Low Time(3)
TSCK/2
—
—
ns
—
SP71
TSCH
SCKx Input High Time(3)
TSCK/2
—
—
ns
—
SP72
TSCF
SCKx Input Fall Time
—
5
10
ns
—
SP73
TSCR
SCKx Input Rise Time
—
5
10
ns
—
—
—
—
ns
See parameter DO32
—
—
—
ns
See parameter DO31
Time(4)
SP30
TDOF
SDOx Data Output Fall
SP31
TDOR
SDOx Data Output Rise Time(4)
SP35
TSCH2DOV, SDOx Data Output Valid after
TSCL2DOV SCKx Edge
—
—
20
ns
VDD > 2.7V
—
—
30
ns
VDD < 2.7V
SP40
TDIV2SCH, Setup Time of SDIx Data Input
TDIV2SCL to SCKx Edge
10
—
—
ns
—
SP41
TSCH2DIL,
TSCL2DIL
10
—
—
ns
—
SP50
TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input
TSSL2SCL
175
—
—
ns
—
Note 1:
2:
3:
4:
Hold Time of SDIx Data Input
to SCKx Edge
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
DS61156G-page 206
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical(2)
Max.
Units
Conditions
SP51
TSSH2DOZ SSx ↑ to SDOX Output
High-Impedance(4)
5
—
25
ns
—
SP52
TSCH2SSH SSx ↑ after SCKx Edge
TSCL2SSH
TSCK +
20
—
—
ns
—
SP60
TSSL2DOV SDOx Data Output Valid after
SSx Edge
—
—
25
ns
—
Note 1:
2:
3:
4:
These parameters are characterized, but not tested in manufacturing.
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
The minimum clock period for SCKx is 40 ns.
Assumes 50 pF load on all SPIx pins.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 207
PIC32MX5XX/6XX/7XX
FIGURE 31-14:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 31-1 for load conditions.
FIGURE 31-15:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM25
IM33
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 31-1 for load conditions.
DS61156G-page 208
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
IM10
Min.(1)
Max.
Units
Conditions
TLO:SCL Clock Low Time 100 kHz mode
TPB * (BRG + 2)
—
μs
—
400 kHz mode
TPB * (BRG + 2)
—
μs
—
mode(2)
TPB * (BRG + 2)
—
μs
—
Clock High Time 100 kHz mode
TPB * (BRG + 2)
—
μs
—
400 kHz mode
TPB * (BRG + 2)
—
μs
—
1 MHz mode(2)
TPB * (BRG + 2)
—
μs
—
—
300
ns
20 + 0.1 CB
300
ns
Characteristics
1 MHz
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
THI:SCL
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
Fall Time
400 kHz mode
1 MHz mode(2)
—
100
ns
SDAx and SCLx 100 kHz mode
Rise Time
400 kHz mode
—
1000
ns
TSU:DAT Data Input
Setup Time
THD:DAT Data Input
Hold Time
TSU:STA
Start Condition
Setup Time
THD:STA Start Condition
Hold Time
TSU:STO Stop Condition
Setup Time
20 + 0.1 CB
300
ns
1 MHz mode(2)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(2)
100
—
ns
100 kHz mode
0
—
μs
400 kHz mode
0
0.9
μs
1 MHz mode(2)
0
0.3
μs
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode(2)
TPB * (BRG + 2)
—
ns
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode(2)
TPB * (BRG + 2)
—
ns
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
THD:STO Stop Condition
Hold Time
IM40
TAA:SCL
Output Valid
from Clock
IM50
IM51
Note 1:
2:
TBF:SDA Bus Free Time
CB
TPGD
—
Only relevant for
Repeated Start
condition
After this period, the
first clock pulse is
generated
—
—
ns
TPB * (BRG + 2)
—
ns
100 kHz mode
TPB * (BRG + 2)
—
ns
400 kHz mode
TPB * (BRG + 2)
—
ns
1 MHz mode(2)
TPB * (BRG + 2)
—
ns
100 kHz mode
—
3500
ns
—
400 kHz mode
—
1000
ns
—
(2)
—
350
ns
—
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode(2)
0.5
—
μs
The amount of time the
bus must be free
before a new
transmission can start
—
400
pF
—
52
312
ns
—
Bus Capacitive Loading
Pulse Gobbler
—
TPB * (BRG + 2)
1 MHz mode
IM45
CB is specified to be
from 10 to 400 pF
mode(2)
1 MHz
IM34
CB is specified to be
from 10 to 400 pF
Delay(3)
—
BRG is the value of the I2C™ Baud Rate Generator.
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
© 2009-2011 Microchip Technology Inc.
DS61156G-page 209
PIC32MX5XX/6XX/7XX
FIGURE 31-16:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 31-1 for load conditions.
FIGURE 31-17:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS25
IS33
SDAx
In
IS40
IS40
IS45
SDAx
Out
Note: Refer to Figure 31-1 for load conditions.
DS61156G-page 210
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
IS10
IS11
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
Note 1:
Symbol
TLO:SCL
THI:SCL
TF:SCL
TR:SCL
TSU:DAT
THD:DAT
TSU:STA
THD:STA
TSU:STO
THD:STO
TAA:SCL
TBF:SDA
CB
Characteristics
Clock Low Time
Clock High Time
SDAx and SCLx
Fall Time
SDAx and SCLx
Rise Time
Data Input
Setup Time
Data Input
Hold Time
Start Condition
Setup Time
Start Condition
Hold Time
Stop Condition
Setup Time
Stop Condition
Hold Time
Min.
Max.
Units
100 kHz mode
4.7
—
μs
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
1.3
—
μs
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode(1)
0.5
—
μs
100 kHz mode
4.0
—
μs
PBCLK must operate at a
minimum of 800 kHz
400 kHz mode
0.6
—
μs
PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode(1)
0.5
—
μs
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
100
ns
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
1 MHz mode(1)
—
300
ns
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
1 MHz mode(1)
100
—
ns
100 kHz mode
0
—
ns
400 kHz mode
0
0.9
μs
1 MHz mode(1)
0
0.3
μs
100 kHz mode
4700
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
250
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
600
—
ns
100 kHz mode
4000
—
ns
400 kHz mode
600
—
ns
1 MHz mode(1)
250
Output Valid from 100 kHz mode
Clock
400 kHz mode
Bus Free Time
Conditions
—
CB is specified to be from
10 to 400 pF
CB is specified to be from
10 to 400 pF
—
—
Only relevant for Repeated
Start condition
After this period, the first
clock pulse is generated
—
—
ns
0
3500
ns
0
1000
ns
1 MHz mode(1)
0
350
ns
100 kHz mode
4.7
—
μs
400 kHz mode
1.3
—
μs
1 MHz mode(1)
0.5
—
μs
—
400
pF
Bus Capacitive Loading
—
—
The amount of time the bus
must be free before a new
transmission can start
—
Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
© 2009-2011 Microchip Technology Inc.
DS61156G-page 211
PIC32MX5XX/6XX/7XX
FIGURE 31-18:
CiTx Pin
(output)
CAN MODULE I/O TIMING CHARACTERISTICS
New Value
Old Value
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 31-34: CAN MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
—
—
—
ns
See parameter D032
See parameter D031
CA10
TioF
Port Output Fall Time
CA11
TioR
Port Output Rise Time
—
—
—
ns
CA20
Tcwf
Pulse Width to Trigger
CAN Wake-up Filter
700
—
—
ns
Note 1:
2:
Conditions
—
These parameters are characterized but not tested in manufacturing.
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS61156G-page 212
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-35: ETHERNET MODULE SPECIFICATIONS
AC CHARACTERISTICS
Param.
No.
Characteristic
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Min.
Typical
Max.
Units
Conditions
MIIM Timing Requirements
ET1
MDC Duty Cycle
40
—
60
%
—
ET2
MDC Period
400
—
—
ns
—
ET3
MDIO Output Delay
10
—
10
ns
—
ET4
MDIO Input Delay
0
—
300
ns
—
TX Clock Frequency
—
25
—
MHz
—
ET6
TX Clock Duty Cycle
35
—
65
%
—
ET7
ETXDx, ETEN, ETXERR Delay
0
—
25
ns
—
MII Timing Requirements
ET5
ET8
RX Clock Frequency
—
25
—
MHz
—
ET9
RX Clock Duty Cycle
35
—
65
%
—
ET10
ERXDx, ERXDV, ERXERR Delay
10
—
30
ns
—
RMII Timing Requirements
ET11
Reference Clock Frequency
—
50
—
MHz
—
ET12
Reference Clock Duty Cycle
35
—
65
%
—
ET13
ETXDx, ETEN, Delay
2
—
16
ns
—
ET14
ERXDx, ERXDV, ERXERR Delay
2
—
16
ns
—
© 2009-2011 Microchip Technology Inc.
DS61156G-page 213
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS(5)
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Min.
Typical
Max.
Units
Conditions
Greater of
VDD – 0.3
or 2.5
—
Lesser of
VDD + 0.3
or 3.6
V
VSS
—
VSS + 0.3
V
AVSS + 2.0
—
AVDD
V
(Note 1)
2.5
—
3.6
V
VREFH = AVDD (Note 3)
Device Supply
AD01
AD02
AVDD
AVSS
Module VDD Supply
Module VSS Supply
—
—
Reference Inputs
AD05
VREFH
Reference Voltage High
AD05a
AD06
VREFL
Reference Voltage Low
AVSS
—
VREFH –
2.0
V
(Note 1)
AD07
VREF
Absolute Reference
Voltage (VREFH – VREFL)
2.0
—
AVDD
V
(Note 3)
AD08
IREF
Current Drain
—
250
—
400
3
μA
μA
ADC operating
ADC off
Analog Input
AD12
VINH-VINL Full-Scale Input Span
AD13
VINL
AD14
VIN
AD15
AD17
RIN
VREFL
—
VREFH
V
—
Absolute VINL Input
Voltage
AVSS – 0.3
—
AVDD/2
V
—
Absolute Input Voltage
AVSS – 0.3
—
AVDD + 0.3
V
—
Leakage Current
—
+/- 0.001
+/-0.610
μA
VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 kΩ
Recommended
Impedance of Analog
Voltage Source
—
—
5K
Ω
(Note 1)
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr
Resolution
AD21c INL
Integral Nonlinearity
> -1
—
<1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL
Differential Nonlinearity
> -1
—
<1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
(Note 2)
AD23c GERR
Gain Error
> -1
—
<1
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD24n EOFF
Offset Error
> -1
—
<1
LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c
Monotonicity
—
—
—
Note 1:
2:
3:
4:
5:
—
10 data bits
bits
—
—
Guaranteed
These parameters are not characterized or tested in manufacturing.
With no missing codes.
These parameters are characterized, but not tested in manufacturing.
Characterized with a 1 kHz sinewave.
For PIC32MX534/564/664/764 devices, data provided in this table is preliminary.
DS61156G-page 214
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-36: ADC MODULE SPECIFICATIONS(5) (CONTINUED)
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
Min.
Typical
Max.
Units
Conditions
ADC Accuracy – Measurements with Internal VREF+/VREF-
AD20d Nr
Resolution
AD21d INL
Integral Nonlinearity
> -1
—
<1
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD22d DNL
Differential Nonlinearity
> -1
—
<1
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Notes 2,3)
AD23d GERR
Gain Error
> -4
—
<4
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD24d EOFF
Offset Error
> -2
—
<2
LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD25d
Monotonicity
—
—
—
—
Guaranteed
—
10 data bits
bits
(Note 3)
Dynamic Performance
AD31b SINAD
Signal to Noise and
Distortion
55
58.5
—
dB
(Notes 3,4)
AD34b ENOB
Effective Number of Bits
9.0
9.5
—
bits
(Notes 3,4)
Note 1:
2:
3:
4:
5:
These parameters are not characterized or tested in manufacturing.
With no missing codes.
These parameters are characterized, but not tested in manufacturing.
Characterized with a 1 kHz sinewave.
For PIC32MX534/564/664/764 devices, data provided in this table is preliminary.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 215
PIC32MX5XX/6XX/7XX
TABLE 31-37: 10-BIT ADC CONVERSION RATE PARAMETERS(2)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
ADC Speed
TAD
Minimum
1 Msps to
400 ksps(1)
65 ns
Sampling
RS
Time
Maximum
Mininum
132 ns
500Ω
ADC Channels Configuration
VDD
3.0V to 3.6V
VREF- VREF+
ANx
Up to 400 ksps
200 ns
200 ns
5.0 kΩ
CHX
SHA
ADC
2.5V to 3.6V
VREF- VREF+
or
or
AVSS AVDD
ANx
CHX
SHA
ADC
ANx or VREF-
Up to 300 ksps
200 ns
200 ns
5.0 kΩ
2.5V to 3.6V
VREF- VREF+
or
or
AVSS AVDD
ANx
CHX
SHA
ADC
ANx or VREF-
Note 1:
2:
External VREF- and VREF+ pins must be used for correct operation.
These parameters are characterized, but not tested in manufacturing.
DS61156G-page 216
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-38: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics
Min.
Typical(1)
Max.
Units
Analog-to-Digital Clock Period(2)
65
—
—
ns
Conditions
Clock Parameters
AD50
TAD
See Table 31-37
Conversion Rate
AD55
TCONV
Conversion Time
—
12 TAD
—
—
AD56
FCNV
Throughput Rate
(Sampling Speed)
—
—
1000
ksps
AVDD = 3.0V to 3.6V
—
—
400
ksps
AVDD = 2.5V to 3.6V
1 TAD
—
—
—
TSAMP must be ≥ 132 ns
—
1.0 TAD
—
—
Auto-Convert Trigger
(SSRC<2:0> = 111)
not selected
0.5 TAD
—
1.5 TAD
—
—
AD57
TSAMP
Sample Time
—
Timing Parameters
AD60
TPCS
Conversion Start from Sample
Trigger(3)
AD61
TPSS
Sample Start from Setting
Sample (SAMP) bit
AD62
TCSS
Conversion Completion to
Sample Start (ASAM = 1)(3)
—
0.5 TAD
—
—
—
AD63
TDPU
Time to Stabilize Analog Stage
from Analog-to-Digital Off to
Analog-to-Digital On(3)
—
—
2
μs
—
Note 1:
2:
3:
These parameters are characterized, but not tested in manufacturing.
Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
Characterized by design but not tested.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 217
PIC32MX5XX/6XX/7XX
FIGURE 31-19:
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING
CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution Set SAMP
Clear SAMP
SAMP
ch0_dischrg
ch0_samp
eoc
AD61
AD60
AD55
TSAMP
AD55
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
8
5
6
7
8
1 – Software sets ADxCON. SAMP to start sampling.
2 – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit A/D Converter” (DS61104) of the
“PIC32 Family Reference Manual”.
3 – Software clears ADxCON. SAMP to start conversion.
4 – Sampling ends, conversion sequence starts.
5 – Convert bit 9.
6 – Convert bit 8.
7 – Convert bit 0.
8 – One TAD for end of conversion.
DS61156G-page 218
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-20:
ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Execution
Set ADON
SAMP
ch0_dischrg
ch0_samp
eoc
TSAMP
AD55
TSAMP
AD55
TCONV
CONV
ADxIF
Buffer(0)
Buffer(1)
1
2
3
4
5
6
7
3
4
5
6
8
3
4
1 – Software sets ADxCON. ADON to start AD operation.
5 – Convert bit 0.
2 – Sampling starts after discharge period.
TSAMP is described in Section 17. “10-bit A/D Converter” (DS61104)
of the “PIC32 Family Reference Manual .
6 – One TAD for end of conversion.
3 – Convert bit 9.
8 – Sample for time specified by SAMC<4:0>.
7 – Begin conversion of next channel.
4 – Convert bit 8.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 219
PIC32MX5XX/6XX/7XX
FIGURE 31-21:
PARALLEL SLAVE PORT TIMING
CS
PS5
RD
PS6
WR
PS4
PS7
PMD<7:0>
PS1
PS3
PS2
TABLE 31-39: PARALLEL SLAVE PORT REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristics(1)
Min.
Typical
Max.
Units
Conditions
PS1
TdtV2wrH Data In Valid before WR or CS
Inactive (setup time)
20
—
—
ns
—
PS2
TwrH2dtI
WR or CS Inactive to Data-In
Invalid (hold time)
40
—
—
ns
—
PS3
TrdL2dtV
RD and CS Active to Data-Out
Valid
—
—
60
ns
—
PS4
TrdH2dtI
RD Active or CS Inactive to
Data-Out Invalid
0
—
10
ns
—
PS5
Tcs
CS Active Time
TPB + 40
—
—
ns
—
PS6
TWR
WR Active Time
TPB + 25
—
—
ns
—
PS7
TRD
RD Active Time
TPB + 25
—
—
ns
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS61156G-page 220
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
FIGURE 31-22:
PARALLEL MASTER PORT READ TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
PM4
Address
PMA<13:18>
PM6
PMD<7:0>
Data
Data
Address<7:0>
Address<7:0>
PM2
PM7
PM3
PMRD
PM5
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
Conditions
PM1
TLAT
PMALL/PMALH Pulse Width
—
1 TPB
—
—
—
PM2
TADSU
Address Out Valid to
PMALL/PMALH Invalid (address
setup time)
—
2 TPB
—
—
—
PM3
TADHOLD PMALL/PMALH Invalid to Address
Out Invalid (address hold time)
—
1 TPB
—
—
—
PM4
TAHOLD
PMRD Inactive to Address Out
Invalid
(address hold time)
5
—
—
ns
—
PM5
TRD
PMRD Pulse Width
—
1 TPB
—
—
—
PM6
TDSU
PMRD or PMENB Active to Data In
Valid (data setup time)
15
—
—
ns
—
PM7
TDHOLD
PMRD or PMENB Inactive to Data
In Invalid (data hold time)
—
80
—
ns
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 221
PIC32MX5XX/6XX/7XX
FIGURE 31-23:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
TPB
TPB
TPB
TPB
TPB
TPB
TPB
TPB
PB Clock
Address
PMA<13:18>
PM2 + PM3
Address<7:0>
PMD<7:0>
Data
PM12
PM13
PMRD
PM11
PMWR
PM1
PMALL/PMALH
PMCS<2:1>
TABLE 31-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
Min.
Typical
Max.
Units
Conditions
PM11
TWR
PMWR Pulse Width
—
1 TPB
—
—
—
PM12
TDVSU
Data Out Valid before PMWR or
PMENB goes Inactive (data setup
time)
—
2 TPB
—
—
—
PM13
TDVHOLD PMWR or PMEMB Invalid to Data
Out Invalid (data hold time)
—
1 TPB
—
—
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS61156G-page 222
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE 31-42: OTG ELECTRICAL SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristics(1)
USB313 VUSB
USB Voltage
Min.
Typical
Max.
Units
3.0
—
3.6
V
Conditions
Voltage on VUSB must
be in this range for
proper USB operation
USB315 VILUSB
Input Low Voltage for USB Buffer
—
—
0.8
V
—
USB316 VIHUSB
Input High Voltage for USB Buffer
2.0
—
—
V
—
USB318 VDIFS
Differential Input Sensitivity
—
—
0.2
V
The difference
between D+ and Dmust exceed this value
while VCM is met
USB319 VCM
Differential Common Mode Range
0.8
—
2.5
V
—
USB320 ZOUT
Driver Output Impedance
28.0
—
44.0
Ω
—
USB321 VOL
Voltage Output Low
0.0
—
0.3
V
14.25 kΩ load
connected to 3.6V
USB322 VOH
Voltage Output High
2.8
—
3.6
V
14.25 kΩ load
connected to ground
Note 1:
These parameters are characterized, but not tested in manufacturing.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 223
PIC32MX5XX/6XX/7XX
FIGURE 31-24:
EJTAG TIMING CHARACTERISTICS
TTCKeye
TTCKhigh
TTCKlow
Trf
TCK
Trf
TMS
TDI
TTsetup TThold
Trf
Trf
TDO
TRST*
TTRST*low
TTDOout
TTDOzstate
Defined
Trf
Undefined
TABLE 31-43: EJTAG TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
Operating temperature -40°C ≤TA ≤+85°C for Industrial
-40°C ≤TA ≤+105°C for V-Temp
AC CHARACTERISTICS
Param.
No.
Symbol
Description(1)
Min.
Max.
Units
Conditions
EJ1
TTCKCYC
TCK Cycle Time
25
—
ns
—
EJ2
TTCKHIGH
TCK High Time
10
—
ns
—
EJ3
TTCKLOW
TCK Low Time
10
—
ns
—
EJ4
TTSETUP
TAP Signals Setup Time Before
Rising TCK
5
—
ns
—
EJ5
TTHOLD
TAP Signals Hold Time After
Rising TCK
3
—
ns
—
EJ6
TTDOOUT
TDO Output Delay Time from
Falling TCK
—
5
ns
—
EJ7
TTDOZSTATE TDO 3-State Delay Time from
Falling TCK
—
5
ns
—
EJ8
TTRSTLOW
TRST Low Time
25
—
ns
—
EJ9
TRF
TAP Signals Rise/Fall Time, All
Input and Output
—
—
ns
—
Note 1:
These parameters are characterized, but not tested in manufacturing.
DS61156G-page 224
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
32.0
PACKAGING INFORMATION
32.1
Package Marking Information
64-Lead TQFP (10x10x1 mm)
PIC32MX575F
512H-80I/PT
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
e3
0510017
100-Lead TQFP (14x14x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
100-Lead TQFP (12x12x1 mm)
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
*
Note:
Example
Example
PIC32MX575F
512L-80I/PF e3
0510017
Example
PIC32MX575F
512L-80I/PT e3
0510017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e) 3
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 225
PIC32MX5XX/6XX/7XX
32.1
Package Marking Information (Continued)
64-Lead QFN (9x9x0.9 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
121-Lead XBGA (10x10x1.1 mm)
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
DS61156G-page 226
Example
PIC32MX575F
512H-80I/MR
e3
0510017
Example
PIC32MX575F
512H-80I/BG
e3
0510017
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
32.2
Package Details
The following sections give the technical details of the packages.
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DS61156G-page 227
PIC32MX5XX/6XX/7XX
/HDG3ODVWLF7KLQ4XDG)ODWSDFN37±[[PP%RG\PP>74)[email protected]
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DS61156G-page 229
PIC32MX5XX/6XX/7XX
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DS61156G-page 230
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
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DS61156G-page 231
PIC32MX5XX/6XX/7XX
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DS61156G-page 232
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009-2011 Microchip Technology Inc.
DS61156G-page 233
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156G-page 234
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009-2011 Microchip Technology Inc.
DS61156G-page 235
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156G-page 236
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009-2011 Microchip Technology Inc.
DS61156G-page 237
PIC32MX5XX/6XX/7XX
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS61156G-page 238
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
APPENDIX A:
MIGRATING FROM
PIC32MX3XX/4XX TO
PIC32MX5XX/6XX/7XX
DEVICES
This appendix provides an overview of considerations
for migrating from PIC32MX3XX/4XX devices to the
PIC32MX5XX/6XX/7XX family of devices. The code
developed for the PIC32MX3XX/4XX devices can be
ported to the PIC32MX5XX/6XX/7XX devices after
making the appropriate changes outlined below.
A.1
Table A-1 outlines the peripherals and associated
interrupts that are implemented differently on
PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX
devices.
In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
and the transfer done interrupts were changed from 24
to 25.
DMA
PIC32MX5XX/6XX/7XX devices do
stopping DMA transfers in Idle mode.
A.2
not
support
Interrupts
PIC32MX5XX/6XX/7XX devices have persistent
interrupts for some of the peripheral modules. This
means that the interrupt condition for these peripherals
must be cleared before the interrupt flag can be
cleared.
For example, to clear a UART receive interrupt, the
user application must first read the UART Receive
register to clear the interrupt condition and then clear
the associated UxIF flag to clear the pending UART
interrupt. In other words, the UxIF flag cannot be
cleared by software until the UART Receive register is
read.
TABLE A-1:
PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION
DIFFERENCES
Module
Interrupt Implementation
Input Capture
To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
SPI
Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF
register to obtain the number of data to receive/transmit below the level specified by the
SRXISEL<1:0> and STXISEL<1:0> bits.
UART
TX interrupt will be generated as soon as the UART module is enabled.
Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
ADC
All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
PMP
To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 239
PIC32MX5XX/6XX/7XX
APPENDIX B:
REVISION HISTORY
Revision B (November 2009)
The revision includes the following global update:
Revision A (August 2009)
This is the initial released version of this document.
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits.
Other major changes are referenced by their respective
chapter/section in Table B-1.
TABLE B-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, USB, CAN and Added the following devices:
Ethernet 32-bit Flash
- PIC32MX575F256L
Microcontrollers”
- PIC32MX695F512L
- PIC32MX695F512H
The 100-pin TQFP pin diagrams have been updated to reflect the current pin
name locations (see the “Pin Diagrams” section).
Added the 121-pin Ball Grid Array (XBGA) pin diagram.
Updated Table 1: “PIC32 USB and CAN – Features”
Added the following tables:
- Table 4: “Pin Names: PIC32MX534F064L, PIC32MX564F064L,
PIC32MX564F128L, PIC32MX575F256L and PIC32MX575F512L
Devices”
- Table 5: “Pin Names: PIC32MX664F064L, PIC32MX664F128L,
PIC32MX675F256L, PIC32MX675F512L and PIC32MX695F512L
Devices”
- Table 6: “Pin Names: PIC32MX775F256L, PIC32MX775F512L and
PIC32MX795F512L Devices”
Updated the following pins as 5V tolerant:
- 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2)
2.0 “Guidelines for Getting Started
with 32-bit Microcontrollers”
DS61156G-page 240
Removed the last sentence of 2.3.1 “Internal Regulator Mode”.
Removed Section 2.3.2 “External Regulator Mode”
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE B-1:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
4.0 “Memory Organization”
Update Description
Updated all register tables to include the Virtual Address and All Resets
columns.
Updated the title of Figure 4-4 to include the PIC32MX575F256L device.
Updated the title of Figure 4-6 to include the PIC32MX695F512L and
PIC32MX695F512H devices. Also changed PIC32MX795F512L to
PIC32MX795F512H.
Updated the title of Table 4-3 to include the PIC32MX695F512H device.
Updated the title of Table 4-5 to include the PIC32MX575F5256L device.
Updated the title of Table 4-6 to include the PIC32MX695F512L device.
Reversed the order of Table 4-11 and Table 4-12.
Reversed the order of Table 4-14 and Table 4-15.
Updated the title of Table 4-15 to include the PIC32MX575F256L and
PIC32MX695F512L devices.
Updated the title of Table 4-45 to include the PIC32MX575F256L device.
Updated the title of Table 4-47 to include the PIC32MX695F512H and
PIC32MX695F512L devices.
12.0 “I/O Ports”
Updated the second paragraph of 12.1.2 “Digital Inputs” and removed Table
12-1.
22.0 “10-bit Analog-to-Digital
Converter (ADC)”
Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2).
28.0 “Special Features”
Removed references to the ENVREG pin in 28.3 “On-Chip Voltage
Regulator”.
Updated the first sentence of 28.3.1 “On-Chip Regulator and POR” and
28.3.2 “On-Chip Regulator and BOR”.
Updated the Connections for the On-Chip Regulator (see Figure 28-2).
31.0 “Electrical Characteristics”
Updated the Absolute Maximum Ratings and added Note 3.
Added Thermal Packaging Characteristics for the 121-pin XBGA package
(see Table 31-3).
Updated the Operating Current (IDD) DC Characteristics (see Table 31-5).
Updated the Idle Current (IIDLE) DC Characteristics (see Table 31-6).
Updated the Power-Down Current (IPD) DC Characteristics (see Table 31-7).
Removed Note 1 from the Program Flash Memory Wait State Characteristics
(see Table 31-12).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics,
changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see
Figure 31-13).
32.0 “Packaging Information”
Added the 121-pin XBGA package marking information and package details.
“Product Identification System”
Added the definition for BG (121-lead 10x10x1.1 mm, XBGA).
Added the definition for Speed.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 241
PIC32MX5XX/6XX/7XX
Revision C (February 2010)
The revision includes the following updates, as
described in Table B-2:
TABLE B-2:
MAJOR SECTION UPDATES
Section Name
“High-Performance, USB, CAN
and Ethernet 32-bit Flash
Microcontrollers”
Update Description
Added the following devices:
•
•
•
•
•
•
PIC32MX675F256H
PIC32MX775F256H
PIC32MX775F512H
PIC32MX675F256L
PIC32MX775F256L
PIC32MX775F512L
Added the following pins:
•
•
•
•
1.0 “Device Overview”
EREFCLK
ECRSDV
AEREFCLK
AECRSDV
Added the EREFCLK and ECRSDV pins to Table 5 and Table 6.
Updated the pin number pinout I/O descriptions for the following pin names in
Table 1-1:
• SCL3
• SCL5
• RTCC
• C1OUT
• SDA3
• SDA5
• CVREF-
• C2IN-
• SCL2
• TMS
• CVREF+
• C2IN+
• SDA2
• TCK
• CVREFOUT
• C2OUT
• SCL4
• TDI
• C1IN-
• PMA0
• SDA4
• TDO
• C1IN+
• PMA1
Added the following pins to the Pinout I/O Descriptions table (Table 1-1):
4.0 “Memory Organization”
• EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
Added new devices and updated the virtual and physical memory map values in
Figure 4-4.
Added new devices to Figure 4-5.
Added new devices to the following register maps:
•
•
•
•
•
•
•
•
28.0 “Special Features”
Appendix A: “Migrating from
PIC32MX3XX/4XX to
PIC32MX5XX/6XX/7XX
Devices”
DS61156G-page 242
Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps)
Table 4-12 (I2C2 Register Map)
Table 4-15 (SPI1 Register Map)
Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps)
Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps)
Table 4-45 (CAN1 Register Map)
Table 4-46 (CAN2 Register Map)
Table 4-47 (Ethernet Controller Register Map)
Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device
Configuration Word Summary).
Changed all references of POSCMD to POSCMOD in the Device Configuration
Word 1 register (see Register 28-2).
Added the new section Appendix .
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Revision D (May 2010)
The revision includes the following updates, as
described in Table B-3:
TABLE B-3:
MAJOR SECTION UPDATES
Section Name
“High-Performance, USB, CAN
and Ethernet 32-bit Flash
Microcontrollers”
Update Description
Updated the initial Flash memory range to 64K.
Updated the initial SRAM memory range to 16K.
Added the following devices (see Table 1, Table 2, Table 3 and the Pin
Diagrams):
•
•
•
•
•
•
•
•
•
•
•
•
4.0 “Memory Organization”
PIC32MX534F064H
PIC32MX564F064H
PIC32MX664F064H
PIC32MX564F128H
PIC32MX664F128H
PIC32MX764F128H
PIC32MX534F064L
PIC32MX564F064L
PIC32MX664F064L
PIC32MX564F128L
PIC32MX664F128L
PIC32MX764F128L
Added new Memory Maps (Figure 4-1, Figure 4-2 and Figure 4-3).
The bit named I2CSIF was changed to I2C1SIF and the bit named I2CBIF was
changed to I2C1BIF in the Interrupt Register Map tables (Table 4-2, Table 4-3,
Table 4-4, Table 4-5, Table 4-6 and Table 4-7)
Added the following devices to the Interrupt Register Map (Table 4-2):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX564F128H
Added the following devices to the Interrupt Register Map (Table 4-3):
• PIC32MX664F064H
• PIC32MX664F128H
Added the following device to the Interrupt Register Map (Table 4-4):
• PIC32MX764F128H
Added the following devices to the Interrupt Register Map (Table 4-5):
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX564F128L
Added the following devices to the Interrupt Register Map (Table 4-6):
• PIC32MX664F064L
• PIC32MX664F128L
Added the following device to the Interrupt Register Map (Table 4-7):
• PIC32MX764F128L
© 2009-2011 Microchip Technology Inc.
DS61156G-page 243
PIC32MX5XX/6XX/7XX
TABLE B-3:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
4.0 “Memory Organization”
(Continued)
Update Description
Made the following bit name changes in the I2C1, I2C3, I2C4 and I2C5 Register
Map (Table 4-11):
•
•
•
•
•
•
•
I2C3BRG SFR: I2C1BRG was changed to I2C3BRG
I2C4BRG SFR: I2C1BRG was changed to I2C4BRG
I2C5BRG SFR: I2C1BRG was changed to I2C5BRG
I2C4TRN SFR: I2CT1DATA was changed to I2CT2ADATA
I2C4RCV SFR: I2CR2DATA was changed to I2CR2ADATA
I2C5TRN SFR: I2CT1DATA was changed to I2CT3ADATA
I2C5RCV SFR: I2CR1DATA was changed to I2CR3ADATA
Added the RTSMD bit and UEN<1:0> bits to the UART1A, UART1B, UART2A,
UART2B, UART3A and UART3B Register Map (Table 4-13)
Added the SIDL bit to the DMA Global Register Map (Table 4-17).
Changed the CM bit to CMR in the System Control Register Map (Table 4-23).
Added the following devices to the I2C2, SPI1, PORTA, PORTC, PORTD,
PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-12,
Table 4-14, Table 4-24, Table 4-27, Table 4-29, Table 4-31, Table 4-33, Table 4-35
and Table 4-36):
•
•
•
•
•
•
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX664F064L
PIC32MX664F128L
PIC32MX764F128L
Added the following devices to the PORTC, PORTD, PORTE, PORTF, PORTG,
Change Notice and Pull-up Register Maps (Table 4-26, Table 4-28, Table 4-30,
Table 4-32, Table 4-34 and Table 4-37):
•
•
•
•
•
•
PIC32MX534F064H
PIC32MX564F064H
PIC32MX564F128H
PIC32MX664F064H
PIC32MX664F128H
PIC32MX764F128H
Added the following devices to the CAN1 Register Map (Table 4-45):
•
•
•
•
•
•
•
•
PIC32MX534F064H
PIC32MX564F064H
PIC32MX564F128H
PIC32MX764F128H
PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX764F128L
Added the following devices to the Ethernet Controller Register Map (Table 4-47):
•
•
•
•
•
•
DS61156G-page 244
PIC32MX664F064H
PIC32MX664F128H
PIC32MX764F128H
PIC32MX664F064L
PIC32MX664F128L
PIC32MX764F128L
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE B-3:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
31.0 “Electrical
Characteristics”
Update Description
Updated the Typical and Maximum DC Characteristics: Operating Current (IDD) in
Table 31-5.
Updated the Typical and Maximum DC Characteristics: Idle Current (IIDLE) in
Table 31-6.
Updated the Typical and Maximum DC Characteristics: Power-Down Current (IPD)
in Table 31-7.
Added DC Characteristics: Program Memory parameters D130a and D132a in
Table 31-11.
Added the Internal Voltage Reference parameter (D305) to the Comparator
Specifications in Table 31-13.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 245
PIC32MX5XX/6XX/7XX
Revision E (July 2010)
Revision F (December 2010)
Minor corrections were incorporated throughout the
document.
The revision includes the following global update:
VCAP/VDDCORE has been changed to: VCAP/VCORE
Other major changes are referenced by their respective
chapter/section in Table B-4:
TABLE B-4:
SECTION UPDATES
Section Name
Update Description
Removed the following Analog Feature: FV tolerant input pins
High-Performance, USB, CAN and
Ethernet 32-bit Flash Microcontrollers (digital pins only)
1.0 “Device Overview”
4.0 “Memory Organization”
Updated the term LIN 1.2 support as LIN support for the peripheral
feature: Six UART modules with: RS-232, RS-485, and LIN support
Updated the value of 64-pin QFN/TQFP pin number for the following pin
names: PMA0, PMA1 and ECRSDV
The following register map tables were updated:
• Table 4-2:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT
- Changed bits 25/9/-24/8 to U5IS<1:0> in IPC12
- Added note 2
• Table 4-3 through Table 4-7:
- Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT
- Changed bits 25/9-24/8 to U5IS<1:0> in IPC12
• Table 4-3:
- Changed bits 24/8 to I2C5BIF in IFS1
- Added note 2
• Table 4-4:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8 to I2C5BIE in IEC1
- Added note 2 references
• Table 4-5:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8 to I2C5BIE in IEC1
- Added note 2 references
• Table 4-6:
- Changed bit 24/8 to I2C5BIF in IFS1
- Updated the bit value of bit 24/8 as I2C5BIE for the IEC1 register.
- Added note 2
• Table 4-7:
- Changed bit 25/9 to I2C5SIF in IFS1
- Changed bit 24/8 as I2C5BIF in IFS1
- Changed bit 25/9 as I2C5SIE in IEC1
- Changed bit 24/8 as I2C5BIE in IEC1
- Added note 2 references
• Added note 2 to Table 4-8
• Updated the All Resets values for the following registers in Table 4-11:
I2C3CON, I2C4CON, I2C5CON and I2C1CON.
• Updated the All Resets values for the I2C2CON register in Table 4-12
DS61156G-page 246
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
TABLE B-4:
SECTION UPDATES (CONTINUED)
Section Name
4.0 “Memory Organization”
(Continued)
© 2009-2011 Microchip Technology Inc.
Update Description
• Table 4-13:
- Changed register U4RG to U1BRG
- Changed register U5RG to U3BRG
- Changed register U6RG to U2BRG
• Table 4-14:
- Updated the All Resets values for the following registers: SPI3STAT,
SPI2STAT and SPI4STAT
• Table 4-15: Updated the All Resets values for the SPI1STAT register
• Table 4-17: Added note 2
• Table 4-19: Added note 2
• Table 4-20: Updated the All Resets values for the CM1CON and
CM2CON registers
• Table 4-21:
- Updated the All Resets values as 0000 for the CVRCON register
- Updated note 2
• Table 4-38: Updated the All Resets values for the PMSTAT register
• Table 4-40: Updated the All Resets values for the CHECON and
CHETAG registers
• Table 4-42: Updated the bit value of bit 29/13 as ‘—’ for the DEVCFG3
register
• Table 4-44:
- Updated the note references in the entire table
- Changed existing note 1 to note 4
- Added notes 1, 2 and 3
- Changed bits 23/7 in U1PWRC to UACTPND
- Changed register U1DDR to U1ADDR
- Changed register U4DTP1 to U1BDTP1
- Changed register U4DTP2 to U1BDTP2
- Changed register U4DTP3 to U1BDTP3
• Table 4-45:
- Updated the All Resets values for the C1CON and C1VEC registers
- Changed bits 30/14 in C1CON to FRZ
- Changed bits 27/11 in C1CON to CANBUSY
- Changed bits 22/6-16/0 in C1VEC to ICODE<6:0>
- Changed bits 22/6-16/0 in C1TREC to RERRCNT<7:0>
- Changed bits 31/15-24/8 in C1TREC to TERRCNT<7:0>
• Table 4-46:
- Updated the All Resets values for the C2CON and C2VEC registers
- Changed bits 30/14 in C1CON to FRZ
- Changed bits 27/11 in C1CON to CANBUSY
- Changed bits 22/6-16/0 in C1VEC register to ICODE<6:0>
- Changed bits 22/6-16/0 in C1TREC register to RERRCNT<7:0>
- Changed bits 31/15-24/8 in C1TREC to TERRCNT<7:0>
DS61156G-page 247
PIC32MX5XX/6XX/7XX
TABLE B-4:
SECTION UPDATES (CONTINUED)
Section Name
7.0 “Interrupt Controller”
8.0 “Oscillator Configuration”
16.0 “Output Compare”
24.0 “Ethernet Controller”
26.0 “Comparator Voltage Reference
(CVREF)”
28.0 “Special Features”
31.0 “Electrical Characteristics”
Update Description
• Updated the following Interrupt Sources in Table 7-1:
- Changed IC2AM – I2C4 Master Event to: IC4M – I2C4 Master Event
- Changed IC3AM – I2C5 Master Event to: IC5M – I2C4 Master Event
- Changed U1E – UART1A Error to: U1E – UART1 Error
- Changed U4E – UART1B Error to: U4E – UART4 Error
- Changed U1RX – UART1A Receiver to: U1RX – UART1 Receiver
- Changed U4RX – UART1B Receiver to: U4RX – UART4 Receiver
- Changed U1TX – UART1A Transmitter to: U1TX – UART1 Transmitter
- Changed U4TX – UART1B Transmitter to: U4TX – UART4 Transmitter
- Changed U6E – UART2B Error to: U6E – UART6 Error
- Changed U6RX – UART2B Receiver to: U6RX – UART6 Receiver
- Changed U6TX – UART2B Transmitter to: U6TX – UART6 Transmitter
- Changed U5E – UART3B Error to: U5E – UART5 Error
- Changed U5RX – UART3B Receiver to: U5RX – UART5 Receiver
- Changed U5TX – UART3B Transmitter to: U5TX – UART5 Transmitter
Updated Figure 8-1
Updated Figure 16-1
Added a note on using the Ethernet controller pins (see note above
Table 24-3)
Updated the note in Figure 26-1
Updated the bit description for bit 10 in Register 28-2
Added notes 1 and 2 to Register 28-4
Updated the Absolute Maximum Ratings:
• Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V 0.3V to +3.6V was updated
• Voltage on VBUS with respect to VSS - 0.3V to +5.5V was added
Updated the maximum value of DC16 as 2.1 in Table 31-4
Updated the Typical values for the following parameters: DC20b, DC20c,
DC21c, DC22c and DC23c (see Table 31-5)
Updated Table 31-11:
• Removed the following DC Characteristics: Programming temperature
0°C ≤TA ≤+70°C (25°C recommended)
• Updated the Minimum value for the Parameter number D131 as 2.3
• Removed the Conditions for the following Parameter numbers: D130,
D131, D132, D135, D136 and D137
• Updated the condition for the parameter number D130a and D132a
Updated the Minimum, Typical and Maximum values for parameter D305
in Table 31-13
Added note 2 to Table 31-18
Updated the Minimum and Maximum values for parameter F20b (see
Table 31-19)
Updated the following figures:
Appendix A: “Migrating from
PIC32MX3XX/4XX to PIC32MX5XX/
6XX/7XX Devices”
DS61156G-page 248
• Figure 31-4
• Figure 31-9
• Figure 31-19
• Figure 31-20
Removed the A.3 Pin Assignments sub-section.
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
Revision G (May 2011)
The revision includes the following global update:
• All references to VDDCORE/VCAP have been
changed to: VCORE/VCAP
• Added references to the new V-Temp temperature
range: -40ºC to +105ºC
TABLE B-5:
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
Major updates are referenced by their respective
section in the following table.
MAJOR SECTION UPDATES
Section Name
Update Description
High-Performance, USB, CAN and
Ethernet 32-bit Flash Microcontrollers
Removed the shading for all D- and D+ pins in all pin diagrams.
1.0 “Device Overview”
Updated the VBUS description in Table 1-1.
2.0 “Guidelines for Getting Started with Added 2.11 “Referenced Sources”.
32-bit Microcontrollers”
4.0 “Memory Organization”
Added Note 3 to the Interrupt Register Map tables (see Table 4-2 through
Table 4-7.
22.0 “10-bit Analog-to-Digital Converter Updated the ADC Conversion Clock Period Block Diagram (see
Figure 22-2).
(ADC)”
26.0 “Comparator Voltage Reference
(CVREF)”
Updated the Comparator Voltage Reference Block Diagram (see
Figure 26-1).
28.0 “Special Features”
Removed the second paragraph from 28.3.1 “On-Chip Regulator and
POR”.
31.0 “Electrical Characteristics”
Added the new V-Temp temperature range (-40ºC to +105ºC) to the
heading of all specification tables.
Updated the Ambient temperature under bias, updated the Voltage on
any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added
Voltage on VBUS with respect to Vss in Absolute Maximum Ratings.
Added the characteristic, DC5a to Operating MIPS vs. Voltage (see
Table 31-1).
Updated or added the following parameters to the Operating Current
(IDD) DC Characteristics: DC20, DC20b, DC23, and DC23b (see
Table 31-5).
Added the following parameters to the Idle Current (IIDLE) DC
Characteristics: DC30b, DC33b, DC34c, DC35c, and DC36c (see
Table 31-6).
Added the following parameters to the Power-down Current (IPD) DC
Characteristics: DC40g, DC40h, DC40i, and DC41g, (see Table 31-7).
Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing
Requirements (Master Mode) (see Table 31-32).
Updated the 10-bit ADC Conversion Rate Parameters (see Table 31-37).
Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion
Timing Requirements (see Table 31-38).
32.0 “Packaging Information”
Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) –
9x9x0.9 mm Body [QFN] packing diagram.
Product Identification System
Added the new V-Temp (V) temperature information.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 249
PIC32MX5XX/6XX/7XX
NOTES:
DS61156G-page 250
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
INDEX
A
D
AC Characteristics ............................................................ 194
10-bit Conversion Rate Parameters.......................... 216
ADC Specifications ................................................... 214
Analog-to-Digital Conversion Requirements............. 217
EJTAG Timing Requirements ................................... 224
Ethernet .................................................................... 213
Internal FRC Accuracy.............................................. 196
Internal RC Accuracy ................................................ 197
OTG Electrical Specifications ................................... 223
Parallel Master Port Read Requirements ................. 221
Parallel Master Port Write ......................................... 222
Parallel Master Port Write Requirements.................. 222
Parallel Slave Port Requirements ............................. 220
PLL Clock Timing...................................................... 196
Analog-to-Digital Converter (ADC).................................... 153
Assembler
MPASM Assembler................................................... 180
DC Characteristics............................................................ 184
I/O Pin Input Specifications ...................................... 189
I/O Pin Output Specifications.................................... 190
Idle Current (IIDLE) .................................................... 186
Operating Current (IDD) ............................................ 185
Power-Down Current (IPD)........................................ 187
Program Memory...................................................... 191
Temperature and Voltage Specifications.................. 184
Development Support ....................................................... 179
Direct Memory Access (DMA) Controller.......................... 129
B
Block Diagrams
ADC Module.............................................................. 153
Comparator I/O Operating Modes............................. 159
Comparator Voltage Reference ................................ 161
Connections for On-Chip Voltage Regulator............. 174
Core and Peripheral Modules ..................................... 31
DMA .......................................................................... 129
Ethernet Controller.................................................... 157
I2C Circuit ................................................................. 146
Input Capture ............................................................ 139
Interrupt Controller .................................................... 121
JTAG Programming, Debugging and Trace Ports .... 175
MCU............................................................................ 49
Output Compare Module........................................... 141
PIC32 CAN Module................................................... 155
PMP Pinout and Connections to External Devices ... 149
Prefetch Module........................................................ 127
Reset System............................................................ 119
RTCC ........................................................................ 151
SPI Module ............................................................... 143
Timer1....................................................................... 135
Timer2/3/4/5 (16-Bit) ................................................. 137
Typical Multiplexed Port Structure ............................ 133
UART ........................................................................ 147
WDT and Power-up Timer ........................................ 173
Brown-out Reset (BOR)
and On-Chip Voltage Regulator................................ 174
C
C Compilers
MPLAB C18 .............................................................. 180
Clock Diagram .................................................................. 125
Comparator
Specifications............................................................ 192
Comparator Module .......................................................... 159
Comparator Voltage Reference (CVref ............................. 161
Configuration Bit ............................................................... 165
Controller Area Network (CAN)......................................... 155
CPU Module........................................................................ 43
Customer Change Notification Service ............................. 253
Customer Notification Service........................................... 253
Customer Support ............................................................. 253
E
Electrical Characteristics .................................................. 183
AC............................................................................. 194
Errata .................................................................................. 29
Ethernet Controller............................................................ 157
External Clock
Timer1 Timing Requirements ................................... 200
Timer2, 3, 4, 5 Timing Requirements ....................... 201
Timing Requirements ............................................... 195
F
Flash Program Memory .................................................... 117
RTSP Operation ....................................................... 117
I
I/O Ports ........................................................................... 133
Parallel I/O (PIO) ...................................................... 134
Instruction Set................................................................... 177
Inter-Integrated Circuit (I2C) ............................................. 145
Internal Voltage Reference Specifications........................ 193
Internet Address ............................................................... 253
Interrupt Controller............................................................ 121
IRG, Vector and Bit Location .................................... 122
M
MCU
Architecture Overview ................................................ 50
Coprocessor 0 Registers ............................................ 52
Core Exception Types ................................................ 53
EJTAG Debug Support............................................... 54
Power Management ................................................... 54
MCU Module....................................................................... 49
Memory Map....................................................................... 60
Memory Maps ............................................. 56, 57, 58, 59, 61
Memory Organization ......................................................... 55
Layout......................................................................... 55
Microchip Internet Web Site.............................................. 253
Migration
PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 239
MPLAB ASM30 Assembler, Linker, Librarian ................... 180
MPLAB Integrated Development Environment Software.. 179
MPLAB PM3 Device Programmer .................................... 182
MPLAB REAL ICE In-Circuit Emulator System ................ 181
MPLINK Object Linker/MPLIB Object Librarian ................ 180
O
Open-Drain Configuration................................................. 134
Oscillator Configuration .................................................... 125
Output Compare ............................................................... 141
P
Packaging ......................................................................... 225
© 2009-2011 Microchip Technology Inc.
DS61156G-page 251
PIC32MX5XX/6XX/7XX
Details ....................................................................... 227
Marking ..................................................................... 225
Parallel Master Port (PMP) ............................................... 149
PIC32 Family USB Interface Diagram............................... 132
Pinout I/O Descriptions (table) ............................................ 32
Power-on Reset (POR)
and On-Chip Voltage Regulator ................................ 174
Power-Saving Features..................................................... 163
CPU Halted Methods ................................................ 163
Operation .................................................................. 163
with CPU Running..................................................... 163
Prefetch Cache ................................................................. 127
Program Flash Memory
Wait State Characteristics......................................... 192
R
Reader Response ............................................................. 254
Real-Time Clock and Calendar (RTCC)............................ 151
Register Maps ............................................................. 62–116
Registers
DDPCON (Debug Data Port Control)........................ 176
DEVCFG0 (Device Configuration Word 0 ................. 166
DEVCFG1 (Device Configuration Word 1 ................. 168
DEVCFG2 (Device Configuration Word 2 ................. 170
DEVCFG3 (Device Configuration Word 3 ................. 171
DEVID (Device and Revision ID) .............................. 172
Resets ............................................................................... 119
Revision History ................................................................ 240
S
Serial Peripheral Interface (SPI) ....................................... 143
Software Simulator (MPLAB SIM)..................................... 181
Special Features ............................................................... 165
T
Timer1 Module .................................................................. 135
Timer2/3, Timer4/5 Modules ............................................. 137
Timing Diagrams
10-bit Analog-to-Digital Conversion (ASAM = 0, SSRC<2:0> = 000) ................................................ 218
10-bit Analog-to-Digital Conversion (CHPS<1:0> = 01,
ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> =
00001)............................................................... 219
CAN I/O..................................................................... 212
EJTAG ...................................................................... 224
External Clock ........................................................... 194
DS61156G-page 252
I/O Characteristics .................................................... 197
I2Cx Bus Data (Master Mode) .................................. 208
I2Cx Bus Data (Slave Mode) .................................... 210
I2Cx Bus Start/Stop Bits (Master Mode)................... 208
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 210
Input Capture (CAPx) ............................................... 201
OCx/PWM................................................................. 202
Output Compare (OCx)............................................. 202
Parallel Master Port Read......................................... 221
Parallel Master Port Write......................................... 222
Parallel Slave Port .................................................... 220
SPIx Master Mode (CKE = 0) ................................... 203
SPIx Master Mode (CKE = 1) ................................... 204
SPIx Slave Mode (CKE = 0) ..................................... 205
SPIx Slave Mode (CKE = 1) ..................................... 206
Timer1, 2, 3, 4, 5 External Clock .............................. 200
UART Reception....................................................... 148
UART Transmission (8-bit or 9-bit Data) .................. 148
Timing Requirements
CLKO and I/O ........................................................... 197
Timing Specifications
CAN I/O Requirements ............................................. 212
I2Cx Bus Data Requirements (Master Mode)........... 209
I2Cx Bus Data Requirements (Slave Mode)............. 211
Input Capture Requirements..................................... 201
Output Compare Requirements................................ 202
Simple OCx/PWM Mode Requirements ................... 202
SPIx Master Mode (CKE = 0) Requirements............ 203
SPIx Master Mode (CKE = 1) Requirements............ 204
SPIx Slave Mode (CKE = 1) Requirements.............. 206
SPIx Slave Mode Requirements (CKE = 0).............. 205
U
UART ................................................................................ 147
USB On-The-Go (OTG) .................................................... 131
V
VCAP/VCORE pin ................................................................ 174
Voltage Reference Specifications..................................... 193
Voltage Regulator (On-Chip) ............................................ 174
W
Watchdog Timer (WDT).................................................... 173
WWW Address ................................................................. 253
WWW, On-Line Support ..................................................... 29
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
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Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
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representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
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Microchip’s customer notification service helps keep
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To register, access the Microchip web site at
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registration instructions.
© 2009-2011 Microchip Technology Inc.
DS61156G-page 253
PIC32MX5XX/6XX/7XX
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
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Device: PIC32MX5XX/6XX/7XX
Literature Number: DS61156G
Questions:
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3. Do you find the organization of this document easy to follow? If not, why?
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7. How would you improve this document?
DS61156G-page 254
© 2009-2011 Microchip Technology Inc.
PIC32MX5XX/6XX/7XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PIC32 MX 5XX F 512 H T - 80 I / PT - XXX
Example:
PIC32MX575F256H-80I/PT:
General purpose PIC32,
32-bit RISC MCU,
256 KB program memory,
64-pin, Industrial temperature,
TQFP package.
Microchip Brand
Architecture
Product Groups
Flash Memory Family
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed
Temperature Range
Package
Pattern
Flash Memory Family
Architecture
MX = 32-bit RISC MCU core
Product Groups
5XX = General purpose microcontroller family
6XX = General purpose microcontroller family
7XX = General purpose microcontroller family
Flash Memory Family
F
= Flash program memory
Program Memory Size 256 = 256K
512 = 512K
Pin Count
H
L
= 64-pin
= 100-pin
Speed
80
= 80 MHz
Temperature Range
I
V
= -40°C to +85°C (Industrial)
= -40°C to +105°C (V-Temp)
Package
PT
PT
PF
MR
BG
=
=
=
=
=
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)
ES = Engineering Sample
64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)
100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array)
© 2009-2011 Microchip Technology Inc.
DS61156G-page 255
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DS61156G-page 256
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05/02/11
© 2009-2011 Microchip Technology Inc.