Data Sheet

NXP Semiconductors
Data sheet: Advance Information
Document Number: PF3001
Rev. 2.0, 3/2016
Power management integrated
circuit (PMIC) for i.MX 7 and i.MX 6
SoloLite/SoloX/UltraLite processors
PF3001
The PF3001 is a SMARTMOS power management integrated circuit (PMIC)
designed specifically for always ON applications with the NXP i.MX 7 and i.MX
6 SoloLite/SoloX/UltraLite application processors. With up to three buck
converters, six linear regulators, RTC supply, and coin-cell charger, the PF3001
can provide power for a complete system, including applications processors,
memory, and system peripherals.
POWER MANAGEMENT
Features:
• Three adjustable high efficiency buck regulators: 2.75 A, 1.5 A, 1.25 A
• Selectable modes: PWM, PFM, APS
• Programmable output voltage, PWM switching frequency, current limit
• Six adjustable general purpose linear regulators
•
•
•
•
EP SUFFIX
98ASA00719D
48 QFN 7.0 X 7.0
Applications:
• IPTV
• Set top boxes
• POS terminals
• Industrial control
• Medical monitoring
• Home automation/security/energy management
Input voltage range: 2.8 V to 4.5 V or 3.7 V to 5.5 V
I2C control
Coin cell charger and always ON RTC supply
-40 °C to +125 °C Operating Junction Temperature
i.MX
PF3001
DDR MEMORY
Switching regulators
SW3
ES SUFFIX
98ASA00933D
48 QFN 7.0 X 7.0
DDR MEMORY
INTERFACE
0.90 – 1.65 V, 1.5A
Processor
ARM Core
SW1
0.70 – 3.30 V, 2.75A
SW2
1.50 – 1.85 V
or 2.5 -3.3 V, 1.25A
Processor SOC
SD-MMC/
NAND Mem.
Li CELL
Charger
SATA
HDD
RESETBMCU
PWRON
STANDBY
SD_VSEL
INTB
SATA - FLASH
NAND - NOR
Interfaces
Parallel control /
GPIOs
I2C
External AMP
Microphones
Speakers
Audio
Codec
I2C
Sensors
Linear regulators
VLDO1 1.8 – 3.3 V,
VLDO2 0.8 – 1.55 V, 250mA
VCC_SD 1.8 – 1.85 V
or 2.85 – 3.3 V, 100mA
V33
2.85 -3.3 V,
350mA
VLDO3 1.8 – 3.3 V,
100mA
VLDO4 1.8 -3.3 V,
350mA
COINCELL
Camera
100mA
Main Supply
2.8 - 5.5 V
WAM
GPS/MIPI
LVDS
Display
Cluster/
HUD
GPS
MIPI
Micro PCIe
HDMI
USB
Ethernet
CAN
Front USB
POD
Rear Seat
Infotainment
Figure 1. PF3001 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© 2016 NXP B.V.
Camera
Rear USB
POD
Table of Contents
1
2
3
4
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
5.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5.3 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 Functional description and application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.2 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.1 Control logic and interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.3.2 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.3.4 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.3.5 Optional front-end input LDO regulator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.3.6 Internal core voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.7 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.3.8 LDO regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
6.3.9 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
6.4 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6.5 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.5.1 State diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.5.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.5.3 Performance characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.6 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6.6.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.6.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
6.6.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.6.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
6.6.5 Specific registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52
6.6.6 Register map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
7.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
8 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
9.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
10 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.1Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
PF3001
2

NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
The PF3001 is available with pre-programmed OTP memory configurations. The devices are identified using the program codes from
Table 1. Details of the start-up programming for each device can be found in Table 32.
Table 1. Orderable part variations
Part number
Temperature (TA)
Package
Programming options
MC32PF3001A1EP
1 (i.MX 7 with DDR3L)
MC32PF3001A2EP
2 (i.MX 7 with LPDDR3)
MC32PF3001A3EP
MC32PF3001A4EP
MC32PF3001A5EP
-40 °C to 85 °C
(For use in consumer
applications)
3 (i.MX 6SX with DDR3L)
98ASA00719D, 48 QFN 7.0 mm x
7.0 mm with exposed pad
4 (i.MX 6SX with DDR3)
6 (i.MX 6UL with LPDDR2)
MC32PF3001A7EP
7 (i.MX 6UL with DDR3L)
PC33PF3001A7ES
-40 °C to 105 °C
(For use in automotive
applications)
98ASA00933D, 48 QFN 7.0 mm x
7.0 mm WF-type (wettable flank)
6 (i.MX 6UL with LPDDR2)
7 (i.MX 6UL with DDR3L)
MC34PF3001A1EP
1 (i.MX 7 with DDR3L)
MC34PF3001A2EP
2 (i.MX 7 with LPDDR3)
MC34PF3001A3EP
MC34PF3001A4EP
MC34PF3001A5EP
-40 °C to 105 °C
(For use in industrial
applications)
(1)
5 (i.MX 6SL with LPDDR2)
MC32PF3001A6EP
PC33PF3001A6ES
Notes
(1)
3 (i.MX 6SX with DDR3L)
98ASA00719D, 48 QFN 7.0 mm x
7.0 mm with exposed pad
4 (i.MX 6SX with DDR3)
(1)
5 (i.MX 6SL with LPDDR2)
MC34PF3001A6EP
6 (i.MX 6UL with LPDDR2)
MC34PF3001A7EP
7 (i.MX 6UL with DDR3L)
Notes
1. For Tape and Reel add an R2 suffix to the part number.
PF3001

NXP Semiconductors
3
GENERAL DESCRIPTION
2
General description
The PF3001 is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX series of multi-media
application processors. It is also capable of providing full power solutions to i.MX 6SL, 6SX, 6UL, and i.MX7processors.
2.1
Features
This section summarizes the PF3001 features.
• Input voltage range to PMIC: 2.8 V to 4.5 V, or 3.7 V to 5.5 V (2)
• Buck regulators
• SW1, 2.75 A; 0.7 V to 1.425 V, 1.8 V, 3.3 V
• SW2, 1.25 A; 1.50 V to 1.85 V, or 2.50 V to 3.30 V
• SW3, 1.5 A; 0.90 V to 1.65 V
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable PWM switching frequency
• LDOs
• VCC_SD, 1.8 V to 1.85 V, or 2.85 V to 3.30 V, 100 mA based on SD_VSEL
• V33, 2.85 V to 3.30 V, 350 mA
• VLDO1, 1.8 V to 3.3 V, 100 mA
• VLDO2, 0.80 V to 1.55 V, 250 mA
• VLDO3, 1.8 V to 3.3 V, 100 mA
• VLDO4, 1.8 V to 3.3 V, 350 mA
• Always ON RTC regulator/switch VSNVS 3.0 V, 1.0 mA
• Battery backed memory including coin cell charger
• I2C interface
Notes
2. 2.8 V to 4.5 V when VIN is used at input. 3.7 V to 5.5 V when VPWR is used as input.
PF3001
4

NXP Semiconductors
GENERAL DESCRIPTION
2.2
Functional block diagram
PF3001 functional internal block diagram
Power generation
Fixed OTP configuration
Voltage and PWRON
configuration fixed
DVS speed fixed
Sequence and
timing fixed
Phasing and
frequency fixed
Switching regulators
SW1
(0.7 V to 1.425 V,1.8 V,
3.3 V, 2.75 A)
Linear regulators
VCC_SD
(1.80 V to 1.85 V, 100 mA)
or (2.85 V to 3.3 V, 100 mA)
V33
Bias & references
Internal core voltage reference
SW2
(1.50 V to 1.85 V, 1.25 A)
or (2.50 V to 3.30 V, 1.25 A)
( 2.85 V to 3.30 V, 350 mA)
VLDO1
(1.8 V to 3.3 V, 100 mA)
SW3
Logic and control
Parallel MCU interface
(0.90 V to 1.65 V, 1.5 A)
Regulator control
I2C communication & registers
VLDO2
(0.80 V to 1.55 V, 250 mA)
VLDO3
(1.8 V to 3.3 V, 100 mA)
VLDO4
(1.8 V to 3.3 V, 350 mA)
Fault detection and protection
Thermal
Current limit
VPWR front end LDO overvoltage indicator
VSNVS
(1.0 V to 3.0 V, 1.0 mA)
RTC supply with coin cell
charger
Figure 2. PF3001 functional block diagram
PF3001

NXP Semiconductors
5
INTERNAL BLOCK DIAGRAM
3
Internal Block Diagram
PF3001
VLDO1
VLDO1IN
100 mA
VLDO1
VLDO2
VLDO2IN
250 mA
VLDO2
VLDO3
VLDO34IN
100 mA
VLDO3
SW1
VLDO4
VLDO4
2.75 A
Buck
350 mA
O/P
Drive
Core Control logic
1.8 V/3.15 V
100 mA
Initialization State Machine
SW2
V33
2.85 V - 3.30 V
350 mA
V33
SW1IN
GNDREF1
VCC_SD
VCC_SD
SW1FB
SW1LX
O/P
Drive
SW2LX
SW2IN
SW2FB
1.25 A
Buck
GNDREF2
Supplies
Control
OTP
VIN2
SW3FB
ICTEST2
CONTROL
I2C
Interface
VDDIO
SCL
SW3
1.5 A
Buck
SDA
O/P
Drive
SW3IN
SW3LX
GNDREF2
DVS
I2C Register
map
VCOREDIG
VCOREREF
Trim-In-Package
Reference
Generation
VCORE
Clocks and
resets
GNDREF
VPWR
LDOG
VREF
LDO
Clocks
32 kHz and 16 MHz
VIN
Li Cell
Charger
LICELL
Best
of
Supply
INTB
RESETBMCU
SD_VSEL
GND
PWRON
ICTEST1
VSNVS
VSNVS
Figure 3. PF3001 simplified internal block diagram
PF3001
6

NXP Semiconductors
37 NC
38 VIN2
39 ICTEST2
40 GNDREF
41 VCORE
42 VIN
48 PWRON
Transparent top view
43 VCOREDIG
Pinout diagram
44 VCOREREF
4.1
45 SDA
Pin connections
47 VDDIO
4
46 SCL
PIN CONNECTIONS
INTB
1
36 LICELL
SD_VSEL
2
35 NC
RESETBMCU
3
34 VSNVS
GND
4
33 VCC_SD
ICTEST1
5
32 V33
SW1FB
6
31 VPWR
EP
NC
11
26 GNDREF2
GNDREF1
12
25 NC
GND 24
27 SW3FB
NC 23
10
VLDO4 22
SW1IN
VLDO34IN 21
28 SW3IN
VLDO3 20
9
SW2FB 19
SW1LX
SW2IN 18
29 SW3LX
SW2LX 17
8
VLDO2IN 16
SW1LX
VLDO2 15
30 LDOG
VLDO1 14
7
VLDO1IN 13
SW1IN
Figure 4. PF3001 pinout diagram
PF3001

NXP Semiconductors
7
PIN CONNECTIONS
4.2
Pin definitions
Table 2. Pin definitions
Pin number
Pin name
Pin
function
Type
1
INTB
O
Digital
Open drain interrupt signal to processor
2
SD_VSEL
I/O
Digital
Input from i.MX processor to select VCC_SD regulator voltage
• SD_VSEL=0, VCC_SD = 2.85 V to 3.3 V
• SD_VSEL= 1, VCC_SD = 1.8 V to 1.85 V
3
RESETBMCU
O
Digital
Open drain reset output to processor
4
GND
I
GND
Ground reference. Connect to ground.
5
ICTEST1
I
Digital and
Analog
6
SW1FB (3)
I
Analog
SW1 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitance or near the load, if possible for best regulation
7
SW1IN (3)
I
Analog
Input to SW1 regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F
decoupling capacitor as close to the pin as possible
8
SW1LX (3)
O
Analog
Switcher 1 switch node connection. Connect to SW1LX and connect to SW1 inductor
9
SW1LX
(3)
O
Analog
Switcher 1 switch node connection. Connect to SW1LX and connect to SW1 inductor
10
SW1IN (3)
I
Analog
Input to SW1 regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F
decoupling capacitor as close to the pin as possible
11
NC
–
Reserved
Definition
Reserved pin. Connect to GND in application
Leave floating
Ground reference for SW1. Connect to GND. Keep away from high current ground
return paths
12
GNDREF1
GND
GND
13
VLDO1IN
I
Analog
VLDO1 input supply. Bypass with a 1.0 F decoupling capacitor as close to the pin as
possible
14
VLDO1
O
Analog
VLDO1 regulator output. Bypass with a 2.2 F ceramic output capacitor
15
VLDO2
O
Analog
VLDO2 regulator output. Bypass with a 4.7 F ceramic output capacitor
16
VLDO2IN
I
Analog
VLDO2 input supply. Bypass with a 1.0 F decoupling capacitor as close to the pin as
possible
17
SW2LX (3)
O
Analog
Switcher 2 switch node connection. Connect to SW2 inductor
18
SW2IN (3)
I
Analog
Input to SW2 regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F
decoupling capacitor as close to the pin as possible
19
SW2FB (3)
I
Analog
SW2 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
20
VLDO3
O
Analog
VLDO3 regulator output. Bypass with a 2.2 F ceramic output capacitor
21
VLDO34IN
I
Analog
VLDO3 and VLDO4 input supply. Bypass with a 1.0 F decoupling capacitor as close to
the pin as possible
22
VLDO4
O
Analog
VLDO4 regulator output. Bypass with a 2.2 F ceramic output capacitor
23
NC
–
Reserved
24
GND
GND
GND
25
NC
–
Reserved
26
GNDREF2
GND
GND
Reference ground for SW2 and SW3 regulators. Connect to GND. Keep away from high
current ground return paths
27
SW3FB (3)
I
Analog
SW3 output voltage feedback pin. Route this trace separately from the high current path
and terminate at the output capacitor or near the load, if possible for best regulation
28
SW3IN (3)
I
Analog
Input to SW3 regulator. Bypass with at least a 4.7 F ceramic capacitor and a 0.1 F
decoupling capacitor as close to the pin as possible
Leave floating
Ground reference. Connect to ground. Keep away from high current ground return paths
Leave floating
PF3001
8

NXP Semiconductors
PIN CONNECTIONS
Table 2. Pin definitions (continued)
Pin number
Pin name
Pin
function
Type
29
SW3LX (3)
O
Analog
Switcher 3 switch node connection. Connect the SW3 inductor
30
LDOG
O
Analog
Connect to gate of front-end LDO external pass P-MOSFET. Leave floating if VPWR
LDO is not used
31
VPWR
I
Analog
Input to optional front-end VPWR LDO for systems with input voltage > 4.5 V
32
V33
O
Analog
V33 regulator output. Bypass with a 4.7 F ceramic output capacitor
33
VCC_SD
O
Analog
Output of VCC_SD regulator. Bypass with a 2.2 F ceramic output capacitor.
34
VSNVS
O
Analog
VSNVS regulator/switch output. Bypass with 0.47 F capacitor to ground.
35
NC
–
Reserved
36
LICELL
I/O
Analog
37
NC
–
Reserved
38
VIN2
I
Analog
39
ICTEST2
I
Digital &
Analog
40
GNDREF
GND
GND
41
VCORE
O
Analog
Internal analog core supply. Bypass with 1.0 F capacitor to ground
42
VIN
I
Analog
Main IC supply. Bypass with 1.0 F capacitor to ground. Connect to system input supply
if voltage  4.5 V. Connect to drain of external PFET when VPWR LDO is used for
systems with input voltage > 4.5 V
43
VCOREDIG
O
Analog
Internal digital core supply. Bypass with 1.0 F capacitor to ground
44
VCOREREF
O
Analog
Main band gap reference. Bypass with 220 nF capacitor to ground
45
SDA
I/O
Digital
I2C data line (open drain). Pull up to VDDIO with a 4.7 kΩ resistor
46
SCL
I
Digital
I2C clock. Pull up to VDDIO with a 4.7 kΩ resistor
47
VDDIO
I
Analog
Supply for I2C bus. Bypass with 0.1 F ceramic capacitor. Connect to 1.7 V to 3.6 V
supply. Ensure VDDIO is always lesser than or equal to VIN
48
PWRON
I
Digital
Power ON/OFF input from processor
-
EP
GND
GND
Expose pad. Functions as ground return for buck and boost regulators. Tie this pad to
the inner and external ground planes through vias to allow effective thermal dissipation
Definition
Leave floating
Coin cell supply input/output. Bypass with 0.1 F capacitor. Connect to optional coin
cell.
Leave floating
Input to VCC_SD, V33 regulators. Connect to VIN rail and bypass with 10 F capacitor
Reserved pin. Connect to GND in application
Ground reference for IC core circuitry. Connect to ground. Keep away from high current
ground return paths
Notes
3. Unused switching regulators should be connected as follows: Pins SWxLX and SWxFB should be unconnected and Pin SWxIN should be
connected to VIN with a 0.1 F bypass capacitor.
PF3001

NXP Semiconductors
9
GENERAL PRODUCT CHARACTERISTICS
5
General product characteristics
5.1
Maximum ratings
Table 3. Maximum voltage ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol
Description
Value
Unit
Notes
(4)
Electrical ratings
VPWR, ICTEST1, ICTEST2, LDOG
–
-0.3 to 7.5
V
VIN, VIN2, VLDO1IN, SW1IN, SW2IN, SW3IN,
SW1LX, SW2LX, SW3LX
–
-0.3 to 4.8
V
INTB, SD_VSEL, RESETBMCU, SW1FB,
SW2FB, SW3FB, VLDO1, VLDO2IN, VLDO3,
VLDO34IN, VLDO4, V33, VCC_SD, VSNVS,
LICELL, VCORE, SDA, SCL, VDDIO, PWRON
–
-0.3 to 3.6
V
VLDO2 linear regulator output
-0.3 to 2.5
V
VCOREDIG
Digital core supply voltage output
-0.3 to 1.65
V
VCOREREF
Bandgap reference voltage output
-0.3 to 1.5
V
2000
500
V
VLDO2
VESD
ESD ratings
• Human body model
• Charge device model
(5)
Notes
4. 7.5 V Maximum DC voltage rated.
5. ESD testing is performed in accordance with the Human body model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge device model
(CDM), Robotic (CZAP = 4.0 pF).
PF3001
10

NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
5.2
Thermal characteristics
Table 4. Thermal ratings
Symbol
Description (rating)
Min.
Max.
Unit
Notes
Thermal ratings
TA
Ambient operating temperature range
• Industrial version
• Consumer version
-40
-40
105
85
C
TJ
Operating junction temperature range
-40
125
C
Storage temperature range
-65
150
C
–
(8)
C
(7) (8)
TST
TPPRT
Peak package reflow temperature
(6)
QFN48 thermal resistance and package dissipation ratingS
RJA
Junction to ambient, natural convection
• Four layer board (2s2p)
• Eight layer board (2s6p)
–
–
24
15
°C/W
(9) (10)
(11)
RJB
Junction to Board
–
11
°C/W
(12)
RJCBOTTOM
Junction to case bottom
–
1.4
°C/W
(13)
JT
Junction to package top
• Natural convection
–
1.3
°C/W
(14)
Notes
6. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See thermal
protection thresholds for thermal protection features.
7. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
8. NXP's package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and
moisture sensitivity levels (MSL), Go to www.nxp.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all
orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics..
9. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
10. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
11. Per JEDEC JESD51-6 with the board horizontal.
12. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
13. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
14. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC 
JESD51-2. When Greek letters () are not available, the thermal characterization parameter is written as Psi-JT.
PF3001

NXP Semiconductors
11
GENERAL PRODUCT CHARACTERISTICS
5.3
Current consumption
The current consumption of the individual blocks is described in detail in the following table.
Table 5. Current consumption summary
TA= -40 °C to 105 °C, VPWR= 0 V (External pass FET is not populated), VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V,
VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VPWR = 0 V,
VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode
PF3001 conditions
Coin Cell
VSNVS from LICELL, All other blocks
off, VIN = 0.0 V
System conditions
Typ.
Max.
Unit
Notes
No load on VSNVS
4.0
7.0
A
(15) (16)
Off
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 kHz RC on
All other blocks off
VIN UVDET
No load on VSNVS, PMIC able to
wake-up
16
25
A
(15) (16)
ON
VSNVS from VIN
SW1 in APS
SW2 in APS
SW3 in APS
Trimmed 16 MHz RC enabled
Trimmed reference active, VLDO1-4
enabled
V33 enabled
VCC_SD enabled
No load on any of the regulators.
1.2
mA
Notes
15. At 25 °C only.
16. When VIN is below the UVDET threshold, in the range of 1.8 V VIN < 2.65 V, the quiescent current increases by 50 A, typically.
PF3001
12

NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
5.4
Electrical characteristics
Table 6. Electrical characteristics – front-end input LDO
All parameters are specified at TA = -40 °C to 105 °C, VPWR = 5.0 V, VIN = 4.4 V, IVIN = 300 mA, typical external component values, unless
otherwise noted. Typical values are characterized at VPWR = 5.0 V, VIN = 4.4 V, IVIN = 300 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
4.6
3.7
–
–
5.5
4.6
V
(17)
Front end input LDO (VPWR LDO)
VPWR
Operating input voltage
• In regulation
• In dropout operation
VIN
On mode output voltage, 4.6 V < VPWR < 5.5 V, 
0.0 mA < IVIN < 3000 mA
4.3
4.4
4.55
V
IVIN
Operating load current at VIN, 3.7 V < VPWR < 5.5 V
0.0
–
3.0
A
–
5.0
10
mA
ILDOGQ
ON mode quiescent current, No load,
Low power mode output voltage, 4.6 V < VPWR < 5.5 V 
0.0 mA < IVIN < 1.0 mA
3.7
4.5
V
VPWROFFMODE
Off mode output voltage, (CL = 100 F) 4.6 V < VPWR < 5.5 V, 
0.0 mA < IVIN < 35 A
3.2
4.8
V
VPWRUV
VPWR undervoltage threshold (upon undervoltage condition the
external pass FET is turned off)
3.1
–
3.7
V
VPWROV
VPWR overvoltage threshold (upon overvoltage condition interrupt is
asserted at INTB)
5.5
–
6.5
V
VIN
IVINUVILIMIT
VPWR LDO current limit under VIN short-circuit (VIN < UVDET)
–
–
300
mA
IVINLEAKAGE
Reverse leakage current from VIN to VPWR, No external pass FET,
VPWR is grounded, device is in OFF state
–
–
1.0
µA
VPWR LDO Off mode quiescent current
–
–
75
A
IVPWROFF
(18)
Notes
17. While the front end LDO can handle spikes up to 7.5 V at VPWR for as long as 200 µs, the circuit is not expected to be continuously operated
when VPWR is above 5.5 V.
18. This specification gives the leakage current in the VPWR LDO block. Total OFF mode current includes the quiescent current from the other blocks
as specified in Table 5.
PF3001

NXP Semiconductors
13
GENERAL PRODUCT CHARACTERISTICS
Table 7. Static electrical characteristics – SW1
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, typical external component
values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
(19)
Switch mode supply SW1
VSW1IN
Operating input voltage
2.8
–
4.5
V
VSW1
Nominal output voltage
–
Table 40
–
V
-25
25
mV
-25
25
mV
45
mV
-6.0
6.0
%
-6.0
6.0
%
Output voltage accuracy
• PWM, APS, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 2.75 A
0.7 V VSW1 1.2 V
• PFM, APS, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 2.75A
1.225 V < VSW1 < 1.425 V
• PFM, steady state, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 150 mA
1.8 V  VSW1 1.425 V
• PWM, APS, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 2.75A
1.8 V < VSW1 < 3.3 V
• PFM, steady state, 2.8 V < VSW1IN < 4.5 V, 0 < ISW1 < 150 mA
1.8 V VSW1 3.3 V
VSW1ACC
ISW1
ISW1Q
•
Rated output load current,
2.8 V  VSW1IN 4.5 V, 0.7 V VSW1 1.425 V, 1.8 V, 3.3 V
Quiescent current
• PFM mode
• APS mode
-45
–
–
–
2750
mA
–
–
22
300
–
–
µA
3.5
2.6
5.5
4.0
7.5
5.4
A
ISW1LIM
Current limiter peak current detection , current through inductor
• SW1ILM = 0 (default)
• SW1ILM = 1
VSW1
Output ripple
–
5.0
–
mV
Discharge resistance
–
600
–

RSW1DIS
Notes
19. The maximum operating input voltage is 4.55 V when VPWR LDO is used
Table 8. Dynamic electrical characteristics - SW1
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA, typical external component
values, fSW1 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW1IN = 3.6 V, VSW1 = 1.2 V, ISW1 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Start-up Overshoot, ISW1 = 0 mA, slew rate = 25 mV/4 s, 
VIN = VSW1IN = 4.5 V, VSW1 = 1.425 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW1 = 0 mA, 
slew rate = 25 mV/4 s, VIN = VSW1IN = 4.5 V, VSW1 = 1.425 V
–
–
500
µs
Notes
Switch mode supply SW1 (single phase)
VSW1OSH
tONSW1
PF3001
14

NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 9. Static electrical characteristics – SW2
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(20), (21)
Switch mode supply SW2
VSW2IN
Operating Input Voltage
2.8
–
4.5
V
VSW2
Nominal output voltage
–
Table 42
–
V
-3.0
-6.0
–
–
3.0
6.0
%
-6.0
-6.0
–
–
6.0
6.0
–
–
1250
ISW2Q
Quiescent current
• PFM mode
• APS mode (low output voltage settings, CTL_SW2_HL = 0)
• APS mode (high output voltage settings, CTL_SW2_HL = 1)
–
–
–
23
145
305
–
–
–
ISW2LIM
Current limiter peak current detection, current through inductor
• SW2ILM = 0 (default)
• SW2ILM = 1
1.625
1.235
2.5
1.9
3.375
2.565
A
VSW2
Output ripple
–
5.0
–
mV
RONSW2P
SW2 P-MOSFET RDS(on) at VIN = VSW2IN = 3.3 V
–
215
245
m
RONSW2N
SW2 N-MOSFET RDS(on) at VSW2IN = VSW2IN = 3.3 V
–
258
326
m
ISW2PQ
SW2 P-MOSFET leakage current, VIN = VSW2IN = 4.5 V
–
–
10.5
µA
ISW2NQ
SW2 N-MOSFET leakage current, VIN = VSW2IN = 4.5 V
–
–
3.0
µA
RSW2DIS
Discharge resistance during OFF mode
–
600
–

VSW2ACC
ISW2
Output voltage accuracy
• PWM, APS, 2.8 V  VSW2IN 4.5 V, 0  ISW2  1.25 A
• 1.50 V  VSW2  1.85 V
• 2.5 V  VSW2  3.3 V
• PFM, 2.8 V  VSW2IN 4.5 V, 0  ISW2  50 mA
• 1.50 V  VSW2  1.85 V
• 2.5 V  VSW2  3.3 V
Rated output load current, 
2.8 V < VSW2IN < 4.5 V, 1.50 V < VSW2 < 1.85 V, 2.5 V < VSW2 < 3.3 V
mA
(22)
µA
Notes
20. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
21. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any PF3001 regulator, or external system supply.
22. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VSW2IN - VSW2) = ISW2*
(DCR of Inductor +RONSW2P + PCB trace resistance).
Table 10. Dynamic electrical characteristics - SW2
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, typical external component
values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values are characterized at VIN = VSW2IN = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISW2 = 0.0 mA, slew rate = 25 mV/4 s, 
VIN = VSW2IN = 4.5 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW2 = 0.0 mA, 
slew rate = 25 mV/4 s, VIN = VSW2IN = 4.5 V
–
–
500
µs
Notes
Switch Mode Supply SW2
VSW2OSH
tONSW2
PF3001

NXP Semiconductors
15
GENERAL PRODUCT CHARACTERISTICS
Table 11. Static electrical characteristics – SW3
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Parameter
Symbol
Min.
Typ.
Max.
Unit
Notes
(23)
Switch mode supply SW3
VSW3IN
Operating input voltage
2.8
–
4.5
V
VSW3
Nominal output voltage
–
Table 44
–
V
-3.0
–
3.0
-6.0
–
6.0
–
–
1500
mA
–
–
50
150
–
–
µA
1.95
1.45
3.0
2.25
4.05
3.05
A
VSW3ACC
ISW3
ISW3Q
Output voltage accuracy
• PWM, APS, 2.8 V < VSW3IN < 4.5 V, 0 < ISW3 < 1.5 A, 
0.9 V < VSW3 < 1.65 V
• PFM, steady state (2.8 V < VSW3IN < 4.5 V, 0 < ISW3 < 50 mA), 
0.9 V < VSW3 < 1.65 V
Rated output load current, 2.8 V < VSW3IN < 4.5 V, 
0.9 V < VSW3 < 1.65 V, PWM, APS mode
Quiescent current
• PFM mode
• APS mode
%
ISW3LIM
Current limiter peak current detection, current through inductor
• SW3ILIM = 0 (default)
• SW3ILIM = 1
VSW3
Output ripple
–
5.0
–
mV
RONSW3P
SW3 P-MOSFET RDS(on) at VIN = VSW3IN = 3.3 V
–
205
235
m
RONSW3N
SW3 N-MOSFET RDS(on) at VIN = VSW3IN = 3.3 V
–
250
315
m
ISW3PQ
SW3 P-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
12
µA
ISW3NQ
SW3 N-MOSFET leakage current, VIN = VSW3IN = 4.5 V
–
–
4.0
µA
RSW3DIS
Discharge resistance during off mode
–
600
–

(24)
Notes
23. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
24. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation: (VSW3IN - VSW3) =
ISW3* (DCR of Inductor +RONSW3P + PCB trace resistance).
Table 12. Dynamic Electrical Characteristics - SW3
All parameters are specified at TA = -40 °C to 105 °C, VIN = VSW 3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, typical external component
values, fSW3 = 2.0 MHz. Typical values are characterized at VIN = VSW3IN = 3.6 V, VSW3 = 1.5 V, ISW3 = 100 mA, and 25 °C, unless
otherwise noted.
Symbol
VSW3OSH
tONSW3
Parameter
Min.
Typ.
Max.
Unit
Start-up overshoot, ISW3 = 0.0 mA, slew rate = 25 mV/4 s, VIN =
VSW3IN = 4.5 V
–
–
66
mV
Turn-on time, enable to 90% of end value, ISW3 = 0 mA, 
slew rate = 25 mV/4 s, VIN = VSW3IN = 4.5 V
–
–
500
µs
Notes
PF3001
16

NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 13. Static electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Operating input voltage
• Valid coin cell range
• Valid VIN
1.8
2.25
–
–
3.3
4.5
V
(25)
ISNVS
Operating load current, VINMIN < VIN < VINMAX
1.0
–
1000
A
VSNVS
Output voltage
-5.0
• 5.0 A < ISNVS < 1000 A (OFF), 3.20 V < VIN < 4.5 V
-5.0
• 5.0 A < ISNVS < 1000A (ON), 3.20 V < VIN < 4.5 V
• 50A < ISNVS < 1000 A (coin cell mode), 2.84 V < VCOIN < 3.3 V VCOIN-0.10
3.0
3.0
–
7.0
5.0
VCOIN
%
%
V
–
–
110
mV
1100
–
6750
A
Operating input voltage, valid coin cell range
1.8
–
3.3
V
Operating load current
1.0
–
1000
A
–
–
100

VSNVS
VIN
VSNVSDROP
ISNVSLIM
Dropout voltage, 2.85 V < VIN < 2.9 V, 1.0 A < ISNVS < 1000 A
Current limit, VIN > VTH1
VSNVS DC, switch
VLICELL
ISNVS
RDSONSNVS
Internal switch RDS(on), VCOIN = 2.6 V
Notes
25. The maximum operating input voltage is 4.55 V when VPWR LDO is used
Table 14. Dynamic electrical characteristics - VSNVS
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, typical external component values, unless
otherwise noted. Typical values are characterized at VIN = 3.6 V, VSNVS = 3.0 V, ISNVS = 5.0 A, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(26),(27)
VSNVS
VSNVSTON
Turn-on time (load capacitor, 0.47 F), from VIN = VTH1 to 90% of
VSNVS, VCOIN = 0.0 V, ISNVS = 5.0 A
–
–
24
ms
VSNVSOSH
Start-up overshoot, ISNVS = 5.0 A
–
40
70
mV
VSNVSLOTR
Transient load response, 3.2 < VIN 4.5 V, ISNVS = 100 to 1000 A
2.8
–
–
V
VTL1
VIN falling threshold (VIN powered to coin cell powered)
2.45
2.70
3.05
V
VTH1
VIN rising threshold (coin cell powered to VIN powered)
2.50
2.75
3.10
V
VIN threshold hysteresis for VTH1-VTL1
5.0
–
–
mV
Output voltage during crossover, VCOIN > 2.9 V, switch to LDO: 
VIN > VTH1, ISNVS = 100 A, LDO to switch: VIN < VTL1, 
ISNVS = 100 A
2.45
–
–
V
VHYST1
VSNVSCROSS
Notes
26. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to 3.0 V.
27.
From coin cell insertion to VSNVS = 1.0 V, the delay time is typically 400 ms.
PF3001

NXP Semiconductors
17
GENERAL PRODUCT CHARACTERISTICS
Table 15. Static electrical characteristics - VLDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
VLDO1NOM
+0.250
–
–
4.5
4.5
V
(28), (29)
VLDO1 linear regulator
VLDO1IN
Operating input voltage
• 1.8 V  VLDO1NOM  2.5 V
• 2.6 V  VLDO1NOM  3.3 V
VLDO1NOM
Nominal output voltage
–
Table 47
–
V
ILDO1
Operating load current
0.0
–
100
mA
VLDO1TOL
Output voltage tolerance, VLDO1INMIN < VLDO1IN < 4.5 V, 0.0 mA <
ILDO1 < 100 mA, VLDO1 = 1.8 V to 3.3 V
-3.0
–
3.0
%
ILDO1Q
Quiescent current, no load, change in IVIN, when VLDO1 enabled
–
13
–
A
122
167
280
mA
ILDO1LIM
Current limit, ILDO1 when VLDO1 is forced to VLDO1NOM/2
Notes
28. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
29. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any PF3001 regulator, or external system supply.
Table 16. Dynamic electrical characteristics - VLDO1
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO1IN = 3.6 V, VLDO1 = 3.3 V, ILDO1 = 10 mA,
and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
35
52
40
60
–
–
dB
–
–
–
-114
-129
-135
-102
-123
-130
Notes
VLDO1 linear regulator
PSRRVLDO1
PSRR, ILDO1 = 75 mA, 20 Hz to 20 kHz
• VLDO1 = 1.8 V to 3.3 V, VLDO1IN = VLDO1INMIN + 100 mV
• VLDO1 = 1.8 V to 3.3 V, VLDO1IN = VLDO1NOM + 1.0 V
Output noise density, VLDO1IN = VLDO1INMIN, ILDO1 = 75 mA
NOISEVLDO1
• 100 Hz to <1.0 kHz
• 1.0 kHz to <10 kHz
• 10 kHz to 1.0 MHz
dBV/ Hz
tONLDO1
Turn-on time, enable to 90% of end value, VLDO1IN = VLDO1INMIN to
4.5 V, ILDO1 = 0.0 mA, all output voltage settings
60
–
500
s
tOFFLDO1
Turn-off time, disable to 10% of initial value, VLDO1IN = VLDO1INMIN,
ILDO1 = 0.0 mA
–
–
10
ms
LDO1OSHT
Start-up overshoot, VLDO1IN = VLDO1INMIN to 4.5 V, ILDO1 = 0.0 mA
–
1.0
2.0
%
PF3001
18

NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 17. Static electrical characteristics - VLDO2
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO2IN = 3.0 V, VLDO2 = 1.55 V, ILDO2 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO2IN = 3.0 V, VLDO2 = 1.55 V, 
ILDO2 = 10 mA and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
VLDO2 linear regulator
VLDO2IN
Operating input voltage
1.75
–
3.40
V
VLDO2NOM
Nominal output voltage
–
Table 47
–
V
ILDO2
Operating load current
0.0
–
250
mA
VLDO2TOL
Output voltage tolerance, 1.75 V < VLDOIN1 < 3.40 V, 0.0 mA < ILDO2
< 250 mA, VLDO2 = 0.8 V to 1.55 V
-3.0
–
3.0
%
ILDO2Q
Quiescent current, no load, change in IVIN and IVLDO2IN, When VLDO2
enabled
–
16
–
A
333
417
612
mA
ILDO2LIM
Current limit, ILDO2 when VLDO2 is forced to VLDO2NOM/2
Table 18. Dynamic electrical characteristics - VLDO2
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO2IN = 3.0 V, VLDO2 = 1.55 V, ILDO2 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO2IN = 3.0 V, VLDO2 = 1.55 V, ILDO2 =
10 mA and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
50
37
60
45
–
–
dB
–
–
–
-108
-118
-124
-100
-108
-112
60
–
500
s
Turn-off time, disable to 10% of initial value, VLDO2IN = 1.75 V, 
ILDO2 = 0.0 mA
–
–
10
ms
Start-up overshoot, VLDO2IN = 1.75 V to 3.4 V, ILDO2 = 0.0 mA
–
1.0
2.0
%
Notes
VLDO2 linear regulator
PSRR, ILDO2 = 187.5 mA, 20 Hz to 20 kHz
PSRRVLDO2
NOISEVLDO2
tONLDO2
tOFFLDO2
LDO2OSHT
• VLDO2 = 0.8 V to 1.55 V
• VLDO2 = 1.1 V to 1.55 V
Output noise density, VLDO2IN = 1.75 V, ILDO2 = 187.5 mA
• 100 Hz to <1.0 kHz
• 1.0 kHz to <10 kHz
• 10 kHz to 1.0 MHz
Turn-on time, enable to 90% of end value, VLDO2IN = 1.75 V to 3.4 V,
ILDO2 = 0.0 mA
dBV/Hz
PF3001

NXP Semiconductors
19
GENERAL PRODUCT CHARACTERISTICS
Table 19. Static electrical characteristics – VCC_SD
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VCC_SD = 1.85 V, IVCC_SD = 10 mA, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VCC_SD = 1.85 V, IVCC_SD = 10 mA, and 25 °C, unless otherwise
noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
(30), (31),
(32)
VCC_SD linear regulator
VIN
Operating input voltage
2.8
–
4.5
V
VCC_SDNOM
Nominal output voltage
–
Table 50
–
V
IVCC_SD
Operating load current
0.0
–
100
mA
VCC_SDTOL
Output voltage accuracy, 2.8 V < VIN < 4.5 V, 0.0 mA < IVCC_SD <
100 mA, VCC_SD[1:0] = 00 to 11
-3.0
–
3.0
%
IVCC_SDQ
Quiescent current, no load, change in IVIN and IVIN2, when VCC_SD
enabled
–
13
–
A
122
167
280
mA
IVCC_SDLIM
Current limit, IVCC_SD when VCC_SD is forced to VCC_SDNOM/2
Notes
30. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V.
31. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
32. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied
at the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between
1.8 V and 3.3 V. This voltage can be an output from any PF3001 regulator, or external system supply.
Table 20. Dynamic electrical characteristics - VCC_SD
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VCC_SD = 1.85 V, IVCC_SD = 10 mA, typical external component values,
unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VCC_SD = 1.85 V, IVCC_SD = 10 mA, and 25 °C, unless otherwise
noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
35
52
40
60
–
–
dB
–
–
–
-114
-129
-135
-102
-123
-130
Notes
VCC_SD linear regulator
PSRRVCC_SD
PSRR, IVCC_SD = 75 mA, 20 Hz to 20 kHz
• VCC_SD[1:0] = 00 - 10, VIN = 2.8 V + 100 mV
• VCC_SD[1:0] = 10 - 11, VIN = VCC_SDNOM + 1.0 V
Output noise density, VIN = 2.8V, IVCC_SD = 75 mA
NOISEVCC_SD
• 100 Hz to <1.0 kHz
• 1.0 kHz to <10 kHz
• 10 kHz to 1.0 MHz
dBV/Hz
tONVCC_SD
Turn-on time, enable to 90% of end value, VIN = 2.8 V to 4.5 V,
IVCC_SD = 0.0 mA
60
–
500
s
tOFFVCC_SD
Turn-off time, disable to 10% of initial value, VIN = 2.8 V, 
IVCC_SD = 0.0 mA
–
–
10
ms
VCC_SDOSHT
Start-up overshoot, VIN = 2.8 V to 4.5 V, IVCC_SD = 0.0 mA
–
1.0
2.0
%
PF3001
20

NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 21. Static electrical characteristics – V33
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, V33 = 3.3 V, IV33 = 10 mA, typical external component values, unless
otherwise noted. Typical values are characterized at VIN = 3.6 V, V33 = 3.3 V, IV33 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min
Typ
Max
Unit
Notes
2.8
–
4.5
V
(33), (34),
(35)
V33 linear regulator
VIN
Operating input voltage, 2.9 V  V33NOM  3.6 V
V33NOM
Nominal output voltage
–
Table 49
–
V
IV33
Operating load current
0.0
–
350
mA
Output voltage tolerance, 2.8 V < VIN < 4.5 V, 0.0 mA < IV33 < 350 mA,
V33[1:0] = 00 to 11
-3.0
–
3.0
%
–
13
–
A
435
584.5
950
mA
V33TOL
IV33Q
IV33LIM
Quiescent current, no load, change in IVIN, when V33 enabled
Current limit, IV33 when V33 is forced to V33NOM/2
Notes
33. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
34. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
35. Minimum operating voltage is 2.8 V with a valid LICELL voltage (1.8 V to 3.3 V). Minimum operating voltage is 3.1 V when no voltage is applied at
the LICELL pin. If operation down to 2.8 V is required for systems without a coin cell, connect the LICELL pin to any system voltage between 1.8 V
and 3.3 V. This voltage can be an output from any PF3001 regulator, or external system supply.
Table 22. Dynamic electrical characteristics – V33
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, V33 = 3.3 V, IV33 = 10 mA, typical external component values, unless
otherwise noted. Typical values are characterized at VIN = 3.6 V, V33 = 3.3 V, IV33 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
52
60
–
dB
(36)
–
–
–
-114
-129
-135
-102
-123
-130
Turn-on time, enable to 90% of end value, VIN = 2.8 V, to 4.5 V, 
IV33 = 0.0 mA
60
–
500
s
tOFFV33
Turn-off time, disable to 10% of initial value, VIN = 2.8 V, 
IV33 = 0.0 mA
–
–
10
ms
V33OSHT
Start-up overshoot, VIN = 2.8 V to 4.5 V, IV33 = 0.0 mA
–
1.0
2.0
%
V33 linear regulator
PSRRV33
PSRR, IV33 = 262.5 mA, 20 Hz to 20 kHz, V33[1:0] = 00 - 11, 
VIN = V33NOM + 1.0 V
Output noise density, VIN = 2.8 V, IV33 = 262.5 mA
NOISEV33
tONV33
• 100 Hz to <1.0 kHz
• 1.0 kHz to <10 kHz
• 10 kHz to 1.0 MHz
dBV/Hz
Notes
36. When the LDO Output voltage is set above 2.6 V the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
PF3001

NXP Semiconductors
21
GENERAL PRODUCT CHARACTERISTICS
Table 23. Static electrical characteristics – VLDO3
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO3 = 3.3 V, ILDO3 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO3 = 3.3 V,
ILDO3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
VLDO3NOM
+0.250
–
–
3.6
3.6
V
(37)
VLDO3 linear regulator
VLDO34IN
Operating input voltage
• 1.8 V  VLDO3NOM  2.5 V
• 2.6 V  VLDO3NOM  3.3 V
VLDO3NOM
Nominal output voltage
–
Table 48
–
V
ILDO3
Operating load current
0.0
–
100
mA
Output voltage tolerance, VLDO34INMIN < VLDO34IN < 4.5 V, 
0.0 mA < ILDO3 < 100 mA, VLDO3 = 1.8 V to 3.3 V
-3.0
–
3.0
%
–
13
–
A
122
167
280
mA
VLDO3TOL
ILDO3Q
ILDO3LIM
Quiescent current, no load, change in IVIN and IVLDO34IN, When VLDO3
enabled
Current limit, ILDO3 when VLDO3 is forced to VLDO3NOM/2
Notes
37. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
Table 24. Dynamic electrical characteristics – VLDO3
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO3 = 3.3 V, ILDO3 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO3 = 3.3 V,
ILDO3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
• VLDO3 = 1.8 V to 3.3 V, VLDO34IN = VLDO34INMIN + 100 mV
• VLDO3 = 1.8 V to 3.3 V, VLDO34IN = VLDO3NOM + 1.0 V
35
52
40
60
–
–
dB
Output noise density, VLDO34IN = VLDO34INMIN, ILDO3 = 75 mA
• 100 Hz to <1.0 kHz
• 1.0 kHz to <10 kHz
• 10 kHz to 1.0 MHz
–
–
–
-114
-129
-135
-102
-123
-130
Notes
VLDO3 linear regulator
PSRR, ILDO3 = 75 mA, 20 Hz to 20 kHz
PSRRVLDO3
NOISEVLDO3
dBV/Hz
tONLDO3
Turn-on time, enable to 90% of end value, VLDO34IN = VLDO34INMIN to
4.5 V, ILDO3 = 0.0 mA
60
–
500
s
tOFFLDO3
Turn-off time, disable to 10% of initial value, VLDO34IN = VLDO34INMIN,
ILDO3 = 0.0 mA
–
–
10
ms
LDO3OSHT
Start-up overshoot, VLDO34IN = VLDO34IN2MIN to 4.5 V, ILDO3 = 0.0 mA
–
1.0
2.0
%
PF3001
22

NXP Semiconductors
GENERAL PRODUCT CHARACTERISTICS
Table 25. Static electrical characteristics - VLDO4
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO4 = 3.3 V, ILDO4 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO4 = 3.3 V,
ILDO4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
2.8
VLDO4NOM
+0.250
–
–
3.6
3.6
V
(38)
VLDO4 linear regulator
VLDO34IN
Operating input voltage
• 1.8 V  VLDO4NOM  2.5 V
• 2.6 V  VLDO4NOM  3.3 V
VLDO4NOM
Nominal output voltage
–
Table 48
–
V
ILDO4
Operating load current
0.0
–
350
mA
Output voltage tolerance, VLDO34INMIN < VLDO34IN < 4.5 V, 
0.0 mA < ILDO3 < 100 mA, VLDO4 = 1.9 V to 3.3 V
-3.0
–
3.0
%
–
13
–
A
Current limit, ILDO4 when VLDO4 is forced to VLDO4NOM/2
435
584.5
950
mA
PSRR, ILDO4 = 262.5 mA, 20 Hz to 20 kHz
• VLDO4 = 1.9 V to 3.3 V, VLDO34IN = VLDO34INMIN + 100 mV
• VLDO4 = 1.9 V to 3.3 V, VLDO34IN = VLDO4NOM + 1.0 V
35
52
40
60
–
–
dB
VLDO4TOL
ILDO4Q
ILDO4LIM
PSRRVLDO4
Quiescent current, no load, change in IVIN and IVLDO34IN, When VLDO4
enabled
Notes
38. The maximum operating input voltage is 4.55 V when VPWR LDO is used.
Table 26. Dynamic electrical characteristics - VLDO4
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO4 = 3.3 V, ILDO4 = 10 mA, typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, VLDO34IN = 3.6 V, VLDO4 = 3.3 V,
ILDO4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
–
–
–
-114
-129
-135
-102
-123
-130
Unit
Notes
VLDO4 linear regulator
NOISEVLDO4
Output noise density, VLDO34IN2 = VLDO34INMIN, ILDO4 = 262.5 mA
• 100 Hz to <1.0 kHz
• 1.0 kHz to <10 kHz
• 10 kHz to 1.0 MHz
dBV/Hz
tONLDO4
Turn-on time, enable to 90% of end value, VLDO34IN = VLDO34INMIN,
4.5 V, ILDO4 = 0.0 mA
60
–
500
s
tOFFLDO4
Turn-off time, disable to 10% of initial value, VLDO34IN = VLDO34INMIN,
ILDO4 = 0.0 mA
–
–
10
ms
Start-up overshoot, VLDO34IN = VLDO34INMIN, 4.5 V, ILDO4 = 0.0 mA
–
1.0
2.0
%
LDO4OSHT
Table 27. Static electrical characteristics - Coin Cell
All parameters are specified at TA = -40 °C to 105 °C, VIN = 3.6 V, typical external component values, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
Coin cell
VCOINACC
Charge voltage accuracy
-100
–
-100
mV
ICOINACC
Charge current accuracy
-30
–
30
%
ICOIN
Coin cell charge current
• ICOINHI (in On mode)
• ICOINLO (in On mode)
–
–
60
10
–
–
A
PF3001

NXP Semiconductors
23
GENERAL PRODUCT CHARACTERISTICS
Table 28. Static electrical characteristics - Digital I/O
All parameters are specified at TA = -40 °C to 105 °C, VDDIO = 1.7 V to 3.6 V, VPWR = 0 V (external FET not populated), and typical external
component values and full load current range, unless otherwise noted.
Pin Name
PWRON
RESETBMCU
Parameter
• VL
• VH
• VOL
• VOH
Load condition
Min.
Max.
Unit
–
–
0.0
0.8 * VSNVS
0.2 * VSNVS
3.6
V
-2.0 mA
Open Drain
0.0
0.7 * VDDIO
0.4 * VDDIO
VDDIO
V
–
–
0.0
0.8 * VDDIO
0.2 * VDDIO
3.6
V
SCL
• VL
• VH
SDA
• VL
• VH
• VOL
• VOH
–
–
-2.0 mA
Open Drain
0.0
0.8 * VDDIO
0.0
0.7 * VDDIO
0.2 * VDDIO
3.6
0.4 * VDDIO
VDDIO
V
INTB
• VOL
• VOH
-2.0 mA
Open Drain
0.0
0.7 * VDDIO
0.4 * VDDIO
VDDIO
V
–
–
0.0
0.8 * VDDIO
0.2 * VDDIO
3.6
V
SD_VSEL
• VL
• VH
Notes
Table 29. Static electrical characteristics - Internal Supplies
All parameters are specified at TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external component values.
Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Notes
–
–
1.5
1.3
–
–
V
(39)
–
–
2.775
0.0
–
–
V
(39)
(39)
VCOREDIG (digital core supply)
VCOREDIG
Output voltage
• ON mode
• Coin cell mode and OFF mode
VCORE (analog core supply)
VCORE
Output voltage
• ON mode and charging
• Coin cell mode and OFF mode
VCOREREF (bandgap regulator reference)
VCOREREF
Output voltage at 25 °C
–
1.2
–
V
VCOREREFACC
Absolute trim accuracy
–
0.5
–
%
VCOREREFTACC
Temperature drift
–
0.25
–
%
Notes
39. 3.1 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF.
Table 30. Static electrical characteristics - UVDET threshold
All parameters are specified at TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external component values.
Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol
Parameter
Min.
Typ.
Max.
Unit
–
2.5
–
–
3.1
–
V
Notes
VIN UVDET threshold
VUVDET
• Rising
• Falling
PF3001
24
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6
Functional description and application information
6.1
Introduction
The PF3001 is a highly integrated, low quiescent current power management IC featuring three buck regulators and seven LDO
regulators. The PF3001 provides all the necessary rails to power a complete system including the application processor, memory, and
peripherals. The PF3001 operates from an input voltage of up to 5.5 V. Output voltage, start-up sequence, and other functions are set in
integrated one-time-programmable (OTP) memory.
6.2
Power generation
The buck regulators in the PF3001 provide supply to the processor cores and to other voltage domains, such as I/O and memory. Dynamic
voltage scaling is provided to allow controlled supply rail adjustments for the processor cores and other circuitry.
The linear regulators in the PF3001 can be used as general purpose regulators to power peripherals and lower power processor rails. The
VCC_SD LDO regulator supports the dual voltage requirement by high speed SD card readers. Depending on the system power path
configuration, the LDO regulators can be directly supplied from the main input supply or from the switching regulators to power peripherals,
such as audio, camera, Bluetooth, and Wireless LAN, etc.
The VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be
powered from VIN, or from a coin cell.
To accommodate applications powered by main supplies of voltages higher than 4.5 V and up to 5.5 V, the PF3001 incorporates a frontend LDO regulator using an external pass FET to keep the maximum regulator input voltage of the regulators at 4.5 V. Applications with
an input voltage lower than 4.5 V can directly power the regulators without using the front-end LDO.
Table 31 shows a summary of the voltage regulators in the PF3001.
Table 31. PF3001 power tree
Supply
Output voltage (V)
Programming step size (mV)
Maximum load current (mA)
SW1
0.7 to 1.425
1.8 and 3.3
25
(N/A)
2750
SW2
1.5 to 1.85
2.5 to 3.3
50
variable
1250
SW3
0.9 to 1.65
50
1500
VLDO1
1.8 to 3.3
50
100
VLDO2
0.8 to 1.55
50
250
VCC_SD
2.85 to 3.3
1.8 to 1.85
150
50
100
V33
2.85 to 3.3
150
350
VLDO3
1.8 to 3.3
100
100
VLDO4
1.8 to 3.3
100
350
VSNVS
3.0
NA
1.0
PF3001

NXP Semiconductors
25
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
PF3001
SW1
0.700 V to 3.3 V
2.75 A
1.1 V
i.MX Series
MCU
VDD_ARM
(A7 Core)
(SOC Logic)
VIN
4.5 V (typ.)
SW2
1.50 V to 1.85 V
or 2.25 V to 3.30 V
1.25 A
1.8 V
SW3
0.90 V to 1.65 V
1.5 A
1.35 V
VCC_SD
1.80 V to 1.85 V
or 2.85 V to 3.3 V
100 mA
V33
2.85 V to 3.30 V
350 mA
VDDA_1P8
(I/O)
NVCC_DRAM_CKE
(DDR IO)
3.3 V
3.3 V
VCC_SD_IO
NVCC_3P3
(3.3 V GPIO PAD)
VDDA_USBx_3P3
(USB OTG PHY)
VDD_LPSR
NVCC_GPIOx
VIN
MUX /
COIN
CHRG
Coincell
VIN
SW2
VLDO2INMAX = 3.4 V
VSNVS
1.0 V to 3.0 V
1.0 mA
VSNVS_IN
VLDO1
1.8 V to 3.3 V
100 mA
1.8 V
VLDO2
0.80 V to 1.55 V
250 mA
1.5 V
VLDO3
1.8 V to 3.3 V
100 mA
VIN
VLDO4
1.8 V to 3.3 V
350 mA
USB_OTG
DDR3L
Peripherals
3.3 V
3.3 V
Figure 5. PF3001 typical power map
Figure 5 shows a simplified power map with various recommended options to supply the different block within the PF3001, as well as the
typical application voltage domain on the i.MX Series processors. Note that each application power tree is dependent upon the system’s
voltage and current requirements, therefore a proper input voltage should be selected for the regulators.
PF3001
26
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3
Functional description
6.3.1
Control logic and interface signals
The PF3001 is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including INTB,
RESETBMCU, PWRON, and SD_VSEL. Refer to Table 28 for logic levels for these pins.
6.3.1.1
PWRON
PWRON is an input signal to the IC which generates a turn-on event. A turn-on event brings the PF3001 out of OFF mode and into the
ON mode. Refer to Modes of operation for the various modes (states) of operation of the IC. If the PWRON signal is high and VIN > UVDET,
the PMIC turns on; the interrupt and sense bits, PWRONI and PWRONS respectively, are set.
6.3.1.2
RESETBMCU
RESETBMCU is an open-drain, active low output. It is de-asserted 2.0 ms after the last regulator in the start-up sequence is enabled. This
signal can be used to bring the processor out of reset (POR), or as an indicator which all supplies have been enabled; it is only asserted
during a turn-off event. The RESETBMCU signal is internal timer based and does not monitor the regulators.
6.3.1.3
INTB
INTB is an open drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted
after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
6.3.1.4
SD_VSEL
SD_VSEL is an input pin which sets the output voltage range of the VCC_SD regulator. When SD_VSEL = HIGH, the VCC_SD regulator
operates in the lower output voltage range. When SD_VSEL = LOW, the VCC_SD regulator operates in the higher output voltage range.
The SD_VSEL input buffer is powered by the VDDIO supply. When a valid VDDIO voltage is not present, the output of the SD_VSEL buffer
defaults to a logic high thus keeping the VCC_SD regulator output in the lower voltage range.
PF3001
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NXP Semiconductors
27
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.2
Start-up
The PF3001 is available in a number of pre-programmed fixed start-up sequences to suit a wide variety of system configurations. Refer
to Table 32 for programming details of the different values.
Table 32. Start-up configuration (40)
Registers
Pre-programmed OTP configuration
A1
A2
A3
A4
A5
A6
A7
Default I C Address
0x08
0x08
0x08
0x08
0x08
0x08
0x08
VSNVS_VOLT
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
SW1_VOLT
1.10 V
1.10 V
1.375 V
1.375 V
1.375 V
1.4 V
1.4 V
2
SW1_SEQ
1
1
2
1
1
3
3
SW2_VOLT
1.8 V
1.8 V
3.3 V
3.3 V
3.15 V
3.3 V
3.3 V
SW2_SEQ
2
2
4
2
2
3
3
SW3_VOLT
1.35 V
1.2 V
1.35 V
1.5 V
1.2 V
1.2 V
1.35 V
SW3_SEQ
5
5
3
3
4
3
3
VLDO1_VOLT
1.8 V
1.8 V
3.3 V
1.8 V
1.8 V
3.3 V
3.3 V
VLDO1_SEQ
4
4
OFF
OFF
3
3
3
VLDO2_VOLT
1.5 V
1.5 V
1.5 V
1.2 V
1.5 V
1.5 V
1.5 V
VLDO2_SEQ
4
4
OFF
3
OFF
OFF
OFF
VLDO3_VOLT
3.3 V
3.3 V
2.5 V
1.8 V
3.1 V
1.8 V
1.8 V
VLDO3_SEQ
3
3
OFF
OFF
2
3
OFF
VLDO4_VOLT
3.3 V
3.3 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
VLDO4_SEQ
3
3
4
3
3
3
3
V33_VOLT
3.3 V
3.3 V
3.0 V
3.3 V
2.85 V
3.3 V
3.3 V
V33_SEQ
3
3
1
2
OFF
2
2
VCC_SD_VOLT
3.3 V/1.85 V
3.3 V/1.85 V
3.3 V/1.85 V
3.0 V/1.80 V
3.15 V/1.80 V
3.3 V/1.85 V
3.3 V/1.85 V
VCC_SD_SEQ
4
4
5
3
2
3
3
PU CONFIG,
SEQ_CLK_SPEED
2000 µs
2000 µs
500 µs
2000 µs
2000 µs
2000 µs
2000 µs
PU CONFIG, SWDVS_CLK
12.5 mV/µs
12.5 mV/µs
6.25 mV/s
12.5 mV/µs
12.5 mV/µs
6.25 mV/s
6.25 mV/s
PU CONFIG, PWRON
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
Level sensitive
SW1_FREQ
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
SW2_FREQ
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
SW3_FREQ
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
2.0 MHz
Notes
40. This table specifies the default output voltage of the LDOs and SWx after start-up and/or when the LDOs and SWx are enabled. The VCC_SD
voltage depends on the state of the SD_VSEL pin.
PF3001
28
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.3
Start-up timing diagram
Figure 6 shows the start-up timing of the regulators as determined by their OTP sequence. The trimmed 32 kHz clock controls all the startup timing.
UVDET
VIN
tr1
3V
td1 is time from VIN > UVDET to VSNVS
starting to rise. td1 is typically 5 ms
tr1 is time VSNVS takes to go from 1
V to 3 V. Typically it is 650 s.
td1
1V
VSNVS
td2
td2 is user determined delay. Can be
zero if PWRON pulled up to VSNVS
PWRON
td3 is delay of regulator(s) whose OTP sequence is set to 1.
With SEQ_CLK_SPEED = 0.5 ms, td3 is typically 2 ms with a
minimum of 1 ms and maximum of 3 ms
With SEQ_CLK_SPEED = 2 ms, td3 is typically 4.5 ms with a
minimum of 2.5 ms and maximum of 6.5 ms
td3
Regulator
Outputs
td4
td4 is controlled by the OTP
sequence setting of the
regulator(s). Refer to Table 32.
Regulator
Outputs
td5 is the time for RESETBMCU to go high from the
regulator(s) with the last OTP sequence. It is typically
2 ms with a minimum of 1.8 ms and maximum of 2.2 ms.
td5
RESETBMCU
Figure 6. Start-up timing diagram
6.3.4
16 MHz and 32 kHz clocks
The PF3001 incorporates two clocks: a trimmed 16 MHz RC oscillator and an untrimmed 32 kHz RC oscillator. The 32 kHz untrimmed
clock is only used in the following conditions:
• VIN < UVDET
• All regulators are in PFM switching mode
A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
When the 16 MHz is active in the ON mode, the debounce times are referenced to the 32 kHz derived from the 16 MHz clock. The
exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock. Switching frequency of the
switching regulators is derived from the trimmed 16 MHz clock.
The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By
changing the factory trim values of the 16 MHz clock, the user may add an offset as small as 3.0% of the nominal frequency. Contact
your NXP representative for detailed information on this feature.
PF3001

NXP Semiconductors
29
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.5
6.3.5.1
Optional front-end input LDO regulator
LDO regulator description
This section describes the optional front-end LDO regulator provided by the PF3001 in order to facilitate the operation with supply voltages
higher than 4.5 V and up to 5.5 V.
For non-battery operated applications, when the input supply voltage exceeds 4.5 V, the front-end LDO can be activated by populating the
external PMOS pass FET MP1 in Figure 7 and connecting the VPWR pin to the main supply. Under this condition, the LDO control block
self-starts with a local bandgap reference. When the VIN pin reaches UVDET rising threshold, the reference is switched to the main
trimmed bandgap reference to maintain the required VIN accuracy. In applications using an input supply voltage of 4.5 V or lower, the
PMOS pass FET should not be populated, the VPWR pin should be grounded externally, and the VIN pin should be used instead as the
main supply input pin. The input pins of the switching regulators should always be connected to the VIN net.
The main components of the LDO regulator are an external power P-channel MOSFET and an internal differential error amplifier. One
input of the amplifier monitors a fraction of the output voltage at VIN determined by the resistor ratio of R1 and R2 as shown in Figure 7.
The second input to the differential amplifier is from a stable bandgap voltage reference. If the output voltage rises too high relative to the
reference voltage, the gate voltage of the power FET is changed to maintain a constant output voltage.
VP WR
VPWR
VR EF
LDOG
_
MP1
+
VIN
R1
CVI N
R2
VP WR
Figure 7. Front-end LDO block diagram
6.3.5.2
Undervoltage/short-circuit and overvoltage detection
Short-circuit to GND at VIN is detected using an under voltage monitor at VIN which senses excessive droop on the VIN line and
consequently turns off (disable) the external PMOS pass FET. Overvoltage at VPWR is detected if VPWR exceeds the VPWROV threshold
(typically 6.0 V). Upon the detection of an overvoltage event an interrupt is generated and bit 2 is set in INTSTAT3 register. The INTB pin
is pulled low if the VPWROVM mask bit is cleared. The interrupt is filtered using a 122 s debouncing circuit. The VPWROV interrupt is
not asserted if the overvoltage event occurs during start up. The VPWROVS bit can be read using I2C to detect an overvoltage condition.
PF3001
30

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.5.3
External components
Table 33 lists the typical component values for the general purpose LDO regulators.
Table 33. Input LDO external components
Component
Value
Minimum output capacitor on VIN rail
100 F (41)
MP1
Fairchild FDMA908PZ, Vishay SiA447DJ, or comparable
Notes
41. Use X5R/X7R ceramic capacitors with a voltage rating at least two times the nominal voltage. The 100 F capacitance is the total capacitance
on the VIN rail including the capacitance at the various regulator inputs. For example, 2 x 22 F capacitors can be used along with 10 F
capacitors at all the SWx and LDOx inputs to achieve a total of 100 F capacitance.
6.3.6
Internal core voltages
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. VCOREDIG is a
1.5 V regulator powering all the digital logic in the PF3001. VCOREDIG is regulated at 1.28 V in off and coin cell modes. The VCORE
supply is used to bias internal analog rails. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is
kept powered as long as there is a valid supply and/or valid coin cell.
6.3.7
Buck regulators
The PF3001 integrates three independent buck regulators: SW1, SW2, and SW3. Each regulator has associated registers controlling its
output voltage during on mode. After boot up, contents of the SWxVOLT[4:0] register can be set through I2C to set the output voltage
during on mode.
VIN
SWxIN
CINSWx
CINSWxHF
SWx
SWxMODE
ISENSE
Controller
SWxLX
Driver
LSWx
COSWx
SWxFAULT
EP
Internal
Compensation
SWxFB
I2C
Interface
Z2
Z1
EA
VREF
DAC
Discharge
Figure 8. Generic SWx block diagram
PF3001
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NXP Semiconductors
31
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 34. SWx regulators external components
Components
CINSWx
CINSWxHF
COSWx
LSWx
Description
Values
SWx input capacitor
10 F
SWx decoupling input capacitor
0.1 F
SWx output capacitor
2 x 22 F (10 V or higher voltage rated
capacitors) or 3 x 22 F (6.3 V rated capacitors)
1.5 H
SWx inductor
Use X5R or X7R capacitors with voltage rating at least two times the nominal voltage.
6.3.7.1
Switching modes
The buck regulators can operate in different switching modes. Changing between switching modes can occur by I2C programming.
Available switching modes for buck regulators are presented in Table 35.
Table 35. Switching mode description
Mode
Description
OFF
The regulator is switched off and the output voltage is discharged using an internal resistor
PFM
In this mode, the regulator operates in forced PFM mode. The main error amplifier is turned off and a hysteretic comparator is
used to regulate output voltage. Use this mode for load currents less than 50 mA.
PWM
In this mode, the regulator operates in forced PWM mode.
APS
In this mode, the regulator operates in pulse skipping mode at light loads and switches over to PWM modes for heavier load
conditions. This is the default mode in which the regulators power up during a turn-on event.
During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms after the
output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching mode
selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. The operating
mode of the regulator in on mode is controlled using the SWxMODE[3:0] bits associated with each regulator. Table 36 summarizes the
Buck regulator programmability for normal mode.
Table 36. Regulator mode control
SWxMODE[3:0]
Normal mode
0000
Off
0001
PWM
0011
PFM
1000 (default)
APS
PF3001
32

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.7.2
Dynamic voltage scaling
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.
Normal operation: The output voltage is selected by I2C bits SW1[4:0] for SW1 and SW2[2:0] for SW2, and SW3[3:0] for SW3. A voltage
transition initiated by I2C is governed by the DVS stepping rate which is 25 mV per step each 4.0 s.
The regulators have a strong sourcing and sinking capability in PWM mode, therefore the fastest rising and falling slopes are determined
by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the falling slope
can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in PFM mode
could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
Figure 9 shows the general behavior for the regulators when initiated with I2C programming. During the DVS period the overcurrent
condition on the regulator should be masked.
Figure 9. Voltage stepping with fixed DVS
6.3.7.3
Regulator phase clock
The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 37. By default, each regulator is initialized at 90 ° out
of phase with respect to each other. For example, SW1 is set to 0 °, SW2 is set to 90 °, and SW3 is set to 180 ° by default at power up.
Table 37. Regulator phase clock selection
SWxPHASE[1:0]
Phase of clock sent to
regulator (degrees)
00
0
01
90
10
180
11
270
The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 39 shows the
selectable options for SWxFREQ[1:0]. For each frequency, all phases are available, this allows regulators operating at different
frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and
4.0 MHz, 180 ° are the same in terms of phasing. Table 38 shows the optimum phasing when using more than one switching frequency.
PF3001
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NXP Semiconductors
33
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 38. Optimum phasing
Frequencies
Optimum phasing
1.0 MHz
2.0 MHz
0°
180 °
1.0 MHz
4.0 MHz
0°
180 °
2.0 MHz
4.0 MHz
0°
180 °
1.0 MHz
2.0 MHz
4.0 MHz
0°
90 °
90 °
Table 39. Regulator frequency configuration
SWxFREQ[1:0]
Frequency
00
1.0 MHz
01
2.0 MHz (default)
10
4.0 MHz
11
Reserved
6.3.7.4
SW1
SW1 is a 2.75 A buck regulator. The SW1 output voltage is programmable from 1.5 V to 3.3 V. In this configuration, the SW1LX pins are
connected together to a single inductor, providing up to 2.75 A current capability for high current applications. The feedback and all other
controls are accomplished using the SW1FB pin.
6.3.7.5
SW1 setup and control registers
SW1 output voltages are programmable from 0.7 V to 1.425 V in steps of 25 mV. They can additionally be programmed at 1.8 V or 3.3 V.
The output voltage set point is independently programmed for Normal mode by setting the SW1[4:0] bits respectively. Table 40 shows the
output voltage coding.
Table 40. SW1 output voltage configuration
Set Point
SW1[4:0]
SW1x output (V)
Set Point
SW1[4:0]
SW1x output (V)
0
00000
0.700
16
10000
1.100
1
00001
0.725
17
10001
1.125
2
00010
0.750
18
10010
1.150
3
00011
0.775
19
10011
1.175
4
00100
0.800
20
10100
1.200
5
00101
0.825
21
10101
1.225
6
00110
0.850
22
10110
1.250
7
00111
0.875
23
10111
1.275
8
01000
0.900
24
11000
1.300
9
01001
0.925
25
11001
1.325
10
01010
0.950
26
11010
1.350
11
01011
0.975
27
11011
1.375
12
01100
1.000
28
11100
1.400
PF3001
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 40. SW1 output voltage configuration (continued)
Set Point
SW1[4:0]
SW1x output (V)
Set Point
SW1[4:0]
SW1x output (V)
13
01101
1.025
29
11101
1.425
14
01110
1.050
30
11110
1.800
15
01111
1.075
31
11111
3.300
Table 41 provides a list of registers used to configure and operate the SW1 regulator.
Table 41. SW1 register summary
Register
Address
Output
SW1VOLT
0x20
SW1 output voltage set point in normal operation
SW1MODE
0x23
SW1 switching mode selector register
SW1CONF
0x24
SW1 phase and frequency configuration
6.3.7.6
SW2 setup and control registers
SW2 is a single phase, 1.25 A rated buck regulator. The SW2 output voltage is programmable from 1.5 V to 1.85 V in 50 mV steps if the
CTL_SW2_HL bit is low or from 2.5 V to 3.3 V in 150 mV steps, if the bit CTL_SW2_HL is set high. This internal bit CTL_SW2_HL is
decided by the SW2 start-up voltage in the start-up sequence. During normal operation, output voltage of the SW2 regulator can be
changed through I2C only within the range set by the CTL_SW2_HL bit. The output voltage set point is independently programmed for
Normal mode by setting the SW2[2:0] bits, respectively. Table 42 shows the output voltage coding valid for SW2.
Table 42. SW2 output voltage configuration
Low output voltage range
(CTL_SW2_HL= 0)
High output voltage range
(CTL_SW2_HL=1)
SW2[2:0]
SW2 output
SW2[2:0]
SW2 output
000
1.500
000
2.500
001
1.550
001
2.800
010
1.600
010
2.850
011
1.650
011
3.000
100
1.700
100
3.100
101
1.750
101
3.150
110
1.800
110
3.200
111
1.850
111
3.300
Setup and control of SW2 is done through the I2C registers listed in Table 43.
Table 43. SW2 register summary
Register
SW2VOLT
Address
0x35
Description
SW2 output voltage set point on normal operation
SW2MODE
0x38
SW2 switching mode selector register
SW2CONF
0x39
SW2 phase, frequency, and ILIM configuration
PF3001
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NXP Semiconductors
35
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.7.7
SW3 setup and control registers
SW3 output voltage is programmable from 0.90 V to 1.65 V in 50 mV steps to support different types of DDR memory as listed in Table 44.
Table 44. SW3 output voltage configuration
SW3[3:0]
SW3 output (V)
SW3[3:0]
SW3 output (V)
0000
0.90
1000
1.30
0001
0.95
1001
1.35
0010
1.00
1010
1.40
0011
1.05
1011
1.45
0100
1.10
1100
1.50
0101
1.15
1101
1.55
0110
1.20
1110
1.60
0111
1.25
1111
1.65
Table 45 provides a list of registers used to configure and operate SW3.
Table 45. SW3 register summary
Register
Address
Output
SW3VOLT
0x3C
SW3 output voltage set point on normal operation
SW3MODE
0x3F
SW3 switching mode selector register
SW3CONF
0x40
SW3 phase, frequency, and ILIM configuration
6.3.8
LDO regulators description
This section describes the LDO regulators provided by the PF3001. All regulators use the main bandgap as reference. When a regulator
is disabled, the output discharges through an internal pull-down resistor.
VINx
VINx
VREF
_
VLDOxEN
+
VLDOxLPWR
VLDOx
VLDOx
2
IC
Interface
CLDOx
VLDOx
Discharge
Figure 10. General LDO block diagram
PF3001
36
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.8.1
External components
Table 46 lists the typical component values for the general purpose LDO regulators.
Table 46. LDO external components
Regulator
Output capacitor (F)(42)
VLDO1
2.2
VLDO2
4.7
VLDO3
2.2
VLDO4
4.7
V33
4.7
VCC_SD
2.2
Notes
42. Use X5R/X7R ceramic capacitors.
6.3.8.2
Current limit protection
All the LDO regulators in the PF3001 have current limit protection. In the event of an overload condition, the regulators transitions from a
voltage regulator to a current regulator which regulates output current per the current limit threshold.
Additionally, if the REGSCPEN bit in Table 107 is set, the LDO is turned off if the current limit event lasts for more than 8.0 ms. The LDO
is disabled by resetting its VLDOxEN bit, while at the same time, an interrupt VLDOxFAULTI is generated to flag the fault to the system
processor. The VLDOxFAULTI interrupt is maskable through the VLDOxFAULTM mask bit. By default, the REGSCPEN is not set;
therefore, at start-up none of the regulators is disabled if an overloaded condition occurs. A fault interrupt, VLDOxFAULTI, is generated in
an overload condition regardless of the state of the REGSCPEN bit.
6.3.8.3
LDO voltage control
Each LDO is fully controlled through its respective VLDOxCTL register. This register enables the user to set the LDO output voltage
according toTable 47 for VLDO1 and VLDO2; and uses the voltage set point on Table 48 for VLDO3 and VLDO4. Table 49 lists the voltage
set points for the V33 LDO and Table 50 provides the output voltage set points for the VCC_SD LDO, based on SD_VSEL control signal.
Table 47. VLDO1, VLDO2 output voltage configuration
VLDO1[3:0]
VLDO2[3:0]
VLDO1 output (V)
VLDO2 output (V)
0000
1.80
0.80
0001
1.90
0.85
0010
2.00
0.90
0011
2.10
0.95
0100
2.20
1.00
0101
2.30
1.05
0110
2.40
1.10
0111
2.50
1.15
1000
2.60
1.20
1001
2.70
1.25
1010
2.80
1.30
1011
2.90
1.35
1100
3.00
1.40
PF3001

NXP Semiconductors
37
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 47. VLDO1, VLDO2 output voltage configuration (continued)
VLDO1[3:0]
VLDO2[3:0]
VLDO1 output (V)
VLDO2 output (V)
1101
3.10
1.45
1110
3.20
1.50
1111
3.30
1.55
Table 48. VLDO3, VLDO4 output voltage configuration
VLDO3[3:0]
VLDO4[3:0]
VLDO3 or VLDO4 output (V)
0000
1.80
0001
1.90
0010
2.00
0011
2.10
0100
2.20
0101
2.30
0110
2.40
0111
2.50
1000
2.60
1001
2.70
1010
2.80
1011
2.90
1100
3.00
1101
3.10
1110
3.20
1111
3.30
Table 49. V33 output voltage configuration
V33[1:0]
V33 output (V)
00
2.85
01
3.00
10
3.15
11
3.30
Table 50. VCC_SD output voltage configuration
VCC_SD[1:0]
VCC_SD output (V)
VSD_VSEL= 0
VCC_SD output (V)
VSD_VSEL= 1
00
2.85
1.80
01
3.00
1.80
10
3.15
1.80
11
3.30
1.85
Along with the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation. Each regulator
has associated I2C bits for this. Table 51 presents a summary of all valid combinations of the control bits on VLDOxCTL register and the
expected behavior of the LDO output.
PF3001
38
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 51. LDO control
VLDOxEN/
V33EN/
VCC_SDEN
VLDOxOUT/
V33OUT/
VCC_SDOUT
0
Off
1
On
6.3.9
VSNVS LDO/switch
VSNVS powers the low power, SNVS/RTC domain on the processor. It derives its power from either VIN, or coin cell, and cannot be
disabled. When powered by both, VIN takes precedence when above the appropriate comparator threshold. When powered by VIN,
VSNVS is an LDO capable of supplying 3.0 V. When powered by coin cell, the VSNVS output tracks the coin cell voltage by means of a
switch, whose maximum resistance is 100 . In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across
the switch, which is 100 mV at a rated maximum load current of 1000 A.
When the coin cell is applied for the first time, VSNVS outputs 1.0 V. Only when VIN is applied thereafter does VSNVS transition to its default
value, or programmed value if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS changes configuration from
an LDO to a switch, provided certain conditions are met as described in Table 52.
PF3000
VIN
VIN
VTLI
2.25 V
(VTL0) 4.5 VV
4.5
LDO /SWITCH
LICELL
Charger
In pu t
Se nse /
Sel ecto r
VREF
LDO\
_
+
Coin Cell
1.8 - 3.3 V
Z
VSNVS
2
I C In terface
Figure 11. VSNVS supply switch architecture
Table 52 provides a summary of the VSNVS operation at different input voltage VIN and with or without coin cell connected to the system.
Table 52. SNVS Modes of Operation
VSNVSVOLT[2:0]
VIN
MODE
110
> VTH1
VIN LDO 3.0 V
110
< VTL1
Coin cell switch
PF3001

NXP Semiconductors
39
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.3.9.1
VSNVS control
The VSNVS output level is configured through the VSNVSVOLT[2:0] bits on VSNVSCTL register as shown in table Table 53.
Table 53. Register VSNVSCTL - ADDR 0x6B
Name
Bit #
R/W
Default
VSNVSVOLT
2:0
R/W
0b000
Unused
7:3
–
0b00000
Description
Configures VSNVS output voltage.(43)
000 = RSVD
001 = RSVD
010 = RSVD
011 = RSVD
100 = RSVD
101 = RSVD
110 = 3.0 V (default)
111 = RSVD
Unused
Notes
43. Only valid when a valid input voltage is present.
6.3.9.2
VSNVS external components
Table 54. VSNVS external components
Capacitor
Value (F)
VSNVS
0.47
6.3.9.3
Coin cell battery backup
The LICELL pin provides for a connection of a coin cell backup battery or a “super” capacitor. If the voltage at VIN goes below the VIN
threshold (VTL1), contact-bounced, or removed, the coin cell maintained logic is powered by the voltage applied to LICELL. The supply
for internal logic and the VSNVS rail switches over to the LICELL pin when VIN goes below VTL1, even in the absence of a voltage at the
LICELL pin, resulting in clearing of memory and turning off VSNVS. Applications concerned about this behavior can tie the LICELL pin to
any system voltage between 1.8 V and 3.0 V. A 0.47 F capacitor should be placed from LICELL to ground under all circumstances.
6.3.9.4
Coin cell charger control
The coin cell charger circuit functions as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for
rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit while the coin cell voltage is programmable
through the VCOIN[2:0] bits on register COINCTL on Table 55. The coin cell charger voltage is programmable. In the ON state, the charger
current is fixed at ICOINHI. In the OFF state, coin cell charging is not available as the main battery could be depleted unnecessarily. The
coin cell charging stops when VIN is below UVDET.
Table 55. Coin cell charger voltage
VCOIN[2:0]
VCOIN (V) (44)
000
2.50
001
2.70
010
2.80
011
2.90
100
3.00
101
3.10
PF3001
40

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 55. Coin cell charger voltage (continued)
VCOIN[2:0]
VCOIN (V) (44)
110
3.20
111
3.30
Notes
44. Coin cell voltages selected based on the type of LICELL used on the system.
Table 56. Register COINCTL - ADDR 0x1A
Name
Bit #
R/W
Default
VCOIN
2:0
R/W
0x00
Coin cell charger output voltage selection.
See Table 55 for all options selectable through these bits.
COINCHEN
3
R/W
0x00
Enable or disable the coin cell charger
Unused
7:4
–
0x00
Unused
6.3.9.5
Description
External components
Table 57. Coin cell charger external components
Component
Value
Units
100
nF
LICELL bypass capacitor
6.4
Power dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 4. To optimize the
thermal management and to avoid overheating, the PF3001 provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110, THERM120, THERM125, and THERM130 is generated when the respective thresholds specified in
Table 58 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry shuts down the PF3001. This thermal protection acts above the
thermal protection threshold listed in Table 58. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured
such that this protection is not tripped under normal conditions.
Table 58. Thermal protection thresholds
Parameter
Min.
Typ.
Max.
Units
Thermal 110 °C threshold (THERM110)
100
110
120
°C
Thermal 120 °C threshold (THERM120)
110
120
130
°C
Thermal 125 °C threshold (THERM125)
115
125
135
°C
Thermal 130 °C threshold (THERM130)
120
130
140
°C
Thermal warning hysteresis
2.0
–
4.0
°C
Thermal protection threshold
130
140
150
°C
PF3001

NXP Semiconductors
41
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.5
Modes of operation
6.5.1
State diagram
The operation of the PF3001 can be reduced to three states, or modes: ON, OFF, and Coin cell. Figure 12 shows the state diagram of the
PF3001, along with the conditions to enter and exit from each state.
Coin Cell
VIN < UVDET
VIN > UVDET
VIN < UVDET
OFF
PWRON=1
& VIN > UVDET
ON
PWRON = 0
Thermal shudown
Figure 12. State diagram
To complement the state diagram in Figure 12, a description of the states is provided in following sections. Note that VIN must exceed the
rising UVDET threshold to allow a power up. Refer to Table 30 for the UVDET thresholds. Additionally, I2C control is not possible in the
coin cell mode and the interrupt signal, INTB, is only active in the on state.
6.5.1.1
ON mode
The PF3001 enters the on mode after a turn-on event. RESETBMCU is de-asserted, and pulled high via an external pull-up resistor, in
this mode of operation. To enter the on mode, VIN voltage must surpass the rising UVDET threshold and PWRON must be asserted. From
the on mode, when the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin
cell mode.
6.5.1.2
OFF mode
The PF3001 enters the Off mode after a turn-off event. Only VCOREDIG and VSNVS are powered in the mode of operation. To exit the
off mode, a valid turn-on event is required. RESETBMCU is asserted, LOW, in this mode. Turn off events can be achieved using the
PWRON pin, thermal protection, as described by the following.
6.5.1.3
PWRON pin
The PWRON pin is used to power off the PF3001. The PWRON pin powers off the PMIC under conditions where the PWRON pin is low.
6.5.1.4
Thermal protection
If the die temperature surpasses a given threshold, the thermal protection circuit powers off the PMIC to avoid damage. A turn-on event
does not power on the PMIC while it is in thermal protection. The part remains in off mode until the die temperature decreases below a
given threshold. See Power dissipation section for more detailed information.
PF3001
42

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.5.1.5
Coin cell mode
In the coin cell state, the coin cell is the only valid power source to the PMIC. No turn-on event is accepted in the coin cell state. Transition
to the off state requires VIN surpasses the UVDET threshold. RESETBMCU is held low in this mode. If the coin cell is depleted, a complete
system reset occurs. At the next application of power and the detection of a turn-on event, the system re-initializes with all I2C bits
including, those that reset on COINPORB are restored to their default states.
6.5.2
State machine flow summary
Table 59 provides a summary matrix of the PF3001 flow diagram to show the conditions needed to transition from one state to another.
Table 59. State machine flow summary
Next state
Initial State
STATE
6.5.3
OFF
Coin cell
ON
OFF
X
VIN < UVDET
PWRON = 1 and VIN > UVDET
Coin cell
VIN > UVDET
X
X
VIN < UVDET
X
Thermal Shutdown
ON
PWRON = 0
Performance characteristics curves
VIN = 3.6 V, SW1OUT = 1.0 V, SW2OUT = 1.8 V, SW3OUT = 1.0 V, Switching frequency = 2.0 MHz, Mode = APS; LDO1OUT = 1.8 V, 
LDO2OUT = 1.0 V, LDO3OUT = 1.8 V, LDO4OUT = 1.8 V, V33OUT = 3.3 V, VCC_SDOUT = 3.3 V, unless otherwise noted
Figure 14. Load transient response - LDO2
Figure 13. Start-up sequence
PF3001

NXP Semiconductors
43
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Figure 15. Load transient response - LDO1, LDO3 and
VCC_SD
Figure 17. Load transient response - buck regulators
Figure 18. Quiescent current - LDOs
Figure 16. Load transient response - LDO4 and V33
PF3001
44

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Figure 19. Load regulation - LDOs
Figure 21. Dropout voltage - VLDO1, VLDO3,
VCC_SD - VOUT = 1.8 V
Figure 20. Dropout voltage - VLDO1, VLDO3, VCC_SD VOUT = 3.3 V
Figure 22. Dropout voltage - VLDO4, V33 - VOUT = 3.3 V
Figure 23. Dropout voltage - VLDO4 - VOUT = 1.8 V
PF3001

NXP Semiconductors
45
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Control interface I2C block description
6.6
The PF3001 contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers
the resources of the IC can be controlled. The registers also provide status information about how the IC is operating.
I2C device ID
6.6.1
I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. The I2C address of the PF3001 is set to 0x08.
I2C operation
6.6.2
The I2C mode of the interface is implemented generally following the fast mode definition which supports up to 400 kbits/s operation
(exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) Timing diagrams, electrical
specifications, and further details can be found in the I2C specification, which is available for download.
I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte
is sent out unless a STOP command or NACK is received prior to completion.
The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. The host
sends a master command packet after driving the start condition. The device responds to the host if the master command packet contains
the corresponding slave address. In the following examples, the device is always shown responding with an ACK to transmissions from
the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.
.
Packet
Type
Device
Address
7
Host SDA
Reg ister Addre ss
0
START
Host can
also drive
another
Start instead
of Stop
Master Driven Data
( byte 0 )
7
7
0
0
0
STOP
R/W
A
C
K
Slave SDA
A
C
K
A
C
K
Figure 24. I2C write example
Packet
Type
Device
Address
23
Host SDA
START
Register Address
16
15
Device Address
8
7
0
START
0
NA
CK
1
STOP
R/W
R/W
Slave SDA
Host can also
drive another
Start instead of
Stop
PMIC Driven Data
A
C
K
A
C
K
A
C
K
7
0
Figure 25. I2C read example
PF3001
46

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.3
Interrupt handling
The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving
the INTB pin low. Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt remains set until cleared. Each
interrupt can be cleared by writing a “1” to the appropriate bit in the Interrupt Status register; this causes the INTB pin to go high. If there
are multiple interrupt bits set the INTB pin remains low until all are either masked or cleared. If a new interrupt occurs while the processor
clears an existing interrupt bit, the INTB pin remains low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB
pin does not go low. A masked interrupt can still be read from the Interrupt Status register. This gives the processor the option of polling
for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any
interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the
INTB pin goes low after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are
read only, and not latched or clearable. Interrupts generated by external events are debounced; therefore, the event needs to be stable
throughout the debounce period before an interrupt is generated. Nominal debounce periods for each event are documented in the INT
summary Table 60. Due to the asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.6.4
Interrupt bit summary
Table 60 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer to
the related chapters.
Table 60. Interrupt, Mask, and Sense Bits
Interrupt
Mask
Sense
LOWVINI
LOWVINM
LOWVINS
PWRONI
PWRONM
PWRONS
Purpose
Trigger
Debounce time (ms)
Low input voltage detect
Sense is 1 if below 2.70 V threshold
H to L
3.9 (45)
Power on button event
H to L
31.25 (45)
Sense is 1 if PWRON is high.
L to H
31.25
Dual
3.9
THERM110
THERM110M
THERM110S
Thermal 110 °C threshold
Sense is 1 if above threshold
THERM120
THERM120M
THERM120S
Thermal 120 °C threshold
Sense is 1 if above threshold
Dual
3.9
THERM125
THERM125M
THERM125S
Thermal 125 °C threshold
Sense is 1 if above threshold
Dual
3.9
THERM130
THERM130M
THERM130S
Thermal 130 °C threshold
Sense is 1 if above threshold
Dual
3.9
SW1FAULTI
SW1FAULTM
SW1FAULTS
Regulator 1 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
SW2FAULTI
SW2FAULTM
SW2FAULTS
Regulator 2 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
SW3FAULTI
SW3FAULTM
SW3FAULTS
Regulator 3 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VLDO1FAULTI
VLDO1FAULTM
VLDO1FAULTS
VLDO1 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VLDO2FAULTI
VLDO2FAULTM
VLDO2FAULTS
VLDO2 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VCC_SDFAULTI
VCC_SDFAULTM
VCC_SDFAULTS
VCC_SD overcurrent limit
Sense is 1 if above current limit
L to H
8.0
V33FAULTI
V33FAULTM
V33FAULTS
V33 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VLDO3FAULTI
VLDO3FAULTM
VLDO1FAULTS
VLDO3 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
PF3001

NXP Semiconductors
47
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 60. Interrupt, Mask, and Sense Bits (continued)
Interrupt
Mask
Sense
Purpose
Trigger
Debounce time (ms)
VLDO4FAULTI
VLDO4FAULTM
VLDO4FAULTS
VLDO4 overcurrent limit
Sense is 1 if above current limit
L to H
8.0
VPWROVI
VPWROVM
VPWROVS
VPWR pin overvoltage interrupt
L to H
0.122
Notes
45. Typical debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
A full description of all interrupt, mask, and sense registers is provided in Table 61 to Table 72.
Table 61. Register INTSTAT0 - ADDR 0x05
Bit #
R/W
Default
PWRONI
Name
0
R/W1C
0
Power on interrupt bit
LOWVINI
1
R/W1C
0
Low-voltage interrupt bit
THERM110I
2
R/W1C
0
110 °C thermal interrupt bit
THERM120I
3
R/W1C
0
120 °C thermal interrupt bit
THERM125I
4
R/W1C
0
125 °C thermal interrupt bit
THERM130I
5
R/W1C
0
130 °C thermal interrupt bit
7:6
–
0b00
Unused
Description
Unused
Table 62. Register INTMASK0 - ADDR 0x06
Name
Bit #
R/W
Default
PWRONM
0
R/W1C
0
Power on interrupt mask bit
LOWVINM
1
R/W1C
0
Low-voltage interrupt mask bit
THERM110M
2
R/W1C
0
110 °C thermal interrupt mask bit
THERM120M
3
R/W1C
0
120 °C thermal interrupt mask bit
THERM125M
4
R/W1C
0
125 °C thermal interrupt mask bit
THERM130M
5
R/W1C
0
130 °C thermal interrupt mask bit
7:6
–
0b00
Unused
Description
Unused
Table 63. Register INTSENSE0 - ADDR 0x07
Name
Bit #
R/W
Default
Description
PWRONS
0
R
0
Power on sense bit
0 = PWRON low
1 = PWRON high
LOWVINS
1
R
0
Low-voltage sense bit
0 = VIN > 2.7 V
1 = VIN 2.7 V
THERM110S
2
R
0
110 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM120S
3
R
0
120 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM125S
4
R
0
125 °C thermal sense bit
0 = Below threshold
1 = Above threshold
PF3001
48

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 63. Register INTSENSE0 - ADDR 0x07 (continued)
Name
Bit #
R/W
Default
Description
THERM130S
5
R
0
130 °C thermal sense bit
0 = Below threshold
1 = Above threshold
ICTEST1S
6
R
0
0 = ICTEST1 pin is grounded
1 = ICTEST1 to VCOREDIG or greater
ICTEST2S
7
R
0
Additional ICTEST2 voltage sense pin
0 = ICTEST2 pin is grounded
1 = ICTEST2 to VCOREDIG or greater
Table 64. Register INTSTAT1 - ADDR 0x08
Bit #
R/W
Default
SW1FAULTI
Name
0
R/W1C
0
SW1 overcurrent interrupt bit
Description
Unused
1
R/W1C
0
Unused
Unused
2
R/W1C
0
Unused
SW2FAULTI
3
R/W1C
0
SW2 overcurrent interrupt bit
SW3FAULTI
4
R/W1C
0
SW3 overcurrent interrupt bit
Unused
5
R/W1C
0
Unused
Unused
6
R/W1C
0
Unused
Unused
7
–
0
Unused
Table 65. Register INTMASK1 - ADDR 0x09
Name
Bit #
R/W
Default
Description
SW1FAULTM
0
R/W
1
SW1 overcurrent interrupt mask bit
Unused
1
R/W
1
Unused
Unused
2
R/W
1
Unused
SW2FAULTM
3
R/W
1
SW2 overcurrent interrupt mask bit
SW3FAULTM
4
R/W
1
SW3 overcurrent interrupt mask bit
Unused
5
R/W
1
Unused
Unused
6
R/W
1
Unused
Unused
7
–
0
Unused
Table 66. Register INTSENSE1 - ADDR 0x0A
Name
Bit #
R/W
Default
Description
SW1FAULTS
0
R
0
SW1 overcurrent sense bit
0 = Normal operation
1 = Above current limit
Unused
1
R
0
Unused
Unused
2
R
0
Unused
SW2FAULTS
3
R
0
SW2 overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW3FAULTS
4
R
0
SW3 overcurrent sense bit
0 = Normal operation
1 = Above current limit
PF3001

NXP Semiconductors
49
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 66. Register INTSENSE1 - ADDR 0x0A (continued)
Name
Bit #
R/W
Default
Description
Unused
5
R
0
Unused
Unused
6
R
0
Unused
Unused
7
–
0
Unused
Table 67. Register INTSTAT3 - ADDR 0x0E
Name
Bit #
R/W
Default
Description
Unused
0
R/W1C
0
Unused
Unused
1
–
0b0
Unused
VPWROVI
2
R/W1C
0b0
High when overvoltage event is detected in the
front-end LDO circuit. This bit defaults to 0b1
when VPWR is grounded and the VIN path is
used to power the PF3001.
Unused
5:3
–
0b0
Unused
Unused
6
R/W1C
0b0
Unused
Unused
7
R/W1C
0
Unused
Table 68. Register INTMASK3 - ADDR 0x0F
Name
Bit #
R/W
Default
Unused
0
R/W
1
Unused
Unused
1
–
0
Unused
VPWR overvoltage interrupt mask bit
VPWROVM
Description
2
R/W
1
Unused
5:3
–
0b000
Unused
Unused
6
R/W
1
Unused
Unused
7
R/W
1
Unused
Table 69. Register INTSENSE3 - ADDR 0x10
Name
Bit #
R/W
Default
Unused
0
R
0
Unused
Unused
1
–
0b0
Unused
VPWROVS
Description
2
R
0
Unused
5:3
–
0b000
VPWR overvoltage interrupt sense bit
Unused
Unused
6
R
0
Unused
Unused
7
R
0
Unused
PF3001
50

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 70. Register INTSTAT4 - ADDR 0x11
Name
Bit #
R/W
Default
Description
VLDO1FAULTI
0
R/W1C
0
VLDO1 overcurrent interrupt bit
VLDO2FAULTI
1
R/W1C
0
VLDO2 overcurrent interrupt bit
VCC_SDFAULTI
2
R/W1C
0
VCC_SD overcurrent interrupt bit
V33FAULTI
3
R/W1C
0
V33 overcurrent interrupt bit
VLDO3FAULTI
4
R/W1C
0
VLDO3 overcurrent interrupt bit
VLDO4FAULTI
5
R/W1C
0
VLDO4 overcurrent interrupt bit
7:6
–
0b00
Unused
Unused
Table 71. Register INTMASK4 - ADDR 0x12
Name
Bit #
R/W
Default
VLDO1FAULTM
0
R/W
1
VLDO1 overcurrent interrupt mask bit
VLDO2FAULTM
1
R/W
1
VLDO2 overcurrent interrupt mask bit
VCC_SDFAULTM
2
R/W
1
VCC_SD overcurrent interrupt mask bit
V33FAULTM
3
R/W
1
V33 overcurrent interrupt mask bit
VLDO3FAULTM
4
R/W
1
VLDO3 Overcurrent interrupt mask bit
5
R/W
1
VLDO4 Overcurrent interrupt mask bit
7:6
–
0b00
VLDO4FAULTM
Unused
Description
Unused
Table 72. Register INTSENSE4 - ADDR 0x13
Name
Bit #
R/W
Default
VLDO1FAULTS
0
R
0
VLDO1 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VLDO2FAULTS
1
R
0
VLDO2 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VCC_SDFAULTS
2
R
0
VCC_SD overcurrent sense bit
0 = Normal operation
1 = Above current limit
V33FAULTS
3
R
0
V33 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VLDO3FAULTS
4
R
0
VLDO3 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VLDO4FAULTS
5
R
0
VLDO4 overcurrent sense bit
0 = Normal operation
1 = Above current limit
7:6
–
0b00
Unused
Description
Unused
PF3001

NXP Semiconductors
51
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5
Specific registers
6.6.5.1
IC and version identification
The IC and other version details can be read via identification bits. These are hard-wired on the chip and described in Table 73 to Table 75.
Table 73. Register DEVICEID - ADDR 0x00
Name
Bit #
R/W
Default
Description
DEVICEID
3:0
R
0x1
0001 = PF3001
Unused
7:4
–
0x3
Unused
Table 74. Register SILICON REV- ADDR 0x03
Name
Bit #
METAL_LAYER_REV
FULL_LAYER_REV
3:0
7:4
R/W
R
R
Default
Description
0x0
Represents the metal mask revision
Pass 0.0 = 0000
…
Pass 0.15 = 1111
0x1
Represents the full mask revision
Pass 1.0 = 0001
…
Pass 15.0 = 1111
Table 75. Register FABID - ADDR 0x04
Name
Bit #
R/W
Default
Description
FIN
1:0
R
0b00
Allows for characterizing different options within
the same reticule
FAB
3:2
R
0b00
Represents the wafer manufacturing facility
Unused
7:4
R
0b0000
6.6.5.2
Unused
Embedded memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.
Table 76. Register MEMA ADDR 0x1C
Name
MEMA
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank A
Table 77. Register MEMB ADDR 0x1D
Name
MEMB
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank B
Table 78. Register MEMC ADDR 0x1E
Name
MEMC
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank C
PF3001
52

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 79. Register MEMD ADDR 0x1F
Name
MEMD
6.6.5.3
Bit #
R/W
Default
7:0
R/W
0x00
Description
Memory bank D
Register descriptions
This section describes all the PF3001 registers and their individual bits. Address order is as listed in Register map.
6.6.5.3.1
Interrupt status register 0 (INTSTAT0)
INSTAT0 is one of the four status interrupt registers. This register contains six status flags. Write a logic 1 to clear a flag.
Table 80. Status interrupt register 0 (INTSTAT0)
Access: User read/write (46)
Address: 0x05 functional page
7
6
R
W
Default
0
0
5
4
3
2
1
0
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
PWRONI
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
46. Read: Anytime 
Write: Anytime
Table 81. INTSTAT0 field descriptions
Field
Description
5
THERM130I
130 °C thermal interrupt bit — THERM130I is set to 1 when the THERM130 threshold specified in is crossed in either direction (bidirectional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM130 threshold.
1 Die temperature has crossed THERM130 threshold.
4
THERM125I
125 °C thermal interrupt bit — THERM125I is set to 1 when the THERM125 threshold specified in is crossed in either direction (bidirectional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM125 threshold.
1 Die temperature has crossed THERM125 threshold.
3
THERM120I
120 °C thermal interrupt bit — THERM120I is set to 1 when the THERM120 threshold specified in is crossed in either direction (bidirectional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM120 threshold.
1 Die temperature has crossed THERM120 threshold.
110 °C thermal interrupt bit — THERM110I is set to 1 when the THERM110 threshold specified in
2
THERM110I
is crossed in either direction (bi-directional). This flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 Die temperature has not crossed THERM110 threshold.
1 Die temperature has crossed THERM110 threshold.
1
LOWVINI
Low-voltage interrupt bit — LOWVINI is set to 1 when a low-voltage event occurs on VIN. This flag can only be cleared by writing a
1. Writing a 0 has no effect.
0 VIN > 2.7 V (typical)
1 VIN 2.7 V (typical)
0
PWRONI
Power on interrupt bit —PWRONI is set to 1 when the turn on event occurs. This flag can only be cleared by writing a 1. Writing a 0
has no effect.
0 Power on has not occurred.
1 Power on has occurred.
PF3001

NXP Semiconductors
53
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.2
Interrupt status mask register 0 (INTMASK0)
INTMASK0 is the mask register for the status interrupt register INTSTAT0. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 82. Interrupt status mask register 0 (INTMASK0)
Access: User read/write (47)
Address: 0x06 functional page
7
6
R
W
Default
0
5
4
3
2
1
0
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
PWRONM
1
1
1
1
1
1
0
= Unimplemented or Reserved
Notes
47. Read: Anytime
Write: Anytime
Table 83. INTMASK0 field descriptions
Field
Description
5
THERM130M
130 °C thermal interrupt mask bit
0 THERM130I Unmasked
1 THERM130I Masked
4
THERM125M
125 °C thermal interrupt mask bit
0 THERM125I Unmasked
1 THERM125I Masked
3
THERM120M
120 °C thermal interrupt mask bit
0 THERM120I Unmasked
1 THERM120I Masked
2
THERM110M
110 °C thermal interrupt mask bit
0 THERM110I Unmasked
1 THERM110I Masked
1
LOWVINM
Low-voltage interrupt mask bit
0 LOWVINI Unmasked
1 LOWVINI Masked
0
PWRONM
Power on interrupt mask bit
0 PWRONI Unmasked
1 PWRONI Masked
PF3001
54

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.3
Interrupt sense register 0 (INTSENSE0)
This register has seven read-only sense bits. These sense bits reflects the actual state of the corresponding function.
Table 84. Interrupt sense register 0 (INTSENSE0)
Access: User read-only (48)
Address: 0x07 functional page
7
R
6
ICTEST2S
5
4
3
2
1
0
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
PWRONS
X (51)
X (51)
X (51)
X (51)
X (50)
X (49)
W
Default
X (52)
0
= Unimplemented or Reserved
Notes
48.
49.
50.
51.
52.
Read: Anytime
Default value depends on the initial PWRON pin state.
Default value depends on the initial VIN voltage.
Default value depends on the initial temperature of the die.
Default value depends on the initial ICTEST2 pin state.
Table 85. INTSENSE0 field descriptions
Field
7
ICTEST2S
Description
VDDOTP voltage sense bit
0 ICTEST2 grounded.
1 ICTEST2 to VCOREDIG or greater.
5
THERM130S
130 °C thermal interrupt sense bit
0 Die temperature below THERM130 threshold.
1 Die temperature above THERM130 threshold.
4
THERM125S
125 °C thermal interrupt sense bit
0 Die temperature below THERM125 threshold.
1 Die temperature has crossed THERM125 threshold.
3
THERM120S
120 °C thermal interrupt sense bit
0 Die temperature below THERM120 threshold.
1 Die temperature has crossed THERM120 threshold.
2
THERM110S
110 °C thermal interrupt sense bit
0 Die temperature below THERM110 threshold.
1 Die temperature has crossed THERM110 threshold.
1
LOWVINS
Low-voltage interrupt sense bit
0 VIN > 2.7 V (typical)
1 VIN 2.7 V (typical)
0
PWRONS
Power on interrupt sense bit
0 PWRON low.
1 PWRON high.
PF3001

NXP Semiconductors
55
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.4
Interrupt status register 1 (INTSTAT1)
INSTAT1 is one of the three status interrupt registers. This register contains three status flags. Write a logic 1 to clear a flag.
Table 86. Status interrupt register 1 (INTSTAT1)
Access: User read/write (53)
Address: 0x08 functional page
7
6
5
R
W
Default
0
0
0
4
3
SW3FAULTI
SW2FAULTI
0
0
2
1
0
SW1FAULTI
0
0
0
= Unimplemented or Reserved
Notes
53. Read: Anytime
Write: Anytime
Table 87. INTSTAT1 field descriptions
Field
Description
4
SW3FAULTI
SW3 overcurrent interrupt bit — SW3FAULTI is set to 1 when the SW3 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW3 in normal operation
1 SW3 above current limit
3
SW2FAULTI
SW2 overcurrent interrupt bit — SW2FAULTI is set to 1 when the SW2 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW2 in normal operation
1 SW2 above current limit
0
SW1FAULTI
SW1 overcurrent interrupt bit — SW1FAULTI is set to 1 when the SW1 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 SW1 in normal operation
1 SW1 above current limit
6.6.5.3.5
Interrupt status mask register 1 (INTMASK1)
INTMASK1 is the mask register for the status interrupt register INTSTAT1. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 88. Interrupt status mask register 1 (INTMASK1)
Access: User read/write (54)
Address: 0x09 functional page
7
6
5
R
W
Default
0
0
0
4
3
SW3FAULTM
SW2FAULTM
1
1
2
1
0
SW1FAULTM
0
1
0
= Unimplemented or Reserved
Notes
54. Read: Anytime
Write: Anytime
PF3001
56

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 89. INTMASK1 field descriptions
Field
Description
4
SW3FAULTM
SW3 overcurrent interrupt mask bit
0 SW3FAULTI Unmasked
1 SW3FAULTI Masked
3
SW2FAULTM
SW2 overcurrent interrupt mask bit
0 SW2FAULTI Unmasked
1 SW2FAULTI Masked
0
SW1FAULTM
SW1 overcurrent interrupt mask bit
0 SW1FAULTI Unmasked
1 SW1FAULTI Masked
6.6.5.3.6
Interrupt sense register 1 (INTSENSE1)
This register has three read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Table 90. Interrupt sense register 1 (INTSENSE1)
Access: User read-only (55)
Address: 0x0A functional page
7
6
5
R
4
3
SW3FAULTS
SW2FAULTS
X(56)
X(56)
2
1
0
SW1FAULTS
W
Default
0
0
0
0
X(56)
X(56)
= Unimplemented or Reserved
Notes
55. Read: Anytime
56. Default value depends on the regulator initial state
Table 91. INTSENSE1 field descriptions
Field
Description
4
SW3FAULTS
SW3 overcurrent sense bit
0 SW3 in normal operation
1 SW3 above current limit
3
SW2FAULTS
SW2 overcurrent sense bit
0 SW2 in normal operation
1 SW2 above current limit
0
SW1FAULTS
SW1 overcurrent sense bit
0 SW1 in normal operation
1 SW1 above current limit
PF3001

NXP Semiconductors
57
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.7
Interrupt status register 3 (INTSTAT3)
INSTAT3 is one of the status interrupt registers. This register contains a status flag. Write a logic 1 to clear a flag.
Table 92. Status interrupt register 3 (INTSTAT3)
Access: User read/write (57)
Address: 0x0E Functional Page
7
6
5
4
3
R
2
1
0
0
0
VPWROVI
W
Default
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
57. Read: Anytime
Write: Anytime
Table 93. INTSTAT3 field descriptions
Field
2
VPWROVI
6.6.5.3.8
Description
VPWR overvoltage interrupt bit — High when overvoltage event is detected in the front-end LDO circuit. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 VPWR in normal operation range.
1 VPWR in overvoltage range.
Interrupt status mask register 3 (INTMASK3)
INTMASK3 is the mask register for the status interrupt register INTSTAT3. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 94. Interrupt status mask register 3 (INTMASK3)
Access: User read/write (58)
Address: 0x0F functional page
7
6
5
4
3
R
2
1
0
0
1
VPWROVM
W
Default
1
1
0
0
0
1
= Unimplemented or Reserved
Notes
58. Read: Anytime
Write: Anytime
Table 95. INTMASK3 field descriptions
Field
2
VPWROVM
Description
VPWR overvoltage interrupt mask bit
0 VPWROVI Unmasked
1 VPWROVI Masked
PF3001
58

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.9
Interrupt sense register 3 (INTSENSE3)
This register has a read-only sense bit. This sense bit reflects the actual state of the corresponding function.
Table 96. Interrupt sense register 3 (INTSENSE3)
Access: User read-only (59)
Address: 0x10 functional page
7
6
5
4
3
R
2
1
0
0
0
VPWROVS
W
Default
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
59. Read: Anytime
Table 97. INTSENSE3 field descriptions
Field
Description
VPWR overvoltage interrupt sense bit
0 VPWR in normal operation range.
1 VPWR in overvoltage range.
2
VPWROVS
6.6.5.3.10
Interrupt status register 4 (INTSTAT4)
INSTAT4 is one of the status interrupt registers. This register contains six status flags. Write a logic 1 to clear a flag.
Table 98. Status interrupt register 4 (INTSTAT4)
Access: User read/write (60)
Address: 0x11 functional page
7
6
R
W
Default
0
0
5
4
3
VLDO4FAULTI
VLDO3FAULTI
V33FAULTI
0
0
0
2
1
0
VCC_SDFAULTI VLDO2FAULTI VLDO1FAULTI
0
0
0
= Unimplemented or Reserved
Notes
60. Read: Anytime
Write: Anytime
PF3001

NXP Semiconductors
59
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 99. INTSTAT4 field descriptions
Field
Description
5
VLDO4FAULTI
VLDO4 overcurrent interrupt bit — VLDO4FAULTI is set to 1 when the VLDO4 regulator is in current limit protection. This flag can
only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO4 in normal operation
1 VLDO4 above current limit
4
VLDO3FAULTI
VLDO3 overcurrent interrupt bit — VLDO3FAULTI is set to 1 when the VLDO3 regulator is in current limit protection. This flag can
only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO3 in normal operation
1 VLDO3 above current limit
3
V33FAULTI
V33 overcurrent interrupt bit — V33FAULTI is set to 1 when the V33 regulator is in current limit protection. This flag can only be
cleared by writing a 1. Writing a 0 has no effect.
0 V33 in normal operation
1 V33 above current limit
2
VCC_SDFAULTI
VCC_SD overcurrent interrupt bit — VCC_SDFAULTI is set to 1 when the VCC_SD regulator is in current limit protection. This
flag can only be cleared by writing a 1. Writing a 0 has no effect.
0 VCC_SD in normal operation
1 VCC_SD above current limit
1
VLDO2FAULTI
VLDO2 overcurrent interrupt bit — VLDO2FAULTI is set to 1 when the VLDO2 regulator is in current limit protection. This flag can
only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO2 in normal operation range.
1 VLDO2 above current limit
0
VLDO1FAULTI
VLDO1 overcurrent interrupt bit — VLDO1FAULTI is set to 1 when the VLDO1 regulator is in current limit protection. This flag can
only be cleared by writing a 1. Writing a 0 has no effect.
0 VLDO1 in normal operation range.
1 VLDO1 above current limit
6.6.5.3.11
Interrupt status mask register 4 (INTMASK4)
INTMASK4 is the mask register for the status interrupt register INTSTAT4. Write a logic 0 to a bit to unmask the corresponding interrupt.
When unmasked, the corresponding interrupt state is reflected on the INTB pin.
Table 100. Interrupt status mask register 4 (INTMASK4)
Access: User read/write (61)
Address: 0x12 functional page
7
6
R
4
VLDO4FAULTM VLDO3FAULTM
W
Default
5
0
0
1
1
3
V33FAULTM
1
2
1
0
VCC_SDFAULTM VLDO2FAULTM VLDO1FAULTM
1
1
1
= Unimplemented or Reserved
Notes
61. Read: Anytime
Write: Anytime
PF3001
60

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 101. INTMASK4 field descriptions
Field
Description
5
VLDO4FAULTM
VLDO4 overcurrent interrupt mask bit
0 VLDO4FAULTI Unmasked
1 VLDO4FAULTI Masked
4
VLDO3FAULTM
VLDO3 overcurrent interrupt mask bit
0 VLDO3FAULTI Unmasked
1 VLDO3FAULTI Masked
V33 overcurrent interrupt mask bit
0 V33FAULTI Unmasked
1 V33FAULTI Masked
3
V33FAULTM
VCC_SD overcurrent interrupt mask bit
0 VCC_SDFAULTI Unmasked
1 VCC_SDFAULTI Masked
2
VCC_SDFAULTM
1
VLDO2FAULTM
VLDO2 overcurrent interrupt mask bit
0 VLDO2FAULTI Unmasked
1 VLDO2FAULTI Masked
0
VLDO1FAULTM
VLDO1 overcurrent interrupt mask bit
0 VLDO1FAULTI Unmasked
1 VLDO1FAULTI Masked
6.6.5.3.12
Interrupt sense register 4 (INTSENSE4)
This register has read-only sense bits. These sense bits reflect the actual state of the corresponding function.
Table 102. Interrupt sense register 4 (INTSENSE4)
Access: User read-only (62)
Address: 0x13 functional page
7
6
R
5
4
VLDO4FAULTS VLDO3FAULTS
3
V33FAULTS
2
1
0
VCC_SDFAULTS VLDO2FAULTS VLDO1FAULTS
W
Default
0
0
X (63)
X (63)
X (63)
X (63)
X (63)
X (63)
= Unimplemented or Reserved
Notes
62. Read: Anytime
63. Default value depends on the regulator initial state
PF3001

NXP Semiconductors
61
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 103. INTSENSE4 field descriptions
Field
Description
5
VLDO4FAULTS
VLDO4 overcurrent sense bit
0 VLDO4 in normal operation
1 VLDO4 above current limit
4
VLDO3FAULTS
VLDO3 overcurrent sense bit
0 VLDO3 in normal operation
1 VLDO3 above current limit
3
V33FAULTS
V33 overcurrent sense bit
0 V33 in normal operation
1 V33 above current limit
2
VCC_SDFAULT
S
VCC_SD overcurrent sense bit
0 VCC_SD in normal operation
1 VCC_SD above current limit
1
VLDO2FAULTS
VLDO2 overcurrent sense bit
0 VLDO2 in normal operation
1 VLDO2 above current limit
0
VLDO1FAULTS
VLDO1 overcurrent sense bit
0 VLDO1 in normal operation
1 VLDO1 above current limit
6.6.5.3.13
Coin cell control register (COINCTL)
This register is used to control the coin cell charger.
Table 104. Coin cell control register (COINCTL)
Access: User read/write (64)
Address: 0x1A functional page
7
6
5
4
R
2
COINCHEN
W
Default
3
0
0
0
0
0
1
0
VCOIN
0
0
0
= Unimplemented or Reserved
Notes
64. Read: Anytime
Write: Anytime
Table 105. COINCTL field descriptions
Field
3
COINCHEN
2:0
VCOIN
Description
Coin cell charger enable bit
0 Coin Cell charger disabled.
1 Coin Cell charger enabled.
Coin cell charger output voltage selection — This field is used to set the coin cell charging voltage from 2.50 V to 3.30 V. See
Table 55 for all options selectable through these bits.
PF3001
62

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.14
Power control register (PWRCTL)
Table 106. Power control register (PWRCTL)
Access: User read/write (65)
Address: 0x1B functional page
7
R
W
6
5
4
3
2
REGSCPEN
Default
0
0
0
1
0
0
1
0
PWRONRSTEN
RESTARTEN
0
0
= Unimplemented or Reserved
Notes
65. Read: Anytime
Write: Anytime
Table 107. PWRCTL field descriptions
Field
Description
7
REGSCPEN
Short-circuit protection enable bit — When REGSCPEN is set to 1, whenever a current limit event occurs on a LDO regulator, this
regulator is shutdown.
0 Short-circuit protection disabled
1 Short-circuit protection enabled
1
PWRONRSTEN
0
RESTARTEN
6.6.5.3.15
PWRON reset enable bit — When set to 1, the PF3001 can enter OFF mode when the PWRON pin is held low for 4 seconds or
longer. See PWRON Pin section for details.
0 Disallow OFF mode after PWRON held low
1 Allow OFF mode after PWRON held low
Restart enable bit — When set to 1, the PF3001 restarts automatically after a power off event generated by the PWRON (held low
for 4 seconds or longer) when PWR_CFG bit = 1.
0 Automatic restart disabled.
1 Automatic restart enabled.
Embedded memory register A (MEMA)
Table 108. Embedded memory register A (MEMA)
Access: User read/write (66)
Address: 0x1C functional page
7
6
5
4
R
3
2
1
0
0
0
0
0
MEMA
W
Default
0
0
0
0
= Unimplemented or Reserved
Notes
66. Read: Anytime
Write: Anytime
Table 109. MEMA field descriptions
Field
Description
7:0
MEMA
Memory bank A — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
PF3001

NXP Semiconductors
63
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.16
Embedded memory register B (MEMB)
Table 110. Embedded memory register B (MEMB)
Access: User read/write (67)
Address: 0x1D functional page
7
6
5
4
R
2
1
0
0
0
0
0
MEMB
W
Default
3
0
0
0
0
= Unimplemented or Reserved
Notes
67. Read: Anytime
Write: Anytime
Table 111. MEMB field descriptions
Field
Description
7:0
MEMB
Memory bank B — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
6.6.5.3.17
Embedded memory register C (MEMC)
Table 112. Embedded memory register C (MEMC)
Access: User read/write (68)
Address: 0x1E Functional Page
7
6
5
4
R
2
1
0
0
0
0
0
MEMC
W
Default
3
0
0
0
0
= Unimplemented or Reserved
Notes
68. Read: Anytime
Write: Anytime
Table 113. MEMC field descriptions
Field
Description
7:0
MEMC
Memory bank C — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
PF3001
64

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.18
Embedded memory register D (MEMD)
Table 114. Embedded memory register D (MEMD)
Access: User read/write (69)
Address: 0x1F functional page
7
6
5
4
R
3
2
1
0
0
0
0
0
MEMD
W
Default
0
0
0
0
= Unimplemented or Reserved
Notes
69. Read: Anytime
Write: Anytime
Table 115. MEMD field descriptions
Field
Description
7:0
MEMD
Memory bank D — This register is maintained in case of a main battery loss as long as the coin cell is present. The contents of the
embedded memory are reset by COINPORB.
6.6.5.3.19
SW1 voltage control register (SW1VOLT)
This register is used to set the output voltage of the SW1 regulator in normal operation.
Table 116. SW1 voltage control register (SW1VOLT)
Access: User read/write (70)
Address: 0x20 functional page
7
6
5
4
3
R
1
0
X (71)
X (71)
SW1
W
Default
2
0
0
0
X (71)
X (71)
X (71)
= Unimplemented or Reserved
Notes
70. Read: Anytime
Write: Anytime
71. Default value depends on OTP content.
Table 117. SW1VOLT field descriptions
Field
4:0
SW1
Description
SW1 output voltage — Refer to Table 40
PF3001

NXP Semiconductors
65
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.20
SW1 switching mode selector register (SW1MODE)
This register is used to set the switching mode of the SW1 regulator.
Table 118. SW1 switching mode selector register (SW1MODE)
Access: User read/write (72)
Address: 0x23 functional page
7
6
5
4
3
2
1
0
X (73)
X (73)
R
SW1MODE
W
Default
0
0
0
X (73)
0
X (73)
= Unimplemented or Reserved
Notes
72. Read: Anytime
Write: Anytime
73. Default value depends on start-up sequence.
Table 119. SW1MODE field descriptions
Field
3:0
SW1MODE
6.6.5.3.21
Description
SW1 switching mode selector — Refer to Table 36
SW1 configuration register (SW1CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW1 regulator.
Table 120. SW1 configuration register (SW1CONF)
Access: User read/write (74)
Address: 0x24 functional page
7
6
5
R
4
3
SW1PHASE
W
Default
0
0
0
2
1
SW1ILIM
SW1FREQ
0
X (75)
0
X (75)
0
0
= Unimplemented or Reserved
Notes
74. Read: Anytime
Write: Anytime
75. Default value depends on OTP content.
Table 121. SW1CONF field descriptions
Field
5:4
SW1PHASE
3:2
SW1FREQ
0
SW1ILIM
Description
SW1 phase clock bit— SW1PHASE is used to set the phase clock for SW1. Refer to Table 37.
SW1 switching frequency— SW1PHASE is used to set the desired switching frequency for SW1. Refer to Table 39.
SW1 current limiter bit— This bit configures the current limit for SW1.
0 2.75 A (typ).
1 2.0 A (typ).
PF3001
66

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.22
SW2 voltage control register (SW2VOLT)
This register is used to set the output voltage of the SW2 regulator in normal operation.
Table 122. SW2 voltage control register (SW2VOLT)
Access: User read/write (76)
Address: 0x35 functional page
7
6
5
4
3
R
2
1
0
X (77)
X (77)
SW2
W
Default
0
0
0
X (77)
X (77)
X (77)
= Unimplemented or Reserved
Notes
76. Read: Anytime
Write: Anytime
77. Default value depends on start-up sequence.
Table 123. SW2VOLT field descriptions
Field
4:0
SW2
6.6.5.3.23
Description
SW2 output voltage — Refer to Table 42.
SW2 switching mode selector register (SW2MODE)
This register is used to set the switching mode of the SW2 regulator.
Table 124. SW2 switching mode selector register (SW2MODE)
Access: User read/write (78)
Address: 0x38 functional page
7
6
5
4
3
2
1
0
X (79)
X (79)
R
SW2MODE
W
Default
0
0
0
0
X (79)
X (79)
= Unimplemented or Reserved
Notes
78. Read: Anytime
Write: Anytime
79. Default value depends on start-up sequence.
Table 125. SW2MODE field descriptions
Field
3:0
SW2MODE
Description
SW2 switching mode selector — Refer to Table 36.
PF3001

NXP Semiconductors
67
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.24
SW2 configuration register (SW2CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW2 regulator.
Table 126. SW2 configuration register (SW2CONF)
Access: User read/write (80)
Address: 0x39 functional page
7
6
5
R
4
3
SW2PHASE
W
Default
0
0
0
2
1
0
SW2FREQ
X (81)
0
SW2ILIM
X (81)
0
0
= Unimplemented or Reserved
Notes
80. Read: Anytime
Write: Anytime
81. Default value depends on OTP content.
Table 127. SW2CONF field descriptions
Field
Description
5:4
SW2PHASE
SW2 phase clock bit— SW2PHASE is used to set the phase clock for SW2. Refer to Table 37.
3:2
SW2FREQ
SW2 switching frequency— SW2PHASE is used to set the desired switching frequency for SW2. Refer to Table 39.
SW2 current limiter bit— This bit configures the current limit for SW2.
0 2.75 A (typ).
1 2.0 A (typ).
0
SW2ILIM
6.6.5.3.25
SW3 voltage control register (SW3VOLT)
This register is used to set the output voltage of the SW3 regulator in normal operation.
Table 128. SW3 voltage control register (SW3VOLT)
Access: User read/write (82)
Address: 0x3C functional page
7
6
5
4
3
R
1
0
X (83)
X (83)
SW3
W
Default
2
0
0
0
X (83)
X (83)
X (83)
= Unimplemented or Reserved
Notes
82. Read: Anytime
Write: Anytime
83. Default value depends on start-up sequence.
Table 129. SW3VOLT field descriptions
Field
4:0
SW3
Description
SW3 output voltage — Refer to Table 44.
PF3001
68

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.26
SW3 switching mode selector register (SW3MODE)
This register is used to set the switching mode of the SW3 regulator.
Table 130. SW3 switching mode selector register (SW3MODE)
Access: User read/write (84)
Address: 0x3F functional page
7
6
5
4
3
2
1
0
X (85)
X (85)
R
SW3MODE
W
Default
0
0
0
X (85)
0
X (85)
= Unimplemented or Reserved
Notes
84. Read: Anytime
Write: Anytime
85. Default value depends on start-up sequence.
Table 131. SW3MODE field descriptions
Field
3:0
SW3MODE
6.6.5.3.27
Description
SW3 switching mode selector — Refer to Table 36.
SW3 configuration register (SW3CONF)
This register is used to configure DVS, switching frequency, phase and current limit settings of the SW3 regulator.
Table 132. SW3 configuration register (SW3CONF)
Access: User read/write (86)
Address: 0x40 functional page
7
6
5
R
4
3
SW3PHASE
W
Default
0
0
1
2
1
SW3FREQ
0
X (87)
0
SW3ILIM
X (87)
0
0
= Unimplemented or Reserved
Notes
86. Read: Anytime
Write: Anytime
87. Default value depends on OTP content.
Table 133. SW3CONF field descriptions
Field
5:4
SW3PHASE
3:2
SW3FREQ
0
SW3ILIM
Description
SW3 phase clock bit— SW3PHASE is used to set the phase clock for SW3. Refer to Table 37.
SW3 switching frequency— SW3PHASE is used to set the desired switching frequency for SW3. Refer to Table 39.
SW3 current limiter bit— This bit configures the current limit for SW3.
0 3.0 A (typ).
1 2.25 A (typ).
PF3001

NXP Semiconductors
69
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.28
VSNVS control register (VSNVSCTL)
This register is used to control the VSNVS supply operation.
Table 134. VSNVS control register (VSNVSCTL)
Access: User read/write (88)
Address: 0x6B functional page
7
6
5
4
3
2
1
0
R
VSNVSVOLT
W
Default
0
0
0
0
X (89)
0
X (89)
X (89)
= Unimplemented or Reserved
Notes
88. Read: Anytime
Write: Anytime
89. Default value depends on start-up sequence.
Table 135. VSNVSCTL field descriptions
Field
Description
VSNVS output voltage configuration— VSNVSVOLT is used to configure the VSNVS output voltage. Values below are
typical voltages.
000 = RSVD
001 = RSVD
010 = RSVD
011 = RSVD
100 = RSVD
101 = RSVD
110 = 3.0 V (default)
111 = RSVD
2:0
VSNVSVOLT
6.6.5.3.29
VLDO1 control register (VLDO1CTL)
This register is used to configure output voltage, normal mode operation of the VLDO1 regulator.
Table 136. VLDO1 control register (VLDO1CTL)
Access: User read/write (90)
Address: 0x6C functional page
7
6
5
R
3
2
VLDO1EN
W
Default
4
0
0
0
X (91)
1
0
X (91)
X (91)
VLDO1
X (91)
X (91)
= Unimplemented or Reserved
Notes
90. Read: Anytime
Write: Anytime
91. Default value depends on start-up sequence.
PF3001
70
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NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 137. VLDO1CTL field descriptions
Field
Description
VLDO1 enable bit — VLDO1EN is used to enable or disable the VLDO1 regulator.
0 VLDO1 disabled
1 VLDO1 enabled
4
VLDO1EN
3:0
VLDO1
6.6.5.3.30
VLDO1 output voltage configuration— Refer to Table 47.
VLDO2 control register (VLDO2CTL)
This register is used to configure output voltage, normal mode operation of the VLDO2 regulator.
Table 138. VLDO2 control register (VLDO2CTL)
Access: User read/write (92)
Address: 0x6D functional page
7
6
5
R
4
3
2
VLDO2EN
W
Default
0
0
0
1
0
X (93)
X (93)
VLDO2
X (93)
X (93)
X (93)
= Unimplemented or Reserved
Notes
92. Read: Anytime
Write: Anytime
93. Default value depends on start-up sequence.
Table 139. VLDO2CTL field descriptions
Field
4
VLDO2EN
3:0
VLDO2
Description
VLDO2 enable bit — VLDO2EN is used to enable or disable the VLDO2 regulator.
0 VLDO2 Disabled
1 VLDO2 Enabled
VLDO2 output voltage configuration— Refer to Table 47.
PF3001

NXP Semiconductors
71
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.31
VCC_SD control register (VCC_SDCTL)
This register is used to configure output voltage, Normal mode operation of the VCC_SD regulator.
Table 140. CC_SD control register (VCC_SDCTL)
Access: User read/write (94)
Address: 0x6E functional page
7
6
5
R
4
3
2
1
0
VCC_SDEN
W
Default
0
0
0
VCC_SD
X (95)
0
0
X (95)
X (95)
= Unimplemented or Reserved
Notes
94. Read: Anytime
Write: Anytime
95. Default value depends on start-up sequence.
Table 141. VCC_SDCTL field descriptions
Field
Description
VCC_SD enable bit — VCC_SDEN is used to enable or disable the VCC_SD regulator.
0 VCC_SD Disabled
1 VCC_SD Enabled
4
VCC_SDEN
1:0
VCC_SD
6.6.5.3.32
VCC_SD output voltage configuration— Refer to Table 50.
V33 control register (V33CTL)
This register is used to configure output voltage, normal mode operation of the V33 regulator.
Table 142. V33 control register (V33CTL)
Access: User read/write (96)
Address: 0x6F functional page
7
6
5
R
4
3
2
1
0
V33EN
W
Default
0
0
0
X (97)
V33
0
0
X (97)
X (97)
= Unimplemented or Reserved
Notes
96. Read: Anytime
Write: Anytime
97. Default value depends on start-up sequence.
Table 143. V33CTL field descriptions
Field
4
V33EN
1:0
V33
Description
V33 enable bit — V33EN is used to enable or disable the VLDO2 regulator.
0 V33 Disabled
1 V33 Enabled
V33 output voltage configuration— Refer to Table 49.
PF3001
72

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.33
VLDO3 control register (VLDO3CTL)
This register is used to configure output voltage, normal mode operation of the VLDO3 regulator.
Table 144. VLDO3 control register (VLDO3CTL)
Access: User read/write (98)
Address: 0x70 functional page
7
6
5
R
4
3
2
VLDO3EN
W
Default
0
0
0
1
0
X (99)
X (99)
VLDO3
X (99)
X (99)
X (99)
= Unimplemented or Reserved
Notes
98. Read: Anytime
Write: Anytime
99. Default value depends on start-up sequence.
Table 145. VLDO3CTL field descriptions
Field
Description
VLDO3 enable bit — VLDO3EN is used to enable or disable the VLDO3 regulator.
0 VLDO3 Disabled
1 VLDO3 Enabled
4
VLDO3EN
3:0
VLDO3
6.6.5.3.34
VLDO3 output voltage configuration— Refer to Table 48.
VLDO4 control register (VLDO4CTL)
This register is used to configure output voltage, normal mode operation of the VLDO4 regulator.
Table 146. VLDO4 control register (VLDO4CTL)
Access: User read/write (100)
Address: 0x71 functional page
7
6
5
R
4
3
2
VLDO4EN
W
Default
0
0
0
1
0
X (101)
X (101)
VLDO4
X (101)
X (101)
X (101)
= Unimplemented or Reserved
Notes
100. Read: Anytime
Write: Anytime
101. Default value depends on start-up sequence.
Table 147. VLDO4CTL field descriptions
Field
4
VLDO4EN
3:0
VLDO4
Description
VLDO4 enable bit — VLDO4EN is used to enable or disable the VLDO4 regulator.
0 VLDO4 Disabled
1 VLDO4 Enabled
VLDO4 output voltage configuration— Refer to Table 48.
PF3001

NXP Semiconductors
73
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.5.3.35
Page selection register
This register is used to access the extended register pages.
Table 148. Page selection register
Access: User read/write (102)
Address: 0x7F functional page
7
6
5
4
3
2
R
1
0
0
0
PAGE
W
Default
0
0
0
0
0
0
= Unimplemented or Reserved
Notes
102. Read: Anytime
Write: Anytime
Table 149. Page register field descriptions
Field
3:0
PAGE
Description
Register page selection — The PAGE field is used to select the register pages.
0000 Functional page selected
PF3001
74

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
6.6.6
Register map
The register map is only one page and its addresses and data fields are each eight bits wide. This page registers 0x00 to 0x7F are referred
to as “functional”.
Registers missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect. The contents
of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit
Bit #: The bit location in the register (7-0)
R/W: Read/Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Bits reset by SC and VCOREDIG_PORB
Bits reset by PWRON or loaded default
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
Default: The value after reset, as noted in the default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read/Write bits initialized at start-up. Bits are subsequently I2C modifiable, when their reset has been released. “X”,
may also refer to bits which may have other dependencies. For example, some bits may depend on the version of the IC, or a value
from an analog block, for instance the sense bits for the interrupts.
6.6.6.1
Register map
Table 150. Functional page
BITS[7:0]
Add
Register
Name
R/W
Default
00
DeviceID
R
8'b0011_0000
03
04
05
06
07
08
R
FABID
R
INTMASK0
INTSENSE0
INTSTAT1
6
5
4
–
–
–
–
0
0
1
1
3
2
RW1C
R/W
R
RW1C
1
0
DEVICE ID [3:0]
0
0
FULL_LAYER_REV[3:0]
SILICONREVI
D
INTSTAT0
7
0
1
METAL_LAYER_REV[3:0]
8'b0001_0000
0
0
0
1
0
0
0
–
–
–
–
0
0
0
0
0
0
0
0
–
–
THERM130I
THERM125I
THERM120I
THERM110I
LOWVINI
PWRONI
0
0
0
0
0
0
0
0
–
–
THERM130M
THERM125M
THERM120M
THERM110M
LOWVINM
PWRONM
0
0
1
1
1
1
1
1
ICTEST2S
ICTESTS
THERM130S
THERM125S
THERM120S
THERM110S
LOWVINS
PWRONS
0
0
x
x
x
x
x
x
–
–
–
SW3FAULTI
SW2FAULTI
–
–
SW1FAULTI
0
0
0
0
0
x
0
0
FAB[1:0]
0
FIN[1:0]
8'b0000_0000
8'b0000_0000
8'b0011_1111
8'b00xx_xxxx
8'b0000_0000
PF3001

NXP Semiconductors
75
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 150. Functional page (continued)
BITS[7:0]
Add
Register
Name
R/W
Default
09
INTMASK1
R/W
8'b0111_1111
0A
0E
0F
10
11
12
13
1A
1B
INTSENSE1
INTSTAT3
INTMASK3
INTSENSE3
INTSTAT4
INTMASK4
INTSENSE4
COINCTL
PWRCTL
R
RW1C
R/W
R
RW1C
R/W
R
R/W
R/W
7
6
5
4
3
2
1
0
–
–
–
SW3FAULTM
SW2FAULTM
–
–
SW1FAULTM
0
1
1
1
1
1
1
1
–
–
–
SW3FAULTS
SW2FAULTS
–
–
SW1FAULTS
0
x
x
x
x
x
x
x
–
–
–
–
–
VPWROVI
–
–
0
0
0
0
0
0
0
0
–
–
–
–
–
VPWROVI
–
–
1
1
0
0
0
1
0
1
–
–
–
–
–
VPWROVS
–
–
0
0
0
0
0
0
0
x
–
–
0
0
0
0
0
–
–
VLDO4
FAULTM
VLDO3
FAULTM
V33
FAULTM
0
0
1
1
1
1
1
1
–
–
VLDO4
FAULTS
VLDO3
FAULTS
V33
FAULTS
VCC_SD
FAULTS
VLDO2
FAULTS
VLDO1
FAULTS
0
0
x
x
x
x
x
x
–
–
–
–
COINCHEN
0
0
0
0
0
REGSCPEN
–
0
0
8'b0xxx_xxxx
8'b0000_0000
8'b1100_0101
8'b0000_000x
VLDO4FAULTI VLDO3FAULTI
V33FAULTI
8'b0000_0000
8'b0011_1111
8'b00xx_xxxx
VCC_SDFAUL
VLDO2FAULTI VLDO1FAULTI
TI
0
0
VCC_SDFAUL VLDO2FAULT
TM
M
0
VLDO1FAULT
M
VCOIN[2:0]
8'b0000_0000
–
0
PWRONBDBNC[1:0]
8'b0001_0000
0
1
0
0
PWRONRSTE
N
RESTARTEN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MEMA[7:0]
1C
MEMA
R/W
8'b0000_0000
0
0
0
0
MEMB[7:0]
1D
MEMB
R/W
8'b0000_0000
0
0
0
0
MEMC[7:0]
1E
MEMC
R/W
8'b0000_0000
0
0
0
0
MEMD[7:0]
1F
20
21
22
23
MEMD
SW1VOLT
SW1STBY
SW1OFF
SW1MODE
R/W
R/W
R/W
R/W
R/W
8'b0000_0000
0
0
0
–
–
–
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
0
0
0
–
–
–
–
–
–
–
–
–
0
0
0
x
SW1[4:0]
8'b000x_xxxx
8'b000x_xxxx
8'b000x_xxxx
SW1MODE[3:0]
8'b0000_xxxx
–
–
–
–
PF3001
76

NXP Semiconductors
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 150. Functional page (continued)
BITS[7:0]
Add
Register
Name
R/W
Default
24
SW1CONF
R/W
8'bxx00_xxx0
2E
2F
30
31
32
35
36
37
38
39
3C
3D
3E
3F
40
RSVD
RSVD
RSVD
RSVD
RSVD
SW2VOLT
SW2STBY
SW2OFF
SW2MODE
SW2CONF
SW3VOLT
RSVD
RSVD
SW3MODE
SW3CONF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
–
–
SW1PHASE[1:0]
x
x
0
69
6A
RSVD
RSVD
RSVD
R/W
R/W
R/W
4
–
–
–
x
x
x
–
–
–
x
x
x
–
–
–
0
3
2
SW1FREQ[1:0]
x
x
1
0
–
SW1ILIM
x
0
x
x
x
x
x
x
–
–
–
–
x
x
–
8'b0000_0000
x
x
x
–
8'b0000_0000
x
x
x
–
8'b0000_0000
x
x
x
x
–
–
–
–
x
x
x
x
0
–
–
–
x
–
x
x
–
–
–
–
–
SW2_HL
0
x
x
x
–
–
–
–-
–
–
–
–
–
–
–
–
0
x
x
x
x
x
x
x
–
–
–
–
–
–
–
–
x
x
x
x
–
8'b0001_0000
–
–
–
–
8'bx100_0000
–
SW2[2:0]
8'b0xxx_0110
8'b0xxx_xxxx
8'b0xxx_xxxx
0
x
x
x
–
–
–
–
0
0
0
0
–
–
SW2PHASE[1:0]
x
x
0
1
–
–
–
–
0
x
x
x
–
–
–
–
–
0
x
x
–
–
–
SW2MODE[3:0]
8'b0010_1000
1
0
0
0
–
SW2ILIM
x
0
–
–
–
–
–
–
–
x
–
–
–
–
–
–
–
–
–
–
–
–
–
SW2FREQ[1:0]
8'bxx01_xxx0
x
x
SW3[3:0]
8'b0xxx_1100
8'b0xxx_1100
8'b0xxx_1100
0
x
–
x
–
–
0
–
0
0
1
1
–
–
SW3PHASE[1:0]
x
–
1
SW3MODE[3:0]
8'b0011_1000
1
0
SW3FREQ[1:0]
0
0
–
SW3ILIM
0
0
8'bxx10_xxx0
–
66
5
–
0
–
–
–
–
–
8'b0xx0_0000
0
x
x
0
x
x
x
x
–
–
–
–
–
–
–
–
0
x
x
x
x
x
x
x
–
–
–
–
–
–
–
–
x
x
x
–
x
x
x
x
8'b0xxx_xxx0
8'b000x_0000
PF3001

NXP Semiconductors
77
FUNCTIONAL DESCRIPTION AND APPLICATION INFORMATION
Table 150. Functional page (continued)
BITS[7:0]
Add
Register
Name
R/W
Default
6B
VSNVSCTL
R/W
8'b0000_0110
6C
6D
6E
6F
70
71
7F
VLDO1CTL
VLDO2CTL
VCC_SDCTL
V33CTL
VLDO3CTL
VLDO4CTL
RSVD
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
–
–
–
–
–
0
0
0
0
0
–
–
–
VLDO1EN
0
0
0
–
–
–
–
VLDO2EN
0
0
0
–
–
–
–
–
–
VCC_SDEN
–
–
0
0
0
–
x
x
1
0
VSNVSVOLT[2:0]
1
1
0
–
–-
–
–-
VLDO1[3:0]
8'b010x_1110
–
–
VLDO2[3:0]
8'b000x_1000
VCC_SD[1:0]
8'b000x_xx10
–
–
–
V33EN
–
–
0
0
0
–
x
x
–
–
–
VLDO3EN
0
0
0
–
–
–
–
VLDO4EN
0
0
0
–
–
–
–
0
0
0
–
–
V33[1:0]
8'b000x_xx10
–
–
–
–
–
–
0
0
VLDO3[3:0]
8'b010x_0000
–
–
VLDO4[3:0]
8'b000x_xxxx
–
–
–
8'b0000_0000
0
0
0
PF3001
78

NXP Semiconductors
TYPICAL APPLICATIONS
7
Typical applications
7.1
Application diagram
1.0uF
VIN
VLDO1IN
2.2uF
1.0uF
VLDO2IN
4.7uF
1.0uF
PF3001
VLDO1
100 mA
VLDO1
V33
VLDO2
250 mA
VLDO2
VIN
VLDO34IN
SW1OUT
VLDO3
100 mA
VLDO3
2.2uF
4.7uF
SW1
2.75 A
Buck
VLDO4
350 mA
VLDO4
Core Control logic
VIN
VIN
4.7uF
2 x 22uF
SW1FB
GNDREF1
SW2OUT
V33
350 mA
V33
10uF
SW1IN
100nF
Initialization State Machine
4.7uF
1.5uH
SW1LX
VCC_SD
100 mA
VCC_SD
2.2uF
O/P
Drive
SW2
1.25 A
Buck
Supplies
Control
OTP
VIN2
O/P
Drive
1.5uH
SW2LX
SW2IN
VIN
100nF
4.7uF
2 x 22uF
SW2FB
ICTEST2
VDDIO
VDDIO
CONTROL
SW3OUT
I2C Interface
4.7k
4.7k
100nF
SW3
1.5 A
Buck
SCL
To
MCU
O/P
Drive
SDA
1.5uH
SW3LX
SW3IN
VIN
100nF
4.7uF
2 x 22uF
SW3FB
GNDREF2
Clocks
I2C Map
220nF
VCOREREF
1.0uF
VCORE
32kHz and 16MHz
Reference
Generation
Clocks and
resets
Package Pin Legend
GNDREF
Output Pin
Input Pin
+5V
Bi-directional Pin
VPWR
VREF
100nF
LDOG
VIN*
VIN
Best
of
Supply
VDDIO
100k
VDDIO
100k
0.47uF
SD_VSEL
VSNVS
VSNVS
220nF
Li Cell
Charger
INTB
LICELL
RESETBMCU
2 x 47uF
Coin Cell
Battery
LDO
PWRON
4.7uF
ICTEST1
2 x 47uF
Notes:
*: The PF3001 can also be powered through VIN directly (ie. 3.7 V Li-ion battery
application). In this case, the Front-end LDO regulator is not used ; the external
MOSFET has to be unpopulated and VPWR pin must be connected to GND .
To/From Processor
Figure 26. Typical application schematic
PF3001

NXP Semiconductors
79
BILL OF MATERIALS
8
Bill of materials
The following table provides a complete list of the recommended components on a full featured system using the PF3001 Critical
components are provided with a recommended part number; but equivalent components may be used.
Table 151. Bill of materials for -40 °C to 85 °C applications (103)
Value
Qty
Description
Part#
Manufacturer
Component/pin
PMIC
N/A
1
Power management IC
PF3001
NXP
IC
IND PWR 1.5 H at 1.0 MHz 2.9A 20%
2016
DFE252012P-1R5M
Toko Inc.
SW1, SW2, SW3 inductors
IND PWR 1.5 H at 1.0 MHz 2.2A 20%
1210
BRL3225T1R5M
Taiyo Yuden
Alternate for low power
applications
Buck regulators
1.5 µH
3
4.7 µF
3
CAP CER 4.7 F 10 V 20% X5R 0402
GRM155R61A475MEAA
Murata
SW1, SW2, SW3 input
capacitors
0.1 µF
3
CAP CER 0.1 F 10 V 20% X5R 0603
GRM033R61A104ME84
Murata
SW1, SW2, SW3 input
capacitors (optional)
22 µF
6
CAP CER 22 F 10 V 20% X5R 0201
GRM188R61A226ME15
Murata
SW1, SW2, SW3 output
capacitors
Linear regulators
1.0 µF
3
CAP CER 1.0 F 10 V 20% X5R 0201
GRM033R61A105ME44
Murata
VLDO1, VLDO2, VLDO3, and
VLDO4 input capacitors
2.2 µF
3
CAP CER 2.2 F 10V 20% X5R 0201
GRM033R61A225ME47
Murata
VLDO1, VLDO3, VCC_SD
output capacitors
10 µF
1
CAP CER 10 F 10 V 20% X7R 0402
GRM155R61A106ME11
Murata
V33 and VCC_SD input
capacitor
4.7 µF
3
CAP CER 4.7 F 10V 20% X5R 0402
GRM155R61A475MEAA
Murata
VLDO2, VLDO4, V33 output
capacitors
1.0 µF
4
CAP CER 1.0 F 10V 20% X5R 0201
GRM033R61A105ME44
Murata
VCORE, VCOREDIG,
capacitors
0.22 µF
2
CAP CER 0.22 F 10V 20% X5R 0201
GRM033R61A224ME90
Murata
VCOREREF and coin cell output
capacitors
47 µF
4
CAP CER 47 F 10V 20% X5R 0805
GRM21BR61A476ME15
Murata
Front-end LDO capacitors for
VIN and VPWR
2.2 µF
1
CAP CER 2.2 F 10V 20% X5R 0201
GRM033R61A225ME47
Murata
VIN Input Capacitor when not
using front-end LDO
0.1 µF
4
CAP CER 0.1 F 10V 10% X5R 0201
GRM033R61A104KE84
Murata
VPWR, VIN Input
capacitors (optional)
N/A
1
TRAN PMOS 11. A 12 V 12 SOT-1220
PMPB15XP
NXP
External MOSFET
100 k
2
RES MF 100K 1/16W 1% 0402
RC0402FR-07100KL
Yageo America
Pull-up resistor
4.7 k
2
RES MF 4.70K 1/20W 1% 0201
RC0201FR-074K7L
Yageo America
Pull-up resistor
Miscellaneous
Notes
103. NXP does not assume liability, endorse, or warrant components from external manufacturers are referenced in circuit drawings or tables. While
NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
PF3001
80

NXP Semiconductors
BILL OF MATERIALS
Table 152. Bill of materials for -40 °C to 105 °C applications (104)
Value
Qty
Description
Part#
Manufacturer
Component/pin
PMIC
N/A
1
Power management IC
PF3000
NXP
IC
IND PWR 1.5µ[email protected] 2.9A
20% 2016
DFE201610E-1R5M
TOKO INC.
SW1, SW2, SW3 inductors
IND PWR 1.5µ[email protected] 2.2A
20% 1210
BRL3225T1R5M
Taiyo Yuden
Alternate for low power
applications
Buck regulators
1.5 µH
3
4.7 µF
3
CAP CER 4.7µF 10V 10% X7S
0603
GRM188C71A475KE11
Murata
SW1, SW2, SW3 input
capacitors
0.1 µF
3
CAP CER 0.1µF 10V 10% X7S
0201
GRM033C71A104KE14
Murata
SW1, SW2, SW3 input
capacitors (optional)
22 µF
6
CAP CER 22µF 10V 20% X7T
0805
GRM21BD71A226ME44
Murata
SW1, SW2, SW3 output
capacitors
Linear regulators
1.0 µF
3
CAP CER 1.0µF 10V 10% X7S
0402
GRM155C71A105KE11
Murata
VLDO1, VLDO2, VLDO3 and
VLDO4 input capacitors
2.2 µF
3
CAP CER 2.2µF 10V 10% X7S
0402
GRM155C71A225KE11
Murata
VLDO1, VLDO3, VCC_SD
output capacitors
10 µF
1
CAP CER 10µF 10V 20% X7T
0603
GRM188D71A106MA73
Murata
V33 and VCC_SD input capacitor
4.7 µF
3
CAP CER 4.7µF 10V 10% X7S
0603
GRM188C71A475KE11
Murata
VLDO2, VLDO4, V33 output
capacitors
1.0 µF
4
CAP CER 1.0µF 10V 10% X7R
0402
GRM155C71A105KE11
Murata
VCORE, VCOREDIG capacitors
0.22 µF
2
CAP CER 0.22µF 10V 10% X7R
0402
GRM155R71A224KE01
Murata
VCOREREF and coin cell output
capacitors
47 µF
4
CAP CER 47µF 10V 20% X7R
1210
GRM32ER71A476ME15
Murata
Front-end LDO capacitors for
VIN and VPWR.
2.2 µF
1
CAP CER 2.2µF 10V 10% X7S
0402
GRM155C71A225KE11
Murata
VIN Input Capacitor when not
using front-end LDO
0.1 µF
4
CAP CER 0.1µF 10V 10% X7S
0201
GRM033C71A104KE14
Murata
VPWR, VIN input capacitors
(optional)
N/A
1
TRAN PMOS 11. A 12 V 12 SOT1220
PMPB15XP
NXP
External MOSFET
100 k
2
RES MF 100K 1/16W 1% 0402
RC0402FR-07100KL
YAGEO
AMERICA
Pull-up resistors
4.7 k
2
RES MF 4.70K 1/20W 1% 0201
RC0201FR-074K7L
YAGEO
AMERICA
I²C pull-up resistors
Notes
104. NXP does not assume liability, endorse, or warrant components from external manufacturers are referenced in circuit drawings or tables. While
NXP offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
PF3001

NXP Semiconductors
81
THERMAL INFORMATION
9
Thermal information
9.1
Rating data
The thermal rating data of the packages has been simulated with the results listed in Thermal ratings. Junction to ambient thermal
resistance nomenclature: the JEDEC specification reserves the symbol RJA or JA (Theta-JA) strictly for junction-to-ambient thermal
resistance on a 1s test board in natural convection environment. RJMA or JMA (Theta-JMA) is used for both junction-to-ambient on a
2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p test boards. It is anticipated
the generic name, Theta-JA, continues to be commonly used. The JEDEC standards can be consulted at http://www.jedec.org.
9.2
Estimation of junction temperature
An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RJA x PD)
with:
TA = Ambient temperature for the package in °C
RJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction to ambient thermal resistance is an industry standard value providing a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board RJA and the value obtained on a four
layer board RJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
TJ = TB + (RJB x PD) with
TB = Board temperature at the package perimeter in °C
RJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
PF3001
82

NXP Semiconductors
PACKAGING
10
Packaging
10.1
Packaging dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing's document number. See the Thermal characteristics section for specific thermal characteristics
for each package.
Table 153. Package drawing information
Package
Suffix
Package outline drawing number
48-pin QFN 7X7 mm - 0.5mm pitch
EP
98ASA00719D
48 QFN 7.0 mm x 7.0 mm WF-type (wettable flank)
EP
98ASA00933D
PF3001

NXP Semiconductors
83
PACKAGING
PF3001
84

NXP Semiconductors
PACKAGING
PF3001

NXP Semiconductors
85
PACKAGING
PF3001
86

NXP Semiconductors
PACKAGING
PF3001

NXP Semiconductors
87
PACKAGING
PF3001
88

NXP Semiconductors
REVISION HISTORY
11
Revision history
Revision
Date
1.0
2.0
Description of Changes
8/2015
•
Initial release
9/2015
•
Corrected package image on page 1
•
•
Added 98ASA00933D and the page 1 package image for wettable flank
Changed Table 2, pins 7, 10, 18, and 28, from Bypass with at least a 10 F to Bypass with at least a
4.7 F
Added PC33PF3001A6ES and PC33PF3001A7ES to Table 2
3/2016
•
PF3001

NXP Semiconductors
89
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Document Number: PF3001
Rev. 2.0
3/2016
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