LINEAR TECHNOLOGY VOLUME IX NUMBER 1 FEBRUARY 1999 IN THIS ISSUE… COVER ARTICLE Third-Generation DC/DC Controller Reduces Size and Cost .................. 1 Randy G. Flatness Issue Highlights ............................ 2 LTC® in the News ........................... 2 DESIGN FEATURES New Universal Continuous-Time Filter with Extended Frequency Range ... 7 Max W. Hauser SOT-23 Switching Regulators Deliver Low Noise Outputs in a Small Footprint ................... 11 Steve Pietkiewicz Versatile New Switching Regulator Fits in SO-8 ................................. 14 Craig Varga 16-Bit Parallel DAC Has 1LSB Linearity, Ultralow Glitch and Accurate 4-Quadrant Resistors ... 18 Patrick Copley Fast Rate Li-Ion Battery Charger ................................................... 24 Goran Perica DESIGN IDEAS No RSENSE Controller Delivers 12V and 100W at 97% Efficiency .............. 26 Christopher B. Umminger Generating Low Cost, Low Noise, Dual-Voltage Supplies ................. 27 Third-Generation DC/DC Controllers Reduce Size and Cost Introduction The LTC1735 and LTC1736 are the newest members of Linear Technology’s third generation of DC/DC controllers. These controllers use the same constant frequency, current mode architecture and Burst Mode™ operation as the previous generation LTC1435–LTC1437 controllers but with improved features. With OPTI-LOOP™ compensation, new protection circuitry, tighter load regulation and strong MOSFET drivers, these controllers are ideal for the current and future generations of CPU power applications. The LTC1735 is pin compatible with the previous generation LTC1435/ LTC1435A controllers with only minor external component changes. by Randy G. Flatness Protection features include internal foldback current limiting, output overvoltage crowbar and optional short-circuit shutdown. The 0.8V ±1% reference allows the low output voltages and 1% accuracy that will be demanded by future microprocessors. The operating frequency (synchronizable up to 500kHz) is set by an external capacitor, allowing maximum flexibility in optimizing efficiency. The LTC1736 has all of the features of the LTC1735, plus voltage programming for CPU power, in a 24lead SSOP package. The output voltage in LTC1736 applications is programmed by a 5-bit digital-to-analog converter (DAC) that adjusts the outcontinued on page 3 Ajmal Godil Switched Capacitor Voltage Regulator Provides Current Gain ................. 28 Jeff Witt High Current Step-Down Conversion from Low Input Voltages ............. 30 Dave Dwelley How to Design High Order Filters with Stopband Notches Using the LTC1562 Operational Filter (Part 2) ........... 31 Nello Sevastopoulos DESIGN INFORMATION The LTC1658 and LTC1655: Smallest Rail-to-Rail 14-Bit and 16-Bit DACs ................................................... 36 Hassan Malik New Device Cameos ..................... 37 Design Tools ................................ 39 Sales Offices ............................... 40 Figure 1. LTC1736 evaluation circuit: a complete 5V–24V to 0.9V–2V/12A converter in 2.15in2 of PC board space , LTC and LT are registered trademarks of Linear Technology Corporation. Adaptive Power, Burst Mode, C-Load, FilterCAD, Hot Swap, Linear View, Micropower SwitcherCAD, No RSENSE, Operational Filter, OPTI-LOOP, PolyPhase, SwitcherCAD and UltraFast are trademarks of Linear Technology Corporation. Other product names may be trademarks of the companies that manufacture the products. DESIGN FEATURES to latch off. Defeating this feature will allow easy troubleshooting of the circuit and PC layout. The internal short-circuit detection and foldback current limiting still remain active, thereby protecting the power supply system from failure. After the design is complete, you can decide whether to enable the latch-off feature. Fault Protection: put voltage from 0.925V to 2.00V, Overcurrent Latch-Off LTC1735/LTC1736, continued from page 1 according to Intel mobile VID specifications. Details The LTC1735 and LTC1736 are synchronous step-down switching regulator controllers that drive external N-Channel power MOSFETs using a programmable fixed frequency OPTILOOP architecture. OPTI-LOOP compensation effectively removes the constraints placed on COUT by other controllers for proper operation (such as limits on low ESRs). A maximum duty cycle limit of 99% provides low dropout operation, which extends operating time in battery operated systems. A forced-continuous control pin reduces noise and RF interference and can assist secondary winding regulation by disabling Burst Mode when the main output is lightly loaded. Soft-start is provided by an external capacitor that can be used to properly sequence supplies. The operating current level is userprogrammable via an external current sense resistor. A wide input-supply range allows operation from 3.5V to 30V (36V maximum). Protection New internal protection features in the LTC1735 and LTC1736 controllers include foldback current limiting, short circuit detection, short-circuit latch-off and overvoltage protection. These features protect the PC board, the MOSFETs and the load itself (the CPU) against faults. Fault Protection: Current Limit and Current Foldback The LTC1735/LTC1736 current comparator has a maximum sense voltage of 75mV, resulting in a maximum MOSFET current of 75mV/RSENSE. The LTC1735/LTC1736 includes current foldback to help further limit load current when the output is shorted to ground. If the output falls by more than one-half, the maximum sense voltage is progressively lowered from 75mV to 30mV. Under shortcircuit conditions with very low duty cycle, the LTC1735/LTC1736 will begin cycle skipping in order to limit the short-circuit current. In this situation, the bottom MOSFET will be on most of the time, conducting the current. The average short-circuit current will be approximately 30mV/ RSENSE. Note that this function is always active and is independent of the short circuit latch-off. Fault Protection: Output Overvoltage Protection (OVP) An output overvoltage crowbar turns on the synchronous MOSFET to blow a system fuse in the input lead when Table 1. Overvoltage protection comparison Operating Condition Soft Latch Hard Latch Fast Transients Controls Overshoot Latches Off Output Shorted to 5V Output Clamped at OVP Latches Off 62.5 VID Voltage Decrease Regulates New Voltage Latches Off 50.0 Noise Controls Output Latches Off 100.0 87.5 LTC1735/ LTC1736 75.0 COSC VALUE (pF) The RUN/SS pin, in addition to providing soft-start capability, also provides the ability to shut off the controller and latch off when an overcurrent condition is detected. The RUN/SS capacitor, CSS, (refer to Figure 5) is used initially to turn on and limit the inrush current of the controller. After the controller has been started and given adequate time to charge the output capacitor and provide full load current, CSS is used as a short-circuit timer. If the output voltage falls to less than 70% of its nominal output voltage after C SS reaches 4.2V, it is assumed that the output is in a severe overcurrent and/or short-circuit condition and CSS begins discharging. If the condition lasts for a long enough period, as determined by the size of CSS, the controller will be shut down until the RUN/SS pin voltage is recycled. This built-in latch-off can be overridden by providing >5µA at a compliance of 4V to the RUN/SS pin (refer to the LTC1735/LTC1736 Data Sheet for details). This external current shortens the soft-start period but also prevents net discharge of the RUN/SS capacitor during a severe overcurrent and/or short-circuit condition. Why should you defeat overcurrent latch-off? During the prototyping stage of a design, there may be a problem with noise pickup or poor layout causing the protection circuit 37.5 Shorted Top MOSFET LTC1435/ LTC1436 25.0 Output Voltage Can Reverse 12.5 0 0 100 200 300 400 500 OPERATING FREQUENCY (kHz) 600 Figure 2. COSC value vs frequency for the LTC1435/36 and the LTC1735/36 Linear Technology Magazine • February 1999 Bottom MOSFET Overloads Bottom MOSFET Overloads No When Overload is Removed Resumes Normal Operation Troubleshooting Faults Easy DC Measurements Yes Remains Latched Off Difficult; May Require Digital Oscilloscopes 3 DESIGN FEATURES Table 2. FCB possible states FCB Pin DC Voltage: 0V–0.7V Condition Burst Disabled/ Forced Continuous, Current Reversal Enabled DC Voltage: > 0.9V Burst Mode, No Current Reversal Feedback Resistors Regulating a Secondary Winding (VFCBSYNC > 1.5V) Burst Mode Disabled, No Current Reversal the output of the regulator rises much higher than nominal levels. The crowbar can cause huge currents to flow, greater than in normal operation. This feature is designed to protect against a shorted top MOSFET or short circuits to higher supply rails; it does not protect against a failure of the controller itself. Previous latching crowbar schemes for overvoltage protection have a number of problems (see Table 1). One of the most obvious, not to mention most annoying, is nuisance trips caused by noise or transients momentarily exceeding the OVP threshold. Each time that this occurs with latching OVP, a manual reset is required to restart the regulator. Far more subtle is the resulting output voltage reversal. When the synchronous MOSFET latches on, a large reverse current is loaded into the inductor while the output capacitor is discharging. When the output voltage reaches zero, it does not stop there, but rather continues to go negative until the reverse inductor current is 100% 90% BURST EFFICIENCY (%) 80% 70% 60% SYNC 50% CONTINUOUS 40% 30% 20% 0.001 0.01 0.1 1.0 LOAD CURRENT (A) 10.0 Figure 3. Efficiency vs load current for three modes of operation 4 depleted. This requires a sizable Schottky diode across the output to prevent excessive negative voltage on the output capacitor and load. A further problem on the horizon for latching OVP circuits is their incompatibility with on-the-fly CPU core voltage changes. If an output voltage is reprogrammed from a higher voltage to a lower voltage, the OVP will temporarily indicate a fault, since the output capacitor will momentarily hold the previous, higher output voltage. With latching OVP, the result will be another latch-off, with a manual reset required to attain the new output voltage. To prevent this problem, the OVP threshold must be set above the maximum programmable output voltage, which would do little good when the output voltage was programmed near the bottom of its range. In order to avoid these problems with traditional latching OVP circuits, the LTC1735 and LTC1736 use a new “soft latch” OVP circuit. Regardless of operating mode, the synchronous MOSFET is forced on whenever the output voltage exceeds the regulation point by more than 7.5%. However, if the voltage then returns to a safe level, normal operation is allowed to resume, thereby preventing latch-off caused by noise or voltage reprogramming. Only in the case of a true fault, such as a shorted top MOSFET, will the synchronous MOSFET remain latched on until the input voltage collapses or the system fuse blows. The new soft latch OVP also provides protection and easy diagnosis of other overvoltage faults, such as a lower supply rail shorted to a higher voltage. In this scenario, the output voltage of the higher regulator is pulled down to the OVP voltage of the soft-latched regulator, allowing the problem to be easily diagnosed with DC measurements. On the other hand, latching OVP provides only a millisecond glimpse of the fault as it latches off, forcing the use of expensive digital oscilloscopes for troubleshooting. Three Operating Modes/One Pin: Sync, Burst Disable and Secondary Regulation The FCB pin is a multifunction pin that controls the operation of the synchronous MOSFET and is an input for external clock synchronization. When the FCB pin drops below its 0.8V threshold, continuous mode operation is forced. In this case, the top and bottom MOSFETs continue to be driven synchronously regardless of the load on the main output. Burst Mode operation is disabled and current reversal is allowed in the inductor. In addition to providing a logic input to force continuous synchronous operation and external Table 3. Comparison of LTC1735/36 controllers with LTC1435A/36A-PLL controllers Parameter LTC1735/1736 LTC1435A/1436A-PLL Reference 0.8V 1.19V Load Regulation 0.1% Typ, 0.2% Max 0.5% Typ 0.8% Max Max Current Sense 75mV 150mV Minimum On-Time 200ns 300ns Synchronizable Yes LTC1436A-PLL Only Int VCC Voltage 5.2V (7V Max) 5V (10V Max) Power Good Output LTC1736 Only LTC1436A/36A-PLL Only Current Foldback Internal External Output OV Protection Yes No Output OI Latch-Off Optional No Packages SO16, GN16/G24 SO16, G16/GN24 MOSFET Drivers 3× 1× Linear Technology Magazine • February 1999 DESIGN FEATURES 30 no external connections are made, the FCB pin is pulled high by a 0.25µA internal current source. The LTC1735 internal oscillator can be synchronized to an external oscillator by applying a clock signal of at least 1.5VP-P to the FCB pin. When synchronized to an external frequency, Burst Mode operation is disabled but cycle skipping occurs at low load currents since current reversal is inhibited. The bottom gate will come on every 10 clock cycles to ensure that the bootstrap cap is kept refreshed and to keep the frequency above the audio range. The rising edge of an external clock applied to the FCB pin starts a new cycle. The range of synchronization is from 0.9 × fO to 1.3 × fO, with fO set by COSC. Attempting to synchronize to a higher frequency than 1.3 × fO can result in inadequate slope compensation and cause loop instability with high duty cycles. If loop instability is observed while synchronized, additional slope compensation can be obtained by simply decreasing COSC. A plot of operating frequency versus COSC value is shown in Figure 2. Table 2 summarizes the possible states available on the FCB pin. Figure 3 gives a comparison of efficiencies in a regulator for the three operating modes: forced continuous operation, pulse skipping mode (synchronized at f = fO) and Burst Mode operation. B4 B3 B2 B1 B0 VOUT (V) 0 0 0 0 0 2.000V 0 0 0 0 1 1.950V 0 0 0 1 0 1.900V 0 0 0 1 1 1.850V 0 0 1 0 0 1.800V 0 0 1 0 1 1.750V 0 0 1 1 0 1.700V 0 0 1 1 1 1.650V 0 1 0 0 0 1.600V 0 1 0 0 1 1.550V 0 1 0 1 0 1.500V 0 1 0 1 1 1.450V 0 1 1 0 0 1.400V 0 1 1 0 1 1.350V 0 1 1 1 0 1.300V 0 1 1 1 1 * 1 0 0 0 0 1.275V 1 0 0 0 1 1.250V 1 0 0 1 0 1.225V 1 0 0 1 1 1.200V 1 0 1 0 0 1.175V 1 0 1 0 1 1.150V 1 0 1 1 0 1.125V 1 0 1 1 1 1.100V 1 1 0 0 0 1.075V 1 1 0 0 1 1.050V 1 1 0 1 0 1.025V 1 1 0 1 1 1.000V 1 1 1 0 0 0.975V OFF 1 1 1 0 1 0.950V ON 1 1 1 1 0 0.925V 1 1 1 1 1 ** Note: *, ** represent codes without a defined output voltage as specified in Intel specifications. The LTC1736 interprets these codes as a valid inputs and produces output voltage as follows: [01111]=1.250V, [11111]=0.900V. synchronization, the FCB pin provides a means to regulate a flyback winding output. It can force continuous synchronous operation when needed by the flyback winding, regardless of the primary output load. In order to prevent erratic operation if Linear Technology Magazine • February 1999 JP1 BURST MODE 10 5 200 1 2 3 330pF 4 100pF 5 6 CS1, 1000pF 7 8 RUN/SS FCB SGND 400 TG BOOST 600 The LTC1735 is pin compatible with the LTC1435/LTC1435A, with minor component changes. Table 3 shows the differences between the two controllers. The important items to note are: 1. The LTC1735 has a 0.8V reference (versus 1.19V for the LTC1435) that allows lower output voltage operation (down to 0.8V). Thus, the output feedback divider will have to be recalculated for the same output voltage. 2. The LTC1735’s maximum current sense voltage is half that of the LTC1435. This reduces the power lost in the sense resistor by half. Hence, for the same maximum output current, the current sense resistor must be cut in half. + 16 15 VIN INT VCC BG SENSE– PGND SENSE+ EXT VCC M2 FDS6680A 0.22µF 14 CB1 13 D1 CMDSH-3 SW VOSENSE 12 11 + C4 1µF 10 9 C2 4.7µF M1 FDS6680A CIN1 CIN3 22µF 22µF 30V 30V L1† + RCS1 0.005Ω VOUT 1.6V/9A 2µH C3 47pF D2 MBRS340T3 EXT VCC R5 10Ω RS1 10Ω R7 10k 1% R3 10k 1% R2 10Ω †PANASONIC ETQP6F2R0HFA *SANYO OSCON 4SP820M 500 Converting to the LTC1735 RF1 4.7Ω CF1 0.1µF COSC LTC1735 ITH 300 Figure 4. MOSFET gate-charge current vs frequency R6, 1M 0.1µF RC1 33k C1 47pF 15 +VIN JP2 LATCH-OFF (DISABLED) COSC1 47pF CC2 20 FREQUENCY (kHz) RUN CSS TOP AND BOTTOM MOSFETS = FAIRCHILD NDS6680A 25 0 100 FCB/SYNC INT VCC CC1 GATE-CHARGE CURRENT (mA) Table 4. VID output voltage programming (201) 348-7522 (619) 661-6835 VO CO1 180µF 4V + CO3* 820µF 4V GND Figure 5. High efficiency 1.6V/9A CPU power supply 5 DESIGN FEATURES Linear Current Comparator Operation 3. The gate drivers of the LTC1735 are 3× the strength of those in the LTC1435. This equates to faster rise and fall times for driving the same MOSFETs plus the capability to drive larger MOSFETs with less efficiency loss due to transition losses. Since the trend in the marketplace has forced output voltages to lower and lower values, the current sense inputs have been optimized for low voltage operation. The current sense comparator has a linear response characteristic, without discontinuities, from 0V to 6V output voltages. In the LTC1435/LTC1435A, two input stages are used to cover this range, so an overlap exists together with a transition region. The LTC1735/LTC1736 uses only one input stage and includes slope compensation that operates over the full output voltage range. This allows the LTC1735/LTC1736 to be operated in grounded RSENSE applications as well. Speed The LTC1735/LTC1736 are designed to be used in higher current applications than the LTC1435 family. Stronger gate drives allow paralleling multiple MOSFETs or higher operating frequencies. The LTC1735 has been optimized for low output voltage operation by reducing the minimum on-time to less than 200ns. Remember, though, that transition losses can still impose significant efficiency penalties at high input voltages and high frequencies. Just because the LTC1735 can operate at frequencies above 300kHz doesn’t mean it should. Figure 4 shows a plot of MOSFET charge current versus frequency. LTC1736 Additional Features The LTC1736 includes all the features of the LTC1735, plus 5-bit mobile VID control and a power-good comparator in a 24-lead SSOP package. The window comparator monitors the output voltage and its open-drain output is pulled low when the divided Pentium is a registered trademark of Intel Corp. JP1 BURST MODE FCB/SYNC OFF JP2 LATCH-OFF (DISABLED) ON INT VCC COSC1 47pF RC1 33k CC1 330pF CC2 100pF 1 3 4 5 6 PGOOD INT VCC CS1, 1000pF C1 47pF 7 8 9 10 C3 47pF CF1 0.1µF RF1 4.7Ω + R6, 680k 2 R1 100k +VIN RUN 11 12 24 COSC LTC1736 TG BOOST RUN/SS ITH SW FCB VIN INT VCC SGND PGOOD BG SENSE– PGND SENSE+ EXT VCC VFB VID VCC 21 D1 CMDSH-3 20 + C4 1µF 18 VOSENSE B4 B0 B3 B1 B2 Figure 5 shows a 1.6V/9A application using the LTC1735. The input voltage can range from 6V to 26V. Figure 6 shows a VID application using the LTC1736 optimized for output voltages of 1.6V to 1.3V with a 5V to 24V input voltage range. continued on page 35 L1† 1.2µH RCS1 0.004Ω D2 MBRS340T3 C2 4.7µF 16 15 Applications CB1 0.22µF 22 17 + M2 FDS6680A 23 19 CIN1 CIN3 22µF 22µF 30V 30V voltage is not within ±7.5% of the 0.8V reference voltage. The output voltage is digitally set to levels between 0.925V and 2.00V using the voltage identification (VID) inputs B0–B4. The internal 5-bit DAC configured as a precision resistive voltage divider sets the output voltage in 50mV or 25mV increments according to Table 4. The VID codes (00000–11110) are compatible with the Intel mobile Pentium® II processor. The LSB (B0) represents 50mV increments in the upper voltage range (2.00V–1.30V) and 25mV increments in the lower voltage range (1.275V– 0.925V). The MSB is B4. When all bits are low or grounded, the output voltage is 2.00V. The LTC1736 also has remote sense capability. The top of the internal resistive divider is connected to VOSENSE and is referenced to the SGND pin. This allows a Kelvin connection for remotely sensing the output voltage directly across the load, eliminating any PC board trace resistance errors. EXT VCC VOUT 0.9V–2.0V /12A RS1 10Ω VO M1, M3 FDS6680A ×2 14 + CO3* 820µF 4V 13 MSB LSB JP4 E D C B A R5 10Ω R2 10Ω †PANASONIC ETQP6F2R0HFA *PANASONIC EEFVEOG181R (201) 348-7522 Authors can be contacted at (408) 432-1900 Figure 6. High efficiency, VID programmable, 0.9V–2.0V/12A CPU power supply 6 Linear Technology Magazine • February 1999 CONTINUATIONS range. This is true provided the filter magnitude response does not change with varying input signal levels, that is, the filter gain is linear. The gain linearity measured at the 100kHz theoretical center frequency of the filter is shown in Figure 7. The gain is perfectly linear for input amplitudes up to 1.25VRMS (3.5VP-P) so an 84dB dynamic range can be claimed. The input signal, however, can reach amplitudes up to 3VRMS (8.4VP-P, 92dB SNR) with some reduction in gain linearity. The LTC1735 and LTC1736 are the latest members of Linear Technology’s family of constant frequency, N-channel high efficiency controllers. With new protection features, improved circuit operation and strong MOSFET drivers, the LTC1735 is an ideal upgrade to the LTC1435/LTC1435A for higher current applications. With the integrated VID control, the LTC1736 is ideal for CPU power applications. The high performance of these controllers with wide input range, 1% reference and tight load regulation makes them ideal for next generation designs. LTC1562-2, continued from page 10 References level is 44µVRMS over a bandwidth of 800kHz or 98dB below the maximum unclipped output. 1. Hauser, Max. “Universal Continuous-Time Filter Challenges Discrete Designs.” Linear Technology VIII:1 (February 1998), pp. 1–5 and 32. 2. Sevastopoulos, Nello. “How to Design High Order Filters with Stopband Notches Using the LTC1562 Quad Operational Filter, Part 1.” Linear Technology VIII:2 (May 1998), pp. 28-31. 3. Sevastopoulos, Nello. “How to Design High Order Filters with Stopband Notches Using the LTC1562 Quad Operational Filter, Part 2.” in the Design Ideas section of this issue of Linear Technology. 4. LTC1562 Final Data Sheet. 5. For example: Schwartz, Mischa. Information Transmission, Modulation, and Noise, fourth edition, pp. 180–192. McGraw-Hill 1990. band gain can be higher than 0dB or if internal nodes are allowed to have gains higher than 0dB. Please contact the LTC Filter Design and Applications Group for further details. The low noise behavior of the filter makes it useful in applications where the input signal has a wide voltage LTC1735/LTC1736, continued from page 6 Conclusion Acknowledgments Philip Karantzalis and Nello Sevastopoulos of LTC’s Monolithic Filter Design and Applications Group contributed to the application examples. LT1505, continued from page 25 SW, VBAT and GND in Figure 2 will help in spreading the heat and will reduce the power dissipation in conductors and MOSFETs. By doing so, the required peak power from the wall adapter can be much lower than the peak power required by the load. The wall adapter has to supply the average power only. The LT1505 can also be used in other system topologies, such as the telecom application shown in Figure 5. The circuit in Figure 5 uses the battery to supply peak power demands. Conclusion The LT1505 is a complete, singlechip battery charger solution for today’s demanding charging requirements in high performance laptop applications. The device requires a small number of external components and provides all necessary functions for battery charging and power management. High efficiency and small size allow for easy integration with the laptop circuits. Also, by adding a simple external circuit, charging can be easily controlled by the host computer, allowing for more sophisticated charging schemes. Step-Down Conversion, continued from page 30 cuitry works in the same manner as in Figure 1. Efficiency and performance are virtually the same as the LTC1649 solution, but parts count and system cost are lower. In a 3.3V to 2.5V application, the steady-state, no-load duty cycle is 76%. If the input supply drops to 3.135V (3.3V – 5%), the duty cycle requirement rises to 80% at no load, and even higher under heavy or transient load conditions. Both the LTC1649 and the LTC1430A guarantee a maximum duty cycle of greater than 90% to provide acceptable load regulation and transient response. The standard LTC1430 (not the LTC1430A) can max out as low as 83%—not high enough for 3.3V to 2.5V circuits. Applications with larger step-down ratios, such as 3.3V to 2.0V, can use the circuit in Figure 3 successfully with a standar d LTC1430. Other Applications lower cost LTC1430A replacing the LTC1649. The LTC1430A does not include the 3.3V to 5V charge pump and requires a 5V supply to drive the external MOSFET gates. The current drawn from the 5V supply depends on the gate charge of the external MOSFETs but is typically below 50mA, regardless of the load current on the 2.5V output. The drains of the Q1/Q2 pair draw the main load current from the 3.3V supply. The remaining cirLinear Technology Magazine • February 1999 35