Data Sheet

Freescale Semiconductor
Data Sheet: Advance Information
Document Number: MMA27XXW
Rev. 0.5, 4/2013
An Energy-Efficient Solution by Freescale
Xtrinsic MMA27XXW/17XXW DSI3
Inertial Sensor
MMA27XXW
MMA17XXW
MMA27XXW/17XXW family, a SafeAssure solution, includes the DSI3 compatible
overdamped X-axis or Z-axis satellite accelerometers.
Bottom View
Features
•
±25 g, ±125 g, ±187 g, ±250 g, ±375 g, X-axis nominal full-scale range
•
±250 g, Z-axis nominal full-scale range
•
DSI3 compatible
—
Discovery Mode for physical location identification
— High-side bus switch output driver
— Command and Response Mode support for device configuration
— Periodic Data Collection Mode support for acceleration data transfers
—
-40°C to 125°C operating temperature range
Single-pole, IIR high-pass filter with fast startup and optional output rate limiting
•
Pb-Free, 16-pin QFN, 6 x 6 package
VBUF
•
TEST2
Top View
TEST
16 μs internal sample rate, with interpolation to 1 μs
Six selectable low-pass filter options from 180 Hz to 1200 Hz
BUSSW
•
•
16 15 14 13
•
AEC-Q100, Revision G, dated May 14, 2007
BUS_O
1
NC
2
11 VREGA
BUS_I
3
10 TEST_CS
BUSRTN
4
9
ORDERING INFORMATION
Part Number
Axis
Range
Package
Shipping
MMA2702W
X
±25 g
2086-01
Rail
MMA2712W
X
±125 g
2086-01
Rail
MMA2718W
X
±187 g
2086-01
Rail
MMA2725W
X
±250 g
2086-01
Rail
MMA2737W
X
±375 g
2086-01
Rail
MMA1725W
Z
±250 g
2086-01
Rail
MMA2702WR2
X
±25 g
2086-01
Tape & Reel
MMA2712WR2
X
±125 g
2086-01
Tape & Reel
MMA2718WR2
X
±187 g
2086-01
Tape & Reel
MMA2725WR2
X
±250 g
2086-01
Tape & Reel
MMA2737WR2
X
±375 g
2086-01
Tape & Reel
MMA1725WR2
Z
±250 g
2086-01
Tape & Reel
This document contains information on a new product. Specifications and information herein
are subject to change without notice. Freescale reserves the right to change the detail
© 2013 Freescale Semiconductor, Inc. All rights reserved.
12 VSS
17
5
6
7
8
TEST_MOSI
DSI3 Standard Revision 1.0, Dated February 16, 2011
TEST_MISO
•
PCM
Referenced Documents
TEST_SCLK
•
16-PIN QFN
6 MM X 6 MM X 2 MM
CASE 2086-01
Background Diagnostic Mode support during Periodic Data Collection
Mode
Pin Connections
VREG
Contents
1
2
3
4
5
6
7
8
Block Diagram, Pin Descriptions, Application Diagram, and Device Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Device orientation and device marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.3 Electrical characteristics - supply and I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.4 Electrical Characteristics - sensor and signal chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.5 Electrical characteristics - self-test and overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.6 Dynamic electrical characteristics - DSI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.7 Dynamic electrical characteristics - signal chain. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.8 Dynamic electrical characteristics - supply and support circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 User-accessible data array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 OTP and Read/Write register array CRC verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 Voltage regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.4 Internal oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.5 Acceleration signal path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.6 DSI3 physical layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
3.7 Data transmission modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.8 Initialization timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.9 Overload response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
DSI3 Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.1 Address assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
4.2 DSI3 Command and Response Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.3 DSI3 Periodic Data Collection Mode and Background Diagnostic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
4.4 Maximum number of devices on a network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Recommended Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Related Documentation
The MMA27XXW and MMA17XXW devices features and operations are described in a variety of reference manuals, user guides,
and application notes. To find the most-current versions of these documents:
1.
Go to the Freescale homepage at:
http://www.freescale.com/
2.
3.
In the Keyword search box at the top of the page, enter the device number MMA27XXW or MMA17XXW.
In the Refine Your Result pane on the left, click on the Documentation link.
MMA27XXW
2
Sensors
Freescale Semiconductor, Inc.
1
Block Diagram, Pin Descriptions, Application Diagram, and Device
Orientation
1.1
Block diagram
VBUF
Buffer
Voltage
Regulator
BUS_I
Reference
Voltage
VBUF
Internal
Voltage
Regulator
VREF
VREG
VREG
VREGA
VREGA
VBUF
DSI3 Command
Decoder
Low Voltage
Detection
VSS
NVM Programming
Interface
Oscillator
OTP
Serial
Encoder
Array
BUSRTN
TEST_CS
Control
Logic
BUS_I
TEST_SCLK
SPI
RSENSE
TEST_MOSI
BUS_O
TEST_MISO
Daisy-Chain
Switch Driver
BUSSW
PCM
Encoder
PCM
VREG
Self-test
Interface
VREGA
VREG
CONTROL SIGNAL
IN
OUT
DSP
g-cell
ΣΔ
Converter
Sinc filter
Digital
Gain
IIR
LPF
Offset
Monitor
HPF
Interpolation
Compensation
Figure 1. Internal block diagram
MMA27XXW
Sensors
Freescale Semiconductor, Inc.
3
VBUF
TEST2
TEST
Pin descriptions
BUSSW
1.2
16 15 14 13
BUS_O
1
12 VSS
NC
2
11 VREGA
BUS_I
3
10 TEST_CS
BUSRTN
4
9
5
6
7
8
PCM
TEST_SCLK
TEST_MISO
TEST_MOSI
17
VREG
Figure 2. Pin connections
Table 1. Pin descriptions
Pin
Pin name
Formal name
Definition
This pin is connected to the BUS_I pin through an internal sense resistor and provides the supply
connection to the next slave in a daisy-chain configuration. An external capacitor must be connected
between this pin and VSS. Reference Figure 3.
1
BUS_O
Supply out
2
NC
Not connected
This pin is not internally connected and must be left unconnected or tied to VSS in the application.
3
BUS_I
Supply and
communication
This pin is connected to the DSI supply line and supplies power to the device. An external capacitor must
be connected between this pin and BUSRTN. Reference Figure 3.
4
BUSRTN
Supply return
This pin is the DSI supply return node.
Pulse code
If the PCM output is enabled, this pin provides a 4 MHz PCM signal proportional to the acceleration data
modulated output for test purposes. If PCM is unused, this pin must be left unconnected.
5
PCM
6
TEST_SCLK
SPI clock
7
TEST_MISO
SPI data out
8
TEST_MOSI
SPI data in
9
VREG
Internal
supply
10
TEST_CS
Chip select
11
VREGA
Internal
supply
12
VSS
Internal supply
return
This pin is the power supply return node for the internal power supplies and must be connected to
BUSRTN in this application.
13
VBUF
Power supply
This pin is connected to a buffer regulator for the internal circuitry. The buffer regulator supplies the
internal regulators to provide immunity from EMC and supply dropouts. An external capacitor must be
connected between this pin and VSS. Reference Figure 3.
14
TEST2
Test pin
This pin is must be connected to VSS in the application.
15
TEST
Test pin
This pin is must be connected to VSS in the application.
16
BUSSW
Bus switch gate
drive
This pin is the drive for a high-side, daisy-chain switch. When switch is connected, daisy-chain mode is
used, this pin is connected to the gate of a p-channel FET which connects BUS_I to the next slave in the
daisy chain. An external pullup resistor is required on the gate of the p-channel FET. Reference
Section 3.6.4. If unused, this pin must be left unconnected.
17
PAD
Die attach pad
This pin is the die attach flag, and is internally connected to VSS. Reference Section 6 for die attach pad
connection details.
Corner pads
Corner pads
This input pin provides the serial clock to the SPI port for test purposes. An internal pull-down device is
connected to this pin. This pin must be grounded or left unconnected in the application.
This pin functions as the serial data output from the SPI port for test purposes. This pin must be left
unconnected in the application.
This pin functions as the serial data input to the SPI port for test purposes. An internal pull-down device
is connected to this pin. This pin must be grounded or left unconnected in the application.
This pin is connected to the power supply for the internal circuitry. An external capacitor must be
connected between this pin and VSS. Reference Figure 3.
This input pin provides the chip select to the SPI port for test purposes. An internal pullup device is
connected to this pin. This pin must be left unconnected in the application.
This pin is connected to the power supply for the internal circuitry. An external capacitor must be
connected between this pin and VSSA. Reference Figure 3.
The corner pads are internally connected to VSS.
MMA27XXW
4
Sensors
Freescale Semiconductor, Inc.
1.3
Application diagram
VBUF
VREG
BUS_I
VREGA
C2
C3
Optional for ESD
BUS_I
C1
BUSIN
D1
C4
BUSRTN
BUSRTN
VSS
C5
BUSOUT
BUS_O
BUS_I
C6
R1
BUSSW
Optional for
Daisy Chain
M1
BUSOUTDC
Figure 3. MMA27XXW/17XXW application diagram
Table 2. External component recommendations
Ref Des
Type
Description
Purpose
C1
Ceramic
220 pF, 10%, 50 V minimum, X7R
BUSIN EMC and ESD protection. Capacitor value is dependent
on the DSI3 master device and must be chosen by the system
implementer.
C2
Ceramic
1 μF, 10%, 10 V minimum, X7R
Voltage regulator output capacitor
C3
Ceramic
1 μF, 10%, 10 V minimum, X7R
Voltage regulator output capacitor
C4
Ceramic
1 μF, 10%, 10 V minimum, X7R
Voltage regulator output capacitor
C5
Ceramic
100 pF, 10%, 50 V minimum, X7R
BUSOUT EMC and ESD protection
C6
Ceramic
100 pF, 10%, 50 V minimum, X7R
BUSOUT EMC and ESD protection
100 kΩ, 5%, 200 PPM
R1
General purpose
M1
P-channel MOSFET
D1
Zener diode
Pullup resistor for external high-side, daisy-chain FET
High-side, daisy-chain transistor
MMBZ27Vxxxx or equivalent
ESD protection diode
MMA27XXW
Sensors
Freescale Semiconductor, Inc.
5
X: 0 g
Z: 0 g
X: +1 g
Z: 0 g
xxxxxxx
xxxxxxx
xxxxxxx
xxxxxxx
Device orientation and device marking
xxxxxxx
xxxxxxx
1.4
xxxxxxx
xxxxxxx
X: 0 g
Z: 0 g
X: -1 g
Z: 0 g
X: 0 g
Z: +1 g
X: 0 g
Z: -1 g
EARTH GROUND
Figure 4. Device orientation diagram
MMAx7xxW
AWLYWWZ
Data Code Legend:
A: Assembly Location
WL: Wafer Lot Number (g-cell Lot Number)
Y: Year
WW: Work Week
Z: Assembly Lot Number
Figure 5. Device marking
MMA27XXW
6
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Freescale Semiconductor, Inc.
2
Electrical Characteristics
2.1
Maximum ratings
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.
#
Rating
Symbol
Value
Unit
BUS_I_REV
BUS_I_MAX
BUS_I_TRANS
-0.7
+20.0
+25.0
V
V
V
(6)
(6)
(9)
1
2
3
4
Supply voltage (BUS_I, BUS_O, BUSSW)
Reverse current ≤ 160 mA, t ≤ 80 ms
Continuous
Transient (< 10 us)
5
VBUF
-0.3 to +4.0
V
(6)
6
VREG, VREGA, TEST_SCLK, TEST_CS, TEST_MOSI, TEST_MISO, PCM
-0.3 to +3.0
V
(6)
7
8
9
BUS_I, BUS_O and BUSRTN current
Maximum duration 560 μs, with 10 ms repetition rate
Continuous
IIN
IIN
200
150
mA
mA
(6)
(6)
10
Powered shock (six sides, 0.5 ms duration)
gpms
±2000
g
(5)
11
Unpowered shock (six sides, 0.5 ms duration)
gshock
±2000
g
(5)
12
Drop shock (to concrete, tile or steel surface, 10 drops, any orientation)
hDROP
1.2
m
(5)
13
14
Electrostatic discharge (per AEC-Q100), external pins
BUS_I, BUS_O, BUSRTN, HBM (100 pF, 1.5 kΩ)
VESD
±4000
V
(5)
15
16
17
18
Electrostatic discharge (per AEC-Q100)
HBM (100 pF, 1.5 kΩ)
CDM (R = 0 Ω)
MM (200 pF, 0 Ω)
VESD
VESD
VESD
±2000
±500
±200
V
V
V
(5)
(5)
(5)
19
20
21
Temperature range
Storage
Junction
Tstg
TJ
-40 to +125
-40 to +150
°C
°C
(5)
(9)
22
Thermal resistance
θJC
2.5
°C/W
(9,11)
2.2
Operating range
VBUS_I_L ≤ (VBUS_I - VSS) ≤ VBUS_I_H, TL ≤ TA ≤ TH, ΔT ≤ 12°C/min, unless otherwise specified.
#
Characteristic
23 Supply voltage (measured at BUS_I pin)
VHIGH
24
VLOW rising
25
VLOW falling
26
27 Supply voltage (undervoltage)
Programming voltage (IRD ≤ 85 mA)
28
Applied to BUS_I
29 ESD operating voltage
30 (No device reset, CBUS_IN = 220 pF, D1 = MMBZ27Vxxxx)
Maximum ±15 kV air discharge, 330 pF, 2.0 kΩ
31
32 Operating temperature range
33
34
*
*
Symbol
Min
Typ
Max
Units
VBUS_I_HIGH_max
VBUS_I_LOW_Rise
VBUS_I_LOW_Fall
VBUS_I_UV
—
4.5
4.0
20.0
—
—
VBUS_I_UV_F
—
—
—
—
VBUS_I_LOW_Fall
V
V
V
V
(1,6)
(9)
(1)
(3,6)
VPP
14.0
—
VBUS_I_HIGH_max
V
(6)
VBUS_I_ESD
—
—
12.0
V
(9)
TA
TA
TL
-40
-40
—
—
TH
+105
+125
°C
°C
(1)
(5,6)
MMA27XXW
Sensors
Freescale Semiconductor, Inc.
7
2.3
Electrical characteristics - supply and I/O
VBUS_I_L ≤ (VBUS_I - VSS) ≤ VBUS_I_H, TL ≤ TA ≤ TH, ΔT ≤ 12 °C/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
35
Quiescent supply current
VBUS_I = 4 V, VBUS_I = 20 V
*
Iq
4.0
—
8.0
mA
(1)
36
37
Response current
Low
High
*
*
IRESP
2*IRESP
Iq+ 10.50
Iq+ 21.0
Iq+ 12.0
Iq+ 24.0
Iq+ 13.5
Iq+ 27.0
mA
mA
(1)
(1)
IINRUSH_MAX
—
—
30
mA
(6)
VBUF
VREG
VREGA
3.250
2.400
2.425
3.400
2.500
2.500
3.550
2.600
2.575
V
V
V
(1)
(1)
(1)
VBUS_I_UV_F
VBUF_UV_F
VREG_UV_F
VREGA_UV_F
VHYST
3.60
2.80
2.15
2.15
0.04
3.75
3.05
2.25
2.25
—
3.90
3.20
2.35
2.35
—
V
V
V
V
V
(3,6)
(3,6)
(3,6)
(3,6)
(6)
CVBUF, CVREG, CVREGA
ESR
500
0
1000
—
1500
200
nF
mΩ
(9)
(9)
V
mV
(3,6)
(6)
38 VBUF current limit
39
40
41
Internally regulated voltages
VBUF, VBUS_I = 4 V, VBUS_I = 20 V
VREG, VBUS_I = 4 V
VREGA, VBUS_I = 4 V, VBUS_I = 20 V
42
43
44
45
46
Low-voltage detection threshold
BUS_I falling
VBUF falling
VREG falling
VREGA falling
Low-voltage detection hysteresis
47
48
External capacitor (VBUF, VREG, VREGA)
Capacitance
ESR (including interconnect resistance)
49
50
VLOW detection threshold (Section 3.6.1)
VLOW detection threshold
VLOW detection hysteresis
51
52
Discovery Mode current sense (Section 3.6.3)
Sense resistor
IRESP detection threshold (IBUS_O_q ≤ 24 mA)
53
54
*
*
*
VDELTA_THRESH
VDELTA_THRESH_Hyst
VHIGH-1.25 VHIGH-1.0 VHIGH-0.75
40
60
80
RSENSE
IRESP_Det, VIRESP_Offset
1.3
6
2.15
12
3
18
Ω
mA
(6)
(3,6)
Bus switch output low voltage (Section 3.6.4)
ILoad = 100 μA
VBUS_SW_OL
0.0
—
0.45
V
(3,6)
Bus switch open drain output leakage current (BUSSW)
VBUSSW = 20 V
IBUS_SW_ODL
—
—
10
μA
(3,6)
VOH
VREG - 0.1
—
—
V
(3)
VOL
—
—
0.1
V
(3)
Output high voltage (PCM)
55 ILoad = -100 μA
Output low voltage (PCM)
56 ILoad = 100 μA
MMA27XXW
8
Sensors
Freescale Semiconductor, Inc.
2.4
Electrical Characteristics - sensor and signal chain
VBUS_I_L ≤ (VBUS_I - VSS) ≤ VBUS_I_H, TL ≤ TA ≤ TH, ΔT ≤ 12 °C/min, unless otherwise specified.
#
Characteristic
Symbol
Min
Typ
Max
Units
*
*
*
*
*
SENS025
SENS125
SENS187
SENS250
SENS375
19.456
3.8912
2.5944
1.9456
1.2967
20.480
4.0960
2.7310
2.0480
1.3650
21.504
4.3008
2.8676
2.1504
1.4333
LSB/g
LSB/g
LSB/g
LSB/g
LSB/g
(1)
(1)
(1)
(1)
(1)
*
*
*
*
*
SENS025
SENS125
SENS187
SENS250
SENS375
19.046
3.8092
2.5398
1.9046
1.2694
20.480
4.0960
2.7310
2.0480
1.3650
21.914
4.3828
2.9222
2.1914
1.4606
LSB/g
LSB/g
LSB/g
LSB/g
LSB/g
(1)
(1)
(1)
(1)
(1)
*
OFF10Bit
OFF10Bit
OFF10Bit
OFF10Bit
-100
-100
-52
-52
0
0
0
0
+100
+100
+52
+52
LSB
LSB
LSB
LSB
(1)
(6)
(1)
(6)
Digital offset after offset cancellation (10-bit, all filter options)
OFF10Bit
-1
0
+1
LSB
(6,8,9)
72
73
74
Continuous offset monitor limit
10-bit output, before compensation, ±25 g
10-bit output, before compensation, ±125 g, ±250 g Z-axis
10-bit output, before compensation, ±187 g, ±250 g X-axis, ±375 g
OFFMON
OFFMON
OFFMON
-150
-120
-70
—
—
—
+150
+120
+70
LSB
LSB
LSB
(7,8)
(7,8)
(7,8)
75
76
77
78
Range of output (10-bit mode)
Acceleration (signed)
Acceleration (unsigned)
Error code (signed)
Error code (unsigned)
RANGESigned
RANGEUnsigned
ERRSigned
ERRUnsigned
-511
1
—
—
—
—
-512
0
+511
1023
—
—
LSB
LSB
LSB
LSB
(7,8)
(7,9)
(7,8)
(7,9)
79
80
81
82
Cross-axis sensitivity
Z-axis to X-axis
Y-axis to X-axis
X-axis to Z-axis
Y-axis to Z-axis
VZX
VYX
VXZ
VYZ
-5
-5
-5
-5
—
—
—
—
+5
+5
+5
+5
%
%
%
%
(6)
(6)
(6)
(6)
83
84
System output noise peak (peak value of 100 samples @ 2 kHz)
10-bit mode, LPF = 180 Hz, 2-Pole, All Ranges
10-bit mode, LPF = 400 Hz, 4-Pole, All Ranges
nPeak_180
nPeak_400
-3
-4
—
—
+3
+4
LSB
LSB
(1)
(6)
85
86
System output noise average (average value of 100 samples @ 2 kHz)
10-bit mode, LPF = 180 Hz, 2-pole, all ranges
*
10-bit mode, LPF = 400 Hz, 4-pole, all ranges
*
nRMS_180
nRMS_400
—
—
—
—
+1.0
+1.0
LSB
LSB
(1)
(6)
87
Nonlinearity (10-bit output, all ranges)
NLOUT
-2
—
+2
%
(6)
57
58
59
60
61
Sensitivity (TA = 25°C, 10-bit output @ 100 Hz, referenced to 0Hz: ±5%)
±25 g range
±125 g range
±187 g range
±250 g range
±375 g range
62
63
64
65
66
Sensitivity (TL ≤ TA ≤ TH, VBUS_I_UV_F ≤ VBUS_I ≤ VLOW
10-bit output @ 100 Hz, referenced to 0 Hz: ±7%)
±25 g range
±125 g range
±187 g range
±250 g range
±375 g range
67
68
69
70
Digital offset before offset cancellation (10-bit)
±25 g, ±125 g, ±250 g Z-axis
VBUS_I_UV_F ≤ VBUS_I ≤ VLOW, ±25 g, ±125 g, ±250 g Z-axis
±187 g, ±250 g X-axis, ±375 g
VBUS_I_UV_F ≤ VBUS_I ≤ VLOW, ±187 g, ±250 g X-axis, ±375 g
71
*
MMA27XXW
Sensors
Freescale Semiconductor, Inc.
9
2.5
Electrical characteristics - self-test and overload
VBUS_I_L ≤ (VBUS_I - VSS) ≤ VBUS_I_H, TL ≤ TA ≤ TH, ΔT ≤ 12°C/min, unless otherwise specified.
#
Characteristic
88
89
90
91
92
93
10-bit output during active self-test
±25 g range, X-axis
±125 g range, X-axis
±187 g range, X-axis
±250 g range, X-axis
±375 g range, X-axis
±250 g range, Z-axis
94
Self-test accuracy: Δ from stored value, including sensitivity error
-40°C ≤ TA ≤ 125°C (Section 3.5.2)
*
95
96
97
98
Transducer clipping limit
±25 g, X-axis, positive/negative
±125 g, ±187 g, ±250 g, ±375 g, X-axis, positive/negative
±250 g, Z-axis positive
±250 g, Z-axis negative
99
100
101
102
103
Sinc filter clipping limit
±25 g, X-axis, positive/negative (MMA2702WR2)
±125 g, X-axis, positive/negative (MMA2712WR2)
±187 g, X-axis positive/negative (MMA2718WR2)
±250 g, X-axis positive/negative (MMA2725WR2)
±375 g, X-axis positive/negative (MMA2737WR2)
104
105
±250 g, Z-axis, positive (MMA1725WR2)
±250 g, Z-axis, negative (MMA1725WR2)
*
*
*
*
*
*
Symbol
Min
Typ
Max
Units
gST10_25X
gST10_125X
gST10_187X
gST10_250X
gST10_375X
gST10_250Z
ΔSTMIN
124
236
156
117
77
80
ΔSTNOM
—
—
—
—
—
—
ΔSTMAX
208
395
263
198
131
160
LSB
LSB
LSB
LSB
LSB
LSB
(1)
(1)
(1)
(1)
(1)
(1)
ΔSTACC
-10
—
+10
%
(1,5)
gg-cell_ClipLowX
gg-cell_ClipHiX
gg-cell_ClipHiZP
gg-cell_ClipHiZN
400
1700
2200
-3700
470
2100
2700
-3200
500
2300
3300
-2700
g
g
g
g
(9)
(9)
(9)
(9)
gADC_Clip_25X_H
gADC_Clip_125X_H
gADC_Clip_187X_H
gADC_Clip_250X_H
gADC_Clip_375X_H
190
920
1600
1600
1600
210
1100
1900
1900
1900
240
1300
2200
2200
2200
g
g
g
g
g
(9)
(9)
(9)
(9)
(9)
gADC_Clip_250ZPH
gADC_Clip_250ZNH
1500
-3200
2000
-2900
2500
-2500
g
g
(9)
(9)
MMA27XXW
10
Sensors
Freescale Semiconductor, Inc.
2.6
Dynamic electrical characteristics - DSI3
VBUS_I_L ≤ (VBUS_I - VSS) ≤ VBUS_I_H, TL ≤ TA ≤ TH, ΔT ≤ 12°C/min, unless otherwise specified.
#
Characteristic
Reset recovery (all modes, excluding VBUS_I voltage ramp time)
106 POR to 1st command (Section 3.6)
107 POR to acceleration data ready (Section 3.6)
Symbol
Min
Typ
Max
Units
tDSI_POR
tDSP_POR
—
—
5
tDSI_POR
—
—
ms
s
(7,8)
(7,8)
108
109
110
111
Command reception (general)
VHIGH low-pass filter time constant (Section 3.6.1)
VHIGH detection analog delay (Section 3.6.1)
iq low-pass filter time constant (Section 3.6.3)
Command valid time (Section 3.6.1)
tVHIGH_RC
tVHIGH_Delay
tIQ_RC
tCmd_Valid
60
—
200
—
120
—
400
2
180
600
600
—
μs
ns
μs
μs
(8,9)
(8,9)
(8,9)
(7,9)
112
113
114
115
116
Response transmission (general, Section 4.2.3)
Response slew time: 2.0 mA to 10.0 mA, 10.0 mA to 2.0 mA
Response slew time: 4.0 mA to 20.0 mA, 20.0 mA to 4.0 mA
tSLEW1_RESP- tSLEW2_RESP
tSLEW1_RESP_Rise- tSLEW2_RESP_Fall
Response current activation time: current activated to 50%
tSLEW1_RESP
tSLEW2_RESP
ΔtSLEW
ΔtSLEW_rf
tACT_RESP
200
200
-100
-250
200
400
400
—
—
—
600
600
100
250
400
ns
ns
ns
ns
ns
(6,8)
(6,8)
(8,9)
(8,9)
(8,9)
tSTART_DISC
tDISC_BitTime
tPER_DISC
tCmdBlock_DISC
tDisc_Dly
tDisc_Iccqsamp
tIDiscsamp_Dly
tIDiscsamp
tDSI_POR
—
1000/fOSC
—
—
—
—
—
—
16
—
96
48
15
65
31
12
—
—
—
—
—
—
—
ms
μs
s
μs
μs
μs
μs
μs
(7,8)
(7,8)
(7,8)
(7,8)
(7,9)
(7,9)
(7,9)
(7,9)
tSTART_DISC_RSP
tDISC_Ramp_RSP
IDISC_Ramp
tDISC_Idle_RSP
IDISC_Peak
—
—
—
—
—
64
16
1.5
16
2*IRESP
—
—
—
—
—
μs
μs
mA/μs
μs
mA
(7,8)
(7,8)
(6,8)
(7,8)
(6,8)
tCmd_BitTime
tPER_CRM
tCmdBlock_CRM
tCmdBlock_ST_CRM
—
tPER_PDCM
—
—
8
—
456
268
—
8 x tPER_PDCM
—
—
μs
s
μs
μs
(7,8)
(7,8)
(7,8)
(7,8)
tCHIP_CRM
tSTART_CRM
—
—
5
295
—
—
μs
μs
(7,8)
(7,8)
tCmd_BitTime
tPER_PDCM
—
100
—
1
—
—
—
8
—
5
—
1
20
44
—
5000
—
4095
—
—
—
μs
μs
μs
μs
μs
μs
μs
(7,8)
(7,8)
(7,8)
(7,8)
(7,8)
(7,8)
(7,8)
tSTART_PDCM_BDM
tST_RES_PDCM
3
—
20
44
—
—
0.5
—
—
1
6.5
—
4095
4095
—
μs
μs
μs
μs
μs
(7,8)
(7,8)
(7,8)
(7,8)
(7,8)
tSTART_BDM
—
20
—
μs
(7,8)
117
118
119
120
121
122
123
124
Command reception (Discovery Mode)
Command start time (Section 4.1)
Command bit time (Section 4.1)
Command transmission period (Section 4.1)
Command blocking time, Discovery Mode (Section 3.6.1)
ICCQ sample delay time (Section 3.6.3)
ICCQ sample time (Section 3.6.3)
IDISC sample delay time (Section 3.6.3)
IDISC sample time (Section 3.6.3)
125
126
127
128
129
Response transmission (Discovery Mode)
Response start delay (Section 4.1)
Response ramp time (Section 4.1)
Response ramp rate (Section 4.1)
Response idle time (Section 4.1)
Response peak current (Section 4.1)
130
131
132
133
Command reception (Command and Response Mode)
Command bit time (Section 4.2)
Command transmission period (Section 4.2)
Command blocking time, CRM (Section 3.6.1)
Command blocking start time, CRM (Section 3.6.1)
134
135
Response transmission (Command and Response Mode)
Response chip time
Response start time (Section 4.2)
136
137
138
139
140
141
142
Command reception (Periodic Data Collection Mode)
Command bit time (Section 4.3)
Command transmission period (Section 4.3)
Command transmission period resolution
Command blocking time, PDCM (Section 4.3.2)
Command blocking time resolution, PDCM (Section 4.3.2)
Command blocking start time, PDCM (Section 4.3.2)
Command blocking start time, BDM command
143
144
145
146
147
Response transmission (Periodic Data Collection Mode)
Response chip time typical (Section 3.1.15.3)
Response chip resolution (Section 3.1.15.3)
Response start time typical (Section 4.3)
Response start time typical, BDM enabled (Section 4.3)
Response start time resolution
tPER_PDCM_Res
tCmdBlock_PDCM
tCmdBlockRes_PDCM
tCmdBlock_ST_PDCM
tCmdBlock_ST_BDM
tCHIP_PDCM
tCHIPRes_PDCM
tSTART_PDCM
Response transmission (Background Diagnostic Mode)
148 Response start time (Section 4.3)
149 Register write to BUSSW active
150 DSI data latency
OTP program timing
151 Time to program the user OTP array
tBS
—
456
—
μs
(7,8)
tLAT_DSI
—
0.5
6.25
μs
(7,9)
tNVM_WRITE_MAX
—
—
60
ms
(7,8)
MMA27XXW
Sensors
Freescale Semiconductor, Inc.
11
2.7
Dynamic electrical characteristics - signal chain
VBUS_I_L ≤ (VBUS_I - VSS) ≤ VBUS_I_H, TL ≤ TA ≤ TH, ΔT ≤ 12 °C/min, unless otherwise specified.
Table 3.
#
Characteristic
Symbol
Min
Typ
Max
Units
fC_LPF0
fC_LPF6
fC_LPF8
fC_LPF9
fC_LPF11
fC_LPF14
—
—
—
—
—
—
180
325
400
400
800
1200
—
—
—
—
—
—
Hz
Hz
Hz
Hz
Hz
Hz
(6,7)
(6,7)
(7,8)
(7,8)
(7,8)
(7,8)
tOC_SampleRate
fC_OCPH1
tOCPH1
fC_OCPH2
tOCPH2
tOffRate
OFFStep
OFFMONOSC
OFFMONCNTLIMIT
OFFMONCNTSIZE
—
—
—
—
—
—
—
—
—
—
256
10.0
80
1.0
70
2
0.5
500
4096
8192
—
—
—
—
—
—
—
—
—
—
μs
Hz
ms
Hz
ms
s
LSB
μs
1
1
(7,9)
(7,9)
(7,9)
(7,9)
(7,9)
(7,9)
(7,9)
(7,8)
(7,8)
(7,8)
169 Signal delay excluding LPF group delay and interpolation
tSIG_DELAY
—
—
100
μs
(7,9)
170 Interpolation latency
tLAT_INTERP
—
16
—
μs
(7,9)
tST_ACT_180
tST_DEACT_180
tST_ACT_325
tST_DEACT_325
tST_ACT_400
tST_DEACT_400
tST_ACT_800
tST_DEACT_800
tST_ACT_800
tST_DEACT_800
2.00
2.00
1.30
1.30
1.00
1.00
0.50
0.50
0.40
0.40
—
—
—
—
—
—
—
—
—
—
4.00
4.00
2.70
2.70
2.50
2.50
1.75
1.75
1.50
1.50
ms
ms
ms
ms
ms
ms
ms
ms
ms
ms
(3,6)
(3,6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
152
153
154
155
156
157
158
DSP low-pass filter
Cutoff frequency LPF0, 2-pole (referenced to 0 Hz)
Cutoff frequency LPF6, 3-pole (referenced to 0 Hz)
Cutoff frequency LPF8, 3-pole (referenced to 0 Hz)
Cutoff frequency LPF9, 4-pole (referenced to 0 Hz)
Cutoff frequency LPF11, 4-pole (referenced to 0 Hz)
Cutoff frequency LPF14, 4-pole (referenced to 0 Hz)
159
160
161
162
163
164
165
166
167
168
DSP offset cancellation low-pass filter
Offset Cancellation low-pass filter Input sample Rate
Cutoff frequency, startup Phase 1, 1-pole
Startup Phase 1 time
Cutoff frequency, startup Phase 2, 1-pole
Startup Phase 2 time
Offset cancellation output update rate (10-bit)
Offset cancellation output step size (10-bit)
Offset monitor update rate
Offset monitor count limit
Offset monitor counter size
171
172
173
174
175
176
177
178
179
180
Self-test response time (CS Rising to 90% gST10_xxx)
Self-test activation time (180 Hz LPF)
Self-test deactivation time (180 Hz LPF)
Self-test activation time (325 Hz LPF, 3 Pole)
Self-test deactivation time (325 Hz LPF, 3 Pole)
Self-test activation time (400 Hz LPF, 3 or 4 Pole)
Self-test deactivation time (400 Hz LPF, 3 or 4 Pole)
Self-test activation time (800 Hz LPF)
Self-test deactivation time (800 Hz LPF)
Self-test activation time (1200 Hz LPF)
Self-test deactivation time (1200 Hz LPF)
*
*
*
*
*
*
181
182
183
Sensing element rolloff frequency (-3 db)
±25 g, X-axis
±125 g, ±187 g, ±250 g, ±375 g, X-axis
±250 g, Z-axis
fgcell_3dB_xlo
fgcell_3dB_xhi
fgcell_3dB_zhi
938
3952
3100
1600
7200
4500
2592
14370
6500
Hz
Hz
Hz
(6)
(6)
(6)
184
185
186
Sensing element natural frequency
±25 g, X-axis
±125 g, ±187 g, ±250 g, ±375 g, X-axis
±250 g, Z-axis
fgcell_xlo
fgcell_xhi
fgcell_zhi
12651
26000
15000
13200
27500
17000
13871
28700
17500
Hz
Hz
Hz
(9)
(9)
(9)
187
188
189
Sensing element damping ratio
±25 g, X-axis
±125 g, ±187 g, ±250 g, ±375 g, X-axis
±250 g, Z-axis
ζgcell_xlo
ζgcell_xhi
ζgcell_zhi
2.76
1.26
1.40
4.20
2.00
2.00
6.77
3.60
2.90
fgcell_delay100_xlo
fgcell_delay100_xhi
fgcell_delay100_zhi
63
13
35
100
24
40
170
40
55
μs
ms
μs
(9)
(9)
(9)
fPackage
100
—
—
kHz
(9)
Sensing element delay (@100 Hz)
±25 g, X-axis
190
±125 g, ±187 g, ±250 g, ±375 g, X-axis
191
192
±250 g, Z-axis
193 Package resonance frequency
(9)
(9)
(9)
MMA27XXW
12
Sensors
Freescale Semiconductor, Inc.
2.8
Dynamic electrical characteristics - supply and support circuitry
VBUS_I_L ≤ (VBUS_I - VSS) ≤ VBUS_I_H, TL ≤ TA ≤ TH, ΔT ≤ 12 °C/min, unless otherwise specified
#
Characteristic
Symbol
Min
Typ
Max
Units
fOSC
fOSC
7.600
7.879
8.000
8.000
8.400
8.121
MHz
MHz
(1)
(7,8,9)
194
195
Internal oscillator period
Untrained
With oscillator training
196
197
198
199
Oscillator training (Section 3.4.1)
Oscillator training time (CRM and PDCM)
Oscillator training window (CRM and PDCM)
Oscillator training adjustment threshold (CRM and PDCM)
Oscillator training step size (CRM and PDCM)
tOscTrain
OscTrainWIN
OscTrainADJ
OscTrainRES
—
3.4
-60
—
4
—
—
28
—
4.6
60
—
ms
ms
μs
μs
(7)
(7)
(7)
(7)
200 Quiescent current settling time (power applied to Iq = IIDLE ±2 mA)
tSET
—
—
4
ms
(6)
tBUS_I_MICROCUT
tBUS_I_RESET
30
—
—
—
—
1000
μs
μs
(8)
(8)
tBUS_I_POR
—
—
5
μs
(6)
tVBUF_POR
—
—
5
μs
(6)
tVREG_POR
—
—
50
μs
(6)
tPOR_CAPTEST
tCAPTST_TIME
—
—
950
1.5
—
—
μs
μs
(7,8)
(7,8)
201
202
*
BUS_I microcut
Survival time (BUS_I disconnect without reset, CBUF=CREG=CREGA=700nF)
Reset time (BUS_I disconnect time to reset, CBUF=CREG=CREGA=1μF)
BUS_I undervoltage detection delay
203 BUS_I < VBUS_I_UV_F to IRESP deactivation
VBUF undervoltage detection delay
204 VBUF < VBUF_UV_F to IRESP deactivation
VREG, VREGA undervoltage reset delay
205 VREG < VREG_UV_F to POR assertion, VREGA < VREGA_UV_F to POR assertion
206
207
VBUF, VREG, VREGA capacitor monitor
POR to capacitor disconnect
Disconnect time
NOTES
1.
2.
3.
4.
5.
6.
7.
Parameter tested 100% at final test. Temperature = -40°C, 25°C and 105°C, VBUS_I = 8 V, Unless otherwise stated.
Not Applicable.
Parameter verified by pass/fail testing at final test
Parameter verified by pass/fail testing at final test during safe launch.
Parameter verified by qualification testing.
Parameter verified by characterization.
Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and
scan testing. Timing is determined by internal system clock frequency.
8. Parameter verified by functional evaluation.
9. Parameter verified by simulation.
10. Not Applicable.
11. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
*
Indicates critical characteristic.
MMA27XXW
Sensors
Freescale Semiconductor, Inc.
13
3
Functional Description
3.1
User-accessible data array
A user-accessible data array allows for each device to be customized. The array consists of an OTP factory-programmable block,
an OTP user-programmable block, and read-only registers for data and device status. The OTP blocks incorporate independent
data verification (reference Section 3.2). Portions of the factory-programmable array are reserved for factory-programmed trim
values.
Table 4. User-accessible data
Bit Function
Bit Function
Byte
Addr
Register
$00
ICTYPEID
0
0
0
0
0
$01
ICMFGID
0
0
0
0
0
7
6
5
4
3
2
Type
1
0
0
0
1
R
0
1
0
R
$02
ICREVID
0
0
1
ICREVID[4]
0
0
0
0
R
$03
MODTYPE
0
0
0
0
0
MODTYPE[2]
MODTYPE[1]
MODTYPE[0]
U,R
$04
MODMFGID
0
0
0
0
0
MODMFGID[2]
MODMFGID[1]
MODMFGID[0]
U,R
$05
MODREV
0
0
0
0
0
MODREV[2]
MODREV[1]
MODREV[0]
U,R
$06
USERID1
USERID1[7]
USERID1[6]
USERID1[5]
USERID1[4]
USERID1[3]
USERID1[2]
USERID1[1]
USERID1[0]
U,R
$07 $08
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
$09
PN
PN[7]
PN[6]
PN[5]
PN[4]
PN[3]
PN[2]
PN[1]
PN[0]
F,R
$0A
SN0
SN[7]
SN[6]
SN[5]
SN[4]
SN[3]
SN[2]
SN[1]
SN[0]
F,R
$0B
SN1
SN[15]
SN[14]
SN[13]
SN[12]
SN[11]
SN[10]
SN[9]
SN[8]
F,R
$0C
SN2
SN[23]
SN[22]
SN[21]
SN[20]
SN[19]
SN[18]
SN[17]
SN[16]
F,R
$0D
SN3
SN[31]
SN[30]
SN[29]
SN[28]
SN[27]
SN[26]
SN[25]
SN[24]
F,R
$0E $0F
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
$10
DSIREV
0
0
0
0
0
0
0
1
R
$11
PHYSADDR
0
0
0
0
PADDR[3]
PADDR[2]
PADDR[1]
PADDR[0]
U,R/
W
$12
BDM_CFG
0
0
0
0
0
0
0
BDM_EN
R/W
$13
CRM_CFG
0
0
0
CK_CAL_RST
CRM_PER[1]
CRM_PER[0]
CK_CAL_EN
SS_EN
R/W
$14
PDCM_CFG
0
0
0
0
0
0
DATALENGTH
STATLENGTH
R/W
$15
PDCM_EN
PDCM_EN
0
0
0
0
0
0
0
R/W
$16
CHIPTIME
0
0
0
0
0
CHIPTIME[2]
CHIPTIME[1]
CHIPTIME[0]
R/W
$17
PDCM_PER
0
0
0
0
0
PDCM_PER[2]
PDCM_PER[1]
PDCM_PER[0]
R/W
$18
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R/W
$19
PDCM_RSPST_L
PDCM_RSPST[7]
PDCM_RSPST[6]
PDCM_RSPST[5]
PDCM_RSPST[4]
PDCM_RSPST[3]
PDCM_RSPST[2]
PDCM_RSPST[1]
PDCM_RSPST[0]
R/W
R/W
$1A
PDCM_RSPST_H
0
0
0
0
PDCM_RSPST[11]
PDCM_RSPST[10]
PDCM_RSPST[9]
PDCM_RSPST[8]
$1B
PDCM_CMD_B_L
PDCM_CMD_B[7]
PDCM_CMD_B[6]
PDCM_CMD_B[5]
PDCM_CMD_B[4]
PDCM_CMD_B[3]
PDCM_CMD_B[2]
PDCM_CMD_B[1]
PDCM_CMD_B[0]
R/W
$1C
PDCM_CMD_B_H
0
0
0
0
PDCM_CMD_B[11]
PDCM_CMD_B[10]
PDCM_CMD_B[9]
PDCM_CMD_B[8]
R/W
$1D
SOURCEID
0
0
0
0
SOURCEID[3]
SOURCEID[2]
SOURCEID[1]
SOURCEID[0]
R/W
$1E
BUSSW_CTRL
0
0
0
0
0
0
0
BUSSW_CTRL
R/W
$1F
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
$20
DEVLOCK
LOCK_U
0
0
0
0
0
0
0
U,R
$21
DEVSTAT
RESERVED
DEVRES
OSCTRAIN_ERR
BUSSW
TESTMODE
ST_ACTIVE
OFFSET_ERR
OC_INIT
R
$22
DEVSTAT2
F_OTP_ERR
U_OTP_ERR
U_RW_ERR
U_UNLOCKED
RESERVED
ST_INCMPLT
VBUF_UV_ERR
BUSI_UV_ERR
R
$23
ST_CONTROL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
ST_5_PTRN
ST_A_PTRN
SELFTEST
R/W
$24
WRITE_NVM_EN
0
0
0
0
0
0
WR_NVM_EN[1]
WR_NVM_EN[0]
R/W
$25
C_CRMCRCPLY
C_CRMCRCPLY[7]
C_CRMCRCPLY[6]
C_CRMCRCPLY[5]
C_CRMCRCPLY[4]
C_CRMCRCPLY[3]
C_CRMCRCPLY[2]
C_CRMCRCPLY[1]
C_CRMCRCPLY[0]
R/W
$26
R_CRMCRCPLY
R_CRMCRCPLY[7]
R_CRMCRCPLY[6]
R_CRMCRCPLY[5]
R_CRMCRCPLY[4]
R_CRMCRCPLY[3]
R_CRMCRCPLY[2]
R_CRMCRCPLY[1]
R_CRMCRCPLY[0]
R/W
$27
PDCMCRCPLY
PDCMCRCPLY[7]
PDCMCRCPLY[6]
PDCMCRCPLY[5]
PDCMCRCPLY[4]
PDCMCRCPLY[3]
PDCMCRCPLY[2]
PDCMCRCPLY[1]
PDCMCRCPLY[0]
R/W
$28 $2F
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
R
$30
ACC_FCTCFG
0
PCM
AXIS
RNG[4]
RNG[3]
RNG[2]
RNG[1]
RNG[0]
F,R
$31
ACC_STDATA
ACC_ST[7]
ACC_ST[6]
ACC_ST[5]
ACC_ST[4]
ACC_ST[3]
ACC_ST[2]
ACC_ST[1]
ACC_ST[0]
F,R
$32
ACC_CFG
LPF[3]
LPF[2]
LPF[1]
LPF[0]
SD
OC_FILT[2]
OC_FILT[1]
OC_FILT[0]
R/W
$33
ACC_DATAL
ACC_D[7]
ACC_D[6]
ACC_D[5]
ACC_D[4]
ACC_D[3]
ACC_D[2]
ACC_D[1]
ACC_D[0]
R
$34
ACC_DATAH
ACC_D[15]
ACC_D[14]
ACC_D[13]
ACC_D[12]
ACC_D[11]
ACC_D[10]
ACC_D[9]
ACC_D[8]
R
$35
ACC_STAT
0
0
0
0
0
ST_ACTIVE
OFFSET_ERR
OC_INIT
R
Type codes:
F: Freescale programmed OTP location.
U: User programmable OTP location.
R: Readable register.
R/W: User writable register.
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3.1.1
IC Type register
The IC Type register is a read-only register which contains the IC type as defined in the DSI3 standard.
Table 5. IC Type register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$00
ICTYPEID
0
0
0
0
0
0
0
1
3.1.2
IC Manufacturer Identification register
The IC Manufacturer Identification register is a read-only register which contains the IC manufacturer ID as defined in the DSI3
standard.
Table 6. IC Manufacturer Identification register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$01
ICMFGID
0
0
0
0
0
0
1
0
3.1.3
IC Manufacturer Revision register
The IC revision register is a read-only register which contains the IC revision as defined in the DSI3 standard. ICREVID[4] is set
to ‘0’ for the MMAx7xxJWR2 part numbers and set to ‘1’ for the MMAx7xxWR2 part numbers.
Table 7. IC Manufacturer Revision register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$02
ICREVID
0
0
1
ICREVID[4]
0
0
0
0
3.1.4
Module Type register (MODTYPE)
The module type register is a user programmed OTP register which contains user specific module identification information as
defined in the DSI3 Standard. The register is included in the user programmed OTP verification described in Section 3.2.
Table 8. Module Type register
Location
Bit
Address
Register
7
6
5
4
3
$03
MODTYPE
0
0
0
0
0
0
0
0
0
0
Factory Default
3.1.5
2
1
0
MODTYPE[2] MODTYPE[1] MODTYPE[0]
0
0
0
Module Manufacturer ID register (MODMFGID)
The module manufacturer identification register is a user-programmed OTP register which contains user specific module
identification information as defined in the DSI3 Standard. The register is included in the user programmed OTP verification
described in Section 3.2.
Table 9. Module Manufacturer ID register
Location
Bit
Address
Register
7
6
5
4
3
$04
MODMFGID
0
0
0
0
0
0
0
0
0
0
Factory Default
2
1
0
MODMFGID[2] MODMFGID[1] MODMFGID[0]
0
0
0
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3.1.6
Module Revision register (MODREV)
The Module Revision register is a user programmed OTP register which contains user specific module identification information
as defined in the DSI3 Standard. The register is included in the user programmed OTP verification described in Section 3.2.
Table 10. Module Revision register (MODREV)
Location
Bit
Address
Register
7
6
5
4
3
$05
MODREV
0
0
0
0
0
0
0
0
0
0
Factory Default
3.1.7
2
1
0
MODREV[2] MODREV[1] MODREV[0]
0
0
0
User ID 1 registers (USERID1)
User ID registers 1 is a user programmable OTP register which contains user specific information. The bits have no impact on
the device performance. The register is included in the user programmed OTP verification described in Section 3.2.
Table 11. User ID 1 registers
Location
Bit
Address
Register
$06
USERID1
7
Factory Default
3.1.8
6
5
4
3
2
1
0
USERID1[7] USERID1[6] USERID1[5] USERID1[4] USERID1[3] USERID1[2] USERID1[1] USERID1[0]
0
0
0
0
0
0
0
0
Part Number register
The Part Number register is a factory-programmed OTP register which includes the numeric portion of the device part number.
The register is included in the factory-programmed OTP verification described in Section 3.2. Beyond this, the contents of the
part number register have no impact on device operation or performance.
Table 12. Part Number register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$09
PN
PN[7]
PN[6]
PN[5]
PN[4]
PN[3]
PN[2]
PN[1]
PN[0]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Factory Default
PN Register Value
HEX
Range
(g)
Transducer
Decimal
2
0x02
25
Medium-g Lateral
12
0x0C
125
High-g Lateral
18
0x12
187
High g Lateral
25
0x19
250
High-g Lateral / High-g Vertical
37
0x25
375
High-g Lateral
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3.1.9
Device Serial Number registers
The serial number registers are factory-programmed OTP registers which include a unique serial number and lot number
combination for each device, regardless of range or axis of sensitivity. Serial numbers begin at 1 for all produced devices in each
lot and are sequentially assigned. Lot numbers begin at 1 and are sequentially assigned. No lot will contain more devices than
can be uniquely identified by the 13-bit serial number. Depending on lot size and quantities, all possible lot numbers and serial
numbers may not be assigned. The serial number registers are included in the factory-programmed OTP verification described
in Section 3.2. Beyond this, the contents of the serial number registers have no impact on device operation or performance.
Table 13. Device Serial Number registers
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$0A
SN0
SN[7]
SN[6]
SN[5]
SN[4]
SN[3]
SN[2]
SN[1]
SN[0]
$0B
SN1
SN[15]
SN[14]
SN[13]
SN[12]
SN[11]
SN[10]
SN[9]
SN[8]
$0C
SN2
SN[23]
SN[22]
SN[21]
SN[20]
SN[19]
SN[18]
SN[17]
SN[16]
$0D
SN3
SN[31]
SN[30]
SN[29]
SN[28]
SN[27]
SN[26]
SN[25]
SN[24]
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Factory Default
The serial number is composed of the following information:
3.1.10
Bit range
Content
SN[12:0]
Serial Number
SN[31:13]
Lot Number
DSI Protocol Revision register (DSI_REV)
The factory-configuration register is a read-only register which contains the DSI revision supported, as specified in the DSI3
standard. The protocol revision value for DSI3 is $01.
Table 14. DSI Protocol Revision register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$10
DSIREV
0
0
0
0
0
0
0
1
3.1.11
Physical Address register (PHYSADDR)
The physical address register is a user programmed OTP register which contains the physical address of the slave.
If the physical address is zero, the address is assigned either during Discovery Mode as described in Section 4.1.3 or during
Command and Response Mode as described in Section 4.1.2.
If the physical address is non-zero, the device ignores Discovery Mode and uses the programmed physical address for Command
and Response Mode, as described in Section 4.2. The physical address register value can be changed by a Command and
Response Mode register write command. However, if the LOCK_U bit is set, the value will always be reset to the OTP array value
after a reset.
The OTP register value is included in the user programmed OTP verification described in Section 3.2. The value is also stored
in a secondary register that can be written as described above. This secondary register is included in the read/write array
verification described in Section 3.2.
Table 15. Physical Address register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$11
PHYSADDR
0
0
0
0
PADDR[3]
PADDR[2]
PADDR[1]
PADDR[0]
0
0
0
0
0
0
0
0
Factory Default
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3.1.12
DSI3 Background Diagnostic Mode Configuration register (BDM_CFG)
The DSI3 Background Diagnostic Mode configuration register is a user programmed read/write register which contains user
specific configuration information for DSI3 Background Diagnostic Mode. The register is included in the read/write array
verification described in Section 3.2. Reference Section 4.3 for details regarding Background Diagnostic Mode.
Table 16. DSI3 Background Diagnostic Mode Configuration register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$12
BDM_CFG
0
0
0
0
0
0
0
BDM_EN
0
0
0
0
0
0
0
0
Factory Default
3.1.12.1
Background Diagnostic Mode Enable (BDM_EN)
The Background Diagnostic Mode enable bit enables Background Diagnostic Mode as described below and in Section 3.1.14.
Reference Section 4.3 for details regarding Background Diagnostic Mode.
3.1.13
BDM_EN
BDM command fragment length
0
Disabled
1
4
DSI3 Command and Response Mode Configuration register (CRM_CFG)
The DSI3 Command and Response Mode configuration register is a user programmed read/write register which contains user
specific configuration information for DSI3 Command and Response Mode. The register is included in the read/write array
verification described in Section 3.2.
Table 17. DSI3 Command and Response Mode Configuration register
Location
Bit
Address
Register
7
6
5
$13
CRM_CFG
0
0
0
0
0
0
Factory Default
3.1.13.1
4
3
2
1
CK_CAL_RST CRM_PER[1] CRM_PER[0] CK_CAL_EN
0
0
0
0
0
SS_EN
0
Clock Calibration Value Reset (CK_CAL_RST)
The clock calibration reset bit controls the state of the oscillator training when the CK_CAL_EN bit is cleared as described in the
table in Section 3.1.13.3. Reference Section 3.4.1 for details regarding oscillator training.
3.1.13.2
Command and Response Mode Period (CRM_PER[1:0])
The Command and Response Mode Period bits set the period for Command and Response Mode commands in increments of
the Periodic Data Collection Mode Period (PDCM_PER). This value is only necessary for oscillator training and is only used if
the CK_CAL_EN bit is set in the CRM_CFG register. Command and Response Mode commands will be decoded and responded
to regardless of the value of this register as long as the general Command and Response Mode timing parameters specified in
Section 2.6 are met. Reference Section 3.4.1 for details regarding oscillator training.
CRM_PER[1]
CRM_PER[0]
Command and Response Mode period
(Multiples of the Periodic Data Collection Mode period)
0
0
1
0
1
2
1
0
4
1
1
8
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3.1.13.3
Clock Calibration Enable (CK_CAL_EN)
The clock calibration enable bit enables oscillator training over the DSI communication interface. Reference Section 3.4.1 for
details regarding oscillator training.
CK_CAL_EN
CK_CAL_RST
0
0
The oscillator value is maintained at the last trained value prior to clearing the CK_CAL_RST bit.
0
1
The oscillator value is reset to the untrained value with a tolerance specified in Section 2.8.
1
x
Oscillator is trained as specified in Section 3.4.1
3.1.13.4
Oscillator training
Simultaneous Sampling Enable (SS_EN)
The simultaneous sampling enable bit selects between one of two data latency methods. Reference Section 3.7 for details
regarding sample timing.
SS_EN
Data latency
0
Synchronous Sampling Mode: Latency relative to transmission start time (PDCM_RSPST)
1
Simultaneous Sampling Mode: Latency relative to the start of the Periodic Data Collection Mode command (falling edge)
3.1.14
Periodic Data Collection Mode Enable register (PDCM_EN)
The Periodic Data Collection Mode register is a read/write register which contains the Periodic Data Collection Mode Enable bit.
The register is included in the read/write array verification described in Section 3.2.
Table 18. Periodic Data Collection Mode Enable register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$15
PDCM_EN
PDCM_EN
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Factory Default
The Periodic Data Collection Mode Enable bit enables Periodic Data Collection Mode as described in Section 4.3. The
PDCM_EN bit can be set by receiving the Enter PDCM command in Command and Response Mode, or by a Command and
Response Mode register write command. Once Periodic Data Collection Mode is enabled, the registers listed in Section 3.2.3
are locked and the user array read/write register array verification is enabled.
Once set, the PDCM_EN bit can only be cleared by a device reset.
PDCM_EN
BDM_EN
Command and Response Mode
Periodic Data Collection Mode
Background Diagnostic Mode
0
0
Enabled
Disabled
Disabled
0
1
Enabled
Disabled
Disabled
1
0
Disabled
Enabled
Disabled
1
1
Disabled
Enabled
Enabled
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3.1.15
DSI3 Periodic Data Collection Mode Configuration registers (PDCM_CFG1, PDCM_CFG2)
The DSI3 Periodic Data Collection Mode configuration registers are user programmed read/write registers which contain user
specific configuration information for DSI3 Periodic Data Collection Mode. The registers are included in the read/write array
verification described in Section 3.2.
Location
Bit
Addres
s
Register
$14
PDCM_CFG
0
0
0
0
$16
CHIPTIME
0
0
0
0
$17
PDCM_PER
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
DATALENGTH
STATLENGTH
0
CHIPTIME[2]
CHIPTIME[1]
CHIPTIME[0]
PDCM_PER[2]
PDCM_PER[1]
PDCM_PER[0]
$18
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
$19
PDCM_RSPST_L
PDCM_RSPST[7]
PDCM_RSPST[6]
PDCM_RSPST[5]
PDCM_RSPST[4]
PDCM_RSPST[3]
PDCM_RSPST[2]
PDCM_RSPST[1]
PDCM_RSPST[0]
$1A
PDCM_RSPST_H
0
0
0
0
PDCM_RSPST[11]
PDCM_RSPST[10]
PDCM_RSPST[9]
PDCM_RSPST[8]
$1B
PDCM_CMD_B_L
PDCM_CMD_B[7]
PDCM_CMD_B[6]
PDCM_CMD_B[5]
PDCM_CMD_B[4]
PDCM_CMD_B[3]
PDCM_CMD_B[2]
PDCM_CMD_B[1]
PDCM_CMD_B[0]
$1C
PDCM_CMD_B_H
Factory Default
3.1.15.1
0
0
0
0
PDCM_CMD_B[11]
PDCM_CMD_B[10]
PDCM_CMD_B[9]
PDCM_CMD_B[8]
0
0
0
0
0
0
0
0
Data Field Length (DATALENGTH)
The data field length bits set the data field length in the Periodic Data Collection Mode response as described below. The
sensitivity of the data is the same for both the 10-bit and 14-bit data lengths. If the 14-bit data length is selected, four additional
bits of range are transmitted. These additional four bits of range are intended for test use only and are not covered by the
specifications listed in Section 2.
3.1.15.2
DATALENGTH
Data Length
0
10 Bits
1
14 Bits
Status Field Length (STATLENGTH)
The status field length bits set the status field length in the Periodic Data Collection Mode response as described below.
Reference Section 4.3.2.2 for details regarding the Periodic Data Collection Mode status field.
Status Field Length
(Bits)
Data Transmitted
0
4
Reference Section 4.3.2.2
1
0
N/A
STATLEN
3.1.15.3
Chip time (CHIPTIME)
The DSI3 Periodic Data Collection Mode configuration chip time bits set the chip time for Periodic Data Collection Mode as
described below.
CHIPTIME[2]
CHIPTIME[1]
CHIPTIME[0]
Chip time
0
0
0
3.0 μs
0
0
1
3.5 μs
0
1
0
4.0 μs
0
1
1
4.5 μs
1
0
0
5.0 μs
1
0
1
5.5 μs
1
1
0
6.0 μs
1
1
1
6.5 μs
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3.1.15.4
Periodic Data Collection Mode Period (PDCM_PER[3:0])
The Periodic Data Collection Mode period selection bits set the period data collection mode period to be used by the DSI master
as shown in the table below. This value is only necessary for oscillator training and is only used if the CK_CAL_EN bit is set in
the CRM_CFG register. Periodic Data Collection Mode and Background Diagnostic Mode commands will be decoded and
responded to regardless of the value of this register as long as the general Periodic Data Collection Mode timing parameters
specified in Section 2.6 are met. Reference Section 3.4.1 for details regarding oscillator training.
3.1.15.5
PDCM_PER[2]
PDCM_PER[1]
PDCM_PER[0]
Periodic Data Collection Mode Period
0
0
0
500 μs
0
0
1
125 μs
0
1
0
250 μs
0
1
1
333 μs
1
0
0
500 μs
1
0
1
1000 μs
1
1
0
2000 μs
1
1
1
4000 μs
Periodic Data Collection Mode Response Start Time (PDCM_RSPST[11:0])
The DSI3 Periodic Data Collection Mode Response Start Time bits set the Periodic Data Collection Mode response start time.
The value is stored in 1 μs increments, with zero as the default value of 20 μs.
Care must be taken to prevent from programming response start times which cause data contention in the system.
PDCM_RSPST[11:0]
3.1.15.6
Periodic Data Collection Mode Response Start Time
0 - 20
20 μs
21 - 4095
PDCM response start = PDCM_RSPST x 1μs
Periodic Data Collection Mode Command Blocking time (PDCM_CMD_B[11:0])
The DSI3 Periodic Data Collection Mode command blocking time bits set the Periodic Data Collection Mode command blocking
time. in 1μs increments, with zero as the default value of 450 μs. Reference Section 3.6.1 for details regarding the command
receiver and command blocking.
Care must be taken to prevent from programming command blocking times which prevent proper command decoding in the
system and to ensure proper sampling of the VHIGH voltage. As shown in Section 3.6.1, Figure 29, The VHIGH voltage is initially
captured at the end of the command blocking time and then filtered. The user must ensure that the command blocking end time
is set for a time when no command or response transmissions are occurring to provide the most stable BUS_I voltage.
3.1.16
PDCM_CMD_B[11:0]
Periodic Data Collection Mode Command blocking time
0
450 μs
Non-Zero
PDCM Command blocking time = PDCM_CMD_B x 1 μs
Source Identification register (SOURCEID)
The source identification register is a user programmed read/write register which contains the source identification which will be
used for Periodic Data Collection Mode as described in Section 4.3.2.2. The register is included in the read/write array verification
described in Section 3.2. SOURCEID[3:0] is initialized to the values stored in PADDR[3:0] after reset.
Table 19. Source Identification register
Location
Bit
Address
Register
7
6
5
4
$1D
SOURCEID
0
0
0
0
0
0
0
0
Factory Default
3
2
1
0
SOURCEID[3] SOURCEID[2] SOURCEID[1] SOURCEID[0]
PADDR[3]
PADDR[2]
PADDR[1]
PADDR[0]
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3.1.17
Bus Switch Control register (BUSSW_CTRL)
The bus switch control register is a user programmed read/write register which controls the state of the bus switch output driver.
The register is included in the read/write array verification describe in Section 3.2.
Table 20. Bus Switch Control register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$1E
BUSSW_CTRL
0
0
0
0
0
0
0
BUSSW_CTRL
0
0
0
0
0
0
0
0
Factory Default
The BUSSW_CTRL bit controls the state of the BUSSW pin.
BUSSW_CTRL
3.1.18
BUSSW Pin Sate
0
High impedance
An External Pullup is required if an external switch is connected
1
Output Actively Driven Low
Device Lock register (DEVLOCK)
The device lock register is a user programmed OTP register which contains the LOCK_U bit. The register is included in the user
programmed OTP verification describe in Section 3.2. The LOCK_U bit allows the user to prevent writes to the user configuration
array once OTP programming is complete. If the LOCK_U bit is written to ‘1’ when an “Execute Programming of NVM” command
is executed, the LOCK_U OTP bit will be programmed. Upon completion of the OTP programming, future OTP writes to both the
OTP array and the mirror registers for the array are prevented and the User Programmable OTP Array Verification is activated.
The exception to this is the PADDR[3:0] bits. Once the LOCK_U bit is set, the PADDR[3:0] OTP bits cannot be written. However,
the mirror register bits for PADDR[3:0] can be written to allow changes to the physical address through Command and Response
Mode.
Table 21. Device Lock register
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$20
DEVLOCK
LOCK_U
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Factory Default
3.1.19
Device Status registers (DEVSTAT, DEVSTAT2)
The device status registers are read-only registers which contain device status information.
Table 22. Device Status registers
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$21
DEVSTAT
RESERVED
DEVRES
OSCTRAIN_ERR
BUSSW
TESTMODE
ST_ACTIVE
OFFSET_ERR
OC_INIT
$22
DEVSTAT2
F_OTP_ERR U_OTP_ERR
U_RW_ERR
U_UNLOCKED
RESERVED
3.1.19.1
ST_INCMPLT VBUF_UV_ERR BUSIN_UV_ERR
Device Reset (DEVRES)
The device reset bit is set following a device reset. The device reset bit is cleared only by a read of the DEVSTAT register.
DEVRES
Error Condition
0
Normal operation
1
Device reset occurred
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3.1.19.2
Oscillator Training Error (OSCTRAIN_ERR)
The oscillator training error bit is set if an error detected in either the oscillator training settings, or the master communication
timing. Reference Section 3.4.2.
OSCTRAIN_ERR
3.1.19.3
Error Condition
0
No error detected
1
Oscillator Training Error. Reference Section 3.4.2
Bus Switch Status (BUSSW)
The Bus Switch status bit is set if the bus switch output pin is activated.
BUSSW
3.1.19.4
BUSSW Pin State
0
BUSSW pin is inactive
1
BUSSW pin is active
Test Mode (TESTMODE)
The test mode bit is set if the device is in test mode.
TESTMODE
3.1.19.5
Operating Mode
0
Test Mode is not active
1
Test Mode is active
Self-Test Active (ST_ACTIVE)
The self-test active bit is set if any of the self-test bits in the ST_CONTROL register are set.
ST_ACTIVE
3.1.19.6
Condition
0
ST_5_PTRN & ST_A_PTRN & SELFTEST = 0
1
ST_5_PTRN | ST_A_PTRN |SELFTEST = 1
Offset Error Flag (OFFSET_ERR)
The offset error flag is set if the acceleration signal reaches the offset limit.
OFFSET_ERR
3.1.19.7
Error Condition
0
No error detected
1
Offset error detected
Offset Cancellation Init Status Flag (OC_INIT)
The offset cancellation initialization status bit is set once the offset cancellation initialization process is complete, and the filter
has switched to normal mode.
OC_INIT
Error Condition
0
Offset Cancellation in initialization
1
Offset Cancellation initialization complete
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3.1.19.8
Freescale OTP Array Error (F_OTP_ERR)
The factory OTP array error bit is set if a register data fault is detected in the factory OTP array. A device reset is required to clear
the error.
F_OTP_ERR
3.1.19.9
Error Condition
0
No error detected
1
Error Detected in the Factory OTP Array
User OTP Array Error (U_OTP_ERR)
The user OTP array error bit is set if a register data fault is detected in the user OTP array. A device reset is required to clear the
error.
U_OTP_ERR
3.1.19.10
Error Condition
0
No error detected
1
Error Detected in the User OTP Array
User Read/Write Array Error (U_RW_ERR)
The user read/write array error bit is set if a register data fault is detected in the user read/write array. A device reset is required
to clear the error.
U_RW_ERR
3.1.19.11
Error Condition
0
No error detected
1
Error Detected in the User Read/Write Array
User OTP Array Unlocked (U_UNLOCKED)
The user OTP array unlocked bit is set if LOCK_U bit in the DEVLOCK register is not set, indicating that the user array is not
locked.
U_UNLOCKED
3.1.19.12
Condition
0
User Array is Locked
1
User Array is not Locked
Self-Test Incomplete (ST_INCMPLT)
The self-test incomplete bit is set after a device reset and is only cleared when the SELFTEST bit is written to a ‘1’ through
Command and Response Mode.
ST_INCMPLT
3.1.19.13
Condition
0
Self-test has been activated since the last Reset
1
Self-test has not been activated since the last Reset
VBUF Undervoltage Error (VBUF_UV_ERR)
The VBUF undervoltage error bit is set if the VBUF voltage falls below the voltage specified in Section 2.3. Reference Section 3.3
for details on the VBUF undervoltage monitor. The VBUF_UV_ERR bit is cleared on a read of the DEVSTAT2 register.
VBUF_UV_ERR
Error Condition
0
No error detected
1
VBUF Voltage Low
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3.1.19.14
BUS IN Undervoltage Error (BUSI_UV_ERR)
The BUS IN undervoltage error bit is set if the BUS_I voltage falls below the voltage specified in Section 2.3. Reference
Section 3.3 for details on the BUS IN undervoltage monitor. The BUSI_UV_ERR bit is cleared on a read of the DEVSTAT2
register.
BUSI_UV_ERR
3.1.20
Error Condition
0
No error detected
1
BUS_I Voltage Low
Self-Test Control register (ST)
The self-test control register is a user programmed read/write register which contains user specific device configuration
information. The register is included in the read/write array verification described in Section 3.2.
Table 23. Self-Test Control register
Location
Address
$23
Bit
Register
7
6
5
4
3
2
1
0
ST_CONTROL RESERVED RESERVED RESERVED RESERVED RESERVED ST_PTRN_5 ST_PTRN_A SELFTEST
Factory Default
3.1.20.1
0
0
0
0
0
0
0
0
Self-Test Pattern Write Bits (ST_PTRN_5, ST_PTRN_A)
The self-test pattern write bits inhibit DSP writes to the ACC_DATAH and ACC_DATAL registers and forces a write of specific
values to the registers when set. When cleared, DSP writes to the ACC_DATAH and ACC_DATAL registers resume as specified.
These bits are automatically cleared when the PDCM bit is set.
ST_PTRN_A
ST_PTRN_5
0
0
DSP writes to the ACC_DATAH and ACC_DATAL registers as specified
0
1
0x5555 written to ACC_DATAH and ACC_DATAL. DSP write to registers inhibited.
1
0
0xAAAA written to ACC_DATAH and ACC_DATAL. DSP write to registers inhibited.
1
1
0xFFFF written to ACC_DATAH and ACC_DATAL. DSP write to registers inhibited.
3.1.20.2
Function
Self-Test Control (SELFTEST)
The self-test control bit activates and deactivates self-test as described below. Reference Section 3.5.2 for details regarding selftest. This bit is automatically cleared when the PDCM bit is set.
Self-test
Function
0
Self-test deactivated
1
Self-test activated
After a device reset, the ST_INCMPLT bit is set in the DEVSTAT2 register and the device status defaults to Self-test Activation
Incomplete as defined in Section 4.3.2.2. The ST_INCMPLT bit will only be cleared by writing the SELFTEST bits to ‘1’ through
Command and Response Mode. If PDCM is entered without activating self-test, the status bits will include the Self-test Activation
Incomplete” status until a device reset.
If both the SELFTEST bit and one of the Self-test Pattern Write bits are set, the self-test pattern data will be written to the
ACC_DATAH and ACC_DATAL registers. However, the transducer self-test will still be activated as described in Section 3.5.2.
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3.1.21
Write NVM Enable register
The write NVM enable register is a user programmed read/write register that allows the user to write the contents of the user
programmed OTP array mirror registers to the OTP registers. The register is included in the read/write array verification described
in Section 3.2.
Table 24. Write NVM Enable register
Location
Bit
Address
Register
7
6
5
4
3
2
$24
WRITE_NVM_EN
0
0
0
0
0
0
N/A
N/A
N/A
N/A
N/A
N/A
Factory Default
1
0
WR_NVM_EN[1] WR_NVM_EN[0]
N/A
N/A
DSI3 Register Writes executed by the user to the user programmed OTP array only update the mirror register contents for the
OTP array, not the actual OTP registers. To copy the values to the actual OTP registers, a series of three consecutive DSI3
Register Write operations to the Write NVM Enable register must be completed. The register write operations must be
consecutive and in the order shown below to enable the write to NVM. If any commands are transmitted in between the listed
commands, or if the data does not match as shown, the sequence will be reset and no OTP write will be initiated.
Depending upon the operating mode used, the user will need to write the NVM values to OTP either with or without the
PHYSADDR register being written to OTP. If Discovery Mode or switch connected daisy-chain mode will be used, the
PHYSADDR register must remain unprogrammed (0x0000). If a preprogrammed bus mode will be used, the PHYSADDR register
must be programmed to a non-zero value. To support these two user modes, two NVM Write sequences are necessary: one that
allocates the PHYSADDR register to OTP and one that does not.
All user array programming, including locking the user array by setting the LOCK_U bit, must be completed with one NVM Write
command sequence in order to prevent inadvertent user array ECC errors. The procedure for writing to the user OTP array is
listed below:
1.
2.
Write the desired values to the user array registers using Command and Response Mode.
Set the LOCK_U bit in the DEVLOCK registers using Command and Response Mode.
NOTE
This procedure must only be executed once and the LOCK_U bit must be set to prevent
inadvertent ECC errors.
3.
Execute the appropriate NVM Write Sequence using Command and Response Mode to copy the register data to the
OTP array with our without the PHYSADDR register.
Table 25. NVM Write Sequence: PHYSADDR register conditionally included
Register Write to
WRITE_NVM_EN
WRITE_NVM_EN[7:2]
WRITE_NVM_EN[1]
WRITE_NVM_EN[0]
Effect
DSI3 Register Write 1
000000
1
0
No Effect
DSI3 Register Write 2
000000
1
1
No Effect
DSI3 Register Write 3
000000
0
1
Write to OTP initiated
PHYSADDR Register included if and
only if assigned by CRM
Table 26. NVM Write Sequence: PHYSADDR register excluded
Register Write to
WRITE_NVM_EN
WRITE_NVM_EN[7:2]
WRITE_NVM_EN[1]
WRITE_NVM_EN[0]
Effect
DSI3 Register Write 1
000000
0
1
No Effect
DSI3 Register Write 2
000000
1
1
No Effect
0
Write to OTP initiated
PHYSADDR Register is excluded
DSI3 Register Write 3
4.
5.
000000
1
Delay tNVM_WRITE_MAX to allow the device to complete the writes to OTP.
Verify that the OTP write has successfully completed by completing a read back of all of the OTP registers using
Command and Response Mode Register Read commands.
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3.1.22
DSI3 Communication CRC Polynomial registers
The DSI3 communication CRC polynomial registers are user programmed read/write registers which contain the CRC
polynomials used for communication. The register is included in the read/write array verification described in Section 3.2.
Table 27. DSI3 Communication CRC Polynomial registers
Location
Address
Bit
Register
7
6
5
4
3
2
1
0
$25
C_CRMCRCPLY C_CRMCRCPLY[7] C_CRMCRCPLY[6] C_CRMCRCPLY[5] C_CRMCRCPLY[4] C_CRMCRCPLY[3] C_CRMCRCPLY[2] C_CRMCRCPLY[1] C_CRMCRCPLY[0]
$26
R_CRMCRCPLY R_CRMCRCPLY[7] R_CRMCRCPLY[6] R_CRMCRCPLY[5] R_CRMCRCPLY[4] R_CRMCRCPLY[3] R_CRMCRCPLY[2] R_CRMCRCPLY[1] R_CRMCRCPLY[0]
$27
PDCMCRCPLY
PDCMCRCPLY[7]
PDCMCRCPLY[6]
PDCMCRCPLY[5]
PDCMCRCPLY[4]
PDCMCRCPLY[3]
PDCMCRCPLY[2]
PDCMCRCPLY[1]
PDCMCRCPLY[0]
0
0
1
0
1
1
1
1
Factory Default
The C_CRMCRCPLY register contains the 8-bit CRC polynomial used for the Command and Response Mode command as well
as the Background Diagnostic Mode command. The default polynomial is x8 + x5 + x3 + x2 + x + 1. When this register value is
changed using a Command and Response Mode Register Write command, the new polynomial value is enabled for the next
Command and Response Mode command received.
The R_CRMCRCPLY register contains the 8-bit CRC polynomial used for the Command and Response Mode response as well
as the Background Diagnostic Mode response. The default polynomial is x8 + x5 + x3 + x2 + x + 1. When this register value is
changed using a Command and Response Mode Register Write command, the new polynomial value is enabled for the response
to the next Command and Response Mode command received. The response to the Register Write command uses the original
polynomial value.
The PDCMCRCPLY register contains the 8-bit CRC polynomial used for the Periodic Data Collection Mode response. The default
polynomial is x8 + x5 + x3 + x2 + x + 1. This polynomial is enabled once the device enters Periodic Data Collection Mode as
described in Section 4.3.
3.1.23
Acceleration Factory Configuration register (ACC_FCTCFG)
The Acceleration Factory Configuration register is a factory-programmable OTP register which contains acceleration data
specific configuration information. The register is included in the factory-programmed OTP verification. Reference Section 3.2 for
details regarding the OTP verification.
Table 28. Acceleration Factory Configuration register (ACC_FCTCFG)
Location
Address
Register
$30
ACC_FCTCFG
Factory Default
3.1.23.1
Bit
7
6
5
4
3
2
1
0
0
PCM
AXIS
RNG[4]
RNG[3]
RNG[2]
RNG[1]
RNG[0]
0
0
0
0
0
0
0
0
PCM Enable Bit (PCM)
The PCM bit enables the PCM output pin. When the PCM bit is set, the PCM output pin is active and outputs a pulse code
modulated signal proportional to the acceleration response. Reference Section 3.5.4.10 for more information regarding the PCM
output. When the PCM bit is cleared, the PCM output pin is actively pulled low.
PCM
3.1.23.2
PCM Output
0
Actively pulled low
1
PCM signal enabled
Axis Indication Bit (AXIS)
The axis indication bit indicates the axes of sensitivity as shown below.
AXIS
Axis
0
X
1
Z
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3.1.23.3
Range Indication Bits (RNG[4:0])
The range indication bits indicate the full-scale range of the device as shown below.
3.1.24
RNG[4]
RNG[3]
RNG[2]
RNG[1]
RNG[0]
Full-Scale
Acceleration Range
0
0
1
1
0
±25 g
1
0
1
0
0
±125 g
1
0
1
1
0
±187 g
1
1
0
0
1
±250 g
1
1
1
0
0
±375 g
Self-Test Deflection register (ACC_STDATA)
The self-test deflection register is a factory-programmable OTP register which contains the nominal self-test deflection value at
25°C. The register is included in the factory-programmed OTP verification described in Section 3.2.
Table 29. Self-Test Deflection register
Location
Address
$31
Bit
Register
7
ACC_STDATA ACC_ST[7]
6
5
4
3
2
1
0
ACC_ST[6]
ACC_ST[5]
ACC_ST[4]
ACC_ST[3]
ACC_ST[2]
ACC_ST[1]
ACC_ST[0]
The self-test value is a positive deflection value, measured at the factory, and factory-programmed for each device. the stored
value is equal to the difference between the factory measured value at nominal temperature and the minimum self-test limit at
25°C (ACC_STDATA = STMEASURED - ΔSTMIN). When self-test is activated, the acceleration reading is compared to the value in
this register. The difference from the measured deflection value, and the nominal deflection value stored in the register shall not
fall outside the self-test accuracy limits specified in Section 2.5 (ΔSTACC). Reference Section 3.5.2 for more details on calculating
the self-test limits.
3.1.25
Acceleration Configuration register (ACC_CFG)
The acceleration configuration register is a user programmable read/write register which contains acceleration data specific
configuration information. The register is included in the read/write array verification described in Section 3.2.
Table 30. Acceleration Configuration register (ACC_CFG)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$32
ACC_CFG
LPF[3]
LPF[2]
LPF[1]
LPF[0]
SD
OC_FILT[2]
OC_FILT[1]
OC_FILT[0]
0
0
0
0
0
0
0
0
Factory Default
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3.1.25.1
Low-pass filter selection bits (LPF[3:0])
The low-pass filter selection bits select the low-pass filter for the acceleration signal. Reference Section 3.5.4.3 for details
regarding the low-pass filter.
3.1.25.2
LPF[3]
LPF[2]
LPF[1]
LPF[0]
Low-pass filter selected
0
0
0
0
180 Hz, 2 Pole
0
0
0
1
Reserved
0
0
1
0
Reserved
0
0
1
1
Reserved
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
325 Hz, 3 Pole
0
1
1
1
Reserved
1
0
0
0
400 Hz, 3 Pole
1
0
0
1
400 Hz, 4 Pole
1
0
1
0
Reserved
1
0
1
1
800 Hz, 4 Pole
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
1200 Hz, 4 Pole
1
1
1
1
Reserved
SD Bit
The SD bit determines the format of acceleration data. If the SD bit is set to a logic ‘1’, unsigned results are transmitted. If the SD
bit is cleared, signed results are transmitted. Reference Section 3.5.4.9 for details on signed and unsigned data.
SD
3.1.25.3
Operating mode
1
Unsigned Data Output
0
Signed Data Output
Offset cancellation filter selection bits (OC_FILT[2:0])
The offset cancellation filter selection bits select the high-pass filter and rate limiting used for normal operation. Reference
Section 3.5.4.5 for details regarding offset cancellation.
OC_FILT[2]
OC_FILT[1]
OC_FILT[0]
High-pass filter
Rate limiting
0
0
0
0.10 Hz, Single Pole
Enabled
0
0
1
0.10 Hz, Single Pole
Bypassed
0
1
0
Reserved
Reserved
0
1
1
Reserved
Reserved
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
None
NA
1
1
1
None
NA
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3.1.26
Acceleration Data registers (ACC_DATAL, ACC_DATAH)
The Acceleration Data registers are read-only registers which contain the 16-bit output acceleration data. A read of the
ACC_DATAL register responds with the data from both the ACC_DATAH and ACC_DATAL registers. If all 16-bits of data are
desired, it is recommended to read the ACC_DATAL register and to use all 16-bits of the response data.
A read of the either register does not freeze the value of the other register. Thus, subsequent register reads will result in invalid
data when re-assembled into a 16-bit value.
Reference Section 3.5.4.8 for details regarding the 16-bit acceleration data.
Table 31. Acceleration Data registers (ACC_DATAL, ACC_DATAH)
Location
Bit
Address
Register
7
6
5
4
3
2
1
0
$33
ACC_DATAL
ACC_D[7]
ACC_D[6]
ACC_D[5]
ACC_D[4]
ACC_D[3]
ACC_D[2]
ACC_D[1]
ACC_D[0]
$34
ACC_DATAH
ACC_D[15]
ACC_D[14]
ACC_D[13]
ACC_D[12]
ACC_D[11]
ACC_D[10]
ACC_D[9]
ACC_D[8]
0
0
0
0
0
0
0
0
Factory Default
3.1.27
Acceleration Status register (ACC_STAT)
The acceleration status register is a read-only register which contains acceleration data specific status information.
Table 32. Acceleration Status register (ACC_STAT)
Location
Address
Register
$35
ACC_STAT
Factory Default
3.1.27.1
Bit
7
6
5
4
3
0
0
0
0
0
0
0
0
0
0
2
1
ST_ACTIVE OFFSET_ERR
0
0
0
OC_INIT
0
Self-Test Active Flag (ST_ACTIVE)
The self-test active bit is set if any of the self-test bits in the ST_CONTROL register are set.
ST_ACTIVE
3.1.27.2
Condition
0
ST_5_PTRN & ST_A_PTRN & SELFTEST = 0
1
ST_5_PTRN | ST_A_PTRN | SELFTEST = 1
Offset Error Flag (OFFSET_ERR)
The offset error flag is set if the acceleration signal reaches the offset limit.
OFFSET_ERR
3.1.27.3
Error Condition
0
No error detected
1
Offset error detected
Offset Cancellation Init Status Flag (OC_INIT)
The offset cancellation initialization status bit is set once the offset cancellation initialization process is complete, and the filter
has switched to normal mode.
OC_INIT
Error Condition
0
Offset Cancellation in initialization
1
Offset Cancellation initialization complete
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3.1.28
Reserved Registers
A register read command to a reserved register or a register with reserved bits will result in a valid response. The data for
reserved bits may be ‘0’ or ‘1’.
A register write command to a reserved register or a register with reserved bits will execute and result in a valid response. The
data for the reserved bits may be ‘0’ or ‘1’. A write to the reserved bits must always be ‘0’ for normal device operation and
performance.
3.1.29
Invalid Register Addresses
A register read command to a register address outside of the addresses listed in Table 4 will result in a valid response. The data
for the registers will be ‘0x00’.
A register write command to a register address outside of the addresses listed in Table 4 will not execute, but will result in a valid
response. The data for the registers will be ‘0x00’.
A register write command to a read-only register will not execute, but will result in a valid response. The data for the registers will
be the current contents of the register.
3.2
OTP and Read/Write register array CRC verification
3.2.1
Factory-programmed OTP array lock and verification
The factory-programmed OTP array is verified for errors with an error detection algorithm. The error verification is enabled only
when the factory-programmed array is locked.
Once enabled, the verification is continuously calculated on all bits in the registers listed below as well as on the factoryprogrammable device configuration bits with the exception of the factory lock bit. If an error is detected in the OTP array, the
F_OTP_ERR is set in the DEVSTAT2 register.
Register Address
Register Name
$09
PN
$0A - $0D
SN0, SN1, SN2, SN3
$30
ACC_FCTCFG
$31
ACC_STDATA
The verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
3.2.2
User Programmable OTP Array Lock and Error Verification
The User Programmable OTP array is independently verified for errors with an error detection algorithm. The verification is
enabled only when the User Programmable OTP array is locked.
Once the LOCK_U bit is active, the verification is continuously calculated on the user programmable OTP Array, which includes
the registers listed below. If an error is detected in the OTP array, the U_OTP_ERR is set in the DEVSTAT2 register.
Register Address
Register Name
Number of Bits
$03 - $05
MODTYPE[2:0], MODMFGID[2:0], MODREV[2:0]
9
$06
USERID[7:0]
8
$11
PHYSADDR[3:0]
4
$20
DEVLOCK[7]
1
The verification is completed on the memory registers which hold a copy of the fuse array values, not the fuse array values.
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3.2.3
User Programmable Read/Write Array Lock and CRC Verification
The User Programmable read/write array is independently verified for errors with an error detection algorithm. The verification is
enabled only when the PDCM_EN bit is set in the PDCM_EN register.
Once the PDCM_EN bit is set, register writes are ignored and the verification is continuously calculated on the user
programmable read/write array, which includes the registers listed below. If an error is detected in the array, the U_RW_ERR is
set in the DEVSTAT2 register.
Register Address
$11
$12 - $1E
$23
$24
$25 - $27
$32
Register Name
PHYSADDR[3:0] - Secondary Register written during Discovery Mode and/or CRM
BDM_CFG, CRM_CFG, PDCM_CFG, PDCM_EN, CHIPTIME, PDCM_PER_L, PDCM_PER_H, PDCM_RSPST_L,
PDCM_RSPST_H, PDCM_CMD_B_L, PDCM_CMD_B_H, SOURCEID, BUSSW_CTRL
ST_CONTROL
WRITE_NVM_EN
C_CRMCRCPLY, R_CRMCRCPLY, PDCMCRCPLY
ACC_CFG
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3.3
Voltage regulators
The device derives its internal supply voltage from the BUS_I and VSS pins. The internal regulators are supplied by a buffer
regulator (VBUF) to provide immunity from EMC and supply dropouts on BUS_I. External filter capacitors are required, as shown
in Figure 3 on page 5.
The voltage regulator module includes voltage monitoring circuitry which holds the device in reset following power-on until the
internal voltages have increased above the undervoltage detection thresholds. The voltage monitor asserts internal reset when
the external supply or internally regulated voltages fall below the undervoltage detection thresholds. A reference generator
provides a reference voltage for the ΣΔ converter.
BUS_I
VREF
VBUF
Voltage
Regulator
VBUF
VREGA
Voltage
Regulator
Bias
Generator
VREGA
Trim
Bandgap
Reference
VREF
Trim
Trim
VREF_MOD
Reference
Generator
VBUF
VREF
VREGA
Oscillator
Trim
ΣΔ
Converter
OTP
Array
VREG
Voltage
Regulator
VREG
Digital
Logic
DSP
BUS_I
Comparator
BUSI_UV_ERR
Comparator
VBUF_UV_ERR
VBUF
VREG
Comparator
POR
VREGA
VREF
Comparator
Figure 6. Voltage regulation and monitoring
3.3.1
VBUF, VREG and VREGA regulator capacitor
The internal regulators require an external capacitor between the VBUF pin and the VSS pin, the VREG pin and the VSS pin and
the VREGA pin and the VSSA pin for stability. Figure 3 on page 5 shows the recommended types and values for each of these
capacitors.
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3.3.2
BUS_I, VBUF, VREG, VREGA, undervoltage monitor
A circuit is incorporated to monitor the BUS_I supply voltage and the internally regulated voltages, VBUF, VREG and VREGA. If any
of the voltages fall below the specified undervoltage thresholds in Section 2.3, the device will be react as listed below.
•
BUS_I
— If BUS_I falls below the specified threshold at any time, the BUSI_UV_ERR bit is set in the DEVSTAT2 register.
The BUS_I_UV_ERR bit will be cleared once the supply returns above the threshold and either one Periodic Data
Collection Mode status is transmitted with the VBUF_ERR bit set, or a response to a Command and Response
Mode Register Read of the DEVSTAT2 register is transmitted.
•
—
If BUS_I falls below the specified threshold during a command transmission in Command and Response Mode, the
command is ignored, and no DSI3 response transmission occurs. Once the supply returns above the threshold, the
device will resume decoding commands.
—
If BUS_I falls below the specified threshold during a response transmission in Command and Response Mode, the
response is terminated. No attempt is made to resend the response. Once the supply returns above the threshold,
the device will resume decoding commands.
—
If BUS_I falls below the specified threshold during a command transmission in Periodic Data Collection Mode, the
command is ignored and no periodic response occurs during that period. Once the supply returns above the
threshold, the device will resume periodic transmissions in response to commands. The device will resume
decoding Background Diagnostic Mode commands after the Start Condition is met.
—
If BUS_I falls below the specified threshold during a periodic response transmission in Periodic Data Collection
Mode, the response is terminated. No attempt is made to resend the response. Once the supply returns above the
threshold, the device will resume periodic transmissions in response to commands. The device will resume
decoding Background Diagnostic Mode commands after the Start Condition is met.
—
If BUS_I falls below the specified threshold during a Background Diagnostic Mode response transmission in
Periodic Data Collection Mode, the response is terminated. No attempt is made to resend the response. Once the
supply returns above the threshold, the device will resume periodic transmissions in response to commands. The
device will resume decoding Background Diagnostic Mode commands after the Start Condition is met.
VBUF
—
•
If VBUF falls below the specified threshold at any time, the VBUF_UV_ERR bit is set in the DEVSTAT2 register. If a
response transmission is in process, the response is terminated. No attempt is made to resend the response. Once
the supply returns above the threshold, the device will resume decoding commands and transmission of responses.
The VBUF_UV_ERR bit will be cleared once the supply returns above the threshold and one Periodic Data
Collection Mode status is transmitted with the VBUF_UV_ERR bit set.
VREG or VREGA
—
If VREG or VREGA falls below the specified threshold at any time, the device is reset.
Reference Figure 7 for an example of a supply line interruption during a response in Periodic Data Collection Mode.
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BUS_I microcut occurs
BUS_I
BUS_I undervoltage detected
VBUF
VREG
VREGA
Response Terminated
IDATA
POR
Time
Figure 7. BUS_I Microcut response
3.3.3
VBUF Capacitance monitor
A monitor circuit is incorporated to ensure predictable operation if the connection to the external VBUF capacitor becomes open.
The VBUF regulator is disabled tPOR_CAPTEST seconds after POR for a duration of tVBUFCAPTST_TIME seconds. If the external
capacitor is not present, the regulator voltage will fall below the threshold specified in Section 2.3 causing the VBUF_ERR bit to
be set in the DEVSTAT2 register.
Next Power on Cycle
tPOR_CAPTEST
tPOR_CAPTEST
tCAPTST_TIME
tCAPTST_TIME
Cap_Test
VBUF
Capacitor Present
VPORVBUF_f
Capacitor Open
POR
Time
Figure 8. VBUF Capacitor monitor
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3.3.4
VREG capacitance monitor
A monitor circuit is incorporated to ensure predictable operation if the connection to the external VREG capacitor becomes open.
The VREG regulator is disabled tPOR_CAPTEST seconds after POR for a duration of tVREGCAPTST_TIME seconds. If the external
capacitor is not present, the regulator voltage will fall below the internal reset threshold, forcing a device reset.
Next Power on Cycle
tPOR_CAPTEST
tPOR_CAPTEST
tCAPTST_TIME
tCAPTST_TIME
Cap_Test
VREG
Capacitor Present
Capacitor Open
VPORVREG_f
POR
Time
Figure 9. VREG Capacitor Monitor
3.3.5
VREGA Capacitance Monitor
A monitor circuit is incorporated to ensure predictable operation if the connection to the external VREGA capacitor becomes open.
The VREGA regulator is disabled tPOR_CAPTEST seconds after POR for a duration of tVREGCAPTST_TIME seconds. If the external
capacitor is not present, the regulator voltage will fall below the internal reset threshold, forcing a device reset.
Next Power on Cycle
tPOR_CAPTEST
tPOR_CAPTEST
tCAPTST_TIME
tCAPTST_TIME
Cap_Test
VREGA
Capacitor Present
VPORVREGA_f
Capacitor Open
POR
Time
Figure 10. VREGA capacitor monitor
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3.4
Internal oscillator
The device includes a factory-trimmed oscillator as specified in Section 2.8.
3.4.1
Oscillator training
The device includes a feature to train the oscillator to a tighter accuracy than the factory-trimmed capability assuming the system
master has a tighter oscillator accuracy than the slave factory trimmed capability. Oscillator training is enabled if the CK_CAL_EN
bit is set in the CRM_CFG register and is accomplished by verifying the timing of periodic transmissions from the master against
the values stored in the CRM_PER[1:0] and PDCM_PER[2:0] bits of the user read/write register array. The master programs the
intended Periodic Data Collection Mode command period into the PDCM_PER[2:0] bits and the intended Command and
Response Mode command period into the CRM_PER[1:0] bits. The device then calculates the number of transmission periods
for every 4 ms (nCRM_PER_4ms_TYP and nPDCM_PER_4ms_TYP).
In Command and Response Mode, oscillator training is completed over 4 ms periods if and only if the CK_CAL_EN bit is set and
the Command and Response Mode period is between 500 μs and 4 ms, inclusive. The following procedure is used to train the
oscillator (Figure 11):
1.
2.
The device counts the number of oscillator cycles in nCRM_PER_4ms_TYP periods (nOSC_4ms).
nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training window (OscTrainWIN) specified in
Section 2.8, an oscillator adjustment is made. Otherwise, no adjustment is made.
a) If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency target is decreased by
OscTrainRES.
b) If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target is increased by OscTrainRES.
c) The oscillator frequency target value is changed at the end of the command blocking time for the command ending
the nCRM_PER_OSC calculation.
If the CK_CAL_EN bit is cleared after oscillator training has already been initiated, the state of the oscillator is determined by the
state of the CK_CAL_RST bit in the CRM_CFG register. If the CK_CAL_RST bit is cleared, the last adjustment value for the
oscillator is maintained. If the CK_CAL_RST bit is set, the oscillator is reset to its untrained value with the untrained tolerance
specified in Section 2.8.
Command
tCmdBlock_CRM
Response
One CRM Period
4ms = nCRM_PER_4ms_TYP
nOSC_4ms
Oscillator
Adjustment
New Oscillator
Count Starts
t
Figure 11. Command and Response Mode oscillator training timing diagram
In Periodic Data Collection Mode, oscillator training is completed over 4 ms periods if the CK_CAL_EN bit is set. The following
procedure is used to train the oscillator (reference Figure 12):
1.
2.
The device counts the number of oscillator cycles in nPDCM_PER_4ms_TYP periods (nOSC_4ms).
nOSC_4ms is compared to nOSC_4ms_TYP. If the value is within the acceptable training window (OscTrainWIN) specified in
Section 2.8, an oscillator adjustment is made. Otherwise, no adjustment is made.
a) If nOSC_4ms is greater than nOSC_4ms_TYP + OscTrainADJ, the oscillator frequency target is decreased by
OscTrainRES.
b) If nOSC_4ms is less than nOSC_4ms_TYP - OscTrainADJ, the oscillator frequency target is increased by OscTrainRES.
c) The oscillator frequency target value is changed at the end of the command blocking time for the command ending
the nPDCM_PER_OSC calculation.
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Command
tCmdBlock_PDCM
Response
One PDCM Period
4ms = nPDCM_PER_4ms_TYP
nOSC_4ms
New Oscillator
Count Starts
Oscillator
Adjustment
t
Figure 12. Periodic Data Collection Mode oscillator training timing diagram
3.4.2
Oscillator training error handling
If oscillator training is enabled by the user, but the conditions are not correct to complete oscillator training, the OSC_TRAIN bit
is set in the DEVSTAT register. The following conditions will result in the OSCTRAIN_ERR bit being set.
•
The CLK_CAL_EN bit in the CRM_CFG register is set, the device is in Command and Response Mode and Command and
Response Mode period is not set to 500 μs, 666 μs, 1000 μs, 1333 μs, 2000 μs or 4000 μs.
•
The CLK_CAL_EN bit in the CRM_CFG register is set and the measured period (nOSC_4ms) for either Command and
Response Mode or Periodic Data Collection Mode is outside of the Oscillator Training Window (OscTrainWIN).
—
The result of the comparison is filtered with an up and down counter.
—
If nOSC_4ms is outside the oscillator training window, the counter is incremented.
—
If nOSC_4ms is inside the oscillator training window, the counter is decremented.
—
If the counter reaches 64 counts, the OSCTRAIN_ERR bit is set.
—
The up and down counter has a maximum value of 127 and a minimum value of 0.
3.5
Acceleration signal path
3.5.1
Transducer
The device transducer is an overdamped mass-spring-damper system defined by the following transfer function:
2
ωn
H ( s ) = -----------------------------------------------------2
2
s + 2 ⋅ ξ ⋅ ωn ⋅ s + ωn
Eqn. 1
where:
ζ = Damping Ratio
ωn = Natural Frequency = 2∗Π∗fn
Reference Section 2.7 for transducer parameters.
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3.5.2
Self-test interface
The self-test interface applies a voltage to the g-cell, causing deflection of the proof mass. The resulting acceleration readings
can be compared against the values stored in the Self-Test Deflection registers (Reference Section 3.1.24). The self-test
interface is controlled through SPI write operations to the ST_CONTROL register described in Section 3.1.20. The PDCM_EN
bit in the PDCM_EN register must also be low to enable self-test (Periodic Data Collection Mode not enabled). A diagram of the
self-test interface is shown in Figure 13.
SELF-TEST
VOLTAGE
GENERATOR
Transducer
PDCM_EN
PDCM_EN
ST
Figure 13. Self-test interface
Self-test can be verified via two methods:
3.5.2.1
Raw self-test deflection verification
The raw self-test deflection can be verified against raw self-test limits in Section 2.5.
3.5.2.2
Delta self-test deflection verification
The raw self-test deflection can be verified against the nominal temperature self-test deflection value recorded at the time the
device was produced. The production self-test deflection is stored in the ACC_STDATA register such that the minimum stored
value (0x00) is equivalent to ΔSTMIN, and the maximum stored value (0xFF) is equivalent to ΔSTMAX. The Delta Self-test
Deflection limits can then be determined by the following equations:
ΔST ACCMINLIMIT = FLOOR ⋅ [ ( ΔST MIN + ACCSTDATA ) × ( 1 – ΔST ACC ) ]
Eqn. 2
ΔST ACCMAXLIMIT = CEIL ⋅ [ ( ΔST MIN + ACCSTDATA ) × ( 1 + ΔST ACC ) ]
Eqn. 3
where:
ΔSTACC = The accuracy of the self-test deflection relative to the stored deflection as specified in Section 2.5.
ACCSTDATA = The value stored in the ACC_STDATA register.
ΔSTMIN = The minimum self-test deflection at 25°C as specified in Section 2.5.
ΔSTMAX = The maximum self-test deflection at 25°C as specified in Section 2.5.
3.5.3
Analog front-end and ΣΔ converter
A sigma delta modulator converts the differential capacitance of the transducer to a data stream that is input to the DSP.
Transducer
α1=
CTOP
VX
First
Integrator
CINT1
z-1
Second
Integrator
α2
z-1
1 - z-1
CBOT
1-bit
Quantizer
ΣΔ_OUT
1 - z-1
ADC
ΔC = CTOP - CBOT
β1
β2
DAC
V = ±2 × VREF
V = ΔC x VX / CINT1
Figure 14. ΣΔ Converter block diagram
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3.5.4
Digital-signal processor
A digital-signal processor (DSP) is used to perform signal filtering and compensation. A diagram illustrating the signal processing
flow within the DSP is shown in Figure 15.
Sinc
filter
A
ΣΔ_OUT
B
Digital
Gain
F
Downsampling
C Low-pass
filter
D
E
Compensation
Offset
Offset Cancellation Cancellation
Low-pass filter
Output
Rate Limiting
H
G
Interpolation
Output
Scaling
J Output
Figure 15. Signal-chain diagram
Table 33. Signal-chain characteristics
Description
Sample
time
(μs)
Data
Width
(Bits)
Overrange
(Bits
Signal
Width
(Bits)
Signal
Noise
(Bits)
Signal
Margin
(Bits)
A SD
1
1
1
B SINC filter
16
20
14
C Digital gain
16
20
D Low-pass filter
16
26
4
10
3
9
E Compensation
16
26
4
10
3
9
F Down sampling
256
26
4
10
3
9
G Offset cancellation
256
26
4
10
3
9
Typical
Block
Latency
Reference
51 μs
Section 3.5.4.1
Section 3.5.3
14
Section 3.5.4.2
Section 3.5.4.3
Section 3.5.4.3
17 μs
Section 3.5.4.4
Section 3.5.4.5
Section 3.5.4.5
H DSP sampling and interpolation
8
10
8 μs
Section 3.5.4.7
J 10-bit output scaling
1
10
1 μs
Section 3.5.4.8
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3.5.4.1
Decimation Sinc filter
The serial data stream produced by the ΣΔ converter is decimated and converted to parallel values by a 3rd order sinc filter with
a decimation factor of 16.
3
1 – z – 16
H ( z ) = ---------------------------------–
1
16 × ( 1 – z )
Eqn. 4
Figure 16. Sinc-filter response
3.5.4.2
Digital gain
The DSP applies a selectable one or two times digital gain to the output of the sinc filter. The gain applied is dependent on the
output range of the device.
3.5.4.3
Low-pass filter
Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter.
( n 11 ⋅ z 0 ) + ( n 12 ⋅ z – 1 ) + ( n 13 ⋅ z – 2 ) ( n 21 ⋅ z 0 ) + ( n 22 ⋅ z – 1 ) + ( n 23 ⋅ z – 2 )
H ( z ) = a 0 ⋅ -------------------------------------------------------------------------------------------- ⋅ -------------------------------------------------------------------------------------------( d 11 ⋅ z 0 ) + ( d 12 ⋅ z – 1 ) + ( d 13 ⋅ z – 2 ) ( d 21 ⋅ z 0 ) + ( d 22 ⋅ z – 1 ) + ( d 23 ⋅ z – 2 )
Eqn. 5
The device provides the option for one of six low-pass filters. The filter is selected with the LPF[3:0] bits in the ACC_CFG register.
The filter selection options are listed in Section 3.1.25.1. Response parameters for the low-pass filter are specified in Section 2.7.
Filter characteristics are illustrated in the following figures.
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Table 34. Low-pass filter coefficients
Filter
Number
Description
-3dB
Frequency
(±5%)
180 Hz
325Hz
400 Hz
400 Hz
800 Hz
1200 Hz
Filter
order
2
3
3
4
4
4
Group
Delay
Filter Coefficients
a0
0.000534069200512
n11
0.25
d11
1
n12
0.499999985098839
d12
-1.959839582443237
n13
0.25
d13
0.960373640060425
n21
1
d21
1
n22
0
d22
0
n23
0
d23
0
a0
0.04247547499835491180
n11
0.00109037756919860840
d11
1
n12
0.00108939409255981445
d12
-0.95752453804016113281
n13
0
d13
0
n21
0.24988752603530883789
d21
1
n22
0.49999989569187164307
d22
-1.93140876293182373047
n23
0.25011256337165832520
d23
0.93358850479125976562
a0
0.05189235225042199
n11
0.001629077582099646
d11
1
n12
0.001630351547919014
d12
-0.9481076477495780
n13
0
d13
0
n21
0.2500977520825902
d21
1
n22
0.4999999235890745
d22
-1.915847097557409
n23
0.2499023243303036
d23
0.9191065266874253
a0
0.003135988372378
n11
0.000999420881271
d11
1.0
n12
0.001998946070671
d12
-1.892452478408814
n13
0.000999405980110
d13
0.89558845758438
n21
0.250004753470421
d21
1.0
n22
0.499986037611961
d22
-1.919075012207031
n23
0.250009194016457
d23
0.923072755336761
a0
0.011904109735042
n11
0.003841564059258
d11
1.0
n12
0.007683292031288
d12
-1.790004611015320
n13
0.003841534256935
d13
0.801908731460571
n21
0.250001862645149
d21
1.0
n22
0.499994158744812
d22
-1.836849451065064
n23
0.250003993511200
d23
0.852215826511383
a0
0.025461918674409
n11
0.008307680487633
d11
1.0
n12
0.016615495085716
d12
-1.692260980606079
n13
0.008307650685310
d13
0.717722892761230
n21
0.250000774860382
d21
1.0
n22
0.499997481703758
d22
-1.753850817680359
n23
0.250001743435860
d23
0.787081658840179
Attenuation @ 1000
Hz
(dB)
Min
Typ
Max
1190 μs
24.8
25.6
26.5
856 μs
20.2
21.4
22.6
697 μs
15.5
16.7
17.8
841 μs
18.1
19.5
21.0
420 μs
4.42
4.94
5.54
280 μs
1.83
2.03
2.27
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Figure 17. Low-pass filter characteristics: fC = 180 Hz, 2-Pole, tS = 16 μs
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Figure 18. Low-pass filter characteristics: fC = 325 Hz, 3-Pole, tS = 16 μs
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Figure 19. Low-pass filter characteristics: fC = 400 Hz, 3-Pole, tS = 16 μs
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Figure 20. Low-pass filter characteristics: fC = 400 Hz, 4-Pole, tS = 16 μs
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Figure 21. Low-pass filter characteristics: fC = 800 Hz, 4-Pole, tS = 16 μs
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Figure 22. Low-pass filter characteristics: fC = 1200 Hz, 4-Pole, tS = 16 μs
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3.5.4.4
Signal compensation
The device includes internal gain and compensation circuitry to compensate for sensor offset, sensitivity and non-linearity.
3.5.4.5
Offset cancellation
The device provides an optional offset cancellation circuit to remove internal offset error. A block diagram of the offset cancellation
is shown in Figure 23.
OC_FILT[0]
HIGH-PASS FILTER DATAPATH
OFFSET RATE LIMITED DATAPATH
OFFSET RATE LIMITING
To Interpolation
INPUT DATA
INC/DEC
OFFSET CANCELLATION
LOW-PASS FILTER
n + ( n ⋅ z–1 )
1
2
a ⋅ ------------------------------------0
d + ( d ⋅ z–1 )
1
2
OUT
UP/DOWN
COUNTER
0.5 Hz (Derived from fOSC)
Input Data downsampled to 256 μs
CLK
OFFSET MONITOR
OFFMONNEG
INC/DEC
OUT
UP/DOWN
COUNTER
OFFMONPOS
2 kHz (Derived from fOSC)
OFF_ERR
OFFMONCNTLIMIT
CLK
Figure 23. Offset cancellation block diagram
The transfer function for the offset LPF is:
no 1 + ( no 2 ⋅ z – 1 )
H ( z ) = ao 0 ⋅ -------------------------------------------do 1 + ( do 2 ⋅ z – 1 )
Eqn. 6
Response parameters are specified in Section 2 and the offset LPF coefficients are specified in Table 36.
During start up, two phases of the offset LPF are used to allow for fast convergence of the internal offset error during initialization.
The timing for the startup phases is shown in Table 35.
The offset low-pass filter used in normal operation is selected by the OC_FILT[2:0] bits in the ACC_CFG register. Output rate
limiting can be applied to the output of the offset low-pass filter. Rate limiting is also enabled by the OC_FILT[2:0] bits. If rate
limiting is enabled, the offset cancellation output is updated by OFFStep LSB every tOffRate seconds.
The offset cancellation circuit output value is frozen when self-test is active, even if the offset cancellation circuit is in a startup
phase. The timers controlling the startup phase times listed in Table 35 are not frozen. To ensure proper offset cancellation
startup, prior to activating self-test, the user should verify that the offset cancellation initialization is complete by monitoring the
OC_INIT bit in the DEVSTAT register.
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Table 35. Offset cancellation startup characteristics and timing
Offset cancellation
startup phase
Offset LPF
Output rate limiting
Total time for phase
1
10 Hz
Bypassed
80 ms
2
1.0 Hz
Bypassed
70 ms
Self-test
Offset Cancellation Updates are Suspended
Selected by
OC_FILT[2:0]
Complete
User Enabled
Selected by
OC_FILT[2:0]
N/A
Table 36. Offset low-pass filter coefficients
Description
-3 dB frequency
(±5%)
10 Hz
1.0 Hz
0.1 Hz
Coefficients
Latency/Group delay
ao0
0.015956938266754
no1
0.499998132328277
do1
1.0
no2
0.499998132328277
do2
-0.984043061733246
ao0
0.00160720286658033729
no1
0.5
do1
1.0
do2
-0.99839282035827636719
15.91 ms
159.1ms
no2
0.5
ao0
0.0001608133316040
no1
0.4999999403953552
do1
1.0
no2
0.4999999403953552
do2
-0.9998391270637512
1591 ms
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Figure 24. 10 Hz offset cancellation low-pass filter characteristics
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Figure 25. 1.0 Hz offset cancellation low-pass filter characteristics
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Figure 26. 0.1 Hz offset cancellation low-pass filter characteristics
3.5.4.6
Offset monitor
The device includes an offset monitor circuit. The offset monitor is enabled 2.1 seconds following reset regardless of the state of
the OC_FILT bits in the ACC_CFG register. The output of the single pole, low-pass filter in the offset cancellation block is
continuously monitored against the offset limits specified in Section 2.4. An up/down counter is employed to count up If the output
exceeds the limits, and to count down if the output is within the limits. The output of the counter is compared against the count
limit OFFMONCNTLIMIT. If the counter exceeds the limit, the OFFSET_ERR bit in the ACC_STAT register and in the DEVSTAT
register is set. The counter rails once the max counter value is reached (OFFMONCNTSIZE).
3.5.4.7
Data interpolation
The device includes 16 to 1 linear data interpolation to minimize the system sample jitter. Each result produced by the digital
signal processing chain is delayed one sample time. On detection of a Periodic Data Collection Mode command, the transmitted
data is interpolated from the one previous samples, resulting in a latency of one sample time, and a maximum signal jitter of 1 μs.
3.5.4.8
Output scaling
The 26-bit digital output from the DSP is clipped and scaled to a 10-bit, 14-bit, or 16-bit data word. The 10-bit and 14-bit data
words are used for Periodic Data Collection Mode and the 16-bit range is stored in the ACC_DATAH and ACC_DATAL registers
for access during Command and Response Mode.
The sensitivity of the data is the same for all ranges. If the 14-bit data length is selected, four additional bits of range are
transmitted. If the ACC_DATAH and ACC_DATAL registers are accessed, six additional bits of range are available. These
additional bits of range are intended for test use only and are not covered by the specifications listed in Section 2.4. Reference
Table 37 for the acceleration data values for all ranges.
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3.5.4.9
Output data values
Table 37. Nominal acceleration data values
16-bit data
Unsigned digital
value
Decimal
Hex
33280 to 0x8200 to
65535
0xFFFF
10-bit data
Nominal acceleration (g)
Signed digital value
Unsigned digital
value
Signed digital
value
Decimal
Hex
Decimal
Hex
Decimal
Hex
512 to
32767
0x200 to
0x7FFF
NA
NA
NA
NA
25 g
range
125 g
range
187 g
range
250 g
range
375 g
range
Overrange data
33279
0x81FF
511
0x1FF
1023
0x3FF
511
0x1FF
24.9512
124.756
186.633
249.512
374.277
33278
0x81FE
510
0x1FE
1022
0x3FE
510
0x1FE
24.9023
124.512
186.267
249.023
373.544
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32770
0x8002
2
0x0002
514
0x202
2
0x002
0.976563 0.488281 0.730460 0.976563
32769
0x8001
1
0x0001
513
0x201
1
0x001
0.048828 0.244141 0.365230 0.488281 0.732440
32768
0x8000
0
0x0000
512
0x200
0
0x000
32767
0x7FFF
-1
0xFFFF
511
0x1FF
-1
0x3FF
-0.048828 -0.24414 -0.365230 -0.488281 -0.732440
32766
0x7FFE
-2
0xFFFE
510
0x1FE
-2
0x3FE
-0.976563 -0.488281 -0.730460 -0.976563 -1.46488
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
32258
0x7E02
-510
0xFE02
2
0x002
-510
0x202
-24.9023
-124.512
-186.267
-249.023
-373.544
32257
0x7E01
-511
0xFE01
1
0x001
-511
0x201
-24.9512
-124.756
-186.633
-249.512
-374.277
NA
NA
NA
NA
Overrange Data
0
0x000
-512
0x200
Fault
1 to
32256
0
0x0001 to -32767 to 0x8001 to
0x7E00
0xFE00
-512
0x0000
3.5.4.10
-32768
0x8000
0
0
0
0
1.46488
0
PCM output function
The device provides the option for a PCM output function. The PCM output is enabled if the PCM bit is set in the ACC_FCTCFG
register. Selecting the PCM output enables the following functions:
•
The acceleration value output from the offset cancellation block is saturated to 9-bits and converted to an unsigned value.
•
The 9-bit acceleration value is input into a summer clocked at 8MHz.
•
The carry from the summer circuit is output to the PCM pin.
A block diagram of the PCM output is shown in Figure 27.
DSP Output
A
PCM
CARRY
9
9 Bit ADDER
9
B
SUM
fCLK
9
DD
QQ
DD
QQ
DD
QQ
DDFF
QQ
DFF
Q
FF
FF
FF
FF
FF
FF
FF
CLK
QQ
CLK
CLK
QQ
CLK
CLK
QQ
CLK
CLK
QQ
CLK
CLK
Q
Figure 27. PCM output function block diagram
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3.6
DSI3 physical layer
3.6.1
Command receiver
The command receive block converts voltage transitions on the BUS_I pin to a digital pulse train for decoding by the DSI data
link layer.
The supply voltage can vary throughout the specified range, so the communication high voltage (VHIGH) must be sampled and
averaged with a low-pass filter. The communication low voltage is then determined by comparing the supply voltage to the
sampled and averaged VHIGH voltage. Figure 28 shows a block diagram of the command receiver physical layer.
Cmd_Block
VDELTA_THRESH
BUS_I
+
R
VHIGH
Command_Detect
D
Command
Count
Counter
VHigh_Sample
fOSC
Control
Cmd_Start
Logic
Cmd_Valid
Cmd_Block
Command_Detect
VSS
VHigh_Sample
Figure 28. Command receiver physical layer
The start of a command is detected when the comparator output (Command_Detect) is low. The comparator output is input to a
counter that is updated at the internal oscillator frequency. Control logic monitors the counter output and generates the following
signals:
1.
2.
3.
4.
Cmd_Start
a) Asserted when the counter reaches a value of one.
b) Deasserted at POR, if the counter does not reach Cmd_Valid_Count (tCmd_Valid) within tCmd_BitTime of Cmd_Start
assertion, or at the end of the command blocking time for the operating mode (tCmdBlock_DISC, tCmdBlock_CRM,
tCmdBlock_PDCM, tCmdBlock_BDM).
Cmd_Valid
a) Asserted if the counter reaches Cmd_Valid_Count within tCMD_BitTime of Cmd_Start assertion (tCmd_Valid).
b) Deasserted at POR and when Cmd_Start is deasserted.
VHigh_Sample
a) Asserted tDSI_DISC_POR after POR and when Cmd_Start is deasserted.
b) Deasserted when Cmd_Start is asserted.
Cmd_Block:
a) Asserted based on the operating mode:
– Discovery Mode: A complete command is received as defined in Section 4.1.3 and Section 2.6.
b)
–
Command and Response Mode: A complete command is received as defined in Section 4.2 and Section 2.6.
–
Periodic Data Collection Mode: A complete command is received as defined in Section 4.3 and Section 2.6.
Deasserted at POR and when Cmd_Start is deasserted.
Once a full command is received, based on the operating mode, the command is transferred to the DSI data link layer for
decoding.
Figure 29 shows a timing diagram of the command receiver when a valid command is received, and Figure 30 shows a timing
diagram of the command receiver when a microcut is received during the command window. Voltage values and timing
parameters are specified in Section 2.3 and Section 2.7.
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BUS_I
Cmd_Start
tCmd_Valid
Cmd_Valid
tCmdBlock_CRM
tCmdBlock_ST_CRM
Cmd_Block
VHigh_Samp
t
Figure 29. DSI3 Command receiver timing diagram: Valid command
BUS_I
Cmd_Start
tCmd_Valid
Cmd_Valid
Cmd_Block
VHigh_Samp
t
Figure 30. DSI3 Command receiver timing diagram: Microcut
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3.6.2
Response transmitter
The response transmitter block converts two digital signals into two supply modulation currents. The response currents are
generated such that the rise and fall times are the same whether the IRESP current is being transmitted or the 2 x IRESP current
is being transmitted. A diagram of the response transmitter is shown in Figure 29. Current values and timing parameters are
specified in Section 2.3 and Section 2.7.
IDATA
Transmit Level ‘0’
Magnitude
Control
Transmit Level ‘1’
Slew Control
Transmit Level ‘2’
VSS
Figure 31. DSI3 transmitter block diagram
3.6.3
Discovery Mode current sense
The current sense circuit is used during Discovery Mode to determine if any additional slaves are connected to the BUS_O pin
of the device. A diagram of the current sense circuit is shown in Figure 32. Current values and timing parameters are specified
in Section 2.3 and Section 2.7. Details regarding Discovery Mode are included in Section 4.1.3.
IREF
AddrCount
BUS_I
Amp
RSENSE
BUS_O
IOUT
+
ICCQ Sample
-
IDISC >0?
-
Disc_Compare
ICCQ
Control
Logic
LastDevice
ICCQ
Sample & Hold
Disc_Command_Rcvd
Figure 32. Discovery Mode current sense circuit block diagram
VHIGH
VLOW
tDisc_Dly
tDisc_Iccqsamp
ICCQ_SAMPLE
IRESP Activation
tIDiscsamp_Dly
tIDiscsamp
Disc_Compare
t
Figure 33. DSI3 Discovery Mode sensing timing diagram
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3.6.4
Bus-switch control
The bus-switch output pin is the driver for a high-side, daisy-chain switch. When switch connected daisy-chain mode is used, as
described in Section 4.1.2, the BUSSW pin is connected to the gate of an external p-channel FET which connects BUS_I to the
next slave in the daisy chain. If used, an external pullup resistor is required on the gate of the p-channel FET. Reference Figure 3
on page 5 for details on the recommended external circuitry.
BUSIN
R1
M1
To Next Device on the Chain
Bus Switch Enable
Figure 34. Daisy-chain bus switch driver block diagram
3.7
Data transmission modes
3.7.1
Simultaneous Sampling mode
Figure 35. Simultaneous Sampling mode
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3.7.2
Synchronous Sampling mode with minimum latency
Figure 36. Synchronous sampling mode with minimum latency
3.8
Initialization timing
tDSP_POR
POR
Internal
Delay
Offset
Cancellation
Phase 1
Offset
Cancellation
Phase 2
tOCPH1
tOCPH2
Offset
Cancellation
Normal
User set up and self-test control through CRM
Read Status Registers (DEVSTAT, DEVSTAT2)
Initialize Signal Chain
Offset
Verification
Self-test
Verification
Initialize Communication
tDSI_POR
Enabled/Disabled
By OCFILT[2:0]
Discovery
Mode
Offset
Verification
Enter
PDCM
Command
Periodic
Data
Collection
Mode
tSTART_DISC
POR
Figure 37. Initialization timing
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3.9
Overload response
3.9.1
Overload performance
The device is designed to operate within a specified range. Acceleration beyond that range (overload) impacts the output of the
sensor. Acceleration beyond the range of the device can generate a DC shift at the output of the device that is dependent upon
the overload frequency and amplitude. The g-cell is overdamped, providing the optimal design for overload performance.
However, the performance of the device during an overload condition is affected by many other parameters, including:
•
g-cell damping
•
Non-linearity
•
Clipping limits
•
Symmetry
Figure 38 shows the g-cell, ADC and output clipping of the device over frequency. The relevant parameters are specified in
Section 2.
g-cellRolloff
Acceleration (g)
Region Clipped
by Output
LPFRolloff
io
Reg
nC
y ged b
lipp
cell
Determined by g-cell
roll-off and ADC clippi
e to
n du arity
ADC
o
i
t
y
r
e
b
to
in
ed
l Dis on-L
lipp
igna and N
nC
S
o
i
f
g
o
Re
etry
io n
Reg Asymm
gg-cell_Clip
gADC_Clip
Determined by g-cell
roll-off and full scale ra
gRange_Norm
Region of Interest
fLPF
Region of No Signal Distortion Beyond
Specification
fg-Cell
5kHz
10kHz
Frequency (kHz)
Figure 38. Output clipping vs. frequency
3.9.2
Sigma Delta modulator overrange response
Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits
of the DSP. The ΣΔ converter can saturate at levels above those specified in Section 2 (GADC_CLIP). The DSP operates
predictably under all cases of overrange, although the signal may include residual high-frequency components for some time
after returning to the normal range of operation due to non-linear effects of the sensor.
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4
DSI3 Protocol
The DSI3 standard describes two function classes: Signal Function Class and Power Function Class. This device is a slave
conforming to the Signal Function Class requirements. The device does not support Power Function Class. The following
sections describe the DSI3 Signal Function Class features supported by the device.
4.1
Address assignment
The device supports all three address assignment methods described in the DSI3 standard as described below.
4.1.1
Address assignment method for parallel connected slaves
Devices connected in parallel must have preprogrammed addresses by storing a non-zero value into the PADDR[3:0] bits of the
PHYSADDR NVM register. If a non-zero value is stored in this NVM register, The device does not participate in any other address
assignment method and waits for Command and Response Mode for further configuration. Reference Section 4.2 for details
regarding Command and Response Mode.
4.1.2
Address assignment method for bus switch connected daisy-chain devices
A device connected in daisy chain by a bus switch may have either a preprogrammed address as described in Section 4.1.1, or
an un-programmed address.
If the address is preprogrammed, the device does not participate in any other address assignment method and waits for
Command and Response Mode for further configuration information, including activating the bus switch to connect the next
device on the bus. Reference Section 4.2 for details regarding Command and Response Mode.
If the address is un-programmed, once power is applied, the device is the only device on the segment which requires an address
assignment. The device will accept a Command and Response Mode register write command addressed to Address $0 (global
command), which writes the PADDR[3:0] bits to a non-zero value. Once a physical address is assigned to the device, Command
and Response Mode is used with the assigned physical address for further configuration. This includes closing the bus switch to
connect the next device and/or bus segment to the master.
On power up, the device bus switch output defaults to de-activated.
4.1.3
DSI3 Discovery Mode: Address assignment method for resistor connected daisy-chain
devices
A device connected via in daisy chain via a resistor has an un-programmed address and uses Discovery Mode to obtain it’s
physical address (PADDR[3:0]).
The Master device must initiate Discovery Mode automatically after power is applied to the bus segment by sending a sequence
of Discovery commands. The Discovery Command is shown in Figure 39 and the timing is defined in Section 2.6. The device will
detect a Discovery Command tSTART_DISC after a power on reset and for intervals of tPER_Disc until Discovery Mode has ended
(the maximum value of tSTART_DISC).
The Discovery Mode follows the sequence listed below. Figure 39 shows a timing diagram of the Discover Protocol for a four
device segment.
1.
2.
3.
4.
5.
6.
7.
8.
The master powers up the bus segment to a known state.
The master transmits the Discovery Command.
After a predetermined delay (tSTART_DISC_RSP), all devices without a physical address activate a current ramp to the 2x
response current at a ramp rate of iDISC_RAMP.
Each device monitors the current through its sense resistor (ΔiSENSE).
a) If the current is above iRESP, the device disables its response current, increments its physical address counter and
waits for the next Discovery Command.
b) If the current is low (ΔiSENSE less than iRESP), the device continues to ramp its response current to 2* iRESP in time
tDISC_RAMP_RSP and maintains the current at 2* iRESP for time tDISC_IDLE_RSP.
c) After time tDISC_IDLE_RSP, if a device has not detected a current through its current sense resistor of iRESP, the
device accepts physical address '1' and disables its response current.
After a predefined period (tPER_DISC), the master transmits another Discovery Command.
Steps 3 and 4 are repeated, with the device accepting the address in its address assignment counter if the sense current
is low.
The master repeats step 5 until it has transmitted Discovery Commands for all the devices it expects on the bus.
Device initialization can now begin using Command and Response Mode.
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Once the Discovery Mode is complete, a physical address is assigned to the device, and Command and Response Mode is used
with the assigned physical address for further configuration.
tDISC_Bittime
tPER_DISC
= iDISC_Peak
tSTART_DISC_RSP
tDISC_Ramp_RSP +tDISC_Idle_RSP
t_DISC_Ramp_RSP
Figure 39. DSI3 Discovery Mode timing diagram
4.2
DSI3 Command and Response Mode
DSI3 Command and Response Mode is the main communication method used for initialization of the device.
4.2.1
DSI3 Command and Response Mode Command reception
Command and Response Mode data packets are exchanged between a single master and a single slave. The primary purpose
of command and response transactions are to read from and write to registers within the device memory.
An example Command and Response Mode Command is shown in Figure 40. The command consists of 32 bits of data broken
up into multiple fields as described in Section 4.2.1.2.
BUS_I
CMD ED
[0] [7]
PA CMD
[0] [3]
PA
[3]
PA[3:0]
Physical Address
ED
[0]
CMD[3:0]
Command
PA3
PA2
PA1
PA0
C3
C2
C1
0
0
0
1
1
0
0
RD
[7]
RD CRC
[0] [7]
ED[7:0]
Extended Data
Register Data
C0 D15 D14 D13 D12 D11 D10 D9
0
1
0
1
0
1
0
CRC
[0]
CRC[7:0]
RD[7:0]
1
Error Checking
D8
D7
D6
D5
D4
D3
D2
D1
D0
E7
E6
E5
E4
E3
E2
E1
E0
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
1
0
Figure 40. Command and Response Mode example command
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4.2.1.1
Bit encoding
Figure 41 shows the bit encoding used for Command and Response Mode commands from the master device.
0
0
1
0 1
0
1
1
VHIGH
VLOW
Figure 41. Command and Response Mode Command bit encoding
4.2.1.2
Command message format
The Command and Response Mode Command format is shown in Table 38.
Table 38. Command and Response Mode - Command Format
Physical address
Command
Extended Data
Register Data
CRC
PA[3:0]
CMD[3:0]
ED[7:0]
RD[7:0]
CRC[7:0]
Table 39. Command and Response Mode - Field Definitions
Field
PA[3:0]
Length (bits)
4
Definition
Physical Address
Must match the value in the PADDR[3:0] of the PHYSADDR register
CMD[3:0]
4
Command (reference Section 4.2.4)
ED[7:0]
8
Extended Data (reference Section 4.2.4)
RD[7:0]
8
Register Data (reference Section 4.2.4)
CRC[7:0]
8
Error Checking (reference Section 4.2.1.3)
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4.2.1.3
Error checking
The device calculates a 8-bit CRC on the entire 32-bits of each command. Data is entered into the CRC calculator MSB first,
consistent with the transmission order of the message.
The CRC decoding procedure is:
1.
2.
3.
4.
5.
A seed value is preset into the least significant bits of the shift register.
Using a serial CRC calculation method, the receiver rotates the received message and CRC into the least significant
bits of the shift register in the order received (MSB first).
When the calculation on the last bit of the CRC is rotated into the shift register, the shift register contains the CRC check
result.
If the shift register contains all zeros, the CRC is correct.
If the shift register contains a value other than zero, the CRC is incorrect.
The CRC polynomial is specified in the C_CRMCRCPLY register. The CRC default polynomial and Seed for Command and
Response Mode are shown in Table 40.
Table 40. Command and Response Mode Command CRC
Mode
Default Polynomial
Seed
Command and Response Mode
x8 + x5 + x3 + x2 + x + 1
1111 1111
Some example CRC calculations are shown in Table 41.
Table 41. Command and Response Mode - CRC Calculation Examples
Physical Address
Command
Extended Data
Register Data
8 Bit CRC
0x01
0x08
0x11
0x86
0xB0
0x02
0x01
0x25
0xFF
0x38
0x03
0x0F
0x1A
0x41
0x2C
0x04
0x01
0x01
0x01
0xD4
4.2.2
DSI3 Command and Response Mode Response Transmission
An example Command and Response Mode Response is shown in Figure 42. The response consists of 32 bits of data broken
up into multiple fields as described in Section 4.2.2.2.
1st Symbol
Response
Current
Physical
Address
Command
PA3 PA2 PA1 PA0 C3
0
0
0
1
1
Extended Data
Register Data
Error Checking
C2
C1
C0 D15 D14 D13 D12 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
E7
E6
E5
E4
E3
E2
E1
E0
0
0
0
1
0
0
0
1
0
1
1
0
0
0
0
1
1
0
1
1
0
1
0
1
0
1
0
Figure 42. Command and Response Mode Response example
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4.2.2.1
Symbol Encoding
The device response to a Command and Response Mode Command uses multi-level source coding where data nibbles are first
encoded into symbols and then the symbols are encoded into current levels. The symbols are assembled from three consecutive
three-level current pulses called chips. Within a symbol there are three consecutive chips that can assume one of three discrete
current levels: iq, iq + iRESP, and iq + 2 x iRESP. Figure 43 shows the chip transmissions and an example of a three symbol (nine
chip), 12-bit data packet.
Response data bit encoding
Symbol
1 1 0 2
0
2
2
1
2
+2*IRESP
+IRESP
Iq_all
1st 2nd 3rd
0mA
Chips
Each symbol encodes four data bits
Figure 43. Response symbol encoding
Of the 27 possible combinations for three consecutive tri-level chips, the combinations that begin with the null current level (iq)
are discarded. Of the remaining 18 symbols, the two symbols that contain the same value for all three chips are also discarded.
The remaining 16 symbols all begin with a non-null current level and have at least one transition. These characteristics guarantee
that any response packet has a transition at the beginning of a packet and at least one transition in every symbol. Each 3-chip
symbol encodes the information of 4-bits. Table 42 shows the symbol encoding used by the device.
Table 42. Symbol mapping
Encoded Data (4 Bits)
Symbol Transmitted
Binary
HEX
1st Chip
2nd Chip
3rd Chip
0000
0
1
1
0
0001
1
2
1
1
0010
2
1
0
2
0011
3
2
0
2
0100
4
1
0
0
0101
5
2
1
2
0110
6
1
1
2
0111
7
2
0
1
1000
8
2
2
0
1001
9
2
1
0
1010
A
1
2
2
1011
B
2
2
1
1100
C
1
2
0
1101
D
2
0
0
1110
E
1
0
1
1111
F
1
2
1
where:
0 = iq
1 = iRESP
2 = 2 x iRESP
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4.2.2.2
Response Message Format
The Command and Response Mode response format is shown in Table 43.
Table 43. Command and Response Mode response format
Physical Address
Command
Register + 1 Data
Register Data
CRC
PA[3:0]
CMD[3:0]
RD1[7:0]
RD[7:0]
CRC[7:0]
Table 44. Command and Response Mode field definitions
Field
Length (Bits)
PA[3:0]
4
Definition
Physical Address
Matches the value in the PADDR[3:0] of the PHYSADDR register
CMD[3:0]
4
An echo of the received command
ED[7:0]
8
The data contained in the register addressed by RA[7:0] +1 (reference Section 4.2.4)
RD[7:0]
8
The data contained in the register addressed by RA[7:0] (reference Section 4.2.4)
CRC[7:0]
8
Error Checking (reference Section 4.2.2.3)
4.2.2.3
Error Checking
The device calculates a CRC on the entire 32-bits of each response. Data is entered into the CRC calculator MSB first, consistent
with the transmission order of the message.
The CRC Encoding procedure is:
1.
2.
3.
4.
5.
A seed value is preset into the least significant bits of the shift register.
Using a serial CRC calculation method, the transmitter rotates the transmitted message into the least significant bits of
the shift register, MSB first.
Following the transmitted message, the transmitter feeds eight zeros into the shift register, to match the length of the
CRC.
When the last zero is fed into the input adder, the shift register contains the CRC.
The CRC is transmitted.
The CRC polynomial is specified in the R_CRMCRCPLY register. The CRC default polynomial and Seed for Command and
Response Mode are shown in Table 45.
Table 45. Command and Response Mode Response CRC
Mode
Default Polynomial
Seed
Command and Response Mode
x8 + x5 + x3 + x2 + x + 1
1111 1111
Some example CRC calculations are shown in Table 41.
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4.2.3
DSI3 Command and Response Mode timing
A timing diagram for Command and Response Mode is shown in Figure 44. Timing parameters are specified in Section 2.7.
CMD_Start
32nd bit
1st bit
BUS_I
tACT_RESP
tCMD_BitTime
tDSI_POR
tSTART_CRM
VBUS_I_UV_F + VHYST
1st Symbol
tPER_CRM
24th symbol
tCHIP_CRM
Iq+ 2 x IRESP
Response
Current
Iq+ IRESP
Iq
tSLEW1_RESP
tSLEW2_RESP
Figure 44. Command and Response Mode timing diagram
4.2.4
DSI3 Command and Response Mode command summary
Table 46. DSI bus command summary
Command
Data
C3
C2
C1
C0
Hex
Description
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
$0
Register Read
RA[7]
RA[6]
RA[5]
RA[4]
RA[3]
RA[2]
RA[1]
RA[0]
0
0
0
0
0
0
0
0
0
0
0
1
$1
Not Implemented
N/A
0
0
1
0
$2
Not Implemented
N/A
0
0
1
1
$3
Not Implemented
N/A
0
1
0
0
$4
Not Implemented
N/A
0
1
0
1
$5
Not Implemented
N/A
0
1
1
0
$6
Not Implemented
N/A
0
1
1
1
$7
Not Implemented
1
0
0
0
$8
Register Write
RD[7]
RD[6]
RD[5]
RD[4]
RD[3]
RD[2]
RD[1]
RD[0]
1
0
0
1
$9
Not Implemented
N/A
1
0
1
0
$A Not Implemented
N/A
1
0
1
1
$B
0
0
0
0
0
0
0
0
1
1
0
0
$C Not Implemented
N/A
1
1
0
1
$D Not Implemented
N/A
1
1
1
0
$E Not Implemented
N/A
1
1
1
1
$F Not Implemented
N/A
Enter PDCM
N/A
RA[7]
0
RA[6]
0
RA[5]
0
RA[4]
0
RA[3]
0
RA[2]
0
RA[1]
0
RA[0]
0
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4.2.4.1
Register Read Command
The device supports the Register Read Command as a device address specific command only. If the PA[3:0] field in the
command matches the value in the PADDR[3:0] bits of the PHYSADDR register, the device responds to the command.
The device ignores the Register Read Command if the command is sent to any other physical address, including the DSI Global
Device Address of ‘0000’.
The Register Read Command uses the byte address definitions shown in Table 4. Readable registers along with their Byte
addresses are shown in Table 4. If an attempt is made to read a register that is not readable, the device will respond with all zero
data.
Table 47. Register Read Command
Address
PA3
PA2
PA1
Command
Data
PA0
C3
C2
C1
C0
PA[3] PA[2] PA[1] PA[0]
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1] RA[0]
CRC
8 bits
Table 48. Register Read Command bit definitions
Bit Field
Definition
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits in the
PHYSADDR register. Otherwise, the command is ignored.
PA[3:0]
C[3:0]
Register Read Command = ‘0000’
RA[7:0]
RA[7:0] contains the byte address of the register to be read.
Table 49. Response - Register Read Command
Address
PA3
PA2
PA1
Command
Data
PA0
C3
C2
C1
C0
PA[3] PA[2] PA[1] PA[0]
0
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RD[15] RD[14] RD[13] RD[12] RD[11] RD[10] RD[9] RD[8] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0]
CRC
8 bits
Table 50. Register Read Response Bit Definitions
Bit Field
Definition
PA[3:0]
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
C[3:0]
Register Read Command = ‘0000’
RD[15:8]
The data contained in the register addressed by RA[7:0] +1
RD[7:0]
The data contained in the register addressed by RA[7:0]
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4.2.4.2
Register Write Command
The device supports the Register Write Command as a device address specific command. If the PA[3:0] field in the command
matches the value in the PADDR[3:0] bits of the PHYSADDR register, the device will execute the register write and respond to
the command.
The device ignores the Register Write Command if the command is sent to any other physical address, including the DSI Global
Device Address of ‘0000’, with one exception as explained in Section 4.2.4.3.
The Register Write Command uses the byte address definitions shown in Table 4. Writable registers along with their Byte
addresses are shown in Table 4. If an attempt is made to write to a register that is not writable, the device will respond with all
zero data.
Table 51. Register Write Command
Address
PA3
PA2
PA1
Command
Data
PA0
C3
C2
C1
C0
PA[3] PA[2] PA[1] PA[0]
1
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RA[7] RA[6] RA[5] RA[4] RA[3] RA[2] RA[1] RA[0] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0]
CRC
8 bits
Table 52. Register Write Command bit definitions
Bit Field
Definition
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits in the
PHYSADDR register. Otherwise, the command is ignored.
PA[3:0]
C[3:0]
Register Write Command = 1000’
RA[7:0]
RA[7:0] contains the byte address of the register to be read.
RD[7:0]
RD[7:0] contains the data to be written to the register addressed by RA[7:0].
Table 53. Response - Register Write Command
Address
PA3
PA2
PA1
Command
Data
PA0
C3
C2
C1
C0
PA[3] PA[2] PA[1] PA[0]
1
0
0
0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
RD[15] RD[14] RD[13] RD[12] RD[11] RD[10] RD[9] RD[8] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0]
CRC
8 bits
Table 54. Register Write Response bit definitions
Bit Field
Definition
PA[3:0]
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
C[3:0]
Register Write Command = ‘1000’
RD[15:8]
The data contained in the register addressed by RA[7:0] +1
RD[7:0]
The data contained in the register addressed by RA[7:0] (after the register write is executed)
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4.2.4.3
Global Register Write Command to the PHYSADDR register
The device supports the Register Write Command as a global address under the following conditions:
1.
2.
The Register Write Command is written to the PHYSADDR register ($11).
The PADDR[3:0] bits of the PHYSADDR register are equal to ‘0000’ prior to the register write being executed.
If these conditions are met, the device will execute the register write and respond to the command.
Table 55. Global Register Write Command to the PHYSADDR register
Address
Command
Data
PA3
PA2
PA1
PA0
C3
C2
C1
C0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
D5
D4
D3
D2
D1
D0
RD[3] RD[2] RD[1] RD[0]
CRC
8 bits
Table 56. Register Write Command bit definitions
Bit Field
Definition
PA[3:0]
The DSI Global address of ‘0000’.
C[3:0]
Register Write Command = 1000’
RA[7:0]
RA[7:0] must be set to the PHYSADDR register address ($11)
RD[3:0]
RD[3:0] contains the new physical address for the device.
Table 57. Response - Global Register Write Command to the PHYSADDR register
Address
PA3
PA2
PA1
Command
PA0
PA[3] PA[2] PA[1] PA[0]
C3 C2 C1 C0
1
0
0
0
Data
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D3
D2
D1
D0
RD[15] RD[14] RD[13] RD[12] RD[11] RD[10] RD[9] RD[8] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0]
CRC
8 bits
Table 58. Register Write Response bit definitions
Bit Field
Definition
PA[3:0]
The new DSI physical address programmed to the PADDR[3:0] bits in the PHYSADDR register.
C[3:0]
Register Write Command = 1000’
RD[15:8]
The data contained in register by $12
RD[7:0]
The data contained in the PHYSADDR register after the register write is executed.
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4.2.4.4
Enter Periodic Data Collection Mode Command
The device supports an Enter PDCM Command as a device address specific command and as a Global Command.
If the PA[3:0] field in the command matches the value in the PADDR[3:0] bits of the PHYSADDR register, the device will set the
PDCM_EN bit in the PDCM_EN register, enter Periodic Data Collection Mode and respond to the command as shown below. If
the PA[3:0] field in the command matches the Global address of ‘0000’, the device will set the PDCM_EN bit in the PDCM_EN
register and enter Periodic Data Collection Mode. No response is transmitted for a global command. The device ignores the Enter
PDCM command if the command is sent to any other physical address.
Table 59. Enter Periodic Data Collection Mode Command
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
C3
C2
C1
PA[3] PA[2] PA[1] PA[0]
1
0
1
C0 D15 D14 D13 D12 D11 D10 D9
1
0
0
0
0
0
0
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
8 bits
Table 60. Enter Periodic Data Collection Mode Command bit definitions
Bit Field
Definition
PA[3:0]
DSI physical address. This field contains the physical address. This field must match the PADDR[3:0] bits in the
PHYSADDR register or the Global Address of ‘0000’. Otherwise, the command is ignored.
C[3:0]
Enter PDCM Command = 1011’
Table 61. Response - Enter Periodic Data Collection Mode Command
Address
Command
Data
CRC
PA3 PA2 PA1 PA0
C3
C2
C1
PA[3] PA[2] PA[1] PA[0]
1
0
1
C0 D15 D14 D13 D12 D11 D10
1
0
0
0
0
0
D9
D8
Ch[2] Ch[1] Ch[0]
D7 D6 D5 D4 D3 D2 D1 D0
1
0
0
0
0
0
0
0
8 bits
Table 62. Enter Periodic Data Collection Mode Response bit definitions
Bit Field
Definition
PA[3:0]
DSI physical address. This field contains the PADDR[3:0] bits in the PHYSADDR register.
Ch[2:0]
CHIPTIME[2:0] in the CHIPTIME register
C[3:0]
Register Write Command = ‘1000’
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4.3
DSI3 Periodic Data Collection Mode and Background Diagnostic Mode
When the PDCM_EN bit in the PDCM_EN register is set, Periodic Data Collection Mode is enabled. If the BDM_EN bit in the
BDM_CFG register is also set, the optional Background Diagnostic Mode is also enabled.
4.3.1
DSI3 Periodic Data Collection Mode and Background Diagnostic Mode Command
Reception
When Periodic Data Collection Mode is enabled, the device will decode the DSI3 Broadcast Read command as well as
Background Diagnostic Mode command fragments as described below.
4.3.1.1
Bit Encoding
The Command Bit encoding for Periodic Data Collection Mode and Background Diagnostic Mode is the same as the bit encoding
for Command and Response Mode, as described in Section 4.2.1.1.
4.3.1.2
Command Message Format
The command message format for Periodic Data Collection Mode and Background Diagnostic Mode is the same as the
command message format for Command and Response Mode, as described in Section 4.2.1.2.
If Background Diagnostic Mode is disabled, then the device responds with the Periodic Data Collection Mode response only if
the command is the single bit Broadcast Read Command. A Broadcast Read Command may be either a ‘1’ or a ‘0’.
If Background Diagnostic Mode is enabled:
•
Background Diagnostic Mode commands are transmitted and decoded in 4-bit fragments.
•
The device responds with the Periodic Data Collection Mode response if and only if the command is a Broadcast Read
Command or a 4-bit command fragment.
•
A Broadcast Read Command or any command length other than four bits resets the Background Diagnostic Mode command
decode.
•
The device responds with a Background Diagnostic Mode response only when eight consecutive 4-bit command fragments
are received and the decoded command is a valid Command and Response Mode command.
Refer to Section 4.3.4 for additional details on Background Diagnostic Mode timing.
4.3.1.3
Error checking
The error checking for Background Diagnostic Mode commands is the same as the error checking for Command and Response
Mode, and described in Section 4.2.1.3.
No error checking is employed for the Broadcast Read commands.
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4.3.2
DSI3 Periodic Data Collection Mode response transmission
When Periodic Data Collection Mode is enabled and the device receives either a Broadcast Read or Background Diagnostic
Mode command, the device will respond with periodic data as shown in Figure 45 and described in the following sections.
BUS_I
Slave A
Slave C
Slave B
Response
Current
PDCM_RSPST[11:0] on Slave A device
PDCM_RSPST[11:0] on Slave B device
PDCM_RSPST[11:0] on Slave C device
tPER_PDCM
tCmdBlock_PDCM
Command blocking time is independently
programmed in each slave.
tCmdBlock_ST_PDCM
Command
Block
Figure 45. Periodic Data Collection Mode response transmission
4.3.2.1
Symbol encoding
The symbol encoding used for Periodic Data Collection Mode responses is the same as for Command and Response Mode
responses, and described in Section 4.2.2.1.
4.3.2.2
Response message format
The Periodic Data Collection Mode response format is shown in Table 63.
Table 63. Periodic Data Collection Mode - response format
Source ID
Keep Alive Counter
Status
Acceleration Data
CRC
SOURCID[3:0]
KAC[1:0]
S[x:0]
D[x:0]
CRC[7:0]
Table 64. Periodic Data Collection Mode Response field definitions
Field
Length (Bits)
SOURCID[3:0]
4
Transmits the least significant 4 bits of the SOURCEID register
KAC[1:0]
2
Transmits the value of a 2-bit rolling counter. The counter is incremented each time a valid Broadcast Read
Command is received or a valid Background Diagnostic Mode command is received. The counter does
not increment for Command and Response Mode commands or for invalid commands.
S[3:0]
STATLEN = 0: 4
STATLEN = 1: 0
D[x:0]
CRC[7:0]
Definition
Reference Table 65.
DATALEN = 0: 10
Transmits the value in the ACC1_D[15:0] registers as defined in Section 3.1.15.1.
DATALEN = 1, 14
8
Transmits an 8-bit CRC as defined in Section 4.3.2.3
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The status bit messages and message priority are listed in Table 65. Reference Section 5 for details on exception handling.
Table 65. Periodic Data Collection Mode Status field definitions
s[3:0]
Description
DEVSTAT State
Error
Priority
Acceleration Data Field Value
0
0
0
0
Normal mode
N/A
NA
Acceleration Data
0
0
0
1
Offset Error
OFFSET_ERR set
4
Acceleration Data
0
0
1
0
Freescale OTP Array Error
F_OTP_ERR set
1
Error Code
0
0
1
1
User OTP Array Error
U_OTP_ERR set
2
Error Code
0
1
0
0
User Read/Write Array
Error
U_RW_ERR set
3
Error Code
0
1
0
1
Reserved
N/A
8
Acceleration Data
0
1
1
0
Reserved
N/A
9
Acceleration Data
0
1
1
1
Oscillator Training Error
OSCTRAIN_ERR set
6
Acceleration Data
ST_INCMPLT set
5
Acceleration Data
1
0
0
0
Self-test Activation
Incomplete
1
0
0
1
Reserved
N/A
7
Acceleration Data
1
0
1
0
Reserved
N/A
10
Acceleration Data
1
0
1
1
Reserved
N/A
11
Acceleration Data
1
1
0
0
Reserved
N/A
12
Acceleration Data
1
1
0
1
Reserved
N/A
13
Acceleration Data
1
1
1
0
Reserved
N/A
14
Acceleration Data
1
1
1
1
Test mode active
TESTMODE set
15
Error Code
4.3.2.3
Error checking
The device calculates a CRC on the entire response. Data is entered into the CRC calculator MSB first, consistent with the
transmission order of the message.
The CRC Encoding procedure is:
1.
2.
3.
4.
5.
A seed value is preset into the least significant bits of the shift register.
Using a serial CRC calculation method, the transmitter rotates the transmitted message into the least significant bits of
the shift register, MSB first.
Following the transmitted message, the transmitter feeds eight zeros into the shift register, to match the length of the
CRC.
When the last zero is fed into the input adder, the shift register contains the CRC.
The CRC is transmitted.
The CRC polynomial is specified in the PDCMCRCPLY register. The CRC default polynomial and Seed for Command and
Response Mode are shown in Table 66.
Table 66. Periodic Data Collection Mode Response CRC
Mode
Default Polynomial
8
Periodic Data Collection Mode
5
3
Seed
2
x +x +x +x +x+1
SOURCEID[7:0]
Some example CRC calculations are shown in Table 67.
Table 67. Periodic Data Collection Mode - CRC Calculation Examples
Source Identification
(4 Bits)
Keep Alive Counter
(2 Bits)
Status (4 Bits)
Acceleration Data
(10 Bits)
8-bit CRC
0x1
0x3
0x0
0x1FF
0xD6
0x2
0x2
0x0
0x1FE
0x70
0x3
0x1
0x0
0x20D
0xB0
0x4
0x0
0x0
0x1EA
0x5F
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4.3.3
DSI3 Periodic Data Collection Mode timing
A timing diagram for Periodic Data Collection Mode is shown in Figure 46. Timing parameters are specified in Section 2.7.
CMD_Start
BUS_I
tCMD_BitTime
tSTART_PDCM
1st Symbol
tPER_PDCM
24th symbol
tCHIP_PDCM
Iq+ 2 x IRESP
Response
Current
Iq+ IRESP
Iq
tSLEW1_RESP
tSLEW2_RESP
Figure 46. Periodic Data Collection Mode Timing Diagram
4.3.4
4.3.4.1
Background Diagnostic Mode Response Transmission
Symbol Encoding
The Background Diagnostic Mode response symbol encoding is the same as the symbol encoding used for Command and
Response Mode responses and is described in Section 4.2.2.1.
4.3.4.2
Response Message Format
The Background Diagnostic Mode response message format is the same as the format used for Command and Response Mode
responses and is described in Section 4.2.2.1.
•
If a complete 32-bit command is received and decoded to a valid Command and Response Mode command the device
provides a Background Diagnostic Mode response.
•
Responses are initiated by the master transmitting 1 bit Broadcast Read Commands following a completed Background
Diagnostic Mode command transmission.
•
Responses are transmitted in one symbol fragments following the 1-bit Broadcast Read Command, using the same timing
window within the frame that the Background Diagnostic Mode Command used.
•
Responses are transmitted if and only if Broadcast Read Commands are received.
•
Eight consecutive Broadcast Read Commands are required following a valid Background Diagnostic Mode command to
complete a response transmission.
•
If any command other than the Broadcast Read Command is received, no response is transmitted and the remainder of the
Broadcast Read Command response is terminated.
•
The data to be transmitted in the response is latched just before the first symbol of the Background Diagnostic Mode
response.
Reference Figure 47 for Background Diagnostic Mode timing.
4.3.4.3
Error Checking
The error checking for Background Diagnostic Mode responses is the same as used for Command and Response Mode, and
described in Section 4.2.1.3.
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4.3.5
DSI3 Background Diagnostic Mode Timing
A timing diagram for Background Diagnostic Mode is shown in Figure 47. Timing parameters are specified in Section 2.7.
CMD_Start
PA[3:0]
CMD[3:0]
tSTART_PDCM
CRC[3:0]
ED[7:3]
Broadcast Read
Broadcast Read
0
1
BDM Response Data Latched
tSTART_BDM
1-2-1
1-2-0
Figure 47. Background Diagnostic Mode Timing Diagram
4.3.6
DSI3 Periodic Data Collection Mode and Background Diagnostic Mode Command
Summary
When Periodic Data Collection Mode is enabled, the Background Diagnostic Mode supports the Register Read command as
described in the Command and Response Mode command summary, Section 4.2.4.1. The Register Write command is not
supported in Background Diagnostic Mode.
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4.4
Maximum number of devices on a network
The theoretical maximum number of devices on a DSI3 network is 16: 1 master and 15 slaves. The practical limit for the number
of devices on a bus is dependent on the minimum common capability of the devices on the bus. The capability of the device is
different depending on the bus configuration and operating mode. The impact of the device capability on the practical limit for the
number of devices on the network is described in this section.
4.4.1
Preconfigured, Parallel Connected Network
The number of devices in a preconfigured, parallel connected network is not directly limited by the capability of the device. The
practical limit is determined by a combination of the following:
•
The capability of the master device, including, but not limited to:
— The bus operating voltage
—
The bus supply current
—
The bus current limit
— The bit rate
— The response current detection capability (distinguishing response current from quiescent current)
•
The total quiescent current of all slaves on the network.
4.4.2
Bus switch connected daisy-chain network
The number of devices in a bus switch connected daisy-chain network is not directly limited by the capability of the device. The
practical limit is determined by a combination of the following:
•
The capability of the master device, including, but not limited to:
— The bus operating voltage
—
The bus supply current
—
The bus current limit
— The bit rate
— The response current detection capability (distinguishing response current from quiescent current)
•
The total quiescent current of all slaves on the network.
•
The current handling capability and resulting voltage drop of the external bus switches in the network.
4.4.3
Resistor connected daisy-chain network using Discovery Mode
The number of devices in a resistor connected daisy-chain network is limited by the capability of the device. The maximum
number of equivalent devices connected to the BUS_O pin of the device is three. This is limited by the total quiescent current
drawn from the BUS_O pin during Discovery Mode (IBUS_O_q).
The practical limit is determined by a combination of the above restriction and the following:
•
The capability of the master device, including, but not limited to:
— The bus operating voltage
—
The bus supply current
—
The bus current limit
— The bit rate
— The response current detection capability (distinguishing response current from quiescent current)
•
The total quiescent current of all slaves on the network.
•
The maximum allowed quiescent current drawn from the BUS_O pin of other slaves in the system.
•
The resulting voltage drop of the Discovery Mode resistors in all slaves in the network.
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5
Exception Handling
Table 68 summarizes the exception conditions detected by the device and the response for each exception.
Table 68. Exception handling
Condition
Description
Device Response
Exception
PDCM_EN
Power On
Reset
N/A
Power Applied
VBUS_I
Undervoltage
N/A
VBUS_I < VBUS_I_UV_F
• Response Current Deactivated.
• BUSI_UV_ERR set.
• The device reacts to all DSI commands but no response current is activated.
VBUF
Undervoltage
N/A
VBUF < VBUF_UV_F
• Response Current Deactivated.
• VBUF_UV_ERR set.
• The device reacts to all DSI commands but no response current is activated.
VREG < VREG_UV_F
•
•
•
•
The device is held in Reset.
No response to DSI commands.
If activated, BUSSW is deactivated within tBS_OFF.
The device must be re-initialized when VREG returns above VPORCREG_r .
VREGA < VREGA_UV_F
•
•
•
•
The device is held in Reset.
No response to DSI commands.
If activated, BUSSW is deactivated within tBS_OFF.
The device must be re-initialized when VREGA returns above VPORCREGA_r .
VREG
Undervoltage
VREGA
Undervoltage
N/A
N/A
• Reference Section 3.8.
• ST_INCMPLT Bit Set, PDCM S[3:0] = ‘1000’.
N/A
• The device is reset and will continue to be reset every tPOR_CAPTEST until the
capacitor failure is removed.
• No response to DSI commands.
• If activated, BUSSW is deactivated within tBS_OFF.
• The device must be re-initialized when the capacitor failure is removed.
N/A
• The device is reset and will continue to be reset every tPOR_CAPTEST until the
capacitor failure is removed.
• No response to DSI commands.
• If activated, BUSSW is deactivated within tBS_OFF.
• The device must be re-initialized when the capacitor failure is removed.
VREGA
Capacitor Test
Failure
N/A
• The device is reset and will continue to be reset every tPOR_CAPTEST until the
capacitor failure is removed.
• No response to DSI commands.
• If activated, BUSSW is deactivated within tBS_OFF.
• The device must be re-initialized when the capacitor failure is removed.
OTP CRC Fault
(Factory Array)
N/A
OTP CRC Fault
(User Array)
N/A
VBUF Capacitor
Test Failure
VREGCapacitor
Test Failure
0
User R/W Array
CRC Fault
Self-test
Activated
Self-test Never
Activated after
POR
1
Error detected in factoryprogrammed OTP array.
• Periodic Data Collection Mode response data set to error response.
• PDCM S[3:0] = ‘0010’).
Error detected in User
• Periodic Data Collection Mode response data set to error response.
programmed OTP array and • PDCM S[3:0] = ‘0011’).
the LOCK_U bit is set.
N/A
N/A
Error detected in user read • Periodic Data Collection Mode response data set to error response.
write registers and the
• PDCM S[3:0] = ‘0100’).
PDCM_EN bit is set.
0
ST activated during
initialization
1
ST activated in Periodic
Data Collection Mode
0
In initialization, before
Self-test
1
In PDCM, Self-test
incomplete
• Internal self-test circuitry enabled.
• Self-test Activation Incomplete status cleared.
• Acceleration Data Registers (ACC_DATAL, ACC_DATAH) contain self-test active
data.
• Periodic Data Collection Mode acceleration response data normal.
• Self-test Activation ignored.
• Normal Responses to Command and Response Mode.
• Periodic Data Collection Mode acceleration response data normal.
• ST_INCMPLT bit set, PDCM S[3:0] = ‘1000’.
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Recommended Footprint
Reference Freescale Application Note AN3111, latest revision:
http://www.freescale.com/files/sensors/doc/app_note/AN3111.pdf
Reference Freescale Application Note AN4530, latest revision:
http://www.freescale.com/files/sensors/doc/app_note/AN4530.pdf
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7
Package Dimensions
CASE 2086-01
ISSUE C
16 LEAD QFN
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CASE 2086-01
ISSUE C
16 LEAD QFN
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CASE 2086-01
ISSUE C
16 LEAD QFN
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Revision History
Table 69. Revision history
Revision
number
Revision
date
0
10/2012
• Initial release.
04/2013
• Deleted “J” versions of devices and Silicon rev. column on ordering information table. Added Rail options to table.
• Figure 3: Added C6 capacitor between BUSRTN and BUSOUTDC.
• Table 2: Added additional information for description of C1. Added C6 capacitor description. Added additional
information for description of C1.
• Figure 5: Deleted (J) from the marking diagram.
• Section 2.4: Electrical characteristics - Sensor and Signal Chain table: Deleted “trimmed with a...” sentence from
lines 57-66.
• Section 2.5: Electrical characteristics - Self-test and Overload table: Deleted lines 99 and 100 characteristics for
“J” versions of device.
• Section 2.6: Dynamic electrical characteristics - DSI3: Updated Typ values for lines 106, 111, 118, 120-126, 128,
130, 132-136, 140-142, 144, and 147-150. Updated Min and Max values for lines 139, 143, 145, 146, and 150.
• Section 2.7: Dynamic electrical characteristics - signal chain: Added x-pole description to Cutoff frequency lines.
Deleted lines for “Filter order LPFx” and “Filter order, startup Phase x”. Updated Typ values for lines 161, 163,
166, 168, and 178.
• Section 2.7: Dynamic electrical characteristics - supply and support circuitry: Deleted line Oscillator cycles in
training time row, Updated Min, Typ and Max values for lines 199-201 and Min values for lines 208 and 209.
• Deleted Section 2.9.
• Table 33: Updated Typical Block Latency column values.
• Table 34: Updated Group Delay column values.
• Replaced paragraph for Section 4.3.
0.5
Description of changes
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Document Number: MMA27XXW
Rev. 0.5
4/2013
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