Data Sheet

Document Number: MMA690xKQ
Rev. 5, 08/2012
Freescale Semiconductor
Data Sheet: Technical Data
High Accuracy Low g Inertial Sensor
MEMS Sensing, State Machine ASIC
MMA690xKQ
The MMA690xKQ, a SafeAssure solution, is a dual axis, Low g, XY, Sensor
based on Freescale’s HARMEMS technology, with an embedded DSP ASIC,
allowing for additional processing of the digital signals.
Features
Sensitivity in X and Y axes
±3.5 or ±5.0g full-scale range per axis
AEC-Q100 qualified, Rev. F, grade 2 (-40 ≤ TA ≤ 105°C)
50 Hz second order low-pass filter
Unsigned 11-bits digital data output
SPI-compatible serial interface
Capture/hold input for system-wide synchronization support
3.3 or 5.0V single supply operation
On-chip temperature sensor and voltage regulator
Bi-directional internal self-test
Minimal external component requirements
Pb-free 16-pin QFN package
Pulse-code modulated output available for device evaluation
DUAL AXIS SPI
INERTIAL SENSOR
Bottom View
16-PIN QFN
98ASA10571D
CASE 1477-02
Typical Applications
VSSA
PCM_X
•
•
With a ±3.5g or ±5.0g full scale range, the newly designed, high accuracy
sensor, enables Electronic Stability Control (ESC) designers to
accommodate higher original signal noise level without sacrificing resolution.
Tilt Measurement
Electronic Parking Brake
CREGA
•
Top View
CREGA
•
•
•
•
•
•
•
•
•
•
•
•
•
16 15 14 13
CREF 1
ORDERING INFORMATION
MMA6901KQ
±5.0g
MMA6900KQR2
±3.5g
MMA6901KQR2
±5.0g
9 VPP
5
Tubes
6
7
8
CREG
±3.5g
VSS 4
SCLK
MMA6900KQ
Shipping
CS/RESET
Range
11 CAP/HOLD
10 DIN
VCC 3
DOUT
Device Name
12 PCM_Y
CREF 2
Tape and Reel
© 2010-2012 Freescale Semiconductor, Inc. All rights reserved.
PIN CONNECTIONS
SECTION 1 INTRODUCTION
1.1
INTRODUCTION
MMA690xKQ is a two-axis member of Freescale’s family of SPI-compatible accelerometers. These devices incorporate digital
signal processing for filtering, trim, and data formatting.
1.2
SERIAL COMMUNICATION CONFIGURATION
The serial communication configuration provides a 4-wire SPI interface. Device serial number, acceleration range, filter characteristics, and status information are available along with acceleration data via the SPI.
1.3
BLOCK DIAGRAM
A block diagram illustrating the major components of the design is shown in Figure 1-1.
VPP
UNIT
PROGRAMMABLE
DATA ARRAY
VCC
CREG
CREGA
CREGA
VOLTAGE
REGULATOR
REFERENCE
OSCILLATOR
CLOCK
MONITOR
PRIMARY
OSCILLATOR
INTERNAL
CLOCK
CREF
CREF
DIN
VSS
SPI
CONTROL
LOGIC
VSSA
DOUT
SCLK
CS
CAP/HOLD
g-CELL
(Y)
ΣΔ
CONVERTER
SINC
FILTER
CONTROL
IN
IN 1
SELF-TEST
INTERFACE
TEMP.
SENSOR
TEMP
STATUS
OUT
DIGITAL
OUT
DSP
(SEE FIGURE 1-2)
Y OUT
PCM
PCM_Y
X OUT
PCM
PCM_X
IN 0
g-CELL
(X)
ΣΔ
CONVERTER
SINC
FILTER
Figure 1-1 Block Diagram
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DSP
CONTROL
CONTROL
IN
IN 1
IN 0
LOW-PASS
FILTER
STATUS
OUT
OFFSET,
GAIN,
LINEARITY
ADJUST
OUTPUT
SCALING
DIGITAL
OUT
TEMP
Figure 1-2 DSP Block Diagram
1.4
PIN FUNCTIONS
The pinout is illustrated in Figure 1-3. Pin functions are described in the following paragraphs. When self-test is active, the
output becomes more positive in both axes, if ST1 is cleared or more negative in both axes if ST1 is set, as described in
Section 2.1.3.
VSSA
PCM_X
CREGA
CREGA
X: +1g
Y: 0g
16 15 14 13
CREF 1
12 PCM_Y
CREF 2
VSS 4
9 VPP
5
6
7
8
CREG
10 DIN
CS/RESET
TO CENTER OF
GRAVITATIONAL FIELD
11 CAP/HOLD
VCC 3
SCLK
X: 0g
Y: -1g
DOUT
X: 0g
Y: +1g
X: -1g
Y: 0g
Response to static orientation within 1g field.
TOP VIEW
16-PIN QFN PACKAGE
Figure 1-3 Pinout for MMA690xKQ
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1.4.1
VCC
This pin supplies power to the device. Careful printed wiring board layout and capacitor placement is critical to ensure best
performance. An external bypass capacitor between this pin and VSS is required, as described in Section 1.5.
1.4.2
VSS
This pin is the power supply return node for the digital circuitry on the MMA690xKQ device.
1.4.3
VSSA
This pin is the power supply return node for analog circuitry on the MMA690xKQ device. An external bypass capacitor between
this pin and VCC is required, as described in Section 1.5.
1.4.4
CREG
This pin is connected to the internal digital circuitry power supply rail. An external filter capacitor must be connected between
this pin and VSS, as described in Section 1.5.
1.4.5
CREGA
These pins are connected in parallel to the internal analog circuitry power supply rail. One or two external filter capacitors must
be connected between these pins and VSSA, as described in Section 1.5. Two pins are provided to support redundant connection
to the printed wiring board assembly. Redundant external capacitors may be connected to these pins for maximum reliability, as
described in Section 1.5.
1.4.6
CREF
These pins are connected in parallel to an internal reference voltage node utilized by the analog circuitry. One or two external
filter capacitors must be connected between these pins and VSSA, as described shown in Section 1.5. Two pins are provided to
support redundant connection to the printed wiring board assembly. Redundant external capacitors may be connected to these
pins for maximum reliability, as described in Section 1.5.
1.4.7
VPP
This pin should be tied directly to VSS. An internal pull-down device is connected to this pin to reduce the risk of unpredictable
device operation in the event that the connection to VSS opens.
1.4.8
SCLK
This input pin provides the serial clock to the SPI port. The state of this pin is also used as a qualifier for externally-controlled
reset. This input may be used to initiate device reset as described in Section 1.4.9 and Section 2.6. An internal pull-down device
is connected to this pin.
1.4.9
CS/RESET
This pin functions as the chip select input for the SPI port. The state of the DIN pin during low-to-high transitions of SCLK is
latched internally and DOUT is enabled when CS is at a logic low level.
This pin may also be used to initiate a hardware reset. If CS is held low and SCLK is held high for 512 μs, the internal reset
signal is asserted. This behavior is described in Section 2.6.
An internal pull-up device is connected to this pin.
1.4.10
DOUT
This pin functions as the serial data output for the SPI port. SPI data transmitted on DOUT will have an odd number of logic ‘1’
bits set during normal 16-bit transfer, unless an internal oscillator fault condition has been detected. If an internal oscillator fault
condition is present, DOUT is driven to a logic high level continuously when CS/RESET is asserted.
1.4.11
DIN
This pin functions as the serial data input to the SPI port. An internal pull-down device is connected to this pin. SPI data received at DIN must observe odd parity or a transient exception condition will be reported during the subsequent transfer.
1.4.12
CAP/HOLD
When this input pin is low, the SPI acceleration result registers are updated by the DSP whenever a data sample becomes
available. Upon a low-to-high transition of CAP/HOLD, the contents of the acceleration result registers are frozen. The result registers will not be updated so long as this pin remains at a logic ‘1’ level. This pin may be tied directly to VSS if the hold function is
not desired.
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An internal pulldown device is connected to this pin, however it is recommended that CAP/HOLD either be driven by a logic
output or tied to VSS in application circuits. If CAP/HOLD is at logic level ‘1’ during initial startup and through the release of internal
reset, the result register will be 0 counts, which is a reserved result, and should be discarded by the application. This state is
exited by the next high-to-low transition of CAP/HOLD.
1.4.13
PCM_X, PCM_Y
MMA690xKQ provides the option for a Pulse Code Modulated (PCM) output function. The PCM output is activated when
PCM_EN is set in the DEVCTL register. When the PCM function is enabled, the upper nine bits of the 11-bit scaled acceleration
values are used to generate PCM signals proportional to incident respective acceleration, at 250 ns resolution. A simplified block
diagram of the PCM output is shown in Figure 1-4.
OUTPUT SCALING
OC[9:1]
9
A
CARRY
PCM_X/PCM_Y
9-BIT ADDER
9
B
SUM
D
fCLK = 4.0 MHz
D
Q
Q
Q
DFF
Q
D FF
Q
D FF
Q
D FF
Q
DFF
Q
CLK
D
Q
FF
CLK
CLK
FF
CLK
FF
CLK
FF
CLK
CLK
CLK
CLK
D
9
Figure 1-4 PCM Output Function Block Diagram
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1.5
EXTERNAL COMPONENTS
The connections illustrated in Figure 1-5 are recommended. Careful printed wiring board layout and component placement is
essential for best performance. Low ESR capacitors must be connected to CREG and CREGA pins for best performance. A grounded land area with solder mask should be placed under the package for improved shielding of the device from external effects. If
a land area is not provided, no signals should be routed beneath the package.
VCC
MMA690xKQ
VCC
CREG
CREGA
CREGA
CREF
100 nF
1.0 μF
1.0 μF
1.0 μF
100 nF
100 nF
CREF
VSSA
VSS
RECOMMENDED EXTERNAL COMPONENT CONFIGURATION
VCC
MMA690xKQ
VCC
CREG
CREGA
CREGA
CREF
CREF
100 nF
1 μF
1 μF
100 nF
VSSA
VSS
ALTERNATE EXTERNAL COMPONENT CONFIGURATION
Figure 1-5 External Components
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SECTION 2 INTERNAL MODULES
2.1
DATA ARRAY
A 400-bit data array allows each device to be customized. The array interface incorporates parity circuitry for fault detection
along with a locking mechanism, to prevent unintended changes. Portions of the array are reserved for factory-programmed trim
values. Customer accessible data stored in the array are shown in the Table 2-1.
Addresses $00 - $0D are associated with the data array. A writable register at address $0E is provided for device control
operations. Two read-only registers at addresses $0F and $10 provide status information.
Unused bits within the data array are always read as ‘0’ values. Unprogrammed OTP bits are also read as ‘0’ values.
Table 2-1. DSP Configuration Register
Location
Bit Function
Type
Addr
Register
7
6
5
4
3
2
1
0
$00
SN0
SN[7]
SN[6]
SN[5]
SN[4]
SN[3]
SN[2]
SN[1]
SN[0]
$01
SN1
SN[15]
SN[14]
SN[13]
SN[12]
SN[11]
SN[10]
SN[9]
SN[8]
$02
SN2
SN[23]
SN[22]
SN[21]
SN[20]
SN[19]
SN[18]
SN[17]
SN[16]
$03
SN3
SN[31]
SN[30]
SN[29]
SN[28]
SN[27]
SN[26]
SN[25]
SN[24]
$04
DEVCFG0
0
0
0
0
RNG[3]
RNG[2]
RNG[1]
RNG[0]
$05
DEVCFG1
0
0
0
0
RNG[3]
RNG[2]
RNG[1]
RNG[0]
$06
DEVCFG2
0
0
0
0
0
0
0
0
$07
DEVCFG3
0
0
0
0
0
0
0
0
$08
DEVCFG4
0
0
0
0
0
0
0
0
$09
DEVCFG5
1
0
1
0
0
0
0
0
$0A
AXCFG_X
1
0
0
1
0
1
0
1
$0B
AXCFG_Y
1
0
0
1
0
1
0
1
F/R
F/R
F/R
$0C
Unused
N/A
$0D
DSPCFG
0
0
1
0
0
1
0
0
F/R
$0E
DEVCTL
RES_1
RES_0
CE
PCM_EN
HPFB
YINV
ST1
ST0
R/W
$0F
TEMP
TEMP[7]
TEMP[6]
TEMP[5]
TEMP[4]
TEMP[3]
TEMP[2]
TEMP[1]
TEMP[0]
$10
DEVSTAT
IDE
OSCF
DEVINIT
TF
0
0
0
DEVRES
$11
COUNT
COUNT[7]
COUNT[6]
COUNT[5]
COUNT[4]
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
$24
ACC_X11L
ACC_X[7]
ACC_X[6]
ACC_X[5]
ACC_X[4]
ACC_X[3]
ACC_X[2]
ACC_X[1]
ACC_X[0]
$25
ACC_X11H
0
0
0
0
0
ACC_X[10]
ACC_X[9]
ACC_X[8]
$26
ACC_Y11L
ACC_Y[7]
ACC_Y[6]
ACC_Y[5]
ACC_Y[4]
ACC_Y[3]
ACC_Y[2]
ACC_Y[1]
ACC_Y[0]
$27
ACC_Y11H
0
0
0
0
0
ACC_Y[10]
ACC_Y[9]
ACC_Y[8]
F: Factory programmed OTP location
R: Read-only register
R/W: Read/write register
R
N/A: Not applicable
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2.1.1
Device Serial Number
A unique serial number is programmed into each device during manufacturing. The serial number is composed of the following
information.
Table 2-2. Serial Number Assignment
Bit Function
Bit Range
Content
SN12 - SN0
Serial Number
SN31 - SN13
Lot Number
Lot numbers begin at 1 for all devices produced and are sequentially assigned. Serial numbers begin at 1 for each lot, and are
sequentially assigned. No lot will contain more devices than can be uniquely identified by the 13-bit serial number. Not all allowable lot numbers and serial numbers will be assigned.
2.1.2
Full-Scale Range
Full-scale range is indicated by the value programmed into DEVCFG0 and DEVCFG1. Ranges for defined part numbers are
shown in Table 2-3 below.
Table 2-3. Full-Scale Range
Range Bits
Part Number
RNG[3]
RNG[2]
RNG[1]
RNG[0]
Full-Scale Range
(g)
0
0
0
0
3.5
Register
MMA6900KQ
DEVCFG0
DEVCFG1
0
0
0
0
3.5
MMA6901KQ
DEVCFG0
0
1
0
1
5.0
DEVCFG1
0
1
0
1
5.0
2.1.3
Device Control Register (DEVCTL)
A read-write register at address $0E supports a number of device control operations as described in the following. Reserved
bits within DEVCTL are always read as logic ‘0’ values.
Write operations involving DEVCTL are effective approximately 1.0 μs following negation of CS/RESET. This delay must be
considered if successive SPI operations involving write to DEVCTL followed by acceleration data read are conducted in the minimum allowed transfer timing, as the acceleration result may indicate lingering self-test or error status conditions. It is therefore
recommended that acceleration data read operations be delayed by at least 1.2 μs following writes to DEVCTL.
Table 2-4. Device Control Register
Bit
Address
Register
$0E
DEVCTL
2.1.3.1
7
6
5
4
3
2
1
0
RES1
RES0
CE
PCM_EN
HPFB
YINV
ST1
ST0
Reset Control (RES_1, RES_0)
A specific series of three write operations involving these two bits will cause the internal digital circuitry to be reset. The state
of the remaining bits in the DEVCTL register do not affect the reset sequence, however any write operation involving this register
in which both RES_1 and RES_0 are cleared will terminate the sequence.
To reset the internal digital circuitry, the following register write operations must be performed in the order shown:
1. Set RES1. RES0 must remain cleared.
2. Set RES1 and RES0.
3. Clear RES1 and set RES0.
RES1 and RES0 are always read as logic ‘0’ values.
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2.1.3.2
Clear Error (CE)
Setting this bit to a logic ‘1’ state will clear transient error status conditions. It is necessary to either set this bit or perform a
device reset if an error condition has been reported by the device before acceleration data transfer can be resumed. The device
reset condition may be cleared only after device initialization has completed.
Error conditions and classification are described in Section 3.1.
The state of this bit is always read as logic ‘0’.
2.1.3.3
PCM Enable (PCM_EN)
This bit controls the PCM_X and PCM_Y outputs along with internal circuitry which generates a pulse-code modulated signal
from the acceleration result. When this bit is set, the PCM outputs are enabled. When cleared, PCM_X and PCM_Y are driven
to a logic low level.
2.1.3.4
High-pass Filter Bypass (HPFB)
The high-pass filter is disabled through factory settings, therefore writing this bit will have no effect. If read, this bit will be “0”.
2.1.3.5
Y-Axis Signal Inversion Control (YINV)
This control function is provided as a means to verify operation of the two-channel multiplexor which alternately provides
X-axis and Y-axis data to the DSP. An inverter block and multiplexor at the Y-axis input to the DSP are controlled by the YINV bit.
Setting this bit when ST0 is set has the effect of changing the sign of acceleration in the Y-axis. Operation of the YINV bit is
illustrated in Figure 2-1. Y-axis inversion may be selected only during self-test; the state of this bit has no effect when ST0 is
cleared.
ST0
YINV
DSP
1
ΣΔ
SINC
FILTER
ΣΔ
SINC
FILTER
Y-AXIS CONVERTER
X-AXIS CONVERTER
0
Figure 2-1 Y-Axis Inversion Function
Self-test operations controlled by YINV along with ST1 and ST0 are summarized in the Table 2-5.
2.1.3.6
Self-test Control (ST1, ST0)
Bidirectional self-test control is provided through manipulation of these bits. ST1 controls direction while ST0 enables and disables the self-test circuitry. ST1 and ST0 are always cleared following internal reset. When ST0 is set, the high-pass filter is bypassed and the values within the high-pass filter are frozen. Both axes are affected simultaneously by the state of these bits. If
the offset monitor is enabled, self-test activation in a single direction should be limited to less than 30 ms.
Communications Protocol bits S2 - S1 are inverted when self-test is activated, as described in Section 3.2.
Table 2-5. Self-Test Control Operations
Self-Test Operation
YINV
ST1
ST0
X-Axis
Y-Axis
X
X
0
Self-test Disabled, Y-Axis Signal Inversion Disabled
0
0
1
Positive Deflection
0
1
1
Negative Deflection
1
0
1
Positive Deflection
Negative Deflection
1
1
1
Negative Deflection
Positive Deflection
Offset correction is applied within the DSP, and is not affected by the state of the YINV bit. Consequently, inversion of the
Y-axis signal may result in saturation of the Y-axis output value.
Correct operation of the DSP input multiplexor may be confirmed by performing the operations shown in Figure 2-2.
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YINV = 0, ST1 = 0, ST0 = 1
READ ACCELERATION (R1)
YINV = 0, ST1 = 1, ST0 = 1
READ ACCELERATION (R2)
N
R 1 > R2
Y
YINV = 1, ST1 = 0, ST0 = 1
READ ACCELERATION (R3)
YINV = 1, ST1 = 1, ST0 = 1
READ ACCELERATION (R4)
N
R3 ≤ R4
Y
MULTIPLEXOR
VERIFICATION
SUCCESSFUL
MULTIPLEXOR
VERIFICATION
FAILED
Figure 2-2 DSP Input Multiplexor Verification Flow Chart (Y Axis)
2.1.4
Temperature Sensor Value (TEMP)
This read-only register contains a signed value which provides a relative temperature indication. The temperature sensor is
uncalibrated and its output for a given temperature will vary from one device to the next. The value in this register increases with
temperature.
Table 2-6. Temperature Sensor Value Register
Location
Bit Function
Address
Register
7
6
5
4
3
2
1
0
$0F
TEMP
TEMP[7]
TEMP[6]
TEMP[5]
TEMP[4]
TEMP[3]
TEMP[2]
TEMP[1]
TEMP[0]
2.1.5
Device Status Register (DEVSTAT)
This read-only register is accessible in all modes.
Table 2-7. Device Status Register
Location
Bit Function
Address
Register
7
6
5
4
3
2
1
0
$10
DEVSTAT
IDE
0
DEVINIT
TF
0
0
0
DEVRES
2.1.5.1
Internal Data Error Flag (IDE)
This flag will be set if a register data parity fault or a marginally programmed fuse is detected. Device reset is required to clear
this fault condition. If a parity error is associated with the data stored in the fuse array, this fault condition cannot be cleared. This
flag is disabled when the device is in test mode.
2.1.5.2
Device Initialization Flag (DEVINIT)
This flag is set during the interval between negation of internal reset and completion of device initialization. DEVINIT is cleared
automatically.
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2.1.5.3
Temperature Fault Flag (TF)
This flag is set if the value reported by the on-chip temperature sensor exceeds specified limits. TF may be cleared by writing
a logic ‘1’ value to the CE bit in DEVCTL, provided that the fault condition is no longer detected.
2.1.5.4
Device Reset Flag (DEVRES)
This flag is set during device initialization. A logic ‘1’ must be written to the CE bit in the Device Control register (DEVCTL) to
clear this bit. Except when Communications Protocol is active, this bit must be explicitly cleared following reset before acceleration results can be read from MMA690xKQ.
2.1.6
Counter Register (COUNT)
This read-only register provides the value of a free-running 8-bit counter derived from the primary oscillator. A five-bit prescaler
divides the 4.0 MHz primary oscillator frequency by 32. Thus, the value in the register increases by one count every 8.0 μs, and
the counter rolls over every 2.048 ms.
Table 2-8 Counter Register
Location
Bit Function
Address
Register
7
6
5
4
3
2
1
0
$11
COUNT
COUNT[7]
COUNT[6]
COUNT[5]
COUNT[4]
COUNT[3]
COUNT[2]
COUNT[1]
COUNT[0]
2.1.7
Acceleration Result Registers
These read-only registers contain acceleration results produced by the DSP. The values in these registers are frozen by either
of two events:
• CAP/HOLD input at logic high level
• CS input at logic low level
Acceleration result registers are provided for each axis. ACC_X11L/ACC_X11H and ACC_Y11L/ACC_Y11H provide 11-bit results. Updates to ACC_X11L/ACC_X11H and ACC_Y11L/ACC_Y11H are halted upon reading the lower-byte register of either
pair until the upper-byte register is read. There is no requirement to manipulate CAP/HOLD when reading ACC_X11L/ACC_X11H
or ACC_Y11L/ACC_Y11H, however ACC_X11H or ACC_Y11H must be read after reading ACC_X11L or ACC_Y11L, respectively, or further updates to the register pair will not occur.
Table 2-9. X-Axis Acceleration Result Registers
Location
Bit Function
Address
Register
7
6
5
4
3
2
1
0
$24
ACC_X11L
ACC_X[7]
ACC_X[6]
ACC_X[5]
ACC_X[4]
ACC_X[3]
ACC_X[2]
ACC_X[1]
ACC_X[0]
$25
ACC_X11H
0
0
0
0
0
ACC_X[10]
ACC_X[9]
ACC_X[8]
Table 2-10. Y-Axis Acceleration Result Registers
Location
Bit Function
Address
Register
7
6
5
4
3
2
1
0
$26
ACC_Y11L
ACC_Y[7]
ACC_Y[6]
ACC_Y[5]
ACC_Y[4]
ACC_Y[3]
ACC_Y[2]
ACC_Y[1]
ACC_Y[0]
$27
ACC_Y11H
0
0
0
0
0
ACC_Y[10]
ACC_Y[9]
ACC_Y[8]
Sign extension is applied to the upper five bits of ACC_X11H and ACC_Y11H. If an error condition exists, the reserved
value 0 will be read in place of 11-bit acceleration data.
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2.2
VOLTAGE REGULATORS
Separate internal voltage regulators supply fixed voltages to the analog and digital circuitry. External filter capacitors are
required, as shown in Figure 1-5.
The voltage regulator module includes a voltage monitoring circuitry which holds the device in reset following power-on until
internal voltages have stabilized sufficiently for proper operation. The voltage monitor asserts internal reset when the external
supply or internally regulated voltages fall below predetermined levels.
A reference generator provides a stable voltage which is used by the ΣΔ converter. This circuit also requires an external filter
capacitor.
The voltage regulator module is illustrated in Figure 2-3 and Figure 2-4.
VCC
VREGA = 2.50 V
VOLTAGE
REGULATOR
BANDGAP
REFERENCE
VBGA
BIAS
GENERATOR
PRIMARY
OSCILLATOR
TRIM
TRIM
BIAS
GENERATOR
REFERENCE
OSCILLATOR
CREGA
CREGA
OTP
ARRAY
REFERENCE
GENERATOR
VREF = 1.250V
ΣΔ
CONVERTER
BANDGAP
REFERENCE
CREF
CREF
VBG
VOLTAGE
REGULATOR
ΣΔ
CONVERTER
VREG = 2.50V
CREG
DIGITAL
LOGIC
OTP
ARRAY
DSP
Figure 2-3 Power Distribution
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VCC
VOLTAGE
DIVIDER
+
UV
-
VREG
VOLTAGE
DIVIDER
+
UV
-
VOLTAGE
DIVIDER
+
OV
-
VREGA
VOLTAGE
DIVIDER
+
UV
POR
-
VOLTAGE
DIVIDER
+
OV
VBG
VREF
VOLTAGE
DIVIDER
+
UV
-
VOLTAGE
DIVIDER
+
REFER TO SECTION 5.3 FOR
POWER-ON RESET THRESHOLD
LIMITS.
OV
VBGA
Figure 2-4 Voltage Monitoring
2.3
OSCILLATOR
An internal oscillator operating at a nominal frequency of 4.0 MHz provides a stable clock source. The oscillator is factory
trimmed for best performance. A clock generator block divides the 4.0 MHz clock as needed by other blocks.
2.4
CREG MONITOR
A monitor circuit is incorporated to ensure predictable operation of the device in the event that the connection to the external
capacitor at the CREG pin (pin 8) fails, or the capacitor opens. The monitor disables the 2.5 V regulator which powers the digital
circuitry for 2.0 μs every 249.5 μs. If the external capacitor is not present, voltage at the internal supply rail will drop below the
internal reset threshold, continuously forcing the device into reset. Loss of communication from the device is a readily detectable
condition. The XOUT and YOUT pins are driven to the low rail when the device is in the reset state.
2.5
CLOCK MONITOR
Two independent oscillators are provided within MMA690xKQ. One is factory-trimmed and provides the timing reference used
throughout the device. The second oscillator acts as a reference for the first. If the frequency of these two oscillators varies by
more than 10%, an oscillator fault condition is determined. In normal operating mode, an oscillator fault will cause the DOUT pin
to be forced to a continuous logic high state when CS is asserted, as described in Section 3.1.1.2.
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2.6
INTERNAL RESET CONTROLLER
Four conditions can result in an internal reset. The initial power-on condition always results in a reset condition An internal
voltage monitor will assert reset when the supply voltage or a regulated output voltage falls below specified limits. This is referred
to as a low voltage reset. Externally, a hardware reset can be initiated by holding SCLK high and driving the CS pin low for 512 μs.
Finally, the device can be reset through a series of register write operations, as described in Section 2.1.3.1.
2.7
CONTROL LOGIC
A control logic block coordinates a number of activities within the device. These include:
• Post-reset device initialization
• Self-test
• Operating mode selection
• Data array programming
• Device support data transfers
2.8
TEMPERATURE SENSOR
A temperature sensor provides input to the digital signal processing block. Device temperature is incorporated into a correction
value, which is applied to each acceleration result. The upper eight bits of the temperature sensor value are accessible through
the TEMP register, described in Section 2.1.4. The temperature sensor output is continuously compared to under- or over-temperature limits of approximately -40 and +110 °C, respectively. A temperature fault condition is indicated if the temperature sensor
value exceeds the under- or over-temperature limit.
2.8.1
TEMPERATURE SENSOR MONITOR
A monitor circuit associated with the temperature sensor is provided. The monitor will detect over- or under-temperature conditions as well as rapid fluctuations in temperature sensor output such as would be related to failure of the sensor. If a temperature
related fault is detected, an error condition is indicated in lieu of acceleration data.
Rapid fluctuation of the temperature sensor output is detected by comparing the value of each sample to the previous value.
This operation, as well as temperature limit detection is illustrated in Figure 2-5. A fault condition is indicated if predetermined
limits are exceeded.
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Start
Read 10-bit temperature
sensor value (tP)
tP > OTL?
Y
OTL: OVER-TEMPERATURE LIMIT
UTL: UNDER-TEMPERATURE LIMIT
SSL: SAMPLE-TO-SAMPLE LIMIT
N
tP < UTL?
Y
N
Δt = tP - tr
N
TSMEN == 1?
Y
|Δt| > 3?
Y
N
tr = tP
Set Temperature Fault flag
End
Figure 2-5 Temperature Sensor Monitor Flow Chart
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2.9
SPI
The SPI is a full bidirectional port which is used for all configuration and control functions.
2.10
SELF-TEST INTERFACE
The self-test interface provides a mechanism for applying a calibrated voltage to the g-cell. This results in deflection of the
proof mass, causing reported acceleration results to be offset by a specified amount. Control of the self-test interface via the SPI
is accommodated through write operations involving the DEVCTL register at address $0E, described in Section 2.1.3.
2.11
ΣΔ CONVERTERS
Two sigma delta converters provide the interface between the g-cell and digital signal processing block. The output of each
ΣΔ converter is a data stream at a nominal frequency of 1.0 MHz.
2.12
DIGITAL SIGNAL PROCESSING BLOCK
A Digital Signal Processing (DSP) block is used to perform all filtering and correction operations. A diagram illustrating the
signal processing flow within the DSP block is shown in Figure 1-1. The DSP operates at 2.0 MHz, twice the frequency of the
ΣΔ converters. The two interleaved bit streams from the ΣΔ converters are processed simultaneously within the DSP.
Each MMA690xKQ device is factory programmed to select the acceleration range. Filter characteristics for the X- and Y-axes
are customer programmed.
2.12.1
LOW-PASS FILTER
Low-pass filtering occurs in two stages. The serial data stream produced by the ΣΔ converters is decimated and converted to
parallel values by a sinc filter. Parallel data is then processed by an Infinite Impulse Response (IIR) low-pass filter.
A selection of low-pass filter characteristics are available. The cutoff frequency (fC) and rate at which acceleration samples are
determined by the device (tS) vary depending upon which filter is chosen. Power consumption is also affected, as higher sample
rates require greater DSP activity, which in turn requires more supply current.
Response parameters for available low-pass filter are summarized in A.2.
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SECTION 3 SERIAL COMMUNICATIONS
Digital data communication is completed through synchronous serial transfers via the SPI port. Conventional SPI protocol is
employed, acting as a slave device observing CPOL = 0, CPHA = 0, MSB first. All SPI transfers are 16-bits in length, and employ
parity detection to ensure data integrity. During each SPI transfer, an odd number of bits received at DIN must be set to a logic ‘1’
state, or a transient exception condition will be reported during the subsequent transfer. In all normal SPI responses, an odd number of bits transmitted on DOUT will be set to a logic ‘1’ state. Besides parity detection and generation, several other data integrity
features are incorporated into the transfer protocol.
3.1
EXCEPTION CONDITIONS
Under certain conditions, the MMA690xKQ will respond to serial commands with a word, which indicates that an exception
condition has been detected. Response varies according to the Communication Protocol selected. Exceptions fall into five classes and are prioritized. If multiple exception conditions are detected, only the exception of highest priority is reported.
A reset exception condition exists following any device reset. Immediately following reset, a Device Initialization condition will
be indicated until internal initialization of the circuitry has completed. Following internal initialization, a Device Reset exception
condition exists until explicitly cleared by writing a logic ‘1’ to the CE bit in DEVCTL.
Transient exception conditions result from data transmission errors such as data parity faults, an invalid number of clock
cycles, etc. These exceptions are indicated during the following SPI transfer operation. These exceptions do not require an explicit operation to be cleared.
Behavioral exception conditions are defined as those which affect acceleration data results but do not indicate an error condition. In MMA690xKQ, the two behavioral exceptions are activation of self-test and a hold condition resulting from the external
CAP/HOLD pin being driven to a logic high state. Register operations are unaffected by behavioral exceptions. Acceleration data
transfers will complete, with the S/T1 and S/T0 bits indicating that one or both behavioral exception conditions exist.
See Section 3.2 for behavioral exceptions reported by the Communications Protocol.
Critical error exceptions exist when an internal fault, which affects the reliability of device operation or acceleration results, is
detected. If a critical error condition exists, an invalid data value is produced by the device in lieu of acceleration results. Register
operations are unaffected except for the state of S[2:0]. Some critical errors, such as Temperature Fault, may be cleared by
writing a logic ‘1’ to the CE bit in DEVCTL, provided the underlying fault condition no longer persists. Other critical error conditions
require reset of the device to clear.
3.1.1
Defined Exceptions
3.1.1.1
Internal Data Error
Class: Critical error
During reset, a number of internal registers are loaded from a fuse array which stores factory-programmed values. The resistance of each fuse is measured and compared to thresholds to ensure integrity of programmed data. Additionally, the register
array is continuously monitored for correct parity at all time while the device is powered. If either the margin test or parity verification fail, an internal data error exception is reported.
Device reset is required to clear this exception condition.
3.1.1.2
Internal Oscillator Fault
Class: Critical error
If an oscillator fault condition is detected, DOUT is driven high continuously when CS is asserted, as illustrated in Figure 3-1.
Device reset is required to clear this exception condition.
SCLK
CS
DOUT
Figure 3-1 Oscillator Failure Response
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3.1.1.3
Device Initialization
Class: Reset
Following a reset condition, the device requires a period of time to complete initialization of the DSP and internal registers. If
multiple SPI transfers are attempted during this initialization period, the second and all subsequent transfers will result in this
status. The first transfer following reset, regardless of the state of initialization returns device reset status.
This exception condition is cleared automatically upon completion of device initialization.
3.1.1.4
Temperature Fault
Class: Critical
The internal temperature sensor value exceeds the allowable limits for the device. This exception condition may be cleared
by writing a logic ‘1’ to the CE bit in DEVCTL, provided that the temperature has returned to within the operating limits of the
device.
3.1.1.5
Unexpected Axis Selection
Class: Transient
An acceleration data request has been received with an axis specification which is not supported.
This exception condition is reported during the subsequent transfer.
3.1.1.6
Device Reset
Class: Reset
This exception condition is latched any time the device undergoes reset.
Device response will indicate the exception condition in lieu of acceleration data.The device reset exception condition must be
explicitly cleared by writing a logic ‘1’ to the CE bit in DEVCTL.
3.1.1.7
SPI Clock Fault
Class: Transient
A SPI clock fault may result from the following conditions:
• The number of rising clock edges detected while CS is asserted is not equal to the expected number for the
selected communications protocol
• SCLK is high when CS is asserted
This exception condition is reported during the subsequent transfer.
3.1.1.8
DIN Parity Fault
Class: Transient
A parity error was detected on DIN during a data transmission.
This exception condition is reported during the subsequent transfer.
3.1.1.9
HOLD Condition
A HOLD condition exists when the CAP/HOLD pin is driven to a logic high level. Self-test activation is controlled through configuration of ST1 and ST0 in DEVCTL.
3.1.1.10 Self-Test Activation
Class: Behavioral
The device provides two status bits in its response which will indicate a behavioral exception condition if a HOLD condition
exists or self-test is activated. As these are not error conditions, device response is otherwise unaffected. Refer to Section 3.2.1
for details regarding device response to behavioral exception conditions.
A HOLD condition exists when the CAP/HOLD pin is driven to a logic level high level. Self-test activation is controlled through
configuration of ST1 and ST0 in DEVCTL.
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3.1.2
Exception Priority
Table 3-1 provides a summary of exception conditions and order of priority.
Table 3-1. Exception Conditions
Condition
Status Bit
Class
SPI Clock Fault, Previous Transfer
—
Transient
DIN Parity Fault, Previous Transfer
—
Transient
Internal Data Error
IDE
Critical Error
Internal Oscillator Fault
—
Critical Error
Device Initialization
DEVINIT
Reset
Device Reset
DEVRES
Reset
Temperature Fault
TF
Critical Error
Invalid Axis Selection
—
Transient
Hold Condition
—
Behavioral
Self-test
—
Behavioral
If an offset fault condition is detected simultaneously in both the X- and Y-axes, only the X-axis exception is reported by the
device. Hold condition and self-test exceptions have equal priority; if both exceptions exist simultaneously, both are reported by
the device.
3.2
COMMUNICATIONS PROTOCOL
The Communications Protocol provides 11-bit acceleration data along with enhanced status notification in the event that an
exception condition is detected. All transfers are 16-bits in length, with the intended operation indicated by a two-bit transfer type
code transmitted by the SPI master.
Table 3-2. Transfer Type Codes
T1
T0
Transfer Type
0
0
Register Operation
0
1
X-axis acceleration data
1
0
Y-axis acceleration data
1
1
Unused
Device response depends upon the transfer type code and the internal state of the device. If no exception condition has been
detected, the device returns register or acceleration data as requested. If an exception condition exists, response depends upon
the requested operation and the exception. Exceptions are divided into four classes: behavioral, reset, transient, and critical. Certain operations, such as register data write and register pointer write, will not be completed if an exception condition is detected
during the associated SPI transfer. All exception conditions detected by MMA690xKQ are listed in Table 3-1. Response to exceptions is described below, and summarized in Table 3-3.
If both T1 and T0 are set to a logic ‘1’ state, an invalid axis selection exception will be reported by the device.
3.2.1
Device Response
Device response depends upon exception conditions which may be present at the time the transfer takes place. In case of
multiple exceptions, the exception class of highest priority will determine response.
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Table 3-3. Device Response, Exception Conditions
Exception
Command
Response
Priority
Class
ST
HOLD
T1
T0
S2
S1
S0
Register
Acceleration Data
Transient
X
X
X
X
1
1
1
Status code
Status code
Reset
X
X
1
1
1
Critical
X
X
1
1
1
1
1
0
T1
T0
1
0
1
T1
T0
0
1
1
T1
T0
0
0
0
T1
T0
Behavioral
None
T1
T0
Highest
²
$7FF
²
²
As requested
²
As requested
²
Lowest
ST = Self-test active
Commands and response under normal and exception conditions are summarized in the following tables. Note that only
DEVCTL at address $0E is writable when the device is in its normal operating mode.
Table 3-4. Normal Response Summary
Bit
Operation
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Acceleration
Data Read
Command
T1
T0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Response
0
T1
T0
P
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Register Pointer
Read
Command
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Response
0
0
0
0
0
P
0
0
A7
A6
A5
A4
A3
A2
A1
A0
Register Pointer
Write
Command
0
0
0
1
0
P
0
0
A7
A6
A5
A4
A3
A2
A1
A0
Response
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
Register Data
Read
Command
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Response
0
0
0
1
0
P
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Register Data
Write
Command
0
0
1
1
0
P
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Response
0
0
0
1
1
P
0
0
A7
A6
A5
A4
A3
A2
A1
A0
P: Parity
T[1:0] Transfer type code
Note that only DEVCTL is writable when the device operates in normal operating mode. Attempts to write other registers do
not constitute a fault condition, but have no effect.
Table 3-5. Behavioral Response Summary, One Exception Condition
Bit
Operation
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Acceleration
Data Read
Command
T1
T0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Response
1
T1
T0
P
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
Register
Pointer Read
Command
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Response
1
1
1
0
0
P
0
1
A7
A6
A5
A4
A3
A2
A1
A0
Register
Pointer Write
Command
0
0
0
1
0
P
0
0
A7
A6
A5
A4
A3
A2
A1
A0
Response
1
1
1
0
1
0
0
1
0
0
0
0
0
0
0
0
Register Data
Read
Command
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Response
1
1
1
1
0
P
0
1
D7
D6
D5
D4
D3
D2
D1
D0
Register Data
Write
Command
0
0
1
1
0
P
0
0
D7
D6
D5
D4
D3
D2
D1
D0
Response
1
1
1
1
1
P
0
1
A7
A6
A5
A4
A3
A2
A1
A0
P: Parity
T[1:0] Transfer type code
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Behavioral exception conditions exist if self-test is active or the CAP/HOLD input is in a logic high state. MMA690xKQ will respond as shown in Table 3-5 if either exception condition exists. If both exception conditions are true, response is as shown in
Table 3-4.
Table 3-6. Critical/Reset Exception Response Detail
Bit
Operation
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Acceleration Data
Read
Command
T1
T0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Response
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
Register Pointer
Read
Command
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
Response
1
1
1
0
0
P
1
0
Register Address
Register Pointer
Write
Command
0
0
0
1
0
P
0
0
Register Address
Response
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
Register Data
Read
Command
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Response
1
1
1
1
0
P
1
0
Register Data
Register Data
Write
Command
0
0
1
1
0
P
0
0
Register Data
Response
1
1
1
1
1
P
1
0
Register Address
P: Parity
T[1:0] Transfer type code
A special case exists if an internal oscillator fault is detected. This critical error condition results in DOUT being driven high
continuously while CS is asserted, as detailed in Section 3.1.1.2.
Table 3-7. Transient Exception Response Detail
Bit
Operation
15
14
13
12
11
10
9
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
Acceleration Data
Read
Command
T1
T0
0
0
Response
1
1
1
P
Register Pointer
Read
Command
0
0
0
0
0
1
0
0
Response
1
1
1
0
0
P
1
1
Status code
Register Pointer
Write
Command
0
0
0
1
0
P
0
0
Register Address
Response
1
1
1
0
1
P
1
1
Status code
Register Data
Read
Command
0
0
1
0
0
0
0
0
Response
1
1
1
1
0
P
1
1
Status code
Register Data
Write
Command
0
0
1
1
0
P
0
0
Register Data
Response
1
1
1
1
1
P
1
1
Status code
Reserved value (refer to Table 3-8)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P: Parity
T[1:0] Transfer type code
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3.2.2
Acceleration Data Transfer
The format of an acceleration data transfer is illustrated in Figure 3-2. Response to acceleration data transfers is summarized
in Table 3-8. Note that a number of reserved values are defined to indicate error exceptions. MMA690xKQ will produce signed
or unsigned data depending upon the state of the SD bit in the DSPCFG register, as described in Section 2.1.4.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
MOSI
T1
T0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MISO
S2
S1
S0
P
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
BIT
SCLK
CS
0
T[1:0] Transfer type code
S[2:0]: Status code
Figure 3-2 Communications Protocol, Acceleration Data Transfer
Table 3-8. Range of Output, Communications Protocol
11-bit Data Value
Unsigned
Definition
Decimal
Hex
2047
7FF
Critical/Reset Exception Value
2046
7FE
Invalid Axis Selection
2045
7FD
Internal Signal Path Overflow
2044
7FC
Overrange Value
2043
7FB
Maximum Positive Signal Level
•
•
•
1024
•
•
•
400
•
•
•
Zero Signal Level
•
•
•
5
005
Minimum Negative Signal Level
4
004
Underrange Value
3
003
Internal Signal Path Underflow
2
002
SPI Clock Fault
1
001
DIN Parity Fault
0
000
Reserved Value
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3.2.3
Register Operations
Register operations involve four transfer types: register pointer write or read, and register data write or read. The basic format
for register operations is illustrated in Figure 3-3. Response from MMA690xKQ under normal conditions is illustrated. Specific
details for each transfer type are provided in the command/response summaries provided in Section 3.2.1.
15
14
13
12
11
10
9
8
MOSI
T1
T0
A/D
R/W
0
P
0
0
MISO
S2
S1
S0
A/D
R/W
P
EC1
EC0
BIT
7
6
5
4
3
2
1
0
SCLK
CS
D/A7 D/A6 D/A5 D/A4 D/A3 D/A2 D/A1 D/A0
D/A7 D/A6 D/A5 D/A4 D/A3 D/A2 D/A1
D/A0
T[1:0] Transfer type code
S[2:0]: Status code
A/D: ADDRESS/DATA
R/W: READ/WRITE
EC[1:0]: Exception class (refer to Table 3-9 below)
D/A[7:0]: Data or address, depending upon transfer type and status
Figure 3-3 Communications Protocol, Register Operations
Table 3-9. Exception Class Encoding
EC1
EC0
Exception Class
0
0
No Exception
0
1
Behavioral (one exception)
1
0
Critical/Reset
1
1
Transient
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3.3
REPRESENTATION
Table 3-10. Nominal 11-bit Acceleration Data Values
11-bit Unsigned
Digital Value
5.0g Range
2047
Critical/Reset Exception Value
2046
Invalid Axis Selection
2045
Overflow
2044
Overrange
2043
+3.50g
+5.00g
2042
+3.50g
+5.00g
2041
+3.49g
+4.99g
•
•
•
•
•
•
•
•
•
1027
+10.3 mg
+14.7 mg
1026
+6.87 mg
+9.81 mg
1025
+3.43 mg
+4.91 mg
1024
0g
0g
1023
-3.43 mg
-4.91 mg
1022
-6.87 mg
-9.81 mg
1021
-10.3 mg
-14.7 mg
•
•
•
•
•
•
•
•
•
7
-3.49g
-4.99g
6
-3.50g
-5.00g
5
-3.50g
4
3.3.1
Nominal Acceleration
3.5g Range
-5.00g
Underrange
3
Underflow
2
SPI Clock Fault
1
DIN Parity Fault
0
Reserved
Overrange Response
Positive acceleration levels which exceed the full-scale range of the device fall into two categories: overrange and overflow.
Overrange conditions exist when the signal level is beyond the full-scale range of the device but within the computational limits
of the DSP. An overflow condition occurs if the output of the low-pass filter equals or exceeds the maximum digital value which
can be output from the sinc filter. Sinc filter saturation will occur before the internal data path width is exceeded. At 25 °C and
OVLD = 0, the sinc filter will not saturate at sustained acceleration levels with the range of ±200g. The DSP operates predictably
under all cases of overrange, although the signal may include residual high frequency components for some time after returning
to the normal range of operation due to non-linear effects of the sensor. If an overflow condition occurs, the signal is internally
clipped. The DSP will recover from an overflow condition within a few sample times after the input signal returns to the input range
of the DSP. Due to internal clipping within the DSP, some high-frequency artifacts may be present in the output following an overflow condition.
For negative acceleration levels, corresponding underrange and underflow conditions are defined.
3.4
CAP/HOLD INPUT
The CAP/HOLD input provides a system-level synchronization mechanism. When driven high, transfer of acceleration results
from the DSP to the SPI buffers does not occur. The DSP continues its normal operation regardless of the state of CAP/HOLD.
Data read from the device when CAP/HOLD is high will reflect the last values available from the DSP at the time of the signal
transition.
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SECTION 4 OPERATING MODES
MMA690xKQ operates in one of two modes, factory test programming mode and normal operating mode. Factory test and
programming mode is entered only when certain conditions are met, and provides support for programming of customer-defined
data. Normal mode is entered by default when the device is powered on.
4.1
NORMAL OPERATING MODE
Normal mode is entered whenever the device is powered and the VPP pin is held at or below the level of VCC. In normal mode,
acceleration data and device support data transfers are supported.
4.1.1
Power-On Reset
Upon application of voltage at the VCC pin, the internal regulators will begin driving the internal power supply rails. The CREG
and CREGA pins are tied to the internal rails. As voltages at VCC, CREG and CREGA rise, the device becomes operational. An internal reset signal is asserted at this time. Separate comparators on monitor all three voltages, and when all are above specified
thresholds, the reset signal is negated and the device begins its initialization process.
4.1.2
Device Initialization
Following any reset, the device completes a sequence of operations which initialize internal circuitry. Device initialization is
completed in two phases. During the first phase, the fuse array is read and its contents are transferred to mirror registers. Power
to the fuse array is then removed to reduce supply current load. A voltage reference used within the sensor interface stabilizes
during the second phase. If the HPFSEL bit is set in the DSP configuration register (DSPCFG), the high-pass filter is also initialized during phase two.
The device will not respond to SPI accesses during initialization phase one. Acceleration results are not available during initialization phase two, however the SPI is functional and register operations may be performed. If an acceleration data access is
attempted, the device will respond with non-acceleration data. The specific response depends upon the Communications Protocol selected.
The first initialization phase requires approximately 800 μs to complete. The second phase completes in approximately 3.0 ms
if no high-pass filter is selected, and 200 ms if the HPFSEL bit is programmed to a logic ‘1’ state. The DEVINIT bit in the device
status register (DEVSTAT) remains set following reset until the second phase of device initialization completes.
Following completion of the device initialization, the DEVRES bit in DEVSTAT may be cleared by writing a logic ‘1’ value to CE
in DEVCTL. This operation will clear the device reset exception. Once cleared, register operations may be completed or acceleration data values may be read from the device in any desired sequence.
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25
SECTION 5 PERFORMANCE SPECIFICATION
5.1
MAXIMUM RATINGS
Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it. The device
contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep input and output voltages within the range VSS ≤ V ≤ VCC.
Rating
Symbol
Value
Unit
Supply Voltage
VCC
-0.3 to +7
V
(1)
CREG, CREGA, CREF
VREG
-0.3 to +3
V
(1)
VPP
VREG
-0.3 to +11
V
(1)
SCLK, CS, DIN, CAP/HOLD, PCM_X, PCM_Y
VIN
-0.3 to VCC + 0.3
V
(1)
DOUT (high impedance state)
VIN
-0.3 to VCC + 0.3
V
(1)
I
10
mA
(1)
Powered Shock (six sides, 0.5 ms duration)
gpms
±1500
g
(1)
Unpowered Shock (six sides, 0.5 ms duration)
gshock
±2000
g
(1)
Drop Shock (to concrete surface)
hDROP
1.2
m
(1)
Electrostatic Discharge
Human Body Model (HBM)
Charge Device Model (CDM)
Machine Model (MM)
VESD
VESD
VESD
±2000
±500
±200
V
V
V
(1)
Tstg
-40 to +125
°C
(1)
Current Drain per Pin Excluding VCC and VSS
Storage Temperature Range
(1)
(1)
1.Verified by characterization, not tested in production.
5.2
OPERATING RANGE
The operating ratings are the limits normally expected in the application and define the range of operation.
Characteristic
Supply Voltage
Standard Operating Voltage, 3.3V operating range
Standard Operating Voltage, 5.0V operating range
Symbol
Min
Typ
Max
Units
VCC
VCC
VL
+3.15
+4.75
+3.3
+5.0
VH
+3.45
+5.25
V
V
(1)
TA
TL
-40
—
TH
+105
°C
(2)
Operating Temperature Range
(1)
1.Characterized at all values of VL and VH. Production test is conducted at typical voltage unless otherwise noted.
2.Parameters tested 100% at final test.
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5.3
ELECTRICAL CHARACTERISTICS
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4.0 k/min. unless otherwise specified
Characteristic
Symbol
Min
Typ
Max
Units
IDD
—
—
8.0
mA
VPOR_N
VPOR_N
VPOR_N
VPOR_N
2.77
1.80
2.18
1.11
—
—
—
—
3.15
2.32
2.50
1.29
V
V
V
V
(2)
Power-On Reset Threshold (See Figure 5-1)
VCC
CREG
CREGA
CREF
VPOR_A
VPOR_A
VPOR_A
VPOR_A
2.77
1.80
2.18
1.11
—
—
—
—
2.95
2.10
2.31
1.19
V
V
V
V
(2)
Hysteresis (VPOR_N - VPOR_A, See Figure 5-1)
VCC
CREG
CREGA
CREF
VHYST
VHYST
VHYST
VHYST
0
0
0
0
—
—
—
—
388
300
261
150
mV
mV
mV
mV
(2)
VDD
V2.5
VREF
2.42
2.42
1.20
2.50
2.50
1.25
2.58
2.58
1.29
V
V
V
(1)
CREG
ESR
800
—
1000
—
nF
mΩ
(2)
200
—
—
0.004
digit/mv
(2)
NLOUT
-1.0
—
1.0
% FSR
(2)
nSD
—
—
140
μg/√Hz
(2)
SENS
—
3.43
—
mg/digit
(1)
SENS
—
4.91
—
mg/digit
(1)
ΔSENS
-3.0
-3.5
—
+3.0
+3.5
%
%
(1)
*
*
DOUT
—
1024
—
digit
(1)
*
ΔDOUT
-20.4
—
+20.4
digit
(1)
*
ΔΔDOUT
-14.6
—
+14.6
digit
(1)
Supply Current Drain
VCC = 5.25 V, tS = 64 μs
*
Power-On Reset Threshold (See Figure 5-1)
VCC
CREG
CREGA
CREF
Internally Regulated Voltages
CREG
CREGA(3)
CREF
Power Supply Coupling
Nonlinearity
Noise (1.0 Hz-1.0 kHz)
Sensitivity Error
3.5g Range
5.0g Range
Offset at 0 g
11-bit unsigned data
Absolute offset error
-40°C ≤ TA ≤ 105°C
Variation from measured absolute offset error
-40°C ≤ TA ≤ 105°C
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(1)
*
*
*
External Filter Capacitor (CREG, CREGA)
Value
ESR (including interconnect resistance)
Sensitivity
3.5g Range
11-bit data
5.0g Range
11-bit data
(1)
*
*
(1)
(1)
(2)
(1)
1.Parameters tested 100% at final test.
2.Verified by characterization, not tested in production.
3.Tested at VCC = VL and VCC = VH.
* Indicates a Freescale critical characteristic.
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ELECTRICAL CHARACTERISTICS (continued)
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified.
Characteristic
Symbol
Min
Typ
Max
Units
RANGE
CFU
IAU
OFU
ORU
URU
UFU
SCFU
PFU
UNUSED
5
—
—
—
—
—
—
—
—
—
—
2047
2046
2045
2044
4
3
2
1
0
2043
—
—
—
—
—
—
—
—
—
digit
digit
digit
digit
digit
digit
digit
digit
digit
digit
(1)
gOVER
gOVER
+3.22
+4.63
+3.50
+5.00
+3.79
+5.38
g
g
(2)
gUNDER
gUNDER
-3.79
-5.38
-3.50
-5.00
-3.22
-4.63
g
g
(2)
gSAT
< -12
—
> +12
g
(2)
ΔST
ΔST
472
437
525
525
578
630
mg
mg
(4)
VZX
VYX
VZY
-3
-3
-3
—
—
—
+3
+3
+3
%
%
%
(2)
Output High Voltage
DOUT (ILoad = -100 μA)
VOH
0.85
—
—
VCC
(6)
Output Low Voltage
DOUT, (ILoad = 100 μA)
VOL
—
—
0.1
VCC
(6)
ZOUT
COUT
47
—
—
—
—
35
kΩ
pF
(2)
Input High Voltage
CS/RESET, SCLK, DIN, CAP/HOLD
VIH
0.65
—
—
VCC
(6)
High Impedance Leakage Current
DOUT, Input Voltage = VCC or VSS
IIL
-3
—
+3
μA
(4)
Input Low Voltage
CS/RESET, SCLK, DIN, CAP/HOLD
VIL
—
—
0.2
VCC
(6)
IIH
RIN
-30
190
-50
270
-260
350
μA
kΩ
(6)
IIL
30
50
260
μA
(6)
Range of Output
11-bit data, unsigned
Normal
Critical Fault Value
Invalid Axis Selection
Positive Acceleration Overflow Code
Positive Acceleration Overrange Code
Negative Acceleration Underrange Code
Negative Acceleration Underlfow Code
SPI Clock Fault
DIN Parity Fault
Unused Code
Output value on overrange
11-bit data: 2043
3.5g Range
5.0g Range
11-bit data: 5
3.5g Range
5.0g Range
Maximum acceleration without saturation of internal circuitry
(OVLD = 0)
Self-test Output Change(3)
TA = 25 °C
-40 ≤ TA ≤ 105 °C
Cross-Axis Sensitivity(5)
VZX
VYX
VZY
Output Loading (DOUT)
Load Resistance
Load Capacitance
Input Current
High (at VIH)
SCLK, DIN, CAP/HOLD
VPP (internal pull-down resistor)
Low (at VIL)
CS/RESET
*
*
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(1)
(2)
(2)
(4)
(2)
(2)
(2)
(6)
1.Functionality verified 100% via scan. timing characteristic is directly determined by internal oscillator frequency.
2.Verified by characterization, not tested in production.
3.Self-test deflection is trimmed in positive direction. Deflection in negative direction is approximately equal in magnitude.
4.Parameters tested 100% at final test.
5.Verified by characterization. Conformance guaranteed to 20 ppm.
6.Parameters tested 100% at unit probe.
* Indicates a Freescale critical characteristic.
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5.4
CONTROL TIMING
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 4 K/min unless otherwise specified
Characteristic
Symbol
Min
Typ
Max
Units
fC(LPF)
OLPF
47.5
50.0
2
52.5
Hz
1
(1)
Power-On Recovery Time
POR negated to CS low
Power applied to XOUT, YOUT valid
tOP
tXY
⎯
⎯
⎯
⎯
840
15
μs
ms
(1)
Internal Oscillator Frequency
fOSC
3.8
4.0
4.2
MHz
(2)
Clock Monitor Threshold
fMON
3.6
⎯
4.4
MHz
(1)
Chip Select to Internal Reset (See Figure 5-2)
tCSRES
486
512
538
μs
(1)
Serial Interface Timing (See Figure 5-3)
Clock period
CS asserted to SCLK high
Data setup time
Data hold time
SCLK high to data out
SCLK high to CS negated
CS negated to CS asserted
tSCLK
tCSCLK
tDC
tCDIN
tCDOUT
tCHCSH
tCSN
120
60
20
10
—
60
600
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
50
—
—
ns
ns
ns
ns
ns
ns
ns
(3)
fn
⎯
⎯
3
1.2
⎯
⎯
kHz
kHz
(3)
DSP Low-Pass Filter Cut-Off Frequency
Filter Order
Sensing Element Natural Frequency
Sense Element Bandwidth (-3.0 dB)
BWGCELL
(1)
(2)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
1.Functionality verified 100% via scan. timing characteristic is directly determined by internal oscillator frequency.
2.Parameters tested 100% at final test.
3.Verified by characterization, not tested in production.
5.5V
VPOR_N
VPOR_A
VCC
POR
Figure 5-1 Power-Up Timing
CS
tCSRES
INTERNAL RESET
SCLK
Figure 5-2 CS Reset Timing
MMA690xKQ
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Freescale Semiconductor, Inc.
29
CS
tCSN
tCSCLK
tCLK
tCHCSH
SCLK
tDC
tCDIN
DIN
tCDOUT
DOUT
DATA
VALID
Figure 5-3 Serial Interface Timing
MMA690xKQ
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5.5
PACKAGE INFORMATION
The following documents provide a case outline drawing and information regarding printed wiring board mounting for the
MMA690xKQ device. For the most current package revision, visit www.freescale.com and perform a keyword search using the
“98A” listed below. The board mounting application note AN3111 can be also located on the Freescale web site.
5.5.1
Package Dimensions
98ASA10571D
ISSUE B
CASE 1477-02
16 LEAD QFN
PAGE 1 OF 3
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31
98ASA10571D
ISSUE B
CASE 1477-02
16 LEAD QFN
PAGE 2 OF 3
MMA690xKQ
32
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98ASA10571D
ISSUE B
CASE 1477-02
16 LEAD QFN
PAGE 3 OF 3
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APPENDIX A DIGITAL FILTER CHARACTERISTICS
Response curves for filter options are provided in this appendix.
A.1
SINC FILTER CHARACTERISTICS
sinc filter: R =32, N =3, fs =1000000
Magnitude (dB)
0
−50
−100
−150
−200
0
0.5
1
1.5
2
2.5
3
Frequency (Hz)
3.5
2
2.5
3
Frequency (Hz)
3.5
4
4.5
5
x 10
5
Phase (degrees)
0
−2000
−4000
−6000
−8000
0
0.5
1
1.5
4
4.5
5
x 10
5
Figure A-1 Sinc Filter Response, tS = 32 μs
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A.2
LOW-PASS FILTER CHARACTERISTICS
Frequency Response
0
Gain (dB)
−5
−10
−15
−20
−25
−30
1
10
2
Frequency (Hz)
Group Delay
200
100
Phase (radians)
Group Delay (samples)
10
0
10
1
10
2
Frequency (Hz)
Phase Response
5
0
−5
10
1
10
2
Frequency (Hz)
Figure A-2 Low-Pass Filter, fc = 50 Hz, Poles = 2, ts = 32 μs
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Table 6. Revision History
Revision
number
Revision
date
4
03/2012
• Added SafeAssure logo, changed first paragraph and disclaimer to include trademark information.
5
08/2012
•
•
•
•
•
Description of changes
Changed device numbers to include “K” suffix.
Changed AEC-Q100 qualified, Rev. G to Rev. F.
Section 1.4.12, added
Table 2-1: Corrected Addr $0A and $0B bits 7 and 6 from 0 and 1 to 1 and 0.
Section 5.3 Electrical Characteristics table under Offset at 0 g: Changed Offset error to Absolute offset error,
removed temperature range TA = 25°C, removed 11-bit data line, added temperature range -40°C ≤ TA ≤
105°C and values. Added Variation from measured absolute offset error with temperature range of -40°C ≤
TA ≤ 105°C and values.
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disclaims any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in Freescale data sheets and/or
specifications can and do vary in different applications, and actual performance may
vary over time. All operating parameters, including “typicals,” must be validated for each
customer application by customer’s technical experts. Freescale does not convey any
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freescale.com/SalesTermsandConditions.
Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware,
Energy Efficient Solutions logo, Kinetis, mobileGT, PowerQUICC, Processor Expert,
QorIQ, Qorivva, StarCore, Symphony, and VortiQa are trademarks of Freescale
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© 2012 Freescale Semiconductor, Inc.
Document Number: MMA690xKQ
Rev. 5
08/2012
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