Ultrasonic Humidifier 8-Bit Flash MCU HT45F3830 Revision: V1.00 Date: ������������ May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Table of Contents Features............................................................................................................. 6 CPU Features.......................................................................................................................... 6 Peripheral Features.................................................................................................................. 6 General Description ......................................................................................... 7 Block Diagram................................................................................................... 8 Pin Assignment................................................................................................. 8 Pin Descriptions............................................................................................... 9 Absolute Maximum Ratings............................................................................11 D.C. Characteristics........................................................................................ 12 A.C. Characteristics........................................................................................ 13 Slew Rate Control Characteristics................................................................ 14 LVD & LVR Electrical Characteristics........................................................... 14 Over Current/Voltage Protection Electrical Characteristics ...................... 15 Power on Reset Electrical Characteristics................................................... 16 System Architecture....................................................................................... 17 Clocking and Pipelining.......................................................................................................... 17 Program Counter.................................................................................................................... 18 Stack...................................................................................................................................... 19 Arithmetic and Logic Unit – ALU............................................................................................ 19 Flash Program Memory.................................................................................. 20 Structure................................................................................................................................. 20 Special Vectors...................................................................................................................... 20 Look-up Table......................................................................................................................... 20 Table Program Example......................................................................................................... 21 In Circuit Programming.......................................................................................................... 22 On-Chip Debug Support – OCDS.......................................................................................... 22 RAM Data Memory.......................................................................................... 23 Structure................................................................................................................................. 23 General Purpose Data Memory............................................................................................. 24 Special Purpose Data Memory.............................................................................................. 24 Special Function Register Description......................................................... 25 Indirect Addressing Registers – IAR0, IAR1.......................................................................... 25 Memory Pointers – MP0, MP1............................................................................................... 25 Bank Pointer – BP.................................................................................................................. 26 Accumulator – ACC................................................................................................................ 26 Program Counter Low Register – PCL................................................................................... 26 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 27 Status Register – STATUS..................................................................................................... 27 Rev. 1.00 2 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU EEPROM Data Memory................................................................................... 29 EEPROM Data Memory Structure......................................................................................... 29 EEPROM Registers............................................................................................................... 29 Reading Data from the EEPROM ......................................................................................... 31 Writing Data to the EEPROM................................................................................................. 31 Write Protection...................................................................................................................... 31 EEPROM Interrupt................................................................................................................. 31 Programming Considerations................................................................................................. 32 Oscillators....................................................................................................... 33 Oscillator Overview................................................................................................................ 33 System Clock Configurations................................................................................................. 33 Internal RC Oscillator – HIRC................................................................................................ 34 Internal 32kHz Oscillator – LIRC............................................................................................ 34 Operating Modes and System Clocks.......................................................... 35 System Clocks....................................................................................................................... 35 System Operating Modes....................................................................................................... 36 Control Registers................................................................................................................... 37 Operating Mode Switching .................................................................................................... 39 Standby Current Considerations............................................................................................ 43 Wake-up................................................................................................................................. 43 Watchdog Timer.............................................................................................. 44 Watchdog Timer Clock Source............................................................................................... 44 Watchdog Timer Control Register.......................................................................................... 44 Watchdog Timer Operation.................................................................................................... 45 Reset and Initialisation................................................................................... 47 Reset Functions..................................................................................................................... 47 Reset Initial Conditions.......................................................................................................... 49 Input/Output Ports.......................................................................................... 52 Pull-high Resistors................................................................................................................. 52 Port A Wake-up...................................................................................................................... 53 I/O Port Control Registers...................................................................................................... 53 Slew Rate Control.................................................................................................................. 54 Source Current Selection....................................................................................................... 55 Pin-shared Function............................................................................................................... 56 I/O Pin Structures................................................................................................................... 59 Programming Considerations................................................................................................. 59 Timer Modules – TM....................................................................................... 60 Introduction............................................................................................................................ 60 TM Operation......................................................................................................................... 60 TM Clock Source.................................................................................................................... 61 TM Interrupts.......................................................................................................................... 61 TM External Pins.................................................................................................................... 61 TM Input/Output Pin Control Register.................................................................................... 62 Programming Considerations................................................................................................. 63 Rev. 1.00 3 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Compact Type TM – CTM............................................................................... 64 Compact TM Operation.......................................................................................................... 64 Compact Type TM Register Description................................................................................ 64 Compact Type TM Operating Modes..................................................................................... 68 Standard Type TM – STM............................................................................... 74 Standard TM Operation.......................................................................................................... 74 Standard Type TM Register Description................................................................................ 74 Standard Type TM Operating Modes..................................................................................... 78 Periodic Type TM – PTM ................................................................................ 87 Periodic TM Operation .......................................................................................................... 87 Periodic Type TM Register Description ................................................................................. 87 Periodic Type TM Operating Modes ...................................................................................... 91 Nebuliser Resonance Detector.................................................................... 100 Water Shortage Protection........................................................................... 100 Over Current/Voltage Protection................................................................. 100 OCVP Operation.................................................................................................................. 100 OCVP Control Registers...................................................................................................... 101 Input Voltage Range............................................................................................................. 105 Offset Calibration................................................................................................................. 105 I C Interface................................................................................................... 107 2 I2C Interface Operation ........................................................................................................ 107 I2C Registers........................................................................................................................ 108 I2C Bus Communication .......................................................................................................112 I2C Bus Start Signal ..............................................................................................................113 Slave Address ......................................................................................................................113 I2C Bus Read/Write Signal ...................................................................................................113 I2C Bus Slave Address Acknowledge Signal ........................................................................113 I2C Bus Data and Acknowledge Signal ................................................................................114 I2C Time-out Control..............................................................................................................115 Interrupts........................................................................................................117 Interrupt Registers.................................................................................................................117 Interrupt Operation............................................................................................................... 122 External Interrupts................................................................................................................ 123 OCVP Interrupt..................................................................................................................... 124 Multi-function Interrupts........................................................................................................ 124 Time Base Interrupts............................................................................................................ 124 I2C Interrupt.......................................................................................................................... 125 EEPROM Interrupt............................................................................................................... 126 LVD Interrupt........................................................................................................................ 126 TM Interrupts........................................................................................................................ 126 Interrupt Wake-up Function.................................................................................................. 127 Programming Considerations............................................................................................... 127 Rev. 1.00 4 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Low Voltage Detector – LVD........................................................................ 128 LVD Register........................................................................................................................ 128 LVD Operation...................................................................................................................... 129 LCD SCOM Function.................................................................................... 130 LCD Operation..................................................................................................................... 130 LCD Bias Current Control.................................................................................................... 130 Configuration Option.................................................................................... 131 Application Circuit........................................................................................ 131 Instruction Set............................................................................................... 132 Introduction.......................................................................................................................... 132 Instruction Timing................................................................................................................. 132 Moving and Transferring Data.............................................................................................. 132 Arithmetic Operations........................................................................................................... 132 Logical and Rotate Operation.............................................................................................. 133 Branches and Control Transfer............................................................................................ 133 Bit Operations...................................................................................................................... 133 Table Read Operations........................................................................................................ 133 Other Operations.................................................................................................................. 133 Instruction Set Summary............................................................................. 134 Table Conventions................................................................................................................ 134 Instruction Definition.................................................................................... 136 Package Information.................................................................................... 145 16-pin NSOP (150mil) Outline Dimensions.......................................................................... 146 20-pin NSOP (150mil) Outline Dimensions.......................................................................... 147 24-pin SOP (300mil) Outline Dimensions............................................................................ 148 Rev. 1.00 5 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Features CPU Features • Operating Voltage ♦♦ fSYS =12MHz: 2.7V ~ 5.5V ♦♦ fSYS =32kHz: 2.2V ~ 5.5V • Up to 0.33μs instruction cycle with 12MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Oscillators ♦♦ Internal High Speed RC – HIRC ♦♦ Internal Low Speed 32kHz RC – LIRC • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • Fully integrated internal 12MHz oscillator requires no external components • All instructions executed in one or two instruction cycles • Table read instructions • 63 powerful instructions • 4-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 2K×16 • RAM Data Memory: 128×8 • EEPROM Memory: 64×8 • Watchdog Timer function • 22 bidirectional I/O lines • Two pin-shared external interrupts • Slew Rate Control for PC1 Port Output • Programmable I/O port source current for LED applications • Multiple Timer Modules for time measure, input capture, compare match output, PWM output function or single pulse output function ♦♦ 10-bit CTM × 1 ♦♦ 10-bit PTM × 2 ♦♦ 10-bit STM × 1 • Over Current/Voltage Protection (OCVP) Function with interrupt • Dual Time-Base functions for generation of fixed time interrupt signals • I2C Interface • Low voltage reset function • Low voltage detect function • Software controlled 4-SCOM lines LCD Driver with 1/2 bias • Flash program memory can be re-programmed up to 100,000 times • Flash program memory data retention > 10 years • EEPROM data memory can be re-programmed up to 1,000,000 times • EEPROM data memory data retention > 10 years • Package Type: 16/20-pin NSOP, 24-pin SOP Rev. 1.00 6 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU General Description The HT45F3830 is a device dedicated for use in ultrasonic nebuliser applications. The application principle for ultrasonic nebulisers is to use electronic high-frequency oscillation and ceramic nebulising chip high-frequency resonance to break up the liquid water molecules thus generating a fine mist without requiring heating or any chemical substances. Compared with the heating nebulisation method, the ultrasonic method can result in 90% energy savings. Additionally, during the nebulisation process, it can release a large number of negative ions which can precipitate smoke and dust particles in air by electrostatic reaction and also can effectively remove formaldehyde, carbon monoxide, bacteria and other harmful substances thus generating cleaner air and reducing the possibility of disease transmission. The device is a Flash Memory type 8-bit high performance RISC architecture microcontroller containing special internal circuitry for ultrasonic nebuliser applications. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include an over current protection function. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. The device also includes fully integrated low and high speed oscillators which can be flexibly used for different applications. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the internal I2C interface. While the inclusion of flexible I/O programming features, Time-Base functions along with an adjustable ultrasonic nebuliser resonant frequency generator and many other features ensure that the device will find excellent use in different ultrasonic nebuliser applications. This device can use the nebuliser resonance detector to detect the nebuliser resonant frequency, and use the nebuliser resonant frequency selection to output PFM resonant frequency for nebuliser control, it can also use the water shortage protection and OCVP functions for water shortage detection. Rev. 1.00 7 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Block Diagram Low Voltage Detect Flash/EEPROM Programming Circuitry (ICP/OCDS) 8-bit RISC MCU Core Interrupt Controller Low Voltage Reset Internal RC Oscillators EEPROM Data Memory Reset Circuit Flash Program Memory RAM Data Memory Time Base Watchdog Timer Nebuliser Resonant Slew Rate Frequency Selection Controller Nebuliser Resonance Detector & Water Shortage Protection I2C Interface I/O Ports Timer Modules Over Current/Voltage Protection OCVPS[1:0] Pin Assignment PTPI/PC1 1 1� VSS � 15 PA0/SDA/ICPDA/OCDSDA VDD � 14 PTCK1/PC0 4 1� OCVPAI0/PB0 OCVPAI0/PB1 OCVPAI0/PB� VREF/PTCK0/PA7 5 1� OCVPAI0/STP/PA4 OCVPAI0/CTP/PA1 � 11 OCVPAI0/PB� 7 10 OCVPCI/INT1/STCK/PA5 OCVPAI0/INT0/CTCK/PA� 8 9 OCVPAI0/PTP0/PA� HT45F3830/HT45V3830 16NSOP-A PTPI/PC1 1 �0 PA0/SDA/ICPDA/OCDSDA VSS � 19 VDD PTCK1/PC0 � 18 4 17 PA�/SCL/ICPCK/OCDSCK OCVPAI0/PB0 OCVPAI0/PB1 VREF/PTCK0/PA7 5 1� OCVPAI0/PB� SCO��/PB7 � 15 OCVPAI0/PB� SCO��/PB� 7 14 PB4/SCO�0 OCVPAI0/STP/PA4 8 1� PB5/SCO�1 OCVPAI0/CTP/PA1 9 1� 10 11 OCVPCI/INT/STCK/PA5 OCVPAI0/PTP0/PA� OCVPAI0/INT0/CTCK/PA� HT45F3830/HT45V3830 20NSOP-A Rev. 1.00 8 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU PA0/SDA/ICPDA/OCDSDA PTPI/PC1 VSS 1 �4 � �� PA�/SCL/ICPCK/OCDSCK VDD � �� OCVPAI0/PB0 PTCK1/PC0 VREF/PTCK0/PA7 4 �1 OCVPAI0/PB1 5 �0 OCVPAI0/PB� SCO��/PB7 � 19 OCVPAI0/PB� SCO��/PB� 7 18 PB4/SCO�0 PC4 PC5 8 17 PB5/SCO�1 9 1� PC� OCVPAI0/STP/PA4 10 15 PC� OCVPAI0/CTP/PA1 11 14 OCVPAI0/INT0/CTCK/PA� 1� 1� OCVPCI/INT/STCK/PA5 OCVPAI0/PTP0/PA� HT45F3830/HT45V3830 24SOP-A Note: 1. If the pin-shared pin functions have multiple output functions, the desired pin-shared function is determined using corresponding software control bits. 2. The actual device and its equivalent OCDS EV device share the same package type, however the OCDS EV device part number is HT45V3830. Pins OCDSCK and OCDSDA which are pin-shared with PA2 and PA0 are only used for the OCDS EV device. Pin Descriptions With the exception of the power pins and some relevant transformer control pins, all pins on this device can be referenced by their Port name, e.g. PA0, PA1 etc, which refer to the digital I/O function of the pins. However these Port pins are also shared with other function such as the Timer Module pins etc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. Note that the pin description refers to the largest package size, as a result some pins may not exist on smaller package types. Pin Name PA0/SDA/ICPDA/ OCDSDA PA1/CTP/OCVPAI0 PA2/SCL/ICPCK/ OCDSCK Function OPT I/T O/T PA0 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SDA IICC0 ST NMOS I2C data/address line ICPDA — ST CMOS In-circuit programming data/address pin OCDSDA — ST CMOS On-chip debug support data/address pin, for EV chip only PA1 PAPU PAWU CTRL3 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. CTP CTRL3 — CMOS CTM output OCVPAI0 CTRL2 CTRL3 AN — PA2 PAPU PAWU ST CMOS General purpose I/O. Register enabled pull-up and wake-up. SCL IICC0 ST NMOS I2C clock line ICPCK — ST — In-circuit programming clock pin — On-chip debug support clock pin, for EV chip only OCDSCK Rev. 1.00 — ST 9 Description OCVPAI0 input path May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Pin Name PA3/ INT0/CTCK /OCVPAI0 PA4/ STP/OCVPAI0 PA5/OCVPCI/ INT1/STCK PA6/PTP0/ OCVPAI0 PA7/PTCK0/VREF Function OPT I/T O/T PA3 PAPU PAWU CTRL3 ST CMOS INT0 CTRL3 INTEG ST — External interrupt 0 CTCK CTRL3 CTMC0 ST — CTM clock input OCVPAI0 CTRL2 CTRL3 AN — OCVPAI0 input path PA4 PAPU PAWU CTRL3 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. STP CTRL3 ST CMOS STM output or capture input OCVPAI0 CTRL2 CTRL3 AN — PA5 PAPU PAWU CTRL3 ST CMOS OCVPCI CTRL3 AN — OCVP comparator non-inverting signal input INT1 CTRL3 INTEG ST — External interrupt 1 STCK CTRL3 STMC0 ST — STM clock input PA6 PAPU PAWU CTRL3 ST CMOS General purpose I/O. Register enabled pull-up and wake-up. PTP0 CTRL3 ST CMOS PTM0 output or capture input OCVPAI0 CTRL2 CTRL3 AN — PA7 PAPU PAWU CTRL4 ST CMOS PTCK0 CTRL4 PTM0C0 ST — PTM0 clock input or capture input VREF CTRL4 AN — DAC voltage reference PB0 PBPU CTRL4 ST CMOS OCVPAI0 CTRL2 CTRL4 AN — PB1 PBPU CTRL4 ST CMOS OCVPAI0 CTRL2 CTRL4 AN — PB2 PBPU CTRL4 ST CMOS OCVPAI0 CTRL2 CTRL4 AN — PB3 PBPU CTRL4 ST CMOS OCVPAI0 CTRL2 CTRL4 AN — PB4 PBPU CTRL5 ST CMOS General purpose I/O. Register enabled pull-up SCOM0 CTRL5 — SCOM LCD SCOM function pin PB0/OCVPAI0 PB1/OCVPAI0 PB2/OCVPAI0 PB3/OCVPAI0 PB4/SCOM0 Rev. 1.00 10 Description General purpose I/O. Register enabled pull-up and wake-up. OCVPAI0 input path General purpose I/O. Register enabled pull-up and wake-up. OCVPAI0 input path General purpose I/O. Register enabled pull-up and wake-up. General purpose I/O. Register enabled pull-up OCVPAI0 input path General purpose I/O. Register enabled pull-up OCVPAI0 input path General purpose I/O. Register enabled pull-up OCVPAI0 input path General purpose I/O. Register enabled pull-up OCVPAI0 input path May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Pin Name PB5/SCOM1 PB6/SCOM2 PB7/SCOM3 PC0/PTCK1 PC1/ PTP1 Function OPT I/T O/T PB5 PBPU CTRL5 Description ST CMOS General purpose I/O. Register enabled pull-up SCOM1 CTRL5 — SCOM LCD SCOM function pin PB6 PBPU CTRL5 ST CMOS General purpose I/O. Register enabled pull-up SCOM2 CTRL5 — SCOM LCD SCOM function pin PB7 PBPU CTRL5 ST CMOS General purpose I/O. Register enabled pull-up SCOM3 CTRL5 — SCOM LCD SCOM function pin PC0 PCPU ST CMOS General purpose I/O. Register enabled pull-up PTCK1 PTM1C0 ST — PC1 PCPU CTRL4 ST CMOS General purpose I/O. Register enabled pull-up PTM1 clock input or capture input PTP1 CTRL4 ST CMOS PTM1 output or capture input PC2~PC5 PCPU ST CMOS General purpose I/O. Register enabled pull-up VDD VDD — PWR — Positive power supply VSS VSS — PWR — Negative power supply PC2~PC5 Legend: I/T: Input type O/T: Output type OPT: Optional by register option PWR: Power ST: Schmitt Trigger input CMOS: CMOS output NMOS: NMOS output AN: Analog signal SCOM: Software LCD COM output Absolute Maximum Ratings Supply Voltage.................................................................................................VSS−0.3V to VSS+6.0V Input Voltage...................................................................................................VSS−0.3V to VDD+0.3V Storage Temperature.....................................................................................................-50˚C to 125˚C Operating Temperature...................................................................................................-40˚C to 85˚C IOL Total...................................................................................................................................... 80mA IOH Total.....................................................................................................................................-80mA Total Power Dissipation.......................................................................................................... 500mW Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. Rev. 1.00 11 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU D.C. Characteristics Ta=25°C Symbol VDD Parameter Typ. Max. Unit V — fSYS=fHIRC=12MHz 2.7 — 5.5 — fSYS=fLIRC=32kHz 2.2 — 5.5 V Operating Current (HIRC) 3V No load, all peripherals off, 5V fSYS=fHIRC=12MHz — 2.2 3.3 mA — 5 7.5 mA Operating Current (LIRC) 3V No load, all peripherals off, 5V fSYS=fLIRC=32kHz — 10 20 μA μA 3V No load, all peripherals off, Standby Current (SLEEP Mode) 5V WDT off Standby Current (SLEEP Mode) 3V No load, all peripherals off, 5V WDT on Standby Current (IDLE0 Mode) 3V No load, all peripherals off, 5V fSUB on Standby Current (IDLE1 Mode, HIRC) 3V No load, all peripherals off, 5V fSUB on, fSYS=fHIRC=12MHz 5V VIL Input Low Voltage for I/O Ports VIH Input High Voltage for I/O Ports IOL Sink Current for I/O Ports (Except PC1 Port) Rev. 1.00 Min. Operating Voltage (LIRC) ISTB RPH Conditions Operating Voltage (HIRC) IDD IOH Test Conditions VDD Source Current for I/O Ports (Except PC1 Port) Pull-high Resistance for I/O Ports — — 30 50 — 0.2 0.8 μA — 0.5 1 μA — 1.3 5 μA — 2.2 10 μA — 1.3 3 μA — 2.2 5 μA — 0.6 1.2 mA — 1.2 2.4 mA 0 — 1.5 V V — — 0 — 0.2 VDD 5V — 3.5 — 5 V — — V 0.8VDD — VDD 3V VOL=0.1VDD 16 32 — 5V VOL=0.1VDD 32 65 — 3V VOH=0.9VDD, SLEDCn[m+1,m]=00B 5V n=0, 1; m=0, 2, 4, 6 -0.7 -1.5 — -1.5 -2.9 — 3V VOH=0.9VDD, SLEDCn[m+1,m]=01B 5V n=0, 1; m=0, 2, 4, 6 -1.3 -2.5 — -2.5 -5.1 — 3V VOH=0.9VDD, SLEDCn[m+1,m]=10B 5V n=0, 1; m=0, 2, 4, 6 -1.8 -3.6 — -3.6 -7.3 — 3V VOH=0.9VDD, SLEDCn[m+1,m]=11B 5V n=0, 1; m=0, 2, 4, 6 -4 -8 — -8 -16 — 3V — 20 60 100 kΩ 5V — 10 30 50 kΩ 12 mA mA mA mA mA May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU A.C. Characteristics Symbol fSYS fHIRC Parameter Ta=25°C Test Conditions VDD Conditions Typ. Max. Unit System Clock (HIRC) 2.7V ~ 5.5V fSYS=fHIRC=12MHz — 12 — MHz System Clock (LIRC) 2.2V ~ 5.5V fSYS=fLIRC=32kHz — 32 — kHz High Speed Internal RC Oscillator (HIRC) 3V Ta=25°C -2% 12 +2% MHz 5V Ta=25°C -2% 12 +2% MHz 2.7V~ 5.5V Ta=25°C -5% 12 +5% MHz 3V Ta=0°C ~ 70°C -7% 12 +7% MHz 5V Ta=0°C ~ 70°C -7% 12 +7% MHz 3V Ta= -40°C ~ 85°C -10% 12 +10% MHz 5V Ta= -40°C ~ 85°C 2.7V ~ 5.5V Ta=0°C ~ 70°C 2.7V ~ 5.5V Ta= -40°C ~ 85°C Low Speed Internal RC Oscillator (LIRC) -7% 12 +7% MHz -7% 12 +7% MHz -10% 12 +10% MHz -10% 32 +10% 3V ± 0.3V Ta= -40°C ~ 85°C -40% 32 +40% kHz 2.2V ~ 5.5V Ta= -40°C ~ 85°C -50% 32 +60% kHz -10% 32 +10% kHz -40% 32 +40% kHz 3V fLIRC Min. Ta=25°C Ta=25°C 5V 5V ± 0.5V Ta= -40°C ~ 85°C kHz tTIMER xTCKn Input Pin Minimum Pulse Width — — — 30 — ns tDEW Data EEPROM Write Time — — — 2 4 ms tINT External Interrupt Minimum Pulse Width — — 1 3.3 5 μs System Reset Delay Time (Power-on Reset, LVR Hardware Reset, LVR Software Reset, WDT Software Reset) — — 25 50 100 ms System reset delay time (WDT Time-out Hardware Cold Reset) — — 8.3 16.7 33.3 ms tRSTD System Start-up Timer Period (Wake-up from Power Down Mode and fSYS off) tSST System Start-up Timer Period (Slow Mode ↔ Normal Mode) System Start-up Timer Period (Wake-up from Power Down Mode and fSYS on) System Start-up Timer Period (WDT Time-out Hardware Cold Reset) I2C Standard Mode (100kHz) System Frequency fI2C I2C Fast Mode (400kHz) System Frequency — fSYS=fH ~ fH / 64, fH=fHIRC 16 — — tHIRC — fSYS=fSUB=fLIRC 2 — — tLIRC — fHIRC off → on (HTO=1) 16 — — tHIRC — fSYS=fHIRC ~ fHIRC /64 2 — — tH — fSYS=fLIRC 2 — — tSUB 0 — — tH — — — No clock debounce 2 — — MHz — 2 system clocks debounce 4 — — MHz — 4 system clocks debounce 8 — — MHz — No clock debounce 5 — — MHz — 2 system clocks debounce 10 — — MHz — 4 system clocks debounce 20 — — MHz Note: 1. tSYS= 1/fSYS; tSUB=1/fSUB; tHIRC= 1/fHIRC 2. To maintain the accuracy of the internal HIRC oscillator frequency, a 0.1μF decoupling capacitor should be connected between VDD and VSS and located as close to the device as possible. 3. Frequency accuracy (trim at VDD=3V/5V, FADJH=01H, FADJL=00H). Rev. 1.00 13 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Slew Rate Control Characteristics Operating Temperature: -40°C~85°C, unless otherwise specify Symbol Parameter IOL PC1 Port Sink Current IOH PC1 Port Source Current SRRISE SRFALL Output Rising edge Slew Rate for PC1 Port Output Falling edge Slew Rate for PC1 Port Test Conditions VDD 3V Conditions Min. Typ. Max. Unit 24 60 — mA 60 150 — mA -24 -60 — mA -60 -150 — mA 5V SLEWC0[1:0]=00B 0.5V to 4.5V, CLOAD=1000pF 200 — — V/μs 5V SLEWC0[1:0]=01B 0.5V to 4.5V, CLOAD=1000pF — 60 — V/μs 5V SLEWC0[1:0] = 10B 0.5V to 4.5V, CLOAD=1000pF — 30 — V/μs 5V SLEWC0[1:0]=11B 0.5V to 4.5V, CLOAD=1000pF — 15 — V/μs 5V SLEWC0[1:0]=00B 4.5V to 0.5V, CLOAD = 1000pF 200 — — V/μs 5V SLEWC0[1:0]=01B 4.5V to 0.5V, CLOAD=1000pF — 60 — V/μs 5V SLEWC0[1:0]=10B 4.5V to 0.5V, CLOAD=1000pF — 30 — V/μs 5V SLEWC0[1:0]=11B 4.5V to 0.5V, CLOAD=1000pF — 15 — V/μs 5V 3V 5V VOL=0.2VDD VOH=0.8VDD LVD & LVR Electrical Characteristics Ta=25°C Symbol VLVR VLVD ILVR ILVD Parameter Low Voltage Reset Voltage Low Voltage Detector Voltage Additional Current for LVR Enable Additional Current for LVD Enable Test Conditions VDD — Conditions Min. Typ. Max. Unit LVR enable, 2.1V 2.1 LVR enable, 2.55V 2.55 LVR enable, 3.15V -5% V 3.15 +5% V V LVR enable, 3.8V 3.8 V — LVDEN=1, VLVD=2.0V 2.0 V — LVDEN=1, VLVD=2.2V 2.2 V — LVDEN=1, VLVD=2.4V 2.4 V — LVDEN=1, VLVD=2.7V 2.7 — LVDEN=1, VLVD=3.0V — LVDEN=1, VLVD=3.3V 3.3 V — LVDEN=1, VLVD=3.6V 3.6 V — LVDEN=1, VLVD=4.0V 4.0 -5% +5% 3.0 V V V 5V±3% LVR Disable → LVR Enable ─ 60 90 μA LVD Disable → LVD Enable (LVR Disabled) ─ 75 115 μA LVD Disable → LVD Enable (LVR Enabled) ─ 60 90 μA 5V±3% tLVR LVR Minimum Low Voltage Width to Reset — — 120 240 480 μs tLVD LVD Minimum Low Voltage Width to Interrupt — — 60 120 240 μs Rev. 1.00 14 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Symbol Test Conditions Parameter tLVDS LVDO Stable Time tSRESET Software Reset Width to Reset VDD Conditions Min. Typ. Max. Unit — For LVR enable, LVD off → on — — 15 μs — For LVR disable, LVD off → on — — 150 μs — — 45 90 120 μs Note: VLVR or VLVD is the MCU operating voltage level under which a LVR reset or LVD interrupt occurs. Over Current/Voltage Protection Electrical Characteristics Ta=25°C Symbol IOCVP VOS_CMP VHYS VCM_CMP VOS_OPA VCM_OPA VOR Rev. 1.00 Parameter Operating Current Comparator Input Offset Voltage Hysteresis Comparator Common Mode Voltage Range OPA Input Offset Voltage OPA Common Mode Voltage Range OPA Maximum Output Voltage Range Test Conditions VDD 3V Conditions Min. Typ. Max. Unit — — 1250 μA — 730 1250 μA 3V Without calibration (OCVPCOF[4:0]=10000B) -15 — 15 mV 5V Without calibration (OCVPCOF[4:0]=10000B) -15 — 15 mV 3V With calibration -4 — 4 mV 5V With calibration -4 — 4 mV 60 mV 5V DAC VREF=2.5V 3V — 20 40 5V — 20 40 60 mV V 3V — VSS — VDD - 1.4 5V — VSS — VDD - 1.4 V 3V Without calibration (OCVPOOF[5:0]=100000B) -15 — 15 mV 5V Without calibration (OCVPOOF[5:0]=100000B) -15 — 15 mV 3V With calibration -4 — 4 mV 5V With calibration -4 — 4 mV V 3V — VSS — VDD - 1.4 5V — VSS — VDD - 1.4 V 3V — VSS + 0.1 — VDD - 0.1 V 5V — VSS + 0.1 — VDD - 0.1 V 15 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Symbol Ga Parameter PGA Gain Accuracy DNL Differential Non-linearity INL Integral Non-linearity Test Conditions Min. Typ. In non-inverting mode, R2/R1 ≤ 50, using internal resistor, and input voltage > 80mV -5 — 5 % In non-inverting mode, R2/R1=65 or 80 , using internal resistor, and input voltage > 50mV -8 — 8 % In non-inverting mode, R2/R1= 130, using internal resistor, and input voltage > 35mV -10 — 10 % In inverting mode, R2/R1 ≤ 50, using internal resistor, and -300mV < input voltage < -80mV -5 — 5 % In inverting mode, R2/R1=65 or 80, using internal resistor, and -300mV < input voltage < -50mV -8 — 8 % In inverting mode, R2/R1= 130, using internal resistor, and -300mV < input voltage < -35mV -10 — 10 % 3V DAC VREF=VDD — — ±2 LSB 5V DAC VREF=VDD — — ±1 LSB 3V DAC VREF=VDD — — ±2 LSB 5V DAC VREF=VDD — — ±1.5 LSB VDD 3V/ 5V Conditions Max. Unit Power on Reset Electrical Characteristics Ta=25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset — — — — 100 mV RRPOR VDD Rising Rate to Ensure Power-on Reset — — 0.035 — — V/ms tPOR Minimum Time for VDD Stays at VPOR to Ensure Power-on Reset — — 1 — — ms VDD tPOR RRPOR VPOR Rev. 1.00 16 Time May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either an HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clock and Pipelining For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Rev. 1.00 17 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as "JMP" or "CALL" that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Program Counter Program Counter High byte PCL Register PC10~PC8 PCL7~PCL0 The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.00 18 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k B o tto m S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r S ta c k L e v e l 3 o f S ta c k C o u n te r P ro g ra m M e m o ry S ta c k L e v e l 4 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC • Increment and Decrement: INCA, INC, DECA, DEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Rev. 1.00 19 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 2K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. 000H 004H 0�4H 7FFH Reset Interrupt Vectors 1� bits Program Memory Structure Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the "TABRD[m]" or "TABRDL[m]" instructions, respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r Rev. 1.00 D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te 20 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is "700H" which refers to the start address of the last page within the 2K words Program Memory of the device. The table pointer is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "706H" or 6 locations after the start of the TBHP specified page. Note that the value for the table pointer is referenced to the first address specified by the TBHP and TBLP registers if the "TABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page or specific page mov a,07h ; initialise high table pointer mov tbhp,a : : tabrd tempreg1 ; transfers value in table referenced by table pointer ; data at program memory address "706H" transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrd tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address "705H" transferred to tempreg2 and TBLH ; in this example the data "1AH" is transferred to tempreg1 and data "0FH" ; to register tempreg2, the value 00H will be transferred to the high ; byte register TBLH : : org 700h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : Rev. 1.00 21 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Write Pins MCU Programming Pins ICPDA PA0 Programming Serial Data/Address Function ICPCK PA2 Programming Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user must take care of the ICPDA and ICPCK pins for data and clock programming purpose to ensure that no other outputs are connected to these two pins. W r ite r C o n n e c to r S ig n a ls M C U P r o g r a m m in g P in s V D D W r ite r _ V D D P A 0 IC P D A IC P C K P A 2 W r ite r _ V S S V S S * * T o o th e r C ir c u it Note: * may be resistor or capacitor. The resistance of * must be greater than 1kΩ or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS The device has an EV chip named HT45V3830 which is used to emulate the HT45F3830 device. This EV chip device also provides an "On-Chip Debug" function to debug the real MCU device during the development process. The EV chip and the real MCU device are almost functionally compatible except for the "On-Chip Debug" function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HTIDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other Rev. 1.00 22 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU functions which are shared with the OCDSDA and OCDSCK pins in the device will have no effect in the EV chip. However, the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP. For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins EV Chip Pins Pin Description OCDSDA OCDSDA On-chip Debug Support Data/Address input/output OCDSCK OCDSCK On-chip Debug Support Clock input VDD VDD Power Supply GND VSS Ground RAM Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Structure Divided into two sections, the first of these is an area of RAM, known as the Special Purpose Data Memory. Here are located registers which are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is known as the General Purpose Data Memory, which is reserved for general purpose use. All locations within this area are read and write accessible under program control. The overall Data Memory is subdivided into two banks. The Special Purpose Data Memory registers are accessible in all banks, with the exception of the EEC register at address 40H, which is only accessible in Bank 1. Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value. The start address of the Data Memory for the device is the address 00H. Special Purpose Data Memory General Purpose Data Memory Address Capacity Address Bank 0: 00H~7FH Bank 1: 00H~7FH 128×8 Bank 0: 80H~FFH 00H EEC Special Purpose Data �emor� Bank 1 7FH 80H General Purpose Data �emor� FFH Bank 0 Data Memory Structure Rev. 1.00 23 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user programing for both reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value "00H". Bank 0� 1 00H Bank 0 IAR0 �5H Bank 1 Unused 01H �P0 ��H PC 0�H IAR1 �7H PCC 0�H �P1 �8H PCPU 04H BP �9H CTRL� 05H ACC �AH CTRL� 0�H PCL �BH CTRL4 07H TBLP �CH CTRL5 08H TBLH �DH PB 09H TBHP �EH PBC 0AH STATUS �FH 0BH S�OD 40H 0CH LVDC 41H 0DH INTEG 4�H 0EH INTC0 4�H SLEWC0 0FH INTC1 44H SLEDC0 10H INTC� 45H SLEDC1 11H �FI0 4�H PT�0C0 1�H �FI1 47H PT�0C1 1�H �FI� 48H PT�0DL 14H PA 49H PT�0DH PBPU Unused EEC Unused 15H PAC 4AH PT�0AL 1�H PAPU 4BH PT�0AH 17H PAWU 4CH PT�0RPL 18H �FI� 4DH PT�0RPH PT�1C0 19H Unused 4EH 1AH WDTC 4FH PT�1C1 1BH TBC 50H PT�1DL 1CH Unused 51H PT�1DH 1DH Unused 5�H 1EH EEA 5�H PT�1AH 1FH EED 54H PT�1RPL 55H PT�1RPH �0H �1H ��H Unused ��H PT�1AL 5�H IICC0 57H IICC1 58H IICD �4H FADJL 59H IICA �5H FADJH 5AH IICTOC ��H CTRL 5BH OCVPC0 �7H LVRC 5CH OCVPC1 �8H CT�C0 5DH OCVPC� �9H CT�C1 5EH OCVPDA �AH CT�DL 5FH OCVPOCAL �BH CT�DH �0H OCVPCCAL �CH CT�AL �1H SCO�C �DH CT�AH ��H �EH Unused �FH ST�C0 �0H ST�C1 �1H ST�DL ��H ST�DH ��H ST�AL �4H ST�AH Unused 7FH : Unused� read as 00H Special Purpose Data Memory Structure Rev. 1.00 24 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0 or MP1. Acting as a pair, IAR0 and MP0 can together access data from Bank 0 while the IAR1 and MP1 register pair can access data from any bank. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1 Two Memory Pointers, known as MP0 and MP1 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0, while MP1 and IAR1 are used to access data from all banks according to BP register. Direct Addressing can only be used within Bank 0, all other Banks must be addressed indirectly using MP1 and IAR1. The following example shows how to clear a section of four Data Memory locations already defined as locations adres1 to adres4. Indirect Addressing Program Example data .section ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by mp0 inc mp0; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 25 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bank Pointer – BP For this device, the Data Memory is divided into two banks, Bank0 and Bank1. Selecting the required Data Memory area is achieved using the Bank Pointer. Bit 0 of the Bank Pointer is used to select Data Memory Bank 0 or 1. The Data Memory is initialised to Bank 0 after a reset, except for a WDT time-out reset in the Power down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that the Special Purpose Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within any bank. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Accessing data from Bank1 must be implemented using Indirect Addressing. BP Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — DMBP0 R/W — — — — — — — R/W POR — — — — — — — 0 Bit 7 ~ 1 Unimplemented, read as "0" Bit 0DMBP0: Select Data Memory Banks 0: Bank 0 1: Bank 1 Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Rev. 1.00 26 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instruction, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the "CLR WDT" or "HALT" instruction. The PDF flag is affected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction. • TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Rev. 1.00 27 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU STATUS Register Bit 7 6 5 4 3 2 1 0 Name — — TO PDF OV Z AC C R/W — — R R R/W R/W R/W R/W POR — — 0 0 x x x x "x" unknown Bit 7~6 Unimplemented, read as "0" Bit 5TO: Watchdog Time-out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.00 28 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU EEPROM Data Memory One of the special features in the device is its internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is up to 64×8 bits. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped and is therefore not directly accessible in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Bank 0 and a single control register in Bank 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in Bank 0, they can be directly accessed in the same way as any other Special Function Register. The EEC register however, being located in Bank 1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1 Memory Pointer and Indirect Addressing Register, IAR1. Because the EEC control register is located at address 40H in Bank 1, the MP1 Memory Pointer must first be set to the value 40H and the Bank Pointer register, BP, set to the value, 01H, before any operations on the EEC register are executed. Bit Register Name 7 6 5 4 3 2 1 0 EEA — — D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Control Register List EEA Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 ~ 0 Data EEPROM address Data EEPROM address bit 5 ~ bit 0 29 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD cannot be set to "1" at the same time in one instruction. The WR and RD cannot be set to "1" at the same time. Rev. 1.00 30 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered on, the Write enable bit in the control register will be cleared preventing any write operations. Also at power-on the Bank Pointer, BP, will be reset to zero, which means that Data Memory Bank 0 will be selected. As the EEPROM control register is located in Bank 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. However as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must also be set. When an EEPROM write cycle ends, the DEF request flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multifunction interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. More details can be obtained in the Interrupt section. Rev. 1.00 31 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1 where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally completed, otherwise, the EEPROM read or write operation will fail. Programming Examples • Reading data from the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1 ; MP1 points to EEC register ; setup Bank Pointer ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM write ; move read data to register • Writing Data to the EEPROM – polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1, A MOV A, 01H MOV BP, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR BP Rev. 1.00 ; user defined address ; user defined data ; ; ; ; setup memory pointer MP1 MP1 points to EEC register setup Bank Pointer BP points to data memory bank 1 ; set WREN bit, enable write operations ; start Write Cycle - set WR bit — executed immediately ; after set WREN bit ; check for write cycle end ; disable EEPROM write 32 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Oscillators Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. Fully integrated internal oscillators, requiring no external components, are provided to form a range of both fast and slow system oscillators. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Freq. Internal High Speed RC HIRC 12MHz (adjustable) Internal Low Speed RC LIRC 32kHz Oscillator Types System Clock Configurations There are two methods of generating the system clock, a high speed internal RC oscillator and a low speed internal RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for the high speed and the low speed oscillators is chosen via registers. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a nooscillator selection for either the high or low speed oscillator. fH/� High Speed Oscillator HIRC fH/4 Frequenc� Adjusting Circuit fH fH/8 Prescaler fH/1� fSYS fH/�� fH/�4 ADJ[8:0] bits fSUB LIRC Low Speed Oscillator HLCLK� CKS[�:0] bits System Clock Configurations Rev. 1.00 33 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Internal RC Oscillator – HIRC The internal high speed RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a frequency of 12MHz which can be adjusted by changing the ADJ[8:0] bits field value. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Note that if this internal system clock option is selected, it requires no external pins for its operation. The ADJ[8:0] bit field in the FADJH and FADJL registers is used to adjust the HIRC oscillation frequency. The HIRC oscillator is supposed to have a frequency of 12MHz with the default ADJ[8:0] field value, 100000000B. The greater value the ADJ[8:0] field is written, the lower frequency the HIRC oscillator has. The HIRC oscillator will have a maximum adjusted frequency when the ADJ[8:0] field is set to 000000000B. Note that a certain time delay for the HIRC oscillator stabilization should be allowed when the HIRC oscillation frequency is changed by configuring the ADJ[8:0] field. The new HIRC frequency cannot be used until the updated frequency is stable. FADJL Register Bit 7 6 5 4 3 2 1 0 Name ADJ7 ADJ6 ADJ5 ADJ4 ADJ3 ADJ2 ADJ1 ADJ0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0ADJ7~ADJ0: HIRC frequency adjustment control bit 7 ~ bit 0 FADJH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — — ADJ8 R/W — — — — — — — R/W POR — — — — — — — 1 Bit 7~1 Unimplemented, read as "0" Bit 0ADJ8: HIRC frequency adjustment control bit 8 Internal 32kHz Oscillator – LIRC The Internal 32kHz system oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Rev. 1.00 34 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency fH or low frequency fSUB source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from the HIRC oscillator. The low speed system clock source can be sourced from the LIRC oscillator. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. fH/� High Speed Oscillator HIRC fH/4 Frequenc� Adjusting Circuit fH fH/8 Prescaler fSYS fH/�� fH/�4 ADJ[8:0] bits LIRC fH/1� fSUB HLCLK� CKS[�:0] bits Low Speed Oscillator fSUB To peripherals fS fTBC WDT fTB fSYS/4 Time Base TBCK Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillator will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Rev. 1.00 35 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU System Operating Modes There are six different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are two modes allowing normal operation of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP0, SLEEP1, IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operating Mode Description CPU fSYS fH fSUB NORMAL mode On fH~fH/64 On On SLOW mode On fSUB Off On ILDE0 mode Off Off Off On IDLE1 mode Off On On/Off On SLEEP0 mode(Note) Off Off Off Off SLEEP1mode Off Off Off On Note: If the Watchdog Timer configuration option is "Always enabled" which means the fSUB clock must always be on, there is not SLEEP0 mode. NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator. This mode operates allowing the microcontroller to operate normally with a clock source will come from the high speed oscillator, HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from fSUB. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP0 Mode If the WDT configuration option is "Always enabled", there is not SLEEP0 mode. If the WDT configuration option is "controlled by WDTC register" the MCU can enter the SLEEP0 mode. The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP0 mode the CPU will be stopped, and the fSUB and fS clocks will be stopped too, and the Watchdog Timer function is disabled. In this mode, the LVDEN is must cleared to zero. If the LVDEN is set high, it won’t enter the SLEEP0 Mode. SLEEP1 Mode The SLEEP Mode is entered when an HALT instruction is executed and when the IDLEN bit in the SMOD register is low. In the SLEEP1 mode the CPU will be stopped. However the fSUB and fS clocks will continue to operate if the LVDEN is "1" or the Watchdog Timer function is enabled. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU, the system oscillator will be stopped, the low frequency clock fSUB will be on to drive some peripheral functions. Rev. 1.00 36 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU IDLE1 Mode The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the low frequency clock fSUB will be on to drive some peripheral functions. Note: If LVDEN=1 and the SLEEP or IDLE mode is entered, the LVD and bandgap functions will not be disabled, and the fSUB clock will be forced to be enabled. Control Registers The SMOD and CTRL registers are used to control the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 1 1 0 — 0 0 1 0 Bit 7 ~ 5 CKS2 ~ CKS0: The system clock selection when HLCLK is "0" 000: fSUB 001: fSUB 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as "0" Bit 3LTO: LIRC System OSC SST ready flag 0: Not ready 1: Ready This is the low speed system oscillator SST ready flag which indicates when the low speed system oscillator is stable after power on reset or a wake-up has occurred. The flag will change to a high level after 1~2 cycles. Bit 2HTO: HIRC System OSC SST ready flag 0: Not ready 1: Ready This is the high speed system oscillator SST ready flag which indicates when the high speed system oscillator is stable after a wake-up has occurred. This flag is cleared to "0" by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as "1" by the application program after device power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC oscillator is used. Rev. 1.00 37 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 1IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: System Clock Selection 0: fH/2 ~ fH/64 or fSUB 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fSUB clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fSUB clock will be selected. When system clock switches from the fH clock to the fSUB clock and the fH clock will be automatically switched off to conserve power. CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — R/W R/W — — — — LVRF LRF WRF R/W R/W POR 0 — — — — R/W x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6 ~ 3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag Described elsewhere Bit 1LRF: LVRC control register software reset flag Described elsewhere Bit 0WRF: WDTC control register software reset flag Described elsewhere Rev. 1.00 38 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when the device moves between the various operating modes. IDLE1 HALT instruction executed CPU stop IDLEN=1 FSYSON=1 fSYS on fSUB on NORMAL fSYS=fH~fH/�4 fH on CPU run fSYS on fSUB on SLEEP0 HALT instruction executed fSYS off CPU stop IDLEN=0 fSUB off WDT & LVD off IDLE0 HALT instruction executed CPU stop IDLEN=1 FSYSON=0 fSYS off fSUB on SLEEP1 HALT instruction executed fSYS off CPU stop IDLEN=0 fSUB on WDT or LVD on SLOW fSYS=fSUB fSUB on CPU run fSYS on fSUB on fH off Note: If the Watchdog Timer configuration option is "Always enabled" which means the fSUB clock must always be on, there is not SLEEP0 mode. Rev. 1.00 39 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU NORMAL Mode to SLOW Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW Mode by setting the HLCLK bit to "0" and setting the CKS2~CKS0 bits to "000" or "001" in the SMOD register. This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC oscillator and therefore requires this oscillator to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. NORMAL Mode CKS�~CKS0 = 00xB & HLCLK = 0 SLOW Mode WDT and LVD are all off IDLEN = 0 HALT instruction is executed SLEEP0 Mode WDT or LVD is on IDLEN = 0 HALT instruction is executed SLEEP1 Mode IDLEN = 1� FSYSON = 0 HALT instruction is executed IDLE0 Mode IDLEN = 1� FSYSON = 1 HALT instruction is executed IDLE1 Mode Rev. 1.00 40 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU SLOW Mode to NORMAL Mode Switching In SLOW Mode the system uses LIRC low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to "1" or HLCLK bit is "0", but CKS2~CKS0 is set to "010", "011", "100", "101", "110" or "111". As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. SLOW Mode CKS�~CKS0 = 000B� 001B as HLCLK = 0 or HLCLK = 1 NORMAL Mode WDT and LVD are all off IDLEN = 0 HALT instruction is executed SLEEP0 Mode WDT or LVD is on IDLEN = 0 HALT instruction is executed SLEEP1 Mode IDLEN = 1� FSYSON = 0 HALT instruction is executed IDLE0 Mode IDLEN = 1� FSYSON = 1 HALT instruction is executed IDLE1 Mode Entering the SLEEP0 Mode There is only one way for the device to enter the SLEEP0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT and LVD are both off. When this instruction is executed under the conditions described above, the following will occur: • The system clock and the fSUB clock will be stopped and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and stopped. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 41 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Entering the SLEEP1 Mode There is only one way for the device to enter the SLEEP1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "0" and the WDT or LVD is on. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction but the WDT or LVD will remain with the clock source coming with the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting as the WDT is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the "HALT" instruction, but the low frequency fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions as it is enabled. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HALT" instruction in the application program with the IDLEN bit in SMOD register equal to "1" and the FSYSON bit in CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur: • The system clock and the low frequency fSUB will be on and the application program will stop at the "HALT" instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting as it is enabled. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 42 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. The actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the "HALT" instruction. The TO flag is set if a WDT time-out occurs, and causes a wakeup that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the "HALT" instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HALT" instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Rev. 1.00 43 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the internal fS clock which is in turn supplied by the LIRC oscillator. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. The LIRC internal oscillator has an approximate period of 32kHz at a supply voltage of 5V. However, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable/disable operation. This register together with the configuration option control the overall operation of the Watchdog Timer. WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3WE4~WE0: WDT function enable/disable control If the WDT configuration option is "Always enabled": 10101 or 01010: Enable Others: Reset MCU If the WDT configuration option is "Controlled by WDTC register": 10101: Disable 01010: Enable Others: Reset MCU When these bits are changed by the environmental noise or software setting to reset the microcontroller, the reset operation will be activated after a delay time, tSRESET and the WRF bit in the CTRL register will be set high. Bit 2~0WS2~WS0: WDT time-out period selection 000: 28/fS 001: 210/fS 010: 212/fS 011: 214/fS 100: 215/fS 101: 216/fS 110: 217/fS 111: 218/fS These three bits determine the division ratio of the Watchdog Timer source clock, which in turn determines the timeout period. Rev. 1.00 44 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — R/W R/W — — — — LVRF LRF WRF R/W R/W R/W POR 0 — — — — x 0 0 "x" unknown Bit 7FSYSON: fSYS Control in IDLE Mode Described elsewhere. Bit 6~3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag Described elsewhere. Bit 1LRF: LVRC Control register software reset flag Described elsewhere. Bit 0WRF: WDTC Control register software reset flag 0: Not occur 1: Occurred This bit is set high by the WDT Control register software reset and cleared by the application program. Note that this bit can only be cleared to zero by the application program. Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, these clear instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/disable function, there are also five bits, WE4~WE0, in the WDTC register to offer additional enable/disable and reset control of the Watchdog Timer. If the WDT configuration option is that the WDT function is always enabled, the WE4~WE0 bits still have effects on the WDT function. When the WE4~WE0 bits value is equal to 01010B or 10101B, the WDT function is enabled. However, if the WE4~WE0 bits are changed to any other values except 01010B and 10101B, which is caused by the environmental noise or software setting, it will reset the microcontroller after a delay time, tSRESET. If the WDT configuration option is that the WDT function is controlled by the WDTC register, the WE4~WE0 values can determine which mode the WDT operates in. The WDT function will be disabled when the WE4~WE0 bits are set to a value of 10101B. The WDT function will be enabled if the WE4~WE0 bits value is equal to 01010B. If the WE4~WE0 bits are set to any other values except 01010B and 10101B by the environmental noise or software setting, it will reset the device after a delay time, tSRESET. After power on these bits will have the value of 01010B. WDT Configuration Option Always Enabled WE4 ~ WE0 Bits WDT Function 01010B or 10101B Enable Any other values Reset MCU 10101B Disable Controlled by WDTC Register 01010B Enable Any other values Reset MCU Watchdog Timer Enable/Disable Control Rev. 1.00 45 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 bit filed, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single "CLR WDT" instruction to clear the WDT. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC Register WE4~WE0 bits Reset �CU CLR “CLR WDT” Instruction “HALT” Instruction LIRC fS 8-stage Divider fS/�8 WS�~WS0 WDT Prescaler WDT Time-out 8-to-1 �UX Watchdog Timer Rev. 1.00 46 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring internally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Power-on Reset tRSTD SST Time-out Power-On Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The LVR function is always enabled with a specific LVR voltage, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set high. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the LVD&LVR characteristics table. If the low voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. Rev. 1.00 47 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU The actual VLVR is defined by the LVS7~LVS0 bits in the LVRC register. If the LVS7~LVS0 bits are changed to any other value except some certain values defined in the LVRC register by the environmental noise, the LVR will reset the device after a delay time, tSRESET. When this happens, the LRF bit in the CTRL register will be set high. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Low Voltage Reset Timing Chart • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7 ~ 0 LVS7 ~ LVS0: LVR Voltage Select control 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: MCU reset – register is reset to POR value When an actual low voltage condition occurs, an MCU reset will be generated. The reset operation will be activated after the low voltage condition keeps more than a tLVR time. In this situation this register contents will remain the same after such a reset occurs. Any register value, other than the defined values above, will also result in the generation of an MCU reset. The reset operation will be activated after a delay time, tSRESET. However in this situation this register contents will be reset to the POR value. • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — R/W R/W — — — — LVRF LRF WRF R/W R/W POR 0 — — — — R/W x 0 0 "x" unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Described elsewhere Bit 6 ~ 3 Unimplemented, read as "0" Bit 2LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set high when a specific low voltage reset situation condition occurs. This bit can only be cleared to zero by application program. Bit 1LRF: LVRC control register software reset flag 0: Not occurred 1: Occurred This bit is set high when the LVRC register contains any undefined LVR voltage register value. This in effect acts like a software reset function. This bit can only be cleared to zero by application program. Bit 0WRF: WDTC control register software reset flag Described elsewhere Rev. 1.00 48 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as a LVR reset except that the Watchdog time-out flag TO will be set high. WDT Time-out Reset during Normal Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to zero and the TO flag will be set high. Refer to the A.C. Characteristics for tSST details. WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 0 Power-on reset RESET Conditions u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: "u" stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Rev. 1.00 Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack 49 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Reset (Power On) WDT Time-out (Normal Operation) WDT Time-out (SLEEP/IDLE) MP0 xxxx xxxx uuuu uuuu uuuu uuuu MP1 xxxx xxxx uuuu uuuu uuuu uuuu BP ---- ---0 ---- ---0 ---- ---u ACC xxxx xxxx uuuu uuuu uuuu uuuu Register Rev. 1.00 PCL 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu TBHP ---- -xxx ---- -uuu ---- -uuu STATUS --00 xxxx --1u uuuu - - 11 u u u u SMOD 11 0 - 0 0 1 0 11 0 - 0 0 1 0 uuu- uuuu LVDC --00 -000 --00 -000 --uu -uuu INTEG ---- 0000 ---- 0000 ---- uuuu INTC0 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 uuuu uuuu INTC2 --00 --00 --00 --00 --uu --uu MFI0 --00 --00 --00 --00 --uu --uu MFI1 --00 --00 --00 --00 --uu --uu MFI2 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 uuuu uuuu PAPU 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 uuuu uuuu MFI3 -000 -000 -000 -000 -uuu -uuu WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu TBC 0 0 11 - 111 0 0 11 - 111 uuuu -uuu EEA --00 0000 --00 0000 --uu uuuu EED 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- uuuu FADJL 0000 0000 0000 0000 uuuu uuuu FADJH ---- ---1 ---- ---1 ---- ---u CTRL 0--- -x00 0--- -000 u--- -uuu LVRC 0101 0101 0101 0101 uuuu uuuu CTMC0 0000 0000 0000 0000 uuuu uuuu CTMC1 0000 0000 0000 0000 uuuu uuuu CTMDL 0000 0000 0000 0000 uuuu uuuu CTMDH ---- --00 ---- --00 ---- --uu CTMAL 0000 0000 0000 0000 uuuu uuuu CTMAH ---- --00 ---- --00 ---- --uu STMC0 0000 0000 0000 0000 uuuu uuuu STMC1 0000 0000 0000 0000 uuuu uuuu STMDL 0000 0000 0000 0000 uuuu uuuu STMDH ---- --00 ---- --00 ---- --uu STMAL 0000 0000 0000 0000 uuuu uuuu 50 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Reset (Power On) Register WDT Time-out (Normal Operation) WDT Time-out (SLEEP/IDLE) STMAH ---- --00 ---- --00 ---- --uu PC - - 11 1111 - - 11 1111 --uu uuuu PCC - - 11 1111 - - 11 1111 --uu uuuu PCPU --00 0000 --00 0000 --uu uuuu CTRL2 ---- -000 ---- -000 ---- -uuu CTRL3 0000 0000 0000 0000 uuuu uuuu CTRL4 --00 0000 --00 0000 --uu uuuu CTRL5 ---- 0000 ---- 0000 ---- uuuu PB 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 uuuu uuuu SLEWC0 ---- --00 ---- --00 ---- --uu SLEDC0 0000 0000 0000 0000 uuuu uuuu SLEDC1 ---- 0000 ---- 0000 ---- uuuu PTM0C0 0000 0--- 0000 0--- uuuu u--- PTM0C1 0000 0000 0000 0000 uuuu uuuu PTM0DL 0000 0000 0000 0000 uuuu uuuu PTM0DH ---- --00 ---- --00 ---- --uu PTM0AL 0000 0000 0000 0000 uuuu uuuu PTM0AH ---- --00 ---- --00 ---- --uu PTM0RPL 0000 0000 0000 0000 uuuu uuuu PTM0RPH ---- --00 ---- --00 ---- --uu PTM1C0 0000 0--- 0000 0--- uuuu u--- PTM1C1 0000 0000 0000 0000 uuuu uuuu PTM1DL 0000 0000 0000 0000 uuuu uuuu PTM1DH ---- --00 ---- --00 ---- --uu PTM1AL 0000 0000 0000 0000 uuuu uuuu PTM1AH ---- --00 ---- --00 ---- --uu PTM1RPL 0000 0000 0000 0000 uuuu uuuu PTM1RPH ---- --00 ---- --00 ---- --uu IICC0 ---- 000- ---- 000- ---- uuu- IICC1 1000 0001 1000 0001 uuuu uuuu IICD xxxx xxxx xxxx xxxx xxxx xxxx IICA 0000 000- 0000 000- uuuu uuu- IICTOC 0000 0000 0000 0000 uuuu uuuu OCVPC0 11 0 0 1 0 0 0 11 0 0 1 0 0 0 uuuu uuuu OCVPC1 0000 --00 0000 --00 uuuu --uu OCVPC2 -000 0000 -000 0000 -uuu uuuu OCVPDA 0000 0000 0000 0000 uuuu uuuu OCVPOCAL 0010 0000 0010 0000 uuuu uuuu OCVPCCAL 0001 0000 0001 0000 uuuu uuuu SCOMC -000 ---- -000 ---- -uuu ---- Note: "-" stands for unimplemented "u" stands for unchanged "x" stands for unknown Rev. 1.00 51 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PC. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC — — PC5 PC4 PC3 PC2 PC1 PC0 PCC — — PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PCPU — — PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 I/O Ports Register List Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PCPU, and are implemented using weak PMOS transistors. Note that only when the I/O ports are configured as digital input or NMOS output, the internal pullhigh functions can be enabled using the PAPU~PCPU registers. In other conditions, internal pullhigh functions are disabled. PAPU Register Bit 7 6 5 4 3 2 1 0 Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0PAPU7~PAPU0: Port A Pin Pull-high Control 0: Disable 1: Enable Rev. 1.00 52 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU PBPU Register Bit 7 6 5 4 3 2 1 0 Name PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0PBPU7~PBPU0: Port B Pin Pull-high Control 0: Disable 1: Enable PCPU Register Bit 7 6 5 4 3 2 1 0 Name — — PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5~0PCPU5~PCPU0: Port C Pin Pull-high Control 0: Disable 1: Enable Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. Note that only when the Port A pins are configured as general purpose I/Os and the device is in the HALT status, the Port A wake-up functions can be enabled using the relevant bits in the PAWU register. In other conditions, the wake-up functions are disabled. PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0PAWU7~PAWU0: Port A Pin Wake-up Control 0: Disable 1: Enable I/O Port Control Registers Each I/O port has its own control register known as PAC~PCC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Rev. 1.00 53 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU PAC Register Bit 7 6 5 4 3 2 1 0 Name PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7 ~ 0PAC7~PAC0: Port A Pin Input/Output Type Selection 0: Output 1: Input PBC Register Bit 7 6 5 4 3 2 1 0 Name PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7~0PBC7~PBC0: Port B Pin Input/Output Type Selection 0: Output 1: Input PCC Register Bit 7 6 5 4 3 2 1 0 Name — — PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 1 1 1 1 1 1 Bit 7~6 Unimplemented, read as "0" Bit 5~0PCC5~PCC0: Port C Pin Input/Output Type Selection 0: Output 1: Input Slew Rate Control The PC1 port can be setup to have a choice of various slew rate using the SLEWC0 register. Refer to the Slew Rate Control Characteristics section to obtain the exact value. SLEWC0 Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — SLEWC01 SLEWC00 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as “0” Bit 1~0SLEWC01~SLEW00: PC1 output slew rate selection 00: Slew rate = Level 0 01: Slew rate = Level 1 10: Slew rate = Level 2 11: Slew rate = Level 3 Note: Users should refer to the Slew Rate Control Characteristics section to obtain the exact value for different applications. Rev. 1.00 54 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Source Current Selection Each pin in this device can be configured with different output source current which is selected by the corresponding source current selection bits. These source current selection bits are available when the corresponding pin is configured as a CMOS output. Otherwise, these selection bits have no effect. Users should refer to the D.C. Characteristics section to obtain the exact value for different applications. Bit Register Name 7 6 5 4 3 2 1 0 SLEDC0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00 SLEDC1 — — — — SLEDC13 SLEDC12 SLEDC11 SLEDC10 I/O Port Source Current Selection Register List SLEDC0 Register Bit Name 7 6 5 4 3 2 1 0 SLEDC07 SLEDC06 SLEDC05 SLEDC04 SLEDC03 SLEDC02 SLEDC01 SLEDC00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6SLEDC07~SLEDC06: PB7~PB4 source current selection 00: Source current = Level 0 (Min.) 01: Source current = Level 1 10: Source current = Level 2 11: Source current = Level 3 (Max.) Bit 5~4SLEDC05~SLEDC04: PB3~PB0 source current selection 00: Source current = Level 0 (Min.) 01: Source current = Level 1 10: Source current = Level 2 11: Source current = Level 3 (Max.) Bit 3~2SLEDC03~SLEDC02: PA7~PA4 source current selection 00: Source current = Level 0 (Min.) 01: Source current = Level 1 10: Source current = Level 2 11: Source current = Level 3 (Max.) Bit 1~0SLEDC01~SLEDC00: PA3~PA0 source current selection 00: Source current = Level 0 (Min.) 01: Source current = Level 1 10: Source current = Level 2 11: Source current = Level 3 (Max.) Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications Rev. 1.00 55 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU SLEDC1 Register Bit 7 6 5 4 Name — — — — R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 3 2 1 0 SLEDC13 SLEDC12 SLEDC11 SLEDC10 Unimplemented, read as “0” Bit 3~2SLEDC13~SLEDC12: PC5 and PC4 source current selection 00: Source current = Level 0 (Min.) 01: Source current = Level 1 10: Source current = Level 2 11: Source current = Level 3 (Max.) Bit 1~0SLEDC11~SLEDC10: PC3, PC2 and PC0 source current selection 00: Source current = Level 0 (Min.) 01: Source current = Level 1 10: Source current = Level 2 11: Source current = Level 3 (Max.) Note: Users should refer to the D.C. Characteristics section to obtain the exact value for different applications Pin-shared Function The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For these pins, the desired function of the multi-function I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can impose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several different functions and providing a means of function selection, a wide range of different functions can be incorporated into even relatively small package sizes. The device includes the CTRL3 and CTRL4 registers which can select the desired functions of the multi-function pin-shared pins. The most important point to note is to make sure that the desired pin-shared function is properly selected and also deselected. To select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register. After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. To correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions. Bit Register Name 7 6 5 4 3 CTRL2 — — — — — CTRL3 IOCN7 IOCN6 IOCN5 IOCN4 IOCN3 IOCN2 IOCN1 IOCN0 CTRL4 — — IOCN13 IOCN12 IOCN11 IOCN10 IOCN9 IOCN8 CTRL5 — — — — IOCN19 IOCN18 IOCN17 IOCN16 2 1 0 OCVPS2 OCVPS1 OCVPS0 Pin-shared Function Selection Register List Rev. 1.00 56 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU • CTRL2 Register Bit 7 6 5 4 3 Name — — — — — 2 1 0 R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 OCVPS2 OCVPS1 OCVPS0 Bit 7~3 Unimplemented, read as "0" Bit 2~0 OCVPS2 ~ OCVPS0: OCVPAI0 signal input source pin selection 000: PB0 001: PB1 010: PB2 011: PB3 100: PA6 101: PA3 110: PA1 111: PA4 • CTRL3 Register Bit 7 6 5 4 3 2 1 0 Name IOCN7 IOCN6 IOCN5 IOCN4 IOCN3 IOCN2 IOCN1 IOCN0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6IOCN7~IOCN6: PA6 pin function selection 00: PA6 01: PTP0 10: OCVPAI0 11: OCVPAI0 Bit 5IOCN5: PA5 pin function selection 0: PA5/INT1/STCK 1: OCVPCI Bit 4~3IOCN4~IOCN3: PA4 pin function selection 00: PA4 01: STP 10: OCVPAI0 11: OCVPAI0 Bit 2IOCN2: PA3 pin function selection 0: PA3/INT0/CTCK 1: OCVPAI0 Bit 1~0IOCN1~IOCN0: PA1 pin function selection 00: PA1 01: CTP 10: OCVPAI0 11: OCVPAI0 Rev. 1.00 57 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU • CTRL4 Register Bit 7 6 5 4 3 2 1 0 Name — — IOCN13 IOCN12 IOCN11 IOCN10 IOCN9 IOCN8 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5IOCN13: PC1 pin function selection 0: PC1 1: PTP1 Bit 4IOCN12: PB3 pin function selection 0: PB3 1: OCVPAI0 Bit 3IOCN11: PB2 pin function selection 0: PB2 1: OCVPAI0 Bit 2IOCN10: PB1 pin function selection 0: PB1 1: OCVPAI0 Bit 1IOCN9: PB0 pin function selection 0: PB0 1: OCVPAI0 Bit 0IOCN8: PA7 pin function selection 0: PA7/PTCK0 1: VREF • CTRL5 Register Bit 7 6 5 4 3 2 1 0 Name — — — — IOCN19 IOCN18 IOCN17 IOCN16 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3IOCN19: PB7 pin function selection 0: PB7 1: SCOM3 Bit 2IOCN18: PB6 pin function selection 0: PB6 1: SCOM2 Bit 1IOCN17: PB5 pin function selection 0: PB5 1: SCOM1 Bit 0IOCN16: PB4 pin function selection 0: PB4 1: SCOM0 Rev. 1.00 58 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Logic Function Input/Output Structure Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PCC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PC, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Read/Write Timing Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Rev. 1.00 59 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Periodic TM sections. Introduction The device contains a 10-bit Compact TM named CTM, a 10-bit Standard TM named STM and two 10-bit Periodic TMs, named PTM0 and PTM1. Although similar in nature, the different TM types vary in their feature complexity. The common features to the Compact, Standard and Periodic TMs will be described in this section and the detailed operation will be described in corresponding sections. The main features and differences between the three types of TM are summarised in the accompanying table. CTM STM PTM Timer/Counter Function √ √ √ I/P Capture — √ √ Compare Match Output √ √ √ PWM Channels 1 1 1 Single Pulse Output — 1 1 Edge Edge Edge Duty or Period Duty or Period Duty or Period PWM Alignment PWM Adjustment Period & Duty TM Function Summary CTM 10-bit CTM STM PTM 10-bit STM 10-bit PTM0 10-bit PTM1 TM Name/Type Reference TM Operation The three different types of TMs offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. Rev. 1.00 60 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU TM Clock Source The clock source which drives the main counter in the TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control registers, where "x" can stand for C, S or P Type TM and "n" is the specific TM serial number. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact, Standard and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label xTCKn. The TM input pin, xTCKn, is essentially a clock source for the TM and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The TM input pin can be chosen to have either a rising or falling active edge. The PTCKn pins are also used as the external trigger input pin in single pulse output mode for the PTMn. For the STM and PTMn, there is another input pin xTPn, which also can be the STM or PTMn output pin. The STP or PTPn pin is the capture input pin whose active edge can be a rising edge, a falling edge or both rising and falling edges. The active edge transition type is selected using the STIO1~STIO0 bits in the STMC1 register or PTnIO1~PTnIO0 bits in the PTMnC1 register. For the PTMn, there is another capture input, PTCKn, for PTMn capture input mode, which can be used as the external trigger input source except for the PTPn pin. The TMs each have one output pins, named xTPn. The TM output pin can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn output pin is also the pin where the TM generates the PWM output waveform. As the TM input or output pins are pin-shared with other functions, the TM external pin function must first be setup using registers. A single bit in the Pin-shared Function Selection Registers determines if its associated pin is to be used as an external TM pin or if it is to have another function. CTM STM PTMn(n=0 or 1) Input Output Input Output Input Output CTCK CTP STCK/STP STP PTCKn/PTPn PTPn TM External Pins Rev. 1.00 61 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared function is implemented using one register, with a single bit in the register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. TCK input CTCK CTM CTP CCR output CTM Function Pin Control Block Diagram TCK input STCK STM CCR capture input CCR output STP STM Function Pin Control Block Diagram TCK input CCR capture input PTCKn PT�n CCR capture input CCR output PTPn PTMn Function Pin Control Block Diagram Rev. 1.00 62 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, being 10-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these registers is carried out in a specific way described above, it is recommended to use the "MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMnRPL, in the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. xT�n Counter Register (Read onl�) xT�nDL xT�nDH 8-bit Buffer xT�nAL xT�nAH xT�n CCRA Register (Read/Write) PT�nRPL PT�nRPH PT�n CCRP Register (Read/Write) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte xTMnAL or PTMnRPL ––note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMnAH or PTMnRPH ––here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.00 ♦♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH ––here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL ––this step reads data from the 8-bit buffer. 63 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one external output pin. CCRP fSYS/4 fSYS fH/1� fH/�4 fSUB fSUB CTCK 000 001 010 011 100 101 110 111 �-bit Comparator P Comparator P �atch CT�PF Interrupt CTOC b7~b9 10-bit Count-up Counter CTON CTPAU Counter Clear CTCCLR b0~b9 10-bit Comparator A Output Control Polarit� Control CT�1� CT�0 CTIO1� CTIO0 CTPOL 0 1 Comparator A �atch Pin Control CTP IOCN0 CT�AF Interrupt CTCK�~CTCK0 CCRA Compact Type TM Block Diagram Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the CTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a CTM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control one output pin. All operating setup conditions are selected using relevant internal registers. Compact Type TM Register Description Overall operation of the Compact TM is controlled using several registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Bit Register Name 7 6 5 4 CTMC0 CTPAU CTCK2 CTCK1 CTCK0 CTON CTRP2 CTRP1 CTRP0 CTMC1 CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR D0 3 2 1 0 CTMDL D7 D6 D5 D4 D3 D2 D1 CTMDH — — — — — — D9 D8 CTMAL D7 D6 D5 D4 D3 D2 D1 D0 CTMAH — — — — — — D9 D8 Compact TM Register List Rev. 1.00 64 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU CTMC0 Register Bit 7 6 5 4 3 2 1 0 Name CTPAU CTCK2 CTCK1 CTCK0 CTON CTRP2 CTRP1 CTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CTPAU: CTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the CTM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4CTCK2~CTCK0: Select CTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: CTCK rising edge clock 111: CTCK falling edge clock These three bits are used to select the clock source for the CTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3CTON: CTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the CTM. Setting the bit high enables the counter to run, clearing the bit disables the CTM. Clearing this bit to zero will stop the counter from counting and turn off the CTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the CTM is in the Compare Match Output Mode or the PWM Output Mode then the CTM output pin will be reset to its initial condition, as specified by the CTOC bit, when the CTON bit changes from low to high. Bit 2~0 Rev. 1.00 CTRP2~CTRP0: CTM CCRP 3-bit register, compared with the CTM Counter bit 9~bit 7 Comparator P Match Period 000: 1024 CTM clocks 001: 128 CTM clocks 010: 256 CTM clocks 011: 384 CTM clocks 100: 512 CTM clocks 101: 640 CTM clocks 110: 768 CTM clocks 111: 896 CTM clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTCCLR bit is set to zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. 65 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU CTMC1 Register Bit 7 6 5 4 3 2 1 0 Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6CTM1~CTM0: Select CTM Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the CTM. To ensure reliable operation the CTM should be switched off before any changes are made to the CTM1 and CTM0 bits. In the Timer/Counter Mode, the CTM output pin state is undefined. Bit 5~4CTIO1~CTIO0: Select CTP output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Undefined Timer/counter Mode Unused These two bits are used to determine how the CTM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTM is running. In the Compare Match Output Mode, the CTIO1 and CTIO0 bits determine how the CTM output pin changes state when a compare match occurs from the Comparator A. The CTM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTM output pin should be setup using the CTOC bit in the CTMC1 register. Note that the output level requested by the CTIO1 and CTIO0 bits must be different from the initial value setup using the CTOC bit otherwise no change will occur on the CTM output pin when a compare match occurs. After the CTM output pin changes state it can be reset to its initial level by changing the level of the CTON bit from low to high. In the PWM Output Mode, the CTIO1 and CTIO0 bits determine how the CTM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CTIO1 and CTIO0 bits only after the CTM has been switched off. Unpredictable PWM outputs will occur if the CTIO1 and CTIO0 bits are changed when The CTM is running. Rev. 1.00 66 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 3CTOC: CTP Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This is the output control bit for the CTM output pin. Its operation depends upon whether CTM is being used in the Compare Match Output Mode or in the PWM Output Mode. It has no effect if the CTM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the CTM output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM signal is active high or active low. Bit 2CTPOL: CTP Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the CTP output pin. When the bit is set high the CTM output pin will be inverted and not inverted when the bit is zero. It has no effect if the CTM is in the Timer/Counter Mode. Bit 1CTDPX: CTM PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0CTCCLR: Select CTM Counter clear condition 0: CTM Comparatror P match 1: CTM Comparatror A match This bit is used to select the method which clears the counter. Remember that the CTM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTCCLR bit is not used in the PWM Output Mode. CTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 CTM Counter Low Byte Register bit 7 ~ bit 0 CTM 10-bit Counter bit 7 ~ bit 0 CTMDH Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 CTM Counter High Byte Register bit 1 ~ bit 0 CTM 10-bit Counter bit 9 ~ bit 8 67 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU CTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0 CTM CCRA Low Byte Register bit 7 ~ bit 0 CTM 10-bit CCRA bit 7 ~ bit 0 CTMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as "0" Bit 1 ~ 0 CTM CCRA High Byte Register bit 1 ~ bit 0 CTM 10-bit CCRA bit 9 ~ bit 8 Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and CTM0 bits in the CTMC1 register. Compare Match Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the CTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both CTMAF and CTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the CTCCLR bit in the CTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the CTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTCCLR is high no CTMPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTM output pin will change state. The CTM output pin condition however only changes state when a CTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The CTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the CTM output pin. The way in which the CTM output pin changes state are determined by the condition of the CTIO1 and CTIO0 bits in the CTMC1 register. The CTM output pin can be selected using the CTIO1 and CTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTM output pin, which is setup after the CTON bit changes from low to high, is setup using the CTOC bit. Note that if the CTIO1 and CTIO0 bits are zero then no pin change will take place. Rev. 1.00 68 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value Counter overflow CCRP=0 0x3FF CTCCLR = 0; CTM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time CTON CTPAU CTPOL CCRP Int. flag CTMPF CCRA Int. flag CTMAF CTM O/P Pin Output pin set to initial Level Low if CTOC=0 Output not affected by CTMAF flag. Remains High until reset by CTON bit Output Toggle with CTMAF flag Here CTIO [1:0] = 11 Toggle Output select Note CTIO [1:0] = 10 Active High Output select Output Inverts when CTPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – CTCCLR=0 Note: 1. With CTCCLR=0, a Comparator P match will clear the counter 2. The CTM output pin controlled only by the CTMAF flag 3. The output pin reset to initial state by a CTON bit rising edge Rev. 1.00 69 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value CTCCLR = 1; CT� [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared b� CCRA value 0x�FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time CTON CTPAU CTPOL No CT�AF flag generated on CCRA overflow CCRA Int. flag CT�AF CCRP Int. flag CT�PF CT� O/P Pin CT�PF not generated Output pin set to initial Level Low if CTOC=0 Output does not change Output not affected b� CT�AF flag. Remains High until reset b� CTON bit Output Toggle with CT�AF flag Here CTIO [1:0] = 11 Toggle Output select Note CTIO [1:0] = 10 Active High Output select Output Inverts when CTPOL is high Output Pin Reset to Initial value Output controlled b� other pin-shared function Compare Match Output Mode – CTCCLR=1 Note: 1. With CTCCLR=1, a Comparator A match will clear the counter 2. The CTM output pin controlled only by the CTMAF flag 3. The output pin reset to initial state by a CTON rising edge 4. The CTMPF flags is not generated when CTCCLR=1 Rev. 1.00 70 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the CTM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 10 respectively. The PWM function within the CTM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the CTCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The CTOC bit In the CTMC1 register is used to select the required polarity of the PWM waveform while the two CTIO1 and CTIO0 bits are used to enable the PWM output or to force the CTM output pin to a fixed high or low level. The CTPOL bit is used to reverse the polarity of the PWM output waveform. • CTM, PWM Output Mode, Edge-aligned Mode, CTDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=16MHz, CTM clock source is fSYS/4, CCRP=100b, CCRA =128, The CTM PWM output frequency=(fSYS/4) / 512=fSYS/2048=7.8125 kHz, duty=128/512=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • CTM, PWM Output Mode, Edge-aligned Mode, CTDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the CTM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.00 71 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value CTDPX = 0; CT� [1:0] = 10 Counter cleared b� CCRP Counter Reset when CTON returns high CCRP Pause Resume CCRA Counter Stop if CTON bit low Time CTON CTPAU CTPOL CCRA Int. flag CT�AF CCRP Int. flag CT�PF CT� O/P Pin (CTOC=1) CT� O/P Pin (CTOC=0) PW� Dut� C�cle set b� CCRA PW� Period set b� CCRP PW� resumes operation Output controlled b� Output Inverts other pin-shared function when CTPOL = 1 PWM Output Mode – CTDPX=0 Note: 1. Here CTDPX=0 - Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when CTIO[1:0]=00 or 01 4. The CTCCLR bit has no influence on PWM operation Rev. 1.00 72 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value CTDPX = 1; CT� [1:0] = 10 Counter cleared b� CCRA Counter Reset when CTON returns high CCRA Pause Resume CCRP Counter Stop if CTON bit low Time CTON CTPAU CTPOL CCRP Int. flag CT�PF CCRA Int. flag CT�AF CT� O/P Pin (CTOC=1) CT� O/P Pin (CTOC=0) PW� Dut� C�cle set b� CCRP PW� Period set b� CCRA PW� resumes operation Output controlled b� Output Inverts other pin-shared function when CTPOL = 1 PWM Output Mode – CTDPX=1 Note: 1. Here CTDPX=1 – Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTIO[1:0]=00 or 01 4. The CTCCLR bit has no influence on PWM operation Rev. 1.00 73 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can be controlled with one external input pin and can drive one external output pin. CCRP fSYS/4 fSYS fH/16 fH/64 fSUB fSUB STCK 000 001 010 011 100 101 110 111 3-bit Comparator P Comparator P Match STMPF Interrupt STOC b7~b9 10-bit Count-up Counter STON STPAU STCK2~STCK0 Counter Clear 0 1 STCCLR b0~b9 10-bit Comparator A Output Control Polarity Control Pin Control STM1, STM0 STIO1, STIO0 STPOL IOCN2 Comparator A Match STP STMAF Interrupt STIO1, STIO0 Edge Detector CCRA Standard Type TM Block Diagram Standard TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 3-bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the STON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a STM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Standard Type TM Register Description Overall operation of the Standard TM is controlled using series of registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as three CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 STMC0 STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0 STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D7 D6 D5 D4 D3 D2 D1 D0 STMDH — — — — — — D9 D8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH — — — — — — D9 D8 10-bit Standard TM Register List Rev. 1.00 74 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU STMC0 Register Bit 7 6 5 4 3 2 1 0 Name STPAU STCK2 STCK1 STCK0 STON STRP2 STRP1 STRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7STPAU: STM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the STM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4STCK2~STCK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the STM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3STON: STM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the STM. Setting the bit high enables the counter to run, clearing the bit disables the STM. Clearing this bit to zero will stop the counter from counting and turn off the STM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the STM is in the Compare Match Output Mode or the PWM output Mode or Single Pulse Output Mode then the STM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Bit 2~0 Rev. 1.00 STRP2~ STRP0: STM CCRP 3-bit register, compared with the STM Counter bit 9~bit 7 Comparator P Match Period 000: 1024 STM clocks 001: 128 STM clocks 010: 256 STM clocks 011: 384 STM clocks 100: 512 STM clocks 101: 640 STM clocks 110: 768 STM clocks 111: 896 STM clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter’s highest three bits. The result of this comparison can be selected to clear the internal counter if the STCCLR bit is set to zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. 75 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU STMC1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 STM1~ STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the STM. To ensure reliable operation the STM should be switched off before any changes are made to the STM1 and STM0 bits. In the Timer/Counter Mode, the STM output pin state is undefined. Bit 5~4 STIO1~ STIO0: Select STM function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM output Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of STP 01: Input capture at falling edge of STP 10: Input capture at falling/rising edge of STP 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the STM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the STM is running. In the Compare Match Output Mode, the STIO1~STIO0 bits determine how the STM output pin changes state when a compare match occurs from the Comparator A. The STM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the STIO1~STIO0 bits are both zero, then no change will take place on the output. The initial value of the STM output pin should be setup using the STOC bit. Note that the output level requested by the STIO1~STIO0 bits must be different from the initial value setup using the STOC bit otherwise no change will occur on the STM output pin when a compare match occurs. After the STM output pin changes state, it can be reset to its initial level by changing the level of the STON bit from low to high. In the PWM Output Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the STIO1 and STIO0 bits only after the STM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the STM is running. 76 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 3STOC: STM Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM output Mode/ Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether STM is being used in the Compare Match Output Mode or in the PWM output Mode/ Single Pulse Output Mode. It has no effect if the STM is in the Timer/ Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM output Mode it determines if the PWM signal is active high or active low. In the Single Pulse Output Mode it determines the logic level of the STM output pin when the STON bit changes from low to high. Bit 2STPOL: STM Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the STM output pin. When the bit is set high the STM output pin will be inverted and not inverted when the bit is zero. It has no effect if the STM is in the Timer/Counter Mode. Bit 1STDPX: STM PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0STCCLR: Select STM Counter clear condition 0: STM Comparator P match 1: STM Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM output mode, Single Pulse or Input Capture Mode. STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter Low Byte Register bit 7 ~ bit 0 STM 10-bit Counter bit 7 ~ bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R — — — — — — 0 0 POR Bit 7~2 Bit 1~0 Rev. 1.00 Unimplemented, read as "0" STM Counter High Byte Register bit 1 ~ bit 0 STM 10-bit Counter bit 9 ~ bit 8 77 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU STMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STM CCRA Low Byte Register bit 7 ~ bit 0 STM 10-bit CCRA bit 7 ~ bit 0 STMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 STM CCRA High Byte Register bit 1 ~ bit 0 STM 10-bit CCRA bit 9 ~ bit 8 Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA cannot be set to "0". If the CCRA bits are all zero, the counter will overflow when it reaches its maximum 10-bit, 3FF Hex, value, however here the STMAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the STM output pin, will change state. The STM output pin condition however only changes state when an STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the STM output pin. The way in which the STM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The STM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place. Rev. 1.00 78 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value Counter overflow CCRP=0 0x3FF STCCLR = 0; STM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin Output pin set to initial Level Low if STOC=0 Output not affected by STMAF flag. Remains High until reset by STON bit Output Toggle with STMAF flag Here STIO [1:0] = 11 Toggle Output select Note STIO [1:0] = 10 Active High Output select Output Inverts when STPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – STCCLR=0 Note: 1. With STCCLR=0 a Comparator P match will clear the counter 2. The STM output pin controlled only by the STMAF flag 3. The output pin reset to initial state by a STON bit rising edge Rev. 1.00 79 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value STCCLR = 1; STM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time STON STPAU STPOL No STMAF flag generated on CCRA overflow CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin STMPF not generated Output pin set to initial Level Low if STOC=0 Output does not change Output Toggle with STMAF flag Here STIO [1:0] = 11 Toggle Output select Output not affected by STMAF flag. Remains High until reset by STON bit Note STIO [1:0] = 10 Active High Output select Output Inverts when STPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – STCCLR=1 Note: 1. With STCCLR=1 a Comparator A match will clear the counter 2. The STM output pin controlled only by the STMAF flag 3. The output pin reset to initial state by a STON rising edge 4. The STMPF flag is not generated when STCCLR=1 Rev. 1.00 80 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the STM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the STM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function by setting pin-share function register. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM output mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STOC bit in the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS=4MHz, TM clock source is fSYS/4, CCRP=100b and CCRA =128, The STM PWM output frequency=(fSYS/4) / 512=fSYS/2048=1.9531kHz, duty=128/512=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 10-bit STM, PWM Output Mode, Edge-aligned Mode, STDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the STM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.00 81 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value STDPX = 0; STM [1:0] = 10 Counter cleared by CCRP Counter Reset when STON returns high CCRP Pause Resume CCRA Counter Stop if STON bit low Time STON STPAU STPOL CCRA Int. flag STMAF CCRP Int. flag STMPF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function when STPOL = 1 PWM Output Mode – STDPX=0 Note: 1. Here STDPX=0 - Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when STIO[1:0]=00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.00 82 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value STDPX = 1; STM [1:0] = 10 Counter cleared by CCRA Counter Reset when STON returns high CCRA Pause Resume CCRP Counter Stop if STON bit low Time STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cycle set by CCRP PWM Period set by CCRA PWM resumes operation Output controlled by Output Inverts other pin-shared function when STPOL = 1 PWM Output Mode – STDPX=1 Note: 1. Here STDPX=1 - Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when STIO[1:0]=00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.00 83 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Single Pulse Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. S/W Command SET“STON” or STCK Pin Transition CCRA Leading Edge CCRA Trailing Edge STON bit 0à1 STON bit 1à0 S/W Command CLR“STON” or CCRA Compare Match STP Output Pin Pulse Width = CCRA Value Single Pulse Generation Rev. 1.00 84 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value STM [1:0] = 10 ; STIO [1:0] = 11 Counter stopped by CCRA Counter Reset when STON returns high CCRA Pause Counter Stops by software Resume CCRP Time STON Software Trigger Auto. set by STCK pin Cleared by CCRA match STCK pin Software Trigger Software Trigger Software Clear Software Trigger STCK pin Trigger STPAU STPOL No CCRP Interrupts generated CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) Output Inverts when STPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA match 2. CCRP is not used 3. The pulse is triggered by setting the STON bit high 4. In the Single Pulse Mode, STIO [1:0] must be set to "11" and cannot be changed. However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.00 85 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurement. The external signal is supplied on the STP, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STP the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STP the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a STM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STP to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STP, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode. Counter Value STM [1:0] = 01 Counter cleared by CCRP Counter Counter Stop Reset CCRP YY Pause Resume XX Time STON STPAU Active edge Active edge Active edge STM capture pin STP CCRA Int. Flag STMAF CCRP Int. Flag STMPF CCRA Value STIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. STM[1:0]=01 and active edge set by the STIO[1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. The STCCLR and STDPX bits are not used 4. No output function — STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 86 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Periodic Type TM – PTM The Periodic Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can be controlled with two external input pins and can drive one external output pin. CCRP 10-bit Comparator P fSYS/4 000 fSYS fH/1� fH/�4 fSUB 001 fSUB 101 PT�nPF Interrupt PTnOC b0~b9 010 011 10-bit Count-up Counter 100 110 PTCKn Comparator P �atch PTnON PTnPAU Counter Clear PTnCCLR b0~b9 111 PTnCK�~PTnCK0 10-bit Comparator A CCRA Output Control Polarit� Control Pin Control PTn�1� PTn�0 PTnIO1� PTnIO0 PTnPOL IOCNx 0 1 Comparator A �atch PTPn PT�nAF Interrupt PTnIO1� PTnIO0 PTnCAPTS Edge Detector 0 IOCNx Pin Control 1 Periodic Type TM Block Diagram (n=0 or 1) Periodic TM Operation The Periodic Type TM core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 10-bit wide. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the PTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a PTMn interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control more than one output pin. All operating setup conditions are selected using relevant internal registers. Periodic Type TM Register Description Overall operation of the Periodic Type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA value and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 6 5 4 3 2 1 0 PTMnC0 PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTMnDL D7 D6 D5 D4 D3 PTnPOL PTnCAPTS PTnCCLR D2 D1 D0 D8 PTMnDH — — — — — — D9 PTMnAL D7 D6 D5 D4 D3 D2 D1 D0 PTMnAH — — — — — — D9 D8 PTMnRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMnRPH — — — — — — D9 D8 10-bit Periodic TM Register List (n=0 or 1) Rev. 1.00 87 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU PTMnC0 Register Bit 7 6 5 4 3 2 1 0 Name PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7PTnPAU: PTMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the PTMn will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6~4PTnCK2~PTnCK0: Select PTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCKn rising edge clock 111: PTCKn falling edge clock These three bits are used to select the clock source for the PTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3PTnON: PTMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the PTMn. Setting the bit high enables the counter to run, clearing the bit disables the PTMn. Clearing this bit to zero will stop the counter from counting and turn off the PTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the PTMn is in the Compare Match Output Mode, PWM output Mode or Single Pulse Output Mode then the PTMn output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Rev. 1.00 Unimplemented, read as "0" 88 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU PTMnC1 Register Bit 7 6 5 4 3 Name PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTnPOL PTnCAPTS PTnCCLR Bit 7~6PTnM1~PTnM0: Select PTMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the PTMn. To ensure reliable operation the PTMn should be switched off before any changes are made to the PTnM1 and PTnM0 bits. In the Timer/Counter Mode, the PTMn output pin state is undefined. Bit 5~4PTnIO1~PTnIO0: Select PTMn pin PTPn or PTCKn function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Output Mode/Single Pulse Output Mode 00: PWM Output inactive state 01: PWM Output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of PTPn or PTCKn 01: Input capture at falling edge of PTPn or PTCKn 10: Input capture at falling/rising edge of PTPn or PTCKn 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTMn is running. In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a compare match occurs from the Comparator A. The PTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTMn output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that the output level requested by the PTnIO1 and PTnIO0 bits must be different from the initial value setup using the PTnOC bit otherwise no change will occur on the PTMn output pin when a compare match occurs. After the PTMn output pin changes state, it can be reset to its initial level by changing the level of the PTnON bit from low to high. In the PWM Output Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the PTnIO1 and PTnIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed when the PTMn is running. Rev. 1.00 89 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 3PTnOC: PTMn PTPn Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTMn output pin. Its operation depends upon whether PTMn is being used in the Compare Match Output Mode or in the PWM Output Mode/Single Pulse Output Mode. It has no effect if the PTMn is in the Timer/ Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTMn output pin before a compare match occurs. In the PWM Output Mode it determines if the PWM signal is active high or active low. Bit 2PTnPOL: PTMn PTPn Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the PTPn output pin. When the bit is set high the PTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the PTMn is in the Timer/Counter Mode. Bit 1PTnCAPTS: PTMn Capture Trigger Source Selection 0: From PTPn pin 1: From PTCKn pin Bit 0PTnCCLR: Select PTMn Counter clear condition 0: PTMn Comparator P match 1: PTMn Comparator A match This bit is used to select the method which clears the counter. Remember that the Periodic TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not used in the PWM Output Mode, Single Pulse or Capture Input Mode. PTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn Counter Low Byte Register bit 7 ~ bit 0 PTMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0D9~D8: PTMn Counter High Byte Register bit 1 ~ bit 0 PTMn 10-bit Counter bit 9 ~ bit 8 Rev. 1.00 90 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU PTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn CCRA Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRA bit 7 ~ bit 0 PTMnAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0D9~D8: PTMn CCRA High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRA bit 9 ~ bit 8 PTMnRPL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn CCRP Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRP bit 7 ~ bit 0 PTMnRPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0D9~D8: PTMn CCRP High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The Periodic Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register. Compare Match Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMnAF and PTMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. Rev. 1.00 91 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be cleared to zero. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the PTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the PTMn output pin, will change state. The PTMn output pin condition however only changes state when a PTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the PTMn output pin. The way in which the PTMn output pin changes state are determined by the condition of the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The PTMn output pin can be selected using the PTnIO1 and PTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTMn output pin, which is setup after the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1 and PTnIO0 bits are zero then no pin change will take place. Counter Value Counter overflow CCRP > 0 Counter cleared by CCRP value CCRP=0 0x3FF CCRP > 0 PTnCCLR = 0; PTnM[1:0] = 00 Counter Restart Resume CCRP Pause CCRA Stop Time PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin Output pin set to initial Level Low if PTnOC=0 Output not affected by PTMnAF flag. Remains High until reset by PTnON bit Output Toggle with PTMnAF flag Here PTnIO [1:0] = 11 Toggle Output select Note PTnIO [1:0] = 10 Active High Output select Output Inverts when PTnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTnCCLR=0 (n=0 or 1) Note: 1. With PTnCCLR=0 a Comparator P match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge Rev. 1.00 92 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value PTnCCLR = 1; PTnM[1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PTnON PTnPAU PTnPOL No PTMnAF flag generated on CCRA overflow CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTMn O/P Pin PTMnPF not generated Output pin set to initial Level Low if PTnOC=0 Output does not change Output Toggle with PTMnAF flag Here PTnIO [1:0] = 11 Toggle Output select Output not affected by PTMnAF flag. Remains High until reset by PTnON bit Note PTnIO [1:0] = 10 Active High Output select Output Inverts when PTnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTnCCLR=1 (n=0 or 1) Note: 1. With PTnCCLR=1 a Comparator A match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. A PTMnPF flag is not generated when PTnCCLR=1 Rev. 1.00 93 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively. The PWM function within the PTMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the PTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM Output Mode, the PTnCCLR bit has no effect on the PWM operation. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used to select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are used to enable the PWM output or to force the PTMn output pin to a fixed high or low level. The PTnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PTMn, PWM Output Mode, Edge-aligned Mode CCRP 1~1023 0 Period 1~1023 1024 Duty CCRA If fSYS=12MHz, PTMn clock source select fSYS/4, CCRP=512 and CCRA=128, The PTMn PWM output frequency=(fSYS/4)/512=fSYS/2048=5.8594kHz, duty=128/(2×256)=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.00 94 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value PTnM[1:0] = 10 Counter cleared by CCRP Counter Reset when PTnON returns high CCRP Pause Resume Counter Stop if PTnON bit low CCRA Time PTnON PTnPAU PTnPOL CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTMn O/P Pin (PTnOC=1) PTMn O/P Pin (PTnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP Output controlled by other pin-shared function PWM resumes operation Output Inverts When PTnPOL = 1 PWM Output Mode (n=0 or 1) Note: 1. Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTnIO[1:0]=00 or 01 4. The PTnCCLR bit has no influence on PWM operation Rev. 1.00 95 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Single Pulse Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter can only be reset back to zero when the PTnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR bit is not used in this Mode. S/W Command SET“PTnON or ” PTCKn Pin Transition CCRA Leading Edge CCRA Trailing Edge PTnON bit 0à1 PTnON bit 1à0 S/W Command CLR“PTnON” or CCRA Compare Match PTPn Output Pin Pulse Width = CCRA Value Single Pulse Generation (n=0 or 1) Rev. 1.00 96 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value PTnM[1:0] = 10 ; PTnIO[1:0] = 11 Counter stopped by CCRA Counter Reset when PTnON returns high CCRA Pause Counter Stops by software Resume CCRP Time PTnON Software Trigger Auto. set by PTCKn pin Software Trigger Cleared by CCRA match PTCKn pin Software Trigger Software Software Trigger Clear PTCKn pin Trigger PTnPAU PTnPOL CCRP Int. Flag PTMnPF No CCRP Interrupts generated CCRA Int. Flag PTMnAF PTMn O/P Pin (PTnOC=1) PTMn O/P Pin (PTnOC=0) Output Inverts when PTnPOL = 1 Pulse Width set by CCRA Single Pulse Mode (n=0 or 1) Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the PTCKn pin or by setting the PTnON bit high 4. A PTCKn pin active edge will automatically set the PTnON bit high 5. In the Single Pulse Mode, PTnIO[1:0] must be set to "11" and cannot be changed. Rev. 1.00 97 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPn or PTCKn pin which is selected using the PTnCAPTS bit in the PTMnC1 register. The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPn or PTCKn pin the present value in the counter will be latched into the CCRA registers and a PTMn interrupt generated. Irrespective of what events occur on the PTPn or PTCKn pin, the counter will continue to free run until the PTnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a PTMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPn or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPn or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPn or PTCKn pin is pin shared with other functions, care must be taken if the PTMn is in the Capture Input Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode. Rev. 1.00 98 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Counter Value PTnM[1:0] = 01 Counter cleared by CCRP Counter Stop Counter Reset CCRP YY Resume Pause XX Time PTnON PTnPAU Active edge Active edge Active edge PTMn Capture Pin PTPn or PTCKn CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF CCRA Value PTnIO [1:0] Value 00 - Rising edge XX YY XX 01 - Falling edge 10 - Both edges YY 11 - Disable Capture Capture Input Mode (n=0 or 1) Note: 1. PTnM[1:0]=01 and active edge set by the PTnIO[1:0] bits 2. A PTMn Capture input pin active edge transfers the counter value to CCRA 3. PTnCCLR bit not used 4. No output function – PTnOC and PTnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 99 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Nebuliser Resonance Detector Please refer Holtek Applicatoin Notes. Water Shortage Protection Please refer Holtek Applicatoin Notes. Over Current/Voltage Protection The device includes an over current/voltage protection function which provides an over current or over voltage protection protection mechanism for applications. The OCVPAI0 input signal can be converted to a relevant voltage level according to the current value using the OCVP operational amplifier. It is then compared with a reference voltage generated by an 8-bit D/A converter. The voltage on the OCVPCI pin is compared with a reference voltage generated by the 8-bit D/A converter. When the OCVPF flag changes from 0 to 1 and if the corresponding interrupt control is enabled, an OCVP interrupt will be generated to indicate a specific current or voltage condition has occurred. VREF VDD OCVPEN OCVPDA[7:0] 8-bit DAC OCVPVRS S0 OCVPAI0 OCVPCOUT OCVPEN S2 fDEB=fSYS S3 CMP OCVPS[2:0] S4 S5 OCVPO OCVPEN S1 Debounce OPA R1 OCVPINT OCVPSPOL OCVPCI OCVPCHY 2kΩ or 4kΩ OCVPDEB[2:0] OCVPCPS OCVPG2XEN S6 OCVPSWn (n=0~6) S7 OCVPSW7 R2 OCVPAO OCVPG[2:0] OCVP Block Diagram OCVP Operation The OCVP circuit is used to prevent the input current or voltage from being in an unexpected level range. The current on the OCVPAI0 pin is converted to a voltage and then amplified by the OCVP operational amplifier with a programmable gain from 1 to 65 selected by the OCVPG2~OCVPG0 bits in the OCVPC2 register. This is known as the Programmable Gain Amplifier or PGA. This PGA can also be configured to operate in the non-inverting, inverting or input offset calibration mode determined by the OCVPSW7~OCVPSW0 bits in the OCVPC0 register. After the current is converted and amplified to a specific voltage level, it will be compared with a reference voltage provided by an 8-bit D/A converter. The voltage on the OCVPCI pin is also can be selected to compare with a reference provided by the 8-bit D/A converter. To compare the OCVPAO output signal or the OCVPCI input signal with the D/A converter output voltage is selected using the OCVPCPS bit in the OCVPC1 register. The 8-bit D/A converter power can be supplied by the external power pin, VDD or VREF, selected by the OCVPVRS bit in the OCVPC1 register. The comparator output, OCVPCOUT, will first be filtered with a certain debounce time period selected by the OCVPDEB2~OCVPDEB0 bits in the OCVPC2 register. Then a filtered OCVP digital comparator output, OCVPO, is obtained to indicate whether a user-defined Rev. 1.00 100 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU current or voltage condition occurs or not. If the OCVPSPOL bit is cleared to 0 and the comparator inputs force the OCVPO bit to change from 0 to 1, or if the OCVPSPOL bit is set to 1 and the comparator inputs force the OCVPO bit changes from 1 to 0, the corresponding interrupt will be generated if the relevant interrupt control bit is enabled. It is important to note that, only an OCVPINT rising edge can trigger an OCVP interrupt request, so the OCVPSPOL bit must be properly configured according to user’s application requirements. The comparator in the OCVP circuit also has hysteresis function controlled by OCVPCHY bit. Note that the debounce clock, fDEB, comes from the system clock, fSYS. The operational amplifier output voltage also can be read out by means of another A/D converter from the OCVPAO signal. The DAC output voltage is controlled by the OCVPDA register and the DAC output is defined as below: DAC VOUT=(DAC reference voltage/256) × D[7:0] OCVP Control Registers Overall operation of the OCVP function is controlled using several registers. The CTRL2 register is used to select the OCVPAI0 input signal source pin. One register is used to provide the reference voltages for the OCVP circuit. Two registers are used for the operational amplifier and comparator input offset calibration. The remaining three registers are control registers which control the OCVP function, D/A converter reference voltage select, switches on/off control, PGA gain select, comparator non-inverting input select, comparator de-bounce time, comparator hysteresis function and comparator output polarity control, etc. For a more detailed description regarding the input offset voltage calibration procedures, refer to the corresponding input offset calibration sections. Bit Register Name 7 6 5 4 3 2 1 0 CTRL2 — — — — — OCVPS2 OCVPS1 OCVPS0 OCVPDA D7 D6 D5 D4 D3 D2 D1 D0 OCVPC0 OCVPSW7 OCVPSW6 OCVPSW5 OCVPSW4 OCVPSW3 OCVPSW2 OCVPSW1 OCVPSW0 OCVPC1 OCVPEN OCVPCHY OCVPO OCVPSPOL — — OCVPCPS OCVPVRS OCVPC2 — OCVPG2XEN OCVPG2 OCVPG1 OCVPG0 OCVPDEB2 OCVPDEB1 OCVPDEB0 OCVPOCAL OCVPOOFM OCVPORSP OCVPOOF5 OCVPOOF4 OCVPOOF3 OCVPOOF2 OCVPOOF1 OCVPOOF0 OCVPCCAL OCVPCOUT OCVPCOFM OCVPCRSP OCVPCOF4 OCVPCOF3 OCVPCOF2 OCVPCOF1 OCVPCOF0 OCVP Register List CTRL2 Register Rev. 1.00 Bit 7 6 5 4 3 Name — — — — — 2 R/W — — — — — R/W R/W R/W POR — — — — — 0 0 0 Bit 7~3 Unimplemented, read as "0" Bit 2~0 OCVPS2 ~ OCVPS0: OCVPAI0 signal input source pin selection 000: PB0 001: PB1 010: PB2 011: PB3 100: PA6 101: PA3 110: PA1 111: PA4 101 1 0 OCVPS2 OCVPS1 OCVPS0 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU OCVPC0 Register Bit Name 7 6 5 4 3 2 1 0 OCVPSW7 OCVPSW6 OCVPSW5 OCVPSW4 OCVPSW3 OCVPSW2 OCVPSW1 OCVPSW0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 0 0 1 0 0 0 Bit 7OCVPSW7: OCVP switch S7 on/off control 0: Off 1: On Bit 6OCVPSW6: OCVP switch S6 on/off control 0: Off 1: On Bit 5OCVPSW5: OCVP switch S5 on/off control 0: Off 1: On Bit 4OCVPSW4: OCVP switch S4 on/off control 0: Off 1: On Bit 3OCVPSW3: OCVP switch S3 on/off control 0: Off 1: On Bit 2OCVPSW2: OCVP switch S2 on/off control 0: Off 1: On Bit 1OCVPSW1: OCVP switch S1 on/off control 0: Off 1: On Bit 0OCVPSW0: OCVP switch S0 on/off control 0: Off 1: On OCVPC1 Register Bit 7 6 Name OCVPEN OCVPCHY 5 4 3 2 OCVPO OCVPSPOL — — 1 0 OCVPCPS OCVPVRS R/W R/W R/W R R/W — — R/W R/W POR 0 0 0 0 — — 0 0 Bit 7OCVPEN: OCVP function enable control 0: Disable 1: Enable When this bit is cleared to 0, the overall OCVP operation will be disabled and the comparator output, OCVPCOUT, will be equal to 0. Bit 6OCVPCHY: OCVP Comparator Hysteresis function control 0: Disable 1: Enable Bit 5OCVPO: OCVP Comparator debounce output This bit is the debounce version of the OCVPCOUT bit. Bit 4OCVPSPOL: OCVPO polarity control 0: Non-inverted 1: Inverted Bit 3~2 Rev. 1.00 Unimplemented, read as "0" 102 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 1OCVPCPS: OCVP Comparator non-inverting input selection 0: OCVPAO and/or OPAMP output 1: From OCVPCI pin Bit 0OCVPVRS: OCVP D/A Converter reference voltage selection 0: From VDD 1: From VREF pin OCVPC2 Register Bit 7 6 5 4 3 2 1 0 Name — OCVPG2XEN OCVPG2 OCVPG1 OCVPG0 OCVPDEB2 OCVPDEB1 OCVPDEB0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6OCVPG2XEN: R2/R1 ratio doubling enable control 0: Disable (R1=13.2kΩ) 1: Enable (R1=6.6kΩ) When this bit is 1, the R2/R1 ratio selected by the OCVPG2~OCVPG0 bits will be doubled. Bit 5~3OCVPG2~OCVPG0: PGA R2/R1 ratio selection When OCVPG2XEN=0: 000: R2/R1=1 001: R2/R1=4 010: R2/R1=6 011: R2/R1=10 100: R2/R1=15 101: R2/R1=25 110: R2/R1=40 111: R2/R1=65 When OCVPG2XEN=1: 000: R2/R1=2 001: R2/R1=8 010: R2/R1=12 011: R2/R1=20 100: R2/R1=30 101: R2/R1=50 110: R2/R1=80 111: R2/R1=130 The calculating formula of the PGA gain for the inverting and non-inverting mode is described in the “Input Voltage Range” section. Note that the internal resistors, R1 and R2, should be used when the gain is determined by these bits. This means the S4 or S5 switch together with the S7 switch should be on. Otherwise, the gain accuracy will not be guaranteed. Bit 2~0OCVPDEB2~OCVPDEB0: OCVP Comparator output debounce time control 000: Bypass, no debounce 001: (1~2) × tDEB 010: (3~4) × tDEB 011: (7~8) × tDEB 100: (15~16) × tDEB 101: (31~32) × tDEB 110: (63~64) × tDEB 111: (127~128) × tDEB Note: fDEB=fSYS, tDEB=1/fDEB Rev. 1.00 103 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU OCVPDA Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 OCVP D/A Converter Data Register bit 7 ~ bit 0 OCVP D/A Converter Output=(DAC reference voltage/256) × D[7:0] OCVPOCAL Register Bit 7 6 5 4 3 2 1 0 Name OCVPOOFM OCVPORSP OCVPOOF5 OCVPOOF4 OCVPOOF3 OCVPOOF2 OCVPOOF1 OCVPOOF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 0 0 0 0 0 Bit 7OCVPOOFM: OCVP Operational Amplifier operating mode selection 0: Normal operating mode 1: Offset calibration mode This bit is used to select the OCVP operating mode. To select the operational amplifier input offset calibration mode, the OCVPSW7~OCVPSW0 bits must first be set to 28H and then the OCVPOOFM bit must be set to 1 followed by the OCVPCOFM bit being cleared to 0. Refer to the "Operational Amplifier Input Offset Calibration" section for the detailed offset calibration procedures. Bit 6OCVPORSP: OCVP Operational Amplifier input offset voltage calibration reference selection 0: Operational amplifier inverting input is selected 1: Operational amplifier non-verting input is selected OCVPOOF5~OCVPOOF0: OCVP Operational Amplifier input offset voltage calibration value This 6-bit field is used to perform the operational amplifier input offset calibration operation and the value for the OCVP operational amplifier input offset calibration can be restored into this bit field. More detailed information is described in the "Operational Amplifier Input Offset Calibration" section. Bit 5~0 OCVPCCAL Register Bit 7 6 5 4 3 2 1 0 Name OCVPCOUT OCVPCOFM OCVPCRSP OCVPCOF4 OCVPCOF3 OCVPCOF2 OCVPCOF1 OCVPCOF0 R/W R R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 1 0 0 0 0 Bit 7OCVPCOUT: OCVP Comparator output 0: Non-verting input voltage < DAC output voltage 1: Non-verting input voltage > DAC output voltage This bit is used to indicate whether the non-verting input voltage is greater than the DAC output voltage. If the OCVPCOUT is set to 1, the non-verting input voltage is greater than the DAC output voltage. Otherwise, the non-verting input voltage is less than the DAC output voltage. This bit value can be output on the OCVPCOUT pin. Bit 6OCVPCOFM: OCVP Comparator operating mode selection 0: Normal operating mode 1: Offset calibration mode This bit is used to select the OCVP comparator operating mode. To select the comparator input offset calibration mode, the OCVPSW7~OCVPSW0 bits must first be set to 28H and then the OCVPCOFM bit must be set to 1 followed by the OCVPOOFM bit being cleared to 0. Refer to the "Comparator Input Offset Calibration" section for the detailed offset calibration procedures. Rev. 1.00 104 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 5OCVPCRSP: OCVP Comparator input offset voltage calibration reference selection 0: Inverting input as the reference input 1: Non-inverting input is selected as the reference input Bit 4~0OCVPCOF4~OCVPCOF0: OCVP Comparator input offset voltage calibration value This 5-bit field is used to perform the comparator input offset calibration operation and the value for the OCVP comparator input offset calibration can be restored into this bit field. More detailed information is described in the "Comparator Input Offset Calibration" section. Input Voltage Range Together with different PGA operating modes, the input voltage can be positive or negative to provide diverse applications for the device. The PGA output for the positive or negative input voltage is respectively calculated based on different formulas and described by the following examples. • For VIN > 0, the PGA operates in the non-inverting mode and the PGA output is obtained using the formula below: VOUT = (1 + R2 ) x VIN R1 • When the PGA operates in the non-inverting mode, a unity gain buffer is provided. If OCVPSW6~OCVPSW4 bits are set to "000", the PGA gain will be 1 and the PGA will act as a unity gain buffer. The switches S6, S5 and S4 will be off internally and the output voltage of PGA is: VOUT = VIN • If S3 and S4 are on, the input node is OCVPAI0. For input voltage 0 >VIN >-0.4, the PGA operates in the inverting mode and the PGA output is obtained using the formula below. Note that if the input voltage VIN is negative, it can not be lower than -0.4V which will result in current leakage. VOUT = − R2 x VIN R1 Offset Calibration To operate in the input offset calibration mode for the OCVP circuit, the OCVPSW7~OCVPSW0 bits should first be set to 28H. For operational amplifier and comparator input offset calibration, the procedures are similar except for setting the respective control bits. Operational Amplifier Input Offset Calibration Step 1. Set OCVPSW [7:0]=28H (S3 and S5 are on, other switches are off), OCVPOOFM=1, OCVPCOFM=0 and OCVPORSP=1, OCVPCPS=0, the OCVP will operate in the operational amplifier input offset calibration mode. Step 2. Set OCVPDA [7:0]=40H Step 3. Set OCVPOOF [5:0]=000000 and read the OCVPCOUT bit. Step 4. Increase the OCVPOOF [5:0] value by 1 and then read the OCVPCOUT bit. If the OCVPCOUT bit state has not changed, then repeat Step 4 until the OCVPCOUT bit state has changed. If the OCVPCOUT bit state has changed, record the OCVPOOF value as VOOS1 and then go to Step 5. Step 5. Set OCVPOOF [5:0]=111111 and read the OCVPCOUT bit. Rev. 1.00 105 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Step 6. Decrease the OCVPOOF [5:0] value by 1 and then read the OCVPCOUT bit. If the OCVPCOUT bit state has not changed, then repeat Step 6 until the OCVPCOUT bit state has changed. If the OCVPCOUT bit state has changed, record the OCVPOOF value as VOOS2 and then go to Step 7. Step 7. Restore the operational amplifier input offset calibration value VOOS into the OCVPOOF [5:0] bit field. The offset calibration procedure is now finished. Where VOOS = VOOS1 + VOOS2 2 Comparator input Offset Calibration Before the offset calibration, the hysteresis voltage should be zero by setting the OCVPCHY bit to 0. Step 1. Set OCVPSW [7:0]=28H, OCVPCOFM=1, OCVPOOFM=0 and OCVPCRSP=0, the OCVP will now operate in the comparator input offset calibration mode. Step 2. Set OCVPDA [7:0]=40H Step 3. Set OCVPCOF [4:0]=00000 and read the OCVPCOUT bit. Step 4. Increase the OCVPCOF [4:0] value by 1 and then read the OCVPCOUT bit. If the OCVPCOUT bit state has not changed, then repeat Step 4 until the OCVPCOUT bit state has changed. If the OCVPCOUT bit state has changed, record the OCVPCOF value as VCOS1 and then go to Step 5. Step 5. Set OCVPCOF [4:0]=11111 and read the OCVPCOUT bit. Step 6. Decrease the OCVPCOF [4:0] value by 1 and then read the OCVPCOUT bit. If the OCVPCOUT bit state has not changed, then repeat Step 6 until the OCVPCOUT bit state has changed. If the OCVPCOUT bit state has changed, record the OCVPCOF value as VCOS2 and then go to Step 7. Step 7. Restore the comparator input offset calibration value VCOS into the OCVPCOF [4:0] bit field. The offset calibration procedure is now finished. Where VCOS = VCOS1 + VCOS2 2 Rev. 1.00 106 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. VDD SDA SCL Device Slave Device �aster Device Slave I2C Master/Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For this device, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. Data Bus I2C Data Register (IICD) fSYS SCL Pin SDA Pin HTX Debounce Circuitry IICDEB[1:0] Address Address Match–HAAS Comparator Direction Control Data in MSB M U X Shift Register Read/Write Slave I2C Interrupt SRW Data out MSB TXAK Transmit/ Receive Control Unit fSUB IICTOEN I2C Address Register (IICA) 8-bit Data Transfer Complete–HCF Detect Start or Stop HBB IICTOF Time-out Control Address Match I2C Block Diagram Rev. 1.00 107 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU START signal from �aster Send slave address and R/W bit from �aster Acknowledge from slave Send data b�te from �aster Acknowledge from slave STOP signal from �aster The IICDEB1 and IICDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in effect add a debounce time to the external clock to reduce the possibility of glitches on the clock line causing erroneous operation. The debounce time, if selected, can be chosen to be either 2 or 4 system clocks. To achieve the required I2C data transfer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Debounce fSYS > 2MHz fSYS > 5MHz 2 system clocks debounce fSYS > 4MHz fSYS > 10MHz fSYS > 8MHz fSYS > 20MHz 4 system clocks debounce I C Minimum fSYS Frequency 2 I2C Registers There are three control registers associated with the I2C bus, IICC0, IICC1 and IICTOC, and one slave address register, IICA, together with one data register, IICD. Bit Register Name 7 6 5 4 3 2 1 0 IICC0 — — — — IICDEB1 IICDEB0 IICEN — IICC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK IICD D7 D6 D5 D4 D3 D2 D1 D0 IICA A6 A5 A4 A3 A2 A1 A0 — IICTOC IICTOEN IICTOF IICTOS5 IICTOS4 IICTOS3 IICTOS2 IICTOS1 IICTOS0 I2C Register List Rev. 1.00 108 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU IICD Register The IICD register is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the IICD register. After the data is received from the I2C bus, the microcontroller can read it from the IICD register. Any transmission or reception of data from the I2C bus must be made via the IICD register. Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0D7~D0: I2C Data Buffer bit 7~bit 0 IICA Register The IICA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~ 1 of the IICA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the IICA register, the slave device will be selected. Bit 7 6 5 4 3 2 1 0 Name A6 A5 A4 A3 A2 A1 A0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR 0 0 0 0 0 0 0 — Bit 7~1A6~A0: I2C slave address A6~ A0 is the I2C slave address bit 6 ~ bit 0. Bit 0 Unimplemented, read as "0" I2C Control Registers There are two control registers for the I2C interface, IICC0 and IICC1. The register IICC0 is used to control the enable/disable function and to set the data transmission clock frequency. The IICC1 register contains the relevant flags which are used to indicate the I2C communication status. Another register, IICTOC, is used to control the I2C time-out function and will be described in the corresponding section. • IICC0 Register Bit 7 6 5 4 3 2 1 0 Name — — — — IICDEB1 IICDEB0 IICEN — R/W — — — — R/W R/W R/W — POR — — — — 0 0 0 — Bit 7~4 Unimplemented, read as "0" Bit 3~2IICDEB1~IICDEB0: I2C debounce time selection 00: No debounce 01: 2 system clocks debounce 10: 4 system clocks debounce 11: 4 system clocks debounce Rev. 1.00 109 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 1IICEN: I2C interface enable control 0: Disable 1: Enable The bit is the overall on/off control for the I2C interface. When the IICEN bit is cleared to zero to disable the I2C interface, the SDA and SCL lines will lose their I2C function and the I2C operating current will be reduced to a minimum value. When the bit is set high the I2C interface is enabled. If the IICEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 Unimplemented, read as "0" • IICC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Below is an example of the flow of a two-byte I2C data transfer: First, I2C slave device receive a start signal from I2C master and then HCF bit is automatically cleared to zero. Second, I2C slave device finish receiving the 1st data byte and then HCF bit is automatically set to one. Third, user read the 1st data byte from IICD register by the application program and then HCF bit is automatically cleared to zero. Fourth, I2C slave device finish receiving the 2nd data byte and then HCF bit is automatically set to one and so on. Finally, I2C slave device receive a stop signal from I2C master and then HCF bit is automatically set to one. Bit 6HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be "1" when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Rev. 1.00 110 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Bit 4HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received. Bit 2SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1IAMWU: I2C Address Match Control 0: Disable 1: Enable This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave donot receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is "0", it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. Rev. 1.00 111 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the IICC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and IICTOF bits to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer completion or I2C bus time-out occurrence. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this: • Step 1 Set IICEN bit in the IICC0 register to "1" to enable the I2C bus. • Step 2 Write the slave address of the device to the I2C bus address register IICA. • Step 3 Set the IICE and I2C multi-function interrupt enable bit of the interrupt control register to enable the I2C interrupt and the multi-function interrupt. Start SET IICEN Write Slave Address to IICA No I2C Bus Interrupt=? Yes CLR IICE Poll IICF to decide when to go to I2C Bus ISR SET IICE and MFnE Wait for Interrupt Go to Main Program Go to Main Program I2C Bus Initialisation Flow Chart Rev. 1.00 112 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the IICC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I2C bus interrupt can come from three sources, when the program enters the interrupt subroutine, the HAAS and IICTOF bits should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer or I2C time-out. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register, or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the IICC1 register defines whether the master device to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the IICC1 register should be set to "1". If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the IICC1 register should be set to "0". Rev. 1.00 113 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the IICD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the IICD register. If setup as a receiver, the slave device must read the transmitted data from the IICD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the IICC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. SCL Start Slave Address 1 SDA 0 1 1 0 1 SRW ACK 1 0 0 Data SCL 1 0 0 1 0 ACK 1 0 Stop 0 SDA S=Start (1 bit) SA=Slave Address (7 bits) SR=SRW bit (1 bit) M=Slave device send acknowledge bit (1 bit) D=Data (8 bits) A=ACK (RXAK bit for transmitter, TXAK bit for receiver, 1 bit) P=Stop (1 bit) S SA SR M D A D A …… S SA SR M D A D A …… P Note: *When a slave address is matched, the device must be placed in either the transmit mode and then write data to the IICD register, or in the receive mode where it must implement a dummy read from the IICD register to release the I2C SCL line. I2C Communication Timing Diagram Rev. 1.00 114 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Start No No No Yes HAAS=1? Yes HTX=1? IICTOF=1? Yes Yes SET IICTOEN CLR IICTOF SRW=1? No RETI Read from IICD to release SCL Line RETI Yes SET HTX CLR HTX CLR TXAK Write data to IICD to release SCL Line Dummy read from IICD to release SCL Line RETI RETI RXAK=1? No CLR HTX CLR TXAK Write data to IICD to release SCL Line Dummy read from IICD to release SCL Line RETI RETI I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the problem of I2C lockup due to reception of erroneous clock sources, a time-out function is provided. If the clock source to the I2C is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts counting on an I2C bus "START" & "address match" condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out setup by the IICTOC register, then a time-out condition will occur. The time-out function will stop when an I2C "STOP" condition occurs. Rev. 1.00 115 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU SCL Start Slave Address 1 SDA 0 1 1 0 1 SRW ACK 1 0 0 I2C time-out counter start Stop SCL 1 0 0 1 0 1 0 0 SDA I2C time-out counter reset on SCL negative transition I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and the IICTOEN bit will be cleared to zero and the IICTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out IICD, IICA, IICC0 No changed IICC1 Reset to POR condition I C Registers after Time-out 2 The IICTOF flag can be cleared by the application program. There are 64 time-out periods which can be selected using bits in the IICTOC register. The time-out time which can have a range of about 1ms to 64ms is given by the formula: ((1~64) × 32) / fSUB. • IICTOC Register Bit 7 6 5 4 3 2 1 0 Name IICTOEN IICTOF IICTOS5 IICTOS4 IICTOS3 IICTOS2 IICTOS1 IICTOS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7IICTOEN: I2C Time-out function Control 0: Disable 1: Enable Bit 6IICTOF: I2C Time-out flag (set by time-out and clear by software) 0: No time-out occurred 1: Time-out occurred This bit is set high by time-out condition occurs and cleared to zero by software. Bit 5~0IICTOS5~IICTOS0: Time-out period definition I2C time-out clock source is fSUB/32. I2C time-out time is given by: (IICTOS[5:0]+1) × (32/fSUB) Rev. 1.00 116 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains several external interrupt and internal interrupt functions. The external interrupt is generated by the action of the external INT0 and INT1 pins, while the internal interrupts are generated by various internal functions such as the Timer Modules (TMs), Over Current/Voltage Protection function(OCVP), Time Base, LVD, EEPROM and I2C interface. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The interrupt registers fall into three categories. The first is the INTC0~INTC2 registers which setup the primary interrupts, the second is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Enable Bit Request Flag Global Function EMI — — OCVP OCVPE OCVPF — INTn Pin INTnE INTnF n=0 or 1 Multi-function MFnE MFnF n=0~3 Time Base TBnE TBnF n=0 or 1 LVD LVE LVF — EEPROM DEE DEF — I2C IICE IICF — CTMAE CTMAF — CTMPE CTMPF — STMAE STMAF — STMPE STMPF — PTMnAE PTMnAF n=0 or 1 PTMnPE PTMnPF n=0 or 1 Timer Module Notes Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — MF0F INT0F OCVPF MF0E INT0E OCVPE EMI INTC1 TB0F MF3F MF2F MF1F TB0E MF3E MF2E MF1E INTC2 — — INT1F TB1F — — INT1E TB1E MFI0 — — CTMAF CTMPF — — CTMAE CTMPE MFI1 — — STMAF STMPF — — STMAE STMPE MFI2 PTM1AF PTM1PF PTM0AF PTM0PF PTM1AE PTM1PE PTM0AE PTM0PE MFI3 — IICF DEF LVF — IICE DEE LVE Interrupt Register List Rev. 1.00 117 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU INTEG Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3 ~ 2 INT1S1, INT1S0: Defines INT1 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt Bit 1 ~ 0 INT0S1, INT0S0: Defines INT0 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — MF0F INT0F OCVPF MF0E INT0E OCVPE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6MF0F: Multi-function interrupt 0 request flag 0: No request 1: Interrupt request Bit 5INT0F: External interrupt 0 request flag 0: No request 1: Interrupt request Bit 4OCVPF: Over current/voltage protection interrupt request flag 0: No request 1: Interrupt request Bit 3MF0E: Multi-function interrupt 0 control 0: Disable 1: Enable Bit 2 INT0E: External interrupt 0 control 0: Disable 1: Enable Bit 1OCVPE: Over current/voltage protection interrupt control 0: Disable 1: Enable Bit 0EMI: Global Interrupt Control 0: Disable 1: Enable Rev. 1.00 118 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU INTC1 Register Bit 7 6 5 4 3 2 1 0 Name TB0F MF3F MF2F MF1F TB0E MF3E MF2E MF1E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7TB0F: Time Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 6MF3F: Multi-function interrupt 3 request flag 0: No request 1: Interrupt request Bit 5MF2F: Multi-function interrupt 2 request flag 0: No request 1: Interrupt request Bit 4MF1F: Multi-function interrupt 1 request flag 0: No request 1: Interrupt request Bit 3TB0E: Time Base 0 interrupt control 0: Disable 1: Enable Bit 2 MF3E: Multi-function interrupt 3 control 0: Disable 1: Enable Bit 1MF2E: Multi-function interrupt 2 control 0: Disable 1: Enable Bit 0MF1E: Multi-function interrupt 1 control 0: Disable 1: Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Name — — INT1F TB1F — — INT1E TB1E R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5INT1F: External interrupt 1 request flag 0: No request 1: Interrupt request Bit 4TB1F: Time Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0" Bit 1 INT1E: External interrupt 1 control 0: Disable 1: Enable Bit 0TB1E: Time Base 1 interrupt control 0: Disable 1: Enable Rev. 1.00 119 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — CTMAF CTMPF — — CTMAE CTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 CTMAF: CTM comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 CTMPF: CTM comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 CTMAE: CTM comparator A match interrupt control 0: Disable 1: Enable Bit 0 CTMPE: CTM comparator P match interrupt control 0: Disable 1: Enable MFI1 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name — — STMAF STMPF — — STMAE STMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5 STMAF: STM comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4 STMPF: STM comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0" Bit 1 STMAE: STM comparator A match interrupt control 0: Disable 1: Enable Bit 0 STMPE: STM comparator P match interrupt control 0: Disable 1: Enable 120 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU MFI2 Register Bit 7 6 5 4 3 2 1 0 Name PTM1AF PTM1PF PTM0AF PTM0PF PTM1AE PTM1PE PTM0AE PTM0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PTM1AF: PTM1 comparator A match interrupt request flag 0: No request 1: Interrupt request PTM1PF: PTM1 comparator P match interrupt request flag 0: No request 1: Interrupt request PTM0AF: PTM0 comparator A match interrupt request flag 0: No request 1: Interrupt request PTM0PF: PTM0 comparator P match interrupt request flag 0: No request 1: Interrupt request PTM1AE: PTM1 comparator A match interrupt control 0: Disable 1: Enable PTM1PE: PTM1 comparator P match interrupt control 0: Disable 1: Enable PTM0AE: PTM0 comparator A match interrupt control 0: Disable 1: Enable PTM0PE: PTM0 comparator P match interrupt control 0: Disable 1: Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Name — IICF DEF LVF — IICE DEE LVE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Bit 6 Unimplemented, read as "0" IICF: I2C interrupt request flag 0: No request 1: Interrupt request Bit 5DEF: Data EEPROM interrupt request flag 0: No request 1: Interrupt request Bit 4LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2 IICE: I2C interrupt control 0: Disable 1: Enable Bit 1DEE: Data EEPROM interrupt control 0: Disable 1: Enable Bit 0LVE: LVD interrupt control 0: Disable 1: Enable Rev. 1.00 121 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a "JMP" which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a "RETI", which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.00 122 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU E�I auto disabled in ISR Legend xxF Request Flag� no auto reset in ISR xxF Request Flag� auto reset in ISR xxE Enable Bits CT� P CT�PF CT�PE CT� A CT�AF CT�AE ST� P ST�PF ST�PE ST� A ST�AF ST�AE PT�0 P PT�0PF PT�0PE PT�0 A PT�0AF PT�0AE PT�1 P PT�1PF PT�1PE PT�1 A PT�1AF PT�1AE LVD LVF LVE EEPRO� DEF DEE I�C IICF IICE Interrupts contained within �ulti-Function Interrupts Interrupt Name OCVP Request Flags OCVPF Enable Bits OCVPE �aster Enable E�I INT0 Pin INT0F INT0E E�I 08H �. Funct. 0 �F0F �F0E E�I 0CH �. Funct. 1 �F1F �F1E E�I 10H �. Funct. � �F�F �F�E E�I 14H �. Funct. � �F�F �F�E E�I 18H Time Base 0 TB0F TB0E E�I 1CH Time Base 1 TB1F TB1E E�I �0H INT1 Pin INT1F INT1E E�I �4H Vector Priorit� 04H High Low Interrupt Structure External Interrupts The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F, are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective external interrupt enable bit, INT0E~INT1E, must first be set. Additionally the correct interrupt edge type must be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register as well as the relevant pin-shared function selection bits. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Rev. 1.00 123 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU OCVP Interrupt An OCVP interrupt request will take place when the OCVP Interrupt request flag, OCVPF, is set, which occurs when the OCVP circuit detects a specific current or voltage condition. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the OCVP Interrupt enable bit, OCVPE, must first be set. When the interrupt is enabled, the stack is not full and a user-defined current or voltage condition occurs, a subroutine call to the OCVP Interrupt vector, will take place. When the OCVP Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts and the OCVP interrupt request flag will be also automatically cleared. Multi-function Interrupts Within the device there are four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts, LVD Interrupt, I2C Interrupt and EEPROM Interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts, LVD Interrupt, I2C Interrupt and EEPROM Interrupt will not be automatically reset and must be manually reset by the application program. Time Base Interrupts The function of the Time Base interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources which is selected using the TBCK bit in the TBC register. Rev. 1.00 124 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 — TB02 TB01 TB00 R/W R/W R/W R/W R/W — R/W R/W R/W POR 0 0 1 1 — 1 1 1 Bit 7TBON: TB0 and TB1 Control bit 0: Disable 1: Enable Bit 6TBCK: Select fTB Clock Source 0: fTBC 1: fSYS/4 Bit 5 ~ 4 TB11 ~ TB10: Select Time Base 1 Time-out Period 00: 212/fTB 01: 213/fTB 10: 214/fTB 11: 215/fTB Bit 3 Unimplemented, read as "0" Bit 2 ~ 0 TB02 ~ TB00: Select Time Base 0 Time-out Period 000: 28/fTB 001: 29/fTB 010: 210/fTB 011: 211/fTB 100: 212/fTB 101: 213/fTB 110: 214/fTB 111: 215/fTB Time Base Interrupt I2C Interrupt The I2C interrupt is contained within the Multi-function Interrupt.An I2C Interrupt request will take place when the I2C Interrupt request flag, IICF, is set, which occurs when a byte of data has been received or transmitted by the I2C interface, I2C address match or I2C time-out. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, IICE, and associated Multi-function interrupt enable bit, MF3E, must first be set. When the interrupt is enabled, the stack is not full and any of these situations occurs, a subroutine call to the respective I2C interrupt vector, will take place. When the I2C Interface Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the IICF flag will not be automatically cleared, it has to be cleeared by the application program. Rev. 1.00 125 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU EEPROM Interrupt The EEPROM interrupt is contained within the Multi-function Interrupt. An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit, MF3E, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. LVD Interrupt The LVD interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, MF3E, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the LVD Interrupt vector, will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVD interrupt request flag, LVF, will not be automatically cleared, it has to be cleared by the application program. TM Interrupts The Compact, Standard and Periodic Type TMs each have two interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For the different Type TMs there are two interrupt request flags xTMnPF and xTMnAF and two enable bits xTMnPE and xTMnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or comparator A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable bit, MFnF, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant TM Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Rev. 1.00 126 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins or a low power supply voltage may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF3F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 127 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Low Voltage Detector – LVD The device has a Low Voltage Detector function, also known as LVD. This enables the device to monitor the power supply voltage, VDD, and provides a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Name — — LVDO LVDEN — VLVD2 VLVD1 VLVD0 R/W — — R R/W — R/W R/W R/W POR — — 0 0 — 0 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detected 1: Low Voltage Detected Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Rev. 1.00 Bit 3 Unimplemented, read as "0" Bit 2~0 VLVD2 ~ VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V 128 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode. Rev. 1.00 129 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU LCD SCOM Function The device has the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM3, are pin shared with certain pins on the I/O ports. The LCD signals (COM) are generated using the application program. LCD Operation An external LCD panel can be driven using this device by configuring the I/O pins as common pins. The LCD driver function is controlled using the SCOMC register which in addition to controlling the overall on/off function also controls the bias voltage setup function. This enables the LCD COM driver to generate the necessary VDD/2 voltage levels for LCD 1/2 bias operation. The SCOMEN bit in the SCOMC register is the overall master control for the LCD driver. The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function selection bits. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. VDD SCO� operating current VDD/� SCO�0~SCO�� Pin-shared selection bits SCO�EN LCD COM Bias LCD Bias Current Control The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which are being used. The bias resistor choice is implemented using the ISEL1 and ISEL0 bits in the SCOMC register. SCOMC Register Bit 7 6 5 4 3 2 1 0 Name — ISEL1 ISEL0 SCOMEN — — — — R/W — R/W R/W R/W — — — — POR — 0 0 0 — — — — Bit 7 Unimplemented, read as "0" Bit 6~5ISEL1~ISEL0: Select resistor for R type LCD different bias current (VDD=5V) 00: 2×100kΩ (1/2 Bias), IBIAS = 25μA 01: 2×50kΩ (1/2 Bias), IBIAS = 50μA 10: 2×25kΩ (1/2 Bias), IBIAS = 100μA 11: 2×12.5kΩ (1/2 Bias), IBIAS = 200μA Bit 4SCOMEN: LCD function enable control bit 0: Disable 1: Enable When SCOMEN is set high, it will turn on the DC path of resistor to generate 1/2 VDD bias voltage. Bit 3~0 Unimplemented, read as "0" Rev. 1.00 130 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Configuration Option Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Watchdog Timer Option Watchdog Timer Enable/disable Selection: Controlled by WDTC register Always enabled 1 Application Circuit +24V L1 4.7uH +5V C1 24VIN OCVPAI0/INT0/CTCK0/PA3 23 C3 104 + C2 10uF/10V PTP1/PC1 VDD 12 24 4 OCVP0AI0/STP0/PA4 PA2/SCL/ICPCK/OCDSCK OCVP0CI/INT1/STCK0/PA5 PA0/SDA/ICPDA/OCDSDA VSS 5 VREF/PTCK0/PA7 7 8 9 11 13 SCOM3/PB7 PB5/SCOM1 SCOM2/PB6 PB4/SCOM0 1 10 14 R1 R2 2 20K 20K PC3 15 16 PC2 PTCK1/PC0 6 1 104/400V U3 Nebulising Chip 3 3 2 U1 CON1 +24V 2 1 C4 104 C5 104 R3 1 ohm 17 18 19 PC4 OCVPAI0/PB3 PC5 OCVPAI0/PB2 OCVPAO0/CTP0/PA1 OCVPAI0/PB1 OCVPAOI0/PTP0/PA6 OCVPAI0/PB0 22 20 21 HT45F3830_24SOP +24V C8 104 VIN 7805 GND C6 + 10uF/50V U2 2 1 +5V VOUT 3 C9 104 + C7 10uF/10V GND GND Rev. 1.00 131 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 132 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction "RET" in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HALT" instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 133 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] Logical AND Data Memory to ACC OR A,[m] Logical OR Data Memory to ACC XOR A,[m] Logical XOR Data Memory to ACC ANDM A,[m] Logical AND ACC to Data Memory ORM A,[m] Logical OR ACC to Data Memory XORM A,[m] Logical XOR ACC to Data Memory AND A,x Logical AND immediate Data to ACC OR A,x Logical OR immediate Data to ACC XOR A,x Logical XOR immediate Data to ACC CPL [m] Complement Data Memory CPLA [m] Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 134 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Mnemonic Description Cycles Flag Affected Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Read table (specific page) to TBLH and Data Memory Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note 2Note None None None No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read Operation TABRD [m] TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT1" and "CLR WDT2" instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both "CLR WDT1" and "CLR WDT2" instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 135 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 136 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT1 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CLR WDT2 Description Operation Affected flag(s) Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z Rev. 1.00 137 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 138 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None Rev. 1.00 139 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None Rev. 1.00 140 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory is rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None Rev. 1.00 141 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C Rev. 1.00 142 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.00 143 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU TABRD [m] Description Operation Affected flag(s) Read table (specific page) to TBLH and Data Memory The low byte of the program code (specific page) addressed by the table pointer pair (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDC [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 144 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • The Operation Instruction of Packing Materials • Carton information Rev. 1.00 145 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU 16-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.236 BSC — B — 0.154 BSC — C 0.012 — 0.020 C’ — 0.390 BSC — D — — 0.069 E — 0.050 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A — 6 BSC — B — 3.9 BSC — C 0.31 — 0.51 C’ — 9.9 BSC — D — — 1.75 E — 1.27 BSC — F 0.10 — 0.25 G 0.40 — 1.27 H 0.10 — 0.25 α 0° — 8° 146 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU 20-pin NSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A 0.228 0.236 0.244 B 0.146 0.154 0.161 C 0.009 — 0.012 C’ 0.382 0.390 0.398 D — — 0.069 E — 0.032 BSC — F 0.002 — 0.009 G 0.020 — 0.031 H 0.008 — 0.010 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A 5.80 6.00 6.20 B 3.70 3.90 4.10 C 0.23 — 0.30 C’ 9.70 9.90 10.10 1.75 D — — E — 0.80 BSC — F 0.05 — 0.23 G 0.50 — 0.80 H 0.21 — 0.25 α 0° — 8° 147 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU 24-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.606 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7.5 BSC — C 0.31 — 0.51 C’ — 15.4 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 148 May 30, 2016 HT45F3830 Ultrasonic Humidifier 8-Bit Flash MCU Copyright© 2016 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 149 May 30, 2016