A/D 8-Bit Flash MCU with EEPROM HT66F488/HT66F489 Revision: V1.00 Date: ������������������ September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Table of Contents Features............................................................................................................. 7 CPU Features.......................................................................................................................... 7 Peripheral Features.................................................................................................................. 7 General Description ......................................................................................... 8 Selection Table.................................................................................................. 8 Block Diagram................................................................................................... 9 Pin Assignment................................................................................................. 9 Pin Descriptions............................................................................................. 10 Absolute Maximum Ratings........................................................................... 13 D.C. Characteristics........................................................................................ 13 A.C. Characteristics........................................................................................ 15 LVR & LVD Characteristics............................................................................ 16 ADC Electrical Characteristics ..................................................................... 17 Power on Reset Electrical Characteristics................................................... 17 System Architecture....................................................................................... 18 Clocking and Pipelining.......................................................................................................... 18 Program Counter.................................................................................................................... 19 Stack...................................................................................................................................... 20 Arithmetic and Logic Unit – ALU............................................................................................ 20 Flash Program Memory.................................................................................. 21 Structure................................................................................................................................. 21 Special Vectors...................................................................................................................... 21 Look-up Table......................................................................................................................... 22 Table Program Example......................................................................................................... 22 In Circuit Programming.......................................................................................................... 23 On-Chip Debug Support – OCDS.......................................................................................... 24 RAM Data Memory.......................................................................................... 25 Structure................................................................................................................................. 25 General Purpose Data Memory ............................................................................................ 25 Special Purpose Data Memory ............................................................................................. 26 Special Function Register Description......................................................... 27 Indirect Addressing Register – IAR0, IAR1, IAR2.................................................................. 27 Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H.......................................................... 27 Accumulator – ACC................................................................................................................ 29 Program Counter Low Register – PCL................................................................................... 29 Look-up Table Registers – TBLP, TBHP, TBLH...................................................................... 29 Status Register – STATUS .................................................................................................... 29 Rev. 1.00 2 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM EEPROM Data Memory................................................................................... 31 EEPROM Data Memory Structure......................................................................................... 31 EEPROM Registers............................................................................................................... 31 Reading Data from the EEPROM ......................................................................................... 33 Writing Data to the EEPROM................................................................................................. 33 Write Protection...................................................................................................................... 33 EEPROM Interrupt................................................................................................................. 33 Programming Considerations................................................................................................. 34 Oscillator......................................................................................................... 35 Oscillator Overview................................................................................................................ 35 System Clock Configurations................................................................................................. 35 External Crystal/Ceramic Oscillator – HXT............................................................................ 36 Internal RC Oscillator – HIRC................................................................................................ 37 External 32.768kHz Crystal Oscillator – LXT......................................................................... 37 Internal 32kHz Oscillator – LIRC............................................................................................ 38 Supplementary Oscillator....................................................................................................... 38 Operating Modes and System Clocks.......................................................... 39 System Clocks....................................................................................................................... 39 System Operation Modes....................................................................................................... 40 Control Register..................................................................................................................... 41 Fast Wake-up......................................................................................................................... 42 Operating Mode Switching .................................................................................................... 43 Standby Current Considerations............................................................................................ 45 Wake-up................................................................................................................................. 45 Programming Considerations................................................................................................. 46 Watchdog Timer.............................................................................................. 46 Watchdog Timer Clock Source............................................................................................... 46 Watchdog Timer Control Register.......................................................................................... 46 Watchdog Timer Operation.................................................................................................... 48 Reset and Initialisation................................................................................... 49 Reset Functions..................................................................................................................... 49 Reset Initial Conditions.......................................................................................................... 51 Input/Output Ports.......................................................................................... 54 Pull-high Resistors................................................................................................................. 55 Port A Wake-up...................................................................................................................... 55 I/O Port Control Registers...................................................................................................... 55 Pin-shared Functions............................................................................................................. 55 I/O Pin Structures................................................................................................................... 55 I/O Port source current selection............................................................................................ 57 Programming Considerations................................................................................................. 59 Rev. 1.00 3 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Timer Modules – TM....................................................................................... 59 Introduction............................................................................................................................ 59 TM Operation......................................................................................................................... 60 TM Clock Source.................................................................................................................... 60 TM Interrupts.......................................................................................................................... 60 TM External Pins.................................................................................................................... 60 TM Input/Output Pin Control Register.................................................................................... 61 Programming Considerations................................................................................................. 63 Compact Type TM – CTM............................................................................... 64 Compact TM Operation.......................................................................................................... 64 Compact Type TM Register Description................................................................................ 65 Compact Type TM Operating Modes..................................................................................... 69 Standard Type TM – STM............................................................................... 75 Standard TM Operation.......................................................................................................... 75 Standard Type TM Register Description................................................................................ 76 Standard Type TM Operating Modes..................................................................................... 80 Periodic Type TM – PTM0, PTM1................................................................... 90 Periodic TM Operation........................................................................................................... 90 PTM register description........................................................................................................ 91 Periodic Type TM Operating Modes....................................................................................... 95 Analog to Digital Converter......................................................................... 104 A/D Overview....................................................................................................................... 104 A/D Converter Register Description..................................................................................... 104 A/D Converter Data Registers – ADRL, ADRH.................................................................... 105 A/D Converter Control Registers – ADCR0, ADCR1, ACERL.............................................. 105 A/D Operation...................................................................................................................... 108 A/D Input Pins.......................................................................................................................110 Summary of A/D Conversion Steps.......................................................................................110 Programming Considerations................................................................................................112 A/D Transfer Function...........................................................................................................112 A/D Programming Examples.................................................................................................113 Serial Interface Module – SIM.......................................................................115 SPI Interface.........................................................................................................................115 SPI Register..........................................................................................................................116 SPI Communication..............................................................................................................119 I2C Interface......................................................................................................................... 121 I2C Register.......................................................................................................................... 122 I2C Bus Communication....................................................................................................... 126 I2C Bus Start Signal.............................................................................................................. 127 Slave Address...................................................................................................................... 127 I2C Bus Read/Write Signal................................................................................................... 127 I2C Bus Slave Address Acknowledge Signal........................................................................ 127 I2C Bus Data and Acknowledge Signal................................................................................ 128 I2C Time-out Control............................................................................................................. 129 Rev. 1.00 4 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM UART Module Serial Interface..................................................................... 131 UART External Interface...................................................................................................... 131 UART Data Transfer Scheme.............................................................................................. 132 UART Status and Control Registers.................................................................................... 132 Baud Rate Generator........................................................................................................... 138 Calculating the register and error values............................................................................. 138 UART Setup and Control..................................................................................................... 139 Managing receiver errors..................................................................................................... 143 UART Module Interrupt Structure......................................................................................... 144 Address detect mode........................................................................................................... 145 UART Module Power Down and Wake-up........................................................................... 146 Interrupts....................................................................................................... 146 Interrupt Registers................................................................................................................ 146 Interrupt Operation............................................................................................................... 154 External Interrupt.................................................................................................................. 155 Multi-function Interrupt......................................................................................................... 156 A/D Converter Interrupt........................................................................................................ 156 Time Base Interrupts............................................................................................................ 156 Serial Interface Module Interrupts........................................................................................ 157 EEPROM Interrupt............................................................................................................... 158 TM Interrupts........................................................................................................................ 158 LVD Interrupt ....................................................................................................................... 158 UART Interrupt..................................................................................................................... 158 Interrupt Wake-up Function.................................................................................................. 159 Programming Considerations............................................................................................... 159 Software LCD Driver..................................................................................... 160 LCD operation...................................................................................................................... 160 LCD Control Registers......................................................................................................... 160 LCD waveform..................................................................................................................... 165 Low Voltage Detector – LVD........................................................................ 167 LVD Register........................................................................................................................ 167 LVD Operation...................................................................................................................... 168 Configuration Option.................................................................................... 169 Application Circuit........................................................................................ 169 Instruction Set............................................................................................... 170 Introduction.......................................................................................................................... 170 Instruction Timing................................................................................................................. 170 Moving and Transferring Data.............................................................................................. 170 Arithmetic Operations........................................................................................................... 170 Logical and Rotate Operation.............................................................................................. 171 Branches and Control Transfer............................................................................................ 171 Bit Operations...................................................................................................................... 171 Table Read Operations........................................................................................................ 171 Other Operations.................................................................................................................. 171 Rev. 1.00 5 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Instruction Set Summary............................................................................. 172 Table Conventions................................................................................................................ 172 Extended Instruction Set...................................................................................................... 174 Instruction Definition.................................................................................... 176 Extended Instruction Definition............................................................................................ 185 Package Information.................................................................................... 192 28-pin SOP (300mil) Outline Dimensions............................................................................ 193 28-pin SSOP (150mil) Outline Dimensions.......................................................................... 194 Rev. 1.00 6 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Features CPU Features • Operating Voltage ♦♦ fSYS = 8MHz: 2.2V~5.5V ♦♦ fSYS = 10MHz: 2.7V~5.5V ♦♦ fSYS = 12MHz: 3.3V~5.5V ♦♦ fSYS = 16MHz: 4.5V~5.5V • Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V • Power down and wake-up functions to reduce power consumption • Four Oscillators: • External High Frequency Crystal – HXT • External 32.768kHz Crystal-- LXT • Internal High Frequency RC -- HIRC • Internal 32kHz -- LIRC • Fully intergrated internal 8MHz oscillator requires no external components • Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP • All instructions executed in one to three instruction cycles • Table read instructions • 115 powerful instructions • 8-level subroutine nesting • Bit manipulation instruction Peripheral Features • Flash Program Memory: 8K×16 (HT66F489)/4K×16 (HT66F488) • RAM Data Memory: 384×8 • EEPROM Memory: 64×8 • Watchdog Timer function • 30 bidirectional I/O lines • LED driver • 1/3 Bias Software LCD • Serial Interface Module – SIM for SPI or I2C • UART Function • Six pin-shared external interrupts • Multiple Timer Module for time measure, input capture, compare match output, PWM output function or single pulse output function • Dual Time-Base functions for generation of fixed time interrupt signals • 8-channel 12-bit resolution A/D converter • Low voltage reset function • Low voltage detector function • Package: 28-pin SOP/SSOP Rev. 1.00 7 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM General Description The devices are 8-bit high performance RISC architecture microcontroller, designed especially for applications that interface directly to analog signals, such as those from sensor. Offering users the convenience of Flash Memory multi-programming features, this device also includes a wide range of functions and features. Other memory includes an area of RAM Data Memory as well as an area of EEPROM memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter. Multiple and extremely flexible Timer Modules provide timing, pulse generation and PWM generation functions. Communication with the outside world catered for by including fully integrated SPI, I2C and UART interface functions, three popular interfaces which provide designers with a means of easy communication with external peripheral hardware. Protective features such as an internal Watchdog Timer, Low Voltage Reset and Low Voltage Detector coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of HXT, LXT, HIRC and LIRC oscillator functions are provided including a fully integrated system oscillator which requires no external components for its implementation. The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimize power consumption. The inclusion of flexible I/O programming features, Time-Base functions along with many other features ensure that the device will find excellent use in applications such as sensor signal processing, chargers, motor driving, industrial control, consumer product, subsystem controller, etc. Selection Table Most features are common to all devices, the main feature distinguishing them are Memory capacity and whether EEPROM or not. The following table summarises the main features of each device. Part No. Program Memory HT66F488 4K×16 HT66F489 8K×16 Part No. HT66F488 HT66F489 Rev. 1.00 Data Memory Data EEPROM I/O R-type LCD (1/3 Bias) High Current LED Output 384×8 64×8 26 6(SCOM/SSEG) +20SSEG 26 Timer Module RTC A/D Interface Stack Package 10-bit CTM×1 16-bit STM×1 10-bit PTM×2 √ 12-bit×8 SPI/I2C, UART 8 28SOP/SSOP 8 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Block Diagram Watchdog Timer Flash/EEPROM Programming Circuitry (ICP)/OCDS EEPROM Data Memory Flash Program Memory HXT/ LXT Oscillators Internal RC Oscillators Low Voltage Detect 8-bit RISC MCU Core Low Voltage Reset RAM Data Memory Reset Circuit Interrupt Controller Time Bases 12-bit A/D Converter SIM UART I/O CTM STM PTMs Software LCD Pin Assignment PC4/AN4/SSEG22 1 28 PC5/AN5/INT3/SSEG21 PC3/AN3/SSEG23 2 27 PC6/AN6/VREF/INT2/SSEG20 PC0/AN2/SSEG26 3 26 PB1/PTCK0/INT1/AN7/SSEG17 PB7/STP/RX/AN1/SSEG27 4 25 PB2/CTP/INT0/SSEG16 PB6/STCK/TX/AN0/SSEG28 5 24 PB5/SSEG29 6 23 PB3/OSC2/XT2/SSEG15 PB4/OSC1/XT1/ICPCK/SSEG14 VSS/AVSS 7 22 VDD/AVDD PD0/ICPDA/SCOM0/SSEG0 PD1/SCOM1/SSEG1 8 21 PA7/CTCK/SSEG13 9 20 PA6/PTCK1/SCS/SSEG12 PD2/SCOM2/SSEG2 10 19 PA5/PTP1/SCK/SCL/SSEG11 PD3/SCOM3/SSEG3 11 18 PA4/SDI/SDA/SSEG10 PD4/SCOM4/SSEG4 12 17 PA3/SDO/SSEG9 PD5/SCOM5/SSEG5 13 16 PA2/OCDSCK/SSEG8 PA0/OCDSDA/SSEG6 14 15 PA1/SSEG7 HT66F488/489 HT66V488/489 28 SOP-A/SSOP-A Note: 1. If the pin-shared pin functions have multiple outputs simultaneously, the function used is determined by the corresponding software control bit or configuration option. 2. AVDD&VDD means the VDD and AVDD are the double bonding. VSS&AVSS means the VSS and AVSS are the double bonding. 3. HT66V488/489 is the EV chip, and the OCDSDA, OCDSCK pins are for EV chip only. Rev. 1.00 9 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Pin Descriptions Pin Name PA0/OCDSDA/ SSEG6 PA1/SSEG7 PA2/OCDSCK/ SSEG8 PA3/SDO/SSEG9 PA4/SDI/SDA/ SSEG10 Function OPT I/T PA0 PAWU PAPU ST CMOS General purpose I/O. Register enable pull-up and wake-up OCDSDA — ST CMOS OCDS Data/Address pin, for EV chip only SSEG6 SLCDC2 — CMOS Software LCD SEG output PA1 PAWU PAPU ST CMOS General purpose I/O. Register enable pull-up and wake-up SSEG7 SLCDC2 — CMOS Software LCD SEG output PA2 PAWU PAPU ST CMOS General purpose I/O. Register enable pull-up and wake-up OCDSCK — ST SSEG8 SLCDC2 — CMOS Software LCD SEG output PA3 PAWU PAPU ST CMOS General purpose I/O. Register enable pull-up and wake-up — — CMOS SPI Data output SLCDC2 — CMOS Software LCD SEG output PA4 PAWU PAPU ST CMOS General purpose I/O. Register enable pull-up and wake-up SDI — ST SDA — ST NMOS I2C Data CMOS Software LCD SEG output PA5 ST CMOS General purpose I/O. Register enable pull-up and wake-up PTP1 TMPC0 ST CMOS PTM1 input/output SCK — ST CMOS SPI Serial Clock SCL — ST NMOS I2C Clock — CMOS Software LCD SEG output CMOS General purpose I/O. Register enable pull-up and wake-up PA6 PAWU PAPU ST PTCK1 — ST SCS — ST CMOS SPI slaver selection PB2/CTP/INT0/ SSEG16 PTM1 input — CMOS Software LCD SEG output PA7 ST CMOS General purpose I/O. Register enable pull-up and wake-up CTCK — ST — CTM input — CMOS Software LCD SEG output PB0 PBPU ST CMOS General purpose I/O. Register enable pull-up. PTP0 TMPC0 ST CMOS PTM0 output INT4 — ST — External interrupt input — CMOS Software LCD SEG output CMOS General purpose I/O. Register enable pull-up. PB1 PBPU ST PTCK0 — ST — PTM0 input INT1 — ST — External interrupt input AN7 ACERL AN — ADC input SSEG17 SLCDC3 — CMOS Software LCD SEG output PB2 PBPU ST CMOS General purpose I/O. Register enable pull-up. CTP TMPC0 ST CMOS CTM output INT0 — ST SSEG16 SLCDC3 Rev. 1.00 — PAWU PAPU SSEG18 SLCDC3 PB1/PTCK0/ INT1/AN7/ SSEG17 SPI Data input — SSEG13 SLCDC2 PB0/PTP0/INT4/ SSEG18 — PAWU PAPU SSEG12 SLCDC2 PA7/CTCK/ SSEG13 OCDS Clock pin, for EV chip only. SDO SSEG11 SLCDC2 PA6/PTCK1/SCS/ SSEG12 — Description SSEG9 SSEG10 SLCDC2 PA5/PTP1/SCK/ SCL/SSEG11 O/T — — External interrupt input CMOS Software LCD SEG output 10 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Pin Name PB3/OSC2/XT2/ SSEG15 Function OPT I/T PB3 PBPU ST OSC2 CO — HXT HXT pin XT2 CO — LXT LXT pin SSEG15 SLCDC3 PB4/OSC1/ XT1/ICPCK/ SSEG14 PB7/STP/RX/ AN1/SSEG27 PC0/AN2/ SSEG26 PC1/SSEG25 PC2/SSEG24 PC3/AN3/ SSEG23 PC4/AN4/ SSEG22 PC5/AN5/INT3/ SSEG21 Rev. 1.00 CMOS General purpose I/O. Register enable pull-up. ST CO HXT — HXT pin XT1 CO LXT — LXT pin ICPCK — ST — ICP Clock pin — CMOS Software LCD SEG output ST CMOS General purpose I/O. Register enable pull-up. — CMOS Software LCD SEG output PBPU ST CMOS General purpose I/O. Register enable pull-up. STCK — ST TX — — AN0 ACERL AN SSEG28 SLCDC4 — CMOS Software LCD SEG output PB5 PBPU SSEG29 SLCDC4 — STM input CMOS UART data transmission output — ADC input PB7 PBPU ST CMOS General purpose I/O. Register enable pull-up. STP TMPC0 ST CMOS STM input/output RX — ST AN1 ACERL AN SSEG27 SLCDC4 — CMOS Software LCD SEG output CMOS General purpose I/O. Register enable pull-up. — UART data received input — ADC input PC0 PCPU ST AN2 ACERL AN SSEG26 SLCDC4 — CMOS Software LCD SEG output ST CMOS General purpose I/O. Register enable pull-up. — CMOS Software LCD SEG output ST CMOS General purpose I/O. Register enable pull-up. PC1 PCPU SSEG25 SLCDC4 PC2 PCPU SSEG24 SLCDC4 — ADC input — CMOS Software LCD SEG output PC3 PCPU ST CMOS General purpose I/O. Register enable pull-up. AN3 ACERL AN SSEG23 SLCDC4 — CMOS Software LCD SEG output CMOS General purpose I/O. Register enable pull-up. — ADC input PC4 PCPU ST AN4 ACERL AN SSEG22 SLCDC4 — CMOS Software LCD SEG output CMOS General purpose I/O. Register enable pull-up. — ADC input PC5 PCPU ST AN5 ACERL AN — ADC input INT3 — ST — External interrupt input — CMOS Software LCD SEG output CMOS General purpose I/O. Register enable pull-up. PC6 PCPU ST AN6 ACERL AN — ADC input VREF ADCR1 AN — ADC Reference voltage input INT2 — ST — External interrupt input SSEG20 SLCDC3 PC7/INT5/ SSEG19 CMOS Software LCD SEG output PBPU SSEG21 SLCDC3 PC6/AN6/VREF/ INT2/SSEG20 — PB4 PB6 PB6/STCK/TX/ AN0/SSEG28 Description OSC1 SSEG14 SLCDC3 PB5/SSEG29 O/T CMOS General purpose I/O. Register enable pull-up. — CMOS Software LCD SEG output PC7 PCPU ST CMOS General purpose I/O. Register enable pull-up. INT5 — ST SSEG19 SLCDC3 — — External interrupt input CMOS Software LCD SEG output 11 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Pin Name PD0/ICPDA/ SCOM0/SSEG0 PD1/SCOM1/ SSEG1 PD2/SCOM2/ SSEG2 PD3/SCOM3/ SSEG3 PD4/SCOM4/ SSEG4 PD5/SCOM5/ SSEG5 VDD/AVDD VSS/AVSS Function OPT I/T PD0 PDPU ST CMOS General purpose I/O. Register enable pull-up. O/T Description ICPDA — ST CMOS ICP Data/Address pin SCOM0 SLCDC0 SLCDC1 — CMOS Software LCD COM output SSEG0 SLCDC0 SLCDC1 — CMOS Software LCD SEG output PD1 PDPU ST CMOS General purpose I/O. Register enable pull-up. SCOM1 SLCDC0 SLCDC1 — CMOS Software LCD COM output SSEG1 SLCDC0 SLCDC1 — CMOS Software LCD SEG output PD2 PDPU ST CMOS General purpose I/O. Register enable pull-up. SCOM2 SLCDC0 SLCDC1 — CMOS Software LCD COM output SSEG2 SLCDC0 SLCDC1 — CMOS Software LCD SEG output PD3 PDPU ST CMOS General purpose I/O. Register enable pull-up. SCOM3 SLCDC0 SLCDC1 — CMOS Software LCD COM output SSEG3 SLCDC0 SLCDC1 — CMOS Software LCD SEG output PD4 PDPU ST CMOS General purpose I/O. Register enable pull-up. SCOM4 SLCDC1 — CMOS Software LCD COM output SSEG4 SLCDC1 — CMOS Software LCD SEG output PD5 PDPU ST CMOS General purpose I/O. Register enable pull-up. SCOM5 SLCDC1 — CMOS Software LCD COM output SSEG5 SLCDC1 — CMOS Software LCD SEG output VDD — PWR — Positive Power Supply AVDD — PWR — Analog Positive Power Supply VSS — PWR — Negative Power Supply. Ground AVSS — PWR — Analog Negative Power Supply Note: I/T: Input type; O/T: Output type OP: Optional by configuration option (CO) or register option PWR: Power; CO: Configuration option; ST: Schmitt Trigger input CMOS: CMOS output; AN: Analog input pin HXT: High frequency crystal oscillator LXT: Low frequency crystal oscillator *: VDD is the device power supply while AVDD is the ADC power supply. The AVDD pin is bonded together internally with VDD. **: VSS is the device ground pin while AVSS is the ADC ground pin. The AVSS pin is bonded together internally with VSS. Note: 1. This Pin Description Summary table describes all resources which may not be connected to external pins. 2. For 28-SKDIP/SOP package PB0, PC1, PC2 and PC7 are not bonded to external pins and should be properly configured to avoid a floating condition which will result in additional current leakage. Rev. 1.00 12 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Absolute Maximum Ratings Supply Voltage ..................................................................................................VSS−0.3V to VSS+6.0V Input Voltage .................................................................................................... VSS−0.3V to VDD+0.3V Storage Temperature ...................................................................................................... 50˚C to 125˚C Operating Temperature . ................................................................................................... 40˚C to 85˚C IOH Total .................................................................................................................................... -150mA IOL Total ..................................................................................................................................... 100mA Total Power Dissipation ........................................................................................................... 500mW Note: T hese are stress ratings only. Stresses exceeding the range specified under “Absolute Maximum Ratings” may cause substantial damage to these devices. Functional operation of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability. D.C. Characteristics Ta=25°C Symbol VDD Parameter Operating Voltage (HXT) Operating Voltage (HIRC) Test Conditons Min. Typ. Max. Unit fSYS=8MHz 2.2 — 5.5 V fSYS=10MHz 2.7 — 5.5 V fSYS=12MHz 3.3 — 5.5 V fSYS=16MHz 4.5 — 5.5 V — fSYS=8MHz 2.2 — 5.5 V 3V No load, fSYS= fH =8MHz ADC off, WDT enable — 1.0 1.5 mA — 2.5 4.0 mA No load, fSYS= fH =10MHz ADC off, WDT enable — 1.2 2.0 mA — 2.8 4.5 mA 5V No load, fSYS= fH =12MHz ADC off, WDT enable — 3.5 5.5 mA 5V No load, fSYS= fH =16MHz ADC off, WDT enable — 4.5 7.0 mA — 1.2 2.0 mA — 2.8 4.5 mA 5V No load, fSYS= fH/2, ADC off, WDT enable — 2.1 3.3 mA 5V No load, fSYS= fH/4, ADC off, WDT enable — 1.6 2.5 mA 5V No load, fSYS= fH/8, ADC off, WDT enable — 1.2 2.5 mA 5V No load, fSYS= fH/16 ADC off, WDT enable — 1.1 2.0 mA 5V No load, fSYS= fH/32, ADC off, WDT enable — 1.0 2.0 mA 5V No load, fSYS= fH/64, ADC off, WDT enable — 1.0 2.0 mA — 5V 3V Operating Current, Normal Mode, fSYS =fH (HXT), fS =fLIRC Operating Current, Normal Mode, fSYS=fH(HIRC), fS=fLXT or fLIRC IDD Operating Current, Slow Mode 1 fH =12MHz (HXT), fS =fLIRC Rev. 1.00 Conditons VDD 5V 3V 5V No load, fSYS= fH =8MHz ADC off, WDT enable 13 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Symbol Parameter Test Conditons 3V IDD ISTB Operating Current, Slow Mode 0 fSYS=fS=fLXT VIL VIH IOL 5V 3V 5V Operating Current, Slow Mode 0 fSYS=fS=fLIRC 3V Standby Current, IDLE Mode (fSYS=off, fS=fSUB= fLIRC) 3V Standby Current, SLEEP Mode (fSYS=off, fS=fSUB= fLIRC) 3V Standby Current, SLEEP Mode fSYS=12MHz (HXT), fSYS =off, fS=fSUB= fLIRC Input Low Voltage for I/O Ports Input High Voltage for I/O Ports I/O Port Sink Current Large Sink I/O (PD) I/O Port Sink Current (PA, PB, PC) 5V 5V 5V — IBIAS Bias current for LCD Unit No load, ADC off, WDT enable, LXTLP=0 — 15 25 μA — 30 50 μA No load, ADC off, WDT enable, LXTLP=1 — 10 20 μA — 25 45 μA No load, ADC off, WDT enable — 10 20 μA — 20 40 μA No load, system HALT, IDLEN=1, WDT enable — 1.3 3.0 μA — 2.2 5.0 μA No load, system HALT, IDLEN=0, WDT enable — 1.3 3.0 μA — 2.2 5.0 μA — 65 95 μA No load, system HALT, ADC off, WDT enable — 0 — 1.5 V — 0 — 0.2VDD V 5V — 3.5 — 5 V — — 0.8VDD — VDD V 200 — mA 5V VOL=1.5V 120 3V VOH=0.1VDD 15 30 — mA 5V VOH=0.1VDD 30 60 — mA 3V VOL=0.1VDD 15 30 — mA 5V VOL=0.1VDD 30 60 — mA VOH=0.9VDD, select full source current option -3.0 -6.0 — mA VOH=0.9VDD, select 10/22 full source current option -1.5 -3.0 — mA VOH=0.9VDD, select 7/22 full source current option -1.0 -2.0 — mA VOH=0.9VDD, select 4/22 full source current option -0.8 -1.5 — mA VOH=0.9VDD, select full source current option -9.0 -18.0 — mA VOH=0.9VDD, select 10/22 full source current option -4.0 -8.0 — mA VOH=0.9VDD, select 7/22 full source current option -3.0 -6.0 — mA VOH=0.9VDD, select 4/22 full source current option -2.0 -3.6 — mA 20 60 100 kΩ I/O Port Source Current (PA, PB, PC, PD) Pull-high Resistance Max. — 5V RPH Typ. 5V 3V IOH Min. Conditons VDD 3V — 5V 5V 10 30 50 kΩ ISEL[1:0]=00 4.2 8.3 13 μA ISEL[1:0]=01 8.3 16.7 25 μA ISEL[1:0]=10 25 50 75 μA ISEL[1:0]=11 50 100 150 μA VSEG_H 1/3 bias LCD SEG output (SEG_H) 2.2~5.5V No load 0.645 0.67 0.695 VDD VSEG_L 1/3 bias LCD SEG output (SEG_L) 2.2~5.5V No load 0.305 0.33 0.355 VDD Rev. 1.00 14 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM A.C. Characteristics Ta=25°C Symbol Parameter System clock (HXT) fSYS System clock (LIRC) tSST tRSTD Min. Typ. 2.2V~5.5V 0.4 2.7V~5.5V 0.4 3.3V~5.5V Conditions — 4.5V~5.5V System clock (HIRC) System clock (LXT) tTIMER Test Conditons VDD xTCKn Input Pin Minimun Pulse width System Start-up Timer Period (wake up from HALT) 5V — 5V — Unit — 8 MHz — 10 MHz 0.4 — 12 MHz 0.4 — 16 MHz -2% 8 2% MHz — 32768 — Hz -10% 32 +10% kHz -50% 32 +60% kHz 0.06 0.15 0.3 μs fSYS=HXT 128 — — tSYS fSYS=LXT 128 — — tSYS fSYS=HIRC 16 — — tSYS fSYS=LIRC 2 — — tSYS Ta=0°C~70°C — Ta=25°C 2.2V~5.5V Ta=-40°C~85°C — Max. — System Start-up Timer Period (wake up from HALT, fSYS on at HALT) — — 2 — — tSYS System Reset Delay Time (POR, LVR, LVR S/W, WDT S/W reset) — — 25 50 100 ms System Reset Delay Time (WDT reset) — — 8.3 16.7 33.3 ms tINT Interrupt Minimum Pulse Width — — 1 3.3 5 μs tLVR Low Voltage width to reset — — 120 240 480 μs tSRESET Software Reset width to reset — — 45 90 120 μs tEERD EEPROM Read Time — — 1 2 4 tSYS tEEWR EEPROM Write Time — — 1 2 4 ms Note: tSYS=1/fSYS Rev. 1.00 15 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LVR & LVD Characteristics Ta=25°C Symbol VLVR VLVD ILVR Parameter Low Voltage Reset Voltage Low Voltage Detector Voltage Additional Power Consumption if LVR is Used Test Conditions — — 3V 5V 3V ILVD Additional Power Consumption if LVD is Used Conditions VDD 5V 3V 5V Min. Typ. LVR Enable, 2.10V option 2.10 LVR Enable, 2.55V option 2.55 LVR Enable, 3.15V option -5% 3.15 Max. Unit V +5% V V LVR Enable, 3.80V option 3.80 V LVDEN = 1, VLVD = 2.0V 2.0 V LVDEN = 1, VLVD = 2.2V 2.2 V LVDEN = 1, VLVD = 2.4V 2.4 V LVDEN = 1, VLVD = 2.7V LVDEN = 1, VLVD = 3.0V -5% 2.7 3.0 +5% V V LVDEN = 1, VLVD = 3.3V 3.3 LVDEN = 1, VLVD = 3.6V 3.6 V LVDEN = 1, VLVD = 4.0V 4.0 V LVR disable→LVR enable LVD disable→LVD enable (LVR disable) LVD disable→LVD enable (LVR enable) V — 30 45 — 60 90 μA μA ─ 40 60 μA ─ 75 115 μA ─ 30 45 μA ─ 60 90 μA tLVR Low Voltage Width to Reset — — 120 240 480 μs tLVD Low Voltage Width to Interrupt — — 65 125 250 μs — LVD disable→LVD enable (LVR enable) — — 15 μs — LVD disable→LVD enable (LVR disable) — — 200 μs tLVDS Rev. 1.00 LVDO stable time 16 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM ADC Electrical Characteristics Ta=25°C Symbol Test Conditons Parameter Min. Typ. VDD Conditons 2.7V~5.5V — 0 3V/5V — 2.0 Max. Unit — AVDD/VREF V — AVDD+0.1 V tAD VAD ADC Input Voltage VREF ADC Reference Voltage tADC A/D Conversion Time 2.7V~5.5V 12-bit ADC — 16 — tAD A/D Clock Period 2.7V~5.5V — 0.5 — 10 μs tON2ST A/D Converter On-to-Start Time 2.7V~5.5V — 2 — — μs DNL1 A/D Differential Non-linearity 3V/5V VREF=VDD, tAD=0.5μs Ta=25°C -3 — +3 LSB DNL2 A/D Differential Non-linearity 3V/5V VREF=VDD, tAD=0.5μs Ta=-40°C ~ 85°C -4 — +4 LSB INL1 A/D Integral Non-linearity 3V/5V VREF=VDD, tAD=0.5μs Ta=25°C -4 — +4 LSB INL2 A/D Integral Non-linearity 3V/5V VREF=VDD, tAD=0.5μs Ta=-40°C ~ 85°C -6 — +6 LSB IADC Additonal Power consumption if A/D Converter is used 3V — 1.0 2.0 mA — 1.5 3.0 mA tBGS VBG turn on stable time — — 10 — — ms VBG Bandgap reference with buffer voltage — — +5% V IBG Additional power consumption if reference with buffer is used — — 300 μA No load, tAD=0.5μs 5V -5% 1.25 — 200 Power on Reset Electrical Characteristics Ta = 25°C Symbol Test Conditions Parameter VDD Conditions Min. Typ. Max. Unit VPOR VDD Start Voltage to Ensure Power-on Reset ─ ─ ─ ─ 100 mV RRVDD VDD Rising Rate to Ensure Power-on Reset ─ ─ 0.035 ─ ─ V/ms tPOR Minimum time for VDD Stays at VPOR to ensure Power-on Reset ─ ─ 10 ─ ─ ms Rev. 1.00 17 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM System Architecture A key factor in the high-performance features of the Holtek range of microcontrollers is attributed to their internal system architecture. The device takes advantage of the usual features found within RISC microcontrollers providing increased speed of operation and Periodic performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. This makes the device suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT, LXT, HIRC or LIRC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. System Clock and Pipelining Rev. 1.00 18 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Instruction Fetching Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as “JMP” or “CALL” that demand a jump to a nonconsecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter Program Counter High byte PCL Register HT66F488 PC11~PC8 PCL7~PCL0 HT66F489 PC12~PC8 PCL7~PCL0 The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Rev. 1.00 19 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer, and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. P ro g ra m T o p o f S ta c k S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k P o in te r B o tto m C o u n te r S ta c k L e v e l 3 o f S ta c k P ro g ra m M e m o ry S ta c k L e v e l 8 Arithmetic and Logic Unit – ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions: • Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA, LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA • Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA, LAND, LANDM, LOR, LORM, LXOR, LXORM, LCPL, LCPLA • Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC, LRR, LRRA, LRRCA, LRRC, LRLA, LRLCA, LRLC • Increment and Decrement: INCA, INC, DECA, DEC, LINCA, LINC, LDECA, LDEC • Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI, LSNZ, LSZ, LSZA, LSIZ, LSDZ, LSIZA, LSDZA Rev. 1.00 20 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Flash Program Memory The Program Memory is the location where the user code or program is stored. For this device the Program Memory is Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, this Flash device offers users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Structure The Program Memory has a capacity of 4K×16 bits to 8K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by a separate table pointer register. Device Capacity HT66F488 4K×16 HT66F489 8K×16 HT66F489 HT66F488 0000H 0000H Reset 0004H Interrupt Vector Interrupt Vector 003CH 003CH 0FFFH Reset 0004H 16 bits 1FFFH 16 bits Program Memory Structure Special Vectors Within the Program Memory, certain locations are reserved for the reset and interrupts. The location 000H is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. Rev. 1.00 21 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register, TBLP and TBHP. These registers define the total address of the look-up table. After setting up the table pointer, the table data can be retrieved from the Program Memory using the “TABRD [m]” or “TABRDL [m]” instructions respectively when the memory [m] is located in sector 0. If the memory [m] is located in other sectors, the table data can be retrieved from the Program Memory using the “LTABRD [m]” or “LTABRDL [m]” instructions respectively. When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as 0. The accompanying diagram illustrates the addressing data flow of the look-up table. A d d re s s L a s t p a g e o r T B H P R e g is te r T B L P R e g is te r D a ta 1 6 b its R e g is te r T B L H U s e r S e le c te d R e g is te r H ig h B y te L o w B y te Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data located in the Program Memory which is stored there using the ORG statement. The value at this ORG statement is “F00H” which refers to the start address of the last page within the 4K words Program Memory of the HT66F488 device. The table pointer is setup here to have an initial value of “06H”. This will ensure that the first data read from the data table will be at the Program Memory address “F06H” or 6 locations after the start of the present page. Note that the value for the table pointer is referenced to the first address of the last page if the “TABRDL [m]” or “LTABRDL [m]” instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the “TABRDL [m]” or “LTABRDL [m]” instruction is executed. Because the TBLH register a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Rev. 1.00 22 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 : : mov a,06h ; initialise low table pointer - note that this address is referenced mov tblp,a ; to the last page : : tabrdl tempreg1 ; transfers value in table referenced by table pointer data at program ; memory address “F06H” transferred to tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; data at program memory address “F05H” transferred to ; tempreg2 and TBLH ; in this example the data “1AH” is transferred to tempreg1 and data “0FH” ; to register tempreg2 : : org F00h; sets initial address of program memory dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : In Circuit Programming The provision of Flash type Program Memory provides the user with a means of convenient and easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in-circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then programming or upgrading the program at a later stage. This enables product manufacturers to easily keep their manufactured products supplied with the latest program releases without removal and re-insertion of the device. The Holtek Flash MCU to Writer Programming Pin correspondence table is as follows: Holtek Write Pins MCU Programming Pins ICPDA PD0 Programming Serial Data Function ICPCK PB4 Programming Serial Clock VDD VDD Power Supply VSS VSS Ground The Program Memory and EEPROM data memory can both be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. Two additional lines are required for the power supply and ground. The technical details regarding the in-circuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user must take care to ensure that no other outputs are connected to the PD0 and PB4 pins. Rev. 1.00 23 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Note: * may be resistor or capacitor. The resistance of * must be greater than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip, HT66V488/489, which is used to emulate the HT66F488/HT66F489 device. This EV chip device also provides an “On-Chip Debug” function to debug the device during the development process. The EV chip and the actual MCU devices are almost functionally compatible except for the “On-Chip Debug” function. Users can use the EV chip device to emulate the real chip device behavior by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip for debugging, other functions which are shared with the OCDSDA and OCDSCK pins in the actual MCU device will have no effect in the EV chip. For a more detailed OCDS description, refer to the corresponding document named “Holtek e-Link for 8-bit MCU OCDS User’s Guide”. Rev. 1.00 Holtek e-Link Pins EV Chip Pins OCDSDA OCDSDA OCDS Data/Address input/output OCDSCK OCDSCK OCDS Clock input VDD VDD Power Supply GND VSS Ground 24 Pin Description September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM RAM Data Memory The Data Memory is an 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The Data Memory is divided into several sectors, all of which are implemented in 8-bit wide Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The start address of the Special Purpose Data Memory for all devices is the address 00H while the start address of the General Purpose Data Memory is the address 80H. The Special Purpose Data Memory registers are accessible in all sectors, with the exception of the EEC register at address 40H, which is only accessible in Sector 1. Device HT66F488 HT66F489 Capacity Sectors General Purpose: 384×8 0: 80H~FFH 1: 80H~FFH 2: 80H~FFH 00H Sector 0 Special Purpose Data Memory 40H in sector 1 7FH 80H General Purpose Data Memory FFH Sector 0 Sector 1 Sector 2 Data Memory Structure General Purpose Data Memory There are 384 bytes of general purpose memory which are arranged in 80H~FFH of Sector 0~Sector 2. All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. The general purpose data memory is fully accessible by the user program for both read and writing operations. By using the "SET [m].i" and "CLR [m].i" instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Rev. 1.00 25 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. They are overlapped in any sector. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Special Function Register section. Note that for locations that are unused before 80H, any read instruction to these addresses will return the value "00H". 00H 01H 0�H 03H 0�H 0�H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 1�H 13H 1�H 1�H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH �0H �1H ��H �3H ��H ��H �6H �7H �8H �9H �AH �BH �CH �DH �EH �FH 30H 31H 3�H 33H 3�H 3�H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH �ecto� 0~� IAR0 MP0 IAR1 MP1L MP1H ACC PCL TBLP TBLH TBHP �TATU� �MOD IAR� MP�L MP�H Unused INTC0 INTC1 INTC� INTC3 MFI0 MFI1 MFI� Unused PAWU PAPU PA PAC PBPU PB PBC PCPU PC PCC PDPU PD PDC IOHR0 IOHR1 Unused ADRL ADRH ADCR0 ADCR1 ACERL TMPC0 CTMC0 CTMC1 CTMDL CTMDH CTMAL CTMAH �TMC0 �TMC1 �TMDL �TMDH �TMAL �TMAH �TMRP �IMTOC �IMC0 �IMC1 �IMD �IMC�/�IMA �ecto� 0� � �ecto� 1 EEC �0H Unused �1H EEA ��H EED �3H PTM0C0 ��H PTM0C1 PTM0DL ��H �6H PTM0DH �7H PTM0AL �8H PTM0AH �9H PTM0RPL PTM0RPH �AH �BH PTM1C0 �CH PTM1C1 �DH PTM1DL �EH PTM1DH PTM1AL �FH �0H PTM1AH PTM1RPL �1H ��H PTM1RPH �3H INTEG0 ��H INTEG1 ��H WDTC �6H TBC �7H CTRL �8H LVRC �9H LVDC Unused �AH �BH U�R �CH UCR1 �DH UCR� �EH BRG �FH TXR/RXR 60H �LCDC0 61H �LCDC1 �LCDC� 6�H 63H �LCDC3 6�H �LCDC� 6�H Unused 66H Unused 67H Unused 68H IOHR� 69H IOHR3 6AH Unused 6BH Unused Unused 6CH 6DH Unused Unused 6EH Unused 6FH 70H Unused 71H Unused 7�H Unused 73H Unused 7�H Unused 7�H Unused 76H Unused 77H Unused 78H Unused 79H Unused 7AH Unused 7BH Unused 7CH Unused 7DH Unused 7EH Unused 7FH Unused : Unused� �ead as 00H Special Purpose Data Memory Rev. 1.00 26 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Special Function Register Description Most of the Special Function Register details will be described in the relevant functional sections, however several registers require a separate description in this section. Indirect Addressing Register – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair, IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of “00H” and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1L, MP1H, MP2L, MP2H Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. The following example shows how to clear a sector of four Data Memory locations already defined as locations adres1 to adres4. Rev. 1.00 27 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Indirect Addressing Program Example 1 data.section ‘data’ adres1 db? adres2 db? adres3 db? adres4 db? block db? code.section at 0 code org 00h start: mov a, 04h; mov block, a mov a, offset adres1 ; mov mp0, a ; loop: clr IAR0 ; inc mp0; sdz block; jmp loop continue: setup size of block Accumulator loaded with first RAM address setup memory pointer with first RAM address clear the data at address defined by MP0 increment memory pointer check if last memory location has been cleared Indirect Addressing Program Example 2 data .section at 01F0H ´data´ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ´code´ org00h start: mov a,04h; mov block,a mov a, 01h; mov mp1h, a mov a,offset adres1 ; mov mp1l,a ; loop: clr IAR1 ; inc mp1l ; sdz block ; jmp loop continue: setup size of block setup the memory sector Accumulator loaded with first RAM address setup memory pointer with first RAM address clear the data at address defined by MP1L increment memory pointer MP1L check if last memory location has been cleared The important point to note here is that in the example shown above, no reference is made to specific Data Memory addresses. Rev. 1.00 28 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Accumulator – ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user-defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP and TBHP are the table pointers and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the “INC” or “DEC” instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the SC flag, CZ flag, zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/ logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the “CLR WDT” or “HALT” instruction. The PDF flag is affected only by executing the “HALT” or “CLR WDT” instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations. • SC is the result of the “XOR” operation which is performed by the OV flag and the MSB of the current instruction operation result. • CZ is the operational result of different flags for different instuctions. Refer to register definitions for more details. • C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. Rev. 1.00 29 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM • AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. • Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. • OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. • PDF is cleared by a system power-up or executing the “CLR WDT” instruction. PDF is set by executing the “HALT” instruction. • TO is cleared by a system power-up or executing the “CLR WDT” or “HALT” instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Name SC CZ TO PDF OV Z AC C R/W R/W R/W R R R/W R/W R/W R/W POR x x 0 0 x x x x “x” unknown Bit 7SC: The result of the “XOR” operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6CZ: The the operational result of different flags for different instructions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/SBCM/LSBC/LSBCM instructions, the CZ flag is the “AND” operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag will not be affected. Bit 5TO: Watchdog Time-Out flag 0: After power up or executing the “CLR WDT” or “HALT” instruction 1: A watchdog time-out occurred. Bit 4PDF: Power down flag 0: After power up or executing the “CLR WDT” instruction 1: By executing the “HALT” instruction Bit 3OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa. Bit 2Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation C is also affected by a rotate through carry instruction. Rev. 1.00 30 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM EEPROM Data Memory One of the special features in the device is its internal EEPROM Data Memory. EEPROM, which stands for Electrically Erasable Programmable Read Only Memory, is by its nature a non-volatile form of memory, with data retention even when its power supply is removed. By incorporating this kind of data memory, a whole new host of application possibilities are made available to the designer. The availability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller. The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits for the device. Unlike the Program Memory and RAM Data Memory, the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory. Read and Write operations to the EEPROM are carried out in single byte operations using an address and data register in Sector 0 and a single control register in Sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory. These are the address register, EEA, the data register, EED and a single control register, EEC. As both the EEA and EED registers are located in all sectors, they can be directly accessed in the same was as any other Special Function Register. The EEC register however, being located in Sector 1, cannot be directly addressed directly and can only be read from or written to indirectly using the MP1L/MP1H or MP2L/MP2H Memory Pointer and Indirect Addressing Register, IAR1 or IAR2. Because the EEC control register is located at address 40H in Sector 1, the MP1L or MP2L Memory Pointer low byte must first be set to the value 40H and the MP1H or MP2H Memory Pointer high byte set to the value 01H before any operations on the EEC register are executed. Register Name Bit 7 6 5 4 3 2 1 0 EEA — — D5 D4 D3 D2 D1 D0 EED D7 D6 D5 D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Control Registers List EEA Register Bit 7 6 5 4 3 2 1 0 Name — — D5 D4 D3 D2 D1 D0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as “0” Bit 5~0D5~D0: Data EEPROM address Data EEPROM address bit 5 ~ bit 0 Rev. 1.00 31 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM EED Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: Data EEPROM data Data EEPROM data bit 7 ~ bit 0 EEC Register Bit 7 6 5 4 3 2 1 0 Name — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3WREN: Data EEPROM Write Enable 0: Disable 1: Enable This is the Data EEPROM Write Enable Bit which must be set high before Data EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2WR: EEPROM Write Control 0: Write cycle has finished 1: Activate a write cycle This is the Data EEPROM Write Control Bit and when set high by the application program will activate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no effect if the WREN has not first been set high. Bit 1RDEN: Data EEPROM Read Enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero will inhibit Data EEPROM read operations. Bit 0RD: EEPROM Read Control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the application program will activate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no effect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to “1” at the same time in one instruction. The WR and RD can not be set to “1” at the same time. Rev. 1.00 32 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Reading Data from the EEPROM To read data from the EEPROM, the read enable bit, RDEN, in the EEC register must first be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register. The data will remain in the EED register until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM The EEPROM address of the data to be written must first be placed in the EEA register and the data placed in the EED register. To write data to the EEPROM, the write enable bit, WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the EEC register must be immediately set high to initiate a write cycle. These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller, informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered-on the Write Enable bit in the control register will be cleared preventing any write operations. Also at power-on MP1L/MP1H and MP2L/MP2H will be reset to zero, which means that Data Memory Sector 0 will be selected. As the EEPROM control register is located in Sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the Write Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register. When an EEPROM write cycle ends, the DEF request flag will be set. If the global and EEPROM interrupts are enabled and the stack is not full, a jump to the associated Interrupt vector will take place. When the interrupt is serviced the EEPROM interrupt flag will be automatically reset. More details can be obtained in the Interrupt section. Rev. 1.00 33 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the Write Enable bit is normally cleared to zero when not writing. Also the Bank Pointer could be normally cleared to zero as this would inhibit access to Bank 1where the EEPROM control register exist. Although certainly not necessary, consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly. The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples Reading data from the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A SET IAR1.1 SET IAR1.0 BACK: SZ IAR1.0 JMP BACK CLR IAR1 CLR BP MOV A, EED MOV READ_DATA, A ; user defined address ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; set RDEN bit, enable read operations ; start Read Cycle - set RD bit ; check for read cycle end ; disable EEPROM read/write ; move read data to register Writing Data to the EEPROM - polling method MOV A, EEPROM_ADRES MOV EEA, A MOV A, EEPROM_DATA MOV EED, A MOV A, 040H MOV MP1L, A MOV A, 01H MOV MP1H, A CLR EMI SET IAR1.3 SET IAR1.2 SET EMI BACK: SZ IAR1.2 JMP BACK CLR IAR1 CLR MP1H Rev. 1.00 ; user defined address ; user defined data ; setup memory pointer MP1L ; MP1 points to EEC register ; setup memory pointer MP1H ; ; ; ; diable global interrupt set WREN bit, enable write operations start Write Cycle - set WR bit enable global interrupt ; check for write cycle end ; disable EEPROM write 34 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Oscillator Various oscillator options offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and registers. Oscillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts. The external oscillators requiring some external components as well as fully integrated internal oscillators requiring no external components are provided to form a wide range of both fast and slow system oscillators. All oscillator options are selected through the configuration options. The higher frequency oscillator provides higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. With the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/ power ratio, a feature especially important in power sensitive portable applications. Name Freq. Pins External Crystal Type HXT 400kHz~20MHz OSC1/OSC2 Internal High Speed RC HIRC 8MHz — External low speed Crystal LXT 32.768kHz XT1/XT2 Internal Low Speed RC LIRC 32kHz — Oscillator Types System Clock Configurations There are four methods of generating the system clock, two high speed oscillators and two low speed oscillators. The high speed oscillators are the external crystal oscillator and the internal 8MHz RC oscillator. The low speed oscillators are the external 32.768kHz crystal oscillator and internal 32kHz RC oscillator. Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for each of the high speed and the low speed oscillators is chosen via configuration options. The frequency of the slow speed or high speed system clock is also determined using the HLCLK bit and CKS2 ~ CKS0 bits in the SMOD register. Note that two oscillator selections must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator. Rev. 1.00 35 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM High Speed Oscillators HXT fH 6-stage Prescaler HIRC fH/2 fH/4 High Speed Oscillator Configuration Option fH/8 fH/16 Low Speed Oscillators LXT fH/32 fH/64 fL fL fSYS LIRC fSUB Low Speed Oscillator Configuration Option HLCLK, CKS2~CKS0 bits Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) Note: The OSC1/XT1 and OSC2/XT2 share the same pins, so the HXT oscillator and the LXT oscillator can not be selected at the same time. System Clock Configurations External Crystal/Ceramic Oscillator – HXT The External Crystal/Ceramic System Oscillator is one of the high frequency oscillator choices, which is selected via configuration option. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring external capacitors. However, for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Crystal/Resonator Oscillator – HXT Rev. 1.00 36 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Crystal Oscillator C1 and C2 Values Crystal Frequency C1 C2 12MHz 0pF 0pF 8MHz 0pF 0pF 4MHz 0pF 0pF 1MHz 100pF 100pF Note: C1 and C2 values are for guidance only. Crystal Recommended Capacitor Values Internal RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at temperature of 25°C degrees, the fixed oscillation frequency of the HIRC will have a tolerance within 2%. PB3 and PB4 can be used as normal I/O pins. External 32.768kHz Crystal Oscillator – LXT The External 32.768kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via configuration option. This clock source has a fixed frequency of 32.768kHz and requires a 32.768kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768kHz crystal are necessary to provide oscillation. For applications where precise frequencies are essential, these components may be required to provide frequency compensation due to different crystal manufacturing tolerances. During power-up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched off to stop microcontroller activity and to conserve power. However, in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. To do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer specification. The external parallel feedback resistor, Rp, is required. Some configuration options determine if the XT1/XT2 pins are used for the LXT/HXT oscillator or as I/O pins. • If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/ O pins or HXT oscillator. • If the LXT oscillator is used for any clock source, the 32.768kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the effects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Rev. 1.00 37 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM External LXT Oscillator LXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 32.768kHz 10pF 10pF Note: 1. C1 and C2 values are for guidance only. 2. RP=5MΩ~10MΩ is recommended. 32.768kHz Crystal Recommended Capacitor Values LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the TBC register. LXTLP LXT Mode 0 Quick Start Mode 1 Low Power Mode After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly. However, after the LXT oscillator has fully powered up it can be placed into the Low-power mode by setting the LXTLP bit high. The oscillator will continue to run but with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It should be noted that, no matter what condition the LXTLP bit is set to, the LXT oscillator will always function normally, the only difference is that it will take more time to start up if in the Lowpower mode. Internal 32kHz Oscillator – LIRC The Internal 32kHz System Oscillator is the low frequency oscillator. It is a fully integrated RC oscillator with a typical frequency of 32kHz at 5V, requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 32kHz will have a tolerance within 10%. Supplementary Oscillator The low speed oscillator, in addition to providing a system clock source is also used to provide a clock source to two other device functions. These are the Watchdog Timer and the Time Base Interrupts. Rev. 1.00 38 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible, conflicting requirements that are especially true in battery powered portable applications. The fast clocks required for high performance will by their nature increase current consumption and of course vice-versa, lower speed clocks reduce current consumption. As Holtek has provided this device with both high and low speed clock sources and the means to switch between them dynamically, the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks The device has many different clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock options using configuration options and register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency, fH, or a low frequency, fL, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register. The high speed system clock can be sourced from either an HXT or HIRC oscillator, selected via a configuration option. The low speed system clock source can be sourced from internal clock fL. If fL is selected then it can be sourced by either the LXT or LIRC oscillator, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. There are two additional internal clocks for the peripheral circuits, the substitute clock, fSUB, and the Time Base clock, fTBC. Each of these internal clocks is sourced by the LIRC or LXT oscillator. The fSUB clock is used to provide a substitute clock for the microcontroller just after a wake-up has occurred to enable faster wake-up times. The fSUB is used for the Watchdog Timer while the fTBC provides the clock for the Time base and TMs. High Speed Oscillators HXT fH 6-stage Prescaler HIRC fH/2 fH/4 High Speed Oscillator Configuration Option fH/8 fH/16 Low Speed Oscillators LXT fH/32 fH/64 fL fL fSYS LIRC fSUB Low Speed Oscillator Configuration Option HLCLK, CKS2~CKS0 bits Fast Wake-up from SLEEP Mode or IDLE Mode Control (for HXT only) fSUB WDT fTBC fTB fSYS/4 Time Base TBCK System Clock Configurations Note: When the system clock source fSYS is switched to fL from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use. Rev. 1.00 39 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM System Operation Modes There are 6 different modes of operation for the microcontroller, each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application. There are three modes allowing normal operation of the microcontroller, the NORMAL, SLOW0 and SLOW1 Mode. The remaining three modes, the SLEEP, IDLE0 and IDLE1 Modes are used when the microcontroller CPU is switched off to conserve power. Operating Mode Description CPU fSYS fSUB fTBC NORMAL mode On fH~fH/64 On On SLOW0 mode On fL On On SLOW1 mode On fH/2~fH/64 On On ILDE0 mode Off Off On On IDLE1 mode Off On On On SLEEP mode Off Off On Off NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operates allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, HXT or HIRC. SLOW0 Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The clock source used will be from the low speed oscillator LIRC or LXT. Running the microcontroller in this mode allows it to run with much lower operating currents. In the SLOW Mode 0, the fH is off. SLOW1 Mode This is also a mode where the microcontroller operates normally although now with a slower speed clock source. The high speed oscillator will however first be divided by a ratio ranging from 2 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SMOD register. Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLEEP Mode The SLEEP Mode is entered when an HALT instruction is executed and the IDLEN bit in the SMOD register is low. In the SLEEP mode the CPU will be stopped. However the fSUB clock will continue to operate as the Watchdog Timer clock. IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is low. In the IDLE0 Mode the system oscillator will be inhibited from driving the CPU but some peripheral functions will remain operational such as the Watchdog Timer and TMs. In the IDLE0 Mode, the system oscillator will be stopped. Rev. 1.00 40 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM IDLE1 Mode The IDLE1 Mode is entered when a HALT instruction is executed and when the IDLEN bit in the SMOD register is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational such as the Watchdog Timer and TMs. In the IDLE1 Mode, the system oscillator will continue to run, and this system oscillator may be high speed or low speed system oscillator. In the IDLE1 Mode the Watchdog Timer clock, fSUB, will be on. Control Register A single register, SMOD, is used for overall control of the internal clocks within the device. SMOD Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FSTEN LTO HTO IDLEN HLCLK R/W R/W R/W R/W R/W R R R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7 ~ 5 CKS2 ~ CKS0: The system clock selection bits when HLCLK=0 000: fL (LIRC or LXT) 001: fL (LIRC or LXT) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be the LIRC or LXT, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4FSTEN: Fast Wake-up Control (only for HXT) 0: Disable 1: Enable This is the Fast Wake-up Control bit which determines if the fSUB clock source is initially used after the device wakes up. When the bit is high, the fSUB clock source can be used as a temporary system clock to provide a faster wake up time as the fSUB clock is available. Bit 3LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscillator ready flag which indicates when the low speed system oscillator is stable after power on reset. Bit 2HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This is the high speed system oscillator ready flag which indicates when the high speed system oscillator is stable. This flag is cleared to “0” by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore this flag will always be read as “1” by the application program after device power-on. The flag will be low when in the SLEEP, IDLE0 or SLOW0 Mode, but after power on reset or a wake-up has occurred, the flag will change to a high level after 128 clock cycles if the HXT oscillator is used and after 15~16 clock cycles if the HIRC oscillator is used. Rev. 1.00 41 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 1IDLEN: IDLE Mode Control 0: Disable 1: Enable This is the IDLE Mode Control bit and determines what happens when the HALT instruction is executed. If this bit is high, when a HALT instruction is executed the device will enter the IDLE Mode. In the IDLE1 Mode the CPU will stop running but the system clock will continue to keep the peripheral functions operational, if FSYSON bit is high. If FSYSON bit is low, the CPU and the system clock will all stop in IDLE0 mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0HLCLK: System Clock Selection 0: fH/2 ~ fH/64 or fL 1: fH This bit is used to select if the fH clock or the fH/2 ~ fH/64 or fL clock is used as the system clock. When the bit is high the fH clock will be selected and if low the fH/2 ~ fH/64 or fL clock will be selected. When system clock switches from the fH clock to the fL clock and the fH clock will be automatically switched off to conserve power. CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 FSYSON: fSYS Control IDLE Mode 0: Disable 1: Enable Bit 6~ 3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag Describe elsewhere Bit 1LRF: LVRC register software reset flag Describe elsewhere Bit 0WRF: WDTC register software reset flag Describe elsewhere Fast Wake-up To minimise power consumption the device can enter the SLEEP or IDLE0 Mode, where the system clock source to the device will be stopped. However when the device is woken up again, it can take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. To ensure the device is up and running as fast as possible a Fast Wake-up function is provided, which allows fSUB, to act as a temporary clock to first drive the system until the original system oscillator has stabilised. The temporary clock is sourced by the LIRC or LXT oscillator. As the clock source for the Fast Wake-up function is fSUB, the Fast Wake-up function is only available in the SLEEP and IDLE0 modes. The Fast Wake-up enable/disable function is controlled using the FSTEN bit in the SMOD register. If the HXT oscillator is selected as the NORMAL Mode system clock, and if the Fast Wake-up function is enabled, then it will take one to two tSUB clock cycles for the system to wake-up. The system will then initially run under the fSUB clock source until 128 HXT clock cycles have elapsed, at which point the HTO flag will switch high and the system will switch over to operating from the HXT oscillator. Rev. 1.00 42 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM If the HIRC oscillators or LIRC oscillator is used as the system oscillator then it will take 15~16 clock cycles or 1~2 cycles to wake up the system from the SLEEP or IDLE0 Mode. The Fast Wake-up bit, FSTEN will have no effect in these cases. System Oscillator FSTEN Bit Wake-up Time (SLEEP Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) 0 128 HXT cycles 1~2 HXT cycles 1 1~2 fSUB cycles (System runs with fSUB first for 128 HXT cycles and then switches over to run with the HXT clock) 1~2 HXT cycles HIRC × 15~16 HIRC cycles 1~2 HIRC cycles LIRC × 1~2 LIRC cycles 1~2 LIRC cycles LXT × 128 LXT cycles 1~2 LXT cycles HXT Wake-up Times Operating Mode Switching The device can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the present task in hand. In this way microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the HLCLK bit and CKS2~CKS0 bits in the SMOD register while Mode Switching from the NORMAL/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When a HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and FSYSON in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~fH/64 or fL. If the clock is from the fL, the high speed clock source will stop running to conserve power. When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running, which may affect the operation of other internal functions such as the TMs. The accompanying flowchart shows what happens when the device moves between the various operating modes. NORMAL Mode to SLOW0 Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW0 Mode by setting the HLCLK bit to “0” and setting the CKS2~CKS0 bits to “000” or “001” in the SMOD register.This will then use the low speed system oscillator which will consume less power. Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LIRC or LXT oscillator and therefore requires these oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the SMOD register. Rev. 1.00 43 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM NORMAL Mode to SLOW1 Mode Switching When running in the NORMAL Mode, which uses the high speed system oscillator, and therefore consumes more power, the system clock can switch to run in the SLOW1 Mode by setting the HLCLK bit to “0” and setting the CKS2~CKS0 bits to “010”, “011”, “100”, “101”, “110” or “111” in the SMOD register.This will then use a divided clock of the high speed system oscillator which can reduce the operating current. The SLOW1 Mode is still sourced from the HIRC or HXT oscillator and therefore requires less time for full mode switching. SLOW0 Mode to NORMAL Mode Switching In SLOW0 Mode the system uses LIRC or LXT low speed system oscillator. To switch back to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set to “1”. As a certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO bit is checked. The amount of time required for high speed system oscillator stabilization depends upon which high speed system oscillator type is used. SLOW1 Mode to NORMAL Mode Switching In SLOW1 Mode the system still uses high speed system oscillator. To switch back to the NORMAL Mode, where also the high speed system oscillator is used, the HLCLK bit should be set to “1”. As the two modes both use the high speed system oscillator, therefore requires less time for full mode switching. Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “0” and the WDT on. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock will be stopped and the application program will stop at the “HALT” instruction, but the WDT will remain with the clock source coming from the fSUB clock. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “0”. When this instruction is executed under the conditions described above, the following will occur: • The system clock will be stopped and the application program will stop at the “HALT” instruction, but the Time Base clock fTBC and the fSUB clock will be on. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Rev. 1.00 44 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the “HALT” instruction in the application program with the IDLEN bit in SMOD register equal to “1” and the FSYSON bit in CTRL register equal to “1”. When this instruction is executed under the conditions described above, the following will occur: • The system clock and Time Base clock and fSUB will be on and the application program will stop at the “HALT” instruction. • The Data Memory contents and registers will maintain their present condition. • The WDT will be cleared and resume counting. • The I/O ports will maintain their present conditions. • In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be unbonbed pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. In the IDLE1 Mode the system oscillator is on, if the system oscillator is from the high speed system oscillator, the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows: • An external falling edge on Port A • A system interrupt • A WDT overflow If the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the “HALT” instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Rev. 1.00 45 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the “HALT” instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the “HALT” instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled. Programming Considerations The high speed and low speed oscillators both use the same SST counter. For example, if the system is woken up from the SLEEP Mode and the HIRC oscillators need to start-up from an off state. • If the device is woken up from the SLEEP Mode to NORMAL Mode, and the system clock source is from HXT oscillator and FSTEN is “1”, the system clock can be switched to the LIRC or LXT oscillator after wake up. • There are peripheral functions, such as TMs, for which the fSYS is used. If the system clock source is switched from fH to fL, the clock source to the peripheral functions mentioned above will change accordingly. Watchdog Timer The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The Watchdog Timer clock source is provided by the fSUB clock. The fSUB clock can be sourced from either the LIRC or LXT oscillator selected by a configuration option. The LIRC internal oscillator has an approximate frequency of 32kHz and this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768 kHz crystal. The Watchdog Timer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register, WDTC, controls the required timeout period as well as the enable or reset operation. Rev. 1.00 46 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~ 3 WE4 ~ WE0: WDT function software control 10101/01010: WDT enable Other values: Reset MCU When these bits are changed to any other values by the environmental noise to reset the microcontroller, the reset operation will be activated after 2~3 tSUB clock cycles and the WRF bit in the CTRL register will be set to 1to indicate the reset source. Bit 2~ 0 WS2 ~ WS0: WDT Time-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These three bits determine the division ratio of the Watchdog Timer sourece clock, which in turn determines the timeout period. CTRL Register Bit 7 6 5 4 3 2 Name FSYSON — — — — R/W R/W — — — — POR 0 — — — — Bit 7 FSYSON: fSYS Control IDLE Mode Describe elsewhere Bit 6~ 3 Unimplemented, read as “0” 1 0 LVRF LRF WRF R/W R/W R/W 0 0 0 Bit 2LVRF: LVR function reset flag Describe elsewhere Bit 1LRF: LVRC register software reset flag Describe elsewhere Bit 0WRF: WDTC register software reset flag 0: Not occur 1: Occurred This bit is set to 1 by the WDTC Control register software reset and cleared by the application program. Note that this bit can only be cleared to 0 by the application program. Rev. 1.00 47 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Watchdog Timer Operation The Watchdog Timer operates by providing a device reset when its timer overflows. This means that in the application program and during normal operation the user has to strategically clear the Watchdog Timer before it overflows to prevent the Watchdog Timer from executing a reset. This is done using the clear watchdog instructions. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear WDT instructions will not be executed in the correct manner, in which case the Watchdog Timer will overflow and reset the device. With regard to the Watchdog Timer enable/reset function, there are five bits, WE4~WE0, in the WDTC register to additional enable and reset control of the Watchdog Timer. WE4 ~ WE0 Bits WDT Function 10101B/01010B Enable Any other value Reset MCU Watchdog Timer Enable/Reset Control Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the status bit TO. However, if the system is in the SLEEP or IDLE Mode, when a Watchdog Timer time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the Watchdog Timer. The first is a WDT reset, which means a value other than 01010B and 10101B is written into the WE4~WE0 bit locations, the second is using the Watchdog Timer software clear instructions and the third is via a HALT instruction. There is only one method of using software instruction to clear the Watchdog Timer. That is to use the single “CLR WDT” instruction to clear the WDT. The maximum time-out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 seconds for the 218 division ratio, and a minimum timeout of 7.8ms for the 28 division ration. WDTC Register WE4~WE0 bits Reset MCU CLR “CLR WDT”Instruction LXT LIRC M U X fSUB Configuration option 8-stage Divider fSUB/28 WS2~WS0 (fSUB/28 ~ fSUB/218) WDT Prescaler 8-to-1 MUX WDT Time-out (28/fSUB ~ 218/fSUB) Watchdog Timer Rev. 1.00 48 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are several ways in which a microcontroller reset can occur, through events occurring both internally and externally: Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Note: tRSTD is power-on delay, typical time=50ms Power-On Reset Timing Chart Low Voltage Reset – LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is always enabled selected by the configuration option. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally and the LVRF bit in the CTRL register will also be set to1. For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~ VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR can be selected by the LVS7~LVS0 bits in the LVRC register. If the LVS7~LVS0 bits are changed to some certain values by the environmental noise, the LVR will reset the device after 2~3 LIRC/LXT clock cycles. When this happens, the LRF bit in the CTRL register will be set to 1. After power on the register will have the value of 01010101B. Note that the LVR function will be automatically disabled when the device enters the power down mode. Note:tRSTD is power-on delay, typical time=50ms Low Voltage Reset Timing Chart Rev. 1.00 49 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM • LVRC Register Bit 7 6 5 4 3 2 1 0 Name LVS7 LVS6 LVS5 LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R R R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7 ~ 0 LVS7 ~ LVS0: LVR Voltage Select control 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: MCU reset – register is reset to POR value When an actual low voltage condition occurs, as specified by one of the four defined LVR voltage values above, an MCU reset will be generated. The reset operation will be activated after 2~3 LIRC/LXT clock cycles. In this situation this register contents will remain the same after such a reset occurs. • CTRL Register Bit 7 6 5 4 3 2 1 0 Name FSYSON — — — — LVRF LRF WRF R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 FSYSON: fSYS Control IDLE Mode Describe elsewhere Bit 6~ 3 Unimplemented, read as “0” Bit 2LVRF: LVR function reset flag 0: Not occur 1: Occurred This bit is set to 1 when a specific Low Voltage Reset situation condition occurs. This bit can only be cleared to zero by the application program. Bit 1LRF: LVRC register software reset flag 0: Not occur 1: Occurred This bit is set to 1 if the LVRC register contains any non defined LVR voltage register values. This in effect acts like a software reset function. This bit can only be cleared to zero by the application program. Bit 0WRF: WDTC register software reset flag Describe elsewhere Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal operation is the same as an LVR reset except that the Watchdog time-out flag TO will be set to “1”. Note: tRSTD is power-on delay, typical time=16.7ms WDT Time-out Reset during Normal Operation Timing Chart Rev. 1.00 50 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Watchdog Time-out Reset during SLEEP or IDLE Mode The Watchdog time-out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to “0” and the TO flag will be set to “1”. Refer to the A.C. Characteristics for tSST details. Note: The tSST is 15~16 clock cycles if the system clock source is provided by the HIRC. The tSST is 128 clock cycles for HXT/LXT. The tSST is 1~2 clock cycles for the LIRC. WDT Time-out Reset during SLEEP or IDLE Timing Chart Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the SLEEP or IDLE Mode function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 0 Power-on reset u u LVR reset during NORMAL or SLOW Mode operation 1 u WDT time-out reset during NORMAL or SLOW Mode operation 1 1 WDT time-out reset during IDLE or SLEEP Mode operation Note: “u” stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer Modules Timer Modules will be turned off Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. Note that where more than one package type exists the table will reflect the situation for the larger package type. Rev. 1.00 51 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Register Reset (Power On) WDT Time-out (Normal Operation) LVR Reset WDT Time-out (HALT) IAR0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu IAR1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu IAR2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2L xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2H xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ---x xxxx ---u uuuu ---u uuuu ---u uuuu STATUS xx00 xxxx uu1u uuuu uuuu uuuu u u 11 u u u u SMOD 0 0 0 0 0 0 11 0 0 0 0 0 0 11 0 0 0 0 0 0 11 uuuu uuuu INTEG0 0000 0000 0000 0000 0000 0000 uuuu uuuu INTEG1 ---- 0000 ---- 0000 ---- 0000 ---- uuuu WDTC 0 1 0 1 0 0 11 0 1 0 1 0 0 11 0 1 0 1 0 0 11 uuuu uuuu TBC 0 0 11 0 111 0 0 11 0 111 0 0 11 0 111 uuuu uuuu INTC0 -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI0 --00 --00 --00 --00 --00 --00 --uu --uu MFI1 0-00 --00 0-00 --00 0-00 --00 u-uu --uu MFI2 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU 0000 0000 0000 0000 0000 0000 uuuu uuuu PAPU 0000 0000 0000 0000 0000 0000 uuuu uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU 0000 0000 0000 0000 0000 0000 uuuu uuu0 PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU 0000 0000 0000 000 0000 0000 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU --00 0000 --00 0000 --00 0000 --uu uuuu PD - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu PDC - - 11 1111 - - 11 1111 - - 11 1111 --uu uuuu IOHR0 0000 0000 0000 0000 0000 0000 uuuu uuuu IOHR1 0000 0000 0000 0000 0000 0000 uuuu uuuu IOHR2 0000 0000 0000 0000 0000 0000 uuuu uuuu IOHR3 0000 0000 0000 0000 0000 0000 uuuu uuuu CTRL 0--- -000 0--- -000 0--- -000 u--- -uuu LVRC 0101 0101 0101 0101 uuuu uuuu uuuu uuuu ADRL(ADRFS=0) xxxx ---- xxxx ---- xxxx ---- uuuu ---- ADRL(ADRFS=1) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRH(ADRFS=0) xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu Rev. 1.00 52 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Register Reset (Power On) WDT Time-out (Normal Operation) LVR Reset WDT Time-out (HALT) ADRH(ADRFS=1) ---- xxxx ---- xxxx ---- xxxx ---- uuuu ADCR0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 0 11 0 - 0 0 0 uuuu -uuu ADCR1 00--0000 00-- 0000 00-- 0000 uu-- uuuu ACERL 1111 1111 1111 1111 1111 1111 uuuu uuuu TMPC0 -0-0 -0-0 -0-0 -0-0 -0-0 -0-0 -u-u -u-u EEA --00 0000 --00 0000 --00 0000 --uu uuuu EED 0000 0000 0000 0000 0000 0000 uuuu uuuu EEC ---- 0000 ---- 0000 ---- 0000 ---- uuuu CTMC0 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMDH ---- --00 ---- --00 ---- --00 ---- --uu CTMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu CTMAH ---- --00 ---- --00 ---- --00 ---- --uu STMC0 0000 0--- 0000 0--- 0000 0--- uuuu u--- STMC1 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDL 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDH 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAL 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAH 0000 0000 0000 0000 0000 0000 uuuu uuuu STMRP 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0C0 0000 0--- 0000 0--- 0000 0--- uuuu u--- PTM0C1 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0DL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0DH ---- --00 ---- --00 ---- --00 ---- --uu PTM0AL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0AH ---- --00 ---- --00 ---- --00 ---- --uu PTM0RPL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0RPH ---- --00 ---- --00 ---- --00 ---- --uu PTM1C0 0000 0--- 0000 0--- 0000 0--- uuuu u--- PTM1C1 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DH ---- --00 ---- --00 ---- --00 ---- --uu PTM1AL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1AH ---- --00 ---- --00 ---- --00 ---- --uu PTM1RPL 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1RPH ---- --00 ---- --00 ---- --00 ---- --uu SIMTOC 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 111 - 0 0 0 0 111 - 0 0 0 0 111 - 0 0 0 0 uuu- uuuu SIMC1 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA 0000 000- 0000 000- 0000 000- uuuu uuuu SIMC2 0000 0000 0000 0000 0000 0000 uuuu uuuu LVDC --00 -000 --00 -000 --00 -000 --uu -uuu USR 0 0 0 0 1 0 11 0 0 0 0 1 0 11 0 0 0 0 1 0 11 uuuu uuuu UCR1 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 0000 0000 0000 0000 0000 0000 uuuu uuuu BRG xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu Rev. 1.00 53 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Reset (Power On) WDT Time-out (Normal Operation) LVR Reset WDT Time-out (HALT) TXR/RXR xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SLCDC0 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC1 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC2 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC3 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC4 0000 0000 0000 0000 0000 0000 uuuu uuuu Register Note: "-" not implement "u" stands for "unchanged" "x" stands for "unknown" Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device provides bidirectional input/output lines labeled with port names PA~PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction “MOV A, [m]”, where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Bit Register Name 7 6 5 4 3 2 1 0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PAC PAC7 PAC6 PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PBPU PBPU7 PBPU6 PBPU5 PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PB PB7 PB 6 PB 5 PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC6 PBC5 PBC4 PBC3 PBC2 PBC1 PBC0 PCPU PCPU7 PCPU6 PCPU5 PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC6 PCC5 PCC4 PCC3 PCC2 PCC1 PCC0 PDPU0 PDPU — — PDPU5 PDPU4 PDPU3 PDPU2 PDPU1 PD — — PD5 PD4 PD3 PD2 PD1 PD0 PDC — — PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 I/O Control Register List PAPUn, PBPUn, PCPUn, PDPUn: I/O Port Pull-High Control 0: Disable 1: Enable PAWUn: I/O Port A bit 7 ~ bit 0 Wake Up Control 0: Disable 1: Enable PACn, PBCn, PCCn, PDCn: I/O Port Input/Output Control 0: Output 1: Input Rev. 1.00 54 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selected using registers PAPU~PDPU, and are implemented using weak PMOS transistors. Port A Wake-up The HALT instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. This function is especially suitable for applications that can be woken up via external switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. I/O Port Control Registers Each I/O port has its own control register known as PAC~PDC, to control the input/output configuration. With this control register, each CMOS output or input can be reconfigured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a “1”. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a “0”, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control. I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. Rev. 1.00 55 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Generic Input/Output Structure A/D Input/Output Structure Rev. 1.00 56 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM I/O Port source current selection The PA~PD input/output ports have programmable source current functions. Four levels of source current can be selected by the registers. IOHR0 Register Bit 7 6 5 4 3 2 1 0 Name IOHS31 IOHS30 IOHS21 IOHS20 IOHS11 IOHS10 IOHS01 IOHS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6IOHS31~IOHS30: PA3 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 5~4IOHS21~IOHS20: PA2 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 3~2IOHS11~IOHS10: PA1 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 1~0IOHS01~IOHS00: PA0 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output IOHR1 Register Bit 7 6 5 4 3 2 1 0 Name IOHS71 IOHS70 IOHS61 IOHS60 IOHS51 IOHS50 IOHS41 IOHS40 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6IOHS71~IOHS70: PA7 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 5~4IOHS61~IOHS60: PA6 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 3~2IOHS51~IOHS50: PA5 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Rev. 1.00 57 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 1~0IOHS41~IOHS40: PA4 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output IOHR2 Register Bit 7 6 5 4 3 2 1 0 Name IOHSB1 IOHSB0 IOHSA1 IOHSA0 IOHS91 IOHS90 IOHS81 IOHS80 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6IOHSB1~IOHSB0: PC4~PC7 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 5~4IOHSA1~IOHSA0: PC0~PC3 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 3~2IOHS91~IOHS90: PB4~PB7 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 1~0IOHS81~IOHS80: PB0~PB3 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output IOHR3 Register Bit 7 6 5 4 3 2 1 0 Name — — — — IOHSD1 IOHSD0 IOHSC1 IOHSC0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as “0” Bit 3~2IOHSD1~IOHSD0: PD4~PD5 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Bit 1~0IOHSC1~IOHSC0: PD0~PD3 source current output selection bit 00: Full source current output 01: 10/22 full source current output 10: 7/22 full source current output 11: 4/22 full source current output Rev. 1.00 58 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Programming Considerations Within the user program, one of the first things to consider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers, PAC~PDC, are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers, PA~PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the “SET [m].i” and “CLR [m].i” instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer Modules – TM One of the most fundamental functions in any microcontroller device is the ability to control and measure time. To implement time related functions the device includes several Timer Modules, abbreviated to the name TM. The TMs are multi-purpose timing units and serve to provide operations such as Timer/Counter, Input Capture, Compare Match Output and Single Pulse Output as well as being the functional unit for the generation of PWM signals. Each of the TMs has two individual interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the different TM types are described here with more detailed information provided in the individual Compact, Standard and Periodic TM sections. Introduction The device contains a 10-bit Compact TM-CTM, a 16-bit Standard TM-STM and two10-bit Periodic TMs- PTM0 and PTM1. Although similar in nature, the different TM types vary in their feature complexity. The common features to the Compact, Standard and Periodic TMs will be described in this section and the detailed operation will be described in corresponding sections. The main features and differences between the three types of TMs are summarised in the accompanying table. CTM STM Timer/Counter Function √ √ PTM √ I/P Capture — √ √ Compare Match Output √ √ √ PWM Channels 1 1 1 Single Pulse Output PWM Alignment PWM Adjustment Period & Duty — 1 1 Edge Edge Edge Duty or Period Duty or Period Duty or Period TM Function Summary Rev. 1.00 59 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM TM Operation The three different types of TMs offer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running counter whose value is then compared with the value of pre-programmed internal comparators. When the free running counter has the same value as the pre-programmed comparator, known as a compare match situation, a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the TM control registers. The clock source can be a ratio of either the system clock fSYS or the internal high clock fH, the fTBC clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source or for event counting. TM Interrupts The Compact, Standard and Periodic type TMs each has two internal interrupts, the internal comparator A or comparator P, which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one TM input pin, with the label xTCKn. The TM input pin, is essentially a clock source for the TM and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. This external TM input pin is shared with other functions but will be connected to the internal TM if selected using the xTnCK2~xTnCK0 bits. The TM input pin can be chosen to have either a rising or falling active edge. The TMs each have one output pin. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn output pin is also the pin where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other function, the TM output function must first be setup using registers. A single bit in one of the registers determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of output pins for each TM type is different, the details are provided in the accompanying table. TM Type Pin Input Output CTP CTM CTM CTCK STM STM STCK STP PTM0 PTCK0 PTP0 PTM1 PTCK1 PTP1 PTM TM Input/Output pin Rev. 1.00 60 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM TM Input/Output Pin Control Register Selecting to have a TM input/output or whether to retain its other shared function is implemented using one register, with a single bit in the register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. TMPC0 Register Bit 7 6 5 4 3 2 1 0 Name — PTP1CP0 — PTP0CP0 — STPCP0 — CTPCP0 R/W — R/W — R/W — R/W — R/W POR — 0 — 0 — 0 — 0 Bit 7 Unimplemented, read as Bit 6PTP1CP0: PTP1 pin Control 0: Normal I/O 1: PTP1 function Bit 5 Unimplemented, read as Bit 4PTP0CP0: PTP0 pin Control 0: Normal I/O 1: PTP0 function Bit 3 Unimplemented, read as Bit 2STPCP0: STP pin Control 0: Normal I/O 1: STP function Bit 1 Unimplemented, read as Bit 0CTPCP0: CTP pin Control 0: Normal I/O 1: CTP function PB2 data bit CTM Mode Controller (CTM) 1 CTP CTP 0 CTPCP0 CTM Function Pin Control Block Diagram Rev. 1.00 61 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM PB7 data bit 1 STP 0 STPCP0 STPCP0 1 0 STM Mode Controller (STM) 0 STP STP STM Function Pin Control Block Diagram PB0 data bit 1 PTP0 0 PTP0CP0 PTP0CP0 1 0 PTM Mode Controller (PTM0) 0 PTP0 PTP0 PA5 data bit 1 PTP1 0 PTP1CP0 PTP1CP0 1 0 PTM Mode Controller (PTM1) 0 PTP1 PTP1 PTM0, PTM1 Function Pin Control Block Diagram Rev. 1.00 62 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Programming Considerations The TM Counter Registers and the Capture/Compare CCRA or CCRP register, being either 10-bit or 16-bit, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buffer, reading or writing to these register pairs must be carried out in a specific way. The important point to note is that data transfer to and from the 8-bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing this register is carried out in a specific way described above, it is recommended to use the “MOV” instruction to access the CCRA or CCRP low byte register, named xTMnAL or PTMnRPL, in the following access procedures. Accessing the CCRA or CCRP low byte register without following these access procedures will result in unpredictable values. TM Counter Register (Read only) xTMnDL xTMnDH 8-bit Buffer xTMnAL xTMnAH xTM CCRA Register (Read/Write) PTMnRPL PTMnRPH PTMn CCRP Register (Read/Write) Data Bus The following steps show the read and write procedures: • Writing Data to CCRA or CCRP ♦♦ Step 1. Write data to Low Byte xTMnAL or PTMnRPL ––Note that here data is only written to the 8-bit buffer. ♦♦ Step 2. Write data to High Byte xTMnAH or PTMnRPH ––Here data is written directly to the high byte registers and simultaneously data is latched from the 8-bit buffer to the Low Byte registers. • Reading Data from the Counter Registers and CCRA or CCRP Rev. 1.00 ♦♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH ––Here data is read directly from the High Byte registers and simultaneously data is latched from the Low Byte register into the 8-bit buffer. ♦♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL ––This step reads data from the 8-bit buffer. 63 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Compact Type TM – CTM Although the simplest form of the three TM types, the Compact TM type still contains three operating modes, which are Compare Match Output, Timer/Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive one external output pin. Compact Type TM Block Diagram Compact TM Operation At its core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits. The only way of changing the value of the 10-bit counter using the application program, is to clear the counter by changing the CTON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control two output pins. All operating setup conditions are selected using relevant internal registers. Rev. 1.00 64 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Compact Type TM Register Description Overall operation of each Compact TM is controlled using several registers. A read only register pair exists to store the internal counter 10-bit value, while a read/write register pair exists to store the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the three CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 CTMC0 CTPAU CTCK2 CTCK1 CTCK0 CTON CTRP2 CTRP1 CTRP0 CTMC1 CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR CTMDL D7 D6 D5 D4 D3 D2 D1 D0 CTMDH — — — — — — D9 D8 CTMAL D7 D6 D5 D4 D3 D2 D1 D0 CTMAH — — — — — — D9 D8 Compact TM Register List CTMC0 Register Bit 7 6 5 4 3 2 1 0 Name CTPAU CTCK2 CTCK1 CTCK0 CTON CTRP2 CTRP1 CTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7CTPAU: CTM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6 ~ 4 CTCK2 ~ CTCK0: Select CTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: fTBC 110: CTCK rising edge clock 111: CTCK falling edge clock These three bits are used to select the clock source for the CTM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3CTON: CTM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. Rev. 1.00 65 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the CTOC bit, when the CTON bit changes from low to high. Bit 2 ~ 0CTRP2~CTRP0: CTM CCRP 3-bit register, compared with the CTM Counter bit9~bit7 Comparator P Match Period 000: 1024 CTM clocks 001: 128 CTM clocks 010: 256 CTM clocks 011: 384 CTM clocks 100: 512 CTM clocks 101: 640 CTM clocks 110: 768 CTM clocks 111: 896 CTM clocks These three bits are used to setup the value on the internal CCRP 3-bit register, which are then compared with the internal counter's highest three bits. The result of this comparison can be selected to clear the internal counter if the CTCCLR bit is set to zero. Setting the CTCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing all three bits to zero is in effect allowing the counter to overflow at its maximum value. CTMC1 Register Bit 7 6 5 4 3 2 1 0 Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 6CTM1~CTM0: Select CTM Operating Mode 00: Compare Match Output Mode 01: Compare Match Output Mode 10: PWM Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the bits. In the Timer/ Counter Mode, the TM output pin control must be disabled. Bit 5 ~ 4CTIO1~CTIO0: Select CTM output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. Rev. 1.00 66 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM In the Compare Match Output Mode, the CTIO1~CTIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the CTIO1~CTIO0 bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the CTOC bit. Note that the output level requested by the CTIO1~CTIO0 bits must be different from the initial value setup using the CTOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the CTON bit from low to high. In the PWM Mode, the CTIO1 and CTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the CTIO1 and CTIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the CTIO1 and CTIO0 bits are changed when the TM is running. Bit 3CTOC: CTM Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2CTPOL: CTM Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TM output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1CTDPX: CTM PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0CTCCLR: Select CTM Counter clear condition 0: CTM Comparatror P match 1: CTM Comparatror A match This bit is used to select the method which clears the counter. Remember that the Compact TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the CTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTCCLR bit is not used in the PWM Mode. Rev. 1.00 67 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM CTMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0D7~D0: CTM Counter Low Byte Register bit 7 ~ bit 0 CTM 10-bit Counter bit 7 ~ bit 0 CTMDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as “0” Bit 1 ~ 0D9~D8: CTM Counter High Byte Register bit 1 ~ bit 0 CTM 10-bit Counter bit 9 ~ bit 8 CTMAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0D7~D0: CTM CCRA Low Byte Register bit 7 ~ bit 0 CTM 10-bit CCRA bit 7 ~ bit 0 CTMAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7 ~ 2 Unimplemented, read as “0” Bit 1 ~ 0D9~D8: CTM CCRA High Byte Register bit 1 ~ bit 0 CTM 10-bit CCRA bit 9 ~ bit 8 Rev. 1.00 68 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or Timer/Counter Mode. The operating mode is selected using the CTM1 and CTM0 bits in the CTMC1 register. Compare Match Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register, should be set to 00 or 01 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the CTCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both CTMAF and CTMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the CTCCLR bit in the CTMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the CTMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTCCLR is high no CTMPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a CTMAF interrupt request flag is generated after a compare match occurs from Comparator A. The CTMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the CTIO1 and CTIO0 bits in the CTMC1 register. The TM output pin can be selected using the CTIO1 and CTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the CTON bit changes from low to high, is setup using the CTOC bit. Note that if the CTIO1 and CTIO0 bits are zero then no pin change will take place. Rev. 1.00 69 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value 0x3FF CTCCLR = 0; CTM[1:0] = 00 / 01 Counter overflow CCRP > 0 Counter cleared by CCRP value CCRP = 0 Counter Reset Resume CCRP > 0 CCRP Pause CCRA Stop Time CTON CTPAU CTPOL CCRP Int. Flag CTMPF CCRA Int. Flag CTMAF CTM O/P Pin Output Pin set to Initial Level Low if CTOC = 0 Output Toggle with CTMAF flag Now CTIO[1:0] = 10 Active High Output Select Output not affected by CTMAF flag. Remains High until reset by CTON bit Output inverts when CTPOL is high Output Pin Reset to initial value un-defined Here CTIO[1:0] = 11 Toggle Output Select Compare Match Output Mode – CTCCLR = 0 Note: 1. With CTCCLR = 0, a Comparator P match will clear the counter 2. The TM output pin controlled only by the CTMAF flag 3. The output pin reset to initial state by a CTON bit rising edge Rev. 1.00 70 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM CTCCLR = 1; CTM[1:0] = 00 / 01 Counter Value CCRA > 0 Counter cleared by CCRA value 0x3FF Resume CCRA Pause CCRP CCRA = 0 Counter overflow CCRA = 0 Stop Counter Reset Time CTON CTPAU CTPOL No CTMAF flag generated on CCRA overflow CCRA Int. Flag CTMAF CCRP Int. Flag CTMPF CTM O/P Pin Output does not change CTMPF not generated Output not affected by Output Pin set to Initial Level Low if CTOC = 0 Output Toggle with CTMAF flag Output inverts when CTPOL is high Output Pin Reset to initial value CTMAF flag. Remains High Now CTIO[1:0] = 10 Active High Output Select until reset by CTON bit un-defined Here CTIO[1:0] = 11 Toggle Output Select Compare Match Output Mode – CTCCLR = 1 Note: 1. With CTCCLR = 1, a Comparator A match will clear the counter 2. The TM output pin controlled only by the CTMAF flag 3. The output pin reset to initial state by a CTON rising edge 4. The CTMPF flags is not generated when CTCCLR = 1 Rev. 1.00 71 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTM1 and CTM0 in the CTMC1 register should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the CTCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The CTOC bit In the CTMC1 register is used to select the required polarity of the PWM waveform while the two CTIO1 and CTIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The CTPOL bit is used to reverse the polarity of the PWM output waveform. • CTM, PWM Mode, Edge-aligned Mode, CTDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Period 128 256 384 512 640 768 896 1024 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 100b, CCRA =128, The CTM PWM output frequency = (fSYS/4) /512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • CTM, PWM Mode, Edge-aligned Mode, CTDPX=1 CCRP 001b 010b 011b 100b Period Duty 101b 110b 111b 000b 768 896 1024 CCRA 128 256 384 512 640 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the CCRP register value. Rev. 1.00 72 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value CTDPX=0;CTM[1:0]=10 Counter Cleared by CCRP Counter reset when CTON returns high CCRP Counter stop if CTON bit low Pause Resume CCRA Time CTON CTPAU CTPOL CCRA Int. Flag CTMAF CCRP Int. Flag CTMPF CTM O/P Pin (CTOC=1) CTM O/P Pin (CTOC=0) PWM Duty Cycle set by CCRA un-defined PWM resumes operation Output Inverts When CTPOL = 1 PWM Period set by CCRP PWM Mode – CTDPX = 0 Note: 1. Here CTDPX = 0 - Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when CTIO[1:0] = 00 or 01 4. The CTCCLR bit has no influence on PWM operation Rev. 1.00 73 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value CTDPX=1;CTM[1:0]=10 Counter Cleared by CCRA Counter reset when CTON returns high CCRA Counter stop if CTON bit low Pause Resume CCRP Time CTON CTPAU CTPOL CCRP Int. Flag CTMPF CCRA Int. Flag CTMAF CTM O/P Pin (CTOC=1) CTM O/P Pin (CTOC=0) PWM Duty Cycle set by CCRP un-defined PWM resumes operation Output Inverts When CTPOL = 1 PWM Period set by CCRA PWM Mode – CTDPX = 1 Note: 1. Here CTDPX = 1 - Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTIO[1:0] = 00 or 01 4. The CTCCLR bit has no influence on PWM operation Rev. 1.00 74 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Standard Type TM – STM The Standard Type TM contains five operating modes, which are Compare Match Output, Timer/ Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can drive one external output pin. Standard Type TM Block Diagram Standard TM Operation At its core is a 16-bit count-up counter which is driven by a user selectable internal clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is 8-bit wide whose value is compared with the highest 8 bits in the counter while the CCRA is 16 bits and therefore compares with all counter bits. The only way of changing the value of the 16-bit counter using the application program, is to clear the counter by changing the STON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Rev. 1.00 75 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Standard Type TM Register Description Overall operation of the Standard TM is controlled using series of registers. A read only register pair exists to store the internal counter 16-bit value, while a read/write register pair exists to store the internal 16-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as eight CCRP bits. Bit Register Name 7 6 5 4 3 2 1 0 STMC0 STPAU STCK2 STCK1 STCK0 STON — — — STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D7 D6 D5 D4 D3 D2 D1 D0 STMDH D15 D14 D13 D12 D11 D10 D9 D8 STMAL D7 D6 D5 D4 D3 D2 D1 D0 STMAH D15 D14 D13 D12 D11 D10 D9 D8 STMRP D7 D6 D5 D4 D3 D2 D1 D0 2 1 0 16-bit Standard TM Register List STMC0 Register Bit 7 6 5 4 3 Name STPAU STCK2 STCK1 STCK0 STON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7STPAU: STM Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6 ~ 4 STCK2 ~ STCK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: fTBC 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. Bit 3STON: STM Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. Rev. 1.00 76 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Bit 2 ~ 0 Unimplemented, read as “0” STMC1 Register Bit 7 6 5 4 3 2 1 0 Name STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 6STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the bits. In the Timer/ Counter Mode, the TM output pin control must be disabled. Bit 5 ~ 4STIO1~STIO0: Select STM output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of STP 01: Input capture at falling edge of STP 10: Input capture at falling/rising edge of STP 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the STIO1~STIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the STIO1~STIO0 bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the STOC bit. Note that the output level requested by the STIO1~STIO0 bits must be different from the initial value setup using the STOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the STON bit from low to high. Rev. 1.00 77 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM In the PWM Mode, the STIO1 and STIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to change the values of the STIO1 and STIO0 bits only after the TM has been switched off. Unpredictable PWM outputs will occur if the STIO1 and STIO0 bits are changed when the TM is running. Bit 3STOC: STM Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2STPOL: STM Output polarity Control 0: Non-invert 1: Invert This bit controls the polarity of the TM output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the Timer/Counter Mode. Bit 1STDPX: STM PWM period/duty Control 0: CCRP - period; CCRA - duty 1: CCRP - duty; CCRA - period This bit, determines which of the CCRA and CCRP registers are used for period and duty control of the PWM waveform. Bit 0STCCLR: Select STM Counter clear condition 0: TM Comparator P match 1: TM Comparator A match This bit is used to select the method which clears the counter. Remember that the Standard TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 1.00 78 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM STMDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0D7~D0: STM Counter Low Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 7 ~ bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 2 1 0 Bit 7 ~ 0D15~D8: STM Counter High Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 15 ~ bit 8 STMAL Register Bit 7 6 5 4 3 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0D7~D0: STM CCRA Low Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 7 ~ bit 0 STMAH Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0D15~D8: STM CCRA High Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 15 ~ bit 8 STMRP Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 0STMRP: STM CCRP High Byte Register bit 7 ~ bit 0 STM CCRP 8-bit register, compared with the STM Counter bit 15 ~ bit 8. Comparator P Match Period 0: 65536 STM clocks 1~255: 256 × (1~255) STM clocks These eight bits are used to setup the value on the internal CCRP 8-bit register, which are then compared with the internal counter's highest eight bits. The result of this comparison can be selected to clear the internal counter if the STCCLR bit is set to zero. Setting the STCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter. As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing all eight bits to zero is in effect allowing the counter to overflow at its maximum value. Rev. 1.00 79 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Standard Type TM Operating Modes The Standard Type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the STCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both STMAF and STMPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the STMAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A. The STMPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register. The TM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the STON bit changes from low to high, is setup using the STOC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place. Rev. 1.00 80 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value 0xFFFF STCCLR = 0; STM[1:0] = 00 Counter overflow CCRP > 0 Counter cleared by CCRP value CCRP = 0 Counter Reset Resume CCRP > 0 CCRP Pause CCRA Stop Time STON STPAU STPOL CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin Output Pin set to Initial Level Low if STOC = 0 Output Toggle with STMAF flag Now STIO[1:0] = 10 Active High Output Select Output not affected by STMAF flag. Remains High until reset by STON bit Output inverts when STPOL is high Output Pin Reset to initial value Output controlled by other pin - shared function Here STIO[1:0] = 11 Toggle Output Select Compare Match Output Mode – STCCLR = 0 Note: 1. With STCCLR = 0 a Comparator P match will clear the counter 2. The TM output pin controlled only by the STMAF flag 3. The output pin reset to initial state by a STON bit rising edge Rev. 1.00 81 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM STCCLR = 1; STM[1:0] = 00 Counter Value CCRA > 0 Counter cleared by CCRA value 0xFFFF Resume CCRA Pause CCRP CCRA = 0 Counter overflow CCRA = 0 Stop Counter Reset Time STON STPAU STPOL No STMAF flag generated on CCRA overflow CCRP Int. Flag STMAF CCRA Int. Flag STMPF STM O/P Pin Output does not change STMPF not generated Output not affected by Output Pin set to Initial Level Low if STOC = 0 Output Toggle with STMAF flag STMAF flag. Remains High Now STIO[1:0] = 10 Active High Output Select until reset by STON bit Here STIO[1:0] = 11 Toggle Output Select Output inverts when STPOL is high Output Pin Reset to initial value Output controlled by other pin shared function - Compare Match Output Mode – STCCLR = 1 Note: 1. With STCCLR = 1 a Comparator A match will clear the counter 2. The TM output pin controlled only by the STMAF flag 3. The output pin reset to initial state by a STON rising edge 4. The STMPF flags is not generated when STCCLR = 1 Rev. 1.00 82 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the STCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The STOC bit In the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform. • 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0 CCRP 1~255 0 Period CCRP×256 65536 Duty CCRA If fSYS = 16MHz, TM clock source is fSYS/4, CCRP = 2 and CCRA =128, The STM PWM output frequency = (fSYS/4) /512 = fSYS/2048 = 7.8125 kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. • 16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1 CCRP 1~255 Period Duty 0 CCRA CCRP×256 65536 The PWM output period is determined by the CCRA register value together with the TM clock while the PWM duty cycle is defined by the (CCRP×256) except when the CCRP value is equal to 0. Rev. 1.00 83 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value STDPX=0;STM[1:0]=10 Counter Cleared by CCRP Counter reset when STON returns high CCRP Pause Resume CCRA Counter Stop If STON bit low Time STON STPAU STPOL CCRA Int. Flag STMAF CCRP Int. Flag STMPF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cycle set by CCRA Output controlled by Other pin-shared function PWM resumes operation Output Inverts When STPOL = 1 PWM Period set by CCRP PWM Mode – STDPX=0 Note: 1. Here STDPX = 0 - Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues running even when STIO[1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.00 84 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value STDPX=1;STM[1:0]=10 Counter Cleared by CCRA Counter reset when STON returns high CCRA Pause Resume CCRP Counter Stop If STON bit low Time STON STPAU STPOL CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) PWM Duty Cycle set by CCRP Output controlled by Other pin-shared function PWM resumes operation Output Inverts When STPOL = 1 PWM Period set by CCRA PWM Mode – STDPX=1 Note: 1. Here STDPX = 1 - Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when STIO[1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation Rev. 1.00 85 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Single Pulse Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the STON bit, which can be implemented using the application program. However in the Single Pulse Mode, the STON bit can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the STON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The STON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. Single Pulse Generation Rev. 1.00 86 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value STM [1:0] = 10 ; STIO [1:0] = 11 Counter stopped by CCRA Counter Reset when STON returns high CCRA Pause Counter Stops by software Resume CCRP Time STON Software Trigger Auto. set by STCK pin Cleared by CCRA match STCK pin Software Trigger Software Clear Software Trigger Software Trigger STCK pin Trigger STPAU STPOL No CCRP Interrupts generated CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin (STOC=1) STM O/P Pin (STOC=0) Output Inverts when STPOL = 1 Pulse Width set by CCRA Single Pulse Mode Note: 1. Counter stopped by CCRA match 2. CCRP is not used 3. The pulse is triggered by setting the STON bit high or STCK pin 4. In the Single Pulse Mode, STIO [1:0] must be set to “11” and can not be changed. Rev. 1.00 87 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM However a compare match from Comparator A will also automatically clear the STON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the STON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the STP pin, whose active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register. The counter is started when the STON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STP pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the STP pin the counter will continue to free run until the STON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STP pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STP pin, however it must be noted that the counter will continue to run. As the STP pin is pin shared with other functions, care must be taken if the TM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The STCCLR and STDPX bits are not used in this Mode. Rev. 1.00 88 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value STM [1:0] = 01 Counter cleared by CCRP Counter Counter Reset Stop CCRP YY Pause Resume XX Time STON STPAU Active edge Active edge Active edge STM capture pin STP CCRA Int. Flag STMAF CCRP Int. Flag STMPF CCRA Value STIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode Note: 1. STM[1:0] = 01 and active edge set by the STIO[1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. The STCCLR bit is not used 4. No output function - STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 89 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Periodic Type TM – PTM0, PTM1 The PTM contains five operating modes, which are Compare Match Output, Timer/Event Counter, Capture Input, Single Pulse Output and PWM Output modes. The P-type TM can also be controlled with an external input pin and can drive one output pins. Periodic TM Operation There are two P-type TMs, both are 10-bit wide. At the core is a 10 count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P. These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 10-bits wide. The only way of changing the value of the 10 counter using the application program, is to clear the counter by changing the PTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur, a TM interrupt signal will also usually be generated. The Periodic Type TM can operate in a number of different operational modes, can be driven by different clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers. Periodic Type TM Block Diagram (n=0, 1) Rev. 1.00 90 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM PTM register description Overall operation of the P-type TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA/CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Bit Register Name 7 6 5 4 3 2 1 0 PTMnC0 PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTMnDL D7 D6 D5 D4 D3 D2 D1 D0 PTMnDH — — — — — — D9 D8 PTMnAL D7 D6 D5 D4 D3 D2 D1 D0 PTnPOL PTnCKS PTnCCLR PTMnAH — — — — — — D9 D8 PTMnRPL D7 D6 D5 D4 D3 D2 D1 D0 PTMnRPH — — — — — — D9 D8 10-bit Periodic TM Register List (n=0, 1) PTMnC0 Register Bit 7 6 5 4 3 2 1 0 Name PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7PTnPAU: PTMn Counter Pause Control 0: Run 1: Pause The counter can be paused by setting this bit high. Clearing the bit to zero restores normal counter operation. When in a Pause condition the TM will remain powered up and continue to consume power. The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again. Bit 6 ~4 Rev. 1.00 PTnCK2 ~ PTnCK0: Select PTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fTBC 101: fTBC 110: PTCKn rising edge clock 111: PTCKn falling edge clock These three bits are used to select the clock source for the TM. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fTBC are other internal clocks, the details of which can be found in the oscillator section. 91 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 3PTnON: PTMn Counter On/Off Control 0: Off 1: On This bit controls the overall on/off function of the TM. Setting the bit high enables the counter to run, clearing the bit disables the TM. Clearing this bit to zero will stop the counter from counting and turn off the TM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low, the internal counter will retain its residual value until the bit returns high again. If the TM is in the Compare Match Output Mode then the TM output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Unimplemented, read as“0” PTMnC1 Register Bit 7 6 5 4 3 2 1 0 Name PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTnCKS PTnCCLR Bit 7~6PTnM1~PTnM0: Select PTMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: Timer/Counter Mode These bits setup the required operating mode for the TM. To ensure reliable operation the TM should be switched off before any changes are made to the PTnM1 and PTnM0 bits. In the Timer/Counter Mode, the TM output pin control must be disabled. Bit 5~4PTnIO1~PTnIO0: Select PTPn output function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: Toggle output PWM Mode/Single Pulse Output Mode 00: Force inactive state 01: Force active state 10: PWM output 11: Single pulse output Capture Input Mode 00: Input capture at rising edge of PTPn or PTCKn 01: Input capture at falling edge of PTPn or PTCKn 10: Input capture at falling/rising edge of PTPn or PTCKn 11: Input capture disabled Timer/counter Mode Unused These two bits are used to determine how the TM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the TM is running. In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the TM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the TM output pin should be setup using the PTnOC bit in the PTMnC1 register. Note that the output level requested by the PTnIO1 and PTnIO0 bits must be Rev. 1.00 92 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM different from the initial value setup using the PTnOC bit otherwise no change will occur on the TM output pin when a compare match occurs. After the TM output pin changes state it can be reset to its initial level by changing the level of the PTnON bit from low to high. Bit 3PTnOC: PTPn Output control bit Compare Match Output Mode 0: Initial low 1: Initial high PWM Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the TM output pin. Its operation depends upon whether TM is being used in the Compare Match Output Mode or in the PWM Mode/ Single Pulse Output Mode. It has no effect if the TM is in the Timer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the TM output pin before a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2PTnPOL: PTPn Output polarity control 0: Non-invert 1: Invert This bit controls the polarity of the PTPn output pin. When the bit is set high the TM output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in theTimer/Counter Mode. Bit 1PTnCKS: Input Capture trigger source selection 0: External Clock source of Capture Input Mode comes from PTPn 1: External Clock source of Capture Input Mode comes from PTCKn Bit 0PTnCCLR: Select PTMn Counter clear condition 0: PTMn Comparator P match 1: PTMn Comparator A match This bit is used to select the method which clears the counter. Remember that the P-type TM contains two comparators, Comparator A and Comparator P, either of which can be selected to clear the internal counter. With the PTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low, the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow. A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not used in the PWM, Single Pulse or Input Capture Mode. Rev. 1.00 93 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM PTMnDL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn Counter Low Byte Register Bit 7~Bit 0 PTMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R R POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as“0” Bit 1~0D9~D8: PTMn Counter High Byte Register Bit 1~Bit 0 PTMn 10-bit Counter bit 9 ~ bit 8 PTMnAL Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn CCRA Low Byte Register bit 7~bit 0 PTMn 10-bit CCRA bit 7~bit 0 PTMnAH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as“0” Bit 1~0D9~D8: PTMn CCRA High Byte Register Bit 1~Bit 0 PTMn 10-bit CCRA bit 9 ~ bit 8 PTMnRPL Register (n=0, 1) Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0D7~D0: PTMn CCRP Register bit 7 ~ bit 0 PTMn 10-bit CCRP bit 7 ~ bit 0 Rev. 1.00 94 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM PTMnRPH Register Bit 7 6 5 4 3 2 1 0 Name — — — — — — D9 D8 R/W — — — — — — R/W R/W POR — — — — — — 0 0 Bit 7~2 Unimplemented, read as“0” Bit 1~0D9~D8: PTMn CCRP Register bit 1 ~ bit 0 PTMn 10-bit CCRP bit 9 ~ bit 8 Periodic Type TM Operating Modes The P-type TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or Timer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register. Compare Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register, should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow, a compare match from Comparator A and a compare match from Comparator P. When the PTnCCLR bit is low, there are two ways in which the counter can be cleared. One is when a compare match from Comparator P, the other is when the CCRP bits are all zero which allows the counter to overflow. Here both PTMnAF and PTMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However, here only the PTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to “0”. As the name of the mode suggests, after a comparison is made, the TM output pin, will change state. The TM output pin condition however only changes state when a PTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request flag, generated from a compare match occurs from Comparator P, will have no effect on the TM output pin. The way in which the TM output pin changes state are determined by the condition of the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The TM output pin can be selected using the PTnIO1 and PTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the TM output pin, which is setup after the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1 and PTnIO0 bits are zero then no pin change will take place. Rev. 1.00 95 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value Counter overflow CCRP=0 0x3FF PTnCCLR = 0; PTnM [1:0] = 00 CCRP > 0 Counter cleared by CCRP value CCRP > 0 Counter Restart Resume CCRP Pause CCRA Stop Time PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTM O/P Pin Output pin set to initial Level Low if PTnOC=0 Output not affected by PTMnAF flag. Remains High until reset by PTnON bit Output Toggle with PTMnAF flag Here PTnIO [1:0] = 11 Toggle Output select Note PTnIO [1:0] = 10 Active High Output select Output Inverts when PTnPOL is high Output Pin Reset to Initial value un-defined Compare Match Output Mode – PTnCCLR=0 (n=0, 1) Note: 1. With PTnCCLR=0 a Comparator P match will clear the counter 2. The TM output pin is controlled only by the PTMnAF flag 3. The output pin is reset to itsinitial state by a PTnON bit rising edge Rev. 1.00 96 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value PTnCCLR = 1; PTnM [1:0] = 00 CCRA = 0 Counter overflow CCRA > 0 Counter cleared by CCRA value 0x3FF CCRA=0 Resume CCRA Pause Stop Counter Restart CCRP Time PTnON PTnPAU PTnPOL No PTMnAF flag generated on CCRA overflow CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTM O/P Pin PTMPF not generated Output pin set to initial Level Low if PTnOC=0 Output does not change Output Toggle with PTMnAF flag Here PTnIO [1:0] = 11 Toggle Output select Output not affected by PTMnAF flag. Remains High until reset by PTnON bit Note PTnIO [1:0] = 10 Active High Output select Output Inverts when PTnPOL is high Output Pin Reset to Initial value Output controlled by other pin-shared function Compare Match Output Mode – PTnCCLR=1 (n=0, 1) Note: 1. With PTnCCLR=1 a Comparator A match will clear the counter 2. The TM output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. A PTMnPF flag is not generated when PTnCCLR=1 Rev. 1.00 97 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Timer/Counter Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 11 respectively. The Timer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the Timer/Counter Mode the TM output pin is not used. Therefore the above description and Timing Diagrams for the Compare Match Output Mode can be used to understand its function. As the TM output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively. The PWM function within the TM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the TM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the PTnCCLR bit has no effect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency, while the other one is used to control the duty cycle. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP, will be generated when a compare match occurs from either Comparator A or Comparator P. The PTnOC bit in the PTMnC1 register is used to select the required polarity of the PWM waveform while the two PTnIO1 and PTnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The PTnPOL bit is used to reverse the polarity of the PWM output waveform. • 10-bit PWM Mode, Edge-aligned Mode CCRP 0 Period 1024 1~1023 Duty 1~1023 CCRA If fSYS = 16MHz, TM clock source select fSYS/4, CCRP = 512 and CCRA = 128, The PTM PWM output frequency = (fSYS/4) /512 = fSYS/2048 = 7.8125kHz, duty = 128/512 = 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%. Rev. 1.00 98 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value PTnM [1:0] = 10 ; PTnIO [1:0]=10 Counter cleared by CCRP Counter Reset when PTnON returns high CCRP Pause Resume CCRA Counter Stop if PTnON bit low Time PTnON PTnPAU PTnPOL CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF PTM O/P Pin (PTnOC=1) PTM O/P Pin (PTnOC=0) PWM Duty Cycle set by CCRA PWM Period set by CCRP PWM resumes operation Output controlled by Output Inverts other pin-shared function When PTnPOL = 1 PWM mode (n=0, 1) Note: 1. A counter clear sets the PWM Period 2. The internal PWM function continues running even when PTnIO [1:0] = 00 or 01 3. The PTnCCLR bit has no influence on PWM operation Rev. 1.00 99 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Single Pulse Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 11 respectively. The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the TM output pin. The trigger for the pulse output leading edge is a low to high transition of the PTnON bit, which can be implemented using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a TM interrupt. The counter can only be reset back to zero when the PTnON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR bit is not used in this Mode. Single Pulse Generation (n=0, 1) Rev. 1.00 100 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value PTnM [1:0] = 10 ; PTnIO [1:0] = 11 Counter stopped by CCRA Counter Reset when PTnON returns high CCRA Pause Counter Stops by software Resume CCRP Time PTnON Software Trigger Auto. set by PTCKn pin Cleared by CCRA match PTCKn pin Software Trigger Software Trigger Software Clear Software Trigger PTCKn pin Trigger PTnPAU PTnPOL No CCRP Interrupts generated CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTM O/P Pin (PTnOC=1) PTM O/P Pin (PTnOC=0) Output Inverts when PTnPOL = 1 Pulse Width set by CCRA Single Pulse Mode (n=0, 1) Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse is triggered by the PTCKn pin or by setting the PTnON bit high 4. A PTCKn pin active edge will automatically set the PTnON bit hight 5. In the Single Pulse Mode, PTnIO [1:0] must be set to “11” and can not be changed. Rev. 1.00 101 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external signals to capture and store the present value of the internal counter and can therefore be used for applications such as pulse width measurements. The external signal is supplied on the PTPn or PTCKn pin, selected by the PTnCKS bit in the PTMnC1 register. The input pin active edge can be a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTnIO1 and PTnIO0 bits in the PTMnC1 register. The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPn or PTCKn pin the present value in the counter will be latched into the CCRA registers and a TM interrupt generated. Irrespective of what events occur on the PTPn or PTCKn pin the counter will continue to free run until the PTnON bit changes from high to low. When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P, a TM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPn or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPn or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPn pin is pin or PTCKn pin shared with other functions, care must be taken if the PTMn is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode. Rev. 1.00 102 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Counter Value PTnM [1:0] = 01 Counter cleared by CCRP Counter Counter Reset Stop CCRP YY Pause Resume XX Time PTnON PTnPAU Active edge Active edge Active edge PTMn capture pin PTPn or PTCKn CCRA Int. Flag PTMnAF CCRP Int. Flag PTMnPF CCRA Value PTnIO [1:0] Value XX 00 – Rising edge YY 01 – Falling edge XX 10 – Both edges YY 11 – Disable Capture Capture Input Mode (n=0, 1) Note: 1. PTnM [1:0] = 01 and active edge set by the PTnIO [1:0] bits 2. A TM Capture input pin active edge transfers the counter value to CCRA 3. PTnCCLR bit not used 4. No output function – PTnOC and PTnPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero. Rev. 1.00 103 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals by a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains a 8-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. The accompanying block diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Structure A/D Converter Register Description Overall operation of the A/D converter is controlled using five registers. A read only register pair exists to store the ADC data 12-bit value. The remaining three registers are control registers which setup the operating and control function of the A/D converter. Register Name Bit 7 6 5 4 3 2 1 0 ADRL(ADRFS=0) D3 D2 D1 D0 — — — — ADRH(ADRFS=0) D11 D10 D9 D8 D7 D6 D5 D4 ADRL(ADRFS=1) D7 D6 D5 D4 D3 D2 D1 D0 ADRH(ADRFS=1) — — — — D11 D10 D9 D8 START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 ADCR1 ACS4 V125EN — ADCK2 ADCK1 ADCK0 ACERL ACE7 ACE6 ACE5 ACE2 ACE1 ACE0 ADCR0 VREFS1 VREFS0 ACE4 ACE3 A/D Converter Register List Rev. 1.00 104 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM A/D Converter Data Registers – ADRL, ADRH As the device contains an internal 12-bit A/D converter, it requires two data registers to store the converted value. These are a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompanying table. D0~D11 are the A/D conversion result data bits. Any unused bits will be read as zero. ADRFS 0 1 ADRH 7 6 D11 D10 0 0 ADRL 5 4 3 2 1 0 7 6 5 4 3 2 1 0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A/D Data Registers A/D Converter Control Registers – ADCR0, ADCR1, ACERL To control the function and operation of the A/D converter, three control registers known as ADCR0, ADCR1, ACERL are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter, the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter end of conversion status. The ACS4 in the ADCR1 register and ACS2~ACS0 bits in the ADCR0 register define the ADC input channel number. As the device contains only one actual analog to digital converter hardware circuit, each of the individual 8 analog inputs must be routed to the converter. It is the function of the ACS4, ACS2 ~ ACS0 bits to determine which analog channel input signals or internal VBG is actually connected to the internal A/D converter. The ACERL control register contains the ACE7~ACE0 bits which determine which pins on Port C are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. Setting the corresponding bit high will select the A/D input function, clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistors connected to these pins will be automatically removed if the pin is selected to be an A/D input. Rev. 1.00 105 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM ADCR0 Register Bit 7 6 5 4 3 2 1 0 Name START EOCB ADOFF ADRFS — ACS2 ACS1 ACS0 R/W R/W R R/W R/W — R/W R/W R/W POR 0 1 1 0 — 0 0 0 Bit 7START: Start the A/D conversion 0→1→0: start 0→1: reset the A/D converter and set EOCB to "1" This bit is used to initiate an A/D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. When the bit is set high the A/D converter will be reset. Bit 6EOCB: End of A/D conversion flag 0: A/D conversion ended 1: A/D conversion in progress This read only flag is used to indicate when an A/D conversion process has completed. When the conversion process is running the bit will be high. Bit 5ADOFF : ADC module power on/off control bit 0: ADC module power on 1: ADC module power off This bit controls the power to the A/D internal function. This bit should be cleared to zero to enable the A/D converter. If the bit is set high then the A/D converter will be switched off reducing the device power consumption. As the A/D converter will consume a limited amount of power, even when not executing a conversion, this may be an important consideration in power sensitive battery powered applications. Note: 1. it is recommended to set ADOFF=1 before entering IDLE/SLEEP Mode for saving power. 2. ADOFF=1 will power down the ADC module. Bit 4ADRFS: ADC Data Format Control 0: ADC Data MSB is ADRH bit 7, LSB is ADRL bit 4 1: ADC Data MSB is ADRH bit 3, LSB is ADRL bit 0 This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D data register section. Rev. 1.00 Bit 3 Unimplemented, read as “0” Bit 2 ~ 0 ACS2 ~ ACS0: Select A/D channel (when ACS4 is “0”) 000: AN0 001: AN1 010: AN2 011: AN3 100: AN4 101: AN5 110: AN6 111: AN7 These are the A/D channel select control bits. As there is only one internal hardware A/D converter each of the eight A/D inputs must be routed to the internal converter using these bits. If bit ACS4 in the ADCR1 register is set high then the internal VBG will be routed to the A/D Converter. 106 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM ADCR1 Register Bit 7 6 5 4 3 2 1 0 Name ACS4 V125EN — — VREFS ADCK2 ADCK1 ADCK0 R/W R/W R/W — — R/W R/W R/W R/W POR 0 0 — — 0 0 0 0 Bit 7ACS4: Selecte Internal VBG as ADC input Control 0: Disable 1: Enable This bit enables VBG to be connected to the A/D converter. The V125EN bit must first have been set to enable the bandgap circuit VBG voltage to be used by the A/D converter. When the ACS4 bit is set high, the bandgap voltage will be routed to the A/ D converter and the other A/D input channels disconnected. Bit 6V125EN: Internal VBG Control 0: Disable 1: Enable This bit controls the internal Bandgap circuit on/off function to the A/D converter. When the bit is set high the bandgap voltage VBG can be used by the A/D converter. If VBG is not used by the A/D converter and the LVR function is disabled then the bandgap reference circuit will be automatically switched off to conserve power. When VBG is switched on for use by the A/D converter, a time tBG should be allowed for the bandgap circuit to stabilise before implementing an A/D conversion. Bit 5~4 Unimplemented, read as "0" Bit 3VREFS: Selecte ADC reference voltage 0: Internal ADC power AVDD 1: VREF pin This bit is used to select the reference voltage for the A/D converter. If the bit is 1 then the A/D converter reference voltage is supplied on the external pin VREF. If the pin is 0 then the internal reference is used which is taken from the power supply pin AVDD. When the A/D converter reference voltage is supplied on the external pin VREF which is pin-shared with other functions, all of the other pin-shared functions on this pin are disabled. Bit 2 ~ 0 Rev. 1.00 ADCK2 ~ ADCK0: Select ADC clock source 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: Undefined These three bits are used to select the clock source for the A/D converter. 107 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM ACERL Register Bit 7 6 5 4 3 2 1 0 Name ACE7 ACE6 ACE5 ACE4 ACE3 ACE2 ACE1 ACE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 Bit 7ACE7: Define PB1 is A/D input or not 0: Not A/D input 1: A/D input, AN7 Bit 6ACE6: Define PC6 is A/D input or not 0: Not A/D input 1: A/D input, AN6 Bit 5ACE5: Define PC5 is A/D input or not 0: Not A/D input 1: A/D input, AN5 Bit 4ACE4: Define PC4 is A/D input or not 0: Not A/D input 1: A/D input, AN4 Bit 3ACE3: Define PC3 is A/D input or not 0: Not A/D input 1: A/D input, AN3 Bit 2ACE2: Define PC0 is A/D input or not 0: Not A/D input 1: A/D input, AN2 Bit 1ACE1: Define PB7 is A/D input or not 0: Not A/D input 1: A/D input, AN1 Bit 0ACE0: Define PB6 is A/D input or not 0: Not A/D input 1: A/D input, AN0 A/D Operation The START bit in the ADCR0 register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR0 register will be set high and the analog to digital converter will be reset. It is the START bit that is used to control the overall start operation of the internal analog to digital converter. The EOCB bit in the ADCR0 register is used to indicate when the analog to digital conversion process is complete. This bit will be automatically set to “0” by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the interrupts are enabled, an appropriate internal interrupt signal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter, which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the ADCK2~ADCK0 bits in the ADCR1 register. Rev. 1.00 108 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Although the A/D clock source is determined by the system clock fSYS, and by bits ADCK2~ADCK0, there are some limitations on the A/D clock source speed range that can be selected. As the recommended range of permissible A/D clock period, tAD, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, if the system clock operates at a frequency of 4MHz, the ADCK2~ADCK0 bits should not be set to 000B or 110B. Doing so will give A/D clock periods that are less than the minimum A/D clock period or greater than the maximum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. A/D Clock Period (tAD) fSYS 1MHz ADCK2, ADCK1, ADCK0 =000 (fSYS) ADCK2, ADCK1, ADCK0 =001 (fSYS/2) ADCK2, ADCK1, ADCK0 =010 (fSYS/4) ADCK2, ADCK1, ADCK0 =011 (fSYS/8) ADCK2, ADCK1, ADCK0 =100 (fSYS/16) ADCK2, ADCK1, ADCK0 =101 (fSYS/32) ADCK2, ADCK1, ADCK0 =110 (fSYS/64) ADCK2, ADCK1, ADCK0 =111 1μs 2μs 4μs 8μs 16μs* 32μs* 64μs* Undefined 2MHz 500ns 1μs 2μs 4μs 8μs 16μs* 32μs* Undefined 4MHz 250ns* 500ns 1μs 2μs 4μs 8μs 16μs* Undefined Undefined 8MHz 125ns* 250ns* 500ns 1μs 2μs 4μs 8μs 12MHz 83ns* 167ns* 333ns* 667ns 1.33μs 2.67μs 5.33μs Undefined 16MHz 62ns* 125ns* 250ns* 500ns 1μs 2μs 4μs Undefined A/D Clock Period Examples Controlling the power on/off function of the A/D converter circuitry is implemented using the ADOFF bit in the ADCR0 register. This bit must be zero to power on the A/D converter. When the ADOFF bit is cleared to zero to power on the A/D converter internal circuitry a certain delay, as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs by clearing the ACE7~ACE0 bits in the ACERL registers, if the ADOFF bit is zero then some power will still be consumed. In power conscious applications it is therefore recommended that the ADOFF is set high to reduce power consumption when the A/D converter function is not being used. The reference voltage supply to the A/D Converter can be supplied from either the positive power supply pin, AVDD, or from an external reference source supplied on pin VREF. The desired selection is made using the VREFS bit. As the pin is pin-shared with other function, when the VREF pin function is selected, then the other pin functions will be disabled automatically. Rev. 1.00 109 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port C as well as other functions. The ACE7~ACE0 bits in the ACERL registers, determine whether the input pins are setup as A/D converter analog inputs or whether they have other functions. If the ACE7~ACE0 bits for its corresponding pin is set high then the pin will be setup to be an A/D converter input and the original pin functions disabled. In this way, pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the PCC port control register to enable the A/D input as when the ACE7~ACE0 bits enable an A/D input, the status of the port control register will be overridden. The A/D converter has its own reference voltage pins, VREF, however the reference voltage can also be supplied from the power supply pin, a choice which is made through the VREFS bit in the ADCR1 register. A/D Input Structure Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process. • Step 1 Select the required A/D conversion clock by correctly programming bits ADCK2~ADCK0 in the ADCR1 register. • Step 2 Enable the A/D by clearing the ADOFF bit in the ADCR0 register to zero. • Step 3 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS4, ACS2~ACS0 bits which are also contained in the ADCR1 and ADCR0 register. • Step 4 Select which pins are to be used as A/D inputs and configure them by correctly programming the ACE7~ACE0 bits in the ACERL register. • Step 5 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, and the A/D converter interrupt bit, ADE, must both be set high to do this. Rev. 1.00 110 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM • Step 6 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR0 register from low to high and then low again. Note that this bit should have been originally cleared to zero. • Step 7 To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR0 register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method, if the interrupts are enabled and the stack is not full, the program can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR0 register is used, the interrupt enable step above can be omitted. The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period. ADOFF tON2ST ADC module ON off on off A/D sampling time A/D sampling time tADCS START on tADCS EOCB ACS[4, 2:0] 0011B Power-on Reset 0010B 0000B Reset A/D conversion Reset A/D conversion Start of A/D conversion End of A/D conversion Start of A/D conversion tADC A/D conversion time 0001B Start of A/D conversion Reset A/D conversion End of A/D conversion tADC A/D conversion time Note: A/D clock must be fSYS, fSYS/2, fSYS/4, fSYS/8, fSYS/16, fSYS/32, fSYS/64, tADCS=4tAD tADC=tADCS+n*tAD; n=bit count of ADC resolution tON2ST: at least one instruction cycle (fSYS = 12MHz) A/D Conversion Timing Rev. 1.00 111 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Programming Considerations During microcontroller operations where the A/D converter is not being used, the A/D internal circuitry can be switched off to reduce power consumption, by setting bit ADOFF high in the ADCR0 register. When this happens, the internal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the device contains a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the AVDD or VREF voltage, this gives a single bit analog input value of AVDD or VREF divided by 4096. 1 LSB= (AVDD or VREF) /4096 The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × (AVDD or VREF) /4096 The diagram shows the ideal transfer function between the analog input value and the digitised output value for the A/D converter. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the AVDD or VREF level. Ideal A/D Transfer Function Rev. 1.00 112 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an EOCB polling method to detect the end of conversion clr ADE ; mova,03H mov ADCR1,a; clr ADOFF mova,0Fh ; mov ACERL,a mova,00h mov ADCR0,a ; : start_conversion: clr START ; set START ; clr START ; polling_EOC: sz EOCB ; jmp polling_EOC ; mov a,ADRL ; mov ADRL_buffer,a ; mov a,ADRH ; mov ADRH_buffer,a ; : : jmp start_conversion ; Rev. 1.00 disable ADC interrupt select fSYS/8 as A/D clock and switch off VBG setup ACERL to configure pins AN0~AN3 enable and connect AN0 channel to A/D converter high pulse on start bit to initiate conversion reset A/D start A/D poll the ADCR0 register EOCB bit to detect end of A/D conversion continue polling read low byte conversion result value save result to user defined register read high byte conversion result value save result to user defined register start next a/d conversion 113 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Example: using the interrupt method to detect the end of conversion clr ADE ; mova,03H mov ADCR1,a ; Clr ADOFF mova,0Fh ; mov ACERL,a mova,00h mov ADCR0,a ; Start_conversion: clr START ; set START ; clr START ; clrADF ; set ADE ; set EMI ; : : ; ADC_ISR: mov acc_stack,a ; mov a,STATUS mov status_stack,a ; : : mov a,ADRL ; mov adrl_buffer,a ; mov a,ADRH ; mov adrh_buffer,a ; : : EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; mov a,acc_stack ; reti Rev. 1.00 disable ADC interrupt select fSYS/8 as A/D clock and switch off VBG setup ACERL to configure pins AN0~AN3 enable and connect AN0 channel to A/D converter high pulse on START bit to initiate conversion reset A/D start A/D clear ADC interrupt request flag enable ADC interrupt enable global interrupt ADC interrupt service routine save ACC to user defined memory save STATUS to user defined memory read save read save low byte conversion result value result to user defined register high byte conversion result value result to user defined register restore STATUS from user defined memory restore ACC from user defined memory 114 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Serial Interface Module – SIM The device contains a Serial Interface Module, which includes both the four-line SPI interface or two-line I2C interface types, to allow an easy method of communication with external peripheral hardware. Having relatively simple communication protocols, these serial interface types allow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory, etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM interface functional pins must first be selected using the corresponding pin-shared function selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 register. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull-high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash Memory or EEPROM memory devices etc. Originally developed by Motorola, the four line SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the device can be either master or slave. Although the SPI interface specification can control multiple slave devices from a single master, but the device provides only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI interface is a full duplex synchronous serial data link. It is a four line interface with pin names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can also be disabled or enabled using the SIMEN bit in the SIMC0 register. Communication between devices connected to the SPI interface is carried out in a slave/master mode with all data transfer initiations being implemented by the master. The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to “1” to enable SCS pin function, set CSEN bit to “0” the SCS pin will be floating state. The SPI function in this device offers the following features: • Full duplex synchronous data transfer • Both Master and Slave modes • LSB first or MSB first data transmission modes • Transmission complete flag • Rising or falling active clock edge The status of the SPI interface pins is determined by a number of factors such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN. Rev. 1.00 115 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SPI Master/Slave Connection SPI Block Diagram SPI Register There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two control registers SIMC0 and SIMC2. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMD D7 D6 D5 D4 D3 D2 D1 D0 SIMC2 D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF 3 2 1 SIMDBNC1 SIMDBNC0 SIMEN 0 SPIICF SIM Registers List The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the devices write data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the device can read it from the SIMD register. Any transmission or reception of data from the SPI bus must be made via the SIMD register. Rev. 1.00 116 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × "×": unknown There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI function, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency. Although not connected with the SPI function, the SIMC0 register is also used to control the Peripheral Clock Prescaler. Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag etc. SIMC0 Register Bit 7 6 5 4 3 2 1 Name SIM2 SIM1 SIM0 — R/W R/W R/W R/W — R/W R/W R/W R/W POR 1 1 1 — 0 0 0 0 SIMDBNC1 SIMDBNC0 SIMEN 0 SPIICF Bit 7 ~ 5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the CTM. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as “0” Bit 3 ~ 2SIMDBNC1~SIMDBNC0: I2C Debounce Time Selection 00: No debounce 01: 2 system clocks debounce 1x: 4 system clocks debounce Bit 1SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interf ace via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Rev. 1.00 117 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 0SPIICF: SPI Incompleted Flag 0: SPI incompleted is not occurred 1: SPI incompleted is occurred The SPIICF bit is determined by SCS pin. When SCS pin is set to “1”, it will clear the SPI counter. Meanwhile, the interrupt is occurred, if slave device didn’t complete data received, then the incompleted flag, SPIICF, is set to “1”. SIMC2 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 6 Undefined bits These bits can be read or written by user software program. Bit 5CKPOLB: Determines the base condition of the clock line 0: The SCK line will be high when the clock is inactive 1: The SCK line will be low when the clock is inactive The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. Bit 4CKEG: Determines SPI SCK active clock edge type CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is executed otherwise an erroneous clock edge may be generated. The CKPOLB bit determines the base condition of the clock line, if the bit is high, then the SCK line will be low when the clock is inactive. When the CKPOLB bit is low, then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3MLS: SPI Data shift order 0: LSB 1: MSB This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2CSEN: SPI SCS pin Control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low, then the SCS pin will be disabled and placed into I/O pin or the other functions. If the bit is high the SCS pin will be enabled and used as a select pin. Bit 1WCOL: SPI Write Collision flag 0: No collision 1: Collision The WCOL flag is used to detect if a data collision has occurred. If this bit is high it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. The bit can be cleared by the application program. Rev. 1.00 118 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 0TRF: SPI Transmit/Receive Complete flag 0: Data is being transferred 1: SPI data transmission is completed The TRF bit is the Transmit/Receive Complete flag and is set “1” automatically when an SPI data transmission is completed, but must set to “0” by the application program. It can be used to generate an interrupt. SPI Communication After the SPI interface is enabled by setting the SIMEN bit high, then in the Master Mode, when data is written to the SIMD register, transmission/reception will begin simultaneously. When the data transfer is complete, the TRF flag will be set automatically, but must be cleared using the application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register. The master should output a SCS signal to enable the slave device before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. SPI Master Mode Timing SPI Slave Mode Timing – CKEG=0 Rev. 1.00 119 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SPI Slave Mode Timing – CKEG=1 SPI Transfer Control Flowchart Rev. 1.00 120 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM I2C Interface The I 2C interface is used to communicate with external peripheral devices such as sensors, EEPROM memory etc. Originally developed by Philips, it is a two line low speed serial interface for synchronous serial data transfer. The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. I2C Master Slave Bus Connection I2C Interface Operation The I2C serial interface is a two line interface, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two devices communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data, however, it is the master device that has overall control of the bus. For these devices, which only operates in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. The pull-up control function pin-shared with SCL/SDA pin is still applicable even if I2C device is activated and the related internal pull-up register could be controlled by its corresponding pull-up control register. S T A R T s ig n a l fro m M a s te r S e n d s la v e a d d r e s s a n d R /W b it fr o m M a s te r A c k n o w le d g e fr o m s la v e S e n d d a ta b y te fro m M a s te r A c k n o w le d g e fr o m s la v e S T O P s ig n a l fro m M a s te r Rev. 1.00 121 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM I2C Register There are four control registers associated with the I2C bus, SIMC0, SIMC1, SIMA and SIMTOC and one data register, SIMD. The SIMD register, which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Before the microcontroller writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the microcontroller can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. The SIMTOC register is used for I2C time-out control function. Bit Register Name 7 6 5 4 SIMC0 SIM2 SIM1 SIM0 — SIMC1 HCF HAAS HBB HTX TXAK SIMD D7 D6 D5 D4 D3 SIMA IICA6 IICA5 IICA4 IICA3 IICA2 SIMTOC 3 2 1 0 SIMEN SPIICF SRW RCIN RXAK D2 D1 D0 IICA1 IICA0 D0 SIMDEB1 SIMDEB0 SIMTOEN SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2C Register List SIMC0 Register Bit 7 6 5 4 Name SIM2 SIM1 SIM0 — 3 2 1 R/W R/W R/W R/W — R/W R/W R/W R/W POR 1 1 1 — 0 0 0 0 SIMDBNC1 SIMDBNC0 SIMEN 0 SPIICF Bit 7 ~ 5SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Unused mode These bits setup the overall operating mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slave selection and the SPI Master clock frequency. The SPI clock is a function of the system clock but can also be chosen to be sourced from the CTM. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as “0” Bit 3 ~ 2SIMDBNC1~SIMDBNC0: I2C Debounce Time Selection 00: No debounce 01: 2 system clocks debounce 1x: 4 system clocks debounce Rev. 1.00 122 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 1SIMEN: SIM Control 0: Disable 1: Enable The bit is the overall on/off control for the SIM interface. When the SIMEN bit is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a minimum value. When the bit is high the SIM interface is enabled. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initialised by the application program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous settings and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0SPIICF: SPI Incompleted Flag 0: SPI incompleted is not occurred 1: SPI incompleted is occurred The SPIICF bit is determined by SCS pin. When SCS pin is set to “1”, it will clear the SPI counter. Meanwhile, the interrupt is occurred, if slave device didn’t complete data received, then the incompleted flag, SPIICF, is set to”1”. SIMC1 Register Bit 7 6 5 4 3 2 1 0 Name HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R R/W R POR 1 0 0 0 0 0 0 1 Bit 7HCF: I C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. 2 Bit 6HAAS: I2C Bus address match flag 0: Not address match 1: Address match The HAAS flag is the address match flag. This flag is used to determine if the slave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. This flag will be “1” when the I2C bus is busy which will occur when a START signal is detected. The flag will be set to “0” when the bus is free which will occur when a STOP signal is detected. Bit 4HTX: Select I2C slave device is transmitter or receiver 0: Slave device is the receiver 1: Slave device is the transmitter Rev. 1.00 123 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 3TXAK: I2C Bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to “0” before further data is received. Bit 2SRW: I2C Slave Read/Write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SRW flag is the I 2C Slave Read/Write flag. This flag determines whether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SRW flag to determine whether it should be in transmit mode or receive mode. If the SRW flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SRW flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match Wake-up Control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to 1 to enable the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0RXAK: I2C Bus Receive acknowledge flag 0: Slave receive acknowledge flag 1: Slave do not receive acknowledge flag The RXAK flag is the receiver acknowledge flag. When the RXAK flag is “0”, it means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. The slave transmitter will therefore continue sending out data until the RXAK flag is “1”. When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the I2C bus, the actual data to be transmitted must be placed in the SIMD register. After the data is received from the I2C bus, the device can read it from the SIMD register. Any transmission or reception of data from the I2C bus must be made via the SIMD register. Rev. 1.00 124 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SIMD Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR × × × × × × × × "×": unknown SIMA Register Bit 7 6 5 4 3 2 1 0 Name A6 A5 A4 A3 A2 A1 A0 — R/W R/W R/W R/W R/W R/W R/W R/W — POR 0 0 0 0 0 0 0 — bit 7 ~ 1 A6~ A0: I2C slave address A6~ A0 is the I2C slave address bit 6 ~ bit 0. The SIMA register is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register, the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 0 Undefined bit This bit can be read or written by user software program. I C Block Diagram 2 Rev. 1.00 125 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM I2C Bus Communication Communication on the I2C bus requires four separate steps, a START signal, a slave device address transmission, a data transmission and finally a STOP signal. When a START signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS bit to determine whether the interrupt source originates from an address match or from the completion of an 8-bit data transfer. During a data transfer, note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialize the bus, the following are steps to achieve this: Step 1 Set the SIM2~SIM0 and SIMEN bits in the SIMC0 register to “110” and “1” to enable the I2C bus. Step 2 Write the slave address of the device to the I2C bus address register SIMA. Step 3 Set the SIME bit of the interrupt control register to enable the SIM interrupt. I2C Bus Initialisation Flow Chart Rev. 1.00 126 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM I2C Bus Start Signal The START signal can only be generated by the master device connected to the I2C bus and not by the slave device. This START signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A START condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. Slave Address The transmission of a START signal by the master will be detected by all devices on the I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the START signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the master matches the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As an I 2C bus interrupt can come from two sources, when the program enters the interrupt subroutine, the HAAS bit should be examined to see whether the interrupt source has come from a matching slave address or from the completion of a data byte transfer. When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SRW bit in the SIMC1 register defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver. If the SRW flag is “1” then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter. If the SRW flag is “0” then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver. I2C Bus Slave Address Acknowledge Signal After the master has transmitted a calling address, any slave device on the I 2C bus, whose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a STOP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SRW flag to determine if it is to be a transmitter or a receiver. If the SRW flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to “1”. If the SRW flag is low, then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to “0”. Rev. 1.00 127 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt of its slave address. The order of serial bit transmission is the MSB first and the LSB last. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level “0”, before it can receive the next data byte. If the slave transmitter does not receive an acknowledge bit signal from the master receiver, then the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter, the slave device must first write the data to be transmitted into the SIMD register. If setup as a receiver, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. Note: *When a slave address is matched, the devices must be placed in either the transmit mode and then write data to the SIMD register, or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram Rev. 1.00 128 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the I2C lockup problem due to reception of erroneous clock sources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to count on an I2C bus “START” & “address match” condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMTOC register, then a time-out condition will occur. The time-out function will stop when an I2C “STOP” condition occurs. Rev. 1.00 129 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM S ta rt S C L S R W S la v e A d d r e s s 0 1 S D A 1 1 0 1 0 A C K 1 0 I2 C t i m e - o u t c o u n te r s ta rt S to p S C L 1 0 0 1 0 1 0 0 S D A I2 C t im e - o u t c o u n t e r r e s e t o n S C L n e g a tiv e tr a n s itio n I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and the SIMTOEN bit will be cleared to zero and the SIMTOF bit will be set high to indicate that a time-out condition has occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector. When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out SIMD, SIMA, SIMC0 No change SIMC1 Reset to POR condition I C Registers after Time-out 2 The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections which can be selected using the SIMTOS bits in the SIMTOC register. The time-out duration is calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from about 1ms to 64ms. SIMTOC Register Rev. 1.00 Bit 7 Name SIMTOEN 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 SIMTOF SIMTOS5 SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 Bit 7 SIMTOEN: I2C Time-out Control 0: Disable 1: Enable Bit 6 SIMTOF: I2C Time-out flag 0: No time-out occurred 1: Time-out occurred Bit 5~0 SIMTOS5~SIMTOS0: I2C Time-out Time Selection I2C Time-out clock source is fSUB/32 I2C Time-out time is given by: (SIMTOS [5:0] +1) × (32/fSUB) 130 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM UART Module Serial Interface The device contains an integrated full-duplex asynchronous serial communications UART interface that enables communication with external devices that contain a serial interface. The UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwritten or incorrectly framed. The UART function possesses its own internal interrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features: • Full-duplex, Universal Asynchronous Receiver and Transmitter (UART) communication • 8 or 9 bits character length • Even, odd or no parity options • One or two stop bits • Baud rate generator with 8-bit prescaler • Parity, framing, noise and overrun error detection • Support for interrupt on address detect (last character bit=1) • Transmitter and receiver enabled independently • 2-byte Deep FIFO Receive Data Buffer • Transmit and receive interrupts • Transmit and Receive Multiple Interrupt Generation Sources: ♦♦ Transmitter Empty ♦♦ Transmitter Idle ♦♦ Receiver Full ♦♦ Receiver Overrun ♦♦ Address Mode Detect ♦♦ RX pin Wake-up UART External Interface To communicate with an external serial interface, the internal UART has two external pins known as TX and RX. The TX pin is the UART transmitter pin, which can be used as a general purpose I/O or other pin-shared functional pin if the pin is not configured as a UART transmitter, which occurs when the TXEN bit in the UCR2 control register is equal to zero. Similarly, the RX pin is the UART receiver pin, which can also be used as a general purpose I/O or other pin-shared functional pin, if the pin is not configured as a receiver, which occurs if the RXEN bit in the UCR2 register is equal to zero. Along with the UARTEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the RX pin. Rev. 1.00 131 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM UART Data Transfer Scheme The block diagram shows the overall data transfer structure arrangement for the UART. The actual data to be transmitted from the MCU is first transferred to the TXR register by the application program. The data will then be transferred to the Transmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator. Only the TXR register is mapped onto the MCU Data Memory, the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UART is accepted on the external RX pin, from where it is shifted in, LSB first, to the Receiver Shift Register at a rate controlled by the Baud Rate Generator. When the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buffered and can be manipulated by the application program. Only the RXR register is mapped onto the MCU Data Memory, the Receiver Shift Register is not mapped and is therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory. This shared register known as the TXR/RXR register is used for both data transmission and data reception. M�B T�ans�itte� �hift Registe� ………………………… L�B TX Pin RX Pin M�B Receive� �hift Registe� ………………………… L�B CLK CLK Baud Rate Gene�ato� TXR Registe� RXR Registe� Buffe� MCU Data Bus UART Data Transfer Scheme UART Status and Control Registers There are five control registers associated with the UART function. The USR, UCR1 and UCR2 registers control the overall function of the UART, while the BRG register controls the Baud rate. The actual data to be transmitted and received on the serial interface is managed through the TXR/ RXR data registers. Bit Register Name 7 6 5 4 3 2 1 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR2 TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR/RXR TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 BRG BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 UART Register Summary Rev. 1.00 132 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM USR register The USR register is the status register for the UART, which can be read by the program to determine the present status of the UART. All flags within the USR register are read only. Further explanation on each of the flags is given below: Bit 7 6 5 4 3 2 1 0 Name PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is “0”, it indicates a parity error has not been detected. When the flag is “1”, it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6NF: Noise flag 0: No noise is detected 1: Noise is detected The NF flag is the noise flag. When this read only flag is "0", it indicates no noise condition. When the flag is "1", it indicates that the UART has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The NF flag can be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is “0”, it indicates that there is no framing error. When the flag is “1”, it indicates that a framing error has been detected for the current character. The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the receiver buffer has overflowed. When this read only flag is “0”, it indicates that there is no overrun error. When the flag is “1”, it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register. The flag is cleared by a software sequence, which is a read to the status register USR followed by an access to the RXR data register. Bit 3RIDLE: Receiver status 0: Data reception is in progress (data being received) 1: No data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is “0”, it indicates that the receiver is between the initial detection of the start bit and the completion of the stop bit. When the flag is “1”, it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is “1” indicating that the UART receiver is idle and the RX pin stays in logic high condition. Rev. 1.00 133 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 2RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is “0”, it indicates that the RXR read data register is empty. When the flag is “1”, it indicates that the RXR read data register contains new data. When the contents of the shift register are transferred to the RXR register, an interrupt is generated if RIE=1 in the UCR2 register. If one or more errors are detected in the received word, the appropriate receive-related flags NF, FERR, and/or PERR are set within the same clock cycle. The RXIF flag is cleared when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1TIDLE: Transmission idle 0: Data transmission is in progress (data being transmitted) 1: No data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is “0”, it indicates that a transmission is in progress. This flag will be set to “1” when the TXIF flag is “1” and when there is no transmit data or break character being transmitted. When TIDLE is equal to “1”, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register. The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0TXIF: Transmit TXR data register status 0: Character is not transferred to the transmit shift register 1: Character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is “0”, it indicates that the character is not transferred to the transmitter shift register. When the flag is “1”, it indicates that the transmitter shift register has received a character from the TXR data register. The TXIF flag is cleared by reading the UART status register (USR) with TXIF set and then writing to the TXR data register. Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. UCR1 register The UCR1 register together with the UCR2 register are the two UART control registers that are used to set the various options for the UART function, such as overall on/off control, parity control, data transfer bit length etc. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 “x” unknown Bit 7UARTEN: UART function enable control 0: Disable UART. TX and RX pins are as I/O or other pin-shared functional pins 1: Enable UART. TX and RX pins function as UART pins The UARTEN bit is the UART enable bit. When this bit is equal to “0”, the UART will be disabled and the RX pin as well as the TX pin will be as General Purpose I/O or other pin-shared functional pins. When the bit is equal to “1”, the UART will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. Rev. 1.00 134 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM When the UART is disabled, it will empty the buffer so any character remaining in the buffer will be discarded. In addition, the value of the baud rate counter will be reset. If the UART is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmissions and receptions will be terminated and the module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to “1”, a 9-bit data length format will be selected. If the bit is equal to “0”, then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This is the parity enable bit. When this bit is equal to “1”, the parity function will be enabled. If the bit is equal to “0”, then the parity function will be disabled. Replace the most significant bit position with a parity bit. Bit 4PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to “1”, odd parity type will be selected. If the bit is equal to “0”, then even parity type will be selected. Bit 3STOPS: Number of Stop bits selection 0: One stop bit format is used 1: Two stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to “1”, two stop bits are used. If this bit is equal to “0”, then only one stop bit is used. Bit 2TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The TXBRK bit is the Transmit Break Character bit. When this bit is “0”, there are no break characters and the TX pin operates normally. When the bit is “1”, there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to “1”, after the buffered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the received data known as RX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Bit 0TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. Rev. 1.00 135 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM UCR2 register The UCR2 register is the second of the two UART control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation of the UART Transmitter and Receiver as well as enabling the various UART interrupt sources. The register also serves to control the baud rate speed, receiver wake-up enable and the address detect enable. Further explanation on each of the bits is given below: Bit 7 6 5 4 3 2 1 0 Name TXEN RXEN BRGH ADDEN WAKE R/W R/W R/W R/W R/W R/W RIE TIIE TEIE R/W R/W POR 0 0 0 0 0 0 R/W 0 0 Bit 7TXEN: UART Transmitter enabled control 0: UART transmitter is disabled 1: UART transmitter is enabled The bit named TXEN is the Transmitter Enable Bit. When this bit is equal to “0”, the transmitter will be disabled with any pending data transmissions being aborted. In addition the buffers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the TXEN bit is equal to “1” and the UARTEN bit is also equal to “1”, the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter. If this situation occurs, the TX pin will be used as an I/O or other pin-shared functional pin. Bit 6RXEN: UART Receiver enabled control 0: UART receiver is disabled 1: UART receiver is enabled The bit named RXEN is the Receiver Enable Bit. When this bit is equal to “0”, the receiver will be disabled with any pending data receptions being aborted. In addition the receive buffers will be reset. In this situation the RX pin will be used as an I/O or other pin-shared functional pin. If the RXEN bit is equal to “1” and the UARTEN bit is also equal to “1”, the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be used as an I/O or other pin-shared functional pin. Bit 5BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator. This bit, together with the value placed in the baud rate register BRG, controls the Baud Rate of the UART. If this bit is equal to “1”, the high speed mode is selected. If the bit is equal to “0”, the low speed mode is selected. Bit 4ADDEN: Address detect function enable control 0: Address detect function is disabled 1: Address detect function is enabled The bit named ADDEN is the address detect function enable control bit. When this bit is equal to “1”, the address detect function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0 or the 9th bit, which corresponds to RX8 if BNO=1, has a value of “1”, then the received word will be identified as an address, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of BNO. If the address bit known as the 8th or 9th bit of the received word is “0” with the address detect function being enabled, an interrupt will not be generated and the received data will be discarded. Rev. 1.00 136 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 3WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled This bit enables or disables the receiver wake-up function. If this bit is equal to “1” and the MCU is in IDLE or SLEEP mode, a falling edge on the RX input pin will wake-up the device. Please reference the UART RX pin wake-up functions in different operating mode for the detail. If this bit is equal to “0” and the MCU is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake-up the device. Bit 2RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled This bit enables or disables the receiver interrupt. If this bit is equal to “1” and when the receiver overrun flag OERR or receive data available flag RXIF is set, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1TIIE: Transmitter Idle interrupt enable control 0: Transmitter idle interrupt is disabled 1: Transmitter idle interrupt is enabled This bit enables or disables the transmitter idle interrupt. If this bit is equal to “1” and when the transmitter idle flag TIDLE is set, due to a transmitter idle condition, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0TEIE: Transmitter Empty interrupt enable control 0: Transmitter empty interrupt is disabled 1: Transmitter empty interrupt is enabled This bit enables or disables the transmitter empty interrupt. If this bit is equal to “1” and when the transmitter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to “0”, the UART interrupt request flag will not be influenced by the condition of the TXIF flag. TXR/RXR register Bit 7 6 5 4 3 2 1 0 Name TXRX7 TXRX6 TXRX5 TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x” unknown Bit 7~0TXRX7~TXRX0: UART Transmit/Receive Data bit 7 ~ bit 0 BRG Register Bit 7 6 5 4 3 2 1 0 Name BRG7 BRG6 BRG5 BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x “x” unknown Bit 7~0BRG7~BRG0: Baud Rate values By programming the BRGH bit in UCR2 Register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Note: Baud rate= fSYS/[64×(N+1)] if BRGH=0. Baud rate= fSYS/[16×(N+1)] if BRGH=1. Rev. 1.00 137 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Baud Rate Generator To setup the speed of the serial data communication, the UART function contains its own dedicated baud rate generator. The baud rate is controlled by its own internal free running 8-bit timer, the period of which is determined by two factors. The first of these is the value placed in the baud rate register BRG and the second is the value of the BRGH bit with the control register UCR2. The BRGH bit decides if the baud rate generator is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value N in the BRG register which is used in the following baud rate calculation formula determines the division factor. Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fSYS /[64 (N+1)] fSYS /[16 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register, the required baud rate can be setup. Note that because the actual baud rate is determined using a discrete value, N, placed in the BRG register, there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. Calculating the register and error values For a clock frequency of 4MHz, and with BRGH set to “0” determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = fSYS /[64 (N+1)] Re-arranging this equation gives N = [fSYS /(BR×64)] - 1 Giving a value for N = [4000000 /(4800×64)] - 1 = 12.0208 To obtain the closest value, a decimal value of 12 should be placed into the BRG register. This gives an actual or calculated baud rate value of BR = 4000000 /[64×(12 + 1)] = 4808 Therefore the error is equal to (4808 - 4800) /4800 = 0.16% The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rate K/BPS Baud Rates for BRGH=0 fSYS = 16 MHz BRG Kbaud fSYS = 20 MHz Error (%) BRG Kbaud Error (%) 0.3 — — — — — — 1.2 207 1.202 0.16 259 1.202 0.16 2.4 103 2.404 0.16 129 2.404 0.16 4.8 51 4.808 0.16 64 4.808 0.16 9.6 25 9.615 0.16 32 9.470 -1.36 19.2 12 19.231 0.16 15 19.531 1.73 38.4 6 35.714 -6.99 7 39.063 1.73 57.6 3 62.5 8.51 4 62.5 8.51 115.2 1 125 8.51 2 104.17 -9.58 250 0 250 0 0 312.5 25 Baud Rates and Error Values for BRGH = 0 Rev. 1.00 138 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Baud Rate K/BPS Baud Rates for BRGH=1 fSYS = 16 MHz fSYS = 20 MHz BRG Kbaud Error (%) BRG Kbaud Error (%) 0.3 — — — — — — 1.2 — — — — — — 2.4 — — — — — — 4.8 207 4.808 0.16 — — — 9.6 103 9.615 0.16 129 9.615 0.16 19.2 51 19.231 0.16 64 19.231 0.16 38.4 25 38.462 0.16 32 37.879 -1.36 57.6 16 58.824 2.12 21 56.818 -1.35 115.2 8 111.11 -3.55 10 113.636 -1.36 250 3 250 0 4 250 0 Baud Rates and Error Values for BRGH = 1 UART Setup and Control For data transfer, the UART function utilizes a non-return-to-zero, more commonly known as NRZ, format. This is composed of one start bit, eight or nine data bits, and one or two stop bits. Parity is supported by the UART hardware, and can be setup to be even, odd or no parity. For the most common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setting, which is the setting at power-on. The number of data bits and stop bits, along with the parity, are setup by programming the corresponding BNO, PRT, PREN, and STOPS bits in the UCR1 register. The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator, while the data is transmitted and received LSB first. Although the UART transmitter and receiver are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/disabling the UART The basic on/off function of the internal UART function is controlled using the UARTEN bit in the UCR1 register. If the UARTEN, TXEN and RXEN bits are set, then these two UART pins will act as normal TX output pin and RX input pin respectively. If no data is being transmitted on the TX pin, then it will default to a logic high value. Clearing the UARTEN bit will disable the TX and RX pins and allow these two pins to be used as normal I/O or other pin-shared functional pins. When the UART function is disabled the buffer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaffected. If the UARTEN bit in the UCR1 register is cleared while the UART is active, then all pending transmissions and receptions will be immediately suspended and the UART will be reset to a condition as defined above. If the UART is then subsequently re-enabled, it will restart again in the same configuration. Rev. 1.00 139 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Data, parity and stop bit selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register. The BNO bit controls the number of data bits which can be set to either 8 or 9, the PRT bit controls the choice of odd or even parity, the PREN bit controls the parity on/off function and the STOPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit identifies the frame as an address character. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bits Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. UART transmitter Data word lengths of either 8 or 9 bits, can be selected by programming the BNO bit in the UCR1 register. When BNO bit is set, the word length will be set to 9 bits. In this case the 9th bit, which is the MSB, needs to be stored in the TX8 bit in the UCR1 register. At the transmitter core lies the Transmitter Shift Register, more commonly known as the TSR, whose data is obtained from the transmit data register, which is known as the TXR register. The data to be transmitted is loaded into this TXR register by the application program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register, if it is available. It should be noted that the TSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator has defined a shift clock source. However, the transmission can also be initiated by first loading data into the TXR register, after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty, in which case a transfer to the TXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin will then return to the I/O or other pin-shared function. Rev. 1.00 140 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Transmitting data When the UART is transmitting data, the data is shifted on the TX pin from the shift register, with the least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register. It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the TXEN bit to ensure that the TX pin is used as a UART transmitter pin. • Access the USR register and write the data that is to be transmitted into the TXR register. Note that this step will clear the TXIF bit. • This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register. Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UART hardware and if set indicates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register, which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register, resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. To clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmit break If the TXBRK bit is set then break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13×N ‘0’ bits and stop bits, where N=1, 2, etc. If a break character is to be transmitted then the TXBRK bit must be first set by the application program, then cleared to generate the stop bits. Transmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept at a logic high level then the transmitter circuitry will transmit continuous break characters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic highs at the end of the last break character will ensure that the start bit of the next frame is recognized. Rev. 1.00 141 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM UART receiver The UART is capable of receiving word lengths of either 8 or 9 bits. If the BNO bit is set, the word length will be set to 9 bits with the MSB being stored in the RX8 bit of the UCR1 register. At the receiver core lies the Receive Serial Shift Register, commonly known as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receive serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sampled three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register, unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving data When the UART receiver is receiving data, the data is serially shifted in on the external RX input pin, LSB first. In the read mode, the RXR register forms a buffer between the internal bus and the receiver shift register. The RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while a third byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the third byte has been completely shifted in, otherwise this third byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows: • Make the correct selection of BNO, PRT, PREN and STOPS bits to define the word length, parity type and number of stop bits. • Setup the BRG register to select the desired baud rate. • Set the RXEN bit to ensure that the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received the following sequence of events will occur: • The RXIF bit in the USR register will be set when RXR register has data available, at least one character can be read. • When the contents of the shift register have been transferred to the RXR register, then if the RIE bit is set, an interrupt will be generated. • If during reception, a frame error, noise error, parity error, or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. An RXR register read execution Rev. 1.00 142 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Receive break Any break character received by the UART will be managed as a framing error. The receiver will count and expect a certain number of bit times as specified by the values programmed into the BNO and STOPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete after the number of bit times specified by BNO and STOPS. The RXIF bit is set, FERR is set, zeros are loaded into the receive data register, interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the assumption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buffer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following: • The framing error flag, FERR, will be set. • The receive data register, RXR, will be cleared. • The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle status When the receiver is reading data, which means it will be in between the detection of a start bit and the reading of a stop bit, the receiver status flag in the USR register, otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver interrupt The read only receive interrupt flag RXIF in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register, RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing receiver errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR flag The RXR register is composed of a two byte deep FIFO data buffer, where two bytes can be held in the FIFO register, while a third byte can continue to be received. Before the third byte has been entirely shifted in, the data should be read from the RXR register. If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen: • The OERR flag in the USR register will be set. • The RXR contents will not be lost. • The shift register will be overwritten. • An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the RXR register. Rev. 1.00 143 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Noise Error – NF Flag Over-sampling is used for data recovery to identify valid incoming data and noise. If noise is detected within a frame the following will occur: • The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit. • Data will be transferred from the Shift register to the RXR register. • No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by a USR register read operation followed by an RXR register read operation. Framing Error – FERR Flag The read only framing error flag, FERR, in the USR register, is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high, otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared on any reset. Parity Error – PERR Flag The read only parity error flag, PERR, in the USR register, is set if the parity of the received word is incorrect. This error flag is only applicable if the parity is enabled, PREN = 1, and if the parity type, odd or even is selected. The read only PERR flag is buffered along with the received data bytes. It is cleared on any reset. It should be noted that the FERR and PERR flags are buffered along with the corresponding word and should be read before reading the data word. UART Module Interrupt Structure Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt control is enabled and the stack is not full, the program will jump to its corresponding interrupt vector where it can be serviced before returning to the main program. Four of these conditions have the corresponding USR register flags which will generate a UART interrupt if its associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address detect condition, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt when an address detect condition occurs if its function is enabled by setting the ADDEN bit in the UCR2 register. An RX pin wake-up, which is also a UART interrupt source, does not have an associated flag, but will generate a UART interrupt if the microcontroller is woken up by a falling edge on the RX pin, if the WAKE and RIE bits in the UCR register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay, commonly known as the System Start-up Time, for the oscillator to restart and stabilize before the system resumes normal operation. Note that the USR register flags are read only and cannot be cleared or set by the application program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the case for some of the other interrupts. The flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART register section. The overall UART interrupt can be disabled or enabled by the related interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. Rev. 1.00 144 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM USR Register UCR2 Register Transmitter Empty Flag TXIF TEIE 0 1 Transmitter Idle Flag TIDLE TIIE 0 1 RIE 0 1 Receiver Overrun Flag OERR OR Receiver Data Available RXIF RX Pin Wake-up WAKE ADDEN UART Interrupt Request Flag UARF To MCU Interrupt Controller 0 1 0 1 0 1 RX7 if BNO=0 RX8 if BNO=1 UCR2 Register UART Interrupt Scheme Address detect mode Setting the Address Detect Mode bit, ADDEN, in the UCR2 register, enables this special mode. If this bit is enabled then an additional qualifier will be placed on the generation of a Receiver Data Available interrupt, which is requested by the RXIF flag. If the ADDEN bit is enabled, then when data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the MFE, URE and EMI interrupt enable bits must also be enabled for correct interrupt generation. This highest address bit is the 9th bit if BNO=1 or the 8th bit if BNO=0. If this bit is high, then the received word will be defined as an address rather than data. A Data Available interrupt will be generated every time the last bit of the received word is set. If the ADDEN bit is not enabled, then a Receiver Data Available interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detect mode and parity enable are mutually exclusive functions. Therefore if the address detect mode is enabled, then to ensure correct operation, the parity function should be disabled by resetting the parity enable bit to zero. ADDEN 0 1 Bit 9 if BNO=1, Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 × 1 √ ADDEN Bit Function Rev. 1.00 145 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM UART Module Power Down and Wake-up When the fSYS is off, the UART will cease to function. All clock sources to the module are shutdown. If the fSYS is off while a transmission is still in progress, then the transmission will be paused until the UART clock source derived from the microcontroller is activated. In a similar way, if the MCU enters the Power Down Mode while receiving data, then the reception of data will likewise be paused. When the MCU enters the Power Down Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be affected. It is recommended to make sure first that the UART data transmission or reception has been finished before the microcontroller enters the Power Down mode. The UART function contains a receiver RX pin wake-up function, which is enabled or disabled by the WAKE bit in the UCR2 register. If this bit, along with the UART enable bit, UARTEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the Power Down Mode, then a falling edge on the RX pin will wake up the MCU from the Power Down Mode. Note that as it takes certain system clock cycles after a wake-up, before normal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UART wake-up interrupt to occur, in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, UARE, must also be set. If these two bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed. Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. The device contains an external interrupt and internal interrupts functions. The external interrupt is generated by the action of the external INTn pins, while the internal interrupts are generated by various internal functions such as the TMs, Time Base, EEPROM, SIM, UART and the A/D converter. Interrupt Registers Overall interrupt control, which basically means the setting of request flags when certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is controlled by a series of registers, located in the Special Purpose Data Memory, as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. The first is the INTC0~INTC3 registers which setup the primary interrupts, the second is the MFI0~MFI2 registers which setup the Multi-function interrupts. Finally there are INTEG0~INTEG1 registers to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request. The naming convention of these follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an “E” for enable/disable bit or “F” for request flag. Rev. 1.00 146 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Function Enable Bit Request Flag EMI — INTn Pin INTnE INTnF UART UARE UARF Time Base TBnE TBnF A/D Converter ADE ADF Multi-function MFnE MFnF Global Notes — n=0~5 — n=0 or 1 — n=0~2 EEPROM DEE DEF — SIM SIME SIMF — CTMPE CTMPF CTMAE CTMAF STMPE STMPF STMAE STMAF PTMnPE PTMnPF PTMnAE PTMnAF CTM STM PTM — — n=0 or 1 Interrupt Register Bit Naming Conventions Bit Register Name 7 6 5 4 3 2 1 0 INTEG0 INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 INTEG1 — — — — INT5S1 INT5S0 INT4S1 INT4S0 INTC0 — INT2F INT1F INT0F INT2E INT1E INT0E EMI INTC1 UARF INT5F INT4F INT3F UARE INT5E INT4E INT3E INTC2 ADF MF2F MF1F MF0F ADE MF2E MF1E MF0E INTC3 SIMF DEF TB1F TB0F SIME DEE TB1E TB0E MFI0 — — CTMAF CTMPF — — CTMAE CTMPE MFI1 LVF — STMAF STMPF LVE — STMAE STMPE MFI2 PTM1AF PTM1PF PTM0AF PTM0PF PTM1AE PTM1PE PTM0AE PTM0PE Interrupt Register Contents INTEG0 Register Rev. 1.00 Bit 7 6 5 4 3 2 1 0 Name INT3S1 INT3S0 INT2S1 INT2S0 INT1S1 INT1S0 INT0S1 INT0S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ~ 6 INT3S1, INT3S0: Defines INT3 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt Bit 5 ~ 4 INT2S1, INT2S0: Defines INT2 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt Bit 3 ~ 2 INT1S1, INT1S0: Defines INT1 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt 147 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Bit 1 ~ 0 INT0S1, INT0S0: Defines INT0 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt INTEG1 Register Bit 7 6 5 4 3 2 1 0 Name — — — — INT5S1 INT5S0 INT4S1 INT4S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7 ~ 4 Unimplemented, read as "0" Bit 3 ~ 2 INT5S1, INT5S0: Defines INT5 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt Bit 1 ~ 0 INT4S1, INT4S0: Defines INT4 interrupt active edge 00: Disabled Interrupt 01: Rising Edge Interrupt 10: Falling Edge Interrupt 11: Dual Edge Interrupt INTC0 Register Bit 7 6 5 4 3 2 1 0 Name — INT2F INT1F INT0F INT2E INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6INT2F: INT2 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5INT1F: INT1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4INT0F: INT0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3INT2E: INT2 Interrupt Control 0: Disable 1: Enable Bit 2INT1E: INT1 Interrupt Control 0: Disable 1: Enable Bit 1INT0E: INT0 Interrupt Control 0: Disable 1: Enable Bit 0EMI: Global Interrupt Control 0: Disable 1: Enable Rev. 1.00 148 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM INTC1 Register Bit 7 6 5 4 3 2 1 0 Name UARF INT5F INT4F INT3F UARE INT5E INT4E INT3E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7UARF: UART Interrupt Request Flag 0: No request 1: Interrupt request Bit 6INT5F: INT5 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5INT4F: INT4 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4INT3F: INT3 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3UARE: UART Interrupt Control 0: Disable 1: Enable Bit 2INT5E: INT5 Interrupt Control 0: Disable 1: Enable Bit 1INT4E: INT4 Interrupt Control 0: Disable 1: Enable Bit 0INT3E: INT3 Interrupt Control 0: Disable 1: Enable Rev. 1.00 149 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM INTC2 Register Bit 7 6 5 4 3 2 1 0 Name ADF MF2F MF1F MF0F ADE MF2E MF1E MF0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7ADF: A/D Converter Interrupt Request Flag 0: No request 1: Interrupt request Bit 6MF2F: Multi-function 2 Interrupt Request Flag 0: No request 1: Interrupt request Bit 5MF1F: Multi-function 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4MF0F: Multi-function 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3ADE: A/D Converter Interrupt Control 0: Disable 1: Enable Bit 2MF2E: Multi-function 2 Interrupt Control 0: Disable 1: Enable Bit 1MF1E: Multi-function 1 Interrupt Control 0: Disable 1: Enable Bit 0 MF0E: Multi-function 0 Interrupt Control 0: Disable 1: Enable Rev. 1.00 150 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM INTC3 Register Bit 7 6 5 4 3 2 1 0 Name SIMF DEF TB1F TB0F SIME DEE TB1E TB0E R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7SIMF: Serial Interface Module Interrupt Request Flag 0: No request 1: Interrupt request Bit 6DEF: Data EEPROM Interrupt Request Flag 0: No request 1: Interrupt request Bit 5TB1F : Time Base 1 Interrupt Request Flag 0: No request 1: Interrupt request Bit 4TB0F: Time Base 0 Interrupt Request Flag 0: No request 1: Interrupt request Bit 3 SIME: Serial Interface Module Interrupt Control 0: Disable 1: Enable Bit 2DEE: Data EEPROM Interrupt Control 0: Disable 1: Enable Bit 1 TB1E : Time Base 1 Interrupt Control 0: Disable 1: Enable Bit 0TB0E: Time Base 0 Interrupt Control 0: Disable 1: Enable Rev. 1.00 151 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM MFI0 Register Bit 7 6 5 4 3 2 1 0 Name — — CTMAF CTMPF — — CTMAE CTMPE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7 ~ 6 Unimplemented, read as "0" Bit 5CTMAF: CTM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4CTMPF: CTM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3 ~ 2 Unimplemented, read as "0" Bit 1CTMAE: CTM Comparator A match interrupt control 0: Disable 1: Enable Bit 0CTMPE: CTM Comparator P match interrupt control 0: Disable 1: Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name LVF — STMAF STMPF LVE — STMAE STMPE R/W R/W — R/W R/W R/W — R/W R/W POR 0 — 0 0 0 — 0 0 Bit 7LVF: LVD interrupt request flag 0: No request 1: Interrupt request Bit 6 Unimplemented, read as "0" Bit 5STMAF: STM Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4STMPF: STM Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3LVE: LVD interrupt control 0: Disable 1: Enable Bit 2 Unimplemented, read as "0" Bit 1STMAE: STM Comparator A match interrupt control 0: Disable 1: Enable Bit 0STMPE: STM Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.00 152 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM MFI2 Register Bit 7 6 5 4 Name PTM1AF PTM1PF PTM0AF PTM0PF 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PTM1AE PTM1PE PTM0AE PTM0PE Bit 7PTM1AF: PTM1 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 6PTM1PF: PTM1 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 5PTM0AF: PTM0 Comparator A match interrupt request flag 0: No request 1: Interrupt request Bit 4PTM0PF: PTM0 Comparator P match interrupt request flag 0: No request 1: Interrupt request Bit 3PTM1AE: PTM1 Comparator A match interrupt control 0: Disable 1: Enable Bit2PTM1PE: PTM1 Comparator P match interrupt control 0: Disable 1: Enable Bit 1PTM0AE: PTM0 Comparator A match interrupt control 0: Disable 1: Enable Bit 0PTM0PE: PTM0 Comparator P match interrupt control 0: Disable 1: Enable Rev. 1.00 153 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A match or A/D conversion completion etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a “JMP” which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a “RETI”, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority. Some interrupt sources have their own individual vector while others share the same multi-function interrupt vector. Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is applied. All of the interrupt request flags when set will wake-up the device if it is in SLEEP or IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode. Rev. 1.00 154 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM EMI auto disabled in ISR xxF Legend Request Flag, no auto reset in ISR xxF Request Flag, auto reset in ISR xxE Enable Bits CTMP CTMPF CTMPE CTMA CTMAF CTMAE LVD LVF LVE STMP STMPF STMPE STMA STMAF STMAE PTM0P PTM0PF PTM0PE PTM0A PTM0AF PTM0AE PTM1P PTM1PF PTM1PE PTM1A PTM1AF PTM1AE Interrupts contained within Multi-Function Interrupts Interrupt Name Request Flags Enable Bits Master Enable Vector INT0 Pin INT0F INT0E EMI 04H INT1 Pin INT1F INT1E EMI 08H INT2 Pin INT2F INT2E EMI 0CH INT3 Pin INT3F INT3E EMI 10H INT4 Pin INT4F INT4E EMI 14H INT5 Pin INT5F INT5E EMI 18H UART UARF UARE EMI 1CH M. Funct. 0 MF0F MF0E EMI 20H M. Funct. 1 MF1F MF1E EMI 24H M. Funct. 2 MF2F MF2E EMI 28H A/D ADF ADE EMI 2CH Time Base 0 TB0F TB0E EMI 30H Time Base 1 TB1F TB1E EMI 34H EEPROM DEF DEE EMI 38H SIM SIMF SIME EMI 3CH Priority High Low Interrupt Structure External Interrupt The external interrupt is controlled by signal transitions on the pins INT0~INT5. An external interrupt request will take place when the external interrupt request flag, INTnF, is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. To allow the program to branch to the interrupt vector address, the global interrupt enable bit, EMI, and the external interrupt enable bit, INTnE, must first be set. Additionally the correct interrupt edge type must be selected using the INTEGn register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with an I/O pin, it can only be configured as external interrupt pin if its external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register. When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector, will take place. When the interrupt is serviced, the external interrupt request flag, INTnF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that the pull-high resistor selection on the external interrupt pin will remain valid even if the pin is used as an external interrupt input. The INTEG0~INTEG1 registers are used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG0~INTEG1 registers can also be used to disable the external interrupt function. Rev. 1.00 155 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Multi-function Interrupt Within this device there are up to three Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM Interrupts and LVD interrupt. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags, MF0F~MF2F are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. To allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related MultiFunction request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts, namely the TM Interrupts and LVD interrupt, will not be automatically reset and must be manually reset by the application program. A/D Converter Interrupt The device contains an A/D converter which has its own independent interrupt. The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF, is set, which occurs when the A/D conversion process finishes. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and A/D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector, will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Time Base Interrupts The function of the Time Base Interrupts is to provide regular time signal in the form of an internal interrupt. They are controlled by the overflow signals from their respective timer functions. When these happens their respective interrupt request flags, TB0F or TB1F will be set. To allow the program to branch to their respective interrupt vector addresses, the global interrupt enable bit, EMI and Time Base enable bits, TB0E or TB1E, must first be set. When the interrupt is enabled, the stack is not full and the Time Base overflows, a subroutine call to their respective vector locations will take place. When the interrupt is serviced, the respective interrupt request flag, TB0F or TB1F, will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the Time Base Interrupt is to provide an interrupt signal at fixed time periods. Their clock sources originate from the internal clock source fTB. This fTB input clock passes through a divider, the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source that generates fTB, which in turn controls the Time Base interrupt period, can originate from several different sources, as shown in the System Operating Mode section. Rev. 1.00 156 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM TBC Register Bit 7 6 5 4 3 2 1 0 Name TBON TBCK TB11 TB10 LXTLP TB02 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 1 0 1 1 1 Bit 7TBON: TB0 and TB1 Control bit 0: Disable 1: Enable Bit 6TBCK: Select fTB Clock 0: fTBC 1: fSYS/4 Bit 5 ~ 4 TB11 ~ TB10: Select Time Base 1 Time-out Period 00: 4096/fTB 01: 8192/fTB 10: 16384/fTB 11: 32768/fTB Bit 3LXTLP: LXT Low Power Mode control 0: Disable (Quick Start Mode) 1: Enable (Low Power Mode) Bit 2 ~ 0 TB02 ~ TB00: Select Time Base 0 Time-out Period 000: 28/fTB 001: 29/fTB 010: 210/fTB 011: 211/fTB 100: 212/fTB 101: 213/fTB 110: 214/fTB 111: 215/fTB TB02~TB00 fSYS/4 LXT LIRC M U X fTBC M U X ÷28~215 Time Base 0 Interrupt ÷212~215 Time Base 1 Interrupt fTB TBCK bit Configuration Option TB11~TB10 Time Base Interrupt Serial Interface Module Interrupts A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF, is set, which occurs when a byte of data has been received or transmitted by the SIM interface. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Interrupt enable bit, SIME, must first be set. When the interrupt is enabled, the stack is not full and a byte of data has been transmitted or received by the SIM interface, a subroutine call to the respective Interrupt vector, will take place. When the interrupt is serviced, the respective interrupt request flag, SIMF, will be automatically reset and the EMI bit will be cleared to disable other interrupts. Rev. 1.00 157 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM EEPROM Interrupt An EEPROM Interrupt request will take place when the EEPROM Interrupt request flag, DEF, is set, which occurs when an EEPROM Write cycle ends. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and EEPROM Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM Write cycle ends, a subroutine call to the respective EEPROM Interrupt vector, will take place. When the EEPROM Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, and the EEPROM interrupt request flag, DEF, will also be automatically cleared. TM Interrupts The Compact, Standard and Periodic Type TMs each has two interrupts. All of the TM interrupts are contained within the Multi-function Interrupts. For each of the Compact, Standard and Periodic Type TMs there are two interrupt request flags xTMnPF and xTMnAF and two enable bits xTMnPE and xTMnAE. A TM interrupt request will take place when any of the TM request flags are set, a situation which occurs when a TM comparator P or comparator A match situation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the respective TM Interrupt enable bit, and associated Multi-function interrupt enable bit, MFnF, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant TM Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program. LVD Interrupt The Low Voltage Detector Interrupt is contained within the Multi-function Interrupt. An LVD Interrupt request will take place when the LVD Interrupt request flag, LVF, is set, which occurs when the Low Voltage Detector function detects a low power supply voltage. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low Voltage Interrupt enable bit, LVE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the Multi-function Interrupt vector will take place. When the Low Voltage Interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the LVF flag will not be automatically cleared, it has to be cleared by the application program. UART Interrupt Several individual UART conditions can generate a UART interrupt. When these conditions exist, a low pulse will be generated to get the attention of the microcontroller. These conditions are a transmitter data register empty, transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. To allow the program to branch to the respective interrupt vector addresses, the global interrupt enable bit, EMI, and UART interrupt enable bit, UARE, must first be set. When the interrupt is enabled, the stack is not full and any of these conditions are created, a subroutine call to the UART Interrupt vector will take place. When the interrupt is serviced, the UART Interrupt flag, UARF, will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. However, the USR register flags will be cleared automatically when certain actions are taken by the UART, the details of which are given in the UART section. Rev. 1.00 158 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Interrupt Wake-up Function Each of the interrupt functions has the capability of waking up the microcontroller when in the SLEEP or IDLE Mode. A wake-up is generated when an interrupt request flag changes from low to high and is independent of whether the interrupt is enabled or not. Therefore, even though the device is in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pin, a low power supply voltage or comparator input change may cause their respective interrupt flag to be set high and consequently generate an interrupt. Care must therefore be taken if spurious wake-up situations are to be avoided. If an interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interrupt enable bits have no effect on the interrupt wake-up function. Programming Considerations By disabling the relevant interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained within a Multi-function interrupt, then when the interrupt service routine is executed, as only the Multi-function interrupt request flags, MF0F~MF2F, will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the “CALL” instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interrupt from waking up the microcontroller then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator, status register or other registers are altered by the interrupt service program, their contents should be saved to the memory at the beginning of the interrupt service routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts. Rev. 1.00 159 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Software LCD Driver The devices have the capability of driving external LCD panels. The common pins for LCD driving, SCOM0~SCOM5, and segment pins, SSEG0~SSEG29, are pin shared with certain pin on the I/O ports. The LCD signals (COM and SEG) are generated using the application program. LCD operation An external LCD panel can be driven using this device by configuring the I/O pins as common pins and configuring the I/O pins as segment pins. The LCD driver function is controlled using the SLCDC0~SLCDC4 registers which in addition to controlling the overall on/off function, LCD bias current setup function also controls the pin function selection. This enables the LCD COM and SEG driver to generate the necessary VSS, (1/3)VDD, (2/3)VDD voltage and VDD levels for LCD 1/3 bias operation. The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver. The LCD SCOMn pin is selected to be used for LCD driving by the corresponding pin-shared function selection bits. Note that the Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. VDD VDD VDD SCOM0 (2/3)VDD (1/3)VDD SCOM5 LCD Voltage Select Circuit Analog Switch VSS SSEG0 SSEG29 VSS VSS LCD Driver structure LCD Control Registers The LCD COM driver enables a range of selections to be provided to suit the requirement of the LCD panel which are being used. The bias current choice is implemented using the ISEL1 and ISEL0 bits in the SLCDC0 register, the FRAME bit is used to select the output frame. Rev. 1.00 160 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SLCDC0 Register Bit 7 6 5 4 Name FRAME ISEL1 ISEL0 LCDEN 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 COM3EN COM2EN COM1EN COM0EN Bit 7FRAME: Output frame0 or frame1 0: Frame 0 1: Frame 1 Bit 6~5ISEL1~ISEL0: LCD bias current selection (VDD=5V) 00: 8.3μA 01: 16.7μA 10: 50μA 11: 100μA Bit 4 LCDEN: SCOM and SSEG module on/off control 0: Off 1: On SCOMn and SSEGm can be enable by COMnEN and SEGmEN if LCDEN=1 If LCDEN=0, SCOMn and SSEGm output VSS When LCDEN is set, it will turn on the DC path of resistor to generate LCD Bias voltage. Bit 3 COM3EN: LCD or other function selection 0: Other function 1: SCOM3/SSEG3 Bit 2 COM2EN: LCD or other function selection 0: Other function 1: SCOM2/SSEG2 Bit 1 COM1EN: LCD or other function selection 0: Other function 1: SCOM1/SSEG1 Bit 0 COM0EN: LCD or other function selection 0: Other function 1: SCOM0/SSEG0 Rev. 1.00 161 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SLCDC1 Register Bit Name 7 6 5 4 3 2 1 0 COM5EN COM4EN COMSEGS5 COMSEGS4 COMSEGS3 COMSEGS2 COMSEGS1 COMSEGS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 COM5EN: LCD or other function selection 0: Other function 1: SCOM5/SSEG5 Bit 6 COM4EN: LCD or other function selection 0: Other function 1: SCOM4/SSEG4 Bit 5 COMSEGS5: SCOM5 or SSEG 5 selection 0: SCOM5 1: SSEG5 Bit 4 COMSEGS4: SCOM4 or SSEG 4 selection 0: SCOM4 1: SSEG4 Bit 3 COMSEGS3: SCOM3 or SSEG 3 selection 0: SCOM3 1: SSEG3 Bit 2 COMSEGS2: SCOM2 or SSEG 2 selection 0: SCOM2 1: SSEG2 Bit 1 COMSEGS1: SCOM1 or SSEG 1 selection 0: SCOM1 1: SSEG1 Rev. 1.00 162 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SLCDC2 Register Bit 7 6 5 4 3 Name SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN 2 1 0 SEG8EN SEG7EN SEG6EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SEG13EN: SSEG13 function control 0: Disable 1: Enable Bit 6 SEG12EN: SSEG12 function control 0: Disable 1: Enable Bit 5 SEG11EN: SSEG11 function control 0: Disable 1: Enable Bit 4 SEG10EN: SSEG10 function control 0: Disable 1: Enable Bit 3SEG9EN: SSEG9 function control 0: Disable 1: Enable Bit 2 SEG8EN: SSEG8 function control 0: Disable 1: Enable Bit 1 SEG7EN: SSEG7 function control 0: Disable 1: Enable Bit 0 SEG6EN: SSEG6 function control 0: Disable 1: Enable Rev. 1.00 163 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SLCDC3 Register Bit 7 6 5 4 3 2 1 0 Name SEG21EN SEG20EN SEG19EN SEG18EN SEG17EN SEG16EN SEG15EN SEG14EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SEG21EN: SSEG21 function control 0: Disable 1: Enable Bit 6 SEG20EN: SSEG20 function control 0: Disable 1: Enable Bit 5 SEG19EN: SSEG19 function control 0: Disable 1: Enable Bit 4 SEG18EN: SSEG18 function control 0: Disable 1: Enable Bit 3 SEG17EN: SSEG17 function control 0: Disable 1: Enable Bit 2 SEG16EN: SSEG16 function control 0: Disable 1: Enable Bit 1 SEG15EN: SSEG15 function control 0: Disable 1: Enable Bit 0 SEG14EN: SSEG14 function control 0: Disable 1: Enable Note: SSEG14, SSEG15 share the pins with OSC1/XT1, OSC2/XT2 functions, if select the OSC2/ OSC1 or XT2/XT1pin function, then the SEG14, SEG15 have no actions even if the functions are enabled. Rev. 1.00 164 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SLCDC4 Register Bit 7 6 5 4 3 2 1 0 Name SEG29EN SEG28EN SEG27EN SEG26EN SEG25EN SEG24EN SEG23EN SEG22EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SEG29EN: SSEG29 function control 0: Disable 1: Enable Bit 6 SEG28EN: SSEG28 function control 0: Disable 1: Enable Bit 5 SEG27EN: SSEG27 function control 0: Disable 1: Enable Bit 4 SEG26EN: SSEG26 function control 0: Disable 1: Enable Bit 3 SEG25EN: SSEG25 function control 0: Disable 1: Enable Bit 2 SEG24EN: SSEG24 function control 0: Disable 1: Enable Bit 1 SEG23EN: SSEG23 function control 0: Disable 1: Enable Bit 0 SEG22EN: SSEG22 function control 0: Disable 1: Enable LCD waveform The accompanying waveform diagram shows a typical 1/3 Bias LCD waveform generated using the application program. Note that the depiction of a "1" in the diagram illustrates an illuminated LCD pixel. The COM signal polarity generated on pins SCOMn, whether 0 or 1, are generated using the corresponding I/O data registers. Rev. 1.00 165 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM 1/3 Bias LCD Waveform A cyclic LCD waveform includes two frames, known as Frame 0 and Frame 1 which is selected by the FRAME bit in the SLCDC0 register. The following offers a functional explanation. To select Frame 0 clear the FRAME bit to 0. In frame 0, the COM signal output can have a value of VDD, or have a Vbias value of 1/3VDD (SEG_L). The SEG signal can have a value of VSS, or have a Vbias value of 2/3VDD (SEG_H). In frame 1, the COM signal output can have a value of VSS, or have a Vbias value of 2/3VDD (SEG_H). The SEG signal can have a value of VDD have a Vbias value of 1/3VDD (SEG_L). The SCOM0~SCOMn waveform is controlled by the application program using the FRAME bit, and the corresponding I/O data register for the respective SCOM pin to determine whether the SCOM0~SCOMn output has a value of either VDD, VSS or Vbias. The SSEG0~SSEGm waveform is controlled in a similar way using the FRAME bit and the corresponding I/O data register for the respective SSEG pin to determine whether the SSEG0~SSEGn output has a value of either VDD, VSS or Vbias. Rev. 1.00 166 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Low Voltage Detector – LVD Each device has a Low Voltage Detector function, also known as LVD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low Voltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name LVDC. Three bits in this register, VLVD2~VLVD0, are used to select one of eight fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the LVDO bit is set. If the LVDO bit is low, this indicates that the VDD voltage is above the preset low voltage value. The LVDEN bit is used to control the overall on/off function of the low voltage detector. Setting the bit high will enable the low voltage detector. Clearing the bit to zero will switch off the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch off the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 Name — — LVDO R/W — — R POR — — 0 Bit 7~6 3 2 1 0 LVDEN — VLVD2 VLVD1 VLVD0 R/W — R/W R/W R/W 0 — 0 0 0 Unimplemented, read as "0" Bit 5LVDO: LVD Output Flag 0: No Low Voltage Detect 1: Low Voltage Detect Bit 4LVDEN: Low Voltage Detector Control 0: Disable 1: Enable Bit 3 Unimplemented, read as “0” Bit 2~0VLVD2~VLVD0: Select LVD Voltage 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Rev. 1.00 167 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LVD Operation The Low Voltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.0V. When the power supply voltage, VDD, falls below this pre-determined value, the LVDO bit will be set high indicating a low power supply voltage condition. The Low Voltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low Voltage Detector, a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly, at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. LVD Operation The Low Voltage Detector also has its own interrupt which is contained within one of the Multifunction interrupts, providing an alternative means of low voltage detection, in addition to polling the LVDO bit. The interrupt will only be generated after a delay of tLVD after the LVDO bit has been set high by a low voltage condition. When the device is powered down the Low Voltage Detector will remain active if the LVDEN bit is high. In this case, the LVF interrupt request flag will be set, causing an interrupt to be generated if VDD falls below the preset LVD voltage. This will cause the device to wake-up from the SLEEP Mode, however if the Low Voltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP Mode. When LVD function is enabled, it is recommenced to clear LVD flag first, and then enables interrupt function to avoid mistake action. Rev. 1.00 168 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Configuration Option Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Option 1 High Speed/Low Speed System Oscillator Selection – fOSC: HIRC+LIRC HIRC+LXT HXT+LIRC Application Circuit Rev. 1.00 169 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontroller, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5μs and branch or call instructions would be implemented within 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be “CLR PCL” or “MOV PCL, A”. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of several kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions such as INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Rev. 1.00 170 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction “RET” in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits. Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the “SET [m].i” or “CLR [m].i” instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the “HALT” instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Rev. 1.00 171 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Instruction Set Summary The instructions related to the data memory access in the following table can be used when the desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract immediate data from ACC with Carry Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 1 1Note 1 1 1Note 1 1 1Note 1 1 1Note 1Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 Z Z Z Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 1 1Note 1 1Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,x SBC A,[m] SBCM A,[m] DAA [m] Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rev. 1.00 172 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None 2 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None None 2Note 2Note 2Note None None None 2Note None 1 1Note 1Note 1 1Note 1 1 None None None TO, PDF None None TO, PDF Bit Operation CLR [m].i SET [m].i Branch Operation JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m] SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if Data Memory is not zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Table Read Operation TABRD [m] Read table to TBLH and Data Memory TABRDL [m] Read table (last page) to TBLH and Data Memory ITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and ITABRDL [m] Data Memory Miscellaneous NOP CLR [m] SET [m] CLR WDT SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the “CLR WDT” instruction the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after the “CLR WDT” instructions is executed. Otherwise the TO and PDF flags remain unchanged. Rev. 1.00 173 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Extended Instruction Set The extended instructions are used to support the full range address access for the data memory. When the accessed data memory is located in any data memory sections except sector 0, the extended instruction can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Add Data Memory to ACC Add ACC to Data Memory Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory 2 2Note 2 2Note 2 2Note 2 2Note 2Note Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ Z, C, AC, OV, SC, CZ C 2 2 2 2Note 2Note 2Note 2Note 2 Z Z Z Z Z Z Z Z Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory 2 2Note 2 2Note Z Z Z Z Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 2 2Note 2 2Note 2 2Note 2 2Note None None C C None None C C Move Data Memory to ACC Move ACC to Data Memory 2 2Note None None Clear bit of Data Memory Set bit of Data Memory 2Note 2Note None None Arithmetic LADD A,[m] LADDM A,[m] LADC A,[m] LADCM A,[m] LSUB A,[m] LSUBM A,[m] LSBC A,[m] LSBCM A,[m] LDAA [m] Logic Operation LAND A,[m] LOR A,[m] LXOR A,[m] LANDM A,[m] LORM A,[m] LXORM A,[m] LCPL [m] LCPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Complement Data Memory Complement Data Memory with result in ACC Increment & Decrement LINCA [m] LINC [m] LDECA [m] LDEC [m] Rotate LRRA [m] LRR [m] LRRCA [m] LRRC [m] LRLA [m] LRL [m] LRLCA [m] LRLC [m] Data Move LMOV A,[m] LMOV [m],A Bit Operation LCLR [m].i LSET [m].i Rev. 1.00 174 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Mnemonic Description Cycles Flag Affected Branch LSZ [m] LSZA [m] LSNZ [m] LSZ [m].i LSNZ [m].i LSIZ [m] LSDZ [m] LSIZA [m] LSDZA [m] Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if Data Memory is not zero Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note 2Note None None None None None None None None None 3Note 3Note 3Note None None None 3Note None 2Note 2Note 2Note 2 None None None None Table Read LTABRD [m] Read table to TBLH and Data Memory LTABRDL [m] Read table (last page) to TBLH and Data Memory LITABRD [m] Increment table pointer TBLP first and Read table to TBLH and Data Memory Increment table pointer TBLP first and Read table (last page) to TBLH and LITABRDL [m] Data Memory Miscellaneous LCLR [m] LSET [m] LSWAP [m] LSWAPA [m] Clear Data Memory Set Data Memory Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution. Rev. 1.00 175 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Instruction Definition ADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC ADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC Add Data Memory to ACC ADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC ADD A,x Description Operation Affected flag(s) Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ← ACC + x OV, Z, AC, C, SC ADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC AND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z AND A,x Description Operation Affected flag(s) Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bit wise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ x Z ANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z Rev. 1.00 176 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM CALL addr Description Operation Affected flag(s) Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack ← Program Counter + 1 Program Counter ← addr None CLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None CLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None CLR WDT Description Operation Affected flag(s) Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO ← 0 PDF ← 0 TO, PDF CPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z CPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z DAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C Rev. 1.00 177 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM DEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z DECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z HALT Description Operation Affected flag(s) Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO ← 0 PDF ← 1 TO, PDF INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z INCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z JMP addr Description Operation Affected flag(s) Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter ← addr None MOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None MOV A,x Description Operation Affected flag(s) Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC ← x None MOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None Rev. 1.00 178 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM NOP Description Operation Affected flag(s) No operation No operation is performed. Execution continues with the next instruction. No operation None OR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z OR A,x Description Operation Affected flag(s) Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ x Z ORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z RET Description Operation Affected flag(s) Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter ← Stack None RET A,x Description Operation Affected flag(s) Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter ← Stack ACC ← x None RETI Description Operation Affected flag(s) Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter ← Stack EMI ← 1 None RL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None Rev. 1.00 179 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM RLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None RLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C RLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C RR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None RRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None RRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C Rev. 1.00 180 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM RRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C SBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ SBC A, x Description Operation Affected flag(s) Subtract immediate data from ACC with Carry The immediate data and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC - [m] - C OV, Z, AC, C, SC, CZ SBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ SDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None SDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None Rev. 1.00 181 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None SET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None SIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None SIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None SNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None SNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m]≠ 0 None SUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ Rev. 1.00 182 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM SUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ SUB A,x Description Operation Affected flag(s) Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − x OV, Z, AC, C, SC, CZ SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None SWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None SZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None SZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None SZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None Rev. 1.00 183 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM TABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None TABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRD [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None ITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None XOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z XORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z XOR A,x Description Operation Affected flag(s) Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ x Z Rev. 1.00 184 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Description Operation Affected flag(s) Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ← ACC + [m] + C OV, Z, AC, C, SC LADCM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] + C OV, Z, AC, C, SC LADD A,[m] Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation Affected flag(s) ACC ← ACC + [m] OV, Z, AC, C, SC LADDM A,[m] Description Operation Affected flag(s) Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ← ACC + [m] OV, Z, AC, C, SC LAND A,[m] Description Operation Affected flag(s) Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ← ACC ″AND″ [m] Z LANDM A,[m] Description Operation Affected flag(s) Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ← ACC ″AND″ [m] Z LCLR [m] Description Operation Affected flag(s) Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] ← 00H None LCLR [m].i Description Operation Affected flag(s) Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i ← 0 None Rev. 1.00 Add Data Memory to ACC 185 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LCPL [m] Description Operation Affected flag(s) Complement Data Memory Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ← [m] Z LCPLA [m] Description Operation Affected flag(s) Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1′s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC ← [m] Z LDAA [m] Description Operation Affected flag(s) Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD (Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ← ACC + 00H or [m] ← ACC + 06H or [m] ← ACC + 60H or [m] ← ACC + 66H C LDEC [m] Description Operation Affected flag(s) Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] ← [m] − 1 Z LDECA [m] Description Operation Affected flag(s) Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] − 1 Z LINC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] ← [m] + 1 Z LINCA [m] Description Operation Affected flag(s) Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC ← [m] + 1 Z Rev. 1.00 186 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LMOV A,[m] Description Operation Affected flag(s) Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC ← [m] None LMOV [m],A Description Operation Affected flag(s) Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ← ACC None LOR A,[m] Description Operation Affected flag(s) Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ← ACC ″OR″ [m] Z LORM A,[m] Description Operation Affected flag(s) Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ← ACC ″OR″ [m] Z LRL [m] Description Operation Affected flag(s) Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← [m].7 None LRLA [m] Description Operation Affected flag(s) Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← [m].7 None LRLC [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) ← [m].i; (i=0~6) [m].0 ← C C ← [m].7 C LRLCA [m] Description Operation Affected flag(s) Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) ← [m].i; (i=0~6) ACC.0 ← C C ← [m].7 C Rev. 1.00 187 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LRR [m] Description Operation Affected flag(s) Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← [m].0 None LRRA [m] Description Operation Affected flag(s) Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← [m].0 None LRRC [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i ← [m].(i+1); (i=0~6) [m].7 ← C C ← [m].0 C LRRCA [m] Description Operation Affected flag(s) Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i ← [m].(i+1); (i=0~6) ACC.7 ← C C ← [m].0 C LSBC A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] − C OV, Z, AC, C, SC, CZ LSBCM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] − C OV, Z, AC, C, SC, CZ Rev. 1.00 188 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LSDZ [m] Description Operation Affected flag(s) Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] − 1 Skip if [m]=0 None LSDZA [m] Description Operation Affected flag(s) Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC ← [m] − 1 Skip if ACC=0 None LSET [m] Description Operation Affected flag(s) Set Data Memory Each bit of the specified Data Memory is set to 1. [m] ← FFH None LSET [m].i Description Operation Affected flag(s) Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i ← 1 None LSIZ [m] Description Operation Affected flag(s) Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] ← [m] + 1 Skip if [m]=0 None LSIZA [m] Description Operation Affected flag(s) Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] + 1 Skip if ACC=0 None LSNZ [m].i Description Operation Affected flag(s) Skip if Data Memory is not 0 If the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i ≠ 0 None Rev. 1.00 189 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LSNZ [m] Description Operation Affected flag(s) Skip if Data Memory is not 0 If the content of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m] ≠ 0 None LSUB A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ← ACC − [m] OV, Z, AC, C, SC, CZ LSUBM A,[m] Description Operation Affected flag(s) Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ← ACC − [m] OV, Z, AC, C, SC, CZ LSWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 ↔ [m].7~[m].4 None LSWAPA [m] Description Operation Affected flag(s) Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3~ACC.0 ← [m].7~[m].4 ACC.7~ACC.4 ← [m].3~[m].0 None LSZ [m] Description Operation Affected flag(s) Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m]=0 None LSZA [m] Description Operation Affected flag(s) Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC ← [m] Skip if [m]=0 None Rev. 1.00 190 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM LSZ [m].i Description Operation Affected flag(s) Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i=0 None LTABRD [m] Description Operation Affected flag(s) Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LTABRDL [m] Description Operation Affected flag(s) Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LITABRD [m] Description Operation Increment table pointer low byte first and read table to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the program code addressed by the table pointer (TBHP and TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) Affected flag(s) None LITABRDL [m] Description Operation Affected flag(s) Increment table pointer low byte first and read table (last page) to TBLH and Data Memory Increment table pointer low byte, TBLP, first and then the low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] ← program code (low byte) TBLH ← program code (high byte) None LXOR A,[m] Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ← ACC ″XOR″ [m] Z LXORM A,[m] Description Operation Affected flag(s) Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ← ACC ″XOR″ [m] Z Rev. 1.00 191 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.00 192 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM 28-pin SOP (300mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.406 BSC — B — 0.295 BSC — C 0.012 — 0.020 C’ — 0.705 BSC — D — — 0.104 E — 0.050 BSC — F 0.004 — 0.012 G 0.016 — 0.050 H 0.008 — 0.013 α 0° — 8° Symbol Rev. 1.00 Dimensions in mm Min. Nom. Max. — A — 10.30 BSC B — 7.50 BSC — C 0.31 — 0.51 C’ — 17.9 BSC — D — — 2.65 E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8° 193 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM 28-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. — A — 0.236 BSC B — 0.154 BSC — C 0.008 — 0.012 C’ — 0.390 BSC — D — — 0.069 E — 0.025 BSC — F 0.004 — 0.010 G 0.016 — 0.050 H 0.004 — 0.010 α 0° — 8° Symbol A Rev. 1.00 Dimensions in mm Min. Nom. Max. — 6.0 BSC — B — 3.9 BSC — C 0.20 — 0.30 C’ — 9.9 BSC — D — — 1.75 E — 0.635 BSC — F 0.10 — 0.25 G 0.41 — 1.27 H 0.10 — 0.25 α 0° — 8° 194 September 25, 2014 HT66F488/HT66F489 A/D 8-Bit Flash MCU with EEPROM Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.00 195 September 25, 2014