Data Sheet

BUK9612-55B
N-channel TrenchMOS logic level FET
Rev. 02 — 4 June 2010
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
 Low conduction losses due to low
on-state resistance
 Suitable for logic level gate drive
sources
 Q101 compliant
 Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
 12 V and 24 V loads
 General purpose power switching
 Automotive systems
 Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Quick reference data
Symbol
Parameter
Conditions
Min
Typ
Max Unit
VDS
drain-source
voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
55
V
ID
drain current
VGS = 5 V; Tmb = 25 °C;
see Figure 1; see Figure 3
-
-
75
A
Ptot
total power
dissipation
Tmb = 25 °C; see Figure 2
-
-
157
W
VGS = 10 V; ID = 25 A;
Tj = 25 °C
-
9
10
mΩ
VGS = 5 V; ID = 25 A;
Tj = 25 °C;
see Figure 11; see Figure 12
-
10.2 12
mΩ
[1]
Static characteristics
RDSon
drain-source
on-state
resistance
BUK9612-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 1.
Symbol
Quick reference data …continued
Parameter
Conditions
Min
Typ
Max Unit
-
-
172
mJ
-
12
-
nC
Avalanche ruggedness
EDS(AL)S
non-repetitive
ID = 75 A; Vsup ≤ 55 V;
drain-source
RGS = 50 Ω; VGS = 5 V;
avalanche energy Tj(init) = 25 °C; unclamped
Dynamic characteristics
QGD
[1]
gate-drain charge VGS = 5 V; ID = 25 A;
VDS = 44 V; Tj = 25 °C;
see Figure 13
Continuous current is limited by package.
2. Pinning information
Table 2.
Pinning information
Pin
Symbol Description
1
G
gate
Simplified outline
2
D
drain[1]
3
S
source
mb
D
mounting base; connected to
drain
Graphic symbol
D
mb
G
mbb076
S
2
1
3
SOT404 (D2PAK)
[1]
It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Type number
BUK9612-55B
BUK9612-55B
Product data sheet
Package
Name
Description
D2PAK
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 4 June 2010
Version
© NXP B.V. 2010. All rights reserved.
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BUK9612-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDS
drain-source voltage
Tj ≥ 25 °C; Tj ≤ 175 °C
-
-
55
V
VDGR
drain-gate voltage
RGS = 20 kΩ
-
-
55
V
VGS
gate-source voltage
ID
drain current
-15
-
15
V
Tmb = 25 °C; VGS = 5 V;
see Figure 1; see Figure 3
[1]
-
-
75
A
[2]
-
-
79
A
Tmb = 100 °C; VGS = 5 V; see Figure 1
[2]
-
-
56
A
IDM
peak drain current
Tmb = 25 °C; tp ≤ 10 µs; pulsed;
see Figure 3
-
-
322
A
Ptot
total power dissipation
Tmb = 25 °C; see Figure 2
-
-
157
W
Tstg
storage temperature
-55
-
175
°C
Tj
junction temperature
-55
-
175
°C
[1]
-
-
75
A
[2]
-
-
79
A
tp ≤ 10 µs; pulsed; Tmb = 25 °C
-
-
322
A
ID = 75 A; Vsup ≤ 55 V; RGS = 50 Ω;
VGS = 5 V; Tj(init) = 25 °C; unclamped
-
-
172
mJ
Source-drain diode
source current
IS
peak source current
ISM
Tmb = 25 °C
Avalanche ruggedness
EDS(AL)S
non-repetitive
drain-source
avalanche energy
[1]
Continuous current is limited by package.
[2]
Current is limited by power dissipation chip rating.
BUK9612-55B
Product data sheet
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Rev. 02 — 4 June 2010
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BUK9612-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03nn10
80
03na19
120
ID
(A)
Pder
(%)
60
80
40
Capped at 75 A due to package
40
20
0
0
0
50
100
150
200
0
50
100
150
Fig 1.
200
Tmb (°C)
Tmb (°C)
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
03nn08
103
Limit RDSon = VDS/ID
ID
(A)
tp = 10 μ s
102
100 μ s
Capped at 75 A due to package
10
1 ms
DC
10 ms
100 ms
1
1
102
10
VDS (V)
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9612-55B
Product data sheet
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BUK9612-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Rth(j-mb)
thermal resistance
from junction to
mounting base
see Figure 4
-
-
0.95
K/W
Rth(j-a)
thermal resistance
from junction to
ambient
minimum footprint ; mounted on a
printed-circuit board
-
50
-
K/W
03nn09
1
δ = 0.5
Zth(j-mb)
(K/W)
10−1
0.2
0.1
0.05
0.02
10−2
δ=
P
single shot
t
tp
10−3
10−6
tp
T
T
10−5
10−4
10−3
10−2
10−1
1
tp (s)
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9612-55B
Product data sheet
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N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics
V(BR)DSS
drain-source
breakdown voltage
ID = 0.25 mA; VGS = 0 V; Tj = 25 °C
55
-
-
V
ID = 0.25 mA; VGS = 0 V; Tj = -55 °C
50
-
-
V
VGS(th)
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 175 °C;
see Figure 10
0.5
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C;
see Figure 10
-
-
2.3
V
ID = 1 mA; VDS = VGS; Tj = 25 °C;
see Figure 10
1.1
1.5
2
V
-
-
500
µA
IDSS
drain leakage current
VDS = 55 V; VGS = 0 V; Tj = 175 °C
VDS = 55 V; VGS = 0 V; Tj = 25 °C
-
0.02
1
µA
IGSS
gate leakage current
VDS = 0 V; VGS = 15 V; Tj = 25 °C
-
2
100
nA
VDS = 0 V; VGS = -15 V; Tj = 25 °C
-
2
100
nA
VGS = 5 V; ID = 25 A; Tj = 175 °C;
see Figure 11; see Figure 12
-
-
24
mΩ
VGS = 4.5 V; ID = 25 A; Tj = 25 °C
-
-
13.3
mΩ
VGS = 10 V; ID = 25 A; Tj = 25 °C
-
9
10
mΩ
VGS = 5 V; ID = 25 A; Tj = 25 °C;
see Figure 11; see Figure 12
-
10.2
12
mΩ
ID = 25 A; VDS = 44 V; VGS = 5 V;
Tj = 25 °C; see Figure 13
-
31
-
nC
-
6
-
nC
-
12
-
nC
-
2770
3693
pF
-
360
431
pF
-
160
220
pF
-
19
-
ns
-
101
-
ns
-
96
-
ns
RDSon
drain-source on-state
resistance
Dynamic characteristics
QG(tot)
total gate charge
QGS
gate-source charge
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
td(off)
turn-off delay time
tf
fall time
LD
internal drain
inductance
LS
internal source
inductance
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Tj = 25 °C; see Figure 14
VDS = 30 V; RL = 1.2 Ω; VGS = 5 V;
RG(ext) = 10 Ω; Tj = 25 °C
-
75
-
ns
from upper edge of drain mounting base
to centre of die ; Tj = 25 °C
-
2.5
-
nH
from drain lead 6 mm from package to
centre of die ; Tj = 25 °C
-
4.5
-
nH
from source lead 6 mm from package to
source bond pad ; Tj = 25 °C
-
7.5
-
nH
Source-drain diode
BUK9612-55B
Product data sheet
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Rev. 02 — 4 June 2010
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NXP Semiconductors
N-channel TrenchMOS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VSD
source-drain voltage
IS = 25 A; VGS = 0 V; Tj = 25 °C;
see Figure 15
-
0.85
1.2
V
trr
reverse recovery time
-
55
-
ns
Qr
recovered charge
IS = 20 A; dIS/dt = -100 A/µs;
VGS = -10 V; VDS = 30 V; Tj = 25 °C
-
53
-
nC
03nn05
250
RDSon
10
8
6
200
(mΩ)
5
4.8
4.6
150
15
4.4
4.2
4
3.8
3.6
3.4
3.2
3
2.8
2.6
2.4
2.2
100
50
0
0
Fig 5.
03nn04
20
Label is VGS (V)
ID
(A)
2
4
6
10
5
8
10
VDS (V)
Output characteristics: drain current as a
function of drain-source voltage; typical values
3
Fig 6.
03ng53
10−1
7
11
15
Drain-source on-state resistance as a function
of gate-source voltage; typical values
03nn02
80
ID
(A)
VGS (V)
gfs
(S)
10−2
60
min
typ
max
10−3
40
10−4
20
10−5
10−6
0
0
1
2
3
0
VGS (V)
Fig 7.
Sub-threshold drain current as a function of
gate-source voltage
BUK9612-55B
Product data sheet
Fig 8.
20
40
ID (A)
60
Forward transconductance as a function of
drain current; typical values
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BUK9612-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03nn03
100
03ng52
2.5
VGS(th)
(V)
ID
(A)
2.0
max
75
1.5
typ
50
min
1.0
25
0.5
Tj = 175 °C
Tj = 25 °C
0
0
1
2
3
4
5
VGS (V)
Fig 9.
Transfer characteristics: drain current as a
function of gate-source voltage; typical values
0
−60
3.8 4
3
3.2
3.4
3.6
RDSon
(mΩ)
20
5
60
120
180
Tj (°C)
Fig 10. Gate-source threshold voltage as a function of
junction temperature
03nn06
25
0
03ne89
2
10
a
1.5
15
1
10
0.5
Label is VGS (V)
5
0
50
100
150
200
250
0
-60
ID (A)
Fig 11. Drain-source on-state resistance as a function
of drain current; typical values
BUK9612-55B
Product data sheet
0
60
120
Tj (°C)
180
Fig 12. Normalized drain-source on-state resistance
factor as a function of junction temperature
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BUK9612-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
03nn01
5
VGS
03nn07
6000
(V)
C
(pF)
4
VDD = 14 V
VDD = 44 V
Ciss
4000
3
Coss
2
2000
Crss
1
0
0
10
20
30
QG (nC)
0
10−2
40
10−1
1
102
10
VDS (V)
Fig 13. Gate-source voltage as a function of gate
charge; typical values
Fig 14. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
03nn00
100
IS
(A)
75
50
25
Tj = 175 °C
0
0.0
0.3
0.6
Tj = 25 °C
0.9
VSD (V)
1.2
Fig 15. Source current as a function of source-drain voltage; typical values
BUK9612-55B
Product data sheet
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Rev. 02 — 4 June 2010
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N-channel TrenchMOS logic level FET
7. Package outline
SOT404
Plastic single-ended surface-mounted package (D2PAK); 3 leads (one lead cropped)
A
A1
E
mounting
base
D1
D
HD
2
Lp
1
3
c
b
e
e
Q
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
A1
b
c
D
max.
D1
E
e
Lp
HD
Q
mm
4.50
4.10
1.40
1.27
0.85
0.60
0.64
0.46
11
1.60
1.20
10.30
9.70
2.54
2.90
2.10
15.80
14.80
2.60
2.20
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-02-11
06-03-16
SOT404
Fig 16. Package outline SOT404 (D2PAK)
BUK9612-55B
Product data sheet
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Rev. 02 — 4 June 2010
© NXP B.V. 2010. All rights reserved.
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N-channel TrenchMOS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK9612-55B v.2
20100604
Product data sheet
-
BUK95_9612_55B-01
Modifications:
BUK95_9612_55B-01
(9397 750 11247)
BUK9612-55B
Product data sheet
•
The format of this data sheet has been redesigned to comply with the new identity guidelines
of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Type number BUK9612-55B separated from data sheet BUK95_9612_55B-01.
20030428
Product data
-
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 4 June 2010
-
© NXP B.V. 2010. All rights reserved.
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N-channel TrenchMOS logic level FET
9. Legal information
9.1
Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
9.3
Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
BUK9612-55B
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. The product is not designed, authorized or warranted to be
suitable for use in medical, military, aircraft, space or life support equipment,
nor in applications where failure or malfunction of an NXP Semiconductors
product can reasonably be expected to result in personal injury, death or
severe property or environmental damage. NXP Semiconductors accepts no
liability for inclusion and/or use of NXP Semiconductors products in such
equipment or applications and therefore such inclusion and/or use is at the
customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on a weakness or default in the
customer application/use or the application/use of customer’s third party
customer(s) (hereinafter both referred to as “Application”). It is customer’s
sole responsibility to check whether the NXP Semiconductors product is
suitable and fit for the Application planned. Customer has to do all necessary
testing for the Application in order to avoid a default of the Application and the
product. NXP Semiconductors does not accept any liability in this respect.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in the
Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 4 June 2010
© NXP B.V. 2010. All rights reserved.
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BUK9612-55B
NXP Semiconductors
N-channel TrenchMOS logic level FET
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
Adelante, Bitport, Bitsound, CoolFlux, CoReUse, DESFire, EZ-HV,
FabKey, GreenChip, HiPerSmart, HITAG, I²C-bus logo, ICODE, I-CODE,
ITEC, Labelution, MIFARE, MIFARE Plus, MIFARE Ultralight, MoReUse,
QLPAK, Silicon Tuner, SiliconMAX, SmartXA, STARplug, TOPFET,
TrenchMOS, TriMedia and UCODE — are trademarks of NXP B.V.
HD Radio and HD Radio logo — are trademarks of iBiquity Digital
Corporation.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BUK9612-55B
Product data sheet
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Rev. 02 — 4 June 2010
© NXP B.V. 2010. All rights reserved.
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N-channel TrenchMOS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11
Legal information. . . . . . . . . . . . . . . . . . . . . . . .12
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Contact information. . . . . . . . . . . . . . . . . . . . . .13
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2010.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 June 2010
Document identifier: BUK9612-55B