24C04A 4K 5.0V I2C™ Serial EEPROM FEATURES DIP 8-lead SOIC DESCRIPTION 14-lead SOIC This device offers fast (1ms) byte write and extended (-40°C to 125°C) temperature operation. It is recommended that all other applications use Microchip’s 24LC04B. 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA A0 1 8 VCC A1 2 7 WP A2 3 6 SCL VSS 4 5 SDA NC 1 14 NC A0 2 13 Vcc A1 3 12 WP NC 4 A2 5 24C04A The Microchip Technology Inc. 24C04A is a 4K bit Electrically Erasable PROM. The device is organized as with a standard two wire serial interface. Advanced CMOS technology allows a significant reduction in power over NMOS serial devices. A special feature provides hardware write protection for the upper half of the block. The 24C04A has a page write capability of up to eight bytes, and up to four 24C04A devices may be connected to the same two wire bus. A0 24C04A Low power CMOS technology Hardware write protect Two wire serial interface bus, I2C™ compatible 5.0V only operation Self-timed write cycle (including auto-erase) Page-write buffer 1 ms write cycle time for single byte 1,000,000 Erase/Write cycles guaranteed Data retention >200 years 8-pin DIP/SOIC packages Available for extended temperature ranges - Commercial (C): 0˚C to +70˚C - Industrial (I): -40˚C to +85˚C - Automotive (E): -40˚C to +125˚C 24C04A • • • • • • • • • • • PACKAGE TYPES 11 NC 10 SCL Vss 6 9 SDA NC 7 8 NC BLOCK DIAGRAM Vcc Vss Data Buffer (FIFO) Data Reg. SDA SCL Slave Addr. Control Logic A d d r e s s VPP R/W Amp P o i n A0 to t A7 e r Memory Array Increment A8 A0 A1 A2 WP I2C is a trademark of Philips Corporation. 1998 Microchip Technology Inc. DS11183E-page 1 24C04A 1.0 ELECTRICAL CHARACTERISTICS 1.1 Maximum Ratings* TABLE 1-1: Name A0 VCC...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V Storage temperature ..................................... -65˚C to +150˚C Ambient temp. with power applied................. -65˚C to +125˚C Soldering temperature of leads (10 seconds) ............. +300˚C ESD protection on all pins................................................4 kV A1, A2 VSS SDA SCL WP VCC *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: PIN FUNCTION TABLE Function No Function - Must be connected to VCC or VSS Chip Address Inputs Ground Serial Address/Data I/O Serial Clock Write Protect Input +5V Power Supply DC CHARACTERISTICS VCC = +5V (±10%) Commercial (C): Tamb = 0°C to +70°C Industrial (I): Tamb = -40°C to +85°C Automotive (E): Tamb = -40°C to +125°C Parameter Symbol Min. Max. Units VCC detector threshold SCL and SDA pins: High level input voltage Low level input voltage Low level output voltage A1 & A2 pins: High level input voltage Low level input voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Operating current VTH 2.8 4.5 V VIH VIL VOL VCC x 0.7 -0.3 VCC + 1 VCC x 0.3 0.4 V V V VIH VIL ILI ILO CIN, COUT ICC Write ICC Write ICC Read ICCS VCC - 0.5 -0.3 — — — VCC + 0.5 0.5 10 10 7.0 V V µA µA pF — 3.5 mA — 4.25 mA — 750 µA — 100 µA Standby current Conditions IOL = 3.2 mA (SDA only) VIN = 0V to VCC VOUT = 0V to VCC VIN/VOUT = 0V (Note) Tamb = +25˚C, f = 1 MHz FCLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = 0˚C to +70˚C FCLK = 100 kHz, program cycle time = 1 ms, Vcc = 5V, Tamb = (I) and (E) VCC = 5V, Tamb= (C), (I) and (E) SDA=SCL=VCC=5V (no PROGRAM active) WP/TEST = VSS, A0, A1, A2 = VSS Note: This parameter is periodically sampled and not 100% tested FIGURE 1-1: BUS TIMING START/STOP VHYS SCL THD:STA TSU:STA TSU:STO SDA START DS11183E-page 2 STOP 1998 Microchip Technology Inc. 24C04A TABLE 1-3: AC CHARACTERISTICS Parameter Symbol Min. Typ Max. Units Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time FCLK THIGH TLOW TR TF THD:STA — 4000 4700 — — 4000 — — — — — — 100 — — 1000 300 — kHz ns ns ns ns ns START condition setup time TSU:STA 4700 — — ns Data input hold time Data input setup time Data output delay time STOP condition setup time Bus free time THD:DAT TSU:DAT TAA TSU:STO TBUF 0 250 300 4700 4700 — — — — — — — 3500 — — ns ns TI — — 100 ns TWC — .4 .4N — 1 N — ms ms cycles Input filter time constant (SDA and SCL pins) Program cycle time Remarks After this period the first clock pulse is generated Only relevant for repeated START condition (Note 1) ns ns Time the bus must be free before a new transmission can start Byte mode Page mode, N=# of bytes Endurance — 1M 25°C, Vcc = 5.0V, Block Mode (Note 2) Note 1: As transmitter the device must provide this internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on our website. FIGURE 1-2: BUS TIMING DATA TR TF THIGH TLOW SCL TSU:STA THD:DAT TSU:DAT TSU:STO THD:STA SDA IN TSP TAA THD:STA TAA TBUF SDA OUT 1998 Microchip Technology Inc. DS11183E-page 3 24C04A 2.0 FUNCTIONAL DESCRIPTION The 24C04A supports a bidirectional two wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the START and STOP conditions, while the 24C04A works as slave. Both master and slave can operate as transmitter or receiver but the master device determines which mode is activated. Up to four 24C04As can be connected to the bus, selected by A1 and A2 chip address inputs. A0 must be tied to VCC or VSS. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 3.4 Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: The 24C04A does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to enable the master to generate the STOP condition. Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: SCL DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) (D) START CONDITION ADDRESS OR ACKNOWLEDGE VALID (D) (C) (A) SDA DS11183E-page 4 DATA ALLOWED TO CHANGE STOP CONDITION 1998 Microchip Technology Inc. 24C04A 4.0 SLAVE ADDRESS 5.0 The chip address inputs A1 and A2 must be externally connected to either VCC or ground (VSS), thereby assigning a unique address to each device. A0 is not used on the 24C04A and must be connected to either VCC or VSS. Up to four 24C04A devices may be connected to the bus. Chip selection is then accomplished through software by setting the bits A1 and A2 of the slave address to the corresponding hard-wired logic levels of the selected 24C04A. After generating a START condition, the bus master transmits the slave address consisting of a 4-bit device code (1010), followed by the chip address bits A0, A1 and A2. The seventh bit of that byte (A0) is used to select the upper block (addresses 100—1FF) or the lower block (addresses 000—0FF) of the array. BYTE PROGRAM MODE In this mode, the master sends addresses and one data byte to the 24C04A. Following the START signal from the master, the device code (4-bits), the slave address (3-bits), and the R/W bit, which is logic LOW, are placed onto the bus by the master. This indicates to the addressed 24C04A that a byte with a word address will follow after it has generated an acknowledge bit. Therefore the next byte transmitted by the master is the word address and will be written into the address pointer of the 24C04A. After receiving the acknowledge, the master device transmits the data word to be written into the addressed memory location. The 24C04A acknowledges again and the master generates a STOP condition. This initiates the internal programming cycle (Figure 6-1). The eighth bit of the slave address determines if the master device wants to read or write to the 24C04A (Figure 4-1). The 24C04A monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a programming mode. FIGURE 4-1: SLAVE ADDRESS ALLOCATION START READ/WRITE SLAVE ADDRESS 1 0 1 0 1998 Microchip Technology Inc. A2 R/W A1 A A0 DS11183E-page 5 24C04A 6.0 PAGE PROGRAM MODE as a result of only allowing the address registers bottom 3 bits to increment while the upper 5 bits remain unchanged. To program the master sends addresses and data to the 24C04A which is the slave (Figure 6-1 and Figure 6-2). This is done by supplying a START condition followed by the 4-bit device code, the 3-bit slave address, and the R/W bit which is defined as a logic LOW for a write. This indicates to the addressed slave that a word address will follow so the slave outputs the acknowledge pulse to the master during the ninth clock pulse. When the word address is received by the 24C04A, it places it in the lower 8 bits of the address pointer defining which memory location is to be written. (The A0 bit transmitted with the slave address is the ninth bit of the address pointer). The 24C04A will generate an acknowledge after every 8-bits received and store them consecutively in a RAM (8 bytes maximum) buffer until a STOP condition is detected. This STOP condition initiates the internal programming cycle.. If more than 8 bytes are transmitted by the master, the 24C04A will roll over and overwrite the data beginning with the first received byte. This does not affect erase/ write cycles of the EEPROM array and is accomplished FIGURE 6-1: S T A R T SDA LINE S CONTROL BYTE S T O P DATA P A C K A C K A C K PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE S DS11183E-page 6 The PROGRAM cycle takes N milliseconds, whereby N is the number of received data bytes. WORD ADDRESS BUS ACTIVITY BUS ACTIVITY The internal, completely self-timed PROGRAM cycle starts after the STOP condition has been generated by the master and all received data bytes in the page buffer will be written in a serial manner. BYTE WRITE BUS ACTIVITY MASTER FIGURE 6-2: If the master generates a STOP condition after transmitting the first data word (Point ‘P’ on Figure 6-1), byte programming mode is entered. WORD ADDRESS (n) CONTROL BYTE DATA n + 1 DATA n S T O P DATA n + 7 P A C K A C K A C K A C K A C K 1998 Microchip Technology Inc. 24C04A 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for flow diagram. FIGURE 7-1: 8.0 WRITE PROTECTION Programming of the upper half of the memory will not take place if the WP pin is connected to VCC (+5.0V). The device will accept slave and word addresses but if the memory accessed is write protected by the WP pin, the 24C04A will not generate an acknowledge after the first byte of data has been received, and thus the program cycle will not be started when the STOP condition is asserted. ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation 1998 Microchip Technology Inc. DS11183E-page 7 24C04A 9.0 READ MODE Note 1: If the master knows where the address pointer is, it can begin the read sequence at the current address (Figure 9-1) and save time transmitting the slave and word addresses. In this mode the 24C04A transmits data to the master devide. As can be seen from Figure 9-2 and Figure 9-3, the master first sets up the slave and word addresses by doing a write. (Note: Although this is a read mode, the address pointer must be written to). During this period the 24C04A generates the necessary acknowledge bits as defined in the appropriate section. Note 2: In all modes, the address pointer will not increment through a block (256 byte) boundary, but will rotate back to the first location in that block. The master now generates another START condition and transmits the slave address again, except this time the read/write bit is set into the read mode. After the slave generates the acknowledge bit, it then outputs the data from the addressed location on to the SDA pin, increments the address pointer and, if it receives an acknowledge from the master, will transmit the next consecutive byte. This auto-increment sequence is only aborted when the master sends a STOP condition instead of an acknowledge. FIGURE 9-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S CONTROL BYTE S T O P DATA n P N O A C K BUS ACTIVITY A C K FIGURE 9-2: RANDOM READ BUS ACTIVITY MASTER S T A R T CONTROL BYTE S T A R T WORD ADDRESS (n) S P A C K A C K BUS ACTIVITY BUS ACTIVITY MASTER S T O P DATA (n) S SDA LINE FIGURE 9-3: CONTROL BYTE A C K N O A C K SEQUENTIAL READ CONTROL BYTE DATA n DATA n + 1 DATA n + 2 S T O P DATA n + X P SDA LINE BUS ACTIVITY A C K A C K A C K A C K N O A C K DS11183E-page 8 1998 Microchip Technology Inc. 24C04A 10.0 PIN DESCRIPTION 10.4 10.1 A0, A1, A2 Chip Address Inputs This pin must be connected to either VCC or VSS. If tied to VCC, write operations to the upper memory block will not be executed. Read operations are possible. A0 is not used as a chip select bit and must be tied to either Vss or Vcc. The levels on the remaining two address inputs(A1, A2) are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. These inputs must be connected to either VSS or VCC. These two address inputs allow up to four 24C04A's can be connected to the bus 10.2 SDA Serial Address/Data Input/Output This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10KΩ). For normal data transfer, SDA is allowed to change only during SCL LOW. Changes during SCL HIGH are reserved for indicating the START and STOP conditions. 10.3 SCL Serial Clock WP Write Protection If tied to VSS, normal memory operation is enabled (read/write the entire memory). This feature allows the user to assign the upper half of the memory as ROM which can be protected against accidental programming. When write is disabled, slave address and word address will be acknowledged but data will not be acknowledged. Note 1: A “page” is defined as the maximum number of bytes that can be programmed in a single write cycle. The 24C04A page is 8 bytes long. Note 2: A “block” is defined as a continuous area of memory with distinct boundaries. The address pointer can not cross the boundary from one block to another. It will however, wrap around from the end of a block to the first location in the same block. The 24C04A has two blocks, 256 bytes each. This input is used to synchronize the data transfer from and to the device. 1998 Microchip Technology Inc. DS11183E-page 9 24C04A NOTES: DS11183E-page 10 1998 Microchip Technology Inc. 24C04A 24C04A Product Identification System To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed sales offices. 24C04A - /P Package: Temperature Range: P SN SM SL = = = = Plastic DIP Plastic SOIC (150 mil Body), 8-lead Plastic SOIC (207 mil Body), 8-lead Plastic SOIC (150 mil Body), 14-lead Blank = 0°C to +70°C = -40°C to +85°C E = -40°C to +125°C Device: 24C04A 24C04AT 4K I2C Serial EEPROM 4K I2C Serial EEPROM (Tape and Reel) Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office 2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277 3. The Microchip Worldwide Web Site (www.microchip.com) DS11183E-page 11 1998 Microchip Technology Inc. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Microchip Technology RM 406 Shanghai Golden Bridge Bldg. 2077 Yan’an Road West, Hong Qiao District Shanghai, PRC 200335 Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Italy 11/15/99 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. © 1999 Microchip Technology Incorporated. Printed in the USA. 11/99 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. 1999 Microchip Technology Inc.