2N7002K Datasheet

2N7002K
Vishay Siliconix
N-Channel 60-V (D-S) MOSFET
FEATURES
PRODUCT SUMMARY
VDS (V)
RDS(on) (Ω)
ID (mA)
60
2 at VGS = 10 V
300
TO-236
SOT-23
G
BENEFITS
1
3
S
• Halogen-free According to IEC 61249-2-21
Definition
• Low On-Resistance: 2 Ω
• Low Threshold: 2 V (typ.)
• Low Input Capacitance: 25 pF
• Fast Switching Speed: 25 ns
• Low Input and Output Leakage
• TrenchFET® Power MOSFET
• 2000 V ESD Protection
• Compliant to RoHS Directive 2002/95/EC
D
•
•
•
•
•
Low Offset Voltage
Low-Voltage Operation
Easily Driven Without Buffer
High-Speed Circuits
Low Error Voltage
2
APPLICATIONS
Top View
2N7002K (7K)*
* Marking Code
Ordering Information: 2N7002K-T1
2N7002K-T1-E3 (Lead (Pb)-free)
2N7002K-T1-GE3 (Lead (Pb)-free and Halogen-free)
• Direct Logic-Level Interface: TTL/CMOS
• Drivers: Relays, Solenoids, Lamps, Hammers, Display,
Memories, Transistors, etc.
• Battery Operated Systems
• Solid-State Relays
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted
Parameter
Symbol
Limit
Drain-Source Voltage
VDS
60
Gate-Source Voltage
VGS
± 20
Continuous Drain Current (TJ = 150 °C)b
TA = 25 °C
TA = 100 °C
Pulsed Drain Currenta
Power Dissipationb
ID
IDM
TA = 25 °C
TA = 100 °C
Maximum Junction-to-Ambientb
Operating Junction and Storage Temperature Range
PD
Unit
V
300
190
mA
800
0.35
0.14
W
RthJA
350
°C/W
TJ, Tstg
- 55 to 150
°C
Notes:
a. Pulse width limited by maximum junction temperature.
b. Surface Mounted on FR4 board.
* Pb containing terminations are not RoHS compliant, exemptions may apply.
Document Number: 71333
S09-0857-Rev. E, 18-May-09
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2N7002K
Vishay Siliconix
SPECIFICATIONS TA = 25 °C, unless otherwise noted
Limits
Parameter
Symbol
Test Conditions
Min.
VDS
VGS = 0 V, ID = 10 µA
60
VGS(th)
VDS = VGS, ID = 250 µA
1
Typ.a
Max.
Unit
Static
Drain-Source Breakdown Voltage
Gate-Threshold Voltage
Gate-Body Leakage
IGSS
Zero Gate Voltage Drain Current
IDSS
On-State Drain Currenta
ID(on)
Drain-Source On-Resistancea
Forward Transconductancea
Diode Forward Voltage
RDS(on)
2.5
VDS = 0 V, VGS = ± 20 V
± 10
VDS = 0 V, VGS = ± 15 V
1
VDS = 0 V, VGS = ± 10 V
± 150
VDS = 0 V, VGS = ± 10 V, TJ = 85 °C
± 1000
VDS = 0 V, VGS = ± 5 V
± 100
VDS = 60 V, VGS = 0 V
1
VDS = 60 V, VGS = 0 V , TJ = 125 °C
500
VGS = 10 V, VDS = 7.5 V
800
VGS = 4.5 V, VDS = 10 V
500
2
VGS = 4.5 V, ID = 200 mA
4
VDS = 10 V, ID = 200 mA
VSD
IS = 200 mA, VGS = 0 V
Qg
VDS = 10 V, VGS = 4.5 V
ID ≅ 250 mA
µA
nA
µA
mA
VGS = 10 V, ID = 500 mA
gfs
V
100
Ω
mS
1.3
V
0.6
nC
Dynamica
Total Gate Charge
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
0.4
30
VDS = 25 V, VGS = 0 V
f = 1 MHz
pF
6
2.5
Switchinga, b, c
Turn-On Time
td(on)
Turn-Off Time
td(off)
VDD = 30 V, RL = 150 Ω
ID ≅ 200 mA, VGEN = 10 V, RG = 10 Ω
25
35
ns
Notes:
a. For DESIGN AID ONLY, not subject to production testing.
b. Pulse test: PW ≤ 300 µs duty cycle ≤ 2 %.
c. Switching time is essentially independent of operating temperature.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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Document Number: 71333
S09-0857-Rev. E, 18-May-09
2N7002K
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
1.0
TJ = - 55 °C
0.8
5V
I D - Drain Current (mA)
I D - Drain Current (A)
1200
7V 6V
VGS = 10 V
0.6
4V
0.4
900
25 °C
125 °C
600
300
0.2
3V
0.0
0
0
1
2
3
4
5
0
1
2
3
Output Characteristics
Transfer Characteristics
6
40
VGS = 0 V
3.5
32
3.0
C - Capacitance (pF)
R DS(on) - On-Resistance (Ω)
5
VGS - Gate-to-Source Voltage (V)
4.0
2.5
VGS = 4.5 V
2.0
1.5
VGS = 10 V
24
Ciss
16
Coss
1.0
8
Crss
0.5
0
0.0
0
200
400
600
800
0
1000
5
ID - Drain Current (mA)
10
20
25
Capacitance
7
2.0
VGS = 10 V at 500 mA
VDS = 10 V
ID = 250 mA
5
4
3
2
(Normalized)
1.6
R DS(on) - On-Resistance
6
15
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
VGS - Gate-to-Source Voltage (V)
4
VDS - Drain-to-Source Voltage (V)
1.2
VGS = 4.5 V
at 200 mA
0.8
0.4
1
0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.0
- 50
- 25
0
25
50
75
100
125
Qg - Total Gate Charge (nC)
TJ - Junction Temperature (°C)
Gate Charge
On-Resistance vs. Junction Temperature
Document Number: 71333
S09-0857-Rev. E, 18-May-09
150
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3
2N7002K
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
5
1000
R DS(on) - On-Resistance (Ω)
I S - Source Current (A)
VGS = 0 V
100
TJ = 125 °C
10
TJ = 25 °C
4
3
ID = 200 mA
ID = 500 mA
2
1
TJ = - 55 °C
0
1
0.0
0.3
0.6
0.9
1.2
0
1.5
2
4
6
8
10
VSD - Source-to-Drain Voltage (V)
VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-Source Voltage
0.4
3
2.5
0.2
2
0.0
Power (W)
VGS(th) Variance (V)
ID = 250 µA
- 0.2
- 0.4
1.5
1
- 0.6
TA = 25 °C
0.5
- 0.8
- 50
0
- 25
0
25
50
75
100
125
150
0.01
0.1
10
1
TJ - Junction Temperature (°C)
100
600
Time (s)
Threshold Voltage Variance Over Temperature
Single Pulse Power, Junction-to-Ambient
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
Notes:
0.1
PDM
0.1
0.05
t1
t2
1. Duty Cycle, D =
t1
t2
2. Per Unit Base = R thJA = 350 °C/W
0.02
3. T JM - TA = PDMZthJA(t)
Single Pulse
4. Surface Mounted
0.01
10-4
10-3
10-2
10-1
1
10
100
600
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Ambient
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Document Number: 71333
S09-0857-Rev. E, 18-May-09
2N7002K
Vishay Siliconix
TYPICAL CHARACTERISTICS
25 °C, unless otherwise noted
Normalized Effective Transient
Thermal Impedance
2
1
Duty Cycle = 0.5
0.2
0.1
0.1
0.05
0.02
Single Pulse
0.01
10-4
10-3
10-2
10-1
1
10
Square Wave Pulse Duration (s)
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?71333.
Document Number: 71333
S09-0857-Rev. E, 18-May-09
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5
Package Information
Vishay Siliconix
SOT-23 (TO-236): 3-LEAD
b
3
E1
1
E
2
e
S
e1
D
0.10 mm
C
0.004"
A2
A
C
q
Gauge Plane
Seating Plane
Seating Plane
C
A1
Dim
0.25 mm
L
L1
MILLIMETERS
Min
INCHES
Max
Min
Max
0.044
A
0.89
1.12
0.035
A1
0.01
0.10
0.0004
0.004
A2
0.88
1.02
0.0346
0.040
b
0.35
0.50
0.014
0.020
c
0.085
0.18
0.003
0.007
D
2.80
3.04
0.110
0.120
E
2.10
2.64
0.083
0.104
E1
1.20
1.40
0.047
e
0.95 BSC
e1
L
1.90 BSC
0.40
L1
q
0.0748 Ref
0.60
0.016
0.64 Ref
S
0.024
0.025 Ref
0.50 Ref
3°
0.055
0.0374 Ref
0.020 Ref
8°
3°
8°
ECN: S-03946-Rev. K, 09-Jul-01
DWG: 5479
Document Number: 71196
09-Jul-01
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1
AN807
Vishay Siliconix
Mounting LITTLE FOOTR SOT-23 Power MOSFETs
Wharton McDaniel
Surface-mounted LITTLE FOOT power MOSFETs use integrated
circuit and small-signal packages which have been been modified
to provide the heat transfer capabilities required by power devices.
Leadframe materials and design, molding compounds, and die
attach materials have been changed, while the footprint of the
packages remains the same.
See Application Note 826, Recommended Minimum Pad
Patterns With Outline Drawing Access for Vishay Siliconix
MOSFETs, (http://www.vishay.com/doc?72286), for the basis
of the pad design for a LITTLE FOOT SOT-23 power MOSFET
footprint . In converting this footprint to the pad set for a power
device, designers must make two connections: an electrical
connection and a thermal connection, to draw heat away from the
package.
ambient air. This pattern uses all the available area underneath the
body for this purpose.
0.114
2.9
0.081
2.05
0.150
3.8
0.059
1.5
0.0394
1.0
0.037
0.95
FIGURE 1. Footprint With Copper Spreading
The electrical connections for the SOT-23 are very simple. Pin 1 is
the gate, pin 2 is the source, and pin 3 is the drain. As in the other
LITTLE FOOT packages, the drain pin serves the additional
function of providing the thermal connection from the package to
the PC board. The total cross section of a copper trace connected
to the drain may be adequate to carry the current required for the
application, but it may be inadequate thermally. Also, heat spreads
in a circular fashion from the heat source. In this case the drain pin
is the heat source when looking at heat spread on the PC board.
Figure 1 shows the footprint with copper spreading for the SOT-23
package. This pattern shows the starting point for utilizing the
board area available for the heat spreading copper. To create this
pattern, a plane of copper overlies the drain pin and provides
planar copper to draw heat from the drain lead and start the
process of spreading the heat so it can be dissipated into the
Document Number: 70739
26-Nov-03
Since surface-mounted packages are small, and reflow soldering
is the most common way in which these are affixed to the PC
board, “thermal” connections from the planar copper to the pads
have not been used. Even if additional planar copper area is used,
there should be no problems in the soldering process. The actual
solder connections are defined by the solder mask openings. By
combining the basic footprint with the copper plane on the drain
pins, the solder mask generation occurs automatically.
A final item to keep in mind is the width of the power traces. The
absolute minimum power trace width must be determined by the
amount of current it has to carry. For thermal reasons, this
minimum width should be at least 0.020 inches. The use of wide
traces connected to the drain plane provides a low-impedance
path for heat to move away from the device.
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Application Note 826
Vishay Siliconix
0.049
(1.245)
0.029
0.022
(0.559)
(0.724)
0.037
(0.950)
(2.692)
0.106
RECOMMENDED MINIMUM PADS FOR SOT-23
0.053
(1.341)
0.097
(2.459)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index Return to Index
APPLICATION NOTE
Document Number: 72609
Revision: 21-Jan-08
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Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as RoHS-Compliant fulfill the
definitions and restrictions defined under Directive 2011/65/EU of The European Parliament and of the Council
of June 8, 2011 on the restriction of the use of certain hazardous substances in electrical and electronic equipment
(EEE) - recast, unless otherwise specified as non-compliant.
Please note that some Vishay documentation may still make reference to RoHS Directive 2002/95/EC. We confirm that
all the products identified as being compliant to Directive 2002/95/EC conform to Directive 2011/65/EU.
Vishay Intertechnology, Inc. hereby certifies that all its products that are identified as Halogen-Free follow Halogen-Free
requirements as per JEDEC JS709A standards. Please note that some Vishay documentation may still make reference
to the IEC 61249-2-21 definition. We confirm that all the products identified as being compliant to IEC 61249-2-21
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Revision: 02-Oct-12
1
Document Number: 91000
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