HFA1120/883 850MHz Current Feedback Amplifier with Offset Adjust July 1994 Features Description • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. The HFA1120/883 is a high speed, wideband, fast settling current feedback amplifier. Built with Intersil’ proprietary, complementary bipolar UHF-1 process, it is the fastest monolithic amplifier available from any semiconductor manufacturer. • Low Distortion (HD3, 30MHz) . . . . . . . . . . -84dBc (Typ) • Wide -3dB Bandwidth . . . . . . . . . . . . . . . 850MHz (Typ) • Very High Slew Rate . . . . . . . . . . . . . . . 2300V/µs (Typ) • Fast Settling (0.1%) . . . . . . . . . . . . . . . . . . . . 11ns (Typ) • Excellent Gain Flatness (to 50MHz) . . . . . 0.05dB (Typ) • High Output Current . . . . . . . . . . . . . . . . . . 65mA (Typ) • Fast Overdrive Recovery. . . . . . . . . . . . . . . <10ns (Typ) Applications The HFA1120/883’s wide bandwidth, fast settling characteristic, and low output impedance, make this amplifier ideal for driving fast A/D converters. Additionally, it offers offset voltage nulling capabilities as described in the “Offset Adjustment” section of this datasheet. Component and composite video systems will also benefit from this amplifier’s performance, as indicated by the excellent gain flatness, and 0.03%/0.05 Degree Differential Gain/ Phase specifications (RL = 75Ω). Ordering Information • Video Switching and Routing • Pulse and Video Amplifiers PART NUMBER • Wideband Amplifiers • RF/IF Signal Processing HFA1120MJ/883 TEMPERATURE RANGE PACKAGE -55oC to +125oC 8 Lead CerDIP • Flash A/D Driver • Medical Imaging Systems Pinout HFA1120/883 (CERDIP) TOP VIEW BAL 1 -IN 2 +IN 3 V- 4 + 8 NC 7 V+ 6 OUT 5 BAL CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 3-199 511105-883 File Number 3617.1 Spec Number Specifications HFA1120/883 Absolute Maximum Ratings Thermal Information Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V Voltage at Either Input Terminal . . . . . . . . . . . . . . . . . . . . . . V+ to VOutput Current (50% Duty Cycle) . . . . . . . . . . . . . . . . . . . . . . . .±55mA Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC ESD Rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <2000V Storage Temperature Range . . . . . . . . . . . . . . -65oC ≤ TA ≤ +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Thermal Resistance θJA θJC CerDIP Package . . . . . . . . . . . . . . . . . . . 115oC/W 30oC/W Maximum Package Power Dissipation at +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.87W Package Power Dissipation Derating Factor above +75oC CerDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.7mW/oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Supply Voltage (±VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5V Operating Temperature Range . . . . . . . . . . . . .-55oC ≤ TA ≤ +125oC RL ≥ 50Ω TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS Device Tested at: VSUPPLY = ±5V, AV = +1, RF = 510Ω, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified. PARAMETERS Input Offset Voltage SYMBOL VIO Common Mode Rejection Ratio CMRR Power Supply Rejection Ratio PSRRP PSRRN Non-Inverting Input (+IN) Current IBSP CMSIBP +IN Resistance +RIN -IN Current Adjust Range IBSN ADJIBN -IN Current Common Mode Sensitivity CMSIBN -IN Current Power Supply Sensitivity PPSSIBN NPSSIBN Output Voltage Swing VOP100 TEMPERATURE 1 +25oC -6 6 mV 2, 3 +125oC, -55oC -10 10 mV 1 +25oC 40 - dB 2, 3 +125oC, -55oC 38 - dB 1 +25oC 45 - dB 42 - dB VCM = 0V ∆VCM = ±2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V ∆VSUP = ±1.25V V+ = 6.25V, V- = -5V V+ = 3.75V, V- = -5V 2, 3 ∆VSUP = ±1.25V V+ = 5V, V- = -6.25V V+ = 5V, V- = -3.75V VCM = 0V VON100 ∆VCM = ±2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V Note 1 VCM = 0V VCM = 0V, Note 3 ∆VCM = ±2V V+ = 3V, V- = -7V V+ = 7V, V- = -3V ∆VSUP = ±1.25V V+ = 6.25V, V- = -5V V+ = 3.75V, V- = -5V VIN = -3.5V AV = -1 RL = 100Ω VIN = +3.5V VIN = -3V -55oC MAX 45 - dB 2, 3 +125oC, -55oC 42 - dB 1 +25oC -40 40 µA -65 65 µA 1 +25oC - 40 µA/V 2, 3 +125oC, -55oC - 50 µA/V 1 +25oC 25 - kΩ 2, 3 +125oC, -55oC 20 - kΩ 1 +25oC -50 50 µA 2, 3 +125oC, -55oC -75 75 µA 1 +25oC 100 -100 µA 2, 3 +125oC, -55oC 100 -100 µA 1 +25oC - 7 µA/V 2, 3 +125oC, -55oC - 10 µA/V 1 +25oC - 15 µA/V - 27 µA/V +125oC, +125oC, -55oC -55oC 1 +25oC - 15 µA/V 2, 3 +125oC, -55oC - 27 µA/V 1 +25oC 3 - V 2.5 - V - -3 V - -2.5 V 1 2, 3 +125oC, -55oC +25oC +125oC, -55oC Spec Number 3-200 UNITS +25oC 2, 3 VIN = +3V +125oC, MIN 1 2, 3 ∆VSUP = ±1.25V V+ = 5V, V- = -6.25V V+ = 5V, V- = -3.75V AV = -1 RL = 100Ω LIMITS GROUP A SUBGROUPS 2, 3 +IN Current Common Mode Sensitivity Inverting Input (-IN) Current CONDITIONS 511105-883 Specifications HFA1120/883 TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Tested at: VSUPPLY = ±5V, AV = +1, RF = 510Ω, RSOURCE = 0Ω, RL = 100Ω, VOUT = 0V, Unless Otherwise Specified. PARAMETERS Output Voltage Swing SYMBOL AV = -1 RL = 50Ω VON50 Output Current TEMPERATURE MIN MAX UNITS 1, 2 +25oC, +125oC 2.5 - V VIN = -2V 3 -55oC 1.5 - V VIN = +3V 1, 2 +25oC, +125oC - -2.5 V VIN = +2V 3 - -1.5 V 50 - mA 30 - mA - -50 mA 3 -55oC - -30 mA 1 +25oC 14 26 mA CONDITIONS VOP50 VIN = -3V AV = -1 RL = 50Ω +IOUT Note 2 -55oC +25oC, 1, 2 Quiescent Power Supply Current Note 2 ICC +25oC, 1, 2 RL = 100Ω RL = 100Ω +125oC +125oC, 2, 3 IEE +125oC -55oC 3 -IOUT LIMITS GROUP A SUBGROUPS -55oC - 33 mA 1 +25oC -26 -14 mA 2, 3 +125oC, -55oC -33 - mA NOTES: 1. Guaranteed from +IN Common Mode Rejection Test, by: +RIN = 1/CMSIBP . 2. Guaranteed from VOUT Test with RL = 50Ω, by: IOUT = VOUT/50Ω. 3. This is the minimum change in inverting input bias current when a BAL pin is connected to V- through a 50Ω resistor. TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS Table 2 Intentionally Left Blank. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = ±5V, AV = +2, RF = 360Ω, RL = 100Ω, Unless Otherwise Specified. LIMITS PARAMETERS -3dB Bandwidth Gain Flatness Slew Rate Rise and Fall Time SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 300 - MHz BW(-1) AV = -1, RF = 430Ω VOUT = 200mVP-P 1 +25oC BW(+1) AV = +1, RF = 510Ω VOUT = 200mVP-P 1 +25oC 550 - MHz BW(+2) AV = +2, VOUT = 200mVP-P 1 +25oC 350 - MHz GF30 AV = +2, RF = 510Ω, f ≤30MHz VOUT = 200mVP-P 1 +25oC - ±0.04 dB GF50 AV = +2, RF = 510Ω, f ≤50MHz VOUT = 200mVP-P 1 +25oC - ±0.10 dB GF100 AV = +2, RF = 510Ω, f ≤100MHz VOUT = 200mVP-P 1 +25oC - ±0.30 dB +SR(+1) AV = +1, RF = 510Ω VOUT = 5VP-P 1, 2 +25oC 1200 - V/µs -SR(+1) AV = +1, RF = 510Ω VOUT = 5VP-P 1, 2 +25oC 1100 - V/µs +SR(+2) AV = +2, VOUT = 5VP-P 1, 2 +25oC 1650 - V/µs -SR(+2) AV = +2, VOUT = 5VP-P 1, 2 +25oC 1500 - V/µs - 1 ns - 1 ns TR AV = +2, VOUT = 0.5VP-P 1, 2 +25oC TF AV = +2, VOUT = 0.5VP-P 1, 2 +25oC Spec Number 3-201 511105-883 Specifications HFA1120/883 TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = ±5V, AV = +2, RF = 360Ω, RL = 100Ω, Unless Otherwise Specified. LIMITS PARAMETERS SYMBOL Overshoot Settling Time 2nd Harmonic Distortion 3rd Harmonic Distortion CONDITIONS +OS AV = +2, VOUT = 0.5VP-P NOTES TEMPERATURE MIN MAX UNITS 1, 3 +25oC - 25 % -OS AV = +2, VOUT = 0.5VP-P 1, 3 +25oC - 20 % TS(0.1) AV = +2, RF = 510Ω VOUT = 2V to 0V, to 0.1% 1 +25oC - 20 ns TS(0.05) AV = +2, RF = 510Ω VOUT = 2V to 0V, to 0.05% 1 +25oC - 33 ns HD2(30) AV = +2, f = 30MHz VOUT = 2VP-P 1 +25oC - -48 dBc HD2(50) AV = +2, f = 50MHz VOUT = 2VP-P 1 +25oC - -45 dBc HD2(100) AV = +2, f = 100MHz VOUT = 2VP-P 1 +25oC - -35 dBc HD3(30) AV = +2, f = 30MHz VOUT = 2VP-P 1 +25oC - -65 dBc HD3(50) AV = +2, f = 50MHz VOUT = 2VP-P 1 +25oC - -60 dBc HD3(100) AV = +2, f = 100MHz VOUT = 2VP-P 1 +25oC - -40 dBc NOTES: 1. Parameters listed in Table 3 are controlled via design or process parameters and are not directly tested at final production. These parameters are lab characterized upon initial design release, or upon design changes. These parameters are guaranteed by characterization based upon data from multiple production runs which reflect lot-to-lot and within lot variation. 2. Measured between 10% and 90% points. 3. For 200ps input transition times. Overshoot decreases as input transition times increase, especially for AV = +1. Please refer to Performance Curves. TABLE 4. ELECTRICAL TEST REQUIREMENTS MIL-STD-883 TEST REQUIREMENTS SUBGROUPS (SEE TABLE 1) Interim Electrical Parameters (Pre Burn-In) 1 Final Electrical Test Parameters 1 (Note 1), 2, 3 Group A Test Requirements 1, 2, 3 Groups C and D Endpoints 1 NOTE: 1. PDA applies to Subgroup 1 only. Spec Number 3-202 511105-883 HFA1120/883 Die Characteristics DIE DIMENSIONS: 63 x 44 x 19 mils ± 1 mils 1600 x 1130 x 483µm ± 25.4µm METALLIZATION: Type: Metal 1: AICu(2%)/TiW Thickness: Metal 1: 8kÅ ± 0.4kÅ Type: Metal 2: AICu(2%) Thickness: Metal 2: 16kÅ ± 0.8kÅ GLASSIVATION: Type: Nitride Thickness: 4kÅ ± 0.5kÅ WORST CASE CURRENT DENSITY: 2.0 x 105 A/cm2 at 47.5mA TRANSISTOR COUNT: 52 SUBSTRATE POTENTIAL (Powered Up): Floating (Recommend Connection to V-) Metallization Mask Layout HFA1120/883 +IN -IN V- BAL VL VH BAL V+ OUT Spec Number 3-203 511105-883 HFA1120/883 Test Circuit (Applies to Table 1) V+ + ICC 10 0.1 510 VIN K1 NC K2 = POSITION 1: VX VIO = 100 7 2 + - VX 510 0.1 100 0.1 0.1 0.1 470pF 2 - 510 x100 K2 K2 = POSITION 2: VX -IBIAS = 50K 1 1K 6 VOUT DUT 3 + 510 1 100 5 4 100 50 50 K5 200pF VZ +IBIAS = 100K 100K (0.01%) + 10 NC NC 0.1 K4 K3 + VZ IEE 0.1 0.1 0.1 HA-5177 NOTE: All Resistors = ±1% (Ω) All Capacitors = ±10% (µF) Unless Otherwise Noted Chip Components Recommended V- Test Waveforms SIMPLIFIED TEST CIRCUIT FOR LARGE AND SMALL SIGNAL PULSE RESPONSE (Applies to Table 3) AV = +1 TEST CIRCUIT AV = +2 TEST CIRCUIT V+ VIN RS 50Ω V+ VOUT + - 50Ω RF VIN 2 RS 50Ω 50Ω VOUT + - RF 50Ω 360Ω 510Ω V- V- LARGE SIGNAL WAVEFORM SMALL SIGNAL WAVEFORM VOUT VOUT 90% 90% +SR -2.5V RG 360Ω NOTE: VS = ±5V, AV = +2 RS = 50Ω RL=100Ω For Small and Large Signals NOTE: VS = ±5V, AV = +1 RS = 50Ω RL = 100Ω For Small and Large Signals +2.5V 2 50Ω +2.5V +250mV -SR 10% 10% 90% 90% TR , +OS -2.5V -250mV TF , -OS 10% 10% Spec Number 3-204 +250mV -250mV 511105-883 HFA1120/883 Burn-In Circuit HFA1120MJ/883 CERAMIC DIP R3 R2 1 8 2 7 R1 3 D4 4 VD2 + 6 D3 V+ C1 D1 5 C2 NOTES: R1 = R2 = 1kΩ, ±5% (Per Socket) R3 = 10kΩ, ±5% (Per Socket) C1 = C2 = 0.01µF (Per Socket) or 0.1µF (Per Row) Minimum D1 = D2 = 1N4002 or Equivalent (Per Board) D3 = D4 = 1N4002 or Equivalent (Per Socket) V+ = +5.5V ± 0.5V V- = -5.5V ± 0.5V Spec Number 3-205 511105-883 HFA1120/883 Packaging c1 LEAD FINISH F8.3A MIL-STD-1835 GDIP1-T8 (D-4, CONFIGURATION A) 8 LEAD DUAL-IN-LINE FRIT-SEAL CERAMIC PACKAGE -D- -A- BASE METAL -Bbbb S C A-B S MIN MAX MIN MAX b1 A - 0.200 - 5.08 - M (b) b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 SECTION A-A D S D BASE PLANE Q -C- SEATING PLANE A α L S1 eA A A b2 e b ccc M C A-B S D S eA/2 MILLIMETERS SYMBOL E M INCHES (c) c aaa M C A - B S D S NOTES: 1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark. 2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied. 3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness. NOTES c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 D - 0.405 - 10.29 5 E 0.220 0.310 5.59 7.87 5 e 0.100 BSC 2.54 BSC eA 0.300 BSC 7.62 BSC - eA/2 0.150 BSC 3.81 BSC - L 0.125 0.200 3.18 5.08 - Q 0.015 0.060 0.38 1.52 6 S1 0.005 - 0.13 - 7 S2 0.005 - 0.13 - - α 90o 105o 90o 105o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - M - 0.0015 - N 8 0.038 8 2 8 4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b1. 5. This dimension allows for off-center lid, meniscus, and glass overrun. 6. Dimension Q shall be measured from the seating plane to the base plane. 7. Measure dimension S1 at all four corners. 8. N is the maximum number of terminal positions. 9. Dimensioning and tolerancing per ANSI Y14.5M - 1982. 10. Controlling Dimension: Inch 11. Lead Finish: Type A. 12. Materials: Compliant to MIL-I-38535. Spec Number 3-206 511105-883 HFA1120 Semiconductor DESIGN INFORMATION Ultra High Speed Current Feedback Amplifier with Offset Adjust August 1999 The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, RL = 100Ω, TA = +25°C, Unless Otherwise Specified LARGE SIGNAL PULSE RESPONSE (AV = +2) 120 1.2 90 0.9 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (mV) SMALL SIGNAL PULSE RESPONSE (AV = +2) 60 30 0 -30 -60 0.6 0.3 0 -0.3 -0.6 -0.9 -90 -1.2 -120 5ns/DIV 5ns/DIV NON-INVERTING FREQUENCY RESPONSE (VOUT = 200mVP-P) -6 AV = +2 -9 AV = +6 AV = +11 PHASE 0 -90 AV = +1 AV = +2 -180 AV = +6 -270 1 10 100 FREQUENCY (MHz) AV = -5 -6 AV = -10 -9 AV = -20 -12 PHASE 180 AV = -1 90 AV = -5 0 AV = -10 AV = -20 AV = +11 0.3 AV = -1 -3 GAIN (dB) NORMALIZED AV = +1 PHASE (DEGREES) -3 -12 GAIN 0 -360 0.3 1K 1 10 100 FREQUENCY (MHz) Spec Number 3-207 PHASE (DEGREES) GAIN 0 GAIN (dB) NORMALIZED INVERTING FREQUENCY RESPONSE (VOUT = 200mVP-P) -90 -180 1K 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, RL = 100Ω, TA = +25°C, Unless Otherwise Specified FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS (AV = +1, VOUT = 200mVP-P) FREQUENCY RESPONSE FOR VARIOUS LOAD RESISTORS (AV = +2, VOUT = 200mVP-P) +6 GAIN (dB) NORMALIZED GAIN (dB) RL = 100Ω -3 RL = 50Ω -6 PHASE RL = 50Ω RL = 100Ω 0 -90 RL = 1kΩ PHASE (DEGREES) GAIN 0 RL = 1kΩ +3 GAIN 0 -3 RL = 100Ω RL = 50Ω -6 PHASE 0 RL = 50Ω RL = 100Ω -90 RL = 1kΩ -180 -180 RL = 100Ω 0.3 1 -360 10 100 FREQUENCY (MHz) 1K 0.3 FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES (AV = +1) +10 +10 GAIN (dB) NORMALIZED +20 GAIN (dB) 0 0.160VP-P 0.500VP-P 0.920VP-P 1.63VP-P -20 -30 0.3 1 10 100 FREQUENCY (MHz) 1 10 100 FREQUENCY (MHz) -360 1K FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES (AV = +2) +20 -10 -270 RL = 100Ω RL = 1kΩ -270 RL = 1kΩ PHASE (DEGREES) RL = 1kΩ +3 0 FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGES (AV = +6) 1.00VP-P -20 1.84VP-P -30 0.3 1K 0.32VP-P -10 3.26VP-P 1 10 100 FREQUENCY (MHz) 1K -3dB BANDWIDTH vs TEMPERATURE (AV = +1) +10 950 BANDWIDTH (MHz) GAIN (dB) NORMALIZED +20 0 -10 0.96 VP-P -20 TO 3.89 VP-P -30 900 850 800 750 700 0.3 1 10 FREQUENCY (MHz) 100 -50 1K -25 0 +25 +50 +75 +100 +125 TEMPERATURE (oC) Spec Number 3-208 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, RL = 100Ω, TA = +25°C, Unless Otherwise Specified GAIN FLATNESS (AV = +2) DEVIATION FROM LINEAR PHASE (AV = +2) +2.0 DEVIATION (DEGREES) +1.5 GAIN (dB) 0 -0.05 -0.10 -0.15 -0.20 +1.0 +0.5 0 -0.5 -1.0 -1.5 -2.0 1 10 FREQUENCY (MHz) 0 100 SETTLING RESPONSE (AV = +2, VOUT = 2V) 30 45 60 75 90 105 120 FREQUENCY (MHz) 135 150 3rd ORDER INTERMODULATION INTERCEPT (2-TONE) INTERCEPT POINT (dBm) 40 0.6 SETTLING ERROR (%) 15 0.4 0.2 0 -0.2 -0.4 35 30 25 20 15 10 5 -0.6 0 0 -4 1 6 11 16 21 26 TIME (ns) 31 36 41 200 300 FREQUENCY (MHz) 46 2nd HARMONIC DISTORTION vs POUT 400 3rd HARMONIC DISTORTION vs POUT -30 -30 -35 -40 -50 -40 100MHz DISTORTION (dBc) DISTORTION (dBc) 100 -45 50MHz -50 -55 -60 100MHz -60 -70 50MHz -80 -90 30MHz 30MHz -100 -65 -110 -70 -5 -3 -1 1 5 7 9 3 OUTPUT POWER (dBm) 11 13 -5 15 -3 -1 1 3 5 7 9 11 13 15 OUTPUT POWER (dBm) Spec Number 3-209 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, RL = 100Ω, TA = +25°C, Unless Otherwise Specified OVERSHOOT vs INPUT RISE TIME (AV = +2) 35 RF = 360Ω VOUT = 2VP-P 30 VOUT = 1VP-P OVERSHOOT (%) VOUT = 0.5VP-P VOUT = 2VP-P 25 15 RF = 510Ω VOUT = 2VP-P 10 5 RF =510Ω VOUT = 1VP-P RF = 510Ω VOUT = 0.5VP-P 0 200 100 300 400 500 600 700 800 900 100 1000 200 300 INPUT RISE TIME (ps) 500 600 700 800 900 1000 SUPPLY CURRENT vs TEMPERATURE 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 25 24 SUPPLY CURRENT (mA) OVERSHOOT (%) 400 INPUT RISE TIME (ps) OVERSHOOT vs FEEDBACK RESISTOR (AV = +2, tR = 200ps, VOUT = 2VP-P) 23 22 21 20 19 18 360 400 440 480 520 560 600 640 -60 680 -40 -20 SUPPLY CURRENT vs SUPPLY VOLTAGE INPUT OFFSET VOLTAGE (mV) 6 7 8 9 TOTAL SUPPLY VOLTAGE (V+ - V-, V) +20 +40 +60 +80 +100 +120 VIO AND BIAS CURRENTS vs TEMPERATURE 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 5 0 TEMPERATURE (oC) FEEDBACK RESISTOR (Ω) SUPPLY CURRENT (mA) RF = 360Ω VOUT = 1VP-P RF = 360Ω 20 VOUT = 0.5VP-P 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 1.7 1.6 1.5 1.4 1.3 +IBIAS VIO -IBIAS -60 10 -40 -20 0 +20 +40 +60 +80 +100 +120 TEMPERATURE (oC) Spec Number 3-210 45 42 39 36 33 30 27 24 21 18 15 12 9 6 3 0 BIAS CURRENTS (µA) OVERSHOOT (%) OVERSHOOT vs INPUT RISE TIME (AV = +1) 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Typical Performance Curves VSUPPLY = ±5V, RF = 510Ω, RL = 100Ω, TA = +25°C, Unless Otherwise Specified OUTPUT VOLTAGE vs TEMPERATURE (AV = -1, RL = 50Ω) INPUT NOISE vs FREQUENCY 3.7 30 300 3.4 3.3 3.2 | - VOUT | 3.1 3 2.9 2.8 2.7 25 250 225 20 200 175 150 15 125 10 100 75 5 ENI eni INIiniINI+ ini+ 2.6 0 100 2.5 -60 -40 -20 0 +20 +40 +60 +80 +100 +120 1K 10K NOISE CURRENT (pA/√Hz) 275 +VOUT 3.5 NOISE VOLTAGE (nV/√Hz) OUTPUT VOLTAGE (V) 3.6 50 25 0 100K FREQUENCY (Hz) TEMPERATURE (oC) Spec Number 3-211 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. Application Information Optimum Feedback Resistor The enclosed plots of inverting and non-inverting frequency response illustrate the performance of the HFA1120 in various gains. Although the bandwidth dependency on closed loop gain isn’t as severe as that of a voltage feedback amplifier, there can be an appreciable decrease in bandwidth at higher gains. This decrease may be minimized by taking advantage of the current feedback amplifier’s unique relationship between bandwidth and RF . All current feedback amplifiers require a feedback resistor, even for unity gain applications, and RF , in conjunction with the internal compensation capacitor, sets the dominant pole of the frequency response. Thus, the amplifier’s bandwidth is inversely proportional to RF . The HFA1120 design is optimized for a 510Ω RF at a gain of +1. Decreasing RF in a unity gain application decreases stability, resulting in excessive peaking and overshoot. At higher gains the amplifier is more stable, so RF can be decreased in a tradeoff of stability for bandwidth. The table below lists recommended RF values for various gains, and the expected bandwidth. GAIN (ACL) RF (Ω) BANDWIDTH (MHz) -1 430 580 +1 510 850 +2 360 670 +5 150 520 +10 180 240 +19 270 125 in pulse overshoot and possible instability. To this end, it is recommended that the ground plane be removed under traces connected to -IN, and connections to -IN should be kept as short as possible. An example of a good high frequency layout is the Evaluation Board shown in Figure 2. Driving Capacitive Loads Capacitive loads, such as an A/D input, or an improperly terminated transmission line will degrade the amplifier’s phase margin resulting in frequency response peaking and possible oscillations. In most cases, the oscillation can be avoided by placing a resistor (RS) in series with the output prior to the capacitance. Figure 1 details starting points for the selection of this resistor. The points on the curve indicate the RS and CL combinations for the optimum bandwidth, stability, and settling time, but experimental fine tuning is recommended. Picking a point above or to the right of the curve yields an overdamped response, while points below or left of the curve indicate areas of underdamped performance. RS and CL form a low pass network at the output, thus limiting system bandwidth well below the amplifier bandwidth of 850MHz. By decreasing RS as CLincreases (as illustrated in the curves), the maximum bandwidth is obtained without sacrificing stability. Even so, bandwidth does decrease as you move to the right along the curve. For example, at AV = +1, RS = 50Ω, CL = 30pF, the overall bandwidth is limited to 300MHz, and bandwidth drops to 100MHz at AV = +1, RS = 5Ω, CL = 340pF. 50 45 AV = +1 40 PC Board Layout The frequency response of this amplifier depends greatly on the amount of care taken in designing the PC board. The use of low inductance components such as chip resistors and chip capacitors is strongly recommended, while a solid ground plane is a must! RS (Ω) 35 Care must also be taken to minimize the capacitance to ground seen by the amplifier’s inverting input (-IN). The larger this capacitance, the worse the gain peaking, resulting 25 20 15 10 5 A = +2 V 0 0 Attention should be given to decoupling the power supplies. A large value (10µF) tantalum in parallel with a small value (0.1µF) chip capacitor works well in most cases. Terminated microstrip signal lines are recommended at the input and output of the device. Capacitance directly on the output must be minimized, or isolated as discussed in the next section. 30 40 80 120 160 200 240 280 320 360 400 LOAD CAPACITANCE (pF) FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs LOAD CAPACITANCE Evaluation Board The performance of the HFA1120 may be evaluated using the HFA11XX Evaluation Board. Spec Number 3-212 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. The layout and schematic of the board are shown in Figure 2. To order evaluation boards, please contact your local sales office. TOP LAYOUT VH Offset Adjustment 1 The output offset voltage of the HFA1120 may be nulled via connections to the BAL pins. Unlike a voltage feedback amplifier, offset adjustment is accomplished by varying the sign and/or magnitude of the inverting input bias current (-IBIAS). With voltage feedback amplifiers, bias currents are matched and bias current induced offset errors are nulled by matching the impedances seen at the positive and negative inputs. Bias currents are uncorrelated on current feedback amplifiers, so this technique is inappropriate. +IN OUT V+ VL VGND BOTTOM LAYOUT -IBIAS flows through RF causing an output offset error. Likewise, any change in -IBIAS forces a corresponding change in output voltage, providing the capability for output offset adjustment. By nulling -IBIAS to zero, the offset error due to this current is eliminated. In addition, an adjustment limit greater than the -IBIAS limit allows the user to null the contributions from other error sources, such as VIO, or +IN source impedance. For example, the excess adjust current of 50µA (IBNADJ min. - IBSN max.) allows for the nulling of an additional 26mV of output offset error (with RF = 510Ω) at room temperature. The amount of adjustment is a function of RF , so adjust range increases with increased RF . If allowed by other considerations, such as bandwidth and noise, RF can be increased to provide more adjustment range. 500 500 VH R1 50Ω The recommended offset adjustment circuit is shown in Figure 3. IN 10µF 1 8 2 7 10µF 0.1µF +5V 50Ω 3 6 4 5 OUT GND 0.1µF VL GND -5V FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT 510 2 VIN - 6 HFA1120 3 + 5 1 4 10k VOUT V- FIGURE 3. OFFSET VOLTAGE ADJUSTMENT CIRCUIT Spec Number 3-213 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. TYPICAL PERFORMANCE CHARACTERISTICS Device Characterized at: VSUPPLY = ±5V, RF = 360Ω, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified PARAMETERS CONDITIONS TEMPERATURE TYPICAL UNITS +25oC 2 mV Full 10 µV/oC Input Offset Voltage* VCM = 0V Average Offset Voltage Drift Versus Temperature VIO CMRR ∆VCM = ±2V +25oC 46 dB VIO PSRR ∆VS = ±1.25V +25oC 50 dB +Input Current* VCM = 0V +25oC 25 µA Average +Input Current Drift Versus Temperature Full 40 nA/oC -Input Current* VCM = 0V +25oC 12 µA Average -Input Current Drift Versus Temperature Full 40 nA/oC -Input Current Adjust Range VCM = 0V +25oC ±200 µA +Input Resistance ∆VCM = ±2V +25oC 50 kΩ -Input Resistance +25oC 16 Ω Input Capacitance +25oC 2.2 pF f = 100kHz +25oC 4 nV/√Hz +Input Noise Current* f = 100kHz +25oC 18 pA/√Hz -Input Noise Current* f = 100kHz +25oC 21 pA/√Hz Full ±3.0 V AV = -1 +25oC 500 kΩ AV = -1, RL = 100Ω +25oC ±3.3 V Full ±3.0 V ±65 mA -55oC to 0oC ±50 mA +25oC 0.1 Ω Full 24 mA AV = -1, RF = 430Ω, VOUT = 200mVP-P +25oC 580 MHz AV = +1, RF = 510Ω, VOUT = 200mVP-P +25oC 850 MHz AV = +2, RF = 360Ω, VOUT = 200mVP-P +25oC 670 MHz AV = +1, RF = 510Ω, VOUT = 5VP-P +25oC 1500 V/µs AV = +2, VOUT = 5VP-P +25oC 2300 V/µs VOUT = 5VP-P +25oC 220 MHz Input Noise Voltage* Input Common Mode Range Open Loop Transimpedance Output Voltage AV = -1, RL = 100Ω Output Current* +25oC AV = -1, RL = 50Ω AV = -1, RL = 50Ω DC Closed Loop Output Resistance Quiescent Supply Current* -3dB Bandwidth* Slew Rate Full Power Bandwidth RL = Open to +125oC Spec Number 3-214 511105-883 HFA1120 DESIGN INFORMATION (Continued) The information contained in this section has been developed through characterization by Intersil Semiconductor and is for use as application and design information only. No guarantee is implied. TYPICAL PERFORMANCE CHARACTERISTICS (Continued) Device Characterized at: VSUPPLY = ±5V, RF = 360Ω, AV = +2V/V, RL = 100Ω, Unless Otherwise Specified PARAMETERS TEMPERATURE TYPICAL UNITS To 30MHz, RF = 510Ω +25oC ±0.014 dB To 50MHz, RF = 510Ω +25oC ±0.05 dB To 100MHz, RF = 510Ω +25oC ±0.14 dB Linear Phase Deviation* To 100MHz, RF = 510Ω +25oC ±0.6 Degrees 2nd Harmonic Distortion* 30MHz, VOUT = 2VP-P +25oC -55 dBc 50MHz, VOUT = 2VP-P +25oC -49 dBc 100MHz, VOUT = 2VP-P +25oC -44 dBc 30MHz, VOUT = 2VP-P +25oC -84 dBc 50MHz, VOUT = 2VP-P +25oC -70 dBc 100MHz, VOUT = 2VP-P +25oC -57 dBc 100MHz, RF = 510Ω +25oC 30 dBm 1dB Compression 100MHz, RF = 510Ω +25oC 20 dBm Reverse Isolation (S12) 40MHz, RF = 510Ω +25oC -70 dB 100MHz, RF = 510Ω +25oC -60 dB 600MHz, RF = 510Ω +25oC -32 dB VOUT = 0.5VP-P +25oC 500 ps VOUT = 2VP-P +25oC 800 ps Overshoot* VOUT = 0.5VP-P, Input tR/tF = 550ps +25oC 11 % Settling Time* To 0.1%, VOUT = 2V to 0V, RF = 510Ω +25oC 11 ns To 0.05%, VOUT = 2V to 0V, RF = 510Ω +25oC 19 ns To 0.02%, VOUT = 2V to 0V, RF = 510Ω +25oC 34 ns Differential Gain AV = +2, RL = 75Ω, NTSC +25oC 0.03 % Differential Phase AV = +2, RL = 75Ω, NTSC +25oC 0.05 Degrees RF = 510Ω, VIN = 5VP-P +25oC 7.5 ns Gain Flatness* 3rd Harmonic Distortion* 3rd Order Intercept* Rise & Fall Time Overdrive Recovery Time CONDITIONS * See Typical Performance Curve for more information. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Spec Number 3-215 511105-883