IDT 9LPRS525AGLFT

DATASHEET
56-pin CK505 for Intel Systems
ICS9LPRS525
Recommended Application:
56-pin CK505 compatible clock, w/fully integrated Vreg and series
resistors on differential outputs
Features/Benefits:
•
Supports spread spectrum modulation, 0 to -0.5% down
spread
•
Supports CPU clks up to 400MHz
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Output Features:
•
2 - CPU differential low power push-pull pairs
•
7 - SRC differential push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull pair
•
1 - SRC/DOT selectable differential low power push-pull pair
•
1 - SRC/SE selectable differential push-pull pair/Single-ended
outputs
•
5 - PCI, 33MHz
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Table 1: CPU Frequency Select Table
2
1
FS LB
B0b6
0
0
1
1
0
0
1
1
FSLC
B0b7
0
0
0
0
1
1
1
1
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 100ppm frequency accuracy on all outputs
•
SRC outputs meet PCIe Gen2 when sourced from PLL3
1
FSLA
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
SRC
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
PCI
MHz
REF
MHz
USB DOT
MHz MHz
33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3/CFG0
PCI4/SRC5_EN
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96IO
DOTT_96_LRS/SRCT0_LRS
DOTC_96_LRS/SRCC0_LRS
GND
VDD
SRCT1_LRS/SE1
SRCC1_LRS/SE2
GND
VDDPLL3IO
SRCT2_LRS/SATAT_LRS
SRCC2_LRS/SATAC_LRS
GNDSRC
SRCT3_LRS/CR#_C
SRCC3_LRS/CR#_D
VDDSRCIO
SRCT4_LRS
SRCC4_LRS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 SCLK
9LPRS525
PCI0/CR#_A 1
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
SDATA
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0_LRS
CPUC0_LRS
GNDCPU
CPUT1_F_LRS
CPUC1_F_LRS
VDDCPUIO
NC
CPUT2_ITP_LRS/SRCT8_LRS
CPUC2_ITP_LRS/SRCC8_LRS
VDDSRCIO
SRCT7_LRS/CR#_F
SRCC7_LRS/CR#_E
GNDSRC
SRCT6_LRS
SRCC6_LRS
VDDSRC
PCI_STOP#/SRCT5_LRS
CPU_STOP#/SRCC5_LRS
56-SSOP & TSSOP
IDTTM PC MAIN CLOCK
1484B—01/21/10
1
ICS9LPRS525
PC MAIN CLOCK
Pin Description
PIN #
PIN NAME
1
PCI0/CR#_A
2
VDDPCI
TYPE
I/O
PWR
DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before
configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRA#_EN bit located in byte 5 of
SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CRA# enabled. Byte 5, bit 6 controls whether CRA# controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CRA# controls SRC0 pair (default),
1= CRA# controls SRC2 pair
Power supply for PCI clocks, nominal 3.3V
3
PCI1/CR#_B
I/O
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before
configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is
disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRB#_EN bit located in byte 5 of
SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CRB# enabled. Byte 5, bit 6 controls whether CRB# controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CRB# controls SRC1 pair (default)
1= CRB# controls SRC4 pair
4
PCI2/TME
I/O
3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows
0=Overclocking of CPU and SRC allowed
1=Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
5
PCI3/CFG0
I/O
3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information
6
PCI4/SRC5_EN
I/O
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if the SRC5 pair is
enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on pins 29 and 30 as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
7
PCI_F5/ITP_EN
I/O
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of
this pin determines whether pins 38 and 39 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
8
GNDPCI
PWR
Ground pin for the PCI outputs
9
VDD48
PWR
10
USB_48MHz/FSLA
11
GND48
PWR
Power pin for the 48MHz output and PLL.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock
output. 3.3V.
Ground pin for the 48MHz outputs
12
VDD96IO
PWR
13
DOTT_96_LRS/SRCT0_LRS
OUT
14
DOTC_96_LRS/SRCC0_LRS
OUT
15
GND
PWR
16
VDD
PWR
17
SRCT1_LRS/SE1
OUT
18
SRCC1_LRS/SE2
OUT
19
GND
PWR
Power supply, nominal 3.3V
True clock of low power differential SRC1 clock pair with integrated 33 ohm Rs. / 3.3V single-ended output. The powerup default is 100 MHz SRC, 0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of low powerl differential SRC1 clock pair with integrated 33 ohm Rs / 3.3V single-ended output. The powerup default is 100 MHz
SRC, -0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Ground pin.
20
VDDPLL3IO
PWR
Power supply for PLL3 outputs. 1.05V to 3.3V.
21
SRCT2_LRS/SATAT_LRS
OUT
True clock of low power differentiall SRC/SATA clock pair with integrated Rs.
22
SRCC2_LRS/SATAC_LRS
OUT
Complement clock of low power differential push-pull SRC/SATA clock pair with integrated 33 ohm Rs.
23
GNDSRC
PWR
Ground pin for the SRC outputs
24
SRCT3_LRS/CR#_C
I/O
I/O
Power supply for DOT96 outputs, 1.05V to 3.3V.
True clock of low power differential SRC or DOT96 with integrated 33 ohm Rs. The power-up default function is SRC0. After powerup, this pin function
may be changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of low power differential SRC or DOT96 with integrated 33 ohm Rs. The power-up default function is SRC0#. After powerup, this
pin function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
Ground pin.
True clock of low power differential SRC clock pair with integrated 33 ohm Rs./ Clock Request control C for either SRC0 or SRC2 pair. The power-up
default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this
pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CRC#_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRCCLK3 enabled (default)
1= CRC# enabled. Byte 5, bit 2 controls whether CRC# controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CRC# controls SRC0 pair (default),
1= CRC# controls SRC2 pair
IDTTM PC MAIN CLOCK
1484B—01/21/10
2
ICS9LPRS525
PC MAIN CLOCK
Pin Description (continued)
PIN #
25
PIN NAME
SRCC3_LRS/CR#_D
TYPE
I/O
PWR
DESCRIPTION
Complementary clock of low power differential SRC clock pair with integrated 33 ohm Rs/ Clock Request control D for either SRC1 or SRC4 pair.
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before
configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is
disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CRD# controls SRC1 pair (default),
1= CRD# controls SRC4 pair
Power supply for SRC outputs. 1.05V to 3.3V.
26
VDDSRCIO
27
SRCT4_LRS
OUT
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
28
SRCC4_LRS
OUT
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
Stops all CPUCLK, except those set to be free running clocks /
Complement clock of low power differential SRC pair with 33 ohm integrated Rs.
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of low power differential SRC pair
with integrated 33 ohm Rs.
Supply for SRC PLL, 3.3V nominal
29
CPU_STOP#/SRCC5_LRS
I/O
30
PCI_STOP#/SRCT5_LRS
I/O
31
VDDSRC
32
SRCC6_LRS
OUT
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
33
SRCT6_LRS
OUT
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
34
GNDSRC
PWR
35
SRCC7_LRS/CR#_E
I/O
36
SRCT7_LRS/CR#_F
I/O
37
VDDSRCIO
PWR
38
CPUC2_ITP_LRS/SRCC8_LRS
OUT
39
CPUT2_ITP_LRS/SRCT8_LRS
OUT
Ground pin for the SRC outputs
Complement clock of differential push-pull SRC clock pair with 33 ohm integrated Rs. / Clock Request control E for SRC6 pair. The power-up default
is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CRE# enabled.
True clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock
Request Pin, the SR
Power supply for SRC outputs. 1.05V to 3.3V.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
40
NC
N/A
No Connect
41
VDDCPUIO
PWR
Power supply for CPU outputs, 1.05V to 3.3V.
PWR
42
CPUC1_F_LRS
OUT
Complementary clock of low power differential push-pull CPU output with integrated 33 ohm Rs. This CPU clock is free running during iAMT.
43
CPUT1_F_LRS
OUT
True clock of differential push-pull CPU clock pair with integrated 33 ohm Rs. This clock is free running during iAMT.
44
GNDCPU
PWR
Ground pin for the CPU outputs
45
CPUC0_LRS
OUT
Complement clock of low power differential CPU clock pair with integrated 33 ohm Rs.
46
47
CPUT0_LRS
VDDCPU
OUT
PWR
True clock of low power differential CPU clock pair with integrated 33 ohm Rs.
Supply for CPU PLL, 3.3V nominal
48
CK_PWRGD/PD#
IN
49
FSLB/TEST_MODE
IN
50
GNDREF
PWR
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.
Ground pin for the REF outputs.
51
X2
OUT
Crystal output, Nominally 14.318MHz
52
X1
IN
53
VDDREF
PWR
Crystal input, Nominally 14.318MHz.
54
REF0/FSLC/TEST_SEL
I/O
55
SDATA
I/O
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
/TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table
Data pin for SMBus circuitry, 5V tolerant.
56
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
IDTTM PC MAIN CLOCK
1484B—01/21/10
3
ICS9LPRS525
PC MAIN CLOCK
General Description
ICS9LPRS525 is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop
chipsets. ICS9LPRS525 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express
support.
Block Diagram
X1
X2
REF
REF
OSC
CPU(1:0)
SRC8/ITP
CPU
CPU PLL1
SS
SRC
SRC(7:3)
SRC_MAIN
PCI33MHz
SRC
PLL3
SS
PCI(5:0)
PCI33MHz
SRC2/SATA
FSLA
CKPWRGD/PD#
PCI_STOP#
SRC1/SE(2:1)
CPU_STOP#
CR#_(A:F)
SRC5_EN
Control
Logic
Differential Output
ITP_EN
SE Outputs
7
FSLC/TESTSEL
FSLB/TESTMODE
SRC0/DOT96
SATA
PLL2
Non-SS
DOT96MHz
48MHz
48MHz
Power Groups
Pin Number
VDD
GND
41, 47
44
16
15
Description
CPUCLK
Master Clock, Analog
26, 31, 37
23, 34
SRCCLK
20
19
PLL3/SE
12
9
53
2
11
11
50
8
DOT 96Mhz
USB 48
Xtal, REF
PCICLK
IDTTM PC MAIN CLOCK
1484B—01/21/10
4
ICS9LPRS525
PC MAIN CLOCK
Absolute Maximum Ratings - DC Parameters
PARAMETER
Maximum Supply Voltage
Maximum Supply Voltage
Maximum Input Voltage
Minimum Input Voltage
Storage Temperature
Input ESD protection
1
SYMBOL
VDDxxx
VDDxxx_IO
V IH
V IL
Ts
ESD prot
CONDITIONS
Supply Voltage
Low-Voltage Differential I/O Supply
3.3V Inputs
Any Input
Human Body Model
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
UNITS
V
V
V
V
°
C
V
Notes
7
7
4,5,7
4,7
4,7
6,7
Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied, nor guaranteed.
3
Maximum input voltage is not to exceed VDD
Electrical C haracteristics - Input/S upply/C ommon Output D C Parameters
P ARAME TE R
A m bient Operating Tem p
S upply V oltage
S upply V oltage
Input High V oltage
Input Low V oltage
Low Threshold Input- High V oltage
Low Thres hold Input- FS C = '1'
V oltage
Low Threshold Input- FS A ,FSB = '1'
V oltage
Low Threshold Input-Low V oltage
P CI3/CFG0 Input
P CI3/CFG0 Input
P CI3/CFG0 Input
Input Leakage Current
S Y MBOL
Tam bient
V DDxx x
V DDxx x_IO
V IHSE
V I LSE
V I H_FS_TEST
CONDITIONS
S upply V oltage
Low-V oltage Differential I/O S upply
S ingle-ended 3.3V inputs
S ingle-ended 3.3V inputs
3.3 V + /-5%
MIN
0
3.135
0.9975
2
V SS - 0.3
2
V I H_FS_FSC
3.3 V + /-5%
0.7
1.5
V
V I H_FS_FSAB
3.3 V + /-5%
0.7
V DD+0.3
V
V I L_FS
V IL_CFGHI
V I L_CFGMI D
V I L_CFGLO
I IN
V SS - 0.3
2.4
1.3
V SS - 0.3
-5
0.35
V DD+0.3
2
0.9
5
V
V
V
V
uA
Input Leakage Current
I INRES
-200
200
uA
Output High V oltage
Output Low V oltage
V OHSE
V OLSE
3.3 V + /-5%
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
V I N = V DD , V I N = GND
Inputs with pull up or pull down res is tors
V I N = V DD , V I N = GND
S ingle-ended outputs, I OH = -1m A
S ingle-ended outputs, I OL = 1 m A
Full A c tiv e, C L = Full load; Idd 3.3V
Full A ctive, C L = Full load; IDD IO
M 1 mode, 3.3V Rail
M1 Mode, IO Rail
P ower down mode, 3.3V Rail
P ower down m ode, IO Rail
V DD = 3.3 V
Logic Inputs
Output pin c apac itanc e
X 1 & X2 pins
From VDD P ower-Up or de-ass ertion of PD to 1st
c loc k
Output stop after CR deass erted
Output run after CR as serted
CP U output enable after
P CI_S TOP # de-as sertion
1.5
0.4
115
55
36
10
5
0.1
15
7
5
6
6
V
V
mA
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
1.8
ms
400
0
ns
us
10
ns
10
10
5.5
0.4
ns
ns
V
V
mA
1000
ns
300
ns
100
k Hz
33
k Hz
Operating S upply Current
iA M T M ode Current
P owerdown Current
Input Frequency
P in Inductanc e
Input Capac itanc e
I DDOP3.3
I DDOPI O
I DDiAMT3.3
I DDiAMTIO
I DDPD3.3
I DDPDI O
Fi
L pin
CI N
C OUT
C I NX
Clk S tabiliz ation
T STAB
Tdrive_CR_off
Tdrive_CR_on
T DRCROFF
T DRCRON
Tdriv e_CPU
T DRSRC
Tfall_S E
Tris e_S E
S M B us Voltage
Low-lev el Output V oltage
Current sinking at V OLSMB = 0.4 V
S CLK /S DA TA
Cloc k/Data Ris e Time
S CLK /S DA TA
Clock /Data Fall Time
M ax im um S M B us Operating
Frequency
S pread Spec trum M odulation
Frequency
T FALL
T RI SE
V DD
V OLSMB
I PULLUP
T RI 2C
T FI 2C
2.4
Fall/rise time of all 3.3V c ontrol inputs from 20-80%
2.7
@ I PULLUP
S M B Data P in
(Max V IL - 0.15) to
(M in V IH + 0.15)
(Min V IH + 0.15) to
(Max V IL - 0.15)
4
F SMBUS
f SSMOD
Triangular Modulation
IDTTM PC MAIN CLOCK
MAX
UNITS
70
°C
3.465
V
3.465
V
V DD + 0.3
V
0.8
V
V DD + 0.3
V
30
Notes
10
3
3
8
8
9, 10
9, 10
9, 10
2
1
1
10
10
1484B—01/21/10
5
ICS9LPRS525
PC MAIN CLOCK
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
Signal is required to be monotonic in this region.
2
input leakage current does not include inputs with pull-up or pull-down resistors
3
3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.
4
Intentionally blank
Maximum VIH is not to exceed VDD
5
6
Human Body Model
7
Operation under these conditions is neither implied, nor guaranteed.
8
Frequency Select pins which have tri-level input
9
PCI3/CFG0 is optional
10
If present. Not all parts have this feature.
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
Rising Edge Slew Rate
Falling Edge Slew Rate
Slew Rate Variation
Differential Voltage Swing
Crossing Point Voltage
Crossing Point Variation
Maximum Output Voltage
Minimum Output Voltage
Duty Cycle
CPU[1:0] Skew
CPU[2_ITP:0] Skew
SRC[10:0] Skew
SYMBOL
tSLR
tFLR
tSLVAR
VSWING
VXABS
VXABSVAR
VHIGH
VLOW
DCYC
CPUSKEW10
CPUSKEW20
SRCSKEW
CONDITIONS
Averaging on
Averaging on
Averaging on
Averaging off
Averaging off
Averaging off
Averaging off
Averaging off
Averaging on
Differential Measurement
Differential Measurement
Differential Measurement
MIN
2.5
2.5
300
300
-300
45
MAX
4
4
20
550
140
1150
55
100
150
3000
UNITS NOTES
V/ns
2, 3
V/ns
2, 3
%
1, 10
mV
2
mV
1,4,5
mV
1,4,9
mV
1,7
mV
1,8
%
2
ps
1
ps
1
ps
1,6
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
Measurement taken for single ended waveform on a component test board (not in system)
2
Measurement taken from differential waveform on a component test board. (not in system)
3
Slew rate emastured through V_swing voltage range centered about differential zero
4
Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)
Only applies to the differential rising edge (Clock rising, Clock# falling)
5
6
Total distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps.
7
The max voltage including overshoot.
8
The min voltage including undershoot.
9
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross
induced modulation by setting C_cross_delta to be smaller than V_Cross absolute
10
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising
meets Clock# falling. The median cross point is used to calculate the voltage
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER
CPU Jitter - Cycle to Cycle
SRC Jitter - Cycle to Cycle
DOT Jitter - Cycle to Cycle
SYMBOL
CPUJC2C
SRCJC2C
DOTJC2C
CONDITIONS
Differential Measurement
Differential Measurement
Differential Measurement
MIN
MAX
85
125
250
UNITS NOTES
ps
1
ps
1
ps
1
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance
will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver
IDTTM PC MAIN CLOCK
1484B—01/21/10
6
ICS9LPRS525
PC MAIN CLOCK
Differential Clock Tolerances
PPM tolerance
Cycle to Cycle Jitter
Spread
CPU
100
85
-0.50%
SRC
100
125
-0.50%
DOT96
100
250
0
BMC133
100
125
-0.50%
ppm
ps
%
Clock Periods - Differential Outputs with Spread Spectrum Disabled
SSC OFF
CPU
SRC/SATA
DOT96
Center
Freq.
MHz
100.00
133.33
166.67
200.00
266.67
333.33
400.00
100.00
96.00
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
- ppm
+ ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
Period
AbsPer
Average
Average
Average
Min
Nominal
Max
Min
Min
9.91400
9.99900
10.00000
10.00100
7.41425
7.49925
7.50000
7.50075
5.91440
5.99940
6.00000
6.00060
4.91450
4.99950
5.00000
5.00050
3.66462
3.74962
3.75000
3.75037
2.91470
2.99970
3.00000
3.00030
2.41475
2.49975
2.50000
2.50025
9.87400
9.99900
10.00000
10.00100
10.16563
10.41563
10.41667
10.41771
1 Clock
1us
+SSC
Short-Term
Average
Max
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.08600
7.58575
6.08560
5.08550
3.83537
3.08530
2.58525
10.12600
10.66771
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
Clock Periods - Differential Outputs with Spread Spectrum Enabled
SSC ON
CPU
SRC
Center
Freq.
MHz
99.75
133.00
166.25
199.50
266.00
332.50
399.00
99.75
Measurement Window
1us
0.1s
0.1s
0.1s
-SSC
- ppm
+ ppm
-c2c jitter
0 ppm
Short-Term Long-Term
Long-Term
AbsPer
Period
Average
Average
Average
Min
Nominal
Min
Min
Max
9.91406
9.99906
10.02406
10.02506
10.02607
7.41430
7.49930
7.51805
7.51880
7.51955
5.91444
5.99944
6.01444
6.01504
6.01564
4.91453
4.99953
5.01203
5.01253
5.01303
3.66465
3.74965
3.75902
3.75940
3.75977
2.91472
2.99972
3.00722
3.00752
3.00782
2.41477
2.49977
2.50602
2.50627
2.50652
9.87406
9.99906
10.02406
10.02506
10.02607
1 Clock
1us
+SSC
Short-Term
Average
Max
10.05107
7.53830
6.03064
5.02553
3.76915
3.01532
2.51277
10.05107
1 Clock
+c2c jitter Units Notes
AbsPer
Max
10.13607
7.62330
6.11564
5.11053
3.85415
3.10032
2.59777
10.17607
ns
ns
ns
ns
ns
ns
ns
ns
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
Guaranteed by design and characterization, not 100% tested in production.
All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
2
IDTTM PC MAIN CLOCK
1484B—01/21/10
7
ICS9LPRS525
PC MAIN CLOCK
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
Long Accuracy
SYMBOL
ppm
Clock period
Tperiod
Absolute min/max period
Tabs
Output High Voltage
Output Low Voltage
V OH
V OL
Output High Current
I OH
Output Low Current
I OL
Rising Edge Slew Rate
Falling Edge Slew Rate
Pin to Pin Skew
Intential PCI to PCI delay
Duty Cycle
Jitter, Cycle to cycle
t SLR
t FLR
tskew
tskew
dt1
t jcyc-cyc
CONDITIONS
see Tperiod min-max values
33.33MHz output no spread
33.33MHz output spread
33.33MHz output no spread
33.33MHz output nominal/spread
I OH = -1 mA
I OL = 1 mA
V OH @MIN = 1.0 V
[email protected] = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
VT = 1.5 V
MIN
-100
29.99700
30.08421
29.49700
29.56617
2.4
-33
30
1
1
100
45
MAX
UNITS NOTES
100
ppm
1,2
30.00300
ns
2
30.23459
ns
2
30.50300
ns
2
30.58421
ns
2
V
1
0.55
V
1
mA
1
-33
mA
1
mA
1
38
mA
1
4
V/ns
1
4
V/ns
1
250
ps
2
200
ps
2
55
%
2
500
ps
2
Intentional PCI Clock to Clock Delay
200 ps nominal steps
PCI0
PCI1
PCI2
PCI3
PCI4
PCI_F5
1.0ns
Electrical Characteristics - USB48MHz
PARAMETER
Long Accuracy
Clock period
Absolute min/max period
CLK High Time
CLK Low time
Output High Voltage
Output Low Voltage
SYMBOL
ppm
Tperiod
Tabs
THIGH
TLOW
V OH
V OL
Output High Current
I OH
Output Low Current
I OL
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter, Cycle to cycle
t SLR
t FLR
dt1
t jcyc-cyc
CONDITIONS
see Tperiod min-max values
48.00MHz output nominal
48.00MHz output nominal
I OH = -1 mA
I OL = 1 mA
V OH @MIN = 1.0 V
[email protected] = 3.135 V
VOL @ MIN = 1.95 V
VOL @ MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
VT = 1.5 V
VT = 1.5 V
IDTTM PC MAIN CLOCK
MIN
-100
20.83125
20.48125
8.216563
7.816563
2.4
-29
29
1
1
45
MAX
UNITS NOTES
100
ppm
2,4
20.83542
ns
2,3
21.18542
ns
2
11.15198
V
10.95198
V
V
0.55
V
mA
-23
mA
mA
27
mA
2
V/ns
1
2
V/ns
1
55
%
2
350
ps
2
1484B—01/21/10
8
ICS9LPRS525
PC MAIN CLOCK
Electrical Characteristics - REF-14.318MHz
PARAMETER
Long Accuracy
Clock period
Absolute min/max period
CLK High Time
CLK Low time
Output High Voltage
Output Low Voltage
SYMBOL
ppm
Tperiod
Tabs
THIGH
TLOW
VOH
VOL
Output High Current
IOH
Output Low Current
IOL
Rising Edge Slew Rate
Falling Edge Slew Rate
Duty Cycle
Jitter, Cycle to cycle
tSLR
tFLR
dt1
tjcyc-cyc
CONDITIONS
see Tperiod min-max values
14.318MHz output nominal
14.318MHz output nominal
IOH = -1 mA
IOL = 1 mA
VOH @MIN = 1.0 V,
[email protected] = 3.135 V
VOL @MIN = 1.95 V,
VOL @MAX = 0.4 V
Measured from 0.8 to 2.0 V
Measured from 2.0 to 0.8 V
VT = 1.5 V
VT = 1.5 V
MIN
-100
69.82033
69.83400
29.97543
29.57543
2.4
MAX
UNITS Notes
100
ppm
2, 4
69.86224
ns
2, 3
70.84800
ns
2
38.46654
V
38.26654
V
V
0.4
V
-33
-33
mA
30
38
mA
1
1
45
4
4
55
1000
V/ns
V/ns
%
ps
1
1
2
2
NOTES on SE outputs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1
Edge rate in system is measured from 0.8V to 2.0V.
2
Duty cycle, Peroid and Jitter are measured with respect to 1.5V
3
The average period over any 1us period of time
4
Using frequency counter with the measurment interval equal or greater that 0.15s, target frequencies are 14.318180 MHz, 33.333333MHz and 48.000000MHz
IDTTM PC MAIN CLOCK
1484B—01/21/10
9
ICS9LPRS525
PC MAIN CLOCK
Table 1: CPU Frequency Select Table
2
FSLC
B0b7
0
0
0
0
1
1
1
1
1
FSLB
B0b6
0
0
1
1
0
0
1
1
1
FSLA
B0b5
0
1
0
1
0
1
0
1
CPU
MHz
SRC
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
100.00
PCI
MHz
REF
MHz
USB DOT
MHz MHz
33.33 14.318 48.00 96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Table 2: PLL3 Quick Configuration (only applies in Mode 0, see Table 6)
Spread
Pin 17 Pin 18
B1b4 B1b3 B1b2 B1b1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
MHz
100.00
100.00
100.00
100.00
100.00
100.00
N/A
24.576
24.576
98.304
27.000
25.000
N/A
N/A
N/A
MHz
100.00
100.00
100.00
100.00
100.00
100.00
N/A
24.576
98.304
98.304
27.000
25.000
N/A
N/A
N/A
Comment
%
PLL 3 disabled
0.5% Down Spread
SRC clocks from SRC_MAIN
0.5% Down Spread
Only SRCCLK1 from PLL3
1% Down Spread
Only SRCCLK1 from PLL3
1.5% Down Spread
Only SRCCLK1 from PLL3
2% Down Spread
Only SRCCLK1 from PLL3
2.5% Down Spread
Only SRCCLK1 from PLL3
N/A
N/A
None
24.576Mhz on SE1 and SE2
None
24.576Mhz on SE1, 98.304Mhz on SE2
None
98.304Mhz on SE1 and SE2
None
27Mhz on SE1 and SE2
None
25Mhz on SE1 and SE2
N/A
N/A
N/A
N/A
N/A
N/A
IDTTM PC MAIN CLOCK
1484B—01/21/10
10
ICS9LPRS525
PC MAIN CLOCK
Table 3: IO_Vout select table
B9b2
B9b1
B9b0
IO_Vout
0
0
0
0.3V
0
0
1
0.4V
0
1
0
0.5V
0
1
1
0.6V
1
0
0
0.7V
1
0
1
0.8V
1
1
0
0.9V
1
1
1
1.0V
Table 4: Device ID table
B8b7
B8b6
B8b5
B8b4
Comment
0
0
0
0
56 pin TSSOP
Table 5: Slew Rate Selection Table
Bit 1
Bit 0
Slew Rate
0
0
1
1
0
1
0
1
HI-Z
0.7X (1.4V/ns)
0.8X (1.6 V/ns)
1X (2.0 V/ns)
Table 6. PCI3 Configuration Table
Note: 2 bits are needed since
CFG0 is tri-level input
SRC_Main_SE
PCI3/CFG0 PCI2/TME
PCI3_CFG1
PCI3_CFG0
L
HW Strap
HW Strap (Byte 11, bit 7) (Byte 11, bit 6) (Byte 0, bit 2) Config Mode
Low
0 or 1
0
0
0
0 = Default
Mid
0 or 1
0
1
1
1
High
TME=0
1
0
1
2
High
TME=1
1
1
1
3
Table 7. PLL Modes for PCI3 Configurations
PLL1
PLL2
Config
Mode
Outputs
SSC
Outputs
SSC
CPU/SRC/
0 = Default
PCI
Down
USB
NA
1
CPU
Down
USB
NA
2
CPU
Center
USB
NA
3
CPU
Center
USB/LAN25
NA
*Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
PLL3
Outputs
SSC
SRC/PCI
SRC/PCI
SRC/PCI
Down
Down
Down
SRC1
PLL Source
PLL1
(Table 2
applies)
100MHz
100MHz
PLL3
100MHz
PLL3
25MHz SE
PLL2*
Table 8. ME Clock Selection Table
PCIF5/
ITP_EN
iAMT_EN CPU2_AMT_EN CPU1_AMT_EN
Description
x
1
0
0
Reserved
x
1
0
1
Default, CPU1 = iAMT Clock
1
1
1
0
CPU2 = iAMT Clock
1
1
1
1
CPU1 and CPU2 both run in iAMT mode
IDTTM PC MAIN CLOCK
1484B—01/21/10
11
ICS9LPRS525
PC MAIN CLOCK
PCI_STOP# Power Management
Differential Clocks
(Except CPU)
Stoppable
Free running
Stoppable
Free running
Running
Running
Running
Running
CK= High
Running
CK# = Low
Low
Low
CK= Pull down
Running
CK# = Low
Low
CK= Pull down, CK# = Low
Single-ended Clocks
SMBus OE Bit
PCI_STOP#
1
Enable
0
Disable
X
CPU_STOP# Power Management
SMBus OE Bit
PCI_STOP#
1
Enable
0
Disable
X
Differential Clocks
Stoppable
Free running
Running
Running
CK= High
CK# = Low
CK= Pull down
CK# = Low
Low
Running
Running
CR# Power Management
SMBus OE Bit
CR#
1
0
X
Enable
Disable
Differential Clocks
Stoppable
Free running
Running
Running
CK= Pull down, CK# = Low
CK = Pull down, CK# = Low
PD# Power Management
Differential Clocks
(Except CPU1)
CPU1
Latches Open
CK= Pull down, CK# = Low
CK= Pull down, CK# = Low
Power Down
CK= Pull down
CK# = Low
CK= Pull down
CK# = Low
M1
CK= Pull down
CK# = Low
Running
Virtual Power Cycle
to Latches Open
CK= Pull down, CK# = Low
CK= Pull down, CK# = Low
Single-ended Clocks
Device State
w/o Latched input w/Latched input
Low
Hi-Z
IDTTM PC MAIN CLOCK
1484B—01/21/10
12
ICS9LPRS525
PC MAIN CLOCK
General SMBus serial interface information for the ICS9LPRS525
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Index Block Read Operation
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
IDTTM PC MAIN CLOCK
Not acknowledge
stoP bit
1484B—01/21/10
13
ICS9LPRS525
PC MAIN CLOCK
Byte 0 FS Readback and PLL Selection Register
Bit
7
6
5
Pin
-
Name
FSLC
FSLB
FSLA
4
-
iAMT_EN
3
Reserved
Description
Type
0
1
Default
CPU Freq. Sel. Bit (Most Significant)
Latch
R
See Table 1 : CPU Frequency Select
CPU Freq. Sel. Bit
Latch
R
Table
Latch
CPU Freq. Sel. Bit (Least Significant)
R
Set via SMBus or dynamically by CK505 if detects
RW
Legacy Mode
iAMT Enabled
0
dynamic M1
Reserved
RW
0
2
-
SRC_Main_SEL
Select source for SRC Main
1
-
SATA_SEL
Select source for SATA clock
0
-
PD_Restore
RW SRC Main = PLL1 SRC Main = PLL3 Latch
RW
SATA =
SRC_Main
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold powerConfiguration Not
RW
on and go to latches open state
Saved
This bit is ignored and treated at '1' if device is in
iAMT mode.
SATA = PLL2
0
Configuration
Saved
1
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit
7
6
5
4
3
2
1
Pin
13/14
-
0
Name
SRC0_SEL
PLL1_SSC_SEL
PLL3_SSC_SEL
PLL3_CF3
PLL3_CF2
PLL3_CF1
PLL3_CF0
Description
Select SRC0 or DOT96
Select 0.5% down or center SSC
Select 0.5% down or center SSC
PLL3 Quick Config Bit 3
PLL3 Quick Config Bit 2
PLL3 Quick Config Bit 1
PLL3 Quick Config Bit 0
Type
RW
RW
RW
RW
RW
RW
RW
0
SRC0
Down spread
Down spread
1
DOT96
Center spread
Center spread
PCI_SEL
PCI_SEL
RW
PCI from PLL1
PCI from
SRC_MAIN
1
Description
Output enable for REF, if disabled output is tristated
Output enable for USB
Output enable for PCI5
Output enable for PCI4
Output enable for PCI3
Output enable for PCI2
Output enable for PCI1
Output enable for PCI0
Type
0
1
Default
RW
Output Disabled
Output Enabled
1
RW
RW
RW
RW
RW
RW
RW
Output
Output
Output
Output
Output
Output
Output
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Output
Output
Output
Output
Output
Output
Output
1
1
1
1
1
1
1
Description
Reserved
Reserved
Reserved
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Output enable for SRC5
Output enable for SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
Output
Output
Output
Output
Output
0
Disabled
Disabled
Disabled
Disabled
Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
See Table 2: PLL3 Quick
Configuration
Only applies if Byte 0, bit 2 = 0.
Default
0
Latch
0
0
0
0
1
Byte 2 Output Enable Register
Bit
Pin
Name
7
REF_OE
6
5
4
3
2
1
0
USB_OE
PCIF5_OE
PCI4_OE
PCI3_OE
PCI2_OE
PCI1_OE
PCI0_OE
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Byte 3 Output Enable Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
Reserved
Reserved
Reserved
SRC8/ITP_OE
SRC7_OE
SRC6_OE
SRC5_OE
SRC4_OE
IDTTM PC MAIN CLOCK
Default
1
1
1
1
1
1
1
1
1484B—01/21/10
14
ICS9LPRS525
PC MAIN CLOCK
Byte 4 Output Enable and Spread Spectrum Disable Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
SRC3_OE
SATA/SRC2_OE
SRC1_OE
SRC0/DOT96_OE
CPU1_OE
CPU0_OE
PLL1_SSC_ON
PLL3_SSC_ON
Description
Output enable for SRC3
Output enable for SATA/SRC2
Output enable for SRC1
Output enable for SRC0/DOT96
Output enable for CPU1
Output enable for CPU0
Enable PLL1's spread modulation
Enable PLL3's spread modulation
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Spread Disabled
Spread Disabled
1
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Spread Enabled
Spread Enabled
Default
1
1
1
1
1
1
1
1
Type
0
1
Default
RW
Disable CR#_A
Enable CR#_A
0
RW
RW
RW
RW
RW
RW
RW
CR#_A -> SRC0
Disable CR#_B
CR#_B -> SRC1
Disable CR#_C
CR#_C -> SRC0
Disable CR#_D
CR#_D -> SRC1
CR#_A -> SRC2
Enable CR#_B
CR#_B -> SRC4
Enable CR#_C
CR#_C -> SRC2
Enable CR#_D
CR#_D -> SRC4
0
0
0
0
0
0
0
1
Enable CR#_E
Enable CR#_F
Stops with
PCI_STOP#
assertion
Stops with
PCI_STOP#
assertion
Default
0
0
0
0
0
0
1
Default
X
X
X
X
0
0
0
1
Byte 5 Clock Request Enable/Configuration Register
Bit
Pin
Name
7
CR#_A_EN
6
5
4
3
2
1
0
CR#_A_SEL
CR#_B_EN
CR#_B_SEL
CR#_C_EN
CR#_C_SEL
CR#_D_EN
CR#_D_SEL
Description
Enable CR#_A (clk req),
PCI0_OE must be = 1 for this bit to take effect
Sets CR#_A to control either SRC0 or SRC2
Enable CR#_B (clk req)
Sets CR#_B -> SRC1 or SRC4
Enable CR#_C (clk req)
Sets CR#_C -> SRC0 or SRC2
Enable CR#_D (clk req)
Sets CR#_D -> SRC1 or SRC4
Byte 6 Clock Request Enable/Configuration and Stop Control Register
Bit
7
6
5
4
3
2
Pin
Name
CR#_E_EN
CR#_F_EN
Reserved
Reserved
Reserved
Reserved
Description
Enable CR#_E (clk req) -> SRC6
Enable CR#_F (clk req) -> SRC8
Reserved
Reserved
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
0
Disable CR#_E
Disable CR#_F
-
1
SSCD_STP_CRTL
(SRC1)
If set, SSCD (SRC1) stops with PCI_STOP#
RW
Free Running
0
SRC_STP_CRTL
If set, SRCs (except SRC1) stop with PCI_STOP#
RW
Free Running
Type
R
R
R
R
R
R
R
R
0
0
0
Byte 7 Vendor ID/ Revision ID
Bit
7
6
5
4
3
2
1
0
Pin
Name
Rev Code Bit
Rev Code Bit
Rev Code Bit
Rev Code Bit
Vendor ID bit
Vendor ID bit
Vendor ID bit
Vendor ID bit
Description
3
2
1
0
3
2
1
0
Revision ID
Vendor ID
ICS is 0001, binary
IDTTM PC MAIN CLOCK
Vendor specific
1484B—01/21/10
15
ICS9LPRS525
PC MAIN CLOCK
Byte 8 Device ID and Output Enable Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
Device_ID3
Device_ID2
Device_ID1
Device_ID0
Reserved
Reserved
SE1_OE
SE2_OE
Description
Reserved
Reserved
Output enable for SE1
Output enable for SE2
Type
R
R
R
R
RW
RW
RW
RW
Disabled
Disabled
Name
Description
Type
0
7
PCIF5 STOP EN
Allows control of PCIF5 with assertion of
PCI_STOP#
RW
6
5
4
TME_Readback
REF Strength
Test Mode Select
3
Test Mode Entry
2
1
0
IO_VOUT2
IO_VOUT1
IO_VOUT0
Table of Device identifier codes, used for
differentiating between CK505 package options,
etc.
0
1
56-pin device
Enabled
Enabled
Default
0
0
0
0
0
0
0
0
Byte 9 Output Control Register
Bit
Pin
Truested Mode Enable (TME) strap status
Sets the REF output drive strength
Allows test select, ignores REF/FSC/TestSel
Allows entry into test mode, ignores
FSB/TestMode
IO Output Voltage Select (Most Significant Bit)
IO Output Voltage Select
IO Output Voltage Select (Least Significant Bit)
R
RW
RW
1
Default
Stops with
Free running
PCI_STOP#
0
assertion
normal operation no overclocking Latch
1X (2Loads)
2X (3 Loads)
1
Outputs HI-Z
Outputs = REF/N
0
RW
Normal operation
Name
Description
Type
7
SRC5_EN Readback
Readback of SRC5 enable latch
R
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
Reserved
Reserved
CPU 1 Stop Enable
CPU 0 Stop Enable
RW
RW
RW
Test mode
See Table 3: V_IO Selection
(Default is 0.8V)
0
1
0
1
Byte 10 Stop Enable Register
Bit
Pin
Reserved
Enables control of CPU1 with CPU_STOP#
Enables control of CPU 0 with CPU_STOP#
RW
RW
RW
RW
RW
RW
RW
0
CPU/PCI Stop
Enabled
Free Running
Free Running
1
Default
SRC5 Enabled
Latch
Stoppable
Stoppable
0
0
0
0
0
1
1
1
Byte 11 iAMT Enable Register
Bit
7
6
5
4
Pin
Name
PCI3_CFG1
PCI3_CFG0
Reserved
Reserved
Description
See PCI3 Configuration Table 28
3
CPU2_AMT_EN
2
CPU1_AMT_EN
Reserved
Reserved
Determines if CPU2 runs in M1 mode.
Only valid if ITP_EN=1. See Note.
Determines if CPU1 runs in M1 mode. See Note.
1
PCI-E_GEN2
Determines if PCI-E Gen2 compliant
Type
R
R
RW
RW
-
-
Default
Latch
Latch
0
1
RW
Does not Run
Runs
0
RW
Does not Run
1
R
non-Gen2
Runs
PCI-E Gen2
Compliant
Stoppable
0
CPU 2 Stop Enable
Enables control of CPU 0 with CPU_STOP#
RW
NOTE: A value of '00' for Bit(3:2) in Byte 11 is reserved and not a valid configuration.
IDTTM PC MAIN CLOCK
0
See PCI3 Configuration Table
Free Running
1
1
1484B—01/21/10
16
ICS9LPRS525
PC MAIN CLOCK
Byte 12 Byte Count Register
Bit
7
6
5
4
3
2
1
0
Pin
Name
Reserved
Reserved
BC5
BC4
BC3
BC2
BC1
BC0
Description
Read Back byte count register,
max bytes = 32
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
0
0
0
0
1
1
0
1
RW
RW
RW
RW
RW
RW
RW
RW
RW
0
1
Default
1
0
1
1
1
1
0
0
Byte 13 to 28 Reserved
Byte 29 Slew Rate Control
Bit
7
6
5
4
3
2
1
0
Pin
Name
USB_Slew1
USB_Slew0
PCI_Slew1
PCI_Slew0
Reserved
REF Slew Rate
Reserved
Reserved
Description
USB Slew Rate Control (MSB)
USB Slew Rate Control (LSB)
PCI Slew Rate Control (MSB)
PCI Slew Rate Control (LSB)
Changes Ref Slew Rate
IDTTM PC MAIN CLOCK
See Slew Rate Selection Table
See Slew Rate Selection Table
1.2V/ns
2.2V/ns
1484B—01/21/10
17
ICS9LPRS525
PC MAIN CLOCK
Test Clarification Table
HW
Comments
FSLC/
TEST_SEL
HW PIN
Power-up w/ TEST_SEL = 1 to enter test mode
Cycle power to disable test mode
FSLC./TEST_SEL -->3-level latched input
If power-up w/ V>2.0V then use TEST_SEL
If power-up w/ V<2.0V then use FSLC
FSLB/TEST_MODE -->low Vth input
TEST_MODE is a real time input
If TEST_SEL HW pin is 0 during power-up,
test mode can be invoked through B9b3.
If test mode is invoked by B9b3, only B9b4
is used to select HI-Z or REF/N
FSLB/TEST_Mode pin is not used.
Cycle power to disable test mode, one shot control
SW
FSLB/
TEST
TEST_MODE ENTRY BIT
HW PIN
B9b3
REF/N or
HI-Z
B9b4
<2.0V
>2.0V
>2.0V
>2.0V
X
0
0
1
0
X
X
X
0
0
1
0
OUTPUT
NORMAL
HI-Z
REF/N
REF/N
>2.0V
1
X
1
REF/N
<2.0V
X
1
0
HI-Z
<2.0V
X
1
1
REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION)
B9b4: 1= REF/N, Default = 0 (HI-Z)
IDTTM PC MAIN CLOCK
1484B—01/21/10
18
ICS9LPRS525
PC MAIN CLOCK
56-Lead, 300 mil Body, 25 mil, SSOP
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
α
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
VARIATIONS
N
56
D mm.
MIN
18.31
D (inch)
MAX
18.55
MIN
.720
MAX
.730
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
Ordering Information
9LPRS525AFLFT
Example:
XXXX A F LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
IDTTM PC MAIN CLOCK
1484B—01/21/10
19
ICS9LPRS525
PC MAIN CLOCK
c
N
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
-1.20
-.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
SEE VARIATIONS
SEE VARIATIONS
D
8.10 BASIC
0.319 BASIC
E
E1
6.00
6.20
.236
.244
0.50 BASIC
0.020 BASIC
e
L
0.45
0.75
.018
.030
SEE VARIATIONS
SEE VARIATIONS
N
α
0°
8°
0°
8°
aaa
-0.10
-.004
L
E1
INDEX
AREA
E
1 2
a
D
A
A2
A1
VARIATIONS
-C-
e
b
N
SEATING
PLANE
56
D mm.
MIN
MAX
13.90
14.10
D (inch)
MIN
.547
MAX
.555
Reference Doc.: JEDEC Publicat ion 95, M O-153
aaa C
10-0039
Ordering Information
9LPRS525AGLFT
Example:
XXXX A G LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
IDTTM PC MAIN CLOCK
1484B—01/21/10
20
ICS9LPRS525
PC MAIN CLOCK
Revision History
Rev.
0.1
0.2
0.3
0.4
0.5
A
B
Issue Date Description
7/21/2008 Initial Release
1. Updated pinout to remove Vout reference on pin 40
08/060/08 2. Updated VDD_IO pin descriptions to show 1.05V to 3.3V operation
1. Fixed Pagination of Pin Descriptions
2. Changed reference to PCI3 Config Table in Pindes to match table name
8/8/2008 3. Added Byte 29 for Slew Rate control
Page #
1, 3
2,3,17
1) Byte 11, bit 5 is now reserved.
2) Byte 29, bits 7:6 default to 0.8X slew rate (‘10’)
3) Removed reference to STOP drive mode in Power management table.
4) Corrected REF slew rate control from Byte 29b3 to Byte 29b2.
5) Clarified description of Byte 11, bits 2 and 3 to reflect CK505 ME clock selection table.
10/10/2008 6) Marked as Reserved all bits that are not in the 56-pin version of the device
1) updated tables 2, 6 and 7 to clarify interaction of Config Modes with SRC1
4/28/2009 2) Updated ordering revision to A
4/28/2009 Released to final
1/21/2010 Updated Power Groups table
Various
10, 11, 19,
20
4
This product is protected by United States Patent NO. 7,342,420 and other patents.
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Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
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United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
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21