IDT ICS950910

ICS950910
Integrated
Circuit
Systems, Inc.
Programmable Timing Control Hub™ for P4™
Recommended Application:
VIA P4X/P4M/KT/KN266/333 style chipsets.
Output Features:
•
1 - Pair of differential CPU clocks @ 3.3V (CK408)/
1 - Pair of differential open drain CPU clocks (K7)
•
1 - Pair of differential push pull CPU_CS clocks @ 2.5V
•
3 - AGP @ 3.3V
•
7 - PCI @ 3.3V
•
1 - 48MHz @ 3.3V fixed
•
1 - 24_48MHz @ 3.3V
•
2 - REF @ 3.3V, 14.318MHz
Key Specifications:
•
CPU_CS - CPUT/C: <±250ps
•
CPU_CS - AGP: <±250ps
•
CPU - DDR: <±250ps
•
PCI - PCI: <500ps
•
CPU - PCI: Min = 1.0ns, Typ = 2.0ns, Max = 4.0ns
Frequency Table
Pin Configuration
Bit7
Bit6
Bit5
Bit4
CPU
AGP
PCI
FS3
FS2
FS1
FS0
MHz
MHz
MHz
1
0
0
0
0
105.00
70.00
35.00
0.3 % Center Spread
1
0
0
0
1
140.00
70.00
35.00
0.3 % Center Spread
1
0
0
1
0
210.00
70.00
35.00
0.3 % Center Spread
1
0
0
1
1
174.99
70.00
35.00
0.3 % Center Spread
1
0
1
0
0
80.00
53.34
26.66
0.3 % Center Spread
1
0
1
0
1
106.66
53.34
26.66
0.3 % Center Spread
1
0
1
1
0
160.00
53.34
26.66
0.3 % Center Spread
1
0
1
1
1
133.33
53.34
26.66
0.3 % Center Spread
1
1
1
0
0
100.00
66.67
33.33
0.3 % Center Spread
1
1
1
0
1
133.33
66.67
33.33
0.3 % Center Spread
1
1
1
1
0
200.00
66.67
33.33
0.3 % Center Spread
Spread %
1
1
1
1
166.66
66.67
33.33
0.3 % Center Spread
1
1
0
0
0
100.00
66.67
33.33
0 - 0.6% Down Spread
1
1
0
0
1
133.33
66.67
33.33
0 - 0.6% Down Spread
1
1
0
1
0
200.00
66.67
33.33
0 - 0.6% Down Spread
1
0
1
1
166.66
66.67
33.33
56 Vtt_PWRGD#**/REF1
GND 2
1
1
*FS0/REF0 1
0 - 0.6% Down Spread
55 VDDREF
X1 3
54 GND
X2 4
53 CPUCLKT/CPUCLKODT
VDDAGP 5
52 CPUCLKC/CPUCLKODC
*MODE/AGPCLK0 6
51 VDDCPU3.3
*SEL_408/K7/AGPCLK1 7
50 VDDCPU2.5
*(PCI_STOP#)AGPCLK2 8
49 CPUC_CS
GNDAGP 9
48 CPUT_CS
**FS1/PCICLK_F 10
47 GND
***PCICLK1 11
46 FBOUT
*MULTSEL/PCICLK2 12
45 BUF_IN
GNDPCI 13
PCICLK3 14
PCICLK4 15
VDDPCI 16
ICS950910
Bit2
Features/Benefits:
•
Programmable output frequency.
•
Programmable output divider ratios.
•
Programmable output rise/fall time.
•
Programmable output skew.
•
Programmable spread percentage for EMI control.
•
DDR output buffer supports up to 200MHz.
•
Watchdog timer technology to reset system
if system malfunctions.
•
Programmable watch dog safe frequency.
•
Support I2C Index read/write and block read/write
operations.
•
Uses external 14.318MHz crystal.
PCICLK5 17
Board Target
Trace/Term Z
Reference R,
Iref =
VDD/(3*Rr)
50 ohms
Rr = 221 1%,
Iref = 5.00mA
Ioh = 4* I REF
Rr = 475 1%,
Iref = 2.32mA
Ioh = 6* I REF
0
1
50 ohms
Output
Current
Voh @ Z
1.0V @ 50
0.7V @ 50
42 DDRT1
41 DDRC1
40 VDD2.5
*(CLK_STOP#)PCICLK6 18
MULTISEL0
44 DDRT0
43 DDRC0
39 GND
GND48 19
38 DDRT2
*FS3/48MHz 20
37 DDRC2
*FS2/24_48MHz 21
36 DDRT3
AVDD48 22
35 DDRC3
VDD 23
34 VDD2.5
GND 24
33 GND
IREF 25
32 DDRT4
*(PD#)RESET# 26
31 DDRC4
SCLK 27
30 DDRT5
SDATA 28
29 DDRC5
56-SSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
*** A 120k pull-down resistor to GND is needed on this pin.
0735B—09/21/07
ICS950910
Integrated
Circuit
Systems, Inc.
Pin Description
PIN
#
PIN
NAME
1
*FS0/REF0
I/O
2
3
4
5
GND
X1
X2
VDDAGP
PWR
IN
OUT
PWR
6
PIN
TYPE
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin.
Crystal input, Nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Power supply for AGP clocks, nominal 3.3V
I/O
Function select latch input pin, 1=Desktop Mode, 0=Mobile Mode / AGP clock output.
I/O
7
*MODE/AGPCLK0
*SEL_408/K7/AGPCLK1
8
*(PCI_STOP#)AGPCLK2
I/O
9
10
GNDAGP
**FS1/PCICLK_F
PWR
I/O
CPU output type select latch input pin 0= K7, 1= CK408 / AGP clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / AGP clock output.
Ground pin for the AGP outputs
Frequency select latch input pin / 3.3V PCI free running clock output.
11
***PCICLK1
I/O
Memory type select latch input pin 0= DDR, 1= PC133 SDRAM / 3.3V PCI clock output.
12
*MULTSEL/PCICLK2
I/O
13
14
15
16
17
GNDPCI
PCICLK3
PCICLK4
VDDPCI
PCICLK5
PWR
OUT
OUT
PWR
OUT
18
*(CLK_STOP#)PCICLK6
I/O
19
20
21
22
23
24
GND48
*FS3/48MHz
*FS2/24_48MHz
AVDD48
VDD
GND
PWR
I/O
I/O
PWR
PWR
PWR
25
IREF
OUT
3.3V LVTTL input for selection the current multiplier for CPU outputs / 3.3V PCI clock
output.
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
PCI clock output.
Stops all CPU, DDR/SDRAM and FB_OUT clocks at logic 0 level, when input low. This
input is activated by the MODE selection pin / PCI clock output.
Ground pin for the 48MHz outputs
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
Frequency select latch input pin / Fixed 24 or 48MHz clock output. 3.3V.
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Power supply, nominal 3.3V
Ground pin.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current.
26
*(PD#)RESET#
I/O
Asynchronous active low input pin used to power down the device into a low
power state. This input is activated by the MODE selection pin / Real time
system reset signal for frequency gear ratio change or watchdog timer
timeout. This signal is active low.
27
28
SCLK
SDATA
IN
I/O
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
*** A 120k pull-down resistor to GND is needed on this pin.
0735B—09/21/07
2
ICS950910
Integrated
Circuit
Systems, Inc.
Pin Description (Continued)
PIN
#
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
PIN
NAME
DDRC5
DDRT5
DDRC4
DDRT4
GND
VDD2.5
DDRC3
DDRT3
DDRC2
DDRT2
GND
VDD2.5
DDRC1
DDRT1
DDRC0
DDRT0
BUF_IN
FBOUT
GND
CPUT_CS
CPUC_CS
VDDCPU2.5
VDDCPU3.3
PIN
TYPE
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
OUT
PWR
OUT
OUT
PWR
PWR
52
CPUCLKC/CPUCLKODC
OUT
53
CPUCLKT/CPUCLKODT
OUT
54
55
GND
VDDREF
PWR
PWR
56
Vtt_PWRGD#**/REF1
IN
DESCRIPTION
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Ground pin.
Power supply, nominal 2.5V
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
"Complimentary" Clock of differential pair output.
"True" Clock of differential pair output.
Input Buffers for memory outputs.
Memory feed back output.
Ground pin.
True clock of differential pair 2.5V push-pull CPU outputs.
Complimentary" clocks of differential pair 2.5V push-pull CPU outputs.
Power pin for the CPUCLKs. 2.5V
Power pin for the CPUCLKs. 3.3V
"Complementary" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias / "Complementary" clocks of
differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up /
2.5V CPU clock output.
"True" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias / "True" clocks of differential pair CPU
outputs. These open drain outputs need an external 1.5V pull-up / 2.5V CPU clock
output.
Ground pin.
Ref, XTAL power supply, nominal 3.3V
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs
are valid and are ready to be sampled. This is an active low input. / 14.318 MHz
reference clock.
0735B—09/21/07
3
ICS950910
Integrated
Circuit
Systems, Inc.
General Description
The ICS950910 is a single chip clock solution for desktop designs using the VIA P4X/P4M/KT/KN266/333 style chipsets with
PC133 or DDR memory.
The ICS950910 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
FBOUT
Power Groups
Pin Number
Description
VDD
GND
55
2
Xtal, Ref
AGP [0:2], CPU digital, CPU PLL
5
9
16
13
PCI [0:5], PCI_F outputs
22
19
48MHz, Fix Digital, Fix Analog
Master clock, CPU Analog
23
24
34, 40
33, 39
DDR/SDR outputs
50
47
2.5V CPUT/C_CS output
51
54
3.3V CPUT/C & CPUOD_T/C
0735B—09/21/07
4
ICS950910
Integrated
Circuit
Systems, Inc.
General I2C serial interface information
How to Write:
How to Read:
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Index Block Write Operation
Controller (Host)
starT bit
T
Slave Address D2(H)
WR
WRite
Controller (Host)
T
starT bit
Slave Address D2(H)
WR
WRite
ICS (Slave/Receiver)
ICS (Slave/Receiver)
ACK
ACK
Beginning Byte = N
Beginning Byte = N
ACK
ACK
RT
Repeat starT
Slave Address D3(H)
RD
ReaD
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ACK
Data Byte Count = X
ACK
Beginning Byte N
Byte N + X - 1
ACK
X Byte
ACK
P
stoP bit
Byte N + X - 1
N
P
*See notes on the following page.
0735B—09/21/07
5
Not acknowledge
stoP bit
ICS950910
Integrated
Circuit
Systems, Inc.
Byte 0: Functionality and frequency select register (Default=0)
Description
Bi t
Bit2
Bi t
(2,7:4)
Bi t 3
Bi t 1
Bi t 0
PWD
Bit7 Bit6 Bit5 Bit4 CPUCLK AGPCLK PCICLK
MHz
MHz
MHz
FS 3 FS 2 FS 1 FS 0
Spread %
0
0
0
0
0
102.00
68.00
34.00
0
0
0
0
1
105.00
70.00
35.00
0
0
0
1
0
108.00
72.00
36.00
0
0
0
1
1
111.00
74.00
27.00
0
0
1
0
0
114.00
76.00
38.00
0
0
1
0
1
117.00
78.00
39.00
0
0
1
1
0
120.00
80.00
40.00
0
0
1
1
1
123.00
82.00
41.00
0
1
0
0
0
126.00
72.00
36.00
0
1
0
0
1
130.00
74.30
37.10
0
1
0
1
0
133.90
66.95
33.48
0
1
0
1
1
140.00
70.00
35.00
0
1
1
0
0
144.00
72.00
36.00
0
1
1
0
1
148.00
74.00
37.00
0
1
1
1
0
152.00
76.00
38.00
0
1
1
1
1
156.00
78.00
39.00
1
0
0
0
0
105.00
70.00
35.00
1
0
0
0
1
140.00
70.00
35.00
1
0
0
1
0
210.00
70.00
35.00
1
0
0
1
1
174.99
70.00
35.00
1
0
1
0
0
80.00
53.34
26.66
1
0
1
0
1
106.66
53.34
26.66
1
0
1
1
0
160.00
53.34
26.66
1
0
1
1
1
133.33
53.34
26.66
1
1
1
0
0
100.00
66.67
33.33
1
1
1
0
1
133.33
66.67
33.33
1
1
1
1
0
200.00
66.67
33.33
1
1
1
1
1
166.66
66.67
33.33
1
1
0
0
0
100.00
66.67
33.33
1
1
0
0
1
133.33
66.67
33.33
1
1
0
1
0
200.00
66.67
33.33
1
1
0
1
1
166.66
66.67
33.33
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2,7:4
0 - Normal
1 - Spread spectrum enable
0 - Running
1 - Tristate all outputs
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
+/- 0.30% Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0.3 % Center Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
0 - 0.6% Down Spread
Note 1
0
1
0
Notes:
1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
Mode Pin - Power Management Input Control
MODE, Pin 6
(Latched Input)
0
1
Pin 26
Pin 18
Pin 8
PD#
(Input)
RESET#
(Output)
CPU_STOP#
(Input)
PCICLK5
(Output)
PCI_STOP#
(Input)
AGP2
(Output)
0735B—09/21/07
6
ICS950910
Integrated
Circuit
Systems, Inc.
Byte 1: CPU Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
29
10
30
31
32
53, 52
48, 49
PWD
1
1
1
1
1
1
1
1
Description
DDRC5 (Active/Inactive)
PCICLK_F (Active/Inactive)
DDRT5 (Active/Inactive)
DDRC4 (Active/Inactive)
(Reserved)
DDRT4 (Active/Inactive)
CPUCLKT/C_CS (Active/Inactive)
CPUCLKT/C_CS (Active/Inactive)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
46
18
17
15
14
12
11
53, 52
PWD
1
1
1
1
1
1
1
1
Description
FB_OUT Free running control; 1 = free running; 0 = not free running
PCICLK6 (Active/Inactive)
PCICLK5 (Active/Inactive)
PCICLK4 (Active/Inactive)
PCICLK3 (Active/Inactive)
PCICLK2 (Active/Inactive)
PCICLK1 (Active/Inactive)
CPUCLKT/C Free running control; 1 = free running; 0 = not free running
Byte 3: Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Pin#
46
56
48, 49
8
7
6
PWD
1
1
1
1
1
1
1
1
Description
FB_OUT (Active/Inactive)
SEL 24_48, 0=24Mhz 1=48MHz
DDR free running control; 1 = free running; 0 not free running
REF1 (Active/Inactive)
CPUC/T_CS free running control; 1 = free running; 0 not free running
AGPCLK 2 (Active/Inactive)
AGPCLK 1 (Active/Inactive)
AGPCLK 0 (Active/Inactive)
Byte 4: Frequency Select Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
20
21
1
PWD
X
X
X
X
1
1
1
Description
Latched FS3
Latched FS2
Latched FS1
Latched FS0
48MHz (Active/Inactive)
24_48MHz (Active/Inactive)
(Reserved)
REF0 (Active/Inactive)
0735B—09/21/07
7
ICS950910
Integrated
Circuit
Systems, Inc.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Pin#
35
36
37
38
41
42
43
44
PWD
1
1
1
1
1
1
1
1
Description
DDRC3 (Active/Inactive)
DDRT3 (Active/Inactive)
DDRC2 (Active/Inactive)
DDRT2 (Active/Inactive)
DDRC1 (Active/Inactive)
DDRT1 (Active/Inactive)
DDRC0 (Active/Inactive)
DDRT0 (Active/Inactive)
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Revision ID Bit3
Revision ID Bit2
Revision ID Bit1
Revision ID Bit0
Vendor ID Bit3
Vendor ID Bit2
Vendor ID Bit1
Vendor ID Bit0
PWD
X
X
X
X
0
0
0
1
Description
Revision ID values will be based on individual device's revision
(Reserved)
(Reserved)
(Reserved)
(Reserved)
Byte 7: Revision ID and Device ID Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Device ID7
Device ID6
Device ID5
Device ID4
Device ID3
Device ID2
Device ID1
Device ID0
PWD
Description
0
0
0
Device ID values will be based on individual device
1
"01h" in this case.
0
1
1
1
Byte 8: Byte Count Read Back Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Byte7
Byte6
Byte5
Byte4
Byte3
Byte2
Byte1
Byte0
PWD
Description
0
0
0
Note: Writing to this register will configure byte count and how
0
many bytes will be read back, default is 0FH = 15 bytes.
1
1
1
1
0735B—09/21/07
8
ICS950910
Integrated
Circuit
Systems, Inc.
Byte 9: Watchdog Timer Count Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
WD7
WD6
WD5
WD4
WD3
WD2
WD1
WD0
PWD
Description
0
0
0
The decimal representation of these 8 bits correspond to X •
1
290ms the watchdog timer will wait before it goes to alarm mode
and reset the frequency to the safe setting. Default at power up is
0
16 • 290ms = 4.6 seconds.
0
0
0
Byte 10: Programming Enable bit 8 Watchdog Control Register
Bit
Name
PWD
Bi t 7
Program
Enable
0
Bi t 6
WD Enable
0
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
WD Alarm
S F4
S F3
S F2
S F1
S F0
0
0
0
0
0
0
Description
Programming Enable bit
0 = no programming. Frequencies are selected by HW latches or Byte0 1
= enable all I2C programing.
Software Watchdog Enable bit.
This bit will over write WDEN latched value. 0 = disable, 1 = Enable.
Watchdog Alarm Status 0 = normal 1= alarm status
Watchdog safe frequency bits. Writing to these bits will configure the safe
frequency corrsponding to Byte 0 Bit 2, 7:4 table
Byte 11: VCO Frequency M Divider (Reference divider) Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Ndiv 8
Mdiv 6
Mdiv 5
Mdiv 4
Mdiv 3
Mdiv 2
Mdiv 1
Mdiv 0
PWD
X
X
X
X
X
X
X
X
Description
N divider bit 8
The decimal respresentation of Mdiv (6:0) corresposd to the
reference divider value. Default at power up is equal to the
latched inputs selection.
Byte 12: VCO Frequency N Divider (VCO divider) Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Ndiv 7
Ndiv 6
Ndiv 5
Ndiv 4
Ndiv 3
Ndiv 2
Ndiv 1
Ndiv 0
PWD
Description
X
X
X
The decimal representation of Ndiv (8:0) correspond to the
X
VCO divider value. Default at power up is equal to the
latched inputs selecton. Notice Ndiv 8 is located in Byte 11.
X
X
X
X
0735B—09/21/07
9
ICS950910
Integrated
Circuit
Systems, Inc.
Byte 13: Spread Spectrum Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
SS 7
SS 6
SS 5
SS 4
SS 3
SS 2
SS 1
SS 0
PWD
Description
X
X
The Spread Spectrum (12:0) bit will program the spread
X
precentage. Spread precent needs to be calculated based on the
X
VCO frequency, spreading profile, spreading amount and spread
X
frequency. It is recommended to use ICS software for spread
X
programming. Default power on is latched FS divider.
X
X
Byte 14: Spread Spectrum Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Reserved
Reserved
Reserved
SS 12
SS 11
SS 10
SS 9
SS 8
PWD
X
X
X
X
X
X
X
X
Description
Reserved
Reserved
Reserved
Spread Spectrum Bit 12
Spread Spectrum Bit 11
Spread Spectrum Bit 10
Spread Spectrum Bit 9
Spread Spectrum Bit 8
Byte 15: Output Divider Control Register
Bit
Bit 7
B it 6
Bit 5
Bit 4
Bit 3
Bit 2
B it 1
Bit 0
Name
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
CPU Div 3
CPU Div 2
CPU Div 1
CPU Div 0
PWD
0
1
0
1
0
1
0
1
Description
CPUCLKC/T clock divider ratio can be configured via
these 4 bits individually. For divider selection table refer
to Table 1. Default at power up is latched FS divider.
CPUCLKT/C_CS clock divider ratio can be configured
via these 4 bits individually. For divider selection table
refer to Table 1. Default at power up is latched FS
divider.
Byte 16: Output Divider Control Register
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
AGP Div 3
AGP Div 2
AGP Div 1
AGP Div 0
Reser ved
Reser ved
Reser ved
Reser ved
PWD
0
1
0
1
-
Description
AGP clock divider ratio can be configured via these 4
bits individually. For divider selection table refer to
Table 1. Default at power up is latched FS divider.
Reser ved
0735B—09/21/07
10
ICS950910
Integrated
Circuit
Systems, Inc.
Byte 17: Output Divider Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
AGP_INV
Reserved
CPU_INV
CPU_INV
PWD
0
0
0
0
PCI Div 3
PCI Div 2
PCI Div 1
PCI Div 0
1
0
0
1
Description
AGP Phase Inversion bit
Reserved
CPU T/C Phase Inversion bit
CPUT/C_CS Phase Inversion bit
PCI clock divider ratio can be configured via these 4 bits
individually. For divider selection table refer to Table 2.
Default at power up is latched FS divider.
Table 1
Div (3:2)
Div (1:0)
Table 2
00
01
10
11
Div (3:2)
Div (1:0)
00
01
10
11
00
/2
/4
/8
/16
00
/4
/8
/16
/32
01
/3
/6
/12
/24
01
/3
/6
/12
/24
10
/5
/10
/20
/40
10
/5
/10
/20
/40
11
/7
/14
/28
/56
11
/9
/18
/36
/72
Byte 18: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
CPUCLKT/C_CS
Group Skew
Control
CPUCLKT/C
Group Skew
Control
AGPCLK
Group Skew
Control
Reserved
Reserved
PWD
1
0
1
0
1
Description
These 2 bits delay the CPUCLKT/C_CS with respect to
CPUCLKT/C
00 = 0ps 01 = 250ps 10 = 500ps 11 =750ps
These 2 bits delay the CPUCLKT/C clock with respect to
CPUCLKT/C_CS
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
0
These 2 bits delay the AGPCLK clocks with respect to CPUCLK
00 = 0ps 01 = 250ps 10 = 500ps 11 = 750ps
X
X
Reserved
Reserved
Byte 19: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
Reserved
PCICLK(5:0)
Group Skew
Control
PWD
Description
1
0
Reserved
0
0
1
These 4 bits can change the CPU to PCI (5:0) skew from 1.4ns 0
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bits (3:0) will increase or decrease the delay of the
0
PCI clocks by 100ps.
0
0735B—09/21/07
11
ICS950910
Integrated
Circuit
Systems, Inc.
Byte 20: Group Skew Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
PCICLK_F
Group Skew
Control
Reserved
PWD
Description
1
These 4 bits can change the CPU to PCIF skew from 1.4ns 0
2.9ns. Default at power up is - 2.5ns. Each binary increment or
decrement of Bit (3:0) will increase or decrease the delay of the
0
PCI clocks by 100ps.
0
1
0
Reserved
0
0
Byte 21: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
CPUCLKT/C_CS
Slew Rate Control
CPUCLKT1/C1
Slew Rate Control
CPUCLKT2/C2
Slew Rate Control
AGP_0
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
CPUCLKT/C_CS clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
CPUCLKT1/C1 clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
CPUCLKT2/C2 clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
AGP_0 clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Byte 22: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
AGP(2:1)
Slew Rate Control
PCICLK_F
Slew Rate Control
PCICLK(7:4)
Slew Rate Control
PCICLK(3:0)
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
AGP(2:1) clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
PCICLK_F clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(7:4) clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
PCICLK(3:0) clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
Byte 23: Slew Rate Control Register
Bit
Bi t 7
Bi t 6
Bi t 5
Bi t 4
Bi t 3
Bi t 2
Bi t 1
Bi t 0
Name
REF
Slew Rate Control
IOAPIC(1:0)
Slew Rate Control
48MHz
Slew Rate Control
24_48MHz
Slew Rate Control
PWD
0
1
0
1
0
1
0
1
Description
REF clock slew rate control bits.
01 = strong:10 = normal; 00 = weak
IOAPIC(1:0) clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
48MHz clock slew rate control bits.
01 = strong: 10= normal; 00 = weak
24_48MHz clock slew rate control bits.
01 = strong: 10 = normal; 00 = weak
0735B—09/21/07
12
ICS950910
Integrated
Circuit
Systems, Inc.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
VIH
Input High Voltage
Input Low Voltage
CONDITIONS
Input High Current
IIH
IIL1
Input Low Current
IIL2
TYP
VSS - 0.3
VIL
IIH
MIN
2
VIN = VDD; Inputs with no pull-down
resistors
VIN = VDD; Inputs with pull-down
resistors
VIN = 0 V; Inputs with no pull-up
resistors
VIN = 0 V; Inputs with pull-up
resistors
MAX
VDD + 0.3
UNITS
V
0.8
V
5.75
mA
200
µA
-5.75
mA
-200
µA
IDD3.3OP
CL = Full load; Select @ 100 MHz
228
156
360
mA
IDD3.3OP
CL =Full load; Select @ 133 MHz
220
159
360
mA
IDD3.3PD
Fi
Lpin
CIN
COUT
CINX
IREF=2.32 mA
VDD = 3.3 V
12
14.318
45
7
5
6
45
mA
MHz
nH
pF
pF
pF
2.1
ms
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
1
1,2
Clk Stabilization
Logic Inputs
Output pin capacitance
X1 & X2 pins
From PowerUp or deassertion of
PowerDown to 1st clock.
27
tPZH,tPZL
Output enable delay (all outputs)
1
12
ns
tPHZ,tPLZ
Output disable delay (all outputs)
1
12
ns
TSTAB
Delay1
1
Guaranteed by design, not 100% tested in production.
See timing diagrams for buffered and un-buffered timing requirements.
2
0735B—09/21/07
13
ICS950910
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPUCLKC/T (Current Mode)
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 10-20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
Current Source Output
1
VO = Vx
Zo
Impedance
Statistical measurement on single
VHigh
Voltage High
ended signal using oscilloscope
VLow
Voltage Low
Measurement on single ended
Vovs
Max Voltage
signal using absolute value.
Vuds
Min Voltage
Vcross(abs)
Crossing Voltage (abs)
Variation of crossing over all
Crossing Voltage (var)
d-Vcross
edges
VOL = 0.175V, VOH = 0.525V
tr
Rise Time
tf
VOH = 0.525V VOL = 0.175V
Fall Time
d-tr
Rise Time Variation
d-tf
Fall Time Variation
Measurement from differential
dt3
Duty Cycle
wavefrom
tsk3
VT = 50%
Skew
1
VT = 50%
Jitter, Cycle to cycle
tjcyc-cyc
1
2
MIN
TYP
MAX
Ω
3000
660
-150
UNITS
810
20
850
-15
380
850
150
1150
550
mV
22
140
mV
175
175
290
310
10
10
700
700
125
125
ps
ps
ps
ps
45
51
55
%
16
48
100
150
ps
ps
-450
250
mV
mV
Guaranteed by design, not 100% tested in production.
IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics - CPUCLKODC/T
TA = 0 - 70°C; VDD = 1.7 V +/-5%; CL = 5 pF (unless otherwise stated)
PARAMETER
SYMBOL
Output High Voltage
Output Low Voltage
Output Low Current
Rise Time1
Fall Time1
Differential voltageAC1
Differential voltageDC1
Differential Crossover
Voltage1
Duty Cycle1
Skew1
Jitter Diff, Cycle-to-
VOH2B
VOL2B
IOL2B
tr2B
tf2B
CONDITIONS
Termination to Vpull-up(external)
Termination to Vpull-up(external)
VOL = 0.3 V
VOL = 20%, VOH = 80%
VOH = 80%, VOL = 20%,
MIN
TYP
1
MAX
UNITS
1.2
0.4
V
V
mA
ns
ns
18
0.38
0.44
0.9
0.9
VDIF
0.4
V
VDIF
0.2
V
VX
550
1200
1250
mV
45
51.5
140
55
200
%
ps
60
250
ps
100
250
ps
250
ps
dt2B
tsk2B
VT = 50%
VT = 50%
tjcyc-cyc2B VT = VX
cycle1
Jitter SE, Cycle-totjcyc-cyc2B VT = 1.0V
cycle1
tjabs2B
VT = 50%
Jitter, Absolute1
Notes:
1
- Guaranteed by design, not 100% tested in production.
0735B—09/21/07
14
-250
ICS950910
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - CPUT/C_CS
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 2 pF (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
IOH = -12 mA
Output High Voltage
VOH2B
IOL = 12mA
Output Low Voltage
VOL2B
VOH = 1.7V
Output High Voltage
IOH2B
VOL = 0.7V
Output Low Voltage
IOL2B
VOL = 0.4V, VOH = 2.0V
t
Rise Time
r2B
Differential Crossover
Vx
Note3
Voltage
VT = 1.5V
Duty Cycle
d-t2B
VT = 1.5V
tjcyc-cyc2B
Jitter, Cycle to cycle
2
MIN
2
TYP
MAX
1.6
UNITS
V
V
mA
mA
ns
55
%
0.4
-19
19
0.91
45
45
48.7
62
55
100
%
ps
MIN
2.4
TYP
MAX
UNITS
V
V
IOWT can be varied and is selectable thru the MULTSEL pin.
Electrical Characteristics- DDRT/C
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
IOH = -11 mA
VOH3
Output High Voltage
3
IOL = 11 mA
Output Low Voltage
VOL
3
V
Output High Current
IOH
OH = 2.0 V
3
VOL = 0.8 V
Output Low Current
IOL
1
1
Rise Time
Fall Time
Duty Cycle
tr3
1
tf3
1
dt3
Skew
tsk1
Jitter
1
tjcyc-cyc
1
20% to 80%
20% to 80%
VT = 1.5 V
0.4
-12
12
650
650
45
mA
660
660
50.3
950
950
53
ns
ns
%
VT = 1.5 V
102
250
ps
VT = 1.5 V
78
250
ps
Guaranteed by design, not 100% tested in production.
0735B—09/21/07
15
ICS950910
Integrated
Circuit
Systems, Inc.
Electrical Characteristics- PCICLK
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
1
Output Frequency
FO
1
VO = VDD*(0.5)
Output Impedance
RDSP1
1
IOH = -1 mA
Output High Voltage
VOH
1
IOL = 1 mA
Output Low Voltage
VOL
V
[email protected] = 1.0 V
1
Output High Current
IOH
V [email protected] = 3.135 V
VOL @MIN = 1.95 V
1
Output Low Current
IOL
VOL @MAX = 0.4 V
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf1
1
VT = 1.5 V
Duty Cycle
dt1
1
1
Skew
tsk1
Jitter
1
tjcyc-cyc
MIN
TYP
33.33
12
2.4
MAX
55
0.55
-33
-33
30
UNITS
MHz
Ω
V
V
mA
mA
1.8
1.6
52.4
38
2
2
55
VT = 1.5 V
239
500
ps
VT = 1.5 V
205
250
ps
TYP
66.66
MAX
UNITS
MHz
Ω
V
V
0.5
0.5
45
ns
ns
%
Guaranteed by design, not 100% tested in production.
Electrical Characteristics- AGP
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
1
Output Frequency
FO
1
VO = VDD*(0.5)
Output Impedance
RDSP1
1
IOH = -1 mA
Output High Voltage
VOH
1
IOL = 1 mA
Output Low Voltage
VOL
V
OH = 1.0 V
1
Output High Current
IOH
VOH = 3.135 V
VOL = 1.95 V
1
Output Low Current
IOL
VOL = 0.4 V
1
VOL = 0.4 V, VOH = 2.4 V
Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf1
Duty Cycle
1
dt1
MIN
12
2.4
55
0.55
-33
-33
30
mA
mA
0.5
0.5
1.5
1.28
38
2
2
45
52.9
55
%
ns
ns
1
VT = 1.5 V
1
VT = 1.5 V
40
500
ps
VT = 1.5 V
113
250
ps
Skew
tsk1
Jitter
1
tjcyc-cyc
Guaranteed by design, not 100% tested in production.
0735B—09/21/07
16
ICS950910
Integrated
Circuit
Systems, Inc.
Electrical Characteristics - VCH, 48MHz DOT, 48MHz, USB
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 20 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
FO1
Output Frequency
1
VO = VDD*(0.5)
Output Impedance
RDSP1
1
IOH = -1 mA
Output High Voltage
VOH
1
IOL = 1 mA
Output Low Voltage
VOL
V
OH = 1.0 V
1
Output High Current
IOH
VOH = 3.135 V
VOL = 1.95 V
1
Output Low Current
IOL
VOL = 0.4 V
1
VOL = 0.4 V, VOH = 2.4 V
48MHz Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V
48MHz Fall Time
tf1
1
VOL = 0.4 V, VOH = 2.4 V
24MMz Rise Time
tr1
1
VOH = 2.4 V, VOL = 0.4 V
24MHz Fall Time
tf1
1
VT = 1.5 V
48 MHz Duty Cycle
dt1
1
VT = 1.5 V
48MHz Duty Cycle
dt1
1
VT = 1.5 V
48 MHz Jitter
tjcyc-cyc
1
VT = 1.5 V
24MHz Jitter
tjcyc-cyc
MIN
12
2.4
TYP
48
48
MAX
55
0.55
-29
-23
29
UNITS
MHz
Ω
V
V
mA
mA
0.5
0.5
1
1
1.25
1.27
1.26
1.28
27
2
2
2
2
45
45
52.5
51.4
124
111
55
55
350
350
%
%
ps
ps
MIN
TYP
14.32
MAX
0.4
UNITS
MHz
Ω
V
V
-23
mA
1.92
1.92
54.1
27
4
4
55
mA
ns
ns
%
245
500
ps
ns
ns
ns
ns
1
Guaranteed by design, not 100% tested in production.
** USB is 180 degrees phase different to DOT
Electrical Characteristics - REF
TA = 0 - 70°C; VDD=3.3V +/-5%; CL = 30 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
FO1
Output Frequency
VO = VDD*(0.5)
Output Impedance
RDSP11
IOH = -1 mA
Output High Voltage
VOH1
1
IOL = 1 mA
Output Low Voltage
VOL
V
OH = 1.0 V
Output High Current
IOH1
VOH = 3.135 V
VOL = 1.95 V
Output Low Current
IOL1
VOL = 0.4 V
1
V
=
0.4
V, VOH = 2.4 V
Rise Time
tr1
OL
1
VOH = 2.4 V, VOL = 0.4 V
Fall Time
tf1
1
VT = 1.5 V
Duty Cycle
dt1
Jitter
1
tjcyc-cyc1
VT = 1.5 V
Guaranteed by design, not 100% tested in production.
0735B—09/21/07
17
20
2.4
60
-29
29
1
1
45
ICS950910
Integrated
Circuit
Systems, Inc.
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function
when a switch or 2 pin header is used. With no jumper is
installed the pin will be pulled high. With the jumper in
place the pin will be pulled low. If programmability is not
necessary, than only a single resistor is necessary. The
programming resistors should be located close to the series
termination resistor to minimize the current loop area. It is
more important to locate the series termination resistor
close to the driver than the programming resistor.
The I/O pins designated by (input/output) serve as dual
signal functions to the device. During initial power-up, they
act as input pins. The logic level (voltage) that is present on
these pins at this time is read and stored into a 5-bit internal
data latch. At the end of Power-On reset, (see AC
characteristics for timing values), the device changes the
mode of operations for these pins to an output function. In
this mode the pins produce the specified buffered clocks to
external loads.
To program (load) the internal configuration register for
these pins, a resistor is connected to either the VDD (logic 1)
power supply or the GND (logic 0) voltage potential. A 10
Kilohm (10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K W
Via to Gnd
Device
Pad
8.2K W
Clock trace to load
Series Term. Res.
Fig. 1
0735B—09/21/07
18
ICS950910
Integrated
Circuit
Systems, Inc.
Power Down Waveforms
0ns
50ns
25ns
1
2
VCO Internal
CPU 100MHz
3.3V 66MHz
PCI 33MHz
PD#
REF 14.318MHZ
48MHZ
Note
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all
the output clocks are driven Low on their next High to Low tranistiion.
2. Power-up latency <3ms.
3. Waveform shown for 100MHz
Group Offset Waveforms
0ns
10ns
20ns
30ns
40ns
Cycl e R epeat s
CPU 66MHz
CPU 100MHz
CPU 133MHz
3.5V 66MHz
PCI 33MHz
APIC 16.7MHz
REF 14.318MHz
USB 48MHz
Group Skews at Common Transition Edges
GROUP
CPU408 to CPUCS
SYMBOL
CPU
CONDITIONS
50% to 1.25V
MIN
0
TYP
MAX
250
CPU Open Drain to CPUCS
CPU
50% to 1.25V
0
75
250
CPUCS to PCI
CPU408 to PCI
AGP to PCI
SCPU-PCI
SCPU-PCI
SAGP-PCI
1.25 to 1.5V
1.25 to 1.5V
1.5 to 1.5V
0
0
1.5
2.8
3.8
2.87
4
4
3.5
1
Guaranteed by design, not 100% tested in production.
0735B—09/21/07
19
UNITS
ps
ns
ns
ns
ICS950910
Integrated
Circuit
Systems, Inc.
c
N
L
E1
INDEX
AREA
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
N
α
E
1 2
a
h x 45°
D
A
A1
-Ce
N
SEATING
PLANE
b
.10 (.004) C
56
In Millimeters
COMMON DIMENSIONS
MIN
MAX
2.41
2.80
0.20
0.40
0.20
0.34
0.13
0.25
SEE VARIATIONS
10.03
10.68
7.40
7.60
0.635 BASIC
0.38
0.64
0.50
1.02
SEE VARIATIONS
0°
8°
VARIATIONS
D mm.
MIN
MAX
18.31
18.55
In Inches
COMMON DIMENSIONS
MIN
MAX
.095
.110
.008
.016
.008
.0135
.005
.010
SEE VARIATIONS
.395
.420
.291
.299
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
0°
8°
D (inch)
MIN
.720
Reference Doc.: JEDEC Publication 95, MO-118
10-0034
300 mil SSOP Package
Ordering Information
ICS950910yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging
Lead Free (Optional)
Package Type
F = SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
Prefix
ICS = Standard Device
0735B—09/21/07
20
MAX
.730
ICS950910
Integrated
Circuit
Systems, Inc.
Revision History
Rev.
B
Issue Date Description
09/21/07 Updated Pin 18 Typo.
Page #
2
0735B—09/21/07
21