ISL43L841 ® Data Sheet June 30, 2006 Ultra Low ON-Resistance, Low-Voltage, Single Supply, Differential 4 to 1 Analog Multiplexer The Intersil ISL43L841 device contains precision, bidirectional, analog switches configured as a differential 4-channel multiplexer/demultiplexer. It is designed to operate from a single +1.65V to +4.5V supply. The device has an inhibit pin to simultaneously open all signal paths. With a supply voltage of 4.2V and logic high voltage of 2.85V at the logic inputs, the part draws only 20µA max of ICC current. ON resistance is 0.47Ω with a +4.3V supply and 0.65Ω with a single +1.8V supply. Each switch can handle rail to rail analog signals. A channel can handle 300mA of continuous current. The part has low quiescent power consumption of 0.23µW max. All digital inputs are 1.8V logic-compatible when using a single +3V supply. The ISL43L841 is a differential 4 to 1 multiplexer device that is offered in a 16 Ld 3x3 TQFN package. Table 1 summarizes the performance of this family. TABLE 1. FEATURES AT A GLANCE CONFIGURATION Diff 4:1 Mux 4.3V RON 0.47Ω 4.3V tON/tOFF 22ns/12ns 3V RON 0.52Ω 3V tON/tOFF 25ns/15ns 1.8V RON 0.65Ω 1.8V tON/tOFF 40ns/17ns PACKAGES 16 Ld 3x3 TQFN FN6212.1 Features • Pb-Free Plus Anneal (RoHS Compliant) • Pin Compatible Replacement for the MAX4782 and MAX4618 • ON Resistance (RON) - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.47Ω - V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.52Ω - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω • RON Matching Between Channels. . . . . . . . . . . . . . . . 0.12Ω • RON Flatness Across Signal Range . . . . . . . . . . . . . 0.056Ω • Single Supply Operation. . . . . . . . . . . . . . . . +1.65V to +4.5V • Low Power Consumption (PD). . . . . . . . . . . . . . . . . <0.23µW • Low ICC Current when VinH is not at the V+ Rail • Fast Switching Action (VS = +3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15ns • Guaranteed Break-Before-Make • High Current Handling Capacity (300mA Continuous) • Available in 16 Ld 3x3 TQFN • 1.8V CMOS-Logic Compatible (+3V Supply) Applications • Battery Powered, Handheld, and Portable Equipment - Cellular/Mobile Phones - Pagers - Laptops, Notebooks, Palmtops • Portable Test and Measurement • Medical Equipment • Audio and Video Switching Related Literature • Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)” • Application Note AN557 “Recommended Test Procedures for Analog Switches” 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL43L841 Pinout (Note 1) A2 A0 V+ B2 ISL43L841 (3x3 TQFN) TOP VIEW 16 15 14 13 COMA 1 12 B1 A3 2 11 COMB A1 3 10 B0 INH 4 9 B3 6 7 GND ADD0 8 ADD1 5 N.C. LOGIC NOTE: 1. Switches Shown for Logic “0” Inputs. Truth Table Ordering Information ISL43L841 INH ADD0 ADD1 SWITCH ON 1 X X NONE 0 0 0 A0, B0 0 0 1 A1, B1 0 1 0 A2, B2 0 1 1 A3, B3 NOTE: Logic “0” ≤0.5V. Logic “1” ≥1.4V, with a 3V supply. X = Don’t Care. Pin Descriptions PIN V+ FUNCTION PART NO. ISL43L841IRZ (Note) TEMP. RANGE PART (°C) MARKING PACKAGE PKG. DWG. # L81Z -40 to 85 16 Ld 3x3 TQFN L16.3x3A (Pb-Free) ISL43L841IRZ-T L81Z (Note) -40 to 85 16 Ld 3x3 TQFN L16.3x3A Tape and Reel (Pb-Free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. System Power Supply Input (1.65V to 4.5V) N.C. N0 Connect. Not internally connected. GND Ground Connection INH Inhibit Input Pin. Connect to GND for Normal Operation. Connect to V+ to turn all switches off. COMA Analog Switch Channel A Output COMB Analog Switch Channel B Output A0-A3 Analog Switch Channel A Input B0-B3 Analog Switch Channel B Input ADDx Address Input Pin 2 FN6212.1 June 30, 2006 ISL43L841 Absolute Maximum Ratings Thermal Information V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 4.7V Input Voltages INH, Ax, Bx, ADDx (Note 2) . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Output Voltages COMx (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (V+) + 0.3V Continuous Current NO or COM . . . . . . . . . . . . . . . . . . . . . ±300mA Peak Current NO or COM (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . ±500mA ESD Rating HBM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4kV Thermal Resistance (Typical, Note 3) θJA (°C/W) 16 Ld 3x3 TQFN Package . . . . . . . . . . . . . . . . . . . . 75 Maximum Junction Temperature (Plastic Package). . . . . . . . 150°C Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to 150°C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300°C (Lead Tips Only) Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to 85°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 2. Signals on Ax, Bx, COMx, ADDx, or INH exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings. 3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. Electrical Specifications - 4.3V Supply Test Conditions: VSUPPLY = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Notes 4, 8), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Full 0 - V+ V 25 - 0.48 - Ω ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 3.9V, ICOM = 100mA, VAX or VBX = 0V to V+, (See Figure 5) RON Matching Between Channels, ∆RON V+ = 3.9V, ICOM = 100mA, VAX or VBX = Voltage at max RON, (Note 6) RON Flatness, RFLAT(ON) V+ = 3.9V, ICOM = 100mA, VAX or VBX = 0V t0 V+, (Note 7) Full - 0.56 - Ω 25 - 0.12 - Ω Full - 0.13 - Ω 25 - 0.056 - Ω Full - 0.06 - Ω 25 -50 1 50 nA Full -150 - 150 nA 25 -50 0.6 50 nA Full -150 - 150 nA Input Voltage High, VINH, VADDH Full 1.5 1.07 - V Input Voltage Low, VINL, VADDL Full - 0.86 0.4 V V+ = +4.5V, VINH = VADD = 0V or V+ (Note 10) Full -0.5 - 0.5 µA V+ = 3.9V, VAx or VBx = 3.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) 25 - 24 34 ns Full - - 38 ns 25 - 14 24 ns Full - - 28 ns 25 - 21 31 ns Full - - 34 ns 25 - 4 - ns Full 1 - - ns Ax or Bx OFF Leakage Current, IAx(OFF) or IBx(OFF) V+ = 4.5V, VCOM = 0.3V, 3V, VAX or VBX = 3V, 0.3V COM ON Leakage Current, ICOM(ON) V+ = 4.5V, VCOM = VAX or VBX = 0.3V, 3V DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF V+ = 3.9V, VAx or VBx = 3.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) Address Transition Time, tTRANS V+ = 3.9V, VAX or VBX = 3.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) V+ = 4.5V, VAX or VBX = 3.0V, RL = 50Ω, CL = 35pF, (See Figure 3, Note 10) Break-Before-Make Time, tBBM 3 FN6212.1 June 30, 2006 ISL43L841 Electrical Specifications - 4.3V Supply Test Conditions: VSUPPLY = +3.9V to +4.5V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Notes 4, 8), Unless Otherwise Specified (Continued) PARAMETER TEST CONDITIONS TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS Input OFF Capacitance, COFF f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 62 - pF COM OFF Capacitance, COFF f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 218 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 232 - pF OFF Isolation RL = 50Ω, CL = 35pF, f = 100kHz, (See Figures 4 and 6) 25 - 65 - dB 25 - -100 - dB f = 20Hz to 20kHz, 0.5Vp-p, RL = 32Ω 25 - 0.02 - % Full 1.65 - 4.5 V 25 - 0.02 0.05 µA Crosstalk, Note 9 Total Harmonic Distortion (THD) POWER SUPPLY CHARACTERISTICS Power Supply Range Positive Supply Current, I+ V+ = 4.5V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ V+ = 4.2V, VADDx = 2.85V Full - - 0.9 µA 25 - 10 20 µA NOTES: 4. VIN = Input voltage to perform proper function. 5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 6. RON matching between channels is calculated by subtracting the channel with the highest max RON value from the channel with lowest max RON value. 7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range. 8. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation. 9. Between any two switches. 10. Guaranteed but not tested. Electrical Specifications - 3V Supply Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Notes 4, 8) Unless Otherwise Specified TEMP (°C) (NOTE 5) MIN TYP Full 0 - V+ V 25 - 0.53 0.75 Ω Full - - 0.8 Ω 25 - 0.12 0.2 Ω Full - - 0.2 Ω 25 - 0.056 0.15 Ω Full - - 0.15 Ω Input Voltage High, VINH, VADDH Full 1.4 0.8 - V Input Voltage Low, VINL, VADDL Full - 0.67 0.4 V V+ = 3.6V, VINH = VADD = 0V or V+ (Note 10) Full -0.5 - 0.5 µA V+ = 2.7V, VAx or VBx = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) 25 - 27 37 ns Full - - 41 ns 25 - 16 26 ns Full - - 30 ns PARAMETER TEST CONDITIONS (NOTE 5) MAX UNITS ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V to V+, See Figure 5 ON Resistance, RON RON Matching Between Channels, DRON V+ = 2.7V, ICOM = 100mA, VAX or VBX = Voltage at max RON, (Note 6) RON Flatness, RFLAT(ON) V+ = 2.7V, ICOM = 100mA, VAX or VBX = 0V t0 V+, (Note 7) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Inhibit Turn-ON Time, tON Inhibit Turn-OFF Time, tOFF V+ = 2.7V, VAx or VBx = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) 4 FN6212.1 June 30, 2006 ISL43L841 Electrical Specifications - 3V Supply PARAMETER Test Conditions: VSUPPLY = +2.7V to +3.3V, GND = 0V, VINH = 1.4V, VINL = 0.4V (Notes 4, 8) Unless Otherwise Specified (Continued) TEST CONDITIONS Address Transition Time, tTRANS Break-Before-Make Time, tBBM V+ = 2.7V, VAX or VBX = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) V+ = 3.3V, VAX or VBX = 1.5V, RL = 50Ω, CL = 35pF, (See Figure 3, Note 10) TEMP (°C) (NOTE 5) MIN TYP (NOTE 5) MAX UNITS 25 - 24 34 ns Full - - 38 ns 25 - 4 - ns Full 1 - - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0W, (See Figure 2) 25 - -65 - pC Input OFF Capacitance, COFF f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 62 - pF COM OFF Capacitance, COFF f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 218 - pF COM ON Capacitance, CCOM(ON) f = 1MHz, VAX or VBX = VCOM = 0V, (See Figure 7) 25 - 232 - pF OFF Isolation RL = 50Ω, CL = 35pF, f = 100kHz, (See Figures 4 and 6) 25 - 65 - dB 25 - -100 - dB f = 20Hz to 20kHz, 0.5Vp-p, RL = 32Ω 25 - 0.02 - % Full 1.65 - 4.5 V 25 - - 0.05 µA Full - - 0.9 µA Crosstalk, (Note 9) Total Harmonic Distortion (THD) POWER SUPPLY CHARACTERISTICS Power Supply Range V+ = 3.6V, VINH, VADD = 0V or V+, Switch On or Off Positive Supply Current, I+ Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1V, VINL = 0.4V (Notes 4, 8), Unless Otherwise Specified PARAMETER TEST CONDITIONS TEMP (°C) MIN (NOTE 5) TYP MAX (NOTE 5) UNITS Full 0 - V+ V ANALOG SWITCH CHARACTERISTICS Analog Signal Range, VANALOG ON Resistance, RON V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) RON Matching Between Channels, ∆RON V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 1.0V, (See Figure 5) RON Flatness, RFLAT(ON) V+ = 1.8V, ICOM = 10.0mA, VAX or VBX = 0V, 0.9V, 1.6V, (See Figure 5) 25 - 0.65 0.85 Ω Full - - 0.9 Ω 25 - 0.12 - Ω Full - 0.12 - Ω 25 - 0.14 - Ω Full - 0.14 - Ω Input Voltage High, VINH, VADDH Full 1 - - V Input Voltage Low, VINL, VADDL Full - - 0.4 V V+ = 1.8V, VINH, VADD = 0V or V+, (Note 10) Full -0.5 - 0.5 µA Inhibit Turn-ON Time, tON V+ = 1.8V, VAx or VBx = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) 25 - 40 50 ns Inhibit Turn-OFF Time, tOFF V+ = 1.8V, VAx or VBx = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) DIGITAL INPUT CHARACTERISTICS Input Current, IINH, IINL, IADDH, IADDL DYNAMIC CHARACTERISTICS Address Transition Time, tTRANS V+ = 1.8V, VAX or VBX = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 1, Note 10) Full - - 55 ns 25 - 17 27 ns Full - - 31 ns 25 - 32 42 ns Full - - 46 ns Break-Before-Make Time, tBBM V+ = 1.8V, VAX or VBX = 1.0V, RL = 50Ω, CL = 35pF, (See Figure 3, Note 10) 25 - 9 - ns Charge Injection, Q CL = 1.0nF, VG = 0V, RG = 0Ω, (See Figure 2) 25 - -39 - pC 5 FN6212.1 June 30, 2006 ISL43L841 Test Circuits and Waveforms V+ C V+ LOGIC INPUT C tr < 5ns tf < 5ns 50% V+ 0V A0, B0 A1, A2, B1, B2, A3, B3 tON INH VA0, VB0 SWITCH OUTPUT 90% VOUT 90% VOUT COMA COMB GND ADD0-1 LOGIC INPUT CL 35pF RL 50Ω 0V tOFF Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1A. INHIBIT tON/tOFF MEASUREMENT POINTS V+ LOGIC INPUT FIGURE 1B. INHIBIT tON/tOFF TEST CIRCUIT tr < 5ns tf < 5ns 50% V+ C C 0V tTRANS V+ VOUT VA0, VB0 A1, A2, B1, B2, A3, B3 COMA, COMB ADD0-1 GND INH VOUT 90% SWITCH OUTPUT CL 35pF RL 50Ω LOGIC INPUT 10% VA3, VB3 A0, B0 0V tTRANS Logic input waveform is inverted for switches that have the opposite logic sense. Repeat test for other switches. CL includes fixture and stray capacitance. RL -----------------------------V OUT = V (NO or NC) R + R L ( ON ) FIGURE 1C. ADDRESS tTRANS MEASUREMENT POINTS FIGURE 1D. ADDRESS tTRANS TEST CIRCUIT FIGURE 1. SWITCHING TIMES V+ V+ LOGIC INPUT RG OFF OFF ON SWITCH OUTPUT VOUT 0V ∆VOUT Q = ∆VOUT x CL C VOUT Ax, Bx COMA, COMB 0Ω VG ADD1 ADD0 CHANNEL SELECT GND INH LOGIC INPUT CL 1000pF Repeat test for other switches. FIGURE 2A. Q MEASUREMENT POINTS FIGURE 2B. Q TEST CIRCUIT FIGURE 2. CHARGE INJECTION 6 FN6212.1 June 30, 2006 ISL43L841 Test Circuits and Waveforms (Continued) V+ tr < 5ns tf < 5ns V+ C C LOGIC INPUT 0V A0-A3 B0-B3 V+ CL 35pF RL 50Ω ADD0-1 90% SWITCH OUTPUT VOUT VOUT COMA COMB LOGIC INPUT 0V tBBM GND INH Repeat test for other switches. CL includes fixture and stray capacitance. FIGURE 3A. tBBM MEASUREMENT POINTS FIGURE 3B. tBBM TEST CIRCUIT FIGURE 3. BREAK-BEFORE-MAKE TIME V+ 10nF V+ SIGNAL GENERATOR C RON = V1/100mA Ax or Bx Ax or Bx VX 0V or V+ ADD1 ADD0 ANALYZER COMx 100mA CHANNEL SELECT GND 0V or V+ V1 ADD1 ADD0 COMA or COMB GND INH RL CHANNEL SELECT INH Off-Isolation is measured between COM and “Off” NO terminal on each switch. Signal direction through switch is reversed and worst case values are recorded. FIGURE 5. RON TEST CIRCUIT FIGURE 4. OFF ISOLATION TEST CIRCUIT V+ C V+ SIGNAL GENERATOR CHANNEL SELECT COMA Ax or Bx ADD1 ADD0 IMPEDANCE ANALYZER Bx ANALYZER 0V or V+ 50Ω Ax 0V or V+ C COMB GND N.C. INH ADD1 ADD0 COMA or COMB GND INH CHANNEL SELECT RL Crosstalk is measured between adjacent channels with one channel ON and the other channel OFF. Signal direction through switch is reversed and worst case values are recorded. FIGURE 6. CROSSTALK TEST CIRCUIT 7 FIGURE 7. CAPACITANCE TEST CIRCUIT FN6212.1 June 30, 2006 ISL43L841 Detailed Description Power-Supply Considerations The ISL43L841 analog multiplexer offers precise switching capability from a single 1.65V to 4.5V supply with low onresistance (0.47Ω) and high speed operation (tON = 24ns, tOFF = 14ns). The devices are especially well suited to portable battery powered equipment thanks to the low operating supply voltage (1.65V), low power consumption (0.23µW), low leakage currents (50nA max). High frequency applications also benefit from the wide bandwidth, and the very high off isolation and crosstalk rejection. The ISL43L841 construction is typical of most CMOS analog switches, in that they have two supply pins: V+ and GND. V+ and GND drive the internal CMOS switches and set their analog voltage limits. Unlike switches with a 4V maximum supply voltage, the ISL43L841 4.7V maximum supply voltage provides plenty of room for the 10% tolerance of 4.3V supply, as well as room for overshoot and noise spikes. Supply Sequencing and Overvoltage Protection With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between V+ and GND. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pins and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a signal pin or logic pin goes below ground or above the V+ rail. Logic inputs can be protected by adding a 1kΩ resistor in series with the logic input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage, and the submicroamp input current produces an insignificant voltage drop during normal operation. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low RON switch. Connecting schottky diodes to the signal pins as shown in Figure 8 will shunt the fault current to the supply or to ground thereby protecting the switch. These schottky diodes must be sized to handle the expected fault current. The minimum recommended supply voltage is 1.65V but the part will operate with a supply below 1.65V. It is important to note that the input signal range, switching times, and onresistance degrade at lower supply voltages. Refer to the electrical specification tables and Typical Performance Curves for details. V+ and GND power the internal logic (thus setting the digital switching point) and level shifters. The level shifters convert the logic levels to switch V+ and GND signals to drive the analog switch gate terminals. This device cannot be operated with bipolar supplies, because the input switching point becomes negative in this configuration. Logic-Level Thresholds These devices are 1.8V CMOS compatible (0.5V and 1.4V) over a supply range of 2.5V to 4.5V (see Figure 15). At 2.5V the VINL level is about 0.52V. This is still above the 1.8V CMOS guaranteed minimum level of 0.4V, but noise margin is reduced. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL43L841 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example driving the device with 2.85V logic (0V to 2.85V) while operating with a 4.2V supply, the device draws only 10µA of current when both address inputs are high (see Figure 13 for VLOGIC = 2.85V). High-Frequency Performance OPTIONAL SCHOTTKY DIODE OPTIONAL PROTECTION RESISTOR In 50Ω systems, signal response is reasonably flat even past 10MHz with a -3dB bandwidth of 70MHz (see Figure 19). The frequency response is very consistent over a wide V+ range, and for varying analog signal levels. V+ ADDX INH VCOM VNOx GND OPTIONAL SCHOTTKY DIODE FIGURE 8. OVERVOLTAGE PROTECTION 8 An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feed through from a switch’s input to its output. Off Isolation is the resistance to this feed through, while Crosstalk indicates the amount of feed through from one switch to another. Figure 20 details the high Off Isolation and Crosstalk rejection provided by this family. At 100kHz, Off Isolation is about 65dB in 50Ω systems, decreasing approximately 20dB per decade as frequency increases. Higher load impedances decrease Off Isolation and Crosstalk rejection FN6212.1 June 30, 2006 ISL43L841 due to the voltage divider action of the switch OFF impedance and the load impedance. Leakage Considerations Reverse ESD protection diodes are internally connected between each analog-signal pin and both V+ and GND. One of these diodes conducts if any analog signal exceeds V+ or GND. Virtually all the analog leakage current comes from the ESD diodes to V+ or GND. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased by either V+ or GND and the analog signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows between each pin and one of the supply terminals, not to the other switch terminal. This is why both sides of a given switch can show leakage currents of the same or opposite polarity. There is no connection between the analog signal paths and V+ or GND. Typical Performance Curves TA = 25°C, Unless Otherwise Specified 0.75 0.6 ICOM = 100mA V+ = 1.65V V+ = 4.3V ICOM = 100mA 0.7 0.55 0.65 0.5 RON (Ω) RON (Ω) 0.6 V+ = 1.8V 0.55 V+ = 3V 0.45 0.45 25°C 0.4 V+ = 2.7V 0.5 85°C -40°C 0.35 V+ = 3.6V V+ = 4.3V 0.3 0.4 0 1 2 3 4 0 5 1 2 3 4 FIGURE 10. ON RESISTANCE vs SWITCH VOLTAGE FIGURE 9. ON RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE 0.65 0.75 V+ = 3V ICOM = 100mA V+ = 1.8V ICOM = 100mA 0.7 0.6 0.65 85°C 85°C RON (Ω) RON (Ω) 0.55 0.5 0.6 0.55 25°C 25°C 0.45 5 VCOM (V) VCOM (V) 0.5 0.4 0.45 -40°C -40°C 0.35 0.4 0 0.5 1 1.5 2 2.5 VCOM (V) FIGURE 11. ON RESISTANCE vs SWITCH VOLTAGE 9 3 0 0.5 1 1.5 2 VCOM (V) FIGURE 12. ON RESISTANCE vs SWITCH VOLTAGE FN6212.1 June 30, 2006 ISL43L841 Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) -10 50 V+ = 4.2V -20 -30 40 V+ = 1.8V SWEEPING TWO LOGIC INPUTS -40 -50 Q (pC) iV+ (µA) 30 20 -60 -70 -80 SWEEPING ONE LOGIC INPUT 10 V+ = 3V -90 -100 0 -110 1 0 2 3 4 0 5 0.5 1 VLOGIC (V) 1.5 2 2.5 3 VCOM (V) FIGURE 13. I+ CURRENT vs LOGIC VOLTAGE FIGURE 14. CHARGE INJECTION vs SWITCH VOLTAGE 1.3 200 1.2 1.1 150 0.9 tRANS (ns) VINH AND VINL (V) 1 VINH 0.8 0.7 VINL 0.6 0.5 100 50 25°C 85°C 0.4 0.3 -40°C 0.2 1 1.5 2 2.5 3 V+ (V) 3.5 4 FIGURE 15. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE 140 40 120 35 100 30 80 60 85°C 25°C 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5 FIGURE 16. ADDRESS TRANS TIME vs SUPPLY VOLTAGE tOFF (ns) tON (ns) 0 4.5 25 85°C 20 25°C 15 40 -40°C -40°C 10 20 5 0 1 1.5 2 2.5 3 V+ (V) 3.5 4 4.5 FIGURE 17. INHIBIT TURN - ON TIME vs SUPPLY VOLTAGE 10 1 1.5 2 2.5 3 3.5 4 4.5 V+ (V) FIGURE 18. INHIBIT TURN - OFF TIME vs SUPPLY VOLTAGE FN6212.1 June 30, 2006 ISL43L841 0 V+ = 3V -10 20 -20 30 -30 40 450 50 GAIN -10 0 PHASE 20 60 80 RL = 50Ω VIN = 0.2VP-P to 2VP-P 0.1M PHASE (°) 40 100 1M 10M 100M FREQUENCY (Hz) FIGURE 19. FREQUENCY RESPONSE -50 60 ISOLATION -60 70 -70 80 -80 OFF ISOLATION (dB) 0 10 V+ = 3V CROSSTALK (dB) NORMALIZED GAIN (dB) Typical Performance Curves TA = 25°C, Unless Otherwise Specified (Continued) 90 CROSSTALK -90 -100 1k 100 10k 100k 1M 10M 110 100M 500M FREQUENCY (Hz) FIGURE 20. CROSSTALK AND OFF ISOLATION Die Characteristics SUBSTRATE POTENTIAL (POWERED UP): GND (QFN Paddle Connection: To Ground or Float) TRANSISTOR COUNT: 228 PROCESS: Si Gate CMOS 11 FN6212.1 June 30, 2006 ISL43L841 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead Frame Plastic Package (TMLFP) ) L16.3x3A 2X 0.15 C A D A 9 16 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS D/2 D1 D1/2 2X N 6 INDEX AREA 0.15 C B 1 2 3 E1/2 E/2 E1 0.15 C B A2 A C A3 SIDE VIEW A1 9 0.10 M C A B 4X P D2 (DATUM B) 8 7 D2 2 N 1 (DATUM A) N e (Ne-1)Xe REF. E2 E2/2 NX L A2 - - 0.80 9 0.20 REF 0.18 - D1 2.75 BSC 9 1.35 1.50 1.65 7, 8, 10 3.00 BSC - 2.75 BSC 1.35 1.50 9 1.65 7, 8, 10 0.50 BSC - k 0.20 - - - L 0.30 0.40 0.50 8 N 16 2 Nd 4 3 4 3 P - - 0.60 θ - - 12 9 9 8 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. A1 5 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. SECTION "C-C" C L 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. C L L e TERMINAL TIP FOR ODD TERMINAL/SIDE 5, 8 3.00 BSC 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. NX b 10 0.30 D NOTES: 9 CORNER OPTION 4X (Nd-1)Xe REF. 0.23 9 7 BOTTOM VIEW C C - Rev. 0 6/04 2 3 6 INDEX AREA L1 - 0.05 Ne NX k 4X P 8 0.80 - e 5 NX b 0.75 - E2 0.08 C SEATING PLANE 0.70 E1 / / 0.10 C NOTES A E 0 4X MAX A1 D2 B TOP VIEW NOMINAL b E 2X 0.15 C A MIN A3 9 2X SYMBOL L1 10 L e 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220WEED-2 Issue C, except for the E2 and D2 MAX dimension. FOR EVEN TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 12 FN6212.1 June 30, 2006