Application Note AN-1077 PFC Converter Design with IR1150 One Cycle Control IC By R. Brown, M. Soldano, International Rectifier Table of Contents Page Introduction ..........................................................................................1 One Cycle Control for PFC Applications ..............................................2 IR1150 Detailed Description.................................................................3 PFC Converter Design Procedure........................................................4 Converter Specifications .................................................................4 Converter Input and Output Variables Defined ...............................4 Converter Schematic Diagram........................................................5 Maximum Input Power and Currents....................................................6 High Frequency Input Capacitor Requirements ...................................6 Boost Inductor Designs ........................................................................6 Output Capacitor Requirements .....................................................7 Control Section Design ...................................................................7 Output Voltage Divider....................................................................7 Output OVP Divider Design ............................................................8 Switching Frequency Selection.......................................................8 Current Loop and Over-current Protection......................................9 Soft Start Design.............................................................................11 Table of Contents continues on next page… www.irf.com AN-1077 cover Voltage Feedback Loop .......................................................................12 Voltage Loop Compensation...........................................................14 Design Tips ..........................................................................................16 IC Decoupling Capacitor .................................................................16 Inductor Design...............................................................................16 Gate Drive Considerations..............................................................17 PCB Layout.....................................................................................17 Additional Noise Suppression Considerations ................................18 This Application Note describes the design methodology of a Continuous Conduction Mode Power Factor Correction circuit utilizing a boost converter and featuring the IR1150S PFC IC. The IR1150 is based on International Rectifier’s proprietary “One Cycle Control” technique for PFC converter control. This application note presents a complete, step-by-step, design procedure including converter specifications and necessary design tradeoffs. www.irf.com AN-1077 cover Application Note AN-1077 PFC Converter Design with IR1150 One Cycle Control IC R. Brown, M. Soldano, International Rectifier This Application Note describes the design methodology of a Continuous Conduction Mode Power Factor Correction circuit utilizing a boost converter and featuring the IR1150S PFC IC. The IR1150 is based on International Rectifier’s proprietary “One Cycle Control” technique for PFC converter control. This application note presents a complete, step-by-step, design procedure including converter specifications and necessary design tradeoffs. For a sinusoidal voltage this can be written as: Topics Covered • • • • • ¾ PF = Power Factor Correction One Cycle Control operation IR1150 Detailed Description Design procedure and example Design Tips Vrms is the line voltage RMS value I rms is the line current RMS value I rms1 For additional data, please visit our website at: http://www.irf.com/product-info/smps/ http://www.irf.com/e/ir1150ppdus.html/ Keywords: PFC, Power Factor Correction, THD, One Cycle Control, OCC Power factor is defined as the ratio of real power to apparent power, where real power is the time integral of the instantaneous power measured over a full period and the apparent power is simply the product of the rms voltage and rms current measured over the entire period. T 1 VIN I IN dt T ∫0 Apparent Power = VinRMS ⋅ I inRMS PF = PREAL PAPPARENT φ (1) (4) is the line current fundamental harmonic is the displacement angle between voltage and current In this case power factor can be split into distortion factor and displacement factor: kD = Introduction Real Power = Vrms ⋅ I rms1 ⋅ cos( φ ) I rms1 = cos( φ ) Vrms ⋅ I rms I rms I rms1 ; kφ = cos( φ ) I rms (5) Phase shift between the voltage and current waveforms is introduced by the reactive nature of the input, either inductive or capacitive. In a purely resistive load, the voltage and current will be sine waves, in phase, true power will equal apparent power and PF = 1. I rms = ∞ ∑I n =1 2 rmsn (6) (2) (3) International Rectifier Technical Assistance Center: THD = 2 2 I rms − I rms 1 2 I rms1 USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 (7) 1 of 18 Application Note AN-1077 One Cycle Control for PFC Applications The operation of the one cycle control is analyzed in detail in several papers [3][4][5]. The converter output voltage Vo is scaled down thru the output divider and is presented at the input of the error amplifier VFB. The error amplifier is used to provide loop compensation and to generate the error signal or modulation voltage Vm. VFB Vm Figure 3 - Resettable integrator characteristic VREF Cz Cp Rgm An important characteristic is that integration time constant of the integrator must match the switching period, so that at the end of each cycle the ramp will match the integrated value. Figure 1 - Error Amplifier The core of the One Cycle control is a resettable integrator. This block integrates the modulation voltage and is reset at the end of every switching cycle. Figure 4 - PWM Signal Generation Figure 2 - Core of the One Cycle Control Since the voltage loop bandwidth is very small the modulation voltage will vary very slowly and can be considered constant during a switching cycle. This means that the output of the integrator will be a linear ramp. The slope of the integrator ramp is directly proportional to the output voltage of the error amplifier, vm . International Rectifier Technical Assistance Center: The reference for the PWM comparator is obtained by subtracting the voltage across the current sense resistor from the modulation voltage: vm − GDC ⋅ vSNS (8) This is the required input configuration to the general OCC PWM in order to properly control the boost converter with trailing edge modulation. By providing a reference threshold dependant on the input current and a ramp signal dependant on the output voltage, the required control of the converter duty cycle is realized to achieve output voltage regulation and power factor correction. USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 2 of 18 Application Note AN-1077 This control technique does not require direct line voltage sensing: the line voltage information is contained in the inductor current. IR1150 Detailed Description The IR1150 control IC is intended for boost converters for power factor correction operating at a fixed frequency in continuous conduction mode. The IC operates with essentially two loops, an inner current loop and an outer voltage loop. The inner current loop sustains the sinusoidal profile of the average input current based on the dependency of the pulse width modulator duty cycle on the input line voltage, to determine the analogous input line current. Thus, the current loop exploits the imbedded input voltage signal to command the average input current following the input voltage. This is true so long as operation in continuous conduction mode is maintained. There will be some amount of distortion of the current waveform as the line cycle migrates toward the zero crossing and as the converter operates at very light loads given that the inductor has a finite inductance. The resultant harmonic currents under these operating conditions will be well within the Class D specifications of EN61000-3-2, and therefore not an issue. The outer voltage loop controls the output voltage of the boost converter and the output voltage error amplifier produces a voltage at its output, which directly controls the slope of the integrator ramp, and therefore the amplitude of the average input current. The combination of the two control elements controls the amplitude and shape of the input current so as to be proportional to and in phase with the input voltage. The IC employs protection circuits providing for robust operation in the intended application and protection from system level over current, over voltage, under voltage, and brownout conditions. The UVLO circuit monitors the VCC pin and maintains the gate drive signal inactive until the VCC pin voltage reaches the UVLO turn on threshold, VCC ON. The Open Loop Protection (OLP) prevents the controller to operate if the voltage on the feedback pin hasn’t exceeded 20% of its nominal value. If for some reason the voltage control loop is open, the IC will not start, avoiding a potentially catastrophic failure. International Rectifier Technical Assistance Center: Figure 5 - Output Protections As soon as the VCC voltage exceeds this threshold, provided that the VFB pin voltage is greater than 20%VREF, the gate drive will begin switching. In the event that the voltage at the VCC pin should drop below that of the UVLO turn off threshold, VCC UVLO , the IC then turns off, gate drive is terminated, and the turn on threshold must again be exceeded in order to re start the process. A dedicated programmable Over Voltage Protection pin (OVP) is available for to protect the output from overvoltage. The PFC voltage feedback loop is usually very slow. If the output voltage exceeds the set OVP limit, the gate drive will be disabled, until the output voltage will approach again its nominal value. Finally an Output Under Voltage protection OUV is provided: in case of overload or brown out, the converter will automatically limit the current: as a result the output voltage will drop. If the drop exceeds 50% of the nominal output voltage, the controller will shut down and restart. The oscillator is designed such that the switching frequency of the IC is programmable via an external resistor at the FREQ pin. The design incorporates min/max restrictions such that the minimum and maximum operating frequency shall fall within the specified range of 50kHz to 200kHz. It is generally possible to run the IC at a lower switching frequency, but given the large value of the programming resistor that may lead to inaccurate frequency trimming, outside the range of tolerance specified on the Data Sheet. An additional feature of the IR1150S is the ability to force the IC into a “sleep” mode. In the sleep mode, the internal blocks of the IC are disabled and the IC draws a very low quiescent current of 200µA. This is a desirable feature designed to reduce system USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 3 of 18 Application Note AN-1077 power dissipation to an absolute minimum during a standby mode, or to shut down the converter at the discretion of the system designer. The sleep mode is activated any time the OVP pin, (pin 4), is at a voltage level lower than 0.62V (typ). The gate drive output provides sufficient drive capability to efficiently drive MOS gated power switches typical of the application. Operating Temperature Nominal DC Output Voltage Maximum DC Output Voltage Minimum Output Holdup Time 385V 425VDC 30msec @ 285VO Converter Switching Frequency 100kHz Maximum Soft Start time 50msec Converter Input and Output Variables Defined Figure 6 - IR1150S Pinout PFC CONVERTER DESIGN PROCEDURE This section describes a typical design procedure for a Continuous Conduction Mode boost converter for power factor correction using the IR1150S control IC. Additionally, some of the design tradeoffs typical of PFC converter design are discussed. A schematic diagram is presented as a reference to a step by step design procedure for designing a typical 300W PFC converter. An IR1150S Demo Board [2] is available from International Rectifier which highlights the performance of the IR1150 and was designed in accordance with the design procedure presented in this application note. POUT(MAX) Maximum converter output power delivered to load PIN(MAX) Maximum converter input power drawn from AC source ηMIN Minimum worst case efficiency of converter IIN(RMS)MAX Maximum rms value of input current drawn from AC source IIN(PK)MAX Maximum peak value of input current drawn from AC source IIN(AVG)MAX Maximum average value of input current drawn from AC source VIN(RMS)MIN Minimum rms value of input voltage supplied by AC source VIN(PK)MIN Minimum peak value of input voltage supplied by AC source Converter Specifications AC Input Voltage (rms) Input Line Frequency 85V(min) - 264V(max) 47-63Hz Target Efficiency 92% min @ 90VAC / 300W Power Factor (PF) 0.99 min @ 115VAC / 300W Harmonic Distortion 4% max @ 115VAC / 300W AC Inrush Current (peak) 35A max @ 230VAC / 300W Maximum Ambient 50°C International Rectifier Technical Assistance Center: USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 4 of 18 Vin Rth D1 1 + 4 International Rectifier Technical Assistance Center: F1 t 2 3 Cin Rsf Rs Csf Rf 4 3 2 1 VFB OVP COMP ISNS FREQ VCC COM GATE IR1150S L1 8 Cb5 5 6 7 + D3 Cb4 Dg2 Rg1 Dg1 Cz Rgm Rg2 Cp Rg3 Q1 D2 Rd Cd Rfb3 Rfb2 Rfb1 Q2 Rslp1 Rslp2 Rovp3 Rovp2 Rovp1 + Vsleep RTN Cout Vout Application Note AN-1077 Converter Schematic Diagram USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 5 of 18 Application Note AN-1077 Where: Maximum Input Power and Currents Majority of the converter design is based on low line current. That’s the worst case condition for efficiency and input currents. k∆IL = Inductor current ripple factor (30% in this design) r = maximum high frequency voltage ripple factor (∆VIN/VIN), typically between 3% – 9%, 6% used for this design. (Assume PF to be 0.99 or greater at low line) Maximum input power can be calculated assuming a nominal efficiency at low line: PIN ( MAX ) = PO( MAX ) η MIN = 300W = 326W 0.92 The maximum rms AC line current is calculated at the minimum input AC voltage: I IN ( RMS ) MAX = I IN ( RMS ) MAX PO ( MAX ) Assuming sinusoidal AC current, the peak value of the AC current can be calculated: I IN ( PK )MAX = I IN ( AVG ) MAX = Boost Inductor Design Power switch duty cycle must be determined at VIN(PK)MIN. This will represent the peak current for the inductor, at the peak of the rectified line voltage at minimum line voltage. VIN ( PK )MIN = 2 × VIN ( RMS )MIN = 120V VIN ( RMS ) MIN 1.414( 326W ) = 5 .4 A 85V I IN ( AVG ) MAX = 2 × I IN( PK )MAX π 2 × 5.4 A π = 3.4 A High Frequency Input Capacitor Requirements C IN = 0.3 This capacitor can be considered part of the EMI input filter: its main purpose is to bypass the high frequency component of the input current with the shortest possible loop. 2 ( PIN ( MAX ) ) The AC Line input average current can be calculated assuming sinusoidal waveform: C IN = k ∆I L High frequency capacitor is typically a high quality film capacitor rated at beyond the worst case peak of the line voltage. Care must be taken to avoid too large a value as this will introduce current distortion. η MIN (VIN ( RMS ) MIN ) PF 300W = = 3 .8 A 0.92(85V )0.998 I IN ( PK )MAX = CIN = 0.330µF, 630V I IN ( RMS ) MAX 2π × f SW × r × VIN ( RMS ) MIN 3.8 A = 0.335µF 2π × 100kHz × 0.06 × 85V International Rectifier Technical Assistance Center: D= VO VIN ( PK ) MIN VO = 385V − 120V = 0.69 385V ∆I L = 0.2 × I IN ( PK ) MAX = 0.2 × 5.4 A ≅ 1.1A ∆I L 1.1A = 5.4 A + ≅ 6A 2 2 VIN ( PEAK ) MIN × D 120V × 0.69 = = 752.7 µH f SW × ∆I L 100kHz × 1.1A I L( PK )MAX = I IN ( PK )MAX + LBST ∆IL is based on the assumption of 20% ripple current. This is another area where design tradeoffs must be considered. A smaller value of ripple current would be beneficial in terms of reduced distortion, output capacitor USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 6 of 18 Application Note AN-1077 ripple current at fSW , peak current in the power switch and EMI CONTROL SECTION DESIGN However the trade-off here is an increased inductance value to support the reduced ripple current, resulting in increased size and cost. Output Voltage Divider Care must be taken for a given core selection within a given design that the core does not saturate at peak current levels. Conversely, a higher value of allowable ripple current, while resulting in a lower required inductor value, will negatively impact performance in the areas previously pointed out. Cost trade-offs are typical for core materials vs. dissipation, temperature, and inductance roll off with increasing current levels. Consult core manufacturer’s data books and application notes for detailed inductor design considerations. Detailed inductor design is beyond the scope of this application note. Output Capacitor Requirements Output Capacitor design in PFC converters is typically based on hold up time requirements. Typically, with a proper design, ripple voltage and current in the capacitor will not be an issue. Typical values of capacitor for PFC applications are 1µF to 2µF per watt of output power. COUT ( MIN ) = 2 ⋅ PO ⋅ ∆t 2 2 VO − VO( MIN ) (9) Output voltage of the converter is set by voltage divider RFB1, RFB2, and RFB3. The total impedance of this divider string should be selected high enough in value so as to reduce power dissipation in divider. This is of particular concern in terms of meeting stringent standby power specifications, and beneficial in optimizing overall system efficiency. Practical limits do exist however on the maximum impedance of the divider string. The resistor values must not be selected so high as to introduce excessive additional voltage error to the output voltage error amplifier resulting from input bias currents of the amplifier. A reasonable compromise for divider string overall impedance is a target of approximately 1MΩ. RFB1 and RFB2 are typically split equally in value to create the upper resistor in the divider to keep the maximum voltage across each resistor within the voltage rating of these devices, (typically 250V). Divider resistors are selected with a ±1% tolerance in order to minimize output voltage set point error. The resistor tolerances will stack up in addition to tolerance of the error amplifier reference and the error introduced to the error amplifier due to input bias currents and input offset voltage. RFB1 = RFB2 = 499KΩ, 1% tolerance. COUT ( MIN ) = 2 ⋅ 300W ⋅ 30ms = 269µF ( 385V )2 − ( 285V )2 Minimum capacitor value must be derated for capacitor tolerance, -20% in this case, in order to guarantee minimum capacitance requirement is satisfied, thus assuring minimum hold up time. C OUT = C OUT ( MIN ) 1 − ∆CTOL = 269µF = 336µF 1 − 0.2 Standard value of 330µF is used in this case. International Rectifier Technical Assistance Center: This is a standard 1% value. RFB 3 = RFB 3 = VREF ( RFB1 + RFB 2 ) ( Vout VREF ) (10) 7.0V ( 998K ) = 18.48KΩ ( 385V - 7.0V ) (use standard value RFB3 = 18.5kΩ) Calculate new VO value based on actual resistor values USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 7 of 18 Application Note AN-1077 VOUT = VOUT = ( RFB1 + RFB 2 + RFB 3 ) ⋅ VREF RFB 3 (11) ( 998 K + 18.5K) ⋅ 7.0V = 384.6V 18.5K Calculate power dissipation of divider resistors PRFB1 = PRFB 2 PRFB1 = PRFB 2 = (V − VREF )2 = out 2(RFB1 + RFB 2 ) (12) (385V − 7V )2 = 70mW VFB VOVP 7.49V 450mV VREF 7.0V normal 2 × 998kΩ OVP normal Having OVP function on a separate pin allows programming the threshold to the desired value: Output OVP Divider Design Use caution in OVP set point with regard to setting threshold too high. Output capacitors are typically rated at 450V and caution should be exercised so as not to allow VO to exceed their maximum voltage rating. Output capacitor surge voltage ratings are intended as a guard band in terms of abnormal operating conditions and shouldn’t be use as target spec for OVP. An over voltage threshold of 425V is an adequate design target. The same issues, with regard to power dissipation and total impedance of the divider string in the output voltage feedback divider, apply to the OVP divider. Power dissipation of the individual resistors is calculated using the same method as was used in the output voltage feedback divider, as are the resistor values. The IR1150S over voltage comparator has a dedicated internal reference voltage, the value of which is a fixed percentage of the output error amplifier reference. V( REF )OVP = 1.07 ⋅ VREF = 7.49V When the OVP threshold is triggered, the IC will disable the gate drive signal. The comparator has a built in hysteresys of 450mV typ. (see data sheet ‘protection section’). (13) If the same divider string is used as for the voltage feedback, the resulting OVP voltage threshold will be set at 7% higher than the nominal output voltage. VOVP = 1.07 ⋅ VOut = 412V International Rectifier Technical Assistance Center: VOVP = ( ROVP1 + ROVP 2 + ROVP 3 ) ⋅ V( REF )OVP ROVP 3 (14) To design OVP the divider for an over voltage level of 425V as per target specifications of the converter: ROVP1 = ROVP2 = 499kΩ, 1% ROVP 3 = ROVP3 = VREF ( OVP )( ROVP1 + ROVP 2 ) VOVP V( REF )OVP (15) 7.49V ( 998K ) = 17.9 KΩ ( 425V 7.49V ) Verify the new VOVP value based on actual resistor value VOVP = ( 998 K + 17.9 K )7.49V = 425V 17.9 K Power dissipation of ROVP1 and ROVP2 will be the same as RFB1 and RFB2 given that they are the same values. Switching Frequency Selection Switching frequency is user programmable with the IR1150 and is accomplished by selecting the USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 8 of 18 Application Note AN-1077 value for Rf. As such, selection of switching frequency is at the discretion of the user with consideration to overall converter design, with particular consideration of EMI and efficiency requirements. There are essentially two levels of current limitation provided by the IR1150. There is a “soft” current limit, which is essentially a duty cycle limiting fold back type: the converter duty cycle is limited to the point where output power is limited and the output voltage begins to decrease. There is also a “peak” current limit feature which immediately terminates the present drive pulse once the peak limit threshold, ≈ -1.0V, is exceeded. The current sense resistor is selected based at minimum input voltage and maximum output power in order to guarantee normal operation under this condition. The current amplifier has a DC gain GDC=2.5, is internally compensated and bandwidth limited above 280kHz. The operation of the OCC control IC is based on peak current mode, therefore the switch current can be used in alternative to the inductor current as an input to the ISNS pin. The range for the current sense voltage VSNS is between 0V and -1V, and care must be taken when using a current transformer, to meet this range. Figure 7 - Oscillator Frequency vs. Programming Resistor Rf Vm A chart plotting Rf value vs. frequency is provided to determine the appropriate resistor value for the desired switching frequency. Typical design tradeoffs relative to switching frequency must be carefully considered when selecting an optimum switching frequency for a particular converter design. Some key considerations would be; Optimized inductor size, power dissipation, and cost EMI requirements, (EN55011, lower limit of 150kHz) Switching loss in the power switch increase with switching frequency For the design example of this application note, we will select the switching frequency to be 100kHz, a good tradeoff between EMI performance, optimized inductor, and power switch losses. Current Loop and Overcurrent Protection The current sense pin ISNS is the input to the current sense amplifier and the overcurrent protection comparator. International Rectifier Technical Assistance Center: GDCRSIS Vm Vm - GDCRSIS Vm time VGATE time Ton Ts Figure 8 - Ramp relation with duty cycle The current sense resistor determines the point of soft over-current, that is the point at which input current will be limited and the output voltage will drop. The worst case is at low line when the current is the highest and also the boost factor of the converter is higher. The current sense resistor RS must be designed so that at the lowest input line and largest load, the converter will be able to maintain the output voltage. USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 9 of 18 Application Note AN-1077 The required duty cycle at the peak of the sinusoid for desired output voltage at minimum input voltage is given by: D= D= Vout − VIN ( PK )MIN Vout (16) 385V − 120V = 0.69 385V But when Vm saturates to its maximum, an additional increase in current will limit the duty cycle, therefore causing the output voltage to drop. It can be seen from Figure 8 that duty cycle is determined at each cycle as the ratio: VSNS (max) = vm( SAT )( 1 − D ) GDC (17) (18) The required voltage across the current sense resistor to set the “soft” current limit at minimum input voltage is: VSNS (max) = VSNS (max) = VCOMP( EFF ) ⋅ ( 1 − D ) GDC (19) 6.05V ⋅ (1 − 0.69) = 0.75V 2.5 The vm saturation voltage VCOMP(EFF) and the current amplifier DC gain are taken directly from the data sheet (page 4). Now the value of the sense resistor can be calculated from the max peak inductor current derated with an overload factor (KOVL=10%) I IN ( PK )OVL = [ I IN ( PK ) max + ∆I L ] K OVL (20) 2 International Rectifier Technical Assistance Center: 1.1 ]( 1.1 ) = 6.55 A 2 From this maximum current level and the required voltage on the current sense pin, we now calculate the resistor value. RS = When the input voltage is lowered (or the load increased) the voltage loop responds by increasing the modulation voltage Vm. vm − GDC ⋅ VSNS Ton = =D vm TS I IN ( PK )OVL = [ 5.4 A + VSNS (max) I IN ( PK )OVL = 0.75V = 0.115Ω 6.55 A A standard value of 100mΩ can be used: power dissipation in the resistor is now calculated based on worst case rms input current at minimum input voltage: 2 PRS = I IN ( RMS ) MAX ⋅ RS (21) PRS = 3.82 ( 0.100Ω ) = 1.45W Proper derating guidelines dictate a selected value of RS = 0.10Ω, 3W (non inductive resistor). Although the One Cycle Control already provides a cycle by cycle peak current limiting, an additional fast over-current comparator is present for increased protection. If the threshold is reached the current pulse will be terminated. The system will enter into “peak” current limit should the peak input current exceed; I PK _ LMT = − 1.0V 0.100Ω = 10 A Current Sense Filtering The current amplifier is internally compensated with a pole at approximately 280 kHz in order to attenuate the high frequency switching noise often associated with peak current mode control. Blanking time is also provided in order to avoid spurious triggering of the overcurrent protection due to the boost diode reverse recovery spike. Additional external filtering is typically employed in systems operating with peak current mode control, USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 10 of 18 Application Note AN-1077 and may be incorporated with a simple RC filter scheme as shown in schematic diagram. f PSF = 1 (22) 2π ⋅ RSF ⋅ C SF t SS = 2 3 4 Rsf Csf COM GATE FREQ VCC ISNS VFB OVP COMP CZ = 8 7 6 Rs Figure 9 – Current Sense Resistor and Filtering A corner frequency around 1-1.5MHz is recommended. Typical values for the RC filter are: (23) t SS ⋅ iOVEA VCOMP( EFF ) (24) iOVEA and VCOMP(EFF) are taken from the datasheet. 5 Rf iEA−OUT ( MAX ) Since Cp is generally much smaller than CZ, its effect can be neglected. IR1150S 1 CZ ⋅ VCOMP( EFF ) CZ = 50ms × 40µA = 0.33µF 6.05V t ss = 0.33µF ⋅ 6.05V = 50ms 40µA This represents the time needed by the controller to reach full duty cycle capability in the startup phase. The peak current will be limited during this period of time. RSF = 100Ω (also provides additional current limiting into current sense pin during inrush and transients) CSF = 1000pF These component values offer a decent compromise in terms of filtering, (fP ≈ 1.59MHz), while maintaining the integrity of the current sense signal thus maintaining peak current mode control. It should be noted that the input impedance of the current amplifier is approximately 2.2KΩ. The 100Ω resistor will form a divider with this 2.2KΩ resistor thus affecting the actual threshold for the soft current limit. The actual voltage at the current limit amplifier input will in effect be approximately 96% of the voltage across the current sense resistor. Soft Start Design Soft start is controlled by the rate of rise of the error amplifier output voltage, which is a function of the compensation capacitors Cz and Cp, and the maximum available output current of the error amplifier. Soft start time is determined by the following equation: International Rectifier Technical Assistance Center: USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 11 of 18 Application Note AN-1077 v̂o VOLTAGE FEEDBACK LOOP îchg VIN r = RL CO RL VO POWER STAGE G(s) d Figure 11 - Small Signal low frequency model for the boost power stage VREF vm OCC Modulator H3(s) ERROR AMPLIFIER H2(s) Definitions: VFB RL : Load Resistance Output Divider H1(s) CO : Output (bulk) capacitor Figure 10 - Voltage Loop v̂m : Modulation Voltage – this is the output of the Voltage The open loop gain is given by the product: Error Amplifier T ( s ) = G( s ) ⋅ H1( s ) ⋅ H 2 ( s ) ⋅ H 3 ( s ) (25) GDC : DC gain of the current amplifier – it is set internally the IC at 2.5V/V Vin : Peak value of input voltage (i.e. VinRMS max ⋅ 2 ) OUTPUT DIVIDER: H1( s ) The output divider scales the output voltage to be compared with the reference voltage in the error amplifier. Therefore: VOUT = ( RFB1 + RFB 2 + RFB 3 )VREF RFB 3 H1( s ) = VREF Vo (26) For a constant power load the actual RL is negative. This is the typical case when the PFC load is a DC-DC stage: if the input voltage of that stage is reduced it will react by increasing the current, in order to maintain the output power constant. In this case RL will cancel with r and will yield: v̂o 1 = îchg sCo (27) This stage simply attenuates the output voltage signal, by a fixed amount: H1 = 0.018 = −34.8dB POWER STAGE: H 3 ( s ) ⋅ G( s ) (28) When a purely resistive load is present we have: v̂o RL / 2 = îchg 1 + sC RL o 2 (29) We will not consider the resistive load case here, since in the majority of cases the PFC load is the input of another DC-DC converter. The low frequency small signal equivalent circuit for the boost power stage is shown in Figure 11. An explanation of this model can be found in [7][8]. International Rectifier Technical Assistance Center: USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 12 of 18 Application Note AN-1077 In order to derive îchg v̂m we need to look at the v̂o V2 1 = 2 in ⋅ v̂m Vo ⋅ RS ⋅ GDC sCo OCC PWM modulator. The control law is: GDC ⋅ RS ⋅ îg = Where M( d ) = The control to output for the constant power load case is: v̂m M( d ) (30) v̂o v̂g (35) The power stage gain varies as expected with the input voltage. ERROR AMPLIFIER: H 2 ( s ) v̂ g = Vin + v̂in (31) The output voltage error amplifier in the IR1150 control IC is a transconductance type amplifier. Substituting and eliminating the small signal cross terms: îg v̂m = Vin Vo RS GDC (32) 40 Gain 20 0 Figure 13 - Error Amplifier 20 The transfer function is: 40 0.1 1 10 3 100 1 .10 frequency 4 1 .10 5 6 1 .10 1 .10 Figure 12 - Power Stage Gain @ 90V (red) and 265V (blue) The output average current can be calculated from the input current: î ⋅ V p̂ îg = in = chg o Vin Vin îchg v̂m = 2 in V Vo2 RS GDC (33) H 2( s ) = g m ⋅ ( 1 + sRgmC Z ) s( C Z + C P + sRgmC Z C P ) The compensation network shown on the schematic diagram adds a zero and a pole in the transfer function at: International Rectifier Technical Assistance Center: 1 2π ⋅ Rgm ⋅ C Z (37) 1 Cz ⋅ Cp 2π ⋅ Rgm Cz + Cp (38) fZ0 = f P0 = (34) (36) USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 13 of 18 Application Note AN-1077 GVA − H 1 = −6.2dB Voltage Loop Compensation Typical of PFC converters is the requirement to keep the voltage loop bandwidth less than ½ the line frequency in order to avoid distortion of the line current resulting from the voltage loop attempting to regulate out the 120Hz ripple on the output. There is of course, the associated tradeoff between system transient response and input current distortion, where stability of the voltage loop is generally easily achieved. The goals of the voltage loop compensation are the limitation of the open loop gain bandwidth to less than ½ the AC line frequency and the amount of second harmonic ripple injected in the COMP pin from the error amplifier. First we need to calculate the amount of second harmonic ripple on the output capacitor: VOPK = VOPK = Pin 2π ⋅ f 2 nd ⋅ CO ⋅ Vout (39) The amount of 120Hz ripple needs to be small compared with the value of the error amplifier output voltage swing. A percentage around 1% is typical and will minimize distortion: GVA = VCOMP( EFF ) ⋅ 0.01 2 ⋅VOPK H 2( s ) ≅ g m ⋅ ( 1 + sRgm C Z ) (41) sC Z Since CZ has already been determined for the soft start, only Rgm needs to be calculated by forcing: H 2 ( j 2π ⋅ f 2 nd ) = −6.2dB 2 G − H1 1 − R gm = VA g 2 π ⋅ f 2 nd ⋅ C Z m (42) 2 (43) Substituting: Rgm = 8.9kΩ 330W = 3.4V 2π ⋅120 ⋅ 330µF ⋅ 385V GVA = The second pole is usually placed at a much higher frequency than 120Hz, so the error amplifier transfer function can be approximated to: (40) The second pole frequency should be chosen higher than the cross over frequency and significantly lower than the switching frequency in order to attenuate noise: typical value is 1/6 to 1/10 of the switching frequency: f P0 = 1 1 (44) ≅ Cz ⋅ Cp 2π ⋅ Rgm ⋅ Cp 2π ⋅ Rgm Cz + Cp Cp = 1 = 1nF 2π ⋅ 8.9kΩ ⋅17 kHz 6.05V ⋅ 0.01 = 0.089 = −41dB 2 ⋅ 3.4V As calculated from (26) the attenuation of the output divider is already: H1 = 0.018 = −34.8dB The gain of the error amplifier @ 120Hz needs to be: International Rectifier Technical Assistance Center: USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 14 of 18 40 100 20 50 Gain GEA Application Note AN-1077 0 20 50 40 0.1 1 10 3 4 100 1 .10 frequency 5 1 .10 100 6 1 .10 1 .10 0.1 Figure 14 - Error Amplifier Gain 1 10 3 4 100 1 .10 frequency 1 .10 5 1 .10 6 1 .10 Figure 16 - Loop Gain @ 90V (blue), 265V (red) Crossover frequency is between 10Hz and 30Hz, depending on the input AC line value, as required. 0 10 20 0 30 20 40 40 50 60 60 Phase Phase 0 70 80 80 100 120 90 0.1 1 10 3 100 1 .10 Frequency 4 1 .10 5 1 .10 6 1 .10 140 160 Figure 15 - Error Amplifier Phase Finally the loop gain can be drawn: International Rectifier Technical Assistance Center: 180 0.1 1 10 100 1 .10 frequency 3 4 . 1 .10 5 1 .10 1 .10 6 Figure 17 - Loop Phase USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 15 of 18 Application Note AN-1077 Design Tips IC Decoupling Capacitor The PFC converter is a harsh environment for the controller in terms of noise and as such, certain precautions must be considered with regard to proper noise decoupling. The key element to proper bypassing of the IC is the physical location of the bypass capacitor and its connections to the power terminals of the control IC. Inductor Design There is more to consider than merely inductor value when it comes to designing the boost choke. The mechanical design of the choke can have a significant impact on system level noise due to associated parasitic elements. The parasitic inter-winding capacitance associated with the boost inductor can resonate and generate high frequency ringing. In order for the capacitor to provide adequate filtering, it must be located as close as physically possible to the VCC and COM pins and connected thru the shortest available path. Note the location (Figure 18) of the bypass capacitor directly above the SO8 IC which will provide for the shortest possible traces from the capacitor to the VCC and COM pins. This is crucial in providing the tightest decoupling path possible and minimizing any possible noise pickup due to excessive trace lengths. Figure 19 - Ringing on turn on Figure 18 - Proper connection of decoupling capacitor The value of the decoupling capacitor will depend on several factors, including but not limited to switching frequency, power MOS gate drive capacitance and external gate resistance. As a general rule a 470nF ceramic capacitor is recommended. This assumes a larger electrolytic capacitor is still present to provide low frequency filtering. International Rectifier Technical Assistance Center: Figure 20 - Single layer choke Figure 19 shows the power MOSFET turn on current when a multi layer, non optimized boost choke is used. The presence of a high frequency ringing (around 8-10MHz) can be noted. In Figure 20 a single USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 16 of 18 Application Note AN-1077 layer inductor with the same value, but lower interwinding capacitance is used. If not controlled this ringing can produce unacceptable voltages to the sensitive pins of the control IC, which can disrupt proper circuit operation. Although an internal blanking circuit is present to limit the effects of the diode reverse recovery peak on the current loop, it is recommended to add an RC cell on the current sense resistor to increase noise immunity of the control IC. Another extremely good reason to control the ringing is to limit the Electro Magnetic Interferences (EMI), especially in the radiate range Gate Drive Considerations The gate driver of the IR1150S is capable of extremely rapid rise and fall times in addition to the 1.5A peak source and sink current capability. These rapid rise and fall capabilities, while providing for an extremely desirable MosFet drive capacity, can also create noise issues if not properly controlled. Often times it is difficult to meet EMI requirements when drive speeds are too fast resulting in fast rising dI/dt and dV/dt edges. This not only taxes the EMI filter, but can introduce additional noise that the controller is forced to deal with. The waveforms of Figure 21 and Figure 22 below illustrate the gate drive voltage of the IR1150S vs. the power MosFet drain current for an IRFP27N60K power switch. Figure 21 - IR1150S Gate Drive voltage International Rectifier Technical Assistance Center: Figure 22 - IR1150S Gate Drive voltage The rise time must be carefully controlled by virtue of proper selection of gate drive resistors for a specific application. Parasitic elements, both capacitive and inductive, printed circuit board layout, thermal design, system efficiency, and power switch selection are but some of the criteria which is to be considered when selecting the proper drive impedance for a given design. Improper attention to proper gate drive design will most certainly result in performance and noise issues. PCB Layout Proper routing of critical circuit paths is elemental in optimum circuit performance and minimal system noise. Parasitic inductance resulting from long trace length in the power path can introduce noise spikes which can deteriorate performance to unacceptable levels. In addition to creating unwanted system noise, these spikes can decrease reliability of power devices and if severe enough, can be destructive to the point of catastrophic failure of the devices. At the very least, uncontrolled parasitic elements as a consequence of inadequate attention to printed circuit board layout will force the designer to control the additional noise and voltage spikes with additional circuitry, adding cost and decreasing efficiency. It is therefore desirable to pay particular attention to optimizing the PCB layout in terms trace routing, placement, and length, in the critical circuit paths. Proper grounding and utilization of ground planes are helpful within the control section while minimized trace lengths are deUSA ++1 310 252 7105 Europe ++44 (0)208 645 8015 17 of 18 Application Note AN-1077 sirable in the high voltage and current switching paths of the power section. Additional Noise Suppression Considerations The PFC boost diode reverse recovery characteristic is an enormous contributor to system noise both conducted and radiated. This will tax the EMI filter in addition to basic circuit functionality and reliability. There are other considerations besides noise, efficiency for example. The power switch must absorb all the reverse recovery current during its turn on period and therefore must also dissipate the resultant additional power. Consequently, there is additional burden on system level overall efficiency as well as the increased noise levels. SiC diodes provide an excellent solution to address these issues as reverse recovery time is virtually zero, thus there are essentially no reverse recovery currents to be dealt with. While the SiC appears to be the salvation of the PFC boost converter, there are considerations such as surge current capabilities that must be addressed before the SiC diode becomes the mainstay of PFC converter design. [8] [9] [10] [11] [12] [13] Aerospace and Electronic Systems, Vol 26, No. 3, May 1990, pp 490-505 R.B. Ridley, “Average small-signal analysis of the boost power factor correction circuit” VPEC Seminar Proceedings, 1989, pp 108-120 Chen Zhou, M.M. Jovanovic, “ Design Trade-offs in continuous current-mode controlled boost power-factor correction circuits” High-Frequency Power Conversion Conference Proceedings, pp.209-220, 1992 R.Brown, M.Soldano, “One Cycle Control IC Simplifies PFC Designs”, APEC ’05 Conference Proceedings R. Brown, B.Lu, M.Soldano, “Bridgeless PFC implementation using One Cycle Control Technique”, Apec’05 Conference Proceedings. K.M.Smedley, U.S. Patent 5,278,490 “One Cycle Controlled Switching Circuit” L.Dixon, “High Power Factor Preregulator for OffLinePower Supplies”, Unitrode Design Seminars Manual, SEM-700, 1990 Rev.2.3 – June 2005 In the meantime, a simple RC snubber across the boost diode goes a long way in reducing the noise due to reverse recovery. When properly designed, the snubber will be less dissipative then allowing the full reverse recovery current absorbed by the power switch. References [1] [2] [3] [4] [5] [6] [7] IR1150S Data Sheet – International Rectifier Corp., 2005 IRAC1150-300W – CCM Boost Converter for PFC Demo Board Documentation, International Rectifier Corp. 2005. K.M.Smedley, S.Cuk, “One-Cycle Control of Switching Converters” Z. Lai, K.M. Smedley, “A Family of Continuous Conduction Model Power Factor Correction Controllers Based on the General Pulse Width Modulator”, IEEE Trans. On Power Electronics, Vol.13, No.2, 1988 L.M.Smith, Z.Lai, K.M.Smedley, “A New PWM Controller with One-Cycle Response”, IEEE APEC’97 Conference Proceedings, Vol.2, pp.970-976 K.M. Smedley, S. Cuk, “Dynamics of One-Cycle Control Cuk Converters”, IEEE Trans. On Power Electronics,vol.10, No.6, Nov. 1995 V.Vorperian, “Simplified analysis of PWM converters using the model of e PWM switch: parts I and II” IEEE Trans. On International Rectifier Technical Assistance Center: USA ++1 310 252 7105 Europe ++44 (0)208 645 8015 18 of 18