PRELIMINARY ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR GENERAL DESCRIPTION Features The ICS871004I-04 is a high perfor mance ICS Differential-to-0.7V Differential Jitter Attenuator HiPerClockS™ designed for use in PCI Express™ systems. In some PCI Express systems, such as those found in desktop PCs, the PCI Express clocks are generated from a low bandwidth, highphase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS871004I-04 has 3 PLL bandwidth modes: 200kHz, 400kHz and 800kHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 400kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 800kHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. The ICS871004I04 can be set for different modes using the F_SEL pins as shown in Table 3C. • Four 0.7V differential output pairs The ICS871004I-04 uses IDT’s 3rd Generation FemtoClockTM PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express addin cards. PLL BANDWIDTH • One differential clock input • CLK and nCLK supports the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL • Output frequency range: 98MHz - 640MHz • Input frequency range: 98MHz - 128MHz • VCO range: 490MHz - 640MHz • Cycle-to-cycle jitter: 19ps (typical) • Additive phase jitter, RMS: 0.23ps (typical) • 3.3V operating supply • Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs • -40°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BW_SEL[1:0] 0 0 = PLL Bandwidth: ~200kHz 0 1 = PLL Bandwidth: ~400kHz (default) 1 0 = PLL Bandwidth: ~800kHz 1 1 = PLL BYPASS BLOCK DIAGRAM + IREF OE PIN ASSIGNMENT Pullup F_SEL[1:0] Pulldown BW_SEL[1:0] Pulldown:Pullup 2 2 Control Logic Q0 nQ0 CLK Pulldown nCLK Pullup Phase Detector VCO 490 - 640MHz M U X 0 0 ÷5 Q1 (default) nQ1 0 1 ÷4 1 0 ÷2 1 1 ÷1 ÷5 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q0 VDD Q1 nQ1 Q3 nQ3 BW_SEL1 F_SEL1 GND GND nCLK CLK Q2 ICS871004I-04 nQ2 24-Lead TSSOP Q3 4.40mm x 7.8mm x 0.92mm package body nQ3 MR Pulldown nQ0 nQ2 Q2 VDD IREF GND MR BW_SEL0 VDDA F_SEL0 VDD OE G Package Top View The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification. Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice. IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 1 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY TABLE 1. PIN DESCRIPTIONS Number Name 1, 24 nQ0, Q0 Output Type Differential output pair. PCI Express interface levels. 2, 3 nQ2, Q2 Output Differential output pair. PCI Express interface levels. 4, 11, 23 VDD Power 5 IREF Input 6, 15, 16 GND Power 7 MR Input 8 BW_SEL0 Input 9 10 , 17 VDDA F_SEL0, F_SEL1 Power 12 OE Input Input Description Core supply pin. A fixed precision resistor (475Ω) from this pin to ground provides a reference current used for differential current-mode QAx/nQAx and QBx/nQBx clock outputs. Power supply ground. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs (nQx) to go low and the inver ted outputs Pulldown (Qx) to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Pullup See Table 3B. Analog supply pin. Frequency select pins. LVCMOS/LVTTL interface levels. Pulldown See Table 3C. Output enable pin. When HIGH, the outputs are active. When LOW, the Pullup outputs are in a high impedance state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. 13 CLK Input 14 nCLK Input 18 BW_SEL1 Input 19, 20 nQ3, Q3 Output Inver ting differential clock input. Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels. Pulldown See Table 3B. Differential output pair. PCI Express interface levels. 21, 22 nQ1, Q1 Output Differential output pair. PCI Express interface levels. Pullup NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLUP Input Pullup Resistor 51 kΩ RPULLDOWN Input Pulldown Resistor 51 kΩ IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 2 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY TABLE 3A. OUTPUT ENABLE FUNCTION TABLE Inputs OE Outputs Q0:Q3 nQ0:nQ3 0 HiZ HiZ 1 Enabled Enabled TABLE 3B. PLL BANDWIDTH/PLL BYPASS CONTROL Inputs BW_SEL1 BW_SEL0 PLL Bandwidth 0 0 ~200kHz 0 1 ~400kHz (default) 1 0 ~800kHz 1 1 PLL BYPASS TABLE 3C. FREQUENCY SELECT FUNCTION TABLE Input Frequency 100 Inputs F_SEL1 F_SEL0 0 0 Divider Value 5 Output Frequency Range (MHz) 100 (default) 100 0 1 4 125 100 1 0 2 250 100 1 1 1 500 IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 3 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause per manent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Package Thermal Impedance, θJA 82.3°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter VDD Core Supply Voltage Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.3 VDD VDD – IDDA*10Ω VDDA Analog Supply Voltage IDD Power Supply Current TBD mA IDDA Analog Supply Current TBD mA V TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter VIH VIL Input High Voltage Input Low Voltage IIH Input High Current IIL Input Low Current Test Conditions MR, OE, F_SEL0. F_SEL1, BW_SEL0, BW_SEL1 MR, OE, F_SEL0. F_SEL1, BW_SEL0, BW_SEL1 BW_SEL0, OE MR, BW_SEL1, F_SEL0. F_SEL1 BW_SEL0, OE MR, BW_SEL1, F_SEL0. F_SEL1 Minimum Typical Maximum Units 2 VDD + 0.3 V VDD - 0.3 VDD + 0.3 V -0.3 0.8 V -0.3 0.3 V VDD = VIN = 3.465V 5 µA VDD = VIN = 3.465V 150 µA VDD = 3.465V, VIN = 0V -150 µA VDD = 3.465V, VIN = 0V -5 µA TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter Test Conditions CLK VDD = VIN = 3.465V nCLK, VDD = VIN = 3.465V IIH Input High Current IIL Input Low Current VPP Peak-to-Peak Input Voltage CLK VDD = VIN = 3.465V nCLK VDD = VIN = 3.465V Minimum Typical µA µA 15 0 -150 µA µA 0.15 4 Units 15 0 5 VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK at VDD + 0.3V. IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR Maximum 1.3 V VDD - 0.85 V ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY TABLE 5. AC CHARACTERISTICS, VDD = VDDA = 3.3V±10%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay; NOTE 1 tjit Buffer Additive Phase Jitter, RMS; Refer to Additive Phase Jitter Section Test Conditions Minimum PLL in BYPASS Mode PLL in BYPASS Mode 100MHz, Integration Range: 12kHz - 20MHz PLL Mode tjit(cc) Cycle-to-Cycle Jitter ; NOTE 2 tL PLL Lock Time VHIGH Voltage High 660 VLOW Voltage Low -150 VOVS Max. Voltage, Overshoot VUDS Min. Voltage, Undershoot Vrb Ringback Voltage VCROSS Absolute Crossing Voltage ΔVCROSS Total Variation of VCROSS over all edges tR / tF Output Rise/Fall Time Typical 98 Maximum Units 640 MHz 3.8 ns 0.23 ps 19 ps TBD ms 850 mV VHIGH + 0.3 V 0.2 V 550 mV 140 mV -0.3 V 250 measured between 0.175 to 0.525 mV 475 ps ΔtR /ΔtF Rise/Fall Time Variation 125 ps tRFM Rise/Fall Matching 125 ps odc Output Duty Cycle 50 % NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 5 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY ADDITIVE PHASE JITTER band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot. The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in the 1Hz Additive Phase Jitter @ 100MHz SSB PHASE NOISE dBc/HZ (12kHz to 20MHz) = 0.23ps typical OFFSET FROM CARRIER FREQUENCY (HZ) As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The device IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment. 6 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION VDD VDD 100Ω 33Ω Measurement Point nCLK VDDA 49.9Ω 100Ω 33Ω V Cross Points PP 2pF HSCL V CMR CLK Measurement Point GND GND 49.9Ω 2pF 475Ω 3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT - TBD DIFFERENTIAL INPUT LEVEL nQ0:nQ3 Q0:Q3 ➤ tcycle n ➤ tcycle n+1 ➤ ➤ t jit(cc) = tcycle n –tcycle n+1 1000 Cycles DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD CYCLE-TO-CYCLE JITTER SE MEASUREMENT POINTS FOR RISE/FALL TIME MATCHING IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 7 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY PARAMETER MEASUREMENT INFORMATION, CONTINUED SE MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT/SWING DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK SE MEASUREMENT POINTS FOR DELTA CROSS POINT IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 8 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter performance, power supply isolation is required. The ICS871004I04 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VDD, VDDA and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Figure 1 illustrates this for a generic VDD pin and also shows that V DDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the VDDA pin. 3.3V VDD .01μF 10Ω VDDA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS: DIFFERENTIAL OUTPUTS All unused differential outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 9 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3F show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for IDT HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY AN IDT OPEN EMITTER HIPERCLOCKS LVHSTL DRIVER FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V 3.3V R3 125 R4 125 Zo = 50 Ohm LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER 2.5V FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER 2.5V 3.3V 3.3V 2.5V *R3 33 R3 120 Zo = 50Ω R4 120 Zo = 60Ω CLK CLK Zo = 50Ω Zo = 60Ω nCLK HCSL *R4 33 R1 50 R2 50 nCLK HiPerClockS Input HiPerClockS SSTL R1 120 R2 120 *Optional – R3 and R4 can be 0Ω FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 2.5V SSTL DRIVER FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY A 3.3V HCSL DRIVER IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 10 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY RECOMMENDED TERMINATION Figure 4A is the recommended termination for applications which require the receiver and driver to be on a separate PCB. All traces should be 50Ù impedance. FIGURE 4A. RECOMMENDED TERMINATION Figure 6B is the recommended termination for applications which require a point to point connection and contain the driver and receiver on the same PCB. All traces should all be 50Ù impedance. FIGURE 4B. RECOMMENDED TERMINATION IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 11 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY RELIABILITY INFORMATION TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 82.3°C/W 78°C/W 75.9°C/W TRANSISTOR COUNT The transistor count for ICS871004I-04 is: 1395 IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 12 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP TABLE 7. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N Maximum 24 A -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 7.70 E E1 7.90 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 13 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY TABLE 8. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS871004AGI-04 ICS871004AI04 24 Lead TSSOP tube -40°C to 85°C ICS871004AGI-04T ICS871004AI04 24 Lead TSSOP 2500 tape & reel -40°C to 85°C ICS871004AGI-04LF ICS71004AI04L 24 Lead "Lead-Free" TSSOP Tray -40°C to 85°C ICS871004AGI-04LFT ICS71004AI04L 24 Lead "Lead-Free" TSSOP 2500 Tape & Reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ 0.7V DIFFERENTIAL JITTER ATTUNUATOR 14 ICS871004AGI-04 REV A JANUARY 17, 2008 ICS871004I-04 DIFFERENTIAL-TO-0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR PRELIMINARY Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA