IDT ICS8741004AGLF

ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL
PCI EXPRESS™ JITTER ATTENUATOR
General Description
Features
The ICS8741004 is a high performance
Differential-to-LVDS/0.7V Differential Jitter
HiPerClockS™
Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as
those found in desktop PCs, the PCI Express clocks
are generated from a low bandwidth, high phase noise PLL
frequency synthesizer. In these systems, a jitter attenuator may be
required to attenuate high frequency random and deterministic
jitter components from the PLL synthesizer and from the system
board. The ICS8741004 has 3 PLL bandwidth modes: 200kHz,
600kHz and 2MHz. The 200kHz mode will provide maximum jitter
attenuation, but with higher PLL tracking skew and spread
spectrum modulation from the motherboard synthesizer may be
attenuated. The 600kHz provides an intermediate bandwidth that
can easily track triangular spread profiles, while providing good
jitter attenuation. The 2MHz bandwidth provides the best tracking
skew and will pass most spread profiles, but the jitter attenuation
will not be as good as the lower bandwidth modes. Because some
2.5Gb serdes have x20 multipliers while others have x25
multipliers, the ICS8741004 can be set for 1:1 mode or 5/4
multiplication mode (i.e. 100MHz input/125MHz output) using the
F_SEL pins.
•
Two LVDS and two 0.7V differential output pairs
Bank A has two LVDS output pairs and
Bank B has two 0.7V differential output pairs
•
•
One differential clock input pair
•
•
•
•
•
•
Output frequency range: 98MHz - 160MHz
•
•
0°C to 70°C ambient operating temperature
ICS
The ICS8741004 uses IDT’s 3rd Generation FemtoClock™
PLL technology to achieve the lowest possible phase noise.
The device is packaged in a 24 Lead TSSOP package, making it
ideal for use in space constrained applications such as PCI
Express add-in cards.
CLK, CLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Input frequency range: 98MHz - 128MHz
VCO range: 490MHz - 640MHz
Cycle-to-cycle jitter: 35ps (maximum)
Full 3.3V operating supply
Three bandwidth modes allow the system designer to make
jitter attenuation/tracking skew design trade-offs
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
nQA1
QA1
VDDO
QA0
nQA0
MR
BW_SEL
nc
VDDA
F_SELA
VDD
OEA
PLL Bandwidth
BW_SEL
0 = PLL Bandwidth: ~200kHz
Float = PLL Bandwidth: ~600kHz (default)
1 = PLL Bandwidth: ~2MHz
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
nQB1
QB1
VDDO
QB0
nQB0
IREF
F_SELB
OEB
GND
GND
nCLK
CLK
ICS8741004
24-Lead TSSOP
4.4mm x 7.8mm x 0.925mm
package body
G Package
Top View
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Block Diagram
OEA
Pullup
F_SELA Pulldown
QA0
BW_SEL Float
F_SELA
0 ÷5 (default)
1 ÷4
0 = ~200kHz
Float = ~400kHz
1 = ~800kHz
nQA0
QA1
CLK Pulldown
nCLK
Pullup
Phase
Detector
VCO
nQA1
490 - 640 MHz
QB0
F_SELB
0 ÷5 (default)
1 ÷4
M = ÷5 (fixed)
nQB0
QB1
nQB1
F_SELB Pulldown
MR Pulldown
IREF
OEB
Pullup
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 24
QA1, QA1
Output
Differential output pair. LVDS interface levels.
3, 22
VDDO
Power
Output supply pins.
4, 5
QA0, QA0
Output
Differential output pair. LVDS interface levels.
6
MR
Input
Pulldown
Active High Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q[Ax:Bx] to go LOW and the inverted outputs
Q[Ax:Bx] to go HIGH. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
7
BW_SEL
Input
Pullup/
Pulldown
PLL Bandwidth input. LVCMOS/LVTTL interface levels. See Table 3B.
8
nc
Unused
9
VDDA
Power
10
F_SELA
Input
11
VDD
Power
12
OEA
Input
Pullup
13
CLK
Input
Pulldown
14
CLK
Input
Pullup
15, 16
GND
Power
17
OEB
Input
Pullup
18
F_SELB
Input
Pulldown
19
IREF
Input
20, 21
QB0, QB0
Output
Differential output pair. HCSL interface levels.
23, 24
QB1, QB1
Output
Differential output pair. HCSL interface levels.
No connect.
Analog supply pin.
Pulldown
Frequency select pins for QAx/QAx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
Core supply pin.
Output enable for QAx pins. When HIGH, QAx/QAx outputs are enabled.
When LOW, the QAx/QAx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
Non-inverting differential clock input.
Inverting differential clock input.
Power supply ground.
Output enable for QBx pins. When HIGH, QBx/QBx outputs are enabled.
When LOW, the QBx/QBx outputs are in a high impedance state.
LVCMOS/LVTTL interface levels. See Table 3A.
Frequency select pins for QBx/QBx outputs.
LVCMOS/LVTTL interface levels. See Table 3C.
A fixed precision resistor (RREF = 475Ω) from this pin to ground provides a
reference current used for differential current-mode QB0/nQB0 clock outputs.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
Input Capacitance
4
pF
RPULLUP
Input Pullup Resistor
51
kΩ
RPULLDOWN
Input Pulldown Resistor
51
kΩ
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
Test Conditions
3
Minimum
Typical
Maximum
Units
ICS8741004AG REV. ANOVEMBER 1, 2007
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Function Tables
Table 3A. Output Enable Function Table
Inputs
Table 3B. PLL Bandwidth Function Table
Outputs
Input
OEA
OEB
QA[0:1]/QA[0:1]
QB[0:1]/QB[0:1]
BW_SEL
0
0
Hi-Z
Hi-Z
0
1
1
Enabled
Enabled
Float
PLL Bandwidth
~200kHz
~600kHz (default)
1
~2MHz
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDDO + 0.5V
Package Thermal Impedance, θJA
82.3°C/W (0 mps)
Storage Temperature, TSTG
-65°C to 150°C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VDD
Core Supply Voltage
VDDA
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
Analog Supply Voltage
VDD – 0.12
3.3
VDD
V
VDDO
Output Supply Voltage
3.135
3.3
3.465
V
IDD
Power Supply Current
45
mA
IDDA
Analog Supply Current
12
mA
IDDO
Output Supply Current
80
mA
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
Test Conditions
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Table 4B. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
VIH
Parameter
Input High Voltage
Test Conditions
Maximum
Units
2
VDD + 0.3
V
VDD – 0.3
VDD + 0.3
V
OEA, OEB, MR,
F_SELA, F_SELB
-0.3
0.8
V
BW_SEL
-0.3
+0.3
V
VDD/2 – 0.1
VDD/2 + 0.1
V
OEA, OEB, MR,
F_SELA, F_SELB
BW_SEL
VIL
Input Low Voltage
Minimum
Typical
VIM
Input Mid Voltage
BW_SEL
VDD = VIN = 3.465V
µA
Input High Current
F_SELA, F_SELB,
MR, BW_SEL
150
IIH
OEA, OEB
VDD = VIN = 3.465V
5
µA
IIL
Input Low Current
MR,
F_SELA, F_SELB,
VDD = 3.465V, VIN = 0V
-5
µA
OEA, OEB, BW_SEL
VDD = 3.465V, VIN = 0V
-150
µA
Table 4C. Differential DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
IIH
Input High Current
IIL
Test Conditions
Minimum
Typical
Maximum
Units
CLK
VDD = VIN = 3.465V
150
µA
CLK
VDD = VIN = 3.465V
5
µA
CLK
VDD = 3.465V,
VIN = 0V
-5
µA
CLK
VDD = 3.465V,
VIN = 0V
-150
µA
Input Low Current
VPP
Peak-to-Peak Voltage; NOTE 1
VCMR
Common Mode Input Voltage; NOTE 1, 2
0.15
1.3
V
GND + 0.5
VDD – 0.85
V
NOTE 1: VIL should not be less than -0.3V
NOTE 2: Common mode input voltage is defined as VIH.
Table 4D. LVDS DC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Symbol
Parameter
VOD
Differential Output Voltage
∆VOD
VOD Magnitude Change
VOS
Offset Voltage
∆VOS
VOS Magnitude Change
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
Test Conditions
Minimum
Typical
Maximum
Units
290
390
490
mV
50
mV
1.5
V
50
mV
1.2
5
1.35
ICS8741004AG REV. ANOVEMBER 1, 2007
ICS8741004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
AC Electrical Characteristics
Table 5. 0.7V Differential AC Characteristics, VDD = VDDO = 3.3V ± 5%, TA = 0°C to 70°C
Parameter
Symbol
Test Conditions
fMAX
Output Frequency
tjit(cc)
Cycle-to-Cycle Jitter; NOTE 1
tsk(b)
Bank Skew, NOTE 2
VHIGH
Output Voltage High
QBx/QBx
530
VLOW
Output Voltage Low
QBx/QBx
-150
VOVS
Max. Voltage, Overshoot
QBx/QBx
Maximum
Units
160
MHz
35
ps
30
ps
870
mV
mV
VHIGH + 0.35
VUDS
Min. Voltage, Undershoot
QBx/QBx
Ringback Voltage
QBx/QBx
VCROSS
Absolute Crossing Voltage
QBx/QBx
@ 0.7V Swing
∆VCROSS
Total Variation of VCROSS
over all edges
QBx/QBx
@ 0.7V Swing
QBx/QBx
measured between
0.175V to 0.525V
QAx/QAx
20% to 80%
Output Rise/Fall Time
Typical
98
Vrb
tR / tF
Minimum
-0.3
V
V
0.2
V
550
mV
140
mV
175
700
ps
250
600
ps
250
∆tR / ∆tF
Rise/Fall Time Variation
QBx/QBx
125
ps
tRFM
Rise/Fall Matching
QBx/QBx
20
%
odc
Output Duty Cycle
52
%
48
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Parameter Measurement Information
,
VDD,
VDDO
50Ω
33Ω
VDDA
Measurement
Point
49.9Ω
3.3V±5%
POWER SUPPLY
+ Float GND –
2pF
HCSL
50Ω
33Ω
SCOPE
Measurement
Point
VDD,
VDDO
Qx
VDDA
LVDS
nQx
GND
49.9Ω
2pF
RREF = 475Ω
3.3V HCSL Output Load AC Test Circuit
3.3V LVDS Output Load AC Test Circuit
VDD
QX0
QX0
CLK
V
Cross Points
OD
QX1
CLK
QX1
V
tsk(b)
OS
GND
Where X is either Bank A or Bank B
Differential Input Level
Bank Skew
QA[0:1],
QB[0:1]
QA[0:1],
QB[0:1]
QA[0:1],
QB[0:1]
QA[0:1],
QB[0:1]
➤
tcycle n
➤
tcycle n+1
t PW
t
➤
➤
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
odc =
PERIOD
t PW
x 100%
t PERIOD
Cycle-to-Cycle Jitter
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
Output Duty Cycle/Pulse Width/Period
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Parameter Measurement Information, continued
Clock Period (Differential)
Positive Duty
Cycle (Differential)
80%
80%
Negative Duty
Cycle (Differential)
VOD
Clock
Outputs
20%
20%
0.0V
tF
tR
Q/nQ
LVDS Output Rise/Fall Time
Differential Measurement Points for Duty Cycle/Period
TSTABLE
VRB
nQ
VIH = +150mV
VRB = +100mV
0.0V
VRB = -100mV
VIL = -150mV
VCROSS_DELTA = 140mV
Q/nQ
Q
VRB
TSTABLE
SE Measurement Points for Delta Cross Point
Differential Measurement Points for Ringback
VMAX = 1.15V
Rise Edge Rate
Fall Edge Rate
nQ
VCROSS_MAX = 550mV
VIH = +150mV
0.0V
VIL = -150mV
VCROSS_MIN = 250mV
Q
Q/nQ
VMIN = -0.30V
Differential Measurement Points for Rise/Fall Time
SE Measurement Points for Absolute Cross
Point/Swing
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Parameter Measurement Information, continued
VDD
Rise Edge Rate
Fall Edge Rate
out
LVDS
➤
DC Input
VIH = +150mV
0.0V
VIL = -150mV
out
➤
VOS/∆ VOS
Q/nQ
➤
Differential Measurement Points for Rise/Fall Time
Offset Voltage Setup
VDD
LVDS
100
➤
VOD/∆ VOD
out
➤
DC Input
➤
out
Differential Output Voltage Setup
nQ
nQ
tFALL
tRISE
VCROSS_MEDIAN +75mV
VCROSS_MEDIAN
VCROSS_MEDIAN
VCROSS_MEDIAN -75mV
Q
Q
SE Measurement Points for Rise/Fall Time Matching
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Application Information
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter
performance, power supply isolation is required. The ICS8741004
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA and VDDO
should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic VDD pin and also
shows that VDDA requires that an additional 10Ω resistor along with
a 10µF bypass capacitor be connected to the VDDA pin.
3.3V
VDD
.01µF
10Ω
.01µF
10µF
VDDA
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω
nCLK
Zo = 50Ω
nCLK
HiPerClockS
Input
LVHSTL
R1
50
IDT
HiPerClockS
LVHSTL Driver
HiPerClockS
Input
LVPECL
R2
50
R1
50
R2
50
R2
50
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
3.3V
3.3V
3.3V
R3
125
3.3V
R4
125
3.3V
Zo = 50Ω
Zo = 50Ω
CLK
CLK
R1
100
Zo = 50Ω
nCLK
HiPerClockS
Input
LVPECL
R1
84
R2
84
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
2.5V
nCLK
Zo = 50Ω
Receiver
LVDS
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
2.5V
3.3V
3.3V
2.5V
*R3
33
R3
120
Zo = 50Ω
R4
120
Zo = 60Ω
CLK
CLK
Zo = 50Ω
Zo = 60Ω
nCLK
nCLK
HCSL
*R4
33
R1
50
R2
50
HiPerClockS
Input
HiPerClockS
SSTL
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
LVCMOS Control Pins
Differential Outputs
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVDS Outputs
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
LVDS Driver Termination
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers require a
matched load termination of 100Ω across near the receiver input.
For a multiple LVDS outputs buffer, if only partial outputs are used,
it is recommended to terminate the unused outputs.
3.3V
50Ω
3.3V
LVDS Driver
+
R1
100Ω
–
50Ω
100Ω Differential Transmission Line
Figure 4. Typical LVDS Driver Termination
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Recommended Termination
Figure 5A is the recommended termination for applications which
require the receiver and driver to be on a separate PCB. All traces
should be 50Ω impedance.
Figure 5A. Recommended Termination
Figure 5B is the recommended termination for applications which
require a point to point connection and contain the driver and
receiver on the same PCB. All traces should all be 50Ω impedance.
Figure 5B. Recommended Termination
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
Power Considerations
This section provides information on power dissipation and junction temperature for the ICS8741004.
Equations and example calculations are also provided.
1.
Power Dissipation.
The total power dissipation for the ICS741004 is the sum of the core power plus the analog power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (45mA + 12mA) = 197.5mW
•
Power (LVDS_output)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 80mA = 227.2mW
•
Power (HCSL_output)MAX = 45.65mW * 2 = 91.3mW
Total Power_MAX = (3.465V, with all outputs switching) = 197.5mW + 277.2mW + 91.3mW = 556mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device.
The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air flow
and a multi-layer board, the appropriate value is 82.3°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.556W * 82.3°C/W = 115.8°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type
of board (single layer or multi-layer).
Table 6. Thermal Resistance θJA for 24 Lead TSSOP, Forced Convection
θJA Vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
0
1
2.5
82.3°C/W
78.0°C/W
75.9°C/W
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DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
3. Calculations and Equations.
The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 6.
VDD O
VOU T
RL
50
IC
Figure 6. HCSL Driver Circuit and Termination
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load and a termination
voltage of VDDO – 2V.
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (VOH_MAX /RL) * (VDDO_MAX – VOH_MAX)
Pd_L = (VOL_MIN /RL) * (VDDO_MAX – VOL_MIN)
Pd_H = (0.85V /50Ω) * (3.465V – 0.87V) = 44.1mW
Pd_L = (0.15V/50Ω) * 0.15V = 0.45mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 45mW
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Reliability Information
Table 7. θJA vs. Air Flow Table for a 24 Lead TSSOP
θJA vs. Air Flow
Meters per Second
Multi-Layer PCB, JEDEC Standard Test Boards
0
1
2.5
82.3°C/W
78.0°C/W
75.9°C/W
Transistor Count
The transistor count for ICS8741004 is: 1318
Package Outline and Package Dimension
Package Outline - G Suffix for 24 Lead TSSOP
Table 8. Package Dimensions
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
24
A
1.20
A1
0.5
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
7.70
7.90
E
6.40 Basic
E1
4.30
4.50
e
0.65 Basic
L
0.45
0.75
α
0°
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
4 40
B d
0 65
Pit h TSSOP
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Ordering Information
Table 9. Ordering Information
Part/Order Number
8741004AG
8741004AGT
8741004AGLF
8741004AGLFT
Marking
ICS8741004AG
ICS8741004AG
ICS8741004AGLF
ICS8741004AGLF
Package
24 Lead TSSOP
24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
“Lead-Free” 24 Lead TSSOP
Shipping Packaging
Tray
2500 Tape & Reel
Tray
2500 Tape & Reel
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications, such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements
are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any
IDT product for use in life support devices or critical medical instruments.
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Revision History Sheet
Rev
A
Table
Page
Description of Change
T4C
T5
5
6
8&9
11
Differential DC Characteristics Table - added NOTE.
AC Characteristics Table - corrected VHIGH/VLOW units from ps to mV.
Added HCSL Parameter Measurement Information.
Updated Differential Clock Input Interface section.
IDT™ / ICS™ PCI EXPRESS™ JITTER ATTENUATOR
Date
18
10/31/07
ICS8741004AG REV. ANOVEMBER 1, 2007
ICS871004
DIFFERENTIAL-TO-LVDS/0.7V DIFFERENTIAL PCI EXPRESS™ JITTER ATTENUATOR
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