ISL59832 ® Data Sheet June 11, 2008 • Eliminates the Need for Large Output Coupling Capacitors • Integrated Sync Tip Clamp sets Backporch to Ground at the Output For Channel 1 for 1VP-P Standard Video Signal • Integrated Keyed Clamp Puts Channel 2 Output to Ground During Sync • Each Output Drives 2 Standard Video Loads • Response Flat to 5MHz, with 40dB Attenuation at 27MHz • Pb-Free (RoHS compliant) Pinout VEEIN VEEOUT ISL59832 (16 LD TQFN) TOP VIEW 16 15 14 13 SYNC_IN 1 12 CAP+ VS ENABLE 4 5 MDP0046 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 9 7 8 GND 59 832IRZ -40 to +85 16 Ld TQFN PKG. DWG. # 10 VCP 3 IN2 PACKAGE (Pb-Free) 11 CAP- EP 6 GND ISL59832IRZ PART MARKING • Inputs can be AC- or DC-Coupled IN1 PART NUMBER • DC-Coupled Outputs SYNC_OUT 2 Ordering Information TEMP. RANGE (°C) • 3.3V Nominal Supply, Operates Down to 3.0V OUT2 The ISL59832 is a dual channel, single supply video driver with reconstruction filter and charge pump. It is designed to drive SDTV displays with S-Video (Y/C) signals. It operates on a single supply (3.0V to 3.6V) and generates its own negative supply (-1.5V) using a regulated charge pump. Input signals can be AC- or DC-coupled. When AC-coupled, the sync tip clamp sets the blank level to ground at the output of Channel 1 thus ensuring that the sync-tip voltage level is set to approximately -300mV at the back-termination resistor of a standard video load. Channel 1 also has a sync detector whose output is available at SYNC_OUT pin. In a typical application where the luma is connected to Channel 1, and chrominance is connected to Channel 2, SYNC_IN is connected to SYNC_OUT thus providing timing to Channel 2. Channel 2 has a keyed clamp which sets the output to ground when SYNC_IN is driven to the logic high state. The ISL59832 is capable of driving two DC- or AC-coupled standard video loads. The ISL59832 features a 4th order Butterworth reconstruction filter that provides a 9MHz nominal -3dB frequency and 40dB of attenuation at 27MHz. Nominal operational current is 31mA. When powered down, the device draws 1µA maximum supply current. The ISL59832 is available in 16 Ld TQFN package. Features OUT1 Dual Channel, Single Supply Video Reconstruction Filter with Charge Pump FN6267.1 GNDCP Block Diagram ISL59832 CHANNEL 1 Applications VIDEO IN (Y) • Set Top Box Receiver CLAMP + SYNC DETECTOR LPF x2 9MHz VIDEO OUT (Y) CHARGE PUMP • Television • DVD Player CHANNEL 2 VIDEO IN (C) KEYED CLAMP LPF x2 9MHz VIDEO OUT (C) CHARGE PUMP 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL59832 Absolute Maximum Ratings (TA = +25°C) Thermal Information VS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4V VIN to GND. . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VS + 0.3V Maximum Continuous Output Current . . . . . . . . . . . . . . . . . . ±50mA Maximum Current into Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±50mA ESD Rating Human Body Model (Per MIL-STD-883 Method 3015.7) . . .3500V Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . . .350V or Thermal Resistance (Typical, Note 1) θJA (°C/W) 16 Lead TQFN Package . . . . . . . . . . . . . . . . . . . . . 46 Maximum Junction Temperature (Plastic Package) . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. Parameters with MIN and/or MAX limits are 100% tested at +27°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. Electrical Specifications SYMBOL VS = VCP = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1 = CIN2 = 0.1µF, RL1 = RL2 = 150Ω, Typical TA = +27°C. PARAMETER CONDITIONS MIN (Note 2) TYP MAX (Note 2) UNIT 3.0 3.3 3.6 V -1.75 -1.5 -1.25 V DC CHARACTERISTICS VS, VCP Supply Range VEEOUT Charge Pump Output guaranteed by PSRR IS Supply Current No load 14 16 mA ICP Charge Pump Supply Current No load 17 20 mA IPD Power-Down Current ENABLE = 0.4V 0.3 2.5 µA IIN Input Pull-down Current Channel 1, VIN = 0.5V 0.4 4 10 µA IB Input Bias Current Channel 2, VIN = 0.5V, SYNC_IN = 0V -10 -3 10 µA AV DC Gain 1.94 2 2.05 V/V VIN_MAX Max DC Input Range DC-Coupled Input, guaranteed by DC gain test 1.4 VCLAMPOUT1 Output Sync Tip Clamp Level (Channel 1) VIN ≤ 0, AC-coupled input -650 -590 -525 mV VCLAMPOUT2 Keyed Clamp Level (Channel 2) Output level when SYNC_IN = 2.0V -60 -25 0 mV VCLAMPIN Input Clamp Level Input floating 0 30 70 mV VCLAMPIN2 Input Keyed Clamp Level (Channel 2) Input floating, input level when SYNC_IN ≥ 2.0V 275 300 375 mV Output Level Shift (Channel 1) VIN > 0, output shifted relative to input, DC-coupled input -685 -620 -550 mV Output Level Shift (Channel 2) VIN > 0, output shifted relative to input, DC-coupled input -380 -330 -280 mV VOS 2 V FN6267.1 June 11, 2008 ISL59832 Electrical Specifications SYMBOL ICLAMP VS = VCP = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1 = CIN2 = 0.1µF, RL1 = RL2 = 150Ω, Typical TA = +27°C. (Continued) PARAMETER Clamp Restore Current CONDITIONS MIN (Note 2) Force VIN = -0.3V, Channel 1 Force VIN = 1V, Channel 2 135 Force VIN = -0.3V, Channel 2 TYP MAX (Note 2) UNIT -5 -2.5 mA 180 -200 µA -160 µA 200 mV VSLICE Sync Detect Threshold Channel 1 100 PSRRDC Power Supply Rejection VS = +3.0 to +3.6 50 77 0 0.8 1.25 dB -35 dB dB AC CHARACTERISTICS APB Passband Flatness f = 5MHz, relative to 100kHz ASB Stopband Attenuation f ≥ 27MHz relative to 100kHz -50 dG Differential Gain 11-step modulated staircase 0.45 % dP Differential Phase 11-step modulated staircase -0.15 ° Signal To Noise Ratio Peak signal (1.4VP-P) to RMS noise, f = 10kHz to 10MHz 66 dB GDMATCH DC Group Delay Match Channel-to-channel group delay matching at 100kHz 0.1 ns ΔGD Group Delay Deviation Deviation from 100kHz to 3.58MHz 8 ns PSRR Power Supply Rejection VIN = 100mVP-P sine wave, f = 100kHz to 5MHz 35 dB XTALK Channel-to-Channel Crosstalk f = 100kHz to 5MHz -60 dB VNOISE Input Voltage Noise 0.66 mVRMS SNR LOGIC (ENABLE, SYNC_IN) VIL Logic Low Input Voltage VIH Logic High Input Voltage 2.0 Logic Input Current -1 II 0.8 V V 1 µA CHARGE PUMP fCP Charge Pump Clock Frequency 3 12.5 MHz FN6267.1 June 11, 2008 ISL59832 Pin Descriptions NUMBER NAME 1 SYNC_IN 2 SYNC_OUT 3 VS 4 ENABLE 5 IN1 6, 8 GND 7 IN2 9 GNDCP 10 VCP 11 CAP- Charge-Pump Flying Capacitor Negative Terminal. Connect a 0.1µF capacitor from CAP+ to CAP- 12 CAP+ Charge-Pump Flying Capacitor Positive Terminal. Connect a 0.1µF capacitor from CAP+ to CAP- 13 VEEOUT 14 VEEIN Negative Supply. Connect an RC filter between VEEIN and VEEOUT. See “S-Video Typical Application Circuit” on page 6. 15 OUT2 Video Output 2 16 OUT1 Video Output 1 - EP 4 FUNCTION Sync Input. Sync timing logic input for Channel 2. Sync Output. Sync-detection logic output from Channel 1. Positive Power Supply. Bypass to GND with a 0.1µF capacitor. Enable. Connect to VS to enable device. Video Input 1. Luma Channel. Ground Video Input 2. Chroma Channel. Charge Pump Ground. Charge Pump Power Supply. Bypass with a 0.1µF capacitor to GNDCP. Charge Pump Negative Output. Bypass with a 0.22µF capacitor to GND. Exposed Pad. Connect to VEEIN FN6267.1 June 11, 2008 ISL59832 Block Diagram SYNC_OUT VS ENABLE SYNC DETECTOR LPF LEVEL SHIFT (-310mV) IN1 9MHz X2 OUT1 VEEIN + -593mV LPF LEVEL SHIFT (-165mV) IN2 9MHz X2 OUT2 VEEIN KEYED CLAMP + 0V SYNC_IN CHARGE PUMP ISL59832 GND VEEOUT 5 GNDCP CAP+ CAP- VEEIN VCP FN6267.1 June 11, 2008 ISL59832 S-Video Typical Application Circuit +3.3V 0.1μF ENABLE 4.7μF VS SYNC_OUT SYNC_IN 0.1μF Luma Source 75Ω IN1 OUT1 75Ω 75Ω ISL59832 0.1μF Chrominance Source 75Ω OUT2 IN2 75Ω 75Ω VEEIN 10Ω RFIL VEEOUT 0.22μF CS 0.47μF CFIL +3.3V VCP 0.1μF GND CAP+ CAP- GNDCP CCP1 1.0μF CCP2 CF 0.1μF 6 FN6267.1 June 11, 2008 ISL59832 VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω. 10 2 0 1 -10 -20 MAGNITUDE (dB) MAGNITUDE (dB) Typical Performance Curves CHANNEL 2 RL = 75Ω CHANNEL 2 RL = 150Ω -30 -40 CHANNEL 1 RL = 150Ω -50 -60 -70 0.1 0 CHANNEL 1 RL = 150Ω -1 CHANNEL 2 RL = 150Ω -2 -3 -5 100M 0.1 50 -1.40 CHANNEL 1 LUMA CHARGE PUMP VOLTAGE (V) DELAY (ns) 30 20 10 0 -10 CHANNEL 2 CHROMA -20 -30 -40 0.1 1M 10M FREQUENCY (Hz) -1.44 -1.45 -1.46 VCP = VS = 2.7V TO 3.6V VCP = 3.3V VS = 2.7V TO 3.6V -1.47 2.8 2.9 3.0 3.1 3.2 3.3 SUPPLY VOLTAGE (V) 3.4 3.5 3.6 INPUT OF CHANNEL 1 TO OUTPUT OF -10 CHANNEL 2 AND VICE-VERSA MAGNITUDE (dB) MAGNITUDE (dB) -1.43 0 ENABLE = LOW ANY INPUT TO ANY OUTPUT -30 -40 -50 -60 -70 -80 -20 -30 -40 -50 -60 -90 -100 0.1 VS = 3.3V VCP = 2.7 TO 3.6V -1.42 FIGURE 4. CHARGE PUMP VOLTAGE vs SUPPLY VOLTAGE 0 -20 10M ALL MEASUREMENTS AT VEEIN -1.41 -1.48 2.7 100M FIGURE 3. GROUP DELAY vs FREQUENCY -10 1M FREQUENCY (Hz) FIGURE 2. GAIN FLATNESS vs FREQUENCY FIGURE 1. BANDWIDTH vs FREQUENCY 40 CHANNEL 1 RL = 75Ω -4 CHANNEL 1 RL = 75Ω 1M 10M FREQUENCY (Hz) CHANNEL 2 RL = 75Ω 1M 10M FREQUENCY (Hz) 100M FIGURE 5. INPUT-TO-OUTPUT ISOLATION vs FREQUENCY 7 -70 0.1 1M 10M FREQUENCY (Hz) 100M FIGURE 6. LUMA-TO-CHROMA CROSSTALK FN6267.1 June 11, 2008 ISL59832 VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω. 35 SUPPLY CURRENT (mA) 34 NO LOAD INPUT FLOATING 33 32 31 30 29 28 27 26 25 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 DISABLED SUPPLY CURRENT (nA) Typical Performance Curves FIGURE 7. SUPPLY CURRENT vs SUPPLY VOLTAGE 300 250 200 150 100 50 0 3.0 3.1 3.2 3.3 3.4 SUPPLY VOLTAGE (V) 3.5 3.6 0 VAC = 100mVP-P VS = +3.3V + VAC -10 MAGNITUDE (dB) 25 IMPEDANCE (Ω) NO LOAD INPUT FLOATING 350 FIGURE 8. DISABLED SUPPLY CURRENT vs SUPPLY VOLTAGE 30 20 15 10 -20 -30 -40 -50 5 0 0.1 1M 10M FREQUENCY (Hz) -60 0.001 100M 0.1 1M 10M FIGURE 10. POWER SUPPLY REJECTION RATIO vs FREQUENCY 0.6 0.05 WAVEFORM = MODULATED RAMP 0.5 0 IRE to 100 IRE WAVEFORM = MODULATED RAMP 0 IRE TO 100 IRE 0.03 0.01 0.4 -0.01 0.3 DP (°) -0.03 -0.05 -0.07 0.2 0.1 -0.09 0 -0.11 -0.1 -0.13 -0.15 0.01 FREQUENCY (Hz) FIGURE 9. OUTPUT IMPEDANCE vs FREQUENCY DG (%) 400 0 1 2 3 4 5 6 7 8 STEP FIGURE 11. DIFFERENTIAL GAIN 8 9 10 11 -0.2 0 1 2 3 4 5 6 STEP 7 8 9 10 11 FIGURE 12. DIFFERENTIAL PHASE FN6267.1 June 11, 2008 ISL59832 Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω. TIME SCALE = 10ns/DIV CH1 = 1V/DIV CH2 = 1V/DIV TIME SCALE = 5µs/DIV CH1 = 1V/DIV CH2 = 1V/DIV DISABLE SIGNAL ENABLE SIGNAL ΔTIME = 35µs OUTPUT SIGNAL OUTPUT SIGNAL FIGURE 14. ENABLE TIME FIGURE 13. DISABLE TIME TIMEBASE = 100ns/DIV IN = CH1 = 200mV/DIV OUT = CH2 = 500mV/DIV TIME SCALE = 500ns/DIV IN = CH1 = 200mV/DIV OUT = CH2 = 500mV/DIV INPUT INPUT OUTPUT OUTPUT FIGURE 15. 12.5T RESPONSE TIME SCALE = 10µs/DIV IN = CH1 = 500mV/DIV OUT = CH2 = 1V/DIV FIGURE 16. 2T RESPONSE LUMA OUTPUT CHANNEL 1 TIME SCALE = 10µs/DIV LUMA OUT = 500mV/DIV CHROMA OUT = 500mV/DIV CHROMA OUTPUT CHANNEL 2 INPUT OUTPUT FIGURE 17. NTSC COLORBAR 9 FIGURE 18. S-VIDEO SCOPE SHOT FN6267.1 June 11, 2008 ISL59832 Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω. INPUT = NTSC VIDEO + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR) VIDEO SIGNAL TIME SCALE = 5µs/DIV OUT = 500mV/DIV SYNC_OUT = 500mV/DIV TIMEBASE = 1ms/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV CHANNEL 1 OUTPUT SYNC_OUT FIGURE 19. SYNC_OUT SIGNAL FIGURE 20. LUMA CLAMP RESPONSE TO POSITIVE TRANSIENT (CHANNEL 1) INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR) INPUT = NTSC VIDEO + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR) TIMEBASE = 2ms/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV TIMEBASE = 200µs/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV CHANNEL 1 OUTPUT CHANNEL 2 OUTPUT FIGURE 21. LUMA CLAMP RESPONSE TO NEGATIVE TRANSIENT (CHANNEL 1) INPUT = NTSC S-VIDEO (CHROMA) + 2Hz SQUARE WAVE (BEFORE COUPLING CAPACITOR) FIGURE 22. CHROMA CLAMP RESPONSE TO POSITIVE TRANSIENT (CHANNEL 2) 100 RMS NOISE = 1.31mV OUTPUT REFERRED TIMEBASE = 2ms/DIV INPUT: 500mV/DIV OUTPUT: 500mV/DIV µV/√Hz 10 CHARGE PUMP NOISE, CONTRIBUTES ONLY A SMALL PERCENTAGE OF THE OVERALL NOISE 1 CHANNEL 2 OUTPUT 0.1 0.01 FIGURE 23. CHROMA CLAMP RESPONSE TO NEGATIVE TRANSIENT (CHANNEL 2) 10 0M 2M 4M 6M 8M 10M 12M 14M 16M 18M 20M FREQUENCY (Hz) FIGURE 24. NOISE SPECTRUM FN6267.1 June 11, 2008 ISL59832 Typical Performance Curves VCP = VS = 3.3V, CF = 0.1µF, CS = 0.22µF, CFIL = 0.4µF, CIN1= CIN2 = 0.1µF, RL1= RL2 = 150Ω. 0 VS = VCP = +3.3V -10 RL = 150Ω VOUT = 0 TO 2VP, SINE WAVE -20 THD (dBc) TIME SCALE = 20ns/DIV VERTICAL SCALE = 20mV/DIV -30 -40 fIN = 500kHz -50 fIN = 5MHz -60 -70 0.5 0.8 1.1 1.4 1.7 2.0 OUTPUT VOLTAGE (V) FIGURE 25. CHARGE PUMP FEEDTHROUGH AT AMPLIFIER OUTPUT FIGURE 26. THD (dBc) vs OUTPUT VOLTAGE (VP-P) POWER DISSIPATION (W) 4.5 4.0 3.5 3.0 2.5 16 LD TQFN PACKAGE 4mmx4mm θJA = +46°C/W 2.0 1.5 1.0 0.5 0 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 AMBIENT TEMPERATURE (°C) FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Description of Operation and Application Information Theory of Operation The ISL59832 is a single supply video driver with a reconstruction filter and an on-board charge pump. It is designed to drive SDTV displays with S-video (Y-C) or composite video (CV) signals. The input signals can be AC or DC-coupled. When AC-coupled, a sync tip clamp forces the blank level to ground at the output of Channel 1 and a keyed clamp forces the average level of Channel 2 to ground. The ISL59832 is capable of driving two AC- or DCcoupled standard video loads and has a 4th order Butterworth reconstruction filter with nominal -3dB frequency set to 10MHz, providing 40dB of attenuation at 27MHz. The ISL59832 is designed to operate with a single supply voltage range ranging from 3.0V to 3.6V. This eliminates the need for a split supply with the incorporation of a charge pump capable of generating a bottom rail as much as 1.5V below ground; providing a 4.8V range on a single 3.3V supply. This performance is ideal for NTSC video with negative-going sync pulses. Output Amplifier The ISL59832 output amplifiers provide a gain of +6dB. The Channel 1 output amplifier is able to drive a 2.8VP-P video 11 signal into a 150Ω load to ground, while the Channel 2 amplifier is able to drive a 2.8VP-P into a 150Ω or 75Ω load to ground. The outputs are highly-stable, low distortion, low power, high frequency amplifiers capable of driving moderate (10pF) capacitive loads. Input/Output Range The ISL59832 inputs have a dynamic range of 0 to 1.4VP-P. This allows the device to handle the maximum possible video signal inputs. As the input signal moves outside the specified range, the output signal will exhibit increasingly higher levels of harmonic distortion. The Charge Pump The ISL59832 charge pump provides a bottom rail up to 1.5V below ground while operating on a 3.0V to 3.6V power supply. The charge pump is driven by an internal 13MHz clock. To reduce the noise on the power supply generated by the charge pump connect a lowpass RC-network between FN6267.1 June 11, 2008 ISL59832 VEEOUT and VEEIN. See the Typical Application Circuit for further information. VEEOUT Pin VEEOUT is the output pin for the charge pump. Keep in mind that the output of this pin is a fully regulated supply that must be properly bypassed. Bypass this pin with a 0.47µF ceramic capacitor placed as close to the pin and connected to the ground plane of the board. SYNC DETECTOR AND CLAMP TIMING Channel 1 and Channel 3 also have sync detectors whose outputs are available at SYNC_OUT. The slice level for the sync detector is between 100 to 200mV. This means that if the signal level is below 100mV at Channel 1, then SYNC_OUT is high. If the signal level is above 200mV then SYNC_OUT is low. Figure 28 shows the operation of the sync detector. NTSC LUMINANCE CHANNEL 1 INPUT VEEIN Pin +1.00V VEEIN is the subtrate connection for the ISL59832. To reduce the noise on the power supply generated by the charge pump, connect a lowpass RC-network between VEEOUT and VEEIN. See the “S-Video Typical Application Circuit” on page 6 for further information. +300mV Video Performance 100mV < VSLICE < 200mV +0mV DIFFERENTIAL GAIN/PHASE For good video performance, an amplifier is required to maintain the same output impedance and the same frequency and phase response as DC levels are changed at the output. Special circuitry has been incorporated into the ISL59832 to reduce the output impedance variation with the current output. This results in outstanding differential gain and differential phase specifications of 0.45% and 0.15°, while driving 150Ω at a gain of +2V/V. NTSC The ISL59832, generating a negative rail internally, is ideally suited for NTSC video with its accompanying negative-going sync signals. S-VIDEO For a typical S-video application, connect the luma signal to Channel 1, and connect the chrominance signal to Channel 2. For clamp timing connect SYNC_OUT to SYNC_IN. See the “S-Video Typical Application Circuit” on page 6. AC-Coupled Inputs SYNC TIP CLAMP (CHANNEL 1) The ISL59832 features a sync tip clamp that sets the black level of the output video signal to ground. This ensures that the sync-tip voltage level will be approximately -300mV at the back-termination resistor of a standard video load. The clamp is activated whenever the input voltage falls below 0V. The correction voltage required to do this is stored across the input AC-coupling capacitor. Refer to “S-Video Typical Application Circuit” on page 6 for a detailed diagram. SYNC_OUT +3.3V +0mV FIGURE 28. SYNC DETECTOR SLICE LEVEL DC-Coupled Inputs (Channel 1) When DC-coupling the inputs ensure that the lowest signal level is greater than +50mV to prevent the clamp from turning on and distorting the output. When DC-coupled the ISL59832 shifts the signal by -620mV. Amplifier Disable The ISL59832 can be disabled and its outputs placed in high impedance states. The turn-off time is around 10ns and the turn-on time is around 35µs. The turn-on time is longer because extra time is needed for the charge pump to settle before the amplifiers are enabled. When disabled, the device supply current is reduced to 2µA typically, reducing power consumption. The device’s power-down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to the GND pin. Applying a signal that is less than 0.8V above GND will disable the device. The device will be enabled when the ENABLE signal is 2V above GND. Output Drive Capability The maximum output current for the ISL59832 is ±50mA. Maximum reliability is maintained if the output current never exceeds ±50mA, after which the electro-migration limit of the process will be exceeded and the part will be damaged. This limit is set by the design of the internal metal interconnections. KEYED CLAMP (CHANNEL 2) Driving Capacitive Loads and Cables Channel 2 has a keyed clamp which sets the output to ground when SYNC_IN is driven to the logic high state. SYNC_IN may be connected to SYNC_OUT which ensures that Channel 2 clamps during the sync interval for Y-C applications. The ISL59832, internally-compensated to drive 75Ω cables, will drive 10pF loads in parallel with 150Ω or 75Ω with less than 1.3dB of peaking. 12 FN6267.1 June 11, 2008 ISL59832 Power Dissipation With the high output drive capability of the ISL59832, it is possible to exceed the +150°C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for an application to determine if load conditions or package types need to be modified to assure operation of the amplifier in a safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 1: T JMAX – T AMAX PD MAX = --------------------------------------------Θ JA (EQ. 1) Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature ΘJA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: for sourcing: V OUT i PD MAX = V S × I SMAX + ( V S – V OUT i ) × ----------------RL i (EQ. 2) for sinking: PD MAX = V S × I SMAX + ( V OUT i – V S ) × I LOAD i (EQ. 3) By setting Equation 1 equal to Equation 2 and 3, we can solve for the output current and RLOAD values needed to avoid exceeding the maximum junction temperature. Power Supply Bypassing and Printed Circuit Board Layout As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Strip line design techniques are recommended for the input and output signal traces to help control the characteristic impedance. Furthermore, the characteristic impedance of the traces should be 75Ω. Trace lengths should be as short as possible between the output pin and the series 75Ω resistor. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, a single 4.7µF tantalum capacitor in parallel with a 0.1µF ceramic capacitor from VS and VCP to GND will suffice. The AC performance of this circuit depends greatly on the care taken in designing the PC board. The following are recommendations to achieve optimum high frequency performance from your PC board. • Use low inductance components, such as chip resistors and chip capacitors whenever possible. • Minimize signal trace lengths. Trace inductance and capacitance can easily limit circuit performance. Avoid sharp corners; use rounded corners when possible. Vias in the signal lines add inductance at high frequency and should be avoided. PCB traces longer than 1" begin to exhibit transmission line characteristics with signal rise/fall times of 1ns or less. To maintain frequency performance with longer traces, use striplines. VS = Supply voltage • Match channel-to-channel analog I/O trace lengths and layout symmetry. This will minimize propagation delay mismatches. ISMAX = Maximum quiescent supply current • Route all signal I/O lines over continuous ground planes (i.e. no split planes or PCB gaps under these lines). Where: VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current i = Number of output channels • Place termination resistors in their optimum location as close to the device as possible. • Use good quality connectors and cables, matching cable types and keeping cable lengths to a minimum when testing. • Place flying and output capacitor as close to the device as possible for the charge pump. • Decouple well, using a minimum of 2 power supply decoupling capacitors, placed as close to the device as possible. Avoid vias between the capacitor and the device because vias adds unwanted inductance. Larger caps may be farther away. When vias are required in a layout, they should be routed as far away from the device as possible. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 13 FN6267.1 June 11, 2008 ISL59832 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A MILLIMETERS D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW 0.10 M C A B (N-2) (N-1) N b L SYMBOL QFN44 QFN38 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 Basic - Reference 8 Basic - Reference 8 Basic - D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 1 2 3 6.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 0.50 L 0.55 0.40 0.53 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 MILLIMETERS PIN #1 I.D. 3 QFN32 SYMBOL QFN28 QFN24 QFN20 QFN16 A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SEATING PLANE TOLERANCE NOTES E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 11 2/07 0.08 C N LEADS & EXPOSED PAD SEE DETAIL "X" NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. SIDE VIEW 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device. (c) C 5. NE is the number of terminals on the “E” side of the package (or Y-direction). 2 A (L) A1 N LEADS DETAIL X 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 14 FN6267.1 June 11, 2008