A5985 Datasheet

A5985
DMOS Microstepping Driver with Translator
and Overcurrent Protection
FEATURES AND BENEFITS
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Drop-in replacement for A4988
Proprietary Adaptive Percent Fast Decay option
Low RDS(on) outputs
Single supply
Microstepping up to 32 microsteps per full step
Full torque step modes
Short-to-ground protection
Shorted load protection
Short-to-battery protection
Fault output
Low current Sleep mode, < 10 µA
Thin profile QFN
Thermal shutdown circuitry
Synchronous rectification for low power dissipation
Internal UVLO
Crossover-current protection
APPLICATIONS
• Video Security Cameras
• Printers
• Scanners
• Robotics
• ATM
• POS
DESCRIPTION
The A5985 is a complete microstepping motor driver with
built-in translator for easy operation. It is designed to operate
bipolar stepper motors from full-step up to 1/32 step modes.
Step modes are selectable by MSx logic inputs. It has an output
drive capacity of up to 40 V and ±2 A.
A5985 introduces a proprietary Adaptive Percent Fast Decay
(APFD) algorithm to optimize the current waveform over a
wide range of stepper speeds and stepper motor characteristics.
APFD adjusts on-the-fly the amount of fast decay during a
PWM cycle to keep current ripple at a low level over the
various operating conditions. This adaptive feature improves
performance of the system resulting in reduced audible motor
noise, reduced vibration, and increased step accuracy.
The translator is the key to the easy implementation of the
A5985. Simply inputting one pulse on the STEP input drives
the motor one microstep. There are no phase sequence tables,
high frequency control lines, or complex interfaces to program.
The A5985 interface is an ideal fit for applications where a
complex microprocessor is unavailable or is overburdened.
Internal synchronous rectification control circuitry is provided
to improve power dissipation during PWM operation. Internal
circuit protection includes: thermal shutdown with hysteresis,
undervoltage lockout (UVLO), and crossover-current
protection. Special power-on sequencing is not required.
Continued on the next page…
5V
0.1 µF
0.1 µF
5 kΩ
SLEEP
ROSC
CP1
CP2
VCP
VBB2
STEP
MS1
Microcontroller or
Controller Logic
MS2
MS3
VBB1
OUT1A
A5985
OUT1B
SENSE1
DIR
ENABLE
RESET
5V
5 kΩ
OUT2A
VREF
nFAULT
OUT2B
GND
PAD
Typical Application Diagram
5985-DS
SENSE2
100 µF
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Package:
DESCRIPTION (continued)
The A5985 is supplied in a surface-mount QFN package (ET), 5 mm
× 5 mm, with a nominal overall package height of 0.90 mm and an
exposed pad for enhanced thermal dissipation. It is lead (Pb) free
(suffix –T), with 100% matte-tin-plated leadframes.
28-contact QFN
with exposed thermal pad
5 mm × 5 mm × 0.90 mm
(ET package)
Not to scale
SPECIFICATIONS
Selection Guide
Part Number
Package
Packing
A5985GETTR-T
28-contact QFN with exposed thermal pad
1500 pieces per 7-in. reel
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
Load Supply Voltage
VBB
40
V
Output Current
IOUT
±2
A
Logic Input Voltage
VIN
Motor Outputs Voltage
Sense Voltage
Reference Voltage
Operating Ambient Temperature
Maximum Junction
Storage Temperature
VSENSE
VREF
–0.3 to 6
V
–2.0 to VBB + 2 V
V
–0.5 to 0.5
V
5.5
V
–40 to 105
ºC
TJ(max)
150
ºC
Tstg
–55 to 150
ºC
TA
Range G
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
2
A5985
Specifications
Functional Block Diagram
Pin-out Diagrams and Terminal List Table
Electrical Characteristics
Thermal Characteristics
Logic Interface
Functional Description
DMOS Microstepping Driver with Translator
And Overcurrent Protection
2
4
5
6
7
8
9
Device Operation
9
Stepping Current Control 9
100 Percent Torque Operation
9
9
Microstep Select (MSx)
Reset Input ( R̄¯ Ē¯ S̄¯ Ē¯ T̄¯ )
9
Step Input (STEP)
12
Direction Input (DIR)
12
12
Internal PWM Current Control
Blanking12
12
ROSC
Charge Pump (CP1 and CP2)
12
¯ Ē¯ )
Enable Input ( Ē¯ N̄¯ Ā¯ B̄¯ L̄
12
¯ Ē
¯ Ē
¯ P̄
¯ )
13
Sleep Mode ( S̄ L̄
Synchronous Rectification
13
Table of Contents
Protection Functions
Fault Output (nFAULT)
Thermal or Undervoltage Fault Shutdown
Overcurrent Protection
13
13
13
13
Application Information
14
Package Outline Drawing
25
Layout
Pin Circuit Diagrams
Phase Current Diagrams
Full Step (100% Torque)
Half Step (100% Torque)
Sixteenth Step
Thirty-Secondth Step
Full Step (Modified)
Half Step (Modified)
Eighth Step
Quarter Step
Stepping Phase Tables
Full Torque Modes
Common Modes
14
15
16
16
16
17
17
18
18
19
19
20
20
21
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
0.1 µF
ROSC
Internal
Regulator
CP1
CP2
Charge
Pump
OSC
VCP
0.1 µF
REF
DMOS Full Bridge
DAC
VBB1
OUT1A
OUT1B
PWM Latch
Blanking
Mixed Decay
STEP
DIR
OCP
Gate
Drive
RESET
MS1
100 kΩ
Translator
MS2
SENSE1
DMOS Full Bridge
Control
Logic
100 kΩ
PWM Latch
Blanking
Mixed Decay
100 kΩ
ENABLE
OUT2B
SENSE2
Fault
RS2
DAC
SLEEP
RS1
OUT2A
OCP
MS3
VBB2
5V
VREF
nFAULT
GND
PAD
Functional Block Diagram
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
22 VBB1
23 SENSE1
24 OUT1A
25 NC
26 OUT2A
27 SENSE2
28 VBB2
Pin-Out Diagram
OUT2B
1
21 OUT1B
ENABLE
2
20 NC
GND
3
CP1
4
CP2
5
17 REF
VCP
6
16 STEP
NC
7
15 MS3
19 DIR
SLEEP 14
ROSC 13
NC 11
MS2 10
9
18 GND
RESET 12
Terminal List Table
MS1
nFAULT 8
PAD
Name
Number
CP1
4
Charge pump capacitor terminal
Description
CP2
5
Charge pump capacitor terminal
DIR
19
Logic input
Ē¯ N̄¯ Ā¯ B̄¯ L̄¯ Ē¯
2
Logic input
GND
3, 18
MS1
9
Ground*
Logic input
MS2
10
Logic input
MS3
15
Logic input
NC
7, 11, 20, 25
No connection
nFAULT
8
Logic output
OUT1A
24
DMOS Full Bridge 1 Output A
OUT1B
21
DMOS Full Bridge 1 Output B
OUT2A
26
DMOS Full Bridge 2 Output A
OUT2B
1
DMOS Full Bridge 2 Output B
REF
17
Gm reference voltage input
R̄¯ Ē¯ S̄¯ Ē¯ T̄¯
12
Logic input
ROSC
13
Timing set
SENSE1
23
Sense resistor terminal for Bridge 1
SENSE2
27
Sense resistor terminal for Bridge 2
S̄¯ L̄¯ Ē¯ Ē¯ P̄¯ 14
Logic input
STEP
16
Logic input
VBB1
22
Load supply
VBB2
28
Load supply
VCP
6
Reservoir capacitor terminal
PAD
–
Exposed pad for enhanced thermal dissipation*
*The GND pins must be tied together externally by connecting to the PAD ground plane
under the device.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
A5985
DMOS Microstepping Driver with Translator
And Overcurrent Protection
ELECTRICAL CHARACTERISTICS1 valid at TA = 25°C, VBB = 40 V (unless otherwise noted)
Characteristics
Symbol
Test Conditions
Min.
Typ.2
Max.
Units
Operating
8
–
40
V
During Sleep Mode
0
–
40
V
Source + Sink Driver, IOUT = –2 A,
TA = 25°C
–
640
860
mΩ
Source Diode, IF = –2 A
–
–
1.4
V
Sink Diode, IF = 2 A
–
–
1.4
V
10% to 90%
50
100
150
ns
Output Drivers
Load Supply Voltage Range
Output On Resistance
Body Diode Forward Voltage
Output Driver Slew Rate
Motor Supply Current
VBB
RDS(on)
VF
SROUT
fPWM < 50 kHz
–
7.5
10
mA
Operating, outputs disabled
–
6.5
8
mA
Sleep Mode
–
–
10
μA
VIN(1)
2
–
–
V
VIN(0)
–
–
0.8
V
VIN(SLEEP)
IIN(1)
IIN(0)
–
–20
–20
–
<1.0
<1.0
0.4
20
20
V
µA
µA
–
100
–
kΩ
VHYS(IN)
200
–
550
mV
tBLANK
0.7
1
1.3
μs
ROSC = 5 V
20
30
40
μs
ROSC = GND
13
16
19
μs
ROSC = 25 kΩ
23
30
37
μs
IBB
Control Logic
Logic Input Voltage
Logic Input Current
Microstep Select Pins Internal PullDown Resistance
Logic Input Hysteresis
Blank Time
Fixed Off-Time
RMSx
tOFF
MS1, MS2, or MS3 pin
Reference Input Voltage Range
VREF
0
–
4
V
Reference Input Current
IREF
–3
0
3
μA
VREF = 2 V, %ITripMAX = 38.27%
–
–
±15
%
Current Trip-Level Error3
errI
VREF = 2 V, %ITripMAX = 70.71%
–
–
±5
%
Crossover Dead Time
tDT
Fault Output Voltage
VRST
VREF = 2 V, %ITripMAX = 100.00%
Fault Output Leakage Current
Protection
Overcurrent Protection Threshold4
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
ILK
–
–
±5
%
100
475
800
ns
nFAULT pin, IOUT = 1 mA
–
–
0.5
V
nFAULT pin, no fault, pull-up to 5 V
–
–
1
µA
IOCPST
2.6
–
–
A
TTSD
–
165
–
°C
TTSDHYS
–
20
–
°C
1 For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for individual units, within the
specified maximum and minimum limits.
3V
ERR = [(VREF/8) – VSENSE] / (VREF/8).
4 Overcurrent protection (OCP) is tested at T = 25°C in a restricted range and guaranteed by characterization.
A
2 Typical
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic
Symbol
Package Thermal Resistance
Test Conditions*
RθJA
ET package; estimated, on 4-layer PCB, based on JEDEC standard
Value
Units
32
ºC/W
*In still air. Additional thermal information available on Allegro website.
Maximum Power Dissipation, PD(max)
5.5
5.0
4.5
Power Dissipation, PD (W)
4.0
R
θJ
3.5
A
=
32
3.0
ºC
/W
2.5
2.0
1.5
1.0
0.5
0.0
20
40
60
80
100
120
Temperature (°C)
140
160
180
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
7
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
tA
tB
STEP
tC
tD
MSx
RESET, or DIR
Time Duration
Symbol
Typ.
Unit
tA
1
μs
STEP minimum, HIGH pulse width
STEP minimum, LOW pulse width
tB
1
μs
Setup time, input change to STEP
tC
400
ns
Hold time, input change to STEP
tD
400
ns
Figure 1: Logic Interface Timing Diagram
Table 1: Microstep Resolution Truth Table
MS3
MS2
MS1
Microstep Resolution
0
0
0
Full step (100% torque)
0
0
1
Half step (100% torque)
0
1
0
Sixteenth step
0
1
1
Thirty-secondth step
1
0
0
Full step (modified)
1
0
1
Half step (modified)
1
1
0
Quarter step
1
1
1
Eighth step
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
8
A5985
DMOS Microstepping Driver with Translator
And Overcurrent Protection
FUNCTIONAL DESCRIPTION
Device Operation
The A5985 is a complete microstepping motor driver with a
built-in translator for easy operation with minimal control lines.
It is designed to operate bipolar stepper motors in full, half, quarter, eighth, sixteenth, or thirty-secondth step modes. The currents
in each of the two output full-bridges and all of the N-channel
DMOS FETs are regulated with fixed off-time PWM (pulse
width modulated) control circuitry. At each step, the current for
each full-bridge is set by the value of its external current-sense
resistor (RS1 and RS2), a reference voltage (VREF), and the output
voltage of its DAC (which in turn is controlled by the output of
the translator).
At power-on or reset, the translator sets the DACs and the phase
current polarity to the initial Home state (shown in the Phase
Current Diagrams section), and the current regulator to Mixed
Decay Mode for both phases. When a step command signal
occurs on the STEP input, the translator automatically sequences
the DACs to the next level and current polarity. (See Table 2 for
the current-level sequence.) The microstep resolution is set by
the combined effect of the MSx inputs, as shown in Table 1.
Stepping Current Control
The A5985 has two methods of current control. The first method
of current control is called Adaptive Percent Fast Decay (APFD).
APFD is selected by connecting pin ROSC to GND. Essentially,
the IC determines the proper amount of fast decay on both rising
and falling currents. By only adding fast decay when needed, the
output current more accurately tracks the input command from
the D-to-A converter and solves the basic problem of current discontinuity through zero when stepping at slow speeds (see Figure
4). This will result in a performance advantage for slow-speed
high-resolution stepping such as with security camera applications. An additional benefit of APFD is reduced current ripple
across the various operating conditions and motor characteristics.
when current is rising and mixed decay mode (31.25%) when
current is falling. This method is exactly the same as A4984
series of stepper motor drivers. This method may be desired for
drop-in applications to A4984 series. The current waveform and
motor performance should be identical to A4984. The mixed
decay waveforms for this method are shown in Figure 2. This
form of current control is selected by connecting pin ROSC to
greater than 3 V or by connecting a resistor from ROSC to GND.
The Resistor option is used to adjust the off-time as desired (see
ROSC section).
100 Percent Torque Operation
In full- and half-step modes, the device can be programmed so
both phases are at ±100% current levels for full step mode, and
either ±100% or 0% for half step mode.
Microstep Select (MSx)
The microstep resolution is set by the voltage on logic inputs
MSx, as shown in Table 1. Each MSx pin has an internal 100 kΩ
pull-down resistance. When changing the step mode the change
does not take effect until the next STEP rising edge.
If the step mode is changed without a translator reset, and absolute position must be maintained, it is important to change the
step mode at a step position that is common to both step modes in
order to avoid missing steps. When the device is powered down,
or reset due to TSD or an over current event the translator is set to
the home position which is by default common to all step modes.
Reset Input (RESET)
¯S̄¯Ē¯T̄¯ input sets the translator to a predefined Home state
The R̄¯Ē
(shown in Phase Current Diagrams section), and turns off all of
¯S̄¯Ē¯T̄¯
the FET outputs. All STEP inputs are ignored until the R̄¯Ē
input is set to high.
The other method of current control utilizes slow decay mode
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
VSTEP
100.00
70.71
See Enlargement A
IOUT
0
–70.71
–100.00
Enlargement A
toff
IPEAK
tFD
tSD
Slow Decay
Mixed Decay
IOUT
Fa
st
De
ca
y
t
Symbol
toff
IPEAK
Characteristic
Device fixed off-time
Maximum output current
tSD
Slow decay interval
tFD
Fast decay interval
IOUT
Device output current
Figure 2: Current Decay Modes Timing Chart
10
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Slow
Decay
Mixed
Decay
Slow
Decay
Mixed
Decay
Slow
Decay
Mixed
Decay
Slow
Decay
Mixed
Decay
Missed
Step
Step input 10 V/div.
t → , 1 s/div.
Figure 3: Missed Steps in Low-Speed Microstepping
Mixed Decay
ILOAD 500 mA/div.
Step input 10 V/div.
No Missed
Steps
t → , 1 s/div.
Figure 4: Continuous Stepping Using APFD (ROSC Pin Grounded)
11
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Step Input (STEP)
Blanking
A low-to-high transition on the STEP input sequences the translator and advances the motor one increment. The translator controls
the input to the DACs and the direction of current flow in each
winding. The size of the increment is determined by the combined
state of the MSx inputs.
This function blanks the output of the current sense comparators
when the outputs are switched by the internal current control
circuitry. The comparator outputs are blanked to prevent false
overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, tBLANK (µs), is approximately
Direction Input (DIR)
This determines the direction of rotation of the motor. Setting
to logic high and logic low set opposite rotational directions.
Changes to this input do not take effect until the next STEP input
rising edge. Refer to Phase Current diagrams (Figures 10 to 17).
For DIR = LOW, currents change sequentially clockwise around
the circle. For DIR = HIGH, counterclockwise.
Internal PWM Current Control
tBLANK ≈ 1 µs
ROSC
The configuration of the ROSC terminal determines both the
method of current control as well as the fixed off-time (tOFF).
ROSC
Decay Mode
tOFF
GND
APFD
(Adaptive Percent Fast Decay
Mode)
16 µs
Each full-bridge is controlled by a fixed off-time PWM current
control circuit that limits the load current to a desired value,
Resistor to
Slow Decay Rising Current Steps
ROSC/825 (µs)
ITRIP . Initially, a diagonal pair of source and sink FET outputs
GND
Mixed Decay Falling Current Steps
are enabled and current flows through the motor winding and the
Pulled Up to
Slow Decay Rising Current Steps
30 µs
> 3 V Supply Mixed Decay Falling Current Steps
current sense resistor, RSx. When the voltage across RSx equals
the DAC output voltage, the current sense comparator resets the
PWM latch. The latch then turns off either the source FET (when Charge Pump (CP1 and CP2)
in Slow decay mode) or the sink and source FETs (when in Mixed The charge pump is used to generate a gate supply greater than
decay mode).
that of VBB for driving the source-side FET gates. A 0.1 µF
ceramic
capacitor, should be connected between CP1 and CP2. In
The maximum value of current limiting is set by the selection of
addition,
a 0.1 µF ceramic capacitor is required between VCP and
RSx and the voltage at the VREF pin. The transconductance funcVBB,
to
act
as a reservoir for operating the high‑side FET gates.
tion is approximated by the maximum value of current limiting,
ITripMAX (A), which is set by
ITripMAX = VREF / ( 8
× RS)
where RS is the resistance of the sense resistor (Ω) and VREF is
the input voltage on the REF pin (V).
The DAC output reduces the VREF output to the current sense
comparator in precise steps, such that
Itrip = (%ITripMAX / 100)
× ITripMAX
(See table 2 for %ITripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Enable Input (ENABLE)
This input turns on or off all of the FET outputs. When set to a
logic high, the outputs are disabled. When set to a logic low, the
internal control enables the outputs as required. The translator
inputs STEP, DIR, and MSx, as well as the internal sequencing
logic, all remain active, independent of the Ē¯N̄
¯Ā
¯ B̄¯L̄¯ Ē¯ input state.
Sleep Mode (SLEEP)
To minimize power consumption when the motor is not in use,
SLEEP disables much of the internal circuitry including the
12
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A5985
DMOS Microstepping Driver with Translator
And Overcurrent Protection
output FETs, current regulator, and charge pump. A logic low
on the S̄L̄¯Ē¯Ē¯P̄¯ pin puts the A5985 into Sleep mode. A logic high
allows normal operation, as well as start-up (at which time the
A5985 drives the motor to the Home microstep position). When
emerging from Sleep mode, in order to allow the charge pump to
stabilize, provide a delay of 1 ms before issuing a Step command.
THERMAL OR UNDERVOLTAGE FAULT SHUTDOWN
In the event of a fault, overtemperature (excess TJ) or an undervoltage (on VCP), the FET outputs of the A5985 are disabled
until the fault condition is removed. At power-on, the UVLO
(undervoltage lockout) circuit disables the FET outputs and resets
the translator to the Home state.
Synchronous Rectification
OVERCURRENT PROTECTION
A current monitor will protect the IC from damage due to output
shorts. If a short is detected, the IC will latch the fault and disable
the outputs. The fault latch can only be cleared by coming out of
Sleep mode or by cycling the power to VBB. During OCP events,
Absolute Maximum Ratings may be exceeded for a short period
of time before the device latches (see Figure 5).
When a PWM-off cycle is triggered by an internal fixed-off time
cycle, load current recirculates according to the decay mode
selected by the control logic. This synchronous rectification
feature turns on the appropriate FETs during current decay, and
effectively shorts out the body diodes with the low FET RDS(on).
This reduces power dissipation significantly, and can eliminate
the need for external Schottky diodes in many applications. Synchronous rectification turns off when the load current approaches
zero (0 A), preventing reversal of the load current.
Protection Functions
FAULT OUTPUT (nFAULT)
An open drain fault output is provided to notify the user if the IC
has been disabled due to an OCP event. If an OCP event is triggered the device will be disabled and the outputs will be latched
off. The active low nFAULT output will be enabled. The latch can
¯Ē¯Ē¯P̄¯ or R̄¯Ē¯S̄¯Ē¯T̄
¯ low, or by bringing
be reset by commanding S̄L̄
VBB below its UVLO threshold.
5 A / div.
Fault
latched
t→
Figure 5: Overcurrent Event
13
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
APPLICATION INFORMATION
Layout
The printed circuit board should use a heavy groundplane. For
optimum electrical and thermal performance, the A5985 must be
soldered directly onto the board. On the underside of the A5985
package is an exposed pad, which provides a path for enhanced
thermal dissipation. The thermal pad should be soldered directly
to an exposed surface on the PCB. Thermal vias are used to
transfer heat to other layers of the PCB (see Figure 6).
In order to minimize the effects of ground bounce and offset
issues, it is important to have a low impedance single-point
ground, known as a star ground, located very close to the device.
By making the connection between the pad and the ground plane
directly under the A5985, that area becomes an ideal location for
a star ground point. A low-impedance ground will prevent ground
bounce during high-current operation and ensure that the supply
voltage remains stable at the input terminal.
A5985
The two input capacitors should be placed in parallel, and as close
to the device supply pins as possible (see Figure 8). The ceramic
capacitor (C7) should be closer to the pins than the bulk capacitor
(C2). This is necessary because the ceramic capacitor will be
responsible for delivering the high-frequency current components.
The sense resistors, RSx , should have a very low-impedance
path to ground, because they must carry a large current while
supporting very accurate voltage measurements by the current
sense comparators. Long ground traces will cause additional
voltage drops, adversely affecting the ability of the comparators
to accurately measure the current in the windings. The SENSEx
pins have very short traces to the RSx resistors and very thick,
low-impedance traces directly to the star ground underneath the
device. If possible, there should be no other components on the
sense circuits.
Solder
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
PCB
Thermal (2 oz.)
Thermal Vias
Figure 6: Soldering Cross-Section
OUT2B
OUT2A OUT1A
OUT2B
OUT1B
OUT1A
OUT2A
R4
OUT1B
R5
ENABLE
VBB1
STEP
SLEEP
ROSC
A5985
nFAULT
VCP
MS1
GND
OUT2A
REF
CP2
C4
DIR
GND
CP1
MS2
C3
U1
OUT1B
PAD
GND
C7
SENSE1
OUT2B
RESET
GND
OUT1A
VBB2
R5
R4
SENSE2
C7
GND
MS3
C3
C4
GND
BULK
ROSC
C2
C2
ROSC
CAPACITANCE
VBB
Figure 7: ET Package Circuit Layout
VBB
Figure 8: ET Package Typical Application
14
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Pin Circuit Diagrams
VBB
VBB
VCP
CP1
CP2
GND
GND
GND
48 V
GND
PGND
GND
9a
8V
9b
SENSE
MSx
DIR
VREF
ROSC
SLEEP
RESET
ENABLE
STEP
VINT
DMOS
Parasitic
GND
9c
VBB
OUT
DMOS
Parasitic
8V
GND
9d
DMOS
Parasitic
GND
SENSE
9e
Figure 9: Pin Circuit Diagrams
15
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A5985
DMOS Microstepping Driver with Translator
And Overcurrent Protection
I2(A→Β)
100%
2
1
I1(A→Β)
100%
4
3
Figure 10: Full Step (100% Torque)
MSX pins = 000. See Table 2 for step number detail
I2(A→Β)
4
100% 3
2
I1(A→Β)
1
5
100%
6
7
8
Figure 11: Half Step (100% Torque)
MSX pins = 001. See Table 2 for step number detail
16
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
I2(A→Β)
17
25
70%
33
9
70%
1
I1(A→Β)
57
41
49
Figure 12: Sixteenth Step
MSX pins = 010. See Table 3 for step number detail
I2(A→Β)
33
49
70%
65
17
70%
1
I1(A→Β)
113
81
97
Figure 13: Thirty-Second Step
MSX pins = 011. See Table 3 for step number detail
17
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
I2(A→Β)
2
1
70%
I1(A→Β)
70%
4
3
Figure 14: Full Step (70% Torque)
MSX pins = 100. See Table 3 for step number detail
I2(A→Β)
3
4
2
70%
5
70%
1
I1(A→Β)
8
6
7
Figure 15: Half Step (70% Torque)
MSX pins = 101. See Table 3 for step number detail
18
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
I2(A→B)
5
7
3
70%
9
I1(A→B)
1
70%
15
11
13
Figure 16: Quarter Step
MSX pins = 110. See Table 3 for step number detail
I2(A→Β)
9
13
70%
17
5
70%
1
I1(A→Β)
29
21
25
Figure 17: Eighth Step
MSX pins = 111. See Table 3 for step number detail
19
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Stepping Phase Tables
Table 2: Stepping Phase Table, Full Torque Modes
Full (100%)
1
2
3
4
Angle
Winding Current 1
(%)
1
0
100
0
2
45
100
100
Half Step (100%)
Winding Current 2
(%)
3
90
0
100
4
135
–100
100
5
180
–100
0
6
225
–100
–100
7
270
0
–100
8
315
100
–100
20
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Table 3: Stepping Phase Table, Common Modes
Full (70%)
Winding Current 1 (%)
Winding Current 2 (%)
1
0
100
0
2
2.8
100
5
3
5.6
100
10
4
8.4
99
15
5
11.3
98
20
6
14.1
97
24
7
16.9
96
29
8
19.7
94
34
1/4 Step
1/8 Step
1/16 Step
1/32 Step
1
1
1
1
2
2
3
4
2
3
5
6
4
7
8
1
Angle
Half (70%)
2
3
5
9
10
6
11
12
4
7
13
14
8
15
16
3
5
9
17
9
22.5
92
38
10
25.3
90
43
11
28.1
88
47
12
30.9
86
51
13
33.8
83
56
14
36.6
80
60
15
39.4
77
63
16
42.2
74
67
17
45
71
71
18
47.8
67
74
19
50.6
63
77
20
53.4
60
80
21
56.3
55
83
22
59.1
51
86
23
61.9
47
88
24
64.7
43
90
25
67.5
38
92
26
70.3
34
94
27
73.1
29
96
28
75.9
24
97
29
78.8
19
98
30
81.6
15
99
31
84.4
10
100
32
87.2
5
100
33
90
0
100
34
92.8
–5
100
Continued on the next page…
21
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Stepping Phase Table, Common Modes (continued)
Full (70%)
Half (70%)
1/4 Step
1/8 Step
10
1/16 Step
1/32 Step
Angle
Winding Current 1 (%)
Winding Current 2 (%)
18
35
95.6
–10
100
36
98.4
–15
99
37
101.3
–20
98
38
104.1
–24
97
39
106.9
–29
96
40
109.7
–34
94
41
112.5
–38
92
42
115.3
–43
90
43
118.1
–47
88
44
120.9
–51
86
45
123.8
–56
83
46
126.6
–60
80
47
129.4
–63
77
48
132.2
–67
74
49
135
–71
71
50
137.8
–74
67
51
140.6
–77
63
52
143.4
–80
60
53
146.3
–83
55
54
149.1
–86
51
55
151.9
–88
47
56
154.7
–90
43
57
157.5
–92
38
58
160.3
–94
34
59
163.1
–96
29
60
165.9
–97
24
61
168.8
–98
19
62
171.6
–99
15
63
174.4
–100
10
64
177.2
–100
5
65
180
–100
0
66
182.8
–100
–5
67
185.6
–100
–10
19
20
6
11
21
22
12
23
24
2
4
7
13
25
26
14
27
28
8
15
29
30
16
31
32
5
9
17
33
34
Continued on the next page…
22
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Stepping Phase Table, Common Modes (continued)
Full (70%)
Half (70%)
1/4 Step
1/8 Step
1/16 Step
18
35
36
10
19
37
38
20
39
40
3
6
11
21
41
42
22
43
44
12
23
45
46
24
47
48
7
13
25
49
50
1/32 Step
Angle
Winding Current 1 (%)
Winding Current 2 (%)
68
188.4
–99
–15
69
191.3
–98
–20
70
194.1
–97
–24
71
196.9
–96
–29
72
199.7
–94
–34
73
202.5
–92
–38
74
205.3
–90
–43
75
208.1
–88
–47
76
210.9
–86
–51
77
213.8
–83
–56
78
216.6
–80
–60
79
219.4
–77
–63
80
222.2
–74
–67
81
225
–71
–71
82
227.8
–67
–74
83
230.6
–63
–77
84
233.4
–60
–80
85
236.3
–55
–83
86
239.1
–51
–86
87
241.9
–47
–88
88
244.7
–43
–90
89
247.5
–38
–92
90
250.3
–34
–94
91
253.1
–29
–96
92
255.9
–24
–97
93
258.8
–19
–98
94
261.6
–15
–99
95
264.4
–10
–100
96
267.2
–5
–100
97
270
0
–100
98
272.8
5
–100
99
275.6
10
–100
Continued on the next page…
23
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Stepping Phase Table, Common Modes (continued)
Full (70%)
Half (70%)
1/4 Step
1/8 Step
1/16 Step
26
51
52
14
27
53
54
28
55
56
4
8
15
29
57
58
30
59
60
16
31
61
62
32
63
64
1/32 Step
Angle
Winding Current 1 (%)
Winding Current 2 (%)
100
278.4
15
–99
101
281.3
20
–98
102
284.1
24
–97
103
286.9
29
–96
104
289.7
34
–94
105
292.5
38
–92
106
295.3
43
–90
107
298.1
47
–88
108
300.9
51
–86
109
303.8
56
–83
110
306.6
60
–80
111
309.4
63
–77
112
312.2
67
–74
113
315
71
–71
114
317.8
74
–67
115
320.6
77
–63
116
323.4
80
–60
117
326.3
83
–55
118
329.1
86
–51
119
331.9
88
–47
120
334.7
90
–43
121
337.5
92
–38
122
340.3
94
–34
123
343.1
96
–29
124
345.9
97
–24
125
348.8
98
–19
126
351.6
99
–15
127
354.4
100
–10
128
357.2
100
–5
24
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
PACKAGE OUTLINE DRAWING
0.30
5.00 ±0.15
1.15
28
1
2
0.50
28
1
A
5.00 ±0.15
3.15
4.80
3.15
29X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
0.90 ±0.10
C
4.80
C
PCB Layout Reference View
0.50
For Reference Only; not for tooling use
(reference JEDEC MO-220VHHD-1)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.73 MAX
B
2
1
28
3.15
3.15
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
C Reference land pattern layout (reference IPC7351
QFN50P500X500X100-29V1M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
ET Package, 28-Pin QFN with Exposed Thermal Pad
25
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
DMOS Microstepping Driver with Translator
And Overcurrent Protection
A5985
Revision History
Revision No.
Revision Date
–
August 14, 2015
Description
Initial Release
Copyright ©2015, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
26
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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