HT7L5821v100.pdf

HT7L5821
Integrated PFC and Quasi-Resonant
Current Mode PWM Controller
Features
Applications
• Integrated Transition Mode (TM) PFC controller
and Quasi-Resonant (QR) flyback controller
• AC/DC NB adapters
• Wide AC input range from 85Vac to 265Vac
• Battery chargers
• Open-frame SMPS
• Integrated 650V JFET quick high voltage start-up
• General LED lighting applications
• Integrated THD PFC stage optimiser
• Industrial, commercial, and residential fixtures
• Brown-out and brown-in protection
• Internal accurate feedback reference voltage: ±2%
General Description
• Internal 9.6ms PWM soft-start
The HT7L5821 is highly integrated device which
includes a Power Factor Correction controller and quasiresonant flyback controller. The high level of functional
integration provides the means for very cost-effective
designs with a minimum of external components.
• High/Low line over-power compensation
• Latched protection – FB pin
♦♦ Over-power and overload protection
♦♦
Short-circuit protection
♦♦
Open-loop protection
In the PFC stage the device uses a transition mode to
provide a regulated output voltage with low system
costs, low harmonic distortion and high power factor.
For QR flyback the device provides higher efficiencies
and lower EMI when compared with conventional
PWM systems.
• External latch triggering – RT Pin
• Adjustable over-temperature latched – RT pin
• VCC pin and output voltage OVP – latched
• Internal over-temperature shutdown – 140°C
The device also includes a range of features to protect
the controller from fault conditions. These include
secondary side open-loop and over-current protection,
VCC pin over-voltage protection, DET pin overvoltage for output over-voltage protection, brownin/out AC input voltage, internal over-temperature
shutdown and adjustable over-temperature protection
using the RT pin with an external NTC resistor.
• 16-pin NSOP package
Application Circuits
AC
16
14
HVS ZCD
6
OPFC
4
CSPFC
3
INV
1
SEL
13 VIN
9
CSPWM
HT7L5821A
VSS
COMP
2
Rev. 1.00
8
OPWM
NC
RT
12
FB
11
1
DET
10
5
15
VCC
7
July 13, 2015
HT7L5821
Block Diagram
INV
INV
OVP
INV
OVP
INV
UVP
INV
UVP
3
2.5V
HVS
16
VCC
7
COMP
CSPFC
SEL
2
4
1
PFC
Select
+
0.8V
E/A
PFC
Control Logic
Zero Current
Detector
UVLO
INV
OVP
QR
Control Logic
5
10
OPFC
14
ZCD
8
OPWM
13
VIN
Brown
In/Out
PFC
Select
Internal
Soft Start
DET
6
INV
UVP
11
Current
Limit
CSPWM
NC
Voltage
Regulator
VDD
OVP
FB
15
OTP
Valley
Detector
OVP
0.5V
9
12
VSS
RT
Pin Assignment
SEL
1
16
HVS
COMP
2
15
NC
INV
3
14
ZCD
CSPFC
4
13
VIN
CSPWM
5
12
RT
OPFC
6
11
FB
VCC
7
10
DET
OPWM
8
9
VSS
HT7L5821A
16 NSOP-A
Rev. 1.00
2
July 13, 2015
HT7L5821
Pin Description
Pin No.
Symbol
1
SEL
Description
PFC output selected pin
2
COMP
3
INV
PFC compensation pin, a capacitor should be placed between COMP and VSS
4
CSPFC
Current sense pin. A resistor is connected to sense the PFC MOSFET current
5
CSPWM
Current sense pin. A resistor is connected to sense the Flyback MOSFET current
6
OPFC
7
VCC
8
OPWM
Voltage sense for PFC output, regulation voltage is 2.5V
Gate drive output to drive the external MOSFET for PFC
Power supply pin
Gate drive output to drive the external MOSFET for Flyback
9
VSS
Ground pin
10
DET
Zero-current detect pin for Flyback
11
FB
Voltage feedback pin for Flyback. Connect a photo-coupler for system regulation
12
RT
External latch pin
13
VIN
Sense input for mains voltage
14
ZCD
Zero-current detect pin for PFC
15
NC
16
HVS
No connection
HVS pin is connected to the AC line voltage through a resistor
Absolute Maximum Ratings
Value
Unit
VCC Supply Voltage
Parameter
-0.3 to 30
V
HVS Voltage
-0.3 to 650
V
SEL, COMP, INV, CSPFC, CSPWM, FB, RT, VIN
-0.3 to 6
V
Maximum Current at ZCD, DET
3 (source), 3 (sink)
mA
Operating Junction Temperature
-40 to 150
°C
Storage Temperature Range
-55 to 150
°C
150
°C
Value
Unit
-40 to 105
°C
Maximum Junction Temperature
Recommended Operating
Parameter
Operating Ambient temperature
Rev. 1.00
3
July 13, 2015
HT7L5821
Electrical Characteristics
Symbol
VCC=15V, Ta=-40~105°C (Ta=Tj), unless otherwise specified
Parameter
Conditions
Min.
Typ.
Max.
Unit
V
VCC Section
VOP
Continuous Operation Voltage
—
—
—
30
VCC-ON
Turn-On Threshold Voltage
—
15
16.5
18
V
—
9
10
11
V
—
VCC-PWM-OFF PWM Off Threshold Voltage
VCC-OFF
Turn-Off Threshold Voltage
7
8
9
V
—
20
—
μA
IDD-ST
Startup Current
VCC=VCC-ON-0.16V,
gate open
IDD-OP
Operating Current
VCC=15V, OPFC,
OPWM=100kHz,
CL-PFC, CL-PWM=2nF
—
—
10
mA
IDD-GREEN
Green Mode Operating Supply Current
(Average)
VCC=15V, CL-PWM=2nF
OPWM=450Hz
—
5.5
—
mA
IDD-PWM-OFF
Operating Current at PWM-Off Phase
VCC=VCC-PWM-OFF - 0.5V
70
120
170
μA
VCC-OVP
VCC Over-Voltage Protection (Latch-Off)
—
26
27.5
29
V
tVCC-OVP
VCC OVP Debounce Time
—
100
150
200
μs
IDD-LATCH
VCC Over-Voltage Protection Latch-Up Holding
VCC=7.5V
Current
—
120
—
μA
HVS Startup Current Source Section
VHVS-MIN
IHVS
Minimum Startup Voltage on HVS Pin
—
Supply Current Drawn from HVS Pin
—
—
50
V
VAC=90V (VDC=120V),
VCC=0V
1.3
—
—
mA
HVS=500V,
VCC=VCC-OFF+1V
—
8
—
μA
VIN and SEL Section
VVIN-UVP
Threshold Voltage for AC Input Under-Voltage
Protection
—
0.85
0.9
0.95
V
VVIN-RE-UVP
Under-Voltage Protection Reset Voltage
(for Startup)
—
1.2
1.25
1.3
V
tVIN-UVP
Under-Voltage Protection Debounce Time
(No Need at Startup and Hiccup Mode)
—
70
100
130
ms
VVIN-SEL-H
High VVIN Threshold for SEL Comparator
SEL ground
2.45
2.5
2.55
V
VVIN-SEL-L
Low VVIN Threshold for SEL Comparator
SEL open
2.25
2.3
2.35
V
tSEL
SEL-Enable Debounce Time
70
100
130
ms
VSEL-OL
Output Low Voltage of SEL Pin
Io=0.1mA
—
1
—
V
ton-max-PFC
PFC Maximum On Time
CSPFC=0v,COMP=5.5V
32
40
48
μs
—
PWM STAGE
AV
Input-Voltage to Current Sense Attenuation(note)
AV=ΔVCS/ΔVFB,
0<VCS<0.9V
ZFB
Input Impedance(note)
FB>VG
IOZ
Bias Current
FB=VOZ
—
VOZ
Zero Duty-cycle Input Voltage
—
0.7
VFB-OLP
Open-Loop Protection Threshold Voltage
—
3.9
4.2
4.5
V
tFB-OLP
The Debounce Time for Open Loop Protection
—
40
50
60
ms
tss
Internal Soft-Start Time(note)
—
—
9.6
—
ms
Rev. 1.00
4
1/2.75 1/3.00 1/3.25
—
20
V
—
kΩ
0.2
—
mA
0.9
1.1
V
July 13, 2015
HT7L5821
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
DET Pin OVP and Valley Detection Section
VDET-OVP
Comparator Reference Voltage
—
2.45
2.5
2.55
V
tDET-OVP
Output OVP(Latched) Debounce Time
—
100
150
200
μs
VDET-HIGH
Upper Clamp Voltage
IDET=1mA
—
5.7
—
V
VDET-LOW
Lower Clamp Voltage
IDET=-1mA
—
-0.4
—
V
tVALLEY-DELAY
Delay Time from Valley Signal Detected to
Output Turn-on(note)
—
150
200
250
ns
tOFF-BNK
Leading-Edge Blanking Time for DET-OVP
(2.5V) and Valley Signal when PWM MOS
Turns Off(note)
—
3
4
5
μs
tTIME-OUT
Time-Out After tOFF-MIN
—
5
6
7
μs
—
PWM Oscillator Section
tON-MAX-PWM Maximum On Time
38
45
52
μs
VFB≥VN
7
8.5
10
μs
VFB=VG
31
36
41
μs
tOFF-MIN
Minimum Off Time
VN
Beginning of Green-On Mode at FB Voltage
Level
—
1.95
2.1
2.25
V
VG
Beginning of Green-Off Mode at FB Voltage
Level
—
1.05
1.2
1.35
V
ΔVG
Hysteresis for Beginning of Green-Off Mode
at FB Voltage Level
—
—
0.1
—
V
SEL open
1.5
1.55
1.6
V
SEL ground
1.5
1.55
1.6
V
SEL open
1.85
1.9
1.95
V
VCTL-PFC-OFF Threshold Voltage on FB Pin to Disable PFC
VCTL-PFC-ON
Threshold Voltage on FB Pin to Enable PFC
SEL ground
1.7
1.75
1.8
V
tPFC-OFF
PFC Disable Debounce Time to Disable PFC
PFC status from on to off
400
500
600
ms
tPFC-ON
PFC Disable Debounce Time to Enable PFC
PFC status from off to on
—
150
—
μs
VFB<VG
2
2.5
3
ms
tSTARTER-PWM Start Timer (Time-Out Timer)
PWM Output Section
VCLAMP
PWM Gate Output Clamping Voltage
VCC=25V
16
17.5
19
V
VOL
PWM Gate Output Voltage Low
VCC=15V, IO=100mA
—
—
1.5
V
VOH
PWM Gate Output Voltage High
VCC=15V, IO=100mA
8
—
—
V
tR
PWM Gate Output Rising Time
CL=3nF, VCC=12V,
20~80%
—
80
110
ns
tF
PWM Gate Output Falling Time
CL=3nF, VCC=12V,
20~80%
—
40
70
ns
ns
Current Sense Section
tPD
Delay to Output
VLIMIT
The Limit Voltage on CSPWM Pin for Over
Power Compensation
VSLOPE
Slope Compensation(note)
tON-BNK
Leading-Edge Blanking Time
VCS-FLOATING
CSPWM Pin Floating VCSPWM Clamped High
Voltage
tCS-H
The Delay Time Once CS Pin Floating
Rev. 1.00
—
150
200
IDET<75µA, Ta=25°C
—
0.82
0.85
0.88
V
IDET=550µA, Ta=25°C
0.37
0.4
0.43
V
tON=45µs
—
0.3
—
V
tON=0µs
—
0
—
V
—
300
—
ns
CSPWM pin floating
—
3.75
—
V
CSPWM pin floating
—
150
—
μs
—
5
July 13, 2015
HT7L5821
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
RT Pin Over-Temperature Protection Section
TOTP
Internal Threshold Temperature for OTP(note)
—
125
140
155
°C
IRT
Internal Source Current of RT Pin
—
96
107
118
μA
VRT-LATCH
Latch-Mode Triggering Voltage
—
0.95
1
1.05
V
—
—
1.2
—
V
—
0.45
0.5
0.55
V
VRT-RE-LATCH Latch-Mode Release Voltage
LEVEL
Threshold Voltage for Two-level Debounce
Time
tRT-OTP-H
Debounce Time for OTP
tRT-OTP-L
Debounce Time for Externally Triggering
VRT-OTP-
—
—
10
—
ms
70
100
130
μs
—
—
150
—
μΩ
—
VRT <VRT-OTP-LEVEL
PFC Stage
Voltage Error Amplifier Section
Gm
Transconductance(note)
VREF
Feedback Comparator Reference Voltage
2.465
2.5
2.535
V
SEL open
2.65
2.70
2.75
V
SEL ground
2.575
2.625
2.675
V
VINV-OVP
Over Voltage Protection for INV Input
VINV-UVP
Under-Voltage Protection for INV Input
—
0.25
0.35
0.45
V
tINV-UVP
Under-Voltage Protection Debounce Time
—
50
70
90
μs
VINV-BO
PWM and PFC Off Threshold for Brownout
Protection
—
1.15
1.2
1.25
V
VCOMP-BO
Limited Voltage on COMP Pin for Brownout
Protection
—
—
1.6
—
V
VCOMP
Comparator Output High Voltage
—
5.5
—
6.5
V
VOZ
Zero Duty Cycle Voltage on COMP Pin
—
0.65
0.7
0.75
V
ICOMP
Comparator Output Source Current
VINV=2.3V, VCOMP=1.5V
—
30
—
μA
Comparator Output Sink Current
VINV=2.7V, VCOMP=5V
—
30
—
μA
VCOMP=5V
—
0.8
—
V
PFC Current Sense Section
VCSPFC
Threshold Voltage for Peak Current
Cycle-by-Cycle Limit
tPD
Propagation Delay
—
—
110
200
ns
tLEB
Leading Edge Blanking Time
—
—
200
—
ns
V
PFC Zero Current Detection Section
VZCD
Input Threshold Voltage Rise Edge
VZCD increasing
—
1.4
—
VZCD-HYST
Threshold Voltage Hysteresis
VZCD decreasing
—
0.7
—
V
VZCD-HIGH
Upper Clamp Voltage
IZCD=1mA
—
5.7
—
V
VZCD-LOW
Lower Clamp Voltage
IZCD=-1mA
—
-0.4
—
V
tDELAY
Maximum Delay from ZCD to Output Turn-On VCOMP=5V, fS=60kHz
100
—
200
ns
—
190
—
μs
VCOMP=5V
—
1
—
μs
tRESTART-PFC Restart Time
tINHIB
—
Inhibit Time
(Maximum Switching Frequency Limit)
PFC Output Section
VZ
PFC Gate Output Clamping Voltage
VCC=25V
16
17.5
19
V
VOL
PFC Gate Output Voltage Low
VCC=15V, IO=100mA
—
—
1.5
V
VOH
PFC Gate Output Voltage High
VCC=15V, IO=100mA
8
—
—
V
tR
PFC Gate Output Rising Time
CL=3nF, VCC=12V,
20~80%
—
80
110
ns
tF
PFC Gate Output Falling Time
CL=3nF, VCC=12V,
20~80%
—
40
70
ns
Note: Guaranteed by design.
Rev. 1.00
6
July 13, 2015
HT7L5821
Typical Performance Characteristics
10.4
VDD-PWM-OFF(V)
VDD-ON(V)
16.6
16.4
16.2
16
10.2
10
9.8
15.8
-40 -25 -10 5
9.6
20 35 50 65 80 95 110 125
-40 -25 -10
5
20
Temp(℃)
28
8.2
27.8
VDD-OVP(V)
VDD-OFF(V)
8.3
8.1
8
80
95
110 125
27.6
27.4
-40 -25 -10
5
20
35
50
65
80
95
27.2
110 125
-40
-25
-10
5
20
Temp(℃)
35
50
65
80
95
110 125
Temp(℃)
Turn-Off Threshold Voltage
VCC Over-Voltage Protection Threshold
40
2.6
30
2.55
VREF(V)
IDD-ST(uA)
65
PWM Off Threshold Voltage
7.9
20
2.5
2.45
10
2.4
0
-40 -25 -10
5
20
35
50
65
80
95
-40 -25 -10
110 125
5
20
35
50
65
80
95
110 125
Temp(℃)
Temp(℃)
Startup Current
PFC Output Feedback Reference Voltage
0.9
17.5
17
0.85
VCSPFC(V)
VZ(V)
50
Temp(℃)
Turn-On Threshold Voltage
16.5
16
0.8
0.75
15.5
15
0.7
-40 -25
-10
5
20
35
50
65
80
95
110 125
-40 -25
Temp(℃)
-10
5
20
35
50
65
80
95
110 125
Temp(℃)
PFC Gate Output Clamping Voltage
Rev. 1.00
35
PFC Peak Current Limit Voltage
7
July 13, 2015
HT7L5821
18
2.2
2.1
17
16.5
VN(V)
VCLAMP(V)
17.5
16
15.5
2
1.9
15
14.5
-40
-25
-10
5
20
35
50
65
80
95
1.8
110 125
-40
-25
-10
5
20
Temp(℃)
1.4
9.5
1.3
9
1.2
1.1
65
80
95
110 125
8.5
8
1
7.5
-40
-25
-10
5
20
35
50
65
80
95
110 125
-40
-25
-10
5
20
Temp(℃)
35
50
65
80
95
110 125
Temp(℃)
Beginning of Green-Off Mode at VFB
PWM Minimum Off-Time for VFB > VN
38
-0.2
36
-0.3
VDET-LOW(V)
tOFF-MIN(us)
50
Beginning of Green-On Mode at VFB
tOFF-MIN(us)
VG(V)
PWM Gate Output Clamping Voltage
34
32
-0.4
-0.5
-0.6
30
-40
-25
-10
5
20
35
50
65
80
95
-40
110 125
-25
-10
5
20
PWM Minimum Off-Time for VFB=VG
50
65
80
95
110 125
Lower Clamp Voltage of DET Pin
120
2.5
115
IRT(uA)
2.55
2.45
110
105
2.4
100
2.35
-40
-25
-10
5
20
35
50
65
80
95
-40
110 125
-25
-10
5
20
35
50
65
80
95
110 125
Temp(℃)
Temp(℃)
Reference Voltage for Output Over-Voltage
Protection of DET Pin
Rev. 1.00
35
Temp(℃)
Temp(℃)
VDET-OVP(V)
35
Temp(℃)
Internal Source Current of RT Pin
8
July 13, 2015
HT7L5821
VRT-LATCH(V)
1.15
1.1
1.05
1
0.95
-40
-25
-10
5
20
35
50
65
80
95
110 125
Temp(℃)
Over Temperature Protection Threshold Voltage
of RT Pin
Functional Description
PFC Stage
internal ZCD comparator is triggered and a PFC
gate signal is generated. If no triggering signal is
detected on the ZCD pin, the device will generate a
restart signal 190μs after the last PFC gate signal. The
maximum and minimum voltage of the ZCD pin is
internally clamped to 5.7V and 0V respectively
Error Amplifier
The PFC error amplifier is used for regulating the
PFC output voltage. The error amplifier input is the
INV pin and it is connected to a resistor divider from
the PFC output. The error amplifier input voltage is
compared with an internal reference voltage of 2.5V
to make the error amplifier source or sink current
to charge and discharge its output capacitor. The
capacitor voltage will determine the on-time of the
PFC controller to regulate the output voltage. The
sink and source capability of the error amplifier is
approximately 30uA during normal operation and the
typical transconductance value is 150μs.
SEL Pin
A built-in low voltage switch can be turned on or off
according to VIN voltage level. The drain pin of this
internal switch is connected to the SEL pin.
Dynamic Response
The PFC dynamic response is very slow because of
the PFC voltage loop low frequency bandwidth. The
device provides an enhanced dynamic response for
the PFC loop by detecting the feedback voltage on
the INV pin. Whenever the INV voltage is lower than
the reference value 2.3V, it will increase the error
amplifier transconductance and in turn increase the
PFC duty cycle directly. This change in duty cycle
bypasses the slow change of the COMP voltage and
thus results in a fast dynamic response for the PFC
stage.
Brown-in/out Protection – VIN Pin
The device features brown-in/out protection using
AC voltage detection. The VIN pin is used to detect
the AC input voltage using a resistor divider. As the
AC voltage drops and VVIN voltage drops below 0.9V
for 100ms, the UVP protection is activated and the
COMP pin voltage is clamped to around 1.6V. Since
a lower COMP voltage results in a reduced PFC ontime, the energy concentration is limited and therefore
the PFC output voltage decreases. When the INV pin
is lower than 1.2V, the device turns off all PFC and
PWM switching operations and the VCC voltage enters
the hiccup mode. Not until the VVIN voltage increases
beyond 1.25V (typical) and VCC reaches its turn-on
voltage again will the PWM and PFC gate signals be
generated.
ZCD Pin
The device performs zero current detection by using
an auxiliary winding on the PFC boost inductor.
During normal operation, when the PFC MOS is
switched off, the stored energy in the PFC boost
inductor will release its energy to the output. The
voltage on the ZCD pin decreases as the stored energy
in the PFC boost inductor is released to the output.
When the ZCD pin voltage is lower than 0.7V, the
Peak Current Limiting – CSPFC Pin
The CSPFC pin is used to sense the PFC switch
current. During normal PFC operation, the voltage
on the CSPFC pin is compared with a threshold
voltage of 0.8V using the internal comparator.
When the CSPFC pin voltage is greater than the
threshold voltage, the PFC switch will be turned off
immediately. The current-sense resistor is adjustable
to determine the PFC switch peak current.
Rev. 1.00
9
July 13, 2015
HT7L5821
winding VAUX decreases as well. Then, the internal
DET comparator detects the valley voltage of the
switching waveform to achieve valley voltage
switching. This ensures QR operation, minimises
switching losses and reduces EMI. The maximum
and minimum voltage of the DET pin is internally
clamped to 5.7V and -0.4V respectively.
Output Voltage OVP and UVP – INV Pin
Over-voltage and under-voltage protection functions
are integrated into the device for the PFC stage.
Both are detected and determined using the INV pin
voltage. The OVP or UVP circuit is activated to stop
PFC switching operations immediately when the INV
pin voltage is greater than 2.65V or less than 0.35V.
In addition, the de-bounce time of the OVP and UVP
is set to about 70μs to avoid overshoot or abnormal
conditions.
Green-Mode and PFC On/Off Control – FB Pin
A Green Mode mechanism is adopted to reduce
switching losses in the power system�������������
������������
under conditions of light load. The device uses a linear off-time
modulation to decrease����������������������������
���������������������������
switching frequency according to the FB pin voltage. The following figure shows
the FB versus t OFF-MIN characteristic curve. As FB
pin Voltage is lower than VN (2.1V), the tOFF-MIN time
increases with lower FB������������������������������
pin voltage������������������
. The valley voltage detection signal does not activate until the tOFF-MIN
time finishes which extends valley voltage switching
during DCM operation and reduces switching losses
to obtain higher conversion efficiencies. In addition,
in order to reduce the standby power under conditions
of no load or very light-load, the FB pin voltage is
also used to control the PFC on/off operation. As the
FB voltage falls below the VCTL-PFC-OFF threshold voltage the controller will stop PFC switching until the
FB pin voltage returns to VCTL-PFC-ON.
QR Flyback Stage
Startup Current – HVS Pin
For startup purposes the HVS pin is connected to the
AC line input through a resistor. Using an integrated
high-voltage startup circuit, the device provides a
high current to charge the external VCC capacitor to
reduce the controller’s startup time. To reduce power
consumption, when the VCC voltage exceeds the
turn-on voltage and enters normal operation, this high
voltage startup circuit will be switched off to avoid
power losses due to power consumption in the startup
resistor.
Under-Voltage Lockout (UVLO) – VCC Pin
The turn-on, PWM-off and turn-off thresholds are
fixed internally at 16V/10V/8V, respectively. During
startup, the hold-up capacitor (VCC cap.) is charged by
the HV startup current until the VCC voltage reaches
the turn-on voltage. The hold-up capacitor continues
to supply VCC until energy can be delivered from the
auxiliary winding. During this startup process, VCC
must not drop below VCC PWM-OFF.������������������
�����������������
This UVLO hysteresis window ensures that hold-up capacitor is suitable
for supplying VCC during startup. The following figure
shows the VCC waveform in the hiccup mode.
tOFF-MIN(s)
2.5ms
//
36us
PFC-ON
PFC-OFF
VCTL-PFC-OFF
VCC-ON(16V)
VCTL-PFC-ON
8us
VCC-PWM-OFF(10V)
VG
(1.2V)
VCC-OFF(8V)
VN
(2.1V)
FB(V)
FB vs Toff-min Characteristic Curve
High/Low Line Over-Power Compensation –
DET Pin
The power delivered by a flyback power supply is
proportional to the square of the peak current during
QR control. However, due to the inherent propagation
delay of the logic, the actual peak current is higher for
a high input voltage than for a low input voltage. This
results in a significant�����������������������������
����������������������������
difference between the maximum output power delivered by the power supply.
To compensate for this variation for a universal input
range,�����������������������������������������������
����������������������������������������������
the DET pin produces an offset voltage to compensate the threshold voltage of the peak current limit.
PWM Pulse
VCC during Hiccup Mode Operation
Valley Detection – DET Pin
The DET pin is connected to an auxiliary winding
of the transformer using divider resistors. During
the PWM off time, when the transformer inductor
current discharges to zero, the transformer inductor
and parasitic capacitors of the PWM switch start
to resonate concurrently. As the drain voltage on
the PWM switch falls, the voltage on the auxiliary
Rev. 1.00
10
July 13, 2015
HT7L5821
This offset voltage is generated by sensing the current
drawn from the DET pin when the power switch turns
on. The following figure shows the IDET versus VLIMIT
characteristic curve.
DET Pin Over-Voltage Protection – DET OVP
An output over-voltage protection is implemented by
sensing the auxiliary winding voltage on the DET pin.
The QR OVP works by sampling the plateau voltage
on the DET pin after the PWM switch-off sequence.
A 4us internal blanking time guarantees a clean plateau provided that the leakage inductance ringing has
been fully damped. If the sampled plateau voltage
exceeds the OVP trip level of 2.5V and lasts for tDETOVP, the device will enter the latch mode until the AC
power is removed. The protection voltage level can be
determined by the ratio of the external resistor divider
RDET1 and RDET2, as shown in the following figure. The
flat voltage on the DET pin can be expressed by the
following equation:
900
VLIMIT(mV)
800
700
600
500
400
300
0
100
200
300
400
IDET(uA)
500
VDET =(NA/NS)×VO×
600
IDET vs VLIMIT Characteristic Curve
Auxiliary
winding
Leading Edge Blanking – LEB
Each time the PFC or PWM switches are turned on, a
voltage spike occurs on the current sense resistor. To
avoid faulty triggering, a leading-edge blanking time
is built into the device. During the blanking period the
current limit comparator is disabled and cannot switch
off the gate driver.
RDET1
RDET2
10
DET
Plateau
Sampling
2.5V
VCC Pin Over-Voltage Protection – VCC OVP
The VCC OVP function is used to prevent device
damage. If the V CC voltage is higher than V CC-OVP
and lasts for a time tVCC-OVP, the controller stops all
switching operations and enters the latch mode until
the AC plug is removed. Latched
tDET-OVP
DET Over-Voltage Protection
Output Open-Loop and Over-Load Protection
To protect the circuit from being damaged during
conditions of output open-loop or overload, the
device includes an OLP function. Under such fault
conditions, the output voltage is decreased and the
sink current of the photo-coupler is reduced. This will
force the FB pin voltage to increase using an internal
bias. When the FB pin voltage ramps up to 4.2V for
50ms the OLP protection is activated to turn off the
power switch and stop all switching operations.
Adjustable Over-Temperature Protection and
External Latch – RT Pin
The RT pin is used to achieve over-temperature
protection using an NTC resistor and provides an
external latch for additional protection. Typically,
since the external latch is usually used to protect the
power system from abnormal conditions it needs a
fast reaction speed or a short reaction time. Therefore,
the protection debounce time of the external latch is
set to around 100us once the RT pin voltage is lower
than 0.5V. For over temperature protection, since the
temperature could not change rapidly, the protection
debounce time should not be activated quickly. The
protection debounce time for the OTP is set to around
10ms. In addition, to avoid improper latch triggering
due to a lightning test, the RT pin triggering voltage
of the OTP is set to 1.0V, which is higher than the
external latch triggering voltage of 0.5V.
Rev. 1.00
RDET2
RDET1+RDET2
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HT7L5821
Package Information
Note that the package information provided here is for consultation purposes only. As this information may be
updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package
information.
Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be
transferred to the relevant website page.
• Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications)
• Packing Meterials Information
• Carton information
Rev. 1.00
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HT7L5821
16-pin NSOP (150mil) Outline Dimensions
Symbol
Dimensions in inch
Min.
Nom.
Max.
—
A
—
0.236 BSC
B
—
0.154 BSC
—
C
0.012
—
0.020
C'
—
0.390 BSC
—
0.069
D
—
—
E
—
0.050 BSC
—
F
0.004
—
0.010
G
0.016
—
0.050
H
0.004
—
0.010
α
0°
―
8°
Symbol
Rev. 1.00
Dimensions in mm
Min.
Nom.
Max.
A
—
6.000 BSC
—
B
—
3.900 BSC
—
0.51
C
0.31
—
C'
—
9.900 BSC
—
D
—
—
1.75
E
—
1.270 BSC
—
F
0.10
—
0.25
G
0.40
—
1.27
H
0.10
—
0.25
α
0°
―
8°
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HT7L5821
Copyright© 2015 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time
of publication. However, Holtek assumes no responsibility arising from the use of
the specifications described. The applications mentioned herein are used solely
for the purpose of illustration and Holtek makes no warranty or representation that
such applications will be suitable without further modification, nor recommends
the use of its products for application that may present a risk to human life due to
malfunction or otherwise. Holtek's products are not authorized for use as critical
components in life support devices or systems. Holtek reserves the right to alter
its products without prior notification. For the most up-to-date information, please
visit our web site at http://www.holtek.com.tw.
Rev. 1.00
14
July 13, 2015