CI-300004-E-V12-16LX_uDMAC_Problem F2MC-16LX FAMILY 16-BIT MICROCONTROLLERS MB90340 Series MB90350 Series FUNCTIONAL LIMITATION 16LX µDMAC PROBLEM Revision History Date 29 Sep 2005 07 Nov 2005 13 July 2006 Issue V1.0 Initial Version V1.1 re-check, disclaimer added, header/footer modified V1.2 , HWe: typos (font) corrected This document contains 12 pages. Abbreviations: MCU Microcontroller µDMAC Micro DMA Controller CAN Controller Area Network CI-300004-E-V12-16LX_uDMAC_Problem -2- Contents REVISION HISTORY ............................................................................................................ 2 CONTENTS .......................................................................................................................... 3 1 OVERVIEW...................................................................................................................... 5 2 AFFECTED DEVICES...................................................................................................... 5 3 OPERATION OVERVIEW OF CPU, "DMAC AND CAN ................................................. 6 3.1 µDMAC ................................................................................................................... 7 3.2 CAN ........................................................................................................................ 7 3.3 Bus Repeater .......................................................................................................... 7 4 MECHANISM OF THE "DMAC PROBLEM .................................................................... 9 5 MEASURES AGAINST THE "DMAC PROBLEM ......................................................... 11 5.1 Corrective Action to Current Products ................................................................... 11 5.2 Permanent Measures ............................................................................................ 11 -3- CI-300004-E-V12-16LX_uDMAC_Problem Fujitsu does not bear any warranty in the case this handling note is not fully observed. CI-300004-E-V12-16LX_uDMAC_Problem -4- 1 Overview In contrast to ealier evaluation results, the following basic phenomena has been revealed: The µDMAC problem is defined as a malfunction that is caused by the garbling of the DMA transfer source or destination address or transfer data. This type of malfunction may be caused when one of the F2MC-16LX family devices listed in Chapter 2 “Affected Devices” is used to perform an access to the CAN message buffer RAM concurrently with a data transfer using the µDMAC. An example of causing a malfunction is shown below: Example: • UART transmission is performed by transferring data to the transmission data register by using the µDMAC while CAN operation is enabled. This error symptom was confirmed by our operation verification. Note that this error symptom does not occur if one of the following is met: • The µDMAC is not used. • CAN is not used. • The µDMAC is not used during CAN message buffer RAM access. 2 Affected Devices The µDMAC/CAN problem occurs in devices with a µDMAC and a CAN Interface. The following devices are affected: • MB90340 Series: MB90F342A/AS/CA/CAS, MB90F345A/AS/CA/CAS, MB90F346A/AS/CA/CAS,MB90F347A/AS/CA/CAS, MB90F347D/DS, MB90F349A/AS/CA/CAS, MB90341A/AS/CA/CAS, MB90342A/AS/CA/CAS, MB90346A/AS/CA/CAS, MB90347A/AS/CA/CAS, MB90348A/AS/CA/CAS, MB90349A/AS/CA/CAS, MB90V340A-101/102/103/104, MB90V340/S, MB90F038S • MB90350 Series: MB90F351/S, MB90F352/S, MB90F351A/AS/TA/TAS, MB90F352A/AS/TA/TAS, MB90F356A/AS/TA/TAS, MB90F357A/AS/TA/TAS, MB90351A/AS/TA/TAS, MB90352A/AS/TA/TAS, MB90356A/AS/TA/TAS, MB90357A/AS/TA/TAS -5- CI-300004-E-V12-16LX_uDMAC_Problem 3 Operation Overview of CPU, µDMAC and CAN The symptoms of this problem involve the CPU, µDMAC and CAN operations. Figure 1 is a block diagram of a F2MC-16LX family CPU and its peripherals. Transfer request signal (DRQn) µDMAC control circuit (µDMAC_RAM) Bus request signal (HRQU) Address latch and data read/write signals (for a case other than DMA transfer) Bus release signal (HAKU) Address latch and data read/w rite signals (at DMA transfer) CPU Bus repeater Resource bus B CPU operating clock signal Peripheral clock signal Peripheral resource Resource bus operating clock signal Resource bus C CAN control circuit CAN_RAM CAN_RAM access status signal (FREEZ E) Clock circuit control CAN_RAM w ait signal to CPU (RFRQ) CPU wait control circuit FREEZ E: Signal that indicates that the CAN controller is in access to CAN_RAM DRQn: Transfer request signal issued from a peripheral resource to µDMAC RFRQ: HRQU: Bus request signal that µDMAC issues to the CPU upon receipt of a transfer request HAKU: Bus release signal issued by the CPU upon receipt of a bus request from µDMAC Signal that makes a CPU request to access CAN_RAM wait w hen the request is issued while the CAN controller is in access to CAN_RAM Figure 1. Block diagram of F2MC-16LX CPU peripherals CI-300004-E-V12-16LX_uDMAC_Problem -6- 3.1 µDMAC The µDMAC has the function to transfer data directly (DMA transfer) between peripheral resources and memory without the intervention of the CPU. The DMA transfer procedure is explained below. A peripheral resource outputs a transfer request signal (DRQn) to the µDMAC. Upon receipt of the signal, the µDMAC outputs a bus request signal (HRQU) to the CPU. The CPU returns a bus release signal (HAKU) to the µDMAC to release the bus after it finishes the instruction in execution. Upon receipt of the bus release signal (HAKU), the µDMAC drives the bus. The bus that the µDMAC drives on behalf of the CPU is resource bus B including the bus control signals. The µDMAC operates with the peripheral clock. 3.2 CAN The CAN macro includes a message buffer memory (CAN_RAM) connected by a dedicated bus, so during CAN operation, the CAN occasionally accesses the CAN_RAM. When the CPU issues an access request to CAN_RAM during access between CAN and CAN_RAM, the CPU access must wait until the CAN access has been completed because the CAN has higher priority for accessing the CAN_RAM. The procedure is as follows: The CPU issues an access request to CAN_RAM during access between CAN and CAN_RAM A CAN_RAM wait signal (RFRQ) is output to the CPU from the CPU wait control circuit to notify the clock control circuit that the CAN is accessing the CAN_RAM. The clock control circuit stops the CPU operating clock and bus operating clock signals. Because the clock signals for the peripheral resources are not stopped even while the CAN_RAM wait signal (RFRQ) is output to the CPU, only the CPU and bus are made to wait but the peripheral resources including CAN keep operating. 3.3 Bus Repeater To be able to distribute the bus load, the internal buses consist of resource bus B directly connected to the CPU, µDMAC and CAN, and resource bus C connected to other peripheral resources. The role of the bus repeater is to determine the type of bus cycle, address or data and control the signal transfer direction between resource buses B and C based on the bus control signal. The bus repeater operates with the resource bus operating clock. -7- CI-300004-E-V12-16LX_uDMAC_Problem Figure 2 shows an example of the µDMAC control circuit reading data from a peripheral resource. µDMAC control circuit (uDMAC_RAM) Resource bus B Bus repeater Resource bus C Peripheral resource (1) Output of address (2) Output of data Figure 2 Example of the µDMAC control circuit reading data from a peripheral resource CI-300004-E-V12-16LX_uDMAC_Problem -8- 4 Mechanism of the µDMAC Problem Figure 3 shows the timing diagram of the µDMAC problem. When the µDMAC issues a bus request (HRQU) while CAN is operating, bus control is transferred from the CPU to the µDMAC ((3)). If the CAN_RAM select signal is active under this condition, the bus repeater malfunctions. This error mechanism is shown below: (1) While a µDMAC activation cause occurs during CAN operation and the µDMAC outputs a bus request (HRQU), the CPU accesses the CAN_RAM. When the CPU accesses the CAN_RAM, the CAN_RAM select signal is set to active to latch the CAN_RAM address. (2) The CAN_RAM select signal is kept active even after the CPU finishes access to CAN_RAM. Even after the CAN_RAM address has been latched, the CAN_RAM area signal is kept active until the next address is output. (3) The bus release signal (HAKU) is set to active, so the bus control is transferred from the CPU to the µDMAC. After instruction execution is finished, the CPU sets the bus release signal (HAKU) to active to transfer the bus right to the µDMAC. The bus control signal is then output by the µDMAC. (4) The CPU wait control circuit misrecognizes that the CAN_RAM is being accessed by the CPU and outputs a bus wait signal (RFRQ). When the CAN_RAM area signal is still active and the CAN starts accessing the CAN_RAM, the CPU wait control circuit misrecognizes that CAN_RAM is being accessed by the CPU and outputs a bus wait signal. (5) The resource bus B and C operating clock signals are stopped. The CAN_RAM bus wait signal (RFRQ) to the CPU stops the CPU operating clock signal and resource bus B and C operating clock signals but leaves the peripheral resource operating clock signals active. (6) When a bus control signal is supplied from the µDMAC while no clock signal is supplied to the bus repeater, the bus repeater cannot operate normally and an address or data error occurs, resulting in a malfunction. The bus control signal is not stopped because the µDMAC, which is the supply source of the signal, operates with the peripheral clock. When the bus repeater receives the bus control signal while its operating clock signal is not supplied, data transfer between resource buses B and C does not work normally. For this reason, address cycle/data cycle information on resource buses B and C is corrupted. This leads to a malfunction. -9- CI-300004-E-V12-16LX_uDMAC_Problem P er i p h er a l r e so u r c e o p er at in g c l o ck s i g n a l B P er i p h er a l r e so u r c e o p e r at in g c lo ck s i g n a l A ( 5 ) T h e re s o u rc e b u s o p er at i n g cl o ck s i g n a ls a re st o p p e d . R e s o u r c e b u s o p er at in g c l o ck s i g n a l B R e s o u r c e b u s o p er at in g c lo ck s i g n a l A A d d r e s s l at c h sign a l RE A D sign a l W RIT E s i g n a l B us- r igh t r e l ea s e s i g n a l H RQ U O u t p ut f ro m CP U ( R B A E ,, R B R D , R B W R) CP U CA N B us- r igh t r e l ea s e s i g n a l H A KU O u t p ut f ro m u D M A C ( R B A E , R B R D , R B W R) C A N _ R A M d a ta C A N _ R A M a d d re s s R e so ur c e bus C C A N _ R A M a d d re s s P e r ip h e r al re s o u r ce ( 6 ) A d at a t ra n sf e r c a u s e s a c o n fl i ct b et w e en r e s o u rc e b u s s e s B a n d C , d e s t ro y in g t h e a d d r e s s an d da t a . ( 3 ) B u s r i g h t i s r el e a s e d t o uD M A C . R e so ur c e bus B uD M A C A d d re ss 1 ( 2 ) A ft er t h e CA N _ RA M a d d r e s s is o ut p ut , t h e C A N _ RA M ar ea s i g n a l is k ep t o ut p ut u n t i l n ex t a d d r e s s is o ut p ut . A d d r e ss 1 C A N _ R AM a r e a s ig n a l B us w a it sign a l RFRQ ( 4 ) T h e CP U w a it co n t ro l c ir c u it m i s r e co g n iz e s t h at C A N _ R A M i s b e i n g a c c e s s e d by t h e CP U a n d o ut p ut s a b u s w a i t s i g n a l . Figure 3 Timing diagram of the µDMAC problem CI-300004-E-V12-16LX_uDMAC_Problem - 10 - 5 Measures against the µDMAC Problem 5.1 Corrective Action to Current Products Use the applicable products listed in Chapter2 “Affected Devices” under one of the following conditions: 5.2 • Condition 1: Do not use the µDMAC. • Condition 2: Do not use CAN operation if the µDMAC is used. Permanent Measures The cause of this error is a logical problem in the address decode circuit used when CAN accesses CAN_RAM, and accordingly the CAN_RAM area signal is left active even after the CPU finishes accessing CAN_RAM. For this reason, as permanent measures, all error applicable products will sequentially be subjected to an engineering change. The engineering change is explained as follows: Engineering change: The CAN_RAM area signal (RFRQ) will be set to inactive after the CAN_RAM address is output. ((2) in Figure 4) Figure 4 shows the timing chart after the measures are taken. After the above engineering change, the bus wait signal (RFRQ) is also set to inactive when the CPU finishes accessing CAN_RAM. Because the resource bus operating clock signal is not stopped, the bus repeater operates normally. The redesign schedules and the new part numbers for the affected products will be announced in a separate document. - 11 - CI-300004-E-V12-16LX_uDMAC_Problem P er i p h er a l r e so u r c e o p e r at in g c lo ck s i g n a l B P er i p h er a l r e so u r c e o p e r at in g c lo ck s i g n a l A R e s o u r c e b u s o p er at in g c lo c k sign a l B R e s o u r c e b u s o p er at in g c lo ck s i g n a l A A d d r e s s l at c h sign a l READ sign a l W RIT E s i g n a l B us- r igh t r e que st sign a l HRQU O u t p ut f ro m CP U ( R B A E ,, R B R D , R B W R) CP U CA N B us- r igh t r e lea s e s ig n a l H A KU O u t p ut f ro m u D M A C ( R B A E , R B R D , R B W R) B u s r i g h t i s r e le a s e d t o u D M A C C A N _ R A M d a ta R e so urc e bus B C A N _ R A M a d d re s s R e so urc e bus C C A N _ R A M a d d re s s uD M A C D a ta c an b e t r an s f er re d n o rm a l ly b et w ee n r e so u r c e bu sse s B a n d C . A d d r e ss 1 A d d r e ss 1 (2) P e r ip h e r al re s o u r ce A d d r e ss 2 R E A D d a ta W R I T E d a ta A d d r e ss 2 A ft er t h e C A N _ RA M a d d r e s s i s o ut p ut , t h e C A N _ R A M ar e a s i g n a l i s set t o i n a ct i v e . C A N _ R A M ar e a sign a l B us w a it sign a l RFRQ T h e b u s w a i t s i g n a l i s k e p t in a ct iv e b e c a u s e t h e C P U h a s f i n i sh e d a cc e s s i n g C A N _ RA M . Figure 4 Timing chart after engineering change CI-300004-E-V12-16LX_uDMAC_Problem - 12 -