hm90420_5-cm44-10113-1e.pdf

FUJITSU SEMICONDUCTOR
CM44-10113-1E
CONTROLLER MANUAL
2
F MC-16LX
16-BIT MICROCONTROLLER
MB90420G/425G Series
HARDWARE MANUAL
2
F MC-16LX
16-BIT MICROCONTROLLER
MB90420G/425G Series
HARDWARE MANUAL
FUJITSU LIMITED
PREFACE
■ Objectives and Intended Reader
The MB90420G/425G series of products has been developed as a general-purpose product of
the F2MC-16LX series of 16-bit one-chip microcontrollers, which can support applicationspecific IC (ASIC).
This manual, intended for engineers who develop and design products using MB90420G/425Gseries microcontrollers, describes their features, and explains the operation of the MB90420G/
425G series of products.
Be sure to read this manual before using this product.
■ Trademarks
F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
Embedded Algorithm is a trademark of Advanced Micro Devices, Inc.
Other system names and product names appearing in this manual are trademarks of their
respective companies or organizations.
The symbols TM and ® are sometimes omitted in the text.
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■ Structure of This Manual
This manual has 26 chapters and an appendix:
CHAPTER 1 "OUTLINE"
This Chapter describes features and provides the basic specification of the MB90420G/425G
series.
CHAPTER 2 "CPU"
This Chapter describes the CPU of the F2MC-16LX.
CHAPTER 3 "INTERRUPTS"
This chapter describes the relationships between interrupts and the extended intelligent I/O
service (EI2OS).
CHAPTER 4 "RESET"
This chapter describes the reset operation.
CHAPTER 5 "CLOCK"
This chapter describes the clock of the MB90420G/425G series.
CHAPTER 6 "LOW-POWER CONSUMPTION MODE"
This chapter describes the low-power consumption mode.
CHAPTER 7 "MODE SETTINGS"
This chapter describes the operation mode and memory access mode.
CHAPTER 8 "I/O PORTS"
This chapter describes the functions and operation of the I/O ports.
CHAPTER 9 "WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)"
This chapter describes the functions and operation of the watchdog timer, timebase timer,
and watch timer (used as sub-clock).
CHAPTER 10 "INPUT CAPTURE"
This chapter describes the input capture operation.
CHAPTER 11 "16-BIT RELOAD TIMER"
This chapter describes the functions and operations of the 16-bit reload timer.
CHAPTER 12 "REAL-TIME WATCH TIMER"
This chapter describes the functions and operations of the real-time watch timer.
CHAPTER 13 "PPG TIMER"
This chapter describes the PPG timer.
CHAPTER 14 "DELAY INTERRUPT GENERATION MODULE"
This chapter describes the functions and operations of the delay interrupt generation
module.
CHAPTER 15 "DTP/EXTERNAL INTERRUPT CIRCUIT"
This chapter describes the functions and operations of the DTP/external interrupt circuit.
CHAPTER 16 "8/10-BIT A/D CONVERTER"
This chapter describes the functions and operations of the 8/10-bit A/D converter.
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CHAPTER 17 "UART"
This chapter describes the functions and operations of UART.
CHAPTER 18 "CAN CONTROLLER"
This chapter describes an overview of the CAN controller and its functions.
CHAPTER 19 "LCD CONTROLLER/DRIVER"
This chapter describes the functions and operations of the LCD controller/driver.
CHAPTER 20 "LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT"
This chapter describes the functions and operations of the low-voltage/CPU operation
detection reset circuit.
CHAPTER 21 "STEPPING MOTOR CONTROLLER"
This chapter describes the functions and operation of the stepping motor controller.
CHAPTER 22 "SOUND GENERATOR"
This chapter describes the functions and operation of the sound generator.
CHAPTER 23 "ADDRESS MATCH DETECTION FUNCTION"
This chapter describes functions and operations of the address matching detection.
CHAPTER 24 "ROM MIRROR FUNCTION SELECTION MODULE"
This chapter describes the ROM mirror function selection module.
CHAPTER 25 "1M BIT FLASH MEMORY"
This chapter describe functions and operation of the 1M bit flash memory.
CHAPTER 26 "EXAMPLE OF SERIAL WRITE CONNECTION"
This chapter shows an example of a serial programming connection using the AF220/AF210/
AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer
Corporation.
"APPENDIX"
The Appendix provides the I/O map and describes the instructions of the F2MC-16LX.
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The contents of this document are subject to change without notice. Customers are advised to consult
with FUJITSU sales representatives before ordering.
The information and circuit diagrams in this document are presented as examples of semiconductor
device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is
unable to assume responsibility for infringement of any patent rights or other rights of third parties
arising from the use of this information or circuit diagrams.
The products described in this document are designed, developed and manufactured as contemplated
for general use, including without limitation, ordinary industrial use, general office use, personal use, and
household use, but are not designed, developed and manufactured as contemplated (1) for use
accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious
effect to the public, and could lead directly to death, personal injury, severe physical damage or other
loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass
transport control, medical life support system, missile launch control in weapon system), or (2) for use
requiring extremely high reliability (i.e., submersible repeater and artificial satellite).
Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages
arising in connection with above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage
or loss from such failures by incorporating safety design measures into your facility and equipment such
as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions.
If any products described in this document represent goods or technologies subject to certain
restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export of those products from Japan.
©2002 FUJITSU LIMITED Printed in Japan
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CONTENTS
CHAPTER 1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
OUTLINE ....................................................................................................... 1
Product Outline ...................................................................................................................................... 2
Features ................................................................................................................................................ 4
Block Diagram ....................................................................................................................................... 6
Diagram Showing Package Dimensions ................................................................................................ 8
Pin Assignment Diagram ..................................................................................................................... 10
Description of Pin Functions ................................................................................................................ 12
Types of Input/Output Circuits ............................................................................................................. 16
Precautions for Device Handling ......................................................................................................... 18
CHAPTER 2
CPU ............................................................................................................. 21
2.1 Outline of CPU ..................................................................................................................................... 22
2.2 Memory Space ..................................................................................................................................... 23
2.3 Memory Map ........................................................................................................................................ 25
2.4 Addressing ........................................................................................................................................... 27
2.4.1 Addressing with Linear Scheme ..................................................................................................... 28
2.4.2 Addressing with Bank Scheme ....................................................................................................... 29
2.5 Allocation of Multiple-Byte Data in the Memory ................................................................................... 31
2.6 Registers .............................................................................................................................................. 33
2.7 Dedicated Registers ............................................................................................................................ 34
2.7.1 Accumulator (A) .............................................................................................................................. 36
2.7.2 Stack Pointers (USP, SSP) ............................................................................................................ 39
2.7.3 Processor Status (PS) .................................................................................................................... 41
2.7.4 Program Counter (PC) .................................................................................................................... 45
2.7.5 Direct Page Register (DPR) ........................................................................................................... 46
2.7.6 Bank Registers (PCB, DTB, USB, SSB, ADB) ............................................................................... 47
2.8 General-Purpose Register ................................................................................................................... 48
2.9 Prefix Codes ........................................................................................................................................ 50
CHAPTER 3
INTERRUPTS .............................................................................................. 57
3.1 Outline of Interrupts ............................................................................................................................. 58
3.2 Interrupt Sources and Interrupts .......................................................................................................... 60
3.3 Interrupt Control Registers and Peripheral Functions .......................................................................... 63
3.3.1 Interrupt Control Registers (ICR00 to ICR15) ................................................................................. 65
3.3.2 Function of Interrupt Control Registers ........................................................................................... 67
3.4 Hardware Interrupts ............................................................................................................................. 70
3.4.1 Hardware Interrupt Operation ........................................................................................................ 73
3.4.2 Operation Flow for Hardware Interrupts ........................................................................................ 75
3.4.3 Procedure for Using Hardware Interrupts ....................................................................................... 76
3.4.4 Multiple Interrupts ........................................................................................................................... 77
3.4.5 Time for Handling Hardware Interrupts .......................................................................................... 79
3.5 Software Interrupts .............................................................................................................................. 81
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS) .......................................................................... 83
3.6.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ............................................................. 85
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3.6.2 Registers of the Extended intelligent I/O Service (EI2OS) Descriptor (ISD) ..................................
3.6.3 Operation of the Extended intelligent I/O Service (EI2OS) ............................................................
3.6.4 Procedure for Using the Extended Intelligent I/O Service (EI2OS) ................................................
3.6.5 Processing Time for the Extended intelligent I/O Service (EI2OS) ................................................
3.7 Exception Interrupt Because of Undefined Instruction ........................................................................
3.8 Stack Operations of Interrupt Handling ...............................................................................................
3.9 Example Program for Interrupt Handling ............................................................................................
CHAPTER 4
4.1
4.2
4.3
4.4
4.5
4.6
5.1
5.2
5.3
5.4
5.5
5.6
RESET ...................................................................................................... 103
Outline of Reset Operation ...............................................................................................................
Reset Sources and Oscillation Stabilization Wait Time ....................................................................
External Reset Pin ............................................................................................................................
Reset Operation ................................................................................................................................
Reset Source Bit ...............................................................................................................................
State of Each Pin After Reset ...........................................................................................................
CHAPTER 5
7.1
7.2
7.3
132
135
137
140
141
142
144
146
148
150
152
153
MODE SETTINGS ..................................................................................... 155
Setting the Mode ............................................................................................................................... 156
Mode pins (MD2 to MD0) .................................................................................................................. 157
Mode Data ........................................................................................................................................ 158
CHAPTER 8
I/O PORTS ................................................................................................ 161
8.1 I/O Ports ............................................................................................................................................
8.2 Assignment of Registers and Pins Shared with External Pins ..........................................................
8.3 Port 0 ................................................................................................................................................
8.3.1 Port 0 registers (PDR0, DDR0) ....................................................................................................
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118
121
123
126
129
130
LOW-POWER CONSUMPTION MODE .................................................... 131
6.1 Outline of Low-Power Consumption Mode .......................................................................................
6.2 Block Diagram of Low-Power Consumption Control Circuit ..............................................................
6.3 Low-Power Consumption Mode Control Register (LPMCR) .............................................................
6.4 CPU Intermittent Operation Mode .....................................................................................................
6.5 Standby Modes .................................................................................................................................
6.5.1 Sleep Mode ..................................................................................................................................
6.5.2 Timebase Timer Mode .................................................................................................................
6.5.3 Watch Mode .................................................................................................................................
6.5.4 Stop Mode ...................................................................................................................................
6.6 State Transition Diagram ..................................................................................................................
6.7 Pin States in Standby Mode and During Reset .................................................................................
6.8 Notes on Using the Low-Power Consumption Mode ........................................................................
CHAPTER 7
104
107
109
110
112
116
CLOCK ...................................................................................................... 117
Outline of Clock Unit .........................................................................................................................
Block Diagram of the Clock Generation Section ...............................................................................
Clock Selection Register (CKSCR) ...................................................................................................
Clock Mode .......................................................................................................................................
Oscillation stabilization wait time ......................................................................................................
Connection of Resonator and External Clock ...................................................................................
CHAPTER 6
87
90
91
92
95
96
98
162
164
165
167
8.3.2 Description of Port 0 Operation .................................................................................................... 168
8.4 Port 1 ................................................................................................................................................. 170
8.4.1 Port 1 Registers (PDR1, DDR1) ................................................................................................... 172
8.4.2 Description of Port 1 Operation .................................................................................................... 173
8.5 Port 3 ................................................................................................................................................. 175
8.5.1 Port 3 Registers (PDR3, DDR3) ................................................................................................... 177
8.5.2 Description of Port 3 Operation .................................................................................................... 178
8.6 Port 4 ................................................................................................................................................. 180
8.6.1 Port 4 Registers (PDR4, DDR4) ................................................................................................... 182
8.6.2 Description of Port 4 Operation .................................................................................................... 183
8.7 Port 5 ................................................................................................................................................. 185
8.7.1 Port 5 Registers (PDR5, DDR5) ................................................................................................... 187
8.7.2 Description of Port 5 Operation .................................................................................................... 188
8.8 Port 6 ................................................................................................................................................. 190
8.8.1 Port 6 Registers (PDR6, DDR6, ADER) ....................................................................................... 192
8.8.2 Description of Port 6 Operation .................................................................................................... 194
8.9 Port 7 ................................................................................................................................................. 196
8.9.1 Port 7 Registers (PDR7, DDR7) ................................................................................................... 198
8.9.2 Description of Port 7 Operation .................................................................................................... 199
8.10 Port 8 ................................................................................................................................................. 201
8.10.1 Port 8 Registers (PDR8, DDR8) ................................................................................................... 203
8.10.2 Description of Port 8 Operation .................................................................................................... 204
8.11 Port 9 ................................................................................................................................................. 206
8.11.1 Functions of Port 9 Registers (PDR9, DDR9) .............................................................................. 208
8.11.2 Description of Port 9 Operation .................................................................................................... 209
8.12 Example Program for I/O Port ........................................................................................................... 211
CHAPTER 9
WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER
(SUB-CLOCK)
213
9.1 Outline of Watchdog Timer/Timebase Timer/Watch Timer ................................................................ 214
9.2 Block Diagrams of Watchdog Timer/Timebase Timer/Watch Timer .................................................. 215
9.3 List of Registers for Watchdog Timer/Timebase Timer/Watch Timer ................................................ 216
9.3.1 Watchdog Timer Control Register (WDTC) .................................................................................. 217
9.3.2 Timebase Timer Control Register (TBTC) .................................................................................... 219
9.3.3 Watch Timer Control Register (WTC) ........................................................................................... 221
9.4 Operation of Watchdog Timer/Timebase Timer/Watch Timer ........................................................... 223
9.4.1 Watchdog Timer Operation .......................................................................................................... 224
9.4.2 Timebase Timer Operation ........................................................................................................... 226
9.4.3 Watch Timer Operation ................................................................................................................ 228
9.5 Notes on Using The Watchdog Timer/Timebase Timer ..................................................................... 229
9.6 Example Program for Watchdog Timer/Timebase Timer .................................................................. 231
CHAPTER 10 INPUT CAPTURE ...................................................................................... 233
10.1 Outline of Input Capture ..................................................................................................................... 234
10.2 Block Diagram of Input Capture ......................................................................................................... 235
10.3 List of Input Capture Registers .......................................................................................................... 236
10.3.1 Detailed Description of the Input Capture Registers .................................................................... 238
10.3.2 Detailed Description of 16-Bit Free-run Timer Register ................................................................ 240
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10.4 Description of Operations ................................................................................................................. 245
10.4.1 16-bit Input Capture ..................................................................................................................... 246
10.4.2 16-bit Free-run Timer Section ...................................................................................................... 248
CHAPTER 11 16-BIT RELOAD TIMER ........................................................................... 251
11.1 Overview of 16-Bit Reload Timer ......................................................................................................
11.2 Configuration of 16-Bit Reload Timer ................................................................................................
11.3 Pins of 16-Bit Reload Timer ..............................................................................................................
11.4 Registers of 16-Bit Reload Timer ......................................................................................................
11.4.1 Upper Bits of Timer Control Status Registers (TMCSR0/1H) ......................................................
11.4.2 Lower Bits of Timer Control Status Registers (TMCSR0/1L) .......................................................
11.4.3 16-Bit Timer Registers (TMR0/1) .................................................................................................
11.4.4 16-Bit Reload Registers (TMRLR0/1L, TMRLR0/1H) ..................................................................
11.5 Interrupts of 16-Bit Reload Timer ......................................................................................................
11.6 Operation of 16-Bit Reload Timer .....................................................................................................
11.6.1 Internal Clock Mode (Reload Mode) ............................................................................................
11.6.2 Internal Clock Mode (One-Shot Mode) ........................................................................................
11.6.3 Event Count Mode .......................................................................................................................
11.7 Notes on Using the 16-Bit Reload Timer ..........................................................................................
11.8 Sample Programs for the 16-Bit Reload Timer .................................................................................
252
255
257
259
260
262
264
265
266
267
269
271
273
275
276
CHAPTER 12 REAL-TIME WATCH TIMER .................................................................... 281
12.1 Overview of Real-Time Watch Timer ................................................................................................
12.2 Registers of Real-Time Watch Timer ................................................................................................
12.2.1 Real-Time Watch Timer Control Register ....................................................................................
12.2.2 Sub-Second Data Register ..........................................................................................................
12.2.3 Second/Minute/Hour Data Registers ...........................................................................................
282
283
284
286
287
CHAPTER 13 PPG TIMER ............................................................................................... 289
13.1 Overview of PPG Timer ....................................................................................................................
13.2 Block Diagram of PPG Timer ............................................................................................................
13.3 Registers of PPG Timer ....................................................................................................................
13.3.1 Detailed Description of the PPG Timer ........................................................................................
13.4 Operation of PPG Timer ...................................................................................................................
290
292
293
294
299
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE ....................................... 303
14.1 Overview of Delay Interrupt Generation Module ............................................................................... 304
14.2 Operation of Delay Interrupt Generation Module .............................................................................. 306
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT .................................................. 307
15.1 Overview of DTP/External Interrupt Circuit .......................................................................................
15.2 Configuration of DTP/External Interrupt Circuit .................................................................................
15.3 Pins of DTP/External Interrupt Circuit ...............................................................................................
15.4 Registers of DTP/External Interrupt Circuit .......................................................................................
15.4.1 DTP/Interrupt source Register (EIRR) .........................................................................................
15.4.2 DTP/Interrupt Enable Register (ENIR) .........................................................................................
15.4.3 Request Level Setting Register (ELVR) .......................................................................................
15.5 Operation of the DTP/External Interrupt Circuit ................................................................................
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308
310
312
314
315
316
318
320
15.5.1 External Interrupt Function ........................................................................................................... 323
15.5.2 DTP Function ................................................................................................................................ 324
15.6 Notes on Using the DTP/External Interrupt Circuit ............................................................................ 326
15.7 Sample Programs for the DTP/External Interrupt Circuit ................................................................... 328
CHAPTER 16 8/10-BIT A/D CONVERTER ...................................................................... 333
16.1 Overview of 8/10-Bit A/D Converter ................................................................................................... 334
16.2 Configuration of 8/10-Bit A/D Converter ............................................................................................ 336
16.3 Pins of 8/10-Bit A/D Converter ........................................................................................................... 338
16.4 Registers of 8/10-Bit A/D Converter .................................................................................................. 340
16.4.1 Upper Bits of A/D Control Status Register (ADCSH) .................................................................... 341
16.4.2 Lower bits of A/D Control Status Register (ADCSL) ..................................................................... 344
16.4.3 A/D Data Registers (ADCRH/ADCRL) ......................................................................................... 346
16.5 Interrupts of 8/10-Bit A/D Converter .................................................................................................. 348
16.6 Operation of 8/10-Bit A/D Converter .................................................................................................. 349
16.6.1 Conversion Operation Using EI2OS ............................................................................................. 351
16.6.2 A/D Conversion Data Protect Function ......................................................................................... 352
16.7 Notes on Using the 8/10-Bit A/D Converter ....................................................................................... 354
16.8 Sample Program 1 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Single Mode) .......... 355
16.9 Sample Program 2 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Continuous Mode) .. 357
16.10 Sample Program 3 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Stop Mode) ............. 360
CHAPTER 17 UART ......................................................................................................... 363
17.1 Overview of UART ............................................................................................................................. 364
17.2 Configuration of UART ....................................................................................................................... 366
17.3 Pins of UART ..................................................................................................................................... 369
17.4 Registers of UART ............................................................................................................................. 371
17.4.1 Control Registers (SCR0/1) .......................................................................................................... 372
17.4.2 Mode Registers (SMR0/1) ............................................................................................................ 374
17.4.3 Status Registers (SSR0/1) ........................................................................................................... 376
17.4.4 Input Data Registers (SIDR0/1) and Output Data Registers (SODR0/1) ..................................... 378
17.4.5 Communication Prescaler Control Registers (CDCR0/1) ............................................................. 380
17.5 Interrupts of UART ............................................................................................................................. 382
17.5.1 Timing of Receive Interrupt Generation and Flag Setting ............................................................ 384
17.5.2 Timing of Send Interrupt Generation and Flag Setting ................................................................. 385
17.6 Baud Rates of UART ......................................................................................................................... 386
17.6.1 Baud Rate Selection by Dedicated Baud Rate Generator ............................................................ 388
17.6.2 Baud Rate Selection by Internal Timer (16-Bit Reload Timer) ..................................................... 391
17.6.3 Baud Rate Selection by External Clock ........................................................................................ 393
17.7 Operation of UART ............................................................................................................................ 394
17.7.1 Asynchronous Mode Operation (Operation Modes 0, 1) .............................................................. 396
17.7.2 Synchronous Mode Operation (Operation Mode 2) ...................................................................... 399
17.7.3 Bidirectional Communication Function (Normal Mode) ................................................................ 401
17.7.4 Function for Master/Slave Communication (Multiprocessor Mode) .............................................. 403
17.8 Notes on Using UART ....................................................................................................................... 406
17.9 Sample Program for UART ................................................................................................................ 407
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CHAPTER 18 CAN CONTROLLER ................................................................................. 409
18.1 CAN Controller Features ...................................................................................................................
18.2 Block Diagram of CAN Controller .....................................................................................................
18.3 Types of CAN Controller Registers ...................................................................................................
18.3.1 Control Status Register (CSR) .....................................................................................................
18.3.2 Last Event Indication Register (LEIR) ..........................................................................................
18.3.3 Receive and Transmit error Counter (RTEC) ..............................................................................
18.3.4 Bit Timing Register (BTR) ............................................................................................................
18.3.5 Message Buffer Valid Register (BVALR) .....................................................................................
18.3.6 IDE Register (IDER) ....................................................................................................................
18.3.7 Transmission Request Register (TREQR) ...................................................................................
18.3.8 Transmission RTR Register (TRTRR) .........................................................................................
18.3.9 Remote Frame Receive Wait Register (RFWTR) ........................................................................
18.3.10 Transmission Cancel Register (TCANR) .....................................................................................
18.3.11 Transmission Complete Register (TCR) ......................................................................................
18.3.12 Transmission Interrupt Enable Register (TIER) ...........................................................................
18.3.13 Receive Complete Register (RCR) ..............................................................................................
18.3.14 Remote Request Transmission Register (RRTRR) .....................................................................
18.3.15 Receive Overrun Register (ROVRR) ...........................................................................................
18.3.16 Receive Interrupt Enable Register (RIER) ...................................................................................
18.3.17 Acceptance Mask Selection Register (AMSR) .............................................................................
18.3.18 Acceptance mask Registers 0/1 (AMR0/AMR1) ..........................................................................
18.3.19 Message Buffers ..........................................................................................................................
18.3.20 ID Register x (x = 0 to 15) (IDRx) ................................................................................................
18.3.21 DLC Register x (x = 0 to 15) (DLCRx) .........................................................................................
18.3.22 Data Register x (x = 0 to 15) (DTRx) ...........................................................................................
18.3.23 CAN WAKE UP Control Register (CWUCR) ................................................................................
18.4 Transmission Via CAN Controller .....................................................................................................
18.5 Reception Via CAN Controller ..........................................................................................................
18.6 Notes on Using CAN Controller ........................................................................................................
18.7 Transmission Via Message Buffer (x) ...............................................................................................
18.8 Reception Via Message Buffer (x) ....................................................................................................
18.9 Specifying the Multi-Level Message Buffer Configuration ................................................................
18.10 CAN WAKE UP Function ..................................................................................................................
18.11 Sample Program for CAN Controller .................................................................................................
18.12 Precautions when Using CAN Controller ..........................................................................................
410
411
412
421
425
427
428
431
432
433
434
435
436
437
438
439
440
441
442
443
445
447
448
451
452
454
455
458
462
464
466
468
470
472
474
CHAPTER 19 LCD CONTROLLER/DRIVER ................................................................... 475
19.1 Outline of LCD Controller/Driver .......................................................................................................
19.2 Configuration of LCD Controller/Driver .............................................................................................
19.2.1 LCD Controller/Driver’s Internal Divide Resistor ..........................................................................
19.2.2 LCD controller/driver’s external divide resistor ............................................................................
19.3 LCD Controller/Driver Pins ................................................................................................................
19.4 LCD Controller/Driver Register .........................................................................................................
19.4.1 Lower Bits of LCD Control Register (LCRL) ................................................................................
19.4.2 Upper Bits of LCD Control Register (LCRH) ...............................................................................
19.5 Display RAM of the LCD Controller/Driver ........................................................................................
19.6 LCD Controller/Driver Operation .......................................................................................................
x
476
477
479
481
483
485
486
488
490
492
19.6.1 Output Waveform During LCD Controller/Driver Operation (1/2 Duty) ......................................... 493
19.6.2 Output Waveform in LCD Controller/Driver Operation
(1/3 Duty) 496
19.6.3 Output Waveform in LCD Controller/Driver Operation (1/4 Duty) ................................................. 499
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT ...... 503
20.1
20.2
20.3
20.4
20.5
20.6
Outline of the Low-voltage/CPU Operation Detection Reset Circuit .................................................. 504
Configuration of the Low-Voltage/CPU Operation Detection Reset Circuit ....................................... 506
Registers of the Low-voltage/CPU Operation Detection Reset Circuit .............................................. 508
Operation of the Low-voltage/CPU Operation Detection Reset Circuit ............................................. 510
Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit ........................................ 511
Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit ................................ 512
CHAPTER 21 STEPPING MOTOR CONTROLLER ....................................................... 513
21.1 Outline of the Stepping Motor Controller ........................................................................................... 514
21.2 Registers of the Stepping Motor Controller ........................................................................................ 515
21.2.1 PWM Control Register ................................................................................................................. 516
21.2.2 PWM1 and PWM2 Compare Registers ........................................................................................ 517
21.2.3 PWM1/PWM2 Selection Registers ............................................................................................... 519
21.3 Operation of the Stepping Motor Controller ....................................................................................... 521
21.4 Notes on Using the Stepping Motor Controller .................................................................................. 523
CHAPTER 22 SOUND GENERATOR .............................................................................. 525
22.1 Outline of the Sound Generator ......................................................................................................... 526
22.2 Registers of the Sound Generator ..................................................................................................... 527
22.2.1 Sound Control Register ................................................................................................................ 528
22.2.2 Frequency Data Register .............................................................................................................. 530
22.2.3 Amplitude Data Register ............................................................................................................... 531
22.2.4 Decrement Grade Register .......................................................................................................... 532
22.2.5 Tone Count Register .................................................................................................................... 533
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION .......................................... 535
23.1 Outline of the Address Match Detection Function ............................................................................. 536
23.2 Example Application of Address Match Detection Function .............................................................. 539
23.2.1 Example of Program Error Correction .......................................................................................... 540
23.2.2 Example of Correction Processing ............................................................................................... 541
CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE ................................. 543
24.1 Outline of the ROM Mirror Function Selection Module ...................................................................... 544
24.2 ROM Mirror Function Selection Register (ROMM) ............................................................................ 545
CHAPTER 25 1M BIT FLASH MEMORY ......................................................................... 547
25.1
25.2
25.3
25.4
25.5
25.6
Outline of 1M Bit Flash Memory ....................................................................................................... 548
Overall Block Diagram of the Flash Memory and Its Sector Configuration ........................................ 550
Write/Erase Mode .............................................................................................................................. 552
Flash Memory Control Status Register (FMCS) ................................................................................ 554
Starting the Flash Memory Automatic Algorithm ............................................................................... 556
Confirming the Execution State of the Automatic Algorithm .............................................................. 557
xi
25.6.1 Data Polling Flag (DQ7) ...............................................................................................................
25.6.2 Toggle Bit Flag (DQ6) ..................................................................................................................
25.6.3 Timing Limit Excess Flag (DQ5) ..................................................................................................
25.6.4 Sector Erasure Timer Flag (DQ3) ................................................................................................
25.7 Detailed Description of Writing/Erasing Flash Memory Data ............................................................
25.7.1 Setting the Flash Memory to Read/Reset State ...........................................................................
25.7.2 Writing Data to the Flash Memory ...............................................................................................
25.7.3 Erasing All Data in the Flash Memory (Chip Erase) ....................................................................
25.7.4 Erasing Data From the Flash Memory (Sector erasure) ..............................................................
25.7.5 Suspending Flash Memory Sector Erasure .................................................................................
25.7.6 Restarting Flash Memory Sector Erasure ....................................................................................
25.8 Notes on Using Flash Memory ..........................................................................................................
25.9 Sample Program for the 1M Bit Flash Memory .................................................................................
559
561
563
564
565
566
567
569
570
572
573
574
576
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION ....................... 581
26.1
26.2
26.3
26.4
Basic Configuration ...........................................................................................................................
Oscillator Clock Frequency and Serial Clock Input Frequency .........................................................
System Configuration of Flash Microcomputer Programmer ............................................................
Examples of Serial Programming Connection .................................................................................
582
584
585
586
APPENDIX .......................................................................................................................... 595
APPENDIX A I/O Map ................................................................................................................................
APPENDIX B Instructions ...........................................................................................................................
B.1 Instruction Types ............................................................................................................................
B.2 Addressing .....................................................................................................................................
B.3 Direct Addressing ...........................................................................................................................
B.4 Indirect Addressing .........................................................................................................................
B.5 Execution Cycle Count ...................................................................................................................
B.6 Effective Address Field ...................................................................................................................
B.7 How to Read the Instruction List ....................................................................................................
B.8 F2MC-16LX Instruction List ............................................................................................................
B.9 Instruction Map ...............................................................................................................................
596
604
605
606
608
613
619
622
623
626
640
INDEX ...................................................................................................................................663
xii
CHAPTER 1
OUTLINE
This Chapter describes features and provides the basic specification of the MB90420G/
425G series.
1.1 "Product Outline"
1.2 "Features"
1.3 "Block Diagram"
1.4 "Diagram Showing Package Dimensions"
1.5 "Pin Assignment Diagram"
1.6 "Description of Pin Functions"
1.7 "Types of Input/Output Circuits"
1.8 "Precautions for Device Handling"
1
CHAPTER 1 OUTLINE
1.1
Product Outline
This section gives an outline of MB90420G/425G series products.
■ Product Outline
Table 1.1-1 "Outline of MB90420G series products" gives an outline of MB90420G series
products. 1.1-2 "Outline of MB90425G series products (1)" gives an outline of MB90425G series
products.
Table 1.1-1 Outline of MB90420G series products
Feature
Product type
MB90V420G
MB90F423GA
(*1)
EVA product
MB90F423GB
(*2)
System clock
MB90423GA
(*2)
FLASH product
MB90423GB
(*2)
MB90423GC
(*2)
MASK ROM product
F2MC-16LX CPU
CPU
Clock
MB90F423GC
(*2)
2 systems
1 system
2 systems
1 system
2 systems
On-chip PLL clock multiplication scheme (x1, x2, x3, x4, 1/2 for PLL stop) minimum instruction execution time 62.5
ns (4 MHz oscillation x 4)
ROM
External
FLASH ROM 128KB
MASK ROM 128KB
RAM
6KB
6KB
6KB
CAN interface
2ch
Low-voltage/CPU
operation
detection reset
Not used
Package
PGA-256
QFP100, LQFP100
Emulatordedicated power
supply*3
Not used
−
Used
Not used
Used
Used
*1: Being developed
*2: To be developed
*3: Setting of dip-switch S2 for using the evaluation pod MB2145-507. For further information, refer to the "MB2145-507 Hardware
Manual" (Section 2.7 "Switching the Power Source").
2
1.1 Product Outline
Table 1.1-2 Outline of MB90425G series products (1)
Product type
MB90F428GA
(*1)
−
Feature
MB90F428GB
(*2)
MB90F428GC
(*2)
EVA product (*3)
FLASH product
CPU
−
F2MC-16LX CPU
Clock
−
System clock
−
ROM
−
FLASH ROM 128KB
RAM
−
6KB
CAN interface
−
1ch
Low-voltage/CPU
operation detection
reset
−
Package
−
QFP100, CLQFP100
Emulator-dedicated
power supply
−
−
1 system
2 systems
On-chip PLL clock multiplication scheme (x1, x2, x3, x4, 1/2 for PLL
stop) minimum instruction execution time: 62.5 ns (4 MHz oscillation
x4)
Used
Not used
*1: Being developed
*2: To be developed
*3: EVA products use MB90V420G commonly for MB90420G/425G series products.
Table 1.1-3 Outline of MB90425G series products (2)
Feature
MB90427GA
(*2)
MB90427GB
(*2)
MB90427GC
(*2)
Product type
MB90428GA
(*1)
MB90428GB
(*2)
MB90428GC
(*2)
MASK ROM
F2MC-16LX CPU
CPU
Clock
1 system
2 systems
1 system
2 systems
System clock
On-chip PLL clock multiplication scheme (x1, x2, x3, x4, 1/2 for PLL stop) minimum instruction
execution time 62.5 ns (4 MHz oscillation x4)
ROM
MASK ROM 64KB
MASK ROM 128KB
RAM
4KB
6KB
CAN interface
Low-voltage/CPU
operation detection
reset
Package
Emulator-dedicated
power supply
1ch
Used
Not used
Used
Not used
QFP100, CLQFP100
−
*1: Being developed
*2: To be developed
3
CHAPTER 1 OUTLINE
1.2
Features
This section describes the features of MB90420G/425G series products.
■ Features
Table 1.2-1 "Features of MB90420G/425G series products" indicates features of MB90420G/
425G series products.
Table 1.2-1 Features of MB90420G/425G series products
Function
4
Feature
16-bit input capture (4 ch)
Detects rising edge, falling edge or both.
16-bit capture register x4
Detecting a pin input edge latches the counter value of the 16-bit free-run timer and
generates an interrupt request.
16-bit reload timer (2 ch)
Allows 16-bit reload timer operations (e.g., toggle output and one-shot output
selectable) and event count function selection.
Watch timer (main clock)
Is directly driven by the oscillation clock.
Supports the correction of oscillation deviations.
Second/minute/hour registers allowing read/write operations
Signal interrupt
16-bit PPG (3ch)
Output pin (x3), external trigger input pin (x1)
Operation clock frequency: fcp, fcp/22, fcp/24, fcp/26
Delayed interrupt
Generates an interrupt for task switching.
Interrupt requests to the CPU can be generated and cancelled by software
External interrupt (8 ch)
8 independent channels
Interrupt source: Allowed selections are L --> H edge/H --> L edge/L level/H level.
A/D converter
10 bits or 8 bits resolution ×8 ch (input multiplex)
Conversion time: 6.13 µs or less (fcp=16 MHz)
External trigger activation allowed (P50/INT0/ADTG)
Internal timer activation allowed (16-bit reload timer 1)
UART(2ch)
Full-duplex double-buffer scheme
Supports asynchronous/synchronous transfer (with start/stop bits).
Selection of internal timer allowed as clock (16-bit reload timer 0)
Asynchronous: 4808 bps, 5208 bps, 9615 bps, 10417 bps, 19230 bps, 38460 bps,
62500 bps, 500000 bps
Synchronous: 500 Kbps, 1 Mbps, 2 Mbps (when fcp=16 MHz)
CAN interface (*1)
Conforms to CAN specification version 2.0 part A and part B.
Automatic retransmission is executed if an error occurs.
Automatic transmission is executed in response to a remote frame.
Supports data and multiple messages for prioritized 16 message buffers with ID.
Flexible configuration of receiving filter:
All bit compare/all bit mask/partial mask of two bits
Supports up to 1 Mbps.
CAN WAKEUP function (RX connected to INTO internally within the device).
LCD controller / driver (1 ch)
Segment driver and common driver directly drives LCD panel (LCD display).
1.2 Features
Table 1.2-1 Features of MB90420G/425G series products (Continued)
Function
Feature
Low-voltage /CPU operation
detection reset (*2)
Automatically reset if low-voltage is detected.
CPU operation detection function
Stepping motor controller (4 ch)
high current output per channel x 4
All synchronous channels, 8/10 bit PWM x 2
Sound generator
8-bit PWM signal is mixed with tone frequency from 8-bit reload counter.
PWM frequency: 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (when fcp=16 MHz)
Tone frequency: PWM frequency /2/ (reload value +1)
Input/output port
Push-pull output and Schmidt trigger input
Programmable in units of individual bits as input/output or peripheral signal.
Flash memory
Supports automatic programming, Embedded Algorithm TM (*3), write/delete/suspend
deletion and restart deletion commands.
Flag for indicating completion of algorithm processing.
Flash writer made by Minato Electronics.
Boot block configuration
Delete can be executed in units of blocks.
Block protection using the external programming voltage.
*1: Two channels are built-in in the MB90420G series, one channel is built-in in the MB90425G series.
*2: Mounted only in the MB90F423GA/GB, MB90F428GA/GB, MB90423GA/GB, MB90427GA/GB, MB90428GA/GB, but
not in the MB90F423GC, MB90F428GC, MB90423GC, MB90427GC, MB90428GC.
*3: Embedded Algorithm is a registered trademark of Advanced Micro Devices Inc.
5
CHAPTER 1 OUTLINE
1.3
Block Diagram
This section shows a block diagram of MB90420G/425G series products.
■ Block Diagram
Fig 1.3-1 shows a block diagram of MB90420G/425G series products.
Figure 1.3-1 Block diagram
X0,X1
X0A,X1A
RST
CPU
F2MC -16LX core
RAM
Interrupt
controller
ROM
Low voltage/
CPU operation
detect reset
Sound generator
CAN controller
Port 5
External interrupt
P00/SIN0/INT4
P0 1/SOT0/INT5
P0 2/SCK0/INT6
P0 3/SIN1/INT7
P0 4/SOT1
P0 5/SCK1/TRG
P0 6/PPG0/TOT1
P0 7/PPG1/TIN1
(8ch)
Port 8
Stepping
motor
controller
0/1/2/3
UART 0/1
Prescaler
0/1
Port 0
PPG0/1/2
P10/ PPG2
P11/ TOT0/WOT
P12/ TIN0/IN3
P13/ IN2
P14/ IN1
P15/ IN0
F2MC -16LX BUS
P57/SGA
P56/SGO/FRCK
P55/ RX0
P54/ TX0
P53/ INT3
P52/ INT2(/TX1)
P51/ INT1(/RX1)
P50/INT0/ADTG
Clock control
circuit
Port 7
Port 9
P67 - P60/
AN7- AN0
AVCC/AVSS
AVRH
P 91 - P90/
SEG23 - SEG22
Port 4
P47 - P40/
SEG21 - SEG14
Port 3
P37 - P 36/
SEG13 - SEG12
A/D converter
(8ch)
Reload timer
0/1
Watch timer
(main)
ICU 0/1 /2/3
Specification of evaluation device
(MB90V420G)
No built-in ROM provided.
Built-in RAM has a capacity of 6 KB.
6
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
Port 6
Port 1
Free-run timer
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
LCD
controller/
driver
SEG11- SEG0
COM3 - COM0
V3 - V0
1.3 Block Diagram
Notes:
Two and one CAN interfaces are built-in in MB90420G and MB90425G series products,
respectively.
Low-voltage/CPU operation detection reset is built-in in MB90F423GA/GB, MB90F428GA/
GB, MB90423GA/GB, MB90427GA/GB, MB90428GA/GB products only. It is not built-in in
MB90F423GC, MB90F428GC, MB90423GC, MB90427GC, MB90428GC products.
7
CHAPTER 1 OUTLINE
1.4
Diagram Showing Package Dimensions
Two types of packages are used for MB90420G/425G series products.
This diagram showing package dimensions is for reference purposes only. For the
formally correct version, contact us.
■ Package Dimensions (QFP100)
FPT-100P-M06
100-pin plastic QFP
Lead pitch
0.65 mm
Package width
package length
14.00
20.00 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
3.35 mm MAX
(FPT-100P-M06)
100-pin plastic QFP
(FPT-100P-M06)
Note: Pins width and pins thickness include plating thickness.
23.90±0.40(.941±.016)
20.00±0.20(.787±.008)
80
51
81
50
0.10(.004)
17.90±0.40
(.705±.016)
14.00±0.20
(.551±.008)
INDEX
Details of "A" part
100
1
30
0.65(.026)
"A"
C
8
0.25(.010)
+0.35
3.00
+.014
.118
(Mounting height)
31
2001 FUJITSU LIMITED F100008S-c-4-4
0.32±0.05
(.013±.002)
0.13(.005)
M
0.17±0.06
(.007±.002)
0.80±0.20
(.031±.008)
0.88±0.15
(.035±.006)
0.25±0.20
(.010±.008)
(Stand off)
Dimensions in mm (inches).
1.4 Diagram Showing Package Dimensions
■ Package Dimensions (LQFP100)
FPT-100P-M05
100-pin plastic LQFP
Lead pitch
0.50 mm
Package width
package length
14.0
14.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Weight
0.65g
(FPT-100P-M05)
100-pin plastic LQFP
(FPT-100P-M05)
Pins width and pins thickness include plating thickness.
16.00±0.20(.630±.008)SQ
14.00±0.10(.551±.004)SQ
75
51
76
50
0.08(.003)
Details of "A" part
+0.20
100
26
"A"
1
25
0.50(.020)
C
+.008
1.50
.059
(Mounting height)
INDEX
2000 FUJITSU LIMITED F100007S-3c-5
0.20±0.05
(.008±.002)
0.08(.003)
M
0.145±0.055
(.0057±.0022)
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10±0.10
(.004±.004)
(Stand off)
0.25(.010)
Dimensions in mm (inches).
9
CHAPTER 1 OUTLINE
1.5
Pin Assignment Diagram
This section presents the pin assignment diagram of MB90420G/425G series products.
■ Pin Assignment (QFP100)
Figure 1.5-1 "Pin assignment (QFP100)" shows the pin assignment diagram for the plastic
QFP100 type.
Figure 1.5-1 Pin assignment (QFP100)
Vss
X0
X1
Vcc
P00/SIN0/INT4
P01/SOT0/INT5
P02/SCK0/INT6
P03/SIN1/INT7
P04/SOT1
P05/SCK1/TRG
P06/PPG0/TOT1
P07/PPG1/TIN1
P10/PPG2
P11/TOT 0/WOT
P12/TIN0/IN3
P13/IN2
P14/IN1
P15/IN0
COM0
COM1
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
Vss
SEG8
SEG9
SEG10
SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
Vcc
P45/SEG19
P46/SEG20
P47/SEG21
C
P90/SEG22
P91/SEG23
V0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MB90420G/425G Series
TOP VIEW
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
MD1
MD0
P52/INT2 (/TX1)
P51/INT1 (/RX1)
P67/AN7
P66/AN6
P65/AN5
P64/AN4
Vss
P63/AN3
P62/AN2
P61/AN1
P60/AN0
AVss
P50/INT0/ADTG
AVRH
AVcc
V3
V2
V1
10
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
X0A
X1A
P57/SGA
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DVss
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVcc
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVss
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVcc
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVss
P53/INT3
MD2
1.5 Pin Assignment Diagram
■ Pin Assignment (LQFP100)
Figure 1.5-2 "Pin assignment (LQFP100)" shows the pin assignment diagram for the plastic
LQFP100 type.
Figure 1.5-2 Pin assignment (LQFP100)
P57/SGA
X1A
X0A
Vss
X0
X1
Vcc
P00/SIN0/INT4
P01/SOT0/INT5
P02/SCK0/INT6
P03/SIN1/INT7
P04/SOT1
P05/SCK1/TRG
P06/PPG0/TOT1
P07/PPG1/TIN1
P10/PPG2
P11/TOT0 /WOT
P12/TIN0/IN3
P13/IN2
P14/IN1
P15/IN0
COM0
COM1
COM2
COM3
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
Vss
SEG8
SEG9
SEG10
SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
Vcc
P45/SEG19
P46/SEG20
P47/SEG21
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
MB90420G/425G series
TOP VIEW
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DVss
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVcc
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVss
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVcc
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVss
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
P53/INT3
MD2
MD1
MD0
P52/INT2 (/TX1)
P51/INT1 (/RX1)
P67/AN7
P66/AN6
P65/AN5
P64/AN4
Vss
P63/AN3
P62/AN2
P61/AN1
P60/AN0
AVss
P50/INT0/ADTG
AVRH
AVcc
V3
V2
V1
V0
P91/SEG23
P90/SEG22
11
CHAPTER 1 OUTLINE
1.6
Description of Pin Functions
This section describes the pin functions of MB90420G/425G series products.
■ Description of Pin Functions
Table 1.6-1 "Description of pin functions" describes the pin functions of MB90420G/425G series
products.
Table 1.6-1 Description of pin functions
Pin number
Pin name
LQFP
QFP
80
82
Circuit type
X0
Description of function
High-speed oscillation input pin
A
81
83
X1
78
80
X0A
77
79
X1A
75
77
RST
High-speed oscillation output pin
Low-speed oscillation input pin (*1)
A
B
P00
83
84
85
86
85
86
87
88
SIN0
G
External interrupt input pin for INT4
P01
General-purpose input/output port
SOT0
G
External interrupt input pin for INT5
P02
general-purpose input/output port
SCK0
G
Serial clock input/output pin for UART ch.0
INT6
External interrupt input pin for INT6
P03
General-purpose input/output port
SIN1
G
Serial data input pin for UART ch.1
External interrupt input pin for INT7
General-purpose input/output port
G
SOT1
Serial data output pin for UART ch.1
P05
SCK1
TRG
12
Serial data output pin for UART ch.0
INT5
89
90
Serial data input pin for UART ch.0
INT4
P04
88
Reset input pin
General-purpose input/output port
INT7
87
Low-speed oscillation output pin (*2)
General-purpose input/output port
G
Serial clock input/output pin for UART ch.1
External trigger input pin for 16bit PPG ch.0
-2
1.6 Description of Pin Functions
Table 1.6-1 Description of pin functions (Continued)
Pin number
Pin name
LQFP
Circuit type
P06
89
91
PPG0
General-purpose input/output port
G
TOT1
92
PPG1
General-purpose input/output port
G
TIN1
93
General-purpose input/output port
G
PPG2
Output pin for 16bit PPG ch.2
P11
92
93
94
95
TOT0
General-purpose input/output port
G
TOT output pin for 16bit reload timer ch.0
WOT
WOT output pin for watch timer
P12
General-purpose input/output port
TIN0
G
IN3
96 to 98
TIN input pin for 16bit reload timer ch.0
Trigger input pin for input capture ch.3
P13 to P15
94 to 96
Output pin for 16bit PPG ch.1
TIN input pin for 16bit reload timer ch.1
P10
91
Output pin for 16bitPPG ch.0
TOT output pin for 16bit reload timer ch.1
P07
90
Description of function
QFP
General-purpose input/output port
G
IN2 to IN0
Trigger input pin for input capture ch.0 - 2
97 to 100
99 to 100, 1
to 2
COM0 to
COM3
I
LCD controller / driver common output pin
1 to 8, 10 to
13
3 to 10, 12 to
15
SEG0 to
SEG11
I
LCD controller / driver segment output pin
P36 to P37
14 to 15
16 to 17
SEG12 to
SEG13
General-purpose input/output port
E
LCD controller / driver segment output pin
P40 to P47
16 to 20, 22
to 24
18 to 22, 24
to 26
SEG14 to
SEG21
General-purpose input/output port
E
LCD controller / driver segment output pin
P90 to P91
26 to 27
28 to 29
SEG22 to
SEG23
General-purpose input/output port
E
LCD controller / driver segment output pin
P50
34
36
INT0
ADTG
General-purpose input/output port
G
INT0 external interrupt input pin
A/D converter external trigger input pin
13
CHAPTER 1 OUTLINE
Table 1.6-1 Description of pin functions (Continued)
Pin number
Pin name
LQFP
QFP
36 to 39, 41
to 44
38 to 41, 43
to 46
Circuit type
P60 to P67
General-purpose input/output port
F
AN0 to AN7
A/D converter input pin
P51
45
47
INT1
General-purpose input/output port
G
(RX1) (*3)
48
INT2
General-purpose input/output port
G
(TX1) (*3)
52 to 55
52
54 to 57
General-purpose input/output port
G
INT3
External interrupt input pin for INT3
P70 to P73
General-purpose input/output port
PWM1P0
PWM1M0
PWM2P0
PWM2M0
H
Output pin for stepping motor controller ch.0
P74 to P77
57 to 60
59 to 62
PWM1P1
PWM1M1
PWM2P1
PWM2M1
General-purpose input/output port
H
Output pin for stepping motor controller ch.1
P80 to P83
62 to 65
64 to 67
PWM1P2
PWM1M2
PWM2P2
PWM2M2
General-purpose input/output port
H
Output pin for stepping motor controller ch.2
P84 to P87
67 to 70
69 to 72
PWM1P3
PWM1M3
PWM2P3
PWM2M3
General-purpose input/output port
H
Output pin for stepping motor controller ch.3
P54
72
74
General-purpose input/output port
G
TX0
TX output pin for CAN interface
P55
73
75
General-purpose input/output port
G
RX0
14
INT2 external interrupt input pin
TX output pin for CAN interface 1
P53
50
INT1 external interrupt input pin
RX input pin for CAN interface 1
P52
46
Description of function
RX input pin for CAN interface 0
1.6 Description of Pin Functions
Table 1.6-1 Description of pin functions (Continued)
Pin number
Pin name
LQFP
Circuit type
P56
74
76
SGO
General-purpose input/output port
G
FRCK
78
SGO output pin for sound generator
Free-run timer clock input pin
P57
76
Description of function
QFP
General-purpose input/output port
G
SGA
SGA output pin for sound generator
28 to 31
30 to 33
V0 to V3
−
LCD controller / driver reference power pin
56, 66
58, 68
DVCC
−
Dedicated power input pin for high current
output (pin number 54 to 57, 59 to 62, 64 to
67, 69 to 72)
51, 61, 71
53, 63, 73
DVSS
−
dedicated GND power pin for high current
output buffer (pin number 54 to 57, 59 to 62,
64 to 67, 69 to 72)
32
34
AVCC
−
Dedicated power input pin for A/D converter
35
37
AVSS
−
Dedicated GND power pin for A/D converter
33
35
AVRH
−
Vref+ and input pin for A/D converter. Vrefis fixed to AVSS.
47
48
49
50
MD0
MD1
C
Input pin for test mode. Connected to VCC.
49
51
MD2
C/D(*4)
Input pin for test mode. Connected to VSS.
25
27
C
−
Pin for external capacitor. Connect a
condenser of 0.1 µF between this pin and
VSS.
21, 82
23, 84
VCC
−
Power input pin
9, 40, 79
11, 42, 81
VSS
−
GND power pin
*1: For MB90F423GA, MB90F428GA, MB90423GA, MB90427GA, MB90428GA series, pull-down process
is required.
*2: For MB90F423GA, MB90F428GA, MB90423GA, MB90427GA, MB90428GA series, set to OPEN state.
*3: Function used only for MB90420G series products.
*4: Circuit type D is for MASK products, circuit type C is for FLASH products.
15
CHAPTER 1 OUTLINE
1.7
Types of Input/Output Circuits
This section describes the types of the input/output circuits for each pin.
■ Types of Input/Output Circuits
Table 1.7-1 "Types of input/output circuits" shows the types of input/output circuits for each pin.
Table 1.7-1 Types of input/output circuits
Type
Circuit
A
Description
•
•
X1/X1A
Oscillation feedback resistor
: approx. 1 MΩ (X0, X1: main)
Oscillation feedback resistor
: approx. 10 MΩ (X0A, X1A: sub)
X0/X0A
Standby control signal
B
•
•
Pull-up resistor used: approx.50 kΩ
Hysteresis input
•
Hysteresis input
•
•
Pull-down resistor used: approx. 50 kΩ
Hysteresis input
Hysteresis input
C
Hysteresis input
D
Hysteresis input
16
1.7 Types of Input/Output Circuits
Table 1.7-1 Types of input/output circuits (Continued)
Type
Circuit
Description
E
•
•
•
CMOS output
LCDC output
Hysteresis input
•
•
•
CMOS output
Hysteresis input
Analog input
•
•
CMOS output
Hysteresis input
•
•
CMOS high current output
Hysteresis input
•
LCDC output
LCDC output
Hysteresis input
F
LCDC output
Hysteresis input
G
Hysteresis input
H
High current
Hysteresis input
I
LCDC output
17
CHAPTER 1 OUTLINE
1.8
Precautions for Device Handling
For device handling, pay special attention related to the following 11 items:
• Strictly observing the maximum voltage rating (for latch-up prevention)
• Providing a stable supply voltage
• Power-on
• Handling unused pins
• Processing related to A/D converter power supply pins
• Using external clocks
• Power supply pins
• Power-on sequence for analog input of A/D converter
• Handling the power supply to high current output buffer pins (DVCC, DVSS)
• Pull-up/pull-down resistor
• Notes to follow when sub-clock mode is not used
■ Strictly Observing the Maximum Voltage Rating (for Latch-Up Prevention)
Do not apply a voltage higher than VCC or lower than VSS to input pins and output pins of
MB90420G/425G series products. Moreover, do not apply a voltage exceeding the rating range
from VCC-VSS. When a voltage exceeding the rating is applied, a latch-up may occur. During a
latch-up, the supply voltage increases rapidly, which can result in heat-induced damage to
elements. Ensure that the voltage applied does not exceed the maximum rating.
Be careful not to exceed the voltage rating of the digital power supply (VCC) when turning on or
turning off the analog power (AVCC, AVRH), the power supply to high current output buffer pins
(DVCC) and the power to the analog input.
There is no distinction regarding the power-on sequence of analog power (AVCC, AVRH) and
the power supply to high current output buffer pins (DVCC) after the digital power (VCC) is
supplied.
■ Providing a Stable Supply Voltage
Be sure to stabilize the voltage of the VCC power supply since a rapid change in voltage may
lead to incorrect operation. As a reference for the stabilization of voltage deviations, note that
the VCC ripple voltage (p-p value) for commercial frequency (50 to 60 Hz) must be within 10 %
of the VCC supply voltage, and the transient deviation ratio caused by the power switching must
not exceed 0.1 V/ms.
■ Power-On
To prevent incorrect operation of the built-in step-down circuit, voltage start-up time at power-on
(0.2V to 2.7V) must be 50 µs more.
18
1.8 Precautions for Device Handling
■ Handling Unused Pins
Leaving an unused input pin open may result in incorrect operation because of external noise.
In these cases, pull-up or pull-down via a resistor of at least 2KΩ or more must be applied.
An output pin that is not in use must be either set to output status and "open", or set to input
status and handled as an input pin.
■ Processing Related to A/D Converter Power Supply Pins
If unused, the A/D converter must be connected so that AVCC=VCC and AVSS=AVRH= VSS.
■ Using External Clocks
When an external clock is used, an oscillation stabilization wait interval shall be applied at
recovery from power-on reset, sub-clock mode and stop mode. If an external clock is used, as
shown in Figure 1.8-1 "Example of using an external clock", drive only the X0 pin and leave the
X1 pin open.
Figure 1.8-1 Example of using an external clock
X0
OPEN
X1
MB90420G/425G Series
■ Power Pin
To prevent a latch-up, multiple VCC and VSS power pins are connected within the device.
However, VCC and VSS power pins must be connected externally to the same power supply to
decrease unnecessary radiation, prevent an incorrect operation of the strobe signal due to rising
ground level and maintain the total output current standard. (See Figure 1.8-2 "Power supply
pins (VCC/VSS)".)
Figure 1.8-2 Power supply pins (VCC/VSS)
Vcc
Vss
Vss
V
s
s
V
c
c
Vcc
V
s
s
Vcc
V
c
c
Vss
Use low impedance from the current supply source to connect with the VCC and VSS power pins
of the device. Use a bypass condenser of approximately 1.0 µF between VCC and VSS of the
device to connect areas near VCC and VSS power pins.
19
CHAPTER 1 OUTLINE
■ Power-On Sequence for Analog Input of A/D Converter
Apply the voltage to the A/D converter power pins (AVCC, AVRH) and analog input pins (AN0 to
AN7) always after powering on the digital power supply (VCC). Turn off the digital power (VCC)
by turning off the device power after A/D converter and analog input power are turned off. In this
case, AVRH shall not exceed AVCC. Using a pin which is shared as analog input as an input
port requires AVCC not exceeding the input voltage (Turning on and off the voltage to the analog
and digital power supply at the same time causes no problems.)
■ Handling the Power Supply to High Current Output Buffer Pins (DVCC and DVSS)
Apply the power (DVCC and DVSS) to current output buffer pins always after the digital power
(VCC) is turned on. Turn off the digital power (VCC) after the power to the high current output
buffer pin is turned off (Turning on and off the high current output buffer pin power and the
digital power at the same time causes no problems.)
Using the high current output buffer pin as general-purpose port requires the power (DVCC and
DVSS) applied to the high current output buffer pin.
■ Pull-up/Pull-down Resistor
The MB90420G/425G series supports neither internal pull-up nor pull-down resistors. Use
external configuration parts as necessary
■ Notes to Follow in Cases When Sub-Clock Mode is Not Used
If no oscillator is connected to the X0A and X1A pins, apply pull-down processing to the X0A pin
and leave the X1A pin open.
■ Notes on during operation of PLL clock mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped.
Performance of this operation, however, cannot be guaranteed.
20
CHAPTER 2
CPU
This Chapter describes the CPU of the F2MC-16LX.
2.1 "Outline of CPU"
2.2 "Memory Space"
2.3 "Memory Map"
2.4 "Addressing"
2.5 "Allocation of Multiple Byte Data in the Memory"
2.6 "Registers"
2.7 "Dedicated Registers"
2.8 "General-Purpose Registers"
2.9 "Prefix Codes"
21
CHAPTER 2 CPU
2.1
Outline of CPU
The F2MC-16LX CPU core is a 16-bit CPU designed for applications in which highspeed real-time processing is required, such as for various consumer devices and in
vehicles. The F2MC-16LX instruction set is designed for application in device
controllers and is supporting a variety of control operations with high-speed and high
efficiency processing.
■ CPU Features
The F2MC-16LX CPU core supports not only 16-bit data but has also a 32-bit accumulator for
32-bit operations. The memory space can be a maximum of 16 MB, and can be accessed either
with a linear or bank scheme. The instruction system is based on the F2MC-8L A-T architecture
but was further improved with the addition of high-level language compatible instructions,
extensions of the addressing mode, as well as by more powerful instruction for multiplication,
division and bit operations. The F2MC-16LX CPU has the features listed below.
❍ Minimum instruction execution time
62.5 ns (4 MHz oscillation, multiply-by-four)
❍ Maximum memory space
16 MB, access by linear/bank schemes
❍ Instruction system optimized for application in controllers
•
Various data types: bit/byte/word/long word
•
Extended addressing mode: 23 types
•
Using 32-bit accumulator for more powerful high-precision operations (support of 32-bit
data), signed multiplication/division and extended RETI instruction
❍ Powerful interrupt functions
Eight priority levels (programmable)
❍ CPU-independent automatic transfer function
Extended intelligent I/O service up to 16 channels
❍ Support for high-level languages (C language)/Instruction system supporting multi-task
processing
Using system stack pointer/symmetric instruction sets/barrel shift instruction
❍ Increased execution speed
4-byte queuing
Note:
MB90420G/425G series uses only single-chip mode, accessing only memory space of builtin ROM, built-in RAM and built-in circuits for peripherals.
22
2.2 Memory Space
2.2
Memory Space
F2MC-16LX CPU has a memory space of 16 MB. The F2MC-16LX CPU controls generalpurpose data, program data and I/O data, all of which are allocated within the 16 MB
memory space. A part of the memory space is used for special applications, such as
for extension intelligent I/O service (EI2OS) descriptors, general-purpose registers and
vector tables.
■ Memory Space
General-purpose data, programs, and I/O data is allocated anywhere within the 16 MB memory
space of the F2MC-16LX CPU. The CPU indicates such addresses using a 24-bit address bus
to access each peripheral function.
Figure 2.2-1 "Example of relationship between F2MC-16LX system and memory map" indicates
the relationship between the F2MC-16LX system and the memory map.
Figure 2.2-1 Example of relationship between F2MC-16LX system and memory map
F2MC-16LX device
FFFFFFH
Vector table area
Programs
FFFC00H
F2MC-16LX
CPU
Internal bus
FF0000H *1
100000H
010000H
004000H*2
Generalpurpose data
EI2OS
Interrupt
Peripheral
circuit
General
purpose port
002000H
000D00H*3
000380H
000180H
000100H
0000C0H
0000B0H
000020H
000000H
ROM area
Program area
External area *4
ROM are
(FF bank image)
External area *4
Data area
General purpose
register
RAM area
EI 2 OS descriptor
area
External area *4
Interrupt control register area
Peripheral function control
register area
I/O port control register area
I/O area
*1: Internal ROM capacity differs depending on the product type.
*2: Image access area differs depending on the product type.
*3: Internal RAM capacity differs depending on the product type.
*4: No access occurs in single chip mode.
23
CHAPTER 2 CPU
■ ROM area
❍ Vector table area (Address: FFFC00H to FFFFFFH)
•
Used as vector tables for vector call instructions, interrupt vectors and reset vectors.
•
Assigned to the highest portion of ROM area for setting the start address of the
corresponding routine as address data in the applicable vector table.
❍ Program area (Address: Up to FFFBFFH)
•
ROM is built in as an internal program area.
•
The internal ROM capacity differs depending on the product type.
■ RAM area
❍ Data area (Address: 000100H and later)
•
Static RAM is built-in as an internal data area.
•
The internal RAM capacity differs depending on the product type.
❍ General-purpose register area (address: 000180H to 00037FH)
•
Supplemental registers are provided for 8-bit, 16-bit and 32-bit operations and transfer.
•
Allocated in a part of the RAM area, can be uses as general-purpose RAM.
•
Using for general-purpose register allows a high-speed access with short instructions by
general-purpose register addressing.
❍ Extended intelligent I/O service (EI2OS) descriptor area (address: 000100H to 00017FH)
•
Stores transfer mode, I/O address, transfer count and buffer address.
•
Allocated in a part of the RAM area, can be used as general-purpose RAM.
■ I/O Area
❍ Interrupt control register area (address: 0000B0H to 0000BFH)
Interrupt control register (ICR00 to ICR15) supports all peripheral functions that have interrupt
functions, providing interrupt level settings and extended intelligent I/O service (EI2OS) control.
❍ Peripheral function control register area (address: 000020H to 0000AFH)
Provides control of built-in peripheral functions and data input/output.
❍ I/O port control register area (Address: 000000H to 00001FH)
Provides I/O port control and data input/output.
24
2.3 Memory Map
2.3
Memory Map
This section describes the memory map for the different types of MB90420G/425G
series products.
■ Memory Map
Figure 2.3-1 "Memory map" shows the memory map of MB90420G/425G series.
Figure 2.3-1 Memory map
Single chip mode
(using ROM mirror function)
000000 H
Peripheral area
0000C0 H
000100 H
Register
RAM area
Address #2
003900 H
Peripheral area
004000 H
ROM area
(FF bank image)
010000 H
Address #1
ROM area
: Internal access memory
FFFFFFH
: Access prohibited
Product type
Address #1
Address #2
MB90423G
FE0000H
001900H
MB90427G
FF0000H
001100H
MB90428G
FE0000H
001900H
MB90F423G
FE0000H
001900H
MB90F428G
FE0000H
001900H
MB90V420G
FE0000H (*1)
001900H
*1: V products have no built-in ROM. This area should be understood as the ROM decode area of the tool.
25
CHAPTER 2 CPU
Notes:
If "no ROM mirror function" is selected, refer to "ROM mirror function selection module."
The upper 00 bank allows referencing ROM data in the FF bank as an image for effectively
using the C compiler's small model. Because the FF bank's lower 16-bit address is set to the
same value, the table in ROM can be referenced without using a far declaration with a
pointer. For example, when accessing 00C000H, the ROM content at FFC000H is actually
accessed. Since the ROM area in the FF bank exceeds 48KB, not the whole area can be
referenced via the 00 bank image. Therefore, the ROM data in FF4000H to FFFFFFH is
referenced as an image in 004000H to 00FFFFH, and the ROM data table is then stored in
the area FF4000H to FFFFFFH.
26
2.4 Addressing
2.4
Addressing
Both linear and bank address generation schemes are available.
The linear scheme is used to directly specify all 24-bit addresses within the
instruction.
The bank scheme is used to directly specify upper 8-bit addresses via the bank
register depending on how the data will be used and to specify the lower bit addresses
with instructions.
The F2MC-16LX series basically uses bank addressing.
■ Linear addressing and bank addressing
Linear scheme addressing is used to access the 16 MB space as a continuous address space.
The bank scheme is used to divide and control the 16 MB space by dividing it into 256 banks of
64 KB each.
An outline of memory control with linear and bank schemes is shown in Figure 2.4-1 "Memory
control with linear and bank schemes".
Figure 2.4-1 Memory control with linear and bank schemes
Linear scheme
FFFFFFH
123456 H
Bank scheme
FFFFFFH
FF0000 H
FEFFFFH
FE0000 H
FDFFFFH
FD0000 H
FF bank
64k bytes
FE bank
FD bank
123456 H
12 bank
000000 H
123456 H
All specified by instruction
04FFFF H
040000 H
03FFFF H
030000 H
02FFFF H
020000 H
01FFFF H
010000 H
00FFFF H
000000 H
04 bank
03 bank
02 bank
01 bank
00 bank
123456 H
Specified by instruction
Specified by bank register according
to use
27
CHAPTER 2 CPU
2.4.1
Addressing with Linear Scheme
There are two types of linear addressing: Directly addressing 24-bit addresses with an
operand, and using the lower 24 bits of 32-bit general-purpose registers as address.
■ Specification with 24-bit Operand
Figure 2.4-2 Example of linear addressing (specification with 24-bit operand)
JMPP
123456H
Old program counter
+ program bank
17
452D
17452D H
New program counter
12
+ program bank
3456
123456 H
JMPP
123456H
Next instruction
■ Indirect Specification with 32-bit Register
Figure 2.4-3 Example of linear addressing (32-bit register indirectly specified)
MOV A,@RL1+7
Old AL
XXXX
090700 H
3AH
+7
New AL
003A
RL1
(Upper 8 bits are ignored)
RL1: 32-bit (long word) general-purpose register
28
240906F9H
2.4 Addressing
2.4.2
Addressing with Bank Scheme
When applying the bank scheme, the 16 MB memory space is divided into 256 banks
of 64 KB each, and the bank address corresponding to each space is specified via a
bank register. The upper 8 bits of the address are specified with the bank address and
the lower 16 bits are specified with an instruction.
Five bank register types are available depending on use, as listed below.
• program bank register (PCB)
• data bank register (DTB)
• user stack bank register (USB)
• system stack bank register (SSB)
• additional bank register (ADB)
■ Bank Register and Access Space
Table 2.4-1 "Access space and major application for each bank register" shows the access
space and major use of each bank register.
Table 2.4-1 Access space and major application for each bank register
Bank register name
Access
space
Main use
Initial value
at reset
Program bank register (PCB)
program
(PC) space
Stores instruction code, vector table and
immediate data.
FFH
Data bank register (DTB)
Data (DT)
space
Stores readable/writable data and accesses
the control register/data register for built-in/
external peripheral components.
00H
Stack (SP)
space
Area used for PUSH/POP instructions and
stack accesses for storing interrupt registers.
Use SSB if the stack flag (S in CCR) within
the condition register is set to "1", or SSB if
set to "0".
User stack bank register
(USB)
System stack bank register
(SSB) (*1)
Additional bank register
(ADB)
Additional
(AD) space
Stores data that cannot be fully
accommodated in the data (DT) space.
00H
00H
00H
*1: SSB is used always for stacks if an interrupt occurs.
Figure 2.4-4 "Physical address of each bank register" shows the relationship between the
division of memory space into banks and each register. For further information, refer to Section
2.7.6 "Bank Register (PCB, DTB, USB, SSB, ADB)".
29
CHAPTER 2 CPU
Figure 2.4-4 Physical address of each bank register
FFFFFF H
FF0000 H
Physical address
0FFFFF H
0F0000H
0DFFFFH
0D0000 H
Program
space
Additional
space
User stack
space
FFH : PCB (Program bank register)
0FH : ADB (Additional bank register)
0DH : USB (User stack bank register)
0BFFFF H
Data space
0B0000 H
07FFFF H
070000H
0BH : DTB (Data bank register)
System stack
space
07H : SSB (System stack bank register)
000000H
■ Bank Addressing and Default Space
In order to improve the efficiency of instruction code processing, a default address space is
defined for each addressing scheme, as shown in Table 2.4-2 "Addressing and default space".
To use a space other than the default space, specify the prefix code corresponding to the bank
at the beginning of the instruction; this enables accessing an arbitrary bank space
corresponding to the prefix code. For detailed information about the prefix code, refer to "2.9
Prefix Code."
Table 2.4-2 Addressing and default space
Default space
Addressing
Program space
PC indirect, program access, branch system
Data space
Addressing using @RW0, @RW1, @RW4 and @RW5, @A, addr16, dir
Stack space
Addressing using PUSHW, POPW, @RW3 and @RW7
Additional space
Addressing using @RW2 and @RW6
30
2.5 Allocation of Multiple-Byte Data in the Memory
2.5
Allocation of Multiple-Byte Data in the Memory
Multiple-byte data is written to memory sequentially starting from the lower address in
sequence. For 32-bit data, first the lower 16 bits are transferred, then the upper 16 bits.
If a reset signal is input immediately after writing the lower part of the data, the upper
part of the data cannot be written.
■ Allocating multiple-byte data in RAM
Figure 2.5-1 "Allocation of multiple-byte data in RAM" shows the placement of multiple-byte data
in memory. The lower 8 bits of a data item are stored at address n, then address n+1, address
n+2, address n+3, etc.
Figure 2.5-1 Allocation of multiple-byte data in RAM
MSB
H
LSB
01010101B 11001100B 11111111B 00010100B
01010101B
11001100B
11111111B
Address n
00010100B
L
MSB: Most Significant Bit
LSB: Least Significant Bit
■ Allocation of Multiple Byte Length Operand
Figure 2.5-2 "Allocation of multiple-byte operands" shows the placement of a multiple-byte
operand in memory.
Figure 2.5-2 Allocation of multiple-byte operands
JMPP 123456H
H
JMPP
1 2 3 4 5 6H
12H
34H
56H
Address n
63H
L
31
CHAPTER 2 CPU
■ Allocation of Multiple-Byte Data on the Stack
Figure 2.5-3 "Allocation of multiple-byte data on the stack" shows the allocation of multiple-byte
data on the stack.
Figure 2.5-3 Allocation of multiple-byte data on the stack
PUSHW RW1, RW3
H
PUSHW
RW1,
RW3
(35A4 H)
(6DF0H)
SP
6DH
F0H
35H
A4H
Address n
L
RW1: 35A4H
RW3: 6DF0H
*: Stack state after PUSH instruction is executed
■ Accessing Multiple-Byte Data
Basically, all accesses are executed within the current bank, and the next multi-byte access
instruction after the address FFFFH has been accessed will access the address 0000H in the
same bank. Figure 2.5-4 "Example of executing a multiple-byte data access instruction" shows
an example for the execution of an multiple-byte data access instruction.
Figure 2.5-4 Example of executing a multiple-byte data access instruction
H
AL before execution
80FFFFH
23H
L
32
??
01H
.
.
.
800000H
??
MOVW A, 080FFFFH
AL after execution
23H
01H
2.6 Registers
2.6
Registers
The F2MC-16LX registers are roughly divided into two types: CPU-internal dedicated
registers, and general-purpose registers in the built-in RAM.
■ Dedicated Register and General-Purpose Registers
Dedicated registers consist of dedicated hardware in the CPU and their use is limited by the
CPU architecture. General-purpose registers are allocated in the RAM within the same CPU
address space. In addition to accessing without address specification, in the same way as a
dedicated register, the use of these registers may be specified by the user in the same way as
for normal memory. Figure 2.6-1 "Dedicated registers and general-purpose registers" shows the
allocation of the dedicated registers and the general-purpose registers in the device.
Figure 2.6-1 Dedicated registers and general-purpose registers
CPU
RAM
RAM
Dedicated registers
General purpose
register
Accumulator
User stack pointer
Processor status
Program counter
Direct page register
Program bank register
Internal bus
System stack pointer
Data bank register
User stack bank register
System stack bank register
Additional data bank register
33
CHAPTER 2 CPU
2.7
Dedicated Registers
The eleven types of dedicated registers in the CPU are listed below.
• Accumulator (A)
• User stack pointer (USP)
• System stack pointer (SSP)
• Processor status (PS)
• Program counter (PC)
• Direct page register (DPR)
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional data bank register (ADB)
■ Configuration of Dedicated Registers
Figure 2.7-1 "Configuration of dedicated registers" shows the configuration of the dedicated
registers, and Table 2.7-1 "Initial value of dedicated registers" shows the initial values of the
dedicated registers.
Figure 2.7-1 Configuration of dedicated registers
AH
AL
: Accumulator (A)
Two 16-bit registers used for storing operation results.
Alternatively, a single 32-bit register if accessed consecutively.
USP
: User stack pointer (USP)
16-bit pointer indicating a user stack address.
SSP
: System stack pointer (SSP)
16-bit pointer indicating a system stack address.
PS
: Processor status (PS)
16-bit register indicating the system status.
PC
: Program counter (PC)
16-bit register indicating the storage location of the current instruction.
DPR : Direct page register (DPR)
8-bit register specifying bits 8 to 15 of an operand address when
abbreviated direct addressing is used.
PCB : Program bank register (PCB)
8-bit register indicating the program space.
DTB : Data bank register (DTB)
8-bit register indicating the data space.
USB : User stack bank register (USB)
8-bit register indicating the user stack space.
SSB : System stack bank register (SSB)
8-bit register indicating the system stack space.
ADB : Additional data bank register (ADB)
8 bits
8-bit register indicating the additional space.
16 bits
32 bits
34
2.7 Dedicated Registers
Table 2.7-1 Initial value of dedicated registers
Dedicated registers
Initial value
Accumulator (A)
Unspecified
User stack pointer (USP)
Unspecified
System stack pointer (SSP)
Unspecified
Processor status (PS)
bit15
0
Program counter (PC)
Direct page register (DPR)
Program bank register (PCB)
bit13 bit12
bit8 bit7
ILM
PS
0
bit0
CCR
RP
0
0
0
0
0
0
0
1
x
x
x
x
x
Value stored in the reset vector (contents of address FFFFDCH and
FFFFDDH)
01H
Value stored in the reset vector (contents of address FFFFDEH)
Data bank register (DTB)
00H
User stack bank register (USB)
00H
System stack bank register (SSB)
00H
Additional data bank register (ADB)
00H
-: Undefined
x: Unspecified value
Note:
The initial values above are used for controlling devices. Different values are to be used for
ICEs (such as an emulator.)
35
CHAPTER 2 CPU
2.7.1
Accumulator (A)
The accumulator (A) consists of two 16-bit registers (AH and AL) to temporarily store
operation results or other data items.
The A register is used as a 32-/16-/8-bit register, for the purpose of executing a variety
of operations between memory and other registers, or between AH and AL registers. If
data of less than word length is transferred to the AL register, data in the AL register
before transfer is automatically transferred to the AH register by the data save function
(some instructions do not save partial data).
■ Accumulator (A)
❍ Data transfer to the accumulator
The accumulator is used to handle 32-bit (long word), 16-bit (word) and 8-bit (byte) data. There
are exceptions in which it is also used for 4-bit data transfer instructions (MOVN), but in these
cases, the explanation of 8-bit data handling applies as well.
•
AH and AL registers are coupled for handling 32-bit data.
•
Only the AL register is used for 16-bit or 8-bit data.
•
If data of less than byte length is transferred to the AL register, it is stored in the AL register
as 16-bit data by code extension or zero extension. Data in the AL register may also be
handled as either word or byte data.
Data transfer to the accumulator is shown in Figure 2.7-2 "Data transfer to accumulator". An
example of the actual transfer operation is shown in Figure 2.7-3 "Example of accumulator (A)
transfers between AL and AH (8-bit immediate data, zero extension)" to Figure 2.7-6 "Example
of accumulator (A) transfers between AL and AH (16 bit, register indirect)".
36
2.7 Dedicated Registers
Figure 2.7-2 Data transfer to accumulator
32 bit
AH
AL
32-bit data transfer
Data
transfer
Data
transfer
AH
AL
Data migration
16-bit data transfer
Data
transfer
AH
AL
Data migration
8-bit data transfer
00H or FFH* (zero
extension or code
extension)
Data
transfer
*: 000H or FFFH for 4-bit transfer instruction.
❍ Byte-based arithmetic operations of the accumulator
When executing a byte-based arithmetic operation instruction on the contents of the AL register,
the contents that the upper 8 bits of the AL register have before the operation are ignored, and
the upper 8 bits of operation result are set all zeroes.
❍ Initial value of accumulator
The initial value after a reset is unspecified.
Figure 2.7-3 Example of accumulator (A) transfers between AL and AH (8-bit immediate data, zero
extension)
MOV
A, 3000H
(Instruction to store the contents of address 3000H in the AL register)
MSB
Before execution
AH
AL
XXXXH
2456H
DTB
After execution
2456H
0088H
B53000H
Memory space
77H
LSB
88H
B5H
X: Unspecified
MSB: Most Significant Bit
LSB: Loast Significant Bit
DTB: Data bank register
37
CHAPTER 2 CPU
Figure 2.7-4 Example of accumulator (A) transfers between AL and AH (8-bit immediate data, code
extension)
(Instruction to read long-word data from the address calculated
as RW1 content + 8-bit offset, then writing the result to the A register
MOVW A, 3000H
Memory space
MSB
Before execution
AH
AL
XXXXH
2456H
2456H
77H
88H
B5H
DTB
After execution
B53000H
LSB
X: Unspecified
MSB: Most Significant Bit
LSB: Least Significant Bit
DTB: Data bank register
7788H
Figure 2.7-5 Example of transferring 32-bit data to the accumulator (A) (register indirect)
MOVL
(Instruction to read long-word data from the address calculated as
RW1 content + 8-bit offset, then writing the result to the A register)
A, @RW1+6
Memory space
Before execution
AH
XXXXH
AL
XXXXH
8F74H
2B52H
LSB
A6153EH
8FH
2BH
74H
52H
RW1
15H
38H
A61540H
A6H
DTB
After execution
MSB
X : Unspecified
MSB: Most Significant Bit
LSB: Least Significant Bit
DTB : Data bank register
Figure 2.7-6 Example of accumulator (A) transfers between AL and AH (16 bit, register indirect)
MOVW
A, @RW1+6
AH
Before execution
XXXXH
AL
1234H
DTB
After execution
(Instruction to read word data from the address calculated
as RW1 content + 8-bit offset, then writing the result to
the A register)
Memory space
MSB
LSB
1234H
2B52H
A6153EH
8FH
2BH
74H
52H
RW1
15H
38H
A61540H
A6H
X: Unspecified
MSB: Most Significant Bit
LSB: Least Significant Bit
DTB: Data bank register
38
2.7 Dedicated Registers
2.7.2
Stack Pointers (USP, SSP)
There are two types of stack pointers in the MB90420G/425G series: a user stack
pointer (USP) and a system stack pointer (SSP). These are registers used to indicate
the destination address in memory for data relocation or recovery when executing the
PUSH instruction, POP instruction, or subroutines. The upper 8 bits of the stack
address are specified by either the user stack bank register (USB) or the system stack
bank register (SSB).
If the S flag in the condition code register (CCR) is set to "0", the USP and USB
registers become enabled. If the S flag set to "1", SSP and SSB registers are enabled.
■ Stack Selection
The F2MC-16LX uses two types of stacks: system stacks and user stacks. The stack address is
specified with an S flag in the processor status register (PS: CCR), as shown in Table 2.7-2
"Specifying the stack address".
Table 2.7-2 Specifying the stack address
Stack address
S flag
Upper 8 bits
Lower 16 bits
0
User stack bank register (USB)
User stack pointer (USP)
1
System stack bank register (SSB)
System stack pointer (SSP)
: initial value
Resetting initializes the S flag to "1", after which the system stack is used by default. Normally,
stack operations in an interrupt routine use the system stack, and in stack operations other than
operation by an interrupt routine, the user stack is used. Especially in cases when stack space
does not need to be divided, use the system stack only.
Note:
Once an interrupt is accepted, the S flag is set to "1". Thus, the system stack is always used
in case of an interrupt.
Figure 2.7-7 "Stack operation instructions and stack pointers" shows an example of stack
operations when the system stack is used.
39
CHAPTER 2 CPU
Figure 2.7-7 Stack operation instructions and stack pointers
PUSHW A if the S flag is set to 0
Before execution AL
USB C6H
USP F328H
0
SSB 56H
SSP 1234H
A624H
USB C6H
USP F326H
S flag 0
SSB 56H
SSP 1234H
A624H
S flag
After execution
MSB
AL
C6F326H
LSB
XXH
XXH
User stack is used because
the S flag is set to 0
C6F326H
A6H
24H
PUSHW A if the S flag is set to 1.
MSB
A624H
USB C6H
USP F328H
S flag 1
SSB 56H
SSP 1234H
A624H
USB C6H
USP F328H
S flag 1
SSB 56H
SSP 1232H
Before execution AL
After execution
AL
LSB
561232 H
XXH
XXH
561232 H
A6H
24H
The system stack is used because
the S flag is set to 1
X: Unspecified
MSB: Most Significant Bit
LSB: Least Significant Bit
Notes:
In ordinary cases, set the stack pointer to an even address value. If it is set to an odd
address, word accesses are performed in two steps, which degrades processing efficiency.
The initial value after resetting USP register and SSP register is unspecified.
■ System Stack Pointer (SSP)
Using the system stack pointer (SSP) requires setting the S flag in the condition code register
(CCR) within the processor status register (PS) to "1". In this case, the upper 8 bits of the
address used in the stack operation are indicated in the system stack bank register (SSB).
■ User Stack Pointer (USP)
Using the user stack pointer (USP) requires setting the S flag in the condition code register
(CCR) within the processor status register (PS) to "0". In this case, the upper 8 bits of the
address used in the stack operation are indicated in the user stack bank register (USB).
40
2.7 Dedicated Registers
2.7.3
Processor Status (PS)
The processor status register (PS) consists of CPU control bits and a variety of bits
indicating the CPU state.
■ Bit configuration of processor status register (PS)
The PS register consists of three registers listed below.
•
Interrupt level mask register (ILM)
•
Register bank pointer (RP)
•
Condition code register (CCR)
Figure 2.7-8 "Bit configuration of processor status register (PS)" shows the bit configuration of
the processor status register (PS).
Figure 2.7-8 Bit configuration of processor status register (PS)
ILM
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PS
Initial value
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
0 0 0 0
0 0 0 0
I
S
T
N
Z
V
C
0
1
X
X
X
X
X
: Undefined
x: Unspecified value
❍ Interrupt level mask register (ILM)
Indicates the interrupt level CPU currently accepts. It is compared with the interrupt level setting
bit (ICR: IL0-IL2) in the interrupt control register, which is set corresponding to an interrupt
request provided by each peripheral function.
❍ Register bank pointer (RP)
This pointer is used to specify the start address of the memory block (register bank) that is used
as a general-purpose register in the RAM area.
The general-purpose register consists of 32 banks in total, and a bank can be specified by
setting RP to a value of 0 to 31.
❍ Condition code register (CCR)
This register consists of a variety of flags, which are set (1) or reset (0) in accordance with the
execution result of instructions and by interrupt generation.
41
CHAPTER 2 CPU
■ Condition Code Register (PS: CCR)
This register consists of 8 bits including bits representing operation result and the contents of
data transfers as well as bits controlling the acceptance of interrupt requests.
Figure 2.7-9 "Bit configuration of condition code register (CCR)" shows the bit configuration of
the CCR register. For the status of the condition code register (CCR) after an instruction is
executed, refer to the "Programming Manual."
Figure 2.7-9 Bit configuration of condition code register (CCR)
ILM
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PS
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
I
S
T
N
Z
V
C
0
1
X
X
X
X
X
Initial value of CCR
-01XXXXXB
Interrupt enable flag
Stack flag
Sticky bit flag
Negative flag
Zero flag
Overflow flag
Carry flag
X
: Undefined
: Unspecified value
❍ Interrupt enable flag (I)
For interrupt requests other than software interrupts, the following applies: if the I flag is set to
"1", the interrupt is permitted, and if the flag is set to "0", the interrupt is prohibited. This flag is
cleared by reset.
❍ Stack flag (S)
This flag indicates that a pointer is used for a stack operation. If the S flag is set to "0", the user
stack pointer (USP) is enabled, if it is set to "1", the system stack pointer (SSP) is enabled. This
flag is set when an interrupt is accepted or reset is performed.
❍ Sticky bit flag (T)
Executing a logical right shift instruction or arithmetic right shift instruction sets this flag to 1 if a
least one "1" was shifted out over the carry bit.; otherwise, this flag is set to "0". This flag is also
set to "0" if the shifting distance is zero.
❍ Negative flag (N)
Set to 1 if the highest bit of an operation result is "1". Otherwise, cleared to 0.
❍ Zero flag (Z)
Set to 1 if all bits of an operation result are zeroes. Otherwise, cleared to 0.
❍ Overflow flag (V)
Set to 1 if a signed-value overflow occurs when an operation is executed. Otherwise, cleared to
0.
42
2.7 Dedicated Registers
Note:
Bit 7 is an undefined bit. The read value of this bit is not specified. Writing to this bit has no
effect.
❍ Carry flag (C)
Set to 1 if, when an operation is executed, either carry-up from the highest bit or carry-down to
the highest bit occurs. Otherwise, cleared to 0.
■ Register Bank Pointer (PS: RP)
Used to indicate the start address in the general-purpose register bank currently used. This
pointer is used to convert the actual address for general-purpose register addressing.
Figure 2.7-10 "Bit configuration of register bank pointer (RP)" shows the bit configuration for the
register bank pointer (RP).
Figure 2.7-10 Bit configuration of register bank pointer (RP)
ILM
RP
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PS
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
I
S
T
N
Z
V
C
Initial value
of RP
00000 B
■ General-Purpose Register Area and Register Bank Pointer
The register bank pointer is a pointer used to indicate the relationship between the generalpurpose registers in the F2MC-16LX and the internal RAM addresses. For the relationship
between the RP content and the actual address it indicates, refer to the conversion rule in
Figure 2.7-11 "Physical address conversion rule for general purpose register area".
Figure 2.7-11 Physical address conversion rule for general purpose register area
Conversion formula {000180H + (RP) x 10H}
In case of RP = 10H
000370 H
Register bank 31
:
:
000280 H
Register bank 16
:
:
00018 0 H
Register bank 0
•
RP can have a value from 00H to 1FH. Thus, the start address of register banks can be set to
a value in the range 000180H to 00037FH.
•
There are assembler instructions for immediate data transfer of 8 bit data to RP, but only the
lower 5 bits are used in actual operation.
•
The initial value of the RP register after a reset is "00H".
43
CHAPTER 2 CPU
■ Interrupt Level Mask Register (PS: ILM)
The interrupt level mask register (ILM) is a 3-bit register used to indicate the interrupt level the
CPU can accept.
Figure 2.7-12 "Bit configuration of interrupt level mask register (ILM)" shows the bit configuration
of the interrupt level mask register (ILM). For detailed information of the interrupt, refer to
"CHAPTER 3: INTERRUPTS."
Figure 2.7-12 Bit configuration of interrupt level mask register (ILM)
RP
ILM
CCR
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PS
ILM2 ILM1 ILM0 B4 B3 B2 B1 B0
I
S
T
N
Z
V
C
Initial value
of ILM
000B
The interrupt level mask register (ILM) indicates the interrupt level the CPU currently accepts,
which is compared with the values of the bits IL0 to IL2 bit in the interrupt control register
(ICR00 to ICR15) that are set in accordance with the interrupt request of each peripheral
function. Only if the interrupt enable flag indicates that interrupts are enabled (CCR: I=1) and
the interrupt request has a value lower than indicated in these bits (the interrupt level) will the
CPU perform interrupt processing.
•
If the interrupt is accepted, the interrupt level value is retained in the interrupt level mask
register (ILM), and any subsequent interrupt that has the same or a lower level is not
accepted.
•
The interrupt level mask register (ILM) is initialized to 0 by a reset. After that, the interrupt
level will be set to the highest level, indicating interrupt prohibit state.
•
There are assembler instructions for immediate transfer of 8-bit data to the interrupt level
mask register (ILM), but only the lower 3 bits will be used during the actual operation.
Table 2.7-3 Interrupt level mask register (ILM) and interrupt level priority
44
ILM2
ILM1
ILM0
Interrupt level
Interrupt level priority
0
0
0
0
High (interrupt prohibited)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Low
2.7 Dedicated Registers
2.7.4
Program Counter (PC)
The program counter (PC) is a 16-bit counter that indicates the lower 16-bits of the
address in memory at which the instruction code the CPU will execute next is stored.
■ Program counter (PC)
The address at which the instruction code that will be executed next by the CPU executed is
stored consists of the upper 8 bits, specified by the program bank register (PCB), and the lower
16 bits specified by the program counter (PC). The actually used address in memory is created
by combining these two parts to 24 bits, as shown in Figure 2.7-13 "Program counter (PC)". The
contents of the PC is updated by a condition branch instruction, subroutine call instruction,
interrupts or resets. The PC is also used as the base pointer for reading an operand.
Figure 2.7-13 Program counter (PC)
Upper 8 bits
PCB FEH
Lower 16 bits
PC ABCDH
F E A B C D H Next instruction executed
Note:
Neither PC nor PCB can be directly rewritten by a program (e.g. by a MOV PC, #FF
instruction).
45
CHAPTER 2 CPU
2.7.5
Direct Page Register (DPR)
The direct page register (DPR) is an 8-bit register used to specify bits 8 to 15 (addr8 to
addr15) at the operand address when an instruction applying the abbreviated direct
addressing scheme is executed.
■ Direct page register (DPR)
The DPR is an 8-bit register used to specify bits 8 to 15 (addr8 to addr15) in the operand
address when an instruction of the abbreviated direct addressing scheme is executed as shown
in Figure 2.7-14 "Generating a physical address from the direct page register (DPR)". The DPR
has a length of eight bit, and is initialized to "01H" at resetting. Reading and writing the register
by instructions is allowed.
Figure 2.7-14 Generating a physical address from the direct page register (DPR)
DTB register
AAAAAAAA
DPR register
BBBBBBBB
MSB
24bit
physical address
AAAAAAAA
bit24
bit16
Direct address in instruction
CCCCCCCC
LSB
BBBBBBBB
bit15
bit8
CCCCCCCC
bit7
bit0
MSB: Most Significant Bit
LSB: Least Significant Bit
An example of setting and accessing the direct page register (DPR) is shown in Figure 2.7-15
"Example of setting and accessing the direct page register (DPR)".
Figure 2.7-15 Example of setting and accessing the direct page register (DPR)
MOV S:56H, #5AH
Execution result of instruction
Upper 8bit Lower 8bit
DTB register
12H
DPR register
34H
123458 H
123456 H
MSB: Most Significant Bit
LSB: Least Significant Bit
46
5AH
123454 H
MSB
LSB
2.7 Dedicated Registers
2.7.6
Bank Registers (PCB, DTB, USB, SSB, ADB)
The bank registers are used to specify the upper 8-bit address for bank scheme
addressing. They consist of the five registers listed below.
• Program bank register (PCB)
• Data bank register (DTB)
• User stack bank register (USB)
• System stack bank register (SSB)
• Additional bank register (ADB)
Each bank register indicates a memory bank in which program space, data space, user
stack space, system stack space, or additional space are allocated.
■ Bank Register (PCB, DTB, USB, SSB, ADB)
❍ Program bank register (PCB)
The PCB is a bank register that is used to specify a program (PC) space. The PCB is rewritten if
a JMPP, CALLP, RETP, or RETI instruction which branches over the entire 16 MB space are
executed, a software interrupt instruction is executed, a hardware interrupt occurs or an
exception is generated.
❍ Data bank register (DTB)
The DTB is a bank register used to specify a data (DT) space.
❍ User stack bank register (USB)/system stack bank register (SSB)
USB and SSB are bank registers used to specify stack (SP) space. Whether USB or SSB is
used depends on the value off the S flag in the processor status register (PS: CCR). For
detailed information, refer to "2.7.2 Stack Pointers (USP, SSP).
❍ Additional bank register (ADB)
The ADB is a bank register used to specify an additional (AD) space.
❍ Setting each bank and data accessing
All of the bank registers have a length of bytes. PCB is initialized to "FFH" by resetting,
otherwise cleared to "00H". The PCB can be read but not written. Reading and writing is allowed
for all bank registers other than the PCB.
Notes:
The MB90420G/425G series supports only the device built-in memory space.
For information on the operations of each register, refer to "2.4.2 Addressing with bank
scheme."
47
CHAPTER 2 CPU
2.8
General-Purpose Register
The general-purpose register is a memory block located in RAM at the addresses
000180H to 00037FH, where 16 bits x 8 are allocated per bank. It may be used as either
general-purpose eight-bit register (byte register R0 to R7), 16-bit register (word register
RW0 to RW7) or 32-bit register (long word register RL0 to RL7).
The general-purpose register allows high-speed RAM accesses via shorter
instructions. It is allocated in blocks within the register bank, which facilitates
protection of register contents and division in units of functions.
When used as a long word register, it can be used as a linear pointer for direct
accessing the entire space.
■ Configuration of General-Purpose Register
The general-purpose register contains 32 banks in total which are allocated in RAM at the
addresses 000180H to 00037FH. The register bank pointer (RP) specifies which bank to use.
Similarly, the bank currently in use can be identified by reading RP. The start address of each
bank can be determined from RP as follows:
Heading address of general-purpose register = 000180H + RP × 10H
Figure 2.8-1 "Allocation and configuration of general-purpose register bank in the memory
space" shows the allocation and configuration of the general-purpose register bank within the
memory space.
Figure 2.8-1 Allocation and configuration of general-purpose register bank in the memory space
Built-in RAM
000380H
000370H
000360H
0002E0H
0002D0H
0002C0H
0002B0H
0001B0H
0001A0H
000190H
000180H
:
Register bank 31
Byte
address
Register bank 30
02CEH
R6
R7
02CFH RW7
:
:
:
02CCH
02CDH RW6
Register bank 21
02C8H
Register bank 20
02C6H
R4
R5
R2
R3
R0
R1
RW3
Register bank 19
02C4H
:
:
:
:
:
02C2H
Register bank 2
Register bank 1
Register bank 0
:
02CAH
RP
14H
02C0H
LSB
Byte
address
RW2
RW1
RW0
16bit
02CBH RW5
RL2
02C9H RW4
02C7H
RL1
02C5H
02C3H
02C1H
RL0
MSB
Conversion formula: [000180H + RP x 10H]
R0 - R7: Byte register
RW0 - RW7: Word register
RL0 - RL3: Long word register
MSB: Most Significant Bit
LSB: Least Significant Bit
Note:
The register bank pointer (RP) is initialized to "00H" after a reset.
48
RL3
2.8 General-Purpose Register
■ Register Bank
The register bank consist of general-purpose registers (byte register R0 to R7, word register
RW0 to RW7, long word register RL0 to RL3) used for a variety of operations and as pointers.
The long word register is used as a linear pointer for directly accessing the entire memory
space. The contents of the registers in the register bank is not initialized by resetting, as for the
normal RAM, and registers retain their state before the reset. The contents of the registers at
the time of power-on is unspecified. Table 2.8-1 "Typical functions of general-purpose register"
shows typical uses of the general-purpose registers.
Table 2.8-1 Typical functions of general-purpose register
Register name
Function
R0 - R7
Used as operand for various instructions
Note:
R0 is also used as a counter for barrel shift and normalize
instructions.
RW0 - RW7
Used as a pointer.
Used as an operand of various instructions.
Note:
RW0 is also used as a counter for string instructions.
RL0 - RL3
Used as a long pointer.
Used as an operand of various instructions.
49
CHAPTER 2 CPU
2.9
Prefix Codes
Placing a prefix code before an instruction partially changes the operation performed
for the instruction. The MB90420G/425G series has three types of prefix codes:
• bank select prefix (PCB, DTB, ADB, SPB)
• common register bank prefix (CMR)
• flag change suppress prefix (NCC)
■ Prefix Code
❍ Bank select prefix (PCB, DTB, ADB, SPB)
Placing the bank select prefix before an instruction selects the memory space accessed by the
instruction, irrespective of the addressing scheme.
❍ Common register bank prefix (CMR)
Placing the common register bank prefix before an instruction for accessing the register bank
changes a register access of the instruction to the common bank located at the addresses
000180H to 00018FH irrespective of the current register bank pointer (RP) value. (register bank
selected when RPÅÅ0).
❍ Flag change suppression prefix (NCC)
Placing the prefix code for the flag change suppression flag before an instruction will suppress
flag changes caused by executing the instruction.
■ Bank Select Prefix (PCB, DTB, ADB, SPB)
The memory space used for data access is specified individually for each addressing scheme.
Placing the bank select prefix before an instruction allows selecting the memory space
accessed by the instruction independently of the addressing scheme. The bank select prefixes
and the corresponding memory spaces are shown in Table 2.9-1 "Bank select prefix".
Table 2.9-1 Bank select prefix
Bank select prefix
Space selected
PCB
Program space
DTB
Data space
ADB
Additional space
SPB
The user stack space is used if the S flag in the condition code
register (CCR) is set to "0". The system stack space is used if the
flag is set to "1".
If the bank select prefix is used, some instructions may execute irregular operations. Table 2.9-2
"Instructions not affected by bank select prefix" shows instructions not affected by the bank
select prefix and Table 2.9-3 "Instructions requiring caution when the bank select prefix is used"
shows instructions that require caution when they are used with bank select prefix.
50
2.9 Prefix Codes
Table 2.9-2 Instructions not affected by bank select prefix
Instruction type
String instruction
Instruction
Effect of bank select prefix
MOVS
MOVSW
SCEQ
SCWEQ
FILS
FILSW
Stack operation
instruction
PUSHW
POPW
The user stack bank (USB) is used if
the S flag is set to 0. The system stack
bank (SSB) is used if the flag is set to
1, irrespective of whether the prefix is
present
I/O access
instruction
MOV A, io
MOVX A, io
The I/O space (Address 000000H to
0000FFH) is accessed irrespective of
whether the prefix is present
Interrupt recovery
instruction
MOVW A, io
MOV io, A
MOVW io, A
MOV io, #imm8
MOVW io, #imm16
MOVB A, io:bp
MOVB io:bp, A
SETB io:bp
CLRB io:bp
BBC io:bp, rel
BBS io:bp, rel
WBTC io, bp
WBTS io:bp
RETI
The bank register specified by the
operand is used irrespective of
whether a prefix is present.
The system stack bank (SSB) is used
irrespective of whether the prefix is
present.
Table 2.9-3 Instructions requiring caution when the bank select prefix is used
Instruction type
flag change instruction
Instruction
AND CCR, #imm8
Description
Prefix affects the next instruction.
OR CCR, #imm8
ILM setting instruction
PS recovery instruction
MOV ILM, #imm8
Prefix affects the next instruction.
POPW PS
Do not use a bank select prefix to the
PS recovery instruction.
51
CHAPTER 2 CPU
■ Common Register Bank Prefix (CMR)
To facilitate the data exchange between multiple tasks, a method must be provided for easily
accessing the same register bank regardless of the register bank pointer (RP). For this purpose,
the F2MC-16LX series provides a register bank that can be commonly used for each task, called
the common bank. The common bank is located in the area from address 000180H to 00018FH.
Placing the common register bank prefix (CMR) before an instruction for accessing a register
bank allows changing register access by the instruction to the common bank located at address
000180H to 00018FH (i.e. the register bank selected when RP=0) irrespective of the current
register bank pointer (RP) value. However, the instructions listed in Table 2.9-4 "Instructions
requiring caution when the common register bank prefix (CMR) is used" should be handled with
caution.
Table 2.9-4 Instructions requiring caution when the common register bank prefix (CMR) is used
Instruction type
String instruction
Instruction
Description
Do not add the CMR prefix to string
instructions.
MOVS
MOVSW
SCEQ
SCWEQ
FILS
FILSW
Flag change instruction
AND CCR, #imm8
OR CCR, #imm8
PS recovery instruction
POPW PS
Prefix affects the next instruction.
ILM setting instruction
MOV ILM, #imm8
Prefix affects the next instruction.
52
Prefix affects the next instruction.
2.9 Prefix Codes
■ Flag Change Suppression Prefix (NCC)
The flag change suppression prefix (NCC) is used to suppress unnecessary flag changes.
Placing an NCC prefix before the instruction for which you want to suppress the flag change will
prevent a flag change due to execution of the instruction. Changes can be suppressed for the
flags T, N, Z, V and C. The instructions in Table 2.9-5 "Instructions requiring caution when the
flag change suppression prefix (NCC) is used" should be handled with caution.
Table 2.9-5 Instructions requiring caution when the flag change suppression prefix (NCC) is used
Instruction type
String instruction
Instruction
MOVS
MOVSW
SCEQ
SCWEQ
FILS
FILSW
Description
Do not add the NCC prefix to string
instructions.
Flag change instruction
AND CCR, #imm8
OR CCR, #imm8
The condition code register (CCR) changes
in accordance with the instruction
specification irrespective of whether the
prefix is present. The prefix affects the next
instruction.
PS recovery instruction
POPW PS
The condition code register (CCR) changes
in accordance with the instruction
specification irrespective of whether the
prefix is present. The prefix affects the next
instruction.
ILM setting instruction
MOV ILM, #imm8
The prefix affects the next instruction.
Interrupt instruction
Interrupt recovery instruction
INT #vct8
INT9
INT adder16
INTP addr24
RETI
Contextual switch instruction
JCTX @A
The condition code register (CCR) changes
in accordance with the instruction
specification irrespective of whether the
prefix is present.
The condition code register (CCR) changes
in accordance with the instruction
specification irrespective of whether the
prefix is present.
53
CHAPTER 2 CPU
■ Restrictions on Prefix Codes
The three restrictions listed below apply when using prefix codes.
•
No interrupt/hold request is accepted when a prefix code or an interrupt/hold suppress
instruction is used.
•
The effect of a prefix code is delayed if the prefix is placed before an interrupt/hold
instruction.
•
If conflicting prefix codes are placed in sequence, only the last one is effective.
Table 2.9-6 "Prefix code and interrupt/hold suppress instructions" shows restrictions applying to
prefix codes and interrupt/hold suppress instructions.
Table 2.9-6 Prefix code and interrupt/hold suppress instructions
Prefix code
Instructions that will accept
neither interrupt nor hold
request
PCB
DTB
ADB
SPB
CMR
NCC
Interrupt/hold suppress instruction
(instructions that delay the effect of the prefix code)
MOV LM, #imm8
OR CCR, #imm8
AND CCR, #imm8
POPW PS
❍ Suppressing interrupt/hold
When, as shown in Figure 2.9-1 "Suppressing interrupt/hold", prefix code or interrupt/hold
instruction are executed, any generated interrupt hold requests are not accepted. In such cases,
interrupt/hold processing is not executed until another instruction has been executed after the
one with the prefix code respectively after the interrupt/hold suppress instruction.
Figure 2.9-1 Suppressing interrupt/hold
Interrupt/hold suppress instruction
(a)
(a) Normal instruction
Interrupt request generated
54
Interrupt accepted
2.9 Prefix Codes
❍ Delayed effect of prefix codes
If, as shown in Figure 2.9-2 "Interrupt/hold suppress instruction and prefix code", a prefix code is
placed before an interrupt/hold suppress instruction, the prefix code becomes effective starting
with the first instruction after the interrupt/hold suppress instruction.
Figure 2.9-2 Interrupt/hold suppress instruction and prefix code
Interrupt/hold suppress instruction
MOV A, FFH
NCC
MOV ILM,#imm8
ADD A,01H
CCR: XXX10XXB
CCR: XXX10XXB
CCR will not change because of NCC
❍ Continuous prefix codes
If, as shown in Figure 2.9-3 "Continuous prefix codes", conflicting prefix codes (PCB, ADB,
DTB, SPB) are specified in sequence, only the last one is effective.
Figure 2.9-3 Continuous prefix codes
Prefix code
ADB
DTB
PCB
ADD A,01H
The effective prefix code is PCB.
55
CHAPTER 2 CPU
56
CHAPTER 3
INTERRUPTS
This chapter describes the relationships between interrupts and the extended
intelligent I/O service (EI2OS).
3.1 "Outline of Interrupts"
3.2 "Interrupt Sources and Interrupt Vector"
3.3 "Interrupt Control Registers and Peripheral Functions"
3.4 "Hardware Interrupts"
3.5 "Software Interrupts"
3.6 "Interrupts From the Extended Intelligent I/O Service (EI2OS)"
3.7 "Exception Processing Interrupts when Executing Undefined Instructions"
3.8 "Stack Operations of Interrupt Handling"
3.9 "Sample Program for Interrupt Handling"
57
CHAPTER 3 INTERRUPTS
3.1
Outline of Interrupts
F2MC-16LX has four types of interrupt functions for interrupting processing currently
being performed and transfer control to a separately defined program if an event
occurs.
• Hardware interrupts
• Software interrupts
• Interrupts from the extended intelligent I/O service (EI2OS)
• Exception handling
■ Types of Interrupts and Corresponding Functions
❍ Hardware interrupts
Transfers control to a user-defined interrupt handling program in response to an interrupt
request from a peripheral function.
❍ Software interrupts
Transfers control to a user-defined interrupt-handling program by executing a software interruptdedicated instruction (e.g., INT instruction).
❍ Interrupts from the extended intelligent I/O service (EI2OS)
EI2OS is a function for automatic data transfer between a peripheral function and memory. Data
transfer as far as previously performed by the interrupt-handling program is provided in the
same way as via DMA (direct memory access). After completion of data transfer of the specified
count, the interrupt handling program is automatically executed.
Interrupts from EI2OS are a type of hardware interrupt.
❍ Exception handling
Exception handling is basically performed in the same way as interrupt handling. If an exception
event (execution of an undefined function) is detected at the instruction boundary, the normal
course of processing is interrupted. This is equivalent to an "INT10" software interrupt
instruction.
58
3.1 Outline of Interrupts
■ Interrupt Operation
F2MC-16LX has four types of interrupt functions for starting and resuming processing, as shown
in Figure 3.1-1 "Overall operational flow of interrupt processing".
Figure 3.1-1 Overall operational flow of interrupt processing
START
Main program
YES
Valid hardware
interrupt request
String type
instruction being
executed*1
Interrupt start/processing
for resuming
NO
Is EI2OS responsible?
Reading and decoding
next instruction
YES
EI2OS
NO
YES
INT instruction?
NO
EI2OS processing
Software interrupt/
exception handling
Dedicated registers
swapped out to
system stack
Hardware interrupt
acceptance prohibited
(I=0)
Hardware
interrupt
YES
Specified
count completed?
Or, completion request
from peripheral function
issued?
Dedicated registers
swapped out to
system stack
NO
Update of CPU
interrupt handling level
(ILM)
YES
RETI instruction?
NO
Executing normal
instruction
NO
Processing
for return
from interrupt
Contents of dedicated
register returned from
system stack, control
returns to routine being
executed before interrupt
routine was called
Reading interrupt
vector to update PC
and PCB, then
branching to interrupt
routine
Iterative
string type instruction*
completed
YES
Setting pointer to next
instruction by updating
PC
*1: When a string type instruction is being executed, checks for interrupts are made in each step.
59
CHAPTER 3 INTERRUPTS
3.2
Interrupt Sources and Interrupts
F2MC-16LX has functions corresponding to 256 types of interrupt sources. There are
256 interrupt vector tables allocated starting with the highest address in memory. The
interrupt vectors are shared by all interrupts.
Software interrupts may use all of the above interrupts (INT0 to INT256), but some of
these interrupt vectors will then be shared by hardware interrupts and exception
handling interrupts. Hardware interrupts use specific interrupt vectors and have a
special interrupt control register (ICR) for each peripheral function.
■ Interrupt Vectors
Interrupt vector tables, which are referenced for interrupt handling, are allocated starting with
the highest address of the memory area (FFFC00H to FFFFFFH). The interrupt vectors for
EI2OS, exception handling, hardware interrupts, and software interrupts share the same area.
The allocation of interrupt numbers and interrupt vectors in memory is shown in Table 3.2-1 "List
of Interrupt Vectors".
Table 3.2-1 List of interrupt vectors
Software
interrupt
instruction
Vector
address L
Vector
address M
Vector
address H
Mode
data
Interru
pt No
Hardware interrupt
INT0
FFFFFCH
FFFFFDH
FFFFFEH
Unused
#0
None
:
:
:
:
:
:
:
INT7
FFFFE0H
FFFFE1H
FFFFE2H
Unused
#7
None
INT8
FFFFDCH
FFFFDDH
FFFFDEH
FFFFDFH
#8
(RESET vector)
INT9
FFFFD8H
FFFFD9H
FFFFDAH
Unused
#9
None
INT10
FFFFD4H
FFFFD5H
FFFFD6H
Unused
#10
< Exception handling >
INT11
FFFFD0H
FFFFD1H
FFFFD2H
Unused
#11
Hardware interrupt #0
INT12
FFFFCCH
FFFFCDH
FFFFCEH
Unused
#12
Hardware interrupt #1
INT13
FFFFC8H
FFFFC9H
FFFFCAH
Unused
#13
Hardware interrupt #2
INT14
FFFFC4H
FFFFC5H
FFFFC6H
Unused
#14
Hardware interrupt #3
:
:
:
:
:
:
:
INT254
FFFC04H
FFFC05H
FFFC06H
Unused
#254
None
INT255
FFFC00H
FFFC01H
FFFC02H
Unused
#255
None
Reference:
We recommend allocating also unused interrupt vectors at the addresses for exception
handling
60
3.2 Interrupt Sources and Interrupts
■ Interrupt Sources and Interrupt Vectors/Interrupt Control Registers
Table 3.2-2 "Interrupt sources and interrupt vectors/interrupt control registers" shows the
relationship between interrupt sources and the interrupt vectors/interrupt control registers
(except for software interrupts).
Table 3.2-2 Interrupt sources and interrupt vectors/interrupt control registers
Interrupt source
Use
of
EI2OS
Interrupt vector
Number
Interrupt control
register
Address
ICR
Address
Reset
N
#08
08H
FFFFDCH
−
−
INT9 instruction
N
#09
09H
FFFFD8H
−
−
Exception handling
N
#10
0AH
FFFFD4H
−
−
CAN0 RX
N
#11
0BH
FFFFD0H
ICR00
CAN0 TX/NS
N
#12
0CH
FFFFCCH
0000B0H (*1)
CAN1 RX
N
#13
0DH
FFFFC8H
ICR01
CAN1 TX/NS
N
#14
0EH
FFFFC4H
0000B1H (*1)
Input capture 0
V
#15
0FH
FFFFC0H
DTP/external interrupt or channel 0
detected
ICR02
V
#16
10H
FFFFBCH
0000B2H (*1)
Reload timer 0
V
#17
11H
FFFFB8H
ICR03
0000B3H (*1)
ICR04
0000B4H (*1)
ICR05
0000B5H (*1)
ICR06
0000B6H (*1)
ICR07
0000B7H (*1)
ICR08
0000B8H (*1)
ICR09
0000B9H (*1)
ICR10
0000BAH (*1)
DTP/external interrupt or channel 1
detected
V
#18
12H
FFFFB4H
Input capture 1
V
#19
13H
FFFFB0H
DTP/external interrupt or channel 2
detected
V
#20
14H
FFFFACH
Input capture 2
V
#21
15H
FFFFA8H
DTP/external interrupt or channel 3
detected
V
#22
16H
FFFFA4H
Input capture 3
V
#23
17H
FFFFA0H
DTP/external interrupt or channels 4/5
detected
V
#24
18H
FFFF9CH
PPG timer 0
V
#25
19H
FFFF98H
DTP/external interrupt or channels 6/7
detected
V
#26
1AH
FFFF94H
PPG timer 1
V
#27
1BH
FFFF90H
Reload timer 1
V
#28
1CH
FFFF8CH
PPG timer 2
Y
#29
1DH
FFFF88H
Real-time watch timer
N
#30
1EH
FFFF84H
Free-run timer overflow
N
#31
1FH
FFFF80H
A/D converter conversion completed
Y
#32
20H
FFFF7CH
Priority
(*2)
High
61
CHAPTER 3 INTERRUPTS
Table 3.2-2 Interrupt sources and interrupt vectors/interrupt control registers (Continued)
Interrupt source
Free-run timer cancel
Use
of
EI2OS
N
Interrupt vector
Number
#33
Address
21H
FFFF78H
Sound generator
N
#34
22H
FFFF74H
Timebase timer
N
#35
23H
FFFF70H
Watch timer (sub-clock)
N
#36
24H
FFFF6CH
UART1 receive
W
#37
25H
FFFF68H
UART1 transmit
V
#38
26H
FFFF64H
UART0 receive
W
#39
27H
FFFF60H
UART0 transmit
V
#40
28H
FFFF5CH
Flash memory status
N
#41
29H
FFFF58H
Delay interrupt generation module
N
#42
2AH
FFFF54H
Interrupt control
register
ICR
Address
ICR11
0000BBH (*1)
ICR12
0000BCH (*1)
ICR13
0000BDH (*1)
ICR14
0000BEH (*1)
ICR15
0000BFH (*1)
Priority
(*2)
Low
W: Can be used with EI2OS stop function
Y: Can be used
N: Not available
V: Available only if no interrupt sources that share ICR are used
*1: Peripheral functions that share ICR register have the same interrupt level.
When sharing ICR registers while using the extended intelligent I/O service for peripheral functions, either a normal
interrupt or an extended intelligent I/O service can be used.
If, in case of peripheral functions that share an ICR register, one of the functions specifies an extended intelligent I/O
service, the other is not allowed to use an interrupt.
*2: Priority assigned if interrupts with the same level occur.
62
3.3 Interrupt Control Registers and Peripheral Functions
3.3
Interrupt Control Registers and Peripheral Functions
Interrupt control registers (ICR00 to ICR15) are located in the interrupt controller
corresponding to the peripheral functions that use interrupt functions. This registers
control the interrupt and extended intelligent I/O service (EI2OS).
■ List of Interrupt Control Registers
Table 3.3-1 "Interrupt control registers" shows a list of interrupt control registers and the
peripheral functions they correspond to.
Table 3.3-1 Interrupt control registers
Address
Register
Abbreviation
Corresponding peripheral function
0000B0H
Interrupt control register 00
ICR00
CAN0
0000B1H
Interrupt control register 01
ICR01
CAN1
0000B2H
Interrupt control register 02
ICR02
Input capture 0, DTP/external interrupt 0
0000B3H
Interrupt control register 03
ICR03
Reload timer 0, DTP/external interrupt 1
0000B4H
Interrupt control register 04
ICR04
Input capture 1, DTP/external interrupt 2
0000B5H
Interrupt control register 05
ICR05
Input capture 2, DTP/external interrupt 3
0000B6H
Interrupt control register 06
ICR06
Input capture 3, DTP/external interrupt 4/5
0000B7H
Interrupt control register 07
ICR07
PPG timer 0, DTP/external interrupt 6/7
0000B8H
Interrupt control register 08
ICR08
PPG timer 1, reload timer 1
0000B9H
Interrupt control register 09
ICR09
PPG timer 2, watch timer (main clock)
0000BAH
Interrupt control register 10
ICR10
Free-run timer, A/D converter
0000BBH
Interrupt control register 11
ICR11
Free-run timer, sound generator
0000BCH
Interrupt control register 12
ICR12
Timebase timer, watch timer (sub-clock)
0000BDH
Interrupt control register 13
ICR13
UART1
0000BEH
Interrupt control register 14
ICR14
UART0
0000BFH
Interrupt control register 15
ICR15
Flash memory, delay interrupt generation
module
63
CHAPTER 3 INTERRUPTS
■ Functions of Interrupt Control Registers
The interrupt control registers (ICR) have the four functions listed below.
•
Setting the interrupt level for the corresponding peripheral function
•
Selecting whether the interrupt for the corresponding peripheral function is set to either
normal interrupt or extended intelligent I/O service
•
Select the channel of extended intelligent I/O service (EI2OS)
•
Indicates the status of extended intelligent I/O service (EI2OS)
The functions of interrupt control registers (ICR) are partially different depending on whether a
read or a write operation is performed, as shown in Figure 3.3-1 "Interrupt control registers
(ICR00 to ICR15) during write operations" and Figure 3.3-2 "Interrupt control registers (ICR00 to
ICR15) during read operations" in the next section.
Note:
Avoid accessing the interrupt control register (ICR) with read-modify-write instructions as this
might cause incorrect operation.
64
3.3 Interrupt Control Registers and Peripheral Functions
3.3.1
Interrupt Control Registers (ICR00 to ICR15)
The interrupt control registers correspond to the peripheral functions that use
interrupt functions for controlling processing at interrupt request generation. The
functions of these registers are slightly different depending on whether a write or a
read operation is performed.
■ Interrupt Control Registers (ICR00 to ICR15)
Figure 3.3-1 Interrupt control registers (ICR00 to ICR15) during write operations
Write Operation
Address
MSB
0000B0H
to
ICS3 ICS2 ICS1 ICS0
0000BFH
ISE
IL2
IL1
IL2
LSB
Initial value
IL0
00000111B
IL1 IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt level setting bit
Interrupt level 0 (highest)
Interrupt level (no interrupt)
2
ISE
EI OS enabled bit
0
Interrupt sequence started when an interrupt occurs
1
EI2OS started when an interrupt occurs
ICS3 ICS2 ICS1 ICS0
MSB : Most Singnificant Bit
LSB : Least Singnificant Bit
: Initial value
EI2OS channel selection bit
Channel
Descriptor address
0
0
0
0
0
000100 H
0
0
0
1
1
000108 H
0
0
1
0
2
000110 H
0
0
1
1
3
000118 H
0
1
0
0
4
000120 H
0
1
0
1
5
000128 H
0
1
1
0
6
000130 H
0
1
1
1
7
000138 H
1
0
0
0
8
000140 H
1
0
0
1
9
000148 H
1
0
1
0
10
000150 H
1
0
1
1
11
000158 H
1
1
0
0
12
000160 H
1
1
0
1
13
000168 H
1
1
1
0
14
000170 H
1
1
1
1
15
000178 H
65
CHAPTER 3 INTERRUPTS
Figure 3.3-2 Interrupt control registers (ICR00 to ICR15) during read operations
Read Operation
Address
0000B0H
to
0000BFH
MSB
S1
S0
MSB : Most Singnificant Bit
LSB : Least Singnificant Bit
: Undefined
: Initial value
66
ISE
IL2
LSB
Initial value
IL0
--000111B
IL1
IL2
IL1
IL0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Interrupt level setting bit
Interrupt level 0 (highest)
Interrupt level (no interrupt)
ISE
EI2OS enable bit
0
Interrupt sequence started when an interrupt occurs
1
EI2OS started when an interrupt occurs
EI2OS status
2
Whether EI OS is in operation or has not started
In stop state due to the end of counting
S1
S0
0
0
0
1
1
0
Reserved
1
1
In stop state due to request from peripheral function
3.3 Interrupt Control Registers and Peripheral Functions
3.3.2
Function of Interrupt Control Registers
The interrupt control registers (ICR00 to ICR15) consist of bits for the following four
functions:
• Interrupt level setting (IL2 to IL0)
• Extended intelligent I/O service (EI2OS) enable (ISE)
• Extended intelligent I/O service (EI2OS) channel selection (ICS3 to ICS0)
• Extended intelligent I/O service (EI2OS) status indication (S1 to S0)
■ Interrupt Control Register (ICR) Configuration
Figure 3.3-3 "Configuration of interrupt control registers (ICR)" shows the bit configuration of the
interrupt control register (ICR).
Figure 3.3-3 Configuration of interrupt control registers (ICR)
Interrupt control register (ICR) during write operations
Address
0000B0H
to
0000BFH
MSB
LSB
ICS3 ICS2 ICS1 ICS0 ISE
IL2
IL1
IL0
Initial value
00000111B
Interrupt control register (ICR) during read operations
Address
0000B0H
to
0000BFH
MSB
LSB
S1
S0
ISE
IL2
IL1
IL0
Initial value
--000111B
MSB : Most Singnificant Bit
LSB : Least Singnificant Bit
: Undefined
Bits ICS3 to ICS0 are valid only if the extended intelligent I/O service (EI2OS) has been started.
To start EI2OS, set the ISE bit to "1", otherwise, set it "0". If EI2OS is not started, ICS3 to ICS0
do not need to be set.
ICS1 and ICS0 are valid only in write operations, and S1 and S0 are valid only in read
operations.
Note:
- Reading data of higher 2 bits is an unspecified value.
67
CHAPTER 3 INTERRUPTS
■ Function of Interrupt Control Register
❍ Interrupt level setting bits (IL2 to IL0)
Specify the interrupt level of the corresponding peripheral function. The interrupt level is
initialized to level 7 (no interrupt) at reset. The interrupt level setting bits correspond to each
interrupt level as shown in Table 3.3-2 "Relationship between interrupt level setting bits and
interrupt levels".
Table 3.3-2 Relationship between interrupt level setting bits and interrupt levels
IL2
IL1
IL0
Interrupt level
0
0
0
0 (highest interrupt)
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
6 (lowest interrupt)
1
1
1
7 (no interrupt)
❍ Extended intelligent I/O service (EI2OS) enable bit (ISE)
If, when an interrupt request is generated, this bit is set to "1", EI2OS starts. If it is set to "0", an
interrupt sequence starts. If the condition for EI2OS end is satisfied (i.e., the bits S1 and S0 bits
are other than 00B), the ISE bit is cleared. If the corresponding peripheral function does not use
any EI2OS functions, the ISE bit must be set to "0" by software. The ISE bit is initialized to "0" at
a reset.
❍ Extended intelligent I/O service (EI2OS) channel selection bits (ICS3 to ICS0)
The EI2OS channel is specified by write-only bits. The value set by these bits specifies the
EI2OS descriptor address. The ICS bit is initialized to 0000B at reset. Table 3.3-3 "Relationship
between EI2OS channel selection bits and descriptor addresses" shows the relationship
between the EI2OS channel selection bits and the descriptor address.
68
3.3 Interrupt Control Registers and Peripheral Functions
Table 3.3-3 Relationship between EI2 OS channel selection bits and descriptor
addresses
ICS3
ICS2
ICS1
ICS0
Selected channel
Descriptor address
0
0
0
0
0
000100H
0
0
0
1
1
000108H
0
0
1
0
2
000110H
0
0
1
1
3
000118H
0
1
0
0
4
000120H
0
1
0
1
5
000128H
0
1
1
0
6
000130H
0
1
1
1
7
000138H
1
0
0
0
8
000140H
1
0
0
1
9
000148H
1
0
1
0
10
000150H
1
0
1
1
11
000158H
1
1
0
0
12
000160H
1
1
0
1
13
000168H
1
1
1
0
14
000170H
1
1
1
1
15
000178H
❍ Extended intelligent I/O service (EI2OS) status bits (S1, S0)
These bits are read-only bits. Their value is checked at the end of EI2OS operation to determine
the operational status (in operation or ended). They are initialized to 00B at reset. Table 3.3-4
"Relationship between EI2OS status bits and EI2OS status" shows the relationship between the
S0/S1 bits and the EI2OS status.
Table 3.3-4 Relationship between EI2OS status bits and EI2OS status
S1
S0
0
0
Whether EI2OS is being operated or has not started
0
1
In stop state because of the end of counting
1
0
Reserved
1
1
In stop state because of a request from a peripheral function
EI2OS status
69
CHAPTER 3 INTERRUPTS
3.4
Hardware Interrupts
Hardware interrupts are used to temporarily stop the execution of program that is
being executed by the CPU in response to an interrupt request signal from a peripheral
function and then transfer control to a user-defined interrupt handling program. The
extended intelligent I/O service (EI2OS) or an external interrupt may also be executed
as a kind of hardware interrupt.
■ Function of Hardware Interrupts
❍ Function of hardware interrupts
During the processing for hardware interrupts, the interrupt level of an interrupt request signal
output by the peripheral function is compared with the value of the interrupt level mask register
(ILM) in the CPU processor status register (PS). The I flag in the processor status register (PS)
is then referenced to determine whether the interrupt is acceptable.
If the hardware interrupt is accepted, the register contents in the CPU are automatically
swapped out to the system stack and the interrupt level currently requested is stored in the
interrupt level mask register (ILM). After that, control branches to the corresponding interrupt
vector.
❍ Multiple interrupts
Multiple hardware interrupts can occur at the same time.
Extended intelligent I/O service (EI2OS)
EI2OS is a function for automatic transfer between memory and I/O, generating a hardware
interrupt when the number of transfers reaches a pre-defined count. EI2OS cannot start multiple
times concurrently: While one EI2OS process is running, all other interrupt requests and EI2OS
requests are retained.
❍ External interrupts
External interrupts (including wake-up interrupts) are accepted as hardware interrupts
transferred via a peripheral function (interrupt request detection circuit).
❍ Interrupt vectors
The interrupt vector table to be reference for interrupt handling is allocated at the memory
addresses FFFC00H to FFFFFFH, which are shared with software interrupts.
For the allocation of interrupt numbers and interrupt vectors, see Section 3.2 "Interrupt Sources
and Interrupt Vectors".
70
3.4 Hardware Interrupts
■ Configuration for hardware interrupts
The system configuration for handling hardware interrupts is divided into four types of elements,
as shown in Table 3.4-1 "Configuration for handling hardware interrupts". To use hardware
interrupts, the program must specify the location of these four configuration elements.
Table 3.4-1 Configuration for handling hardware interrupts
Configuration element for
handling hardware
interrupts
Function
Peripheral function
Interrupt enable bit, interrupt
request bit
Control of interrupt request by peripheral
function
Interrupt controller
Interrupt control register (ICR)
Setting interrupt level and controlling EI2OS
CPU
Interrupt enable flag (I)
Identifying whether interrupts are enabled
Interrupt level mask register
(ILM)
Comparing request interrupt level and current
interrupt level
Microcode
Executing interrupt handling routine
Interrupt vector table
Storing branch addresses for interrupt
handling
Addresses FFFC00H to
FFFFFFH in memory
■ Suppressing Hardware Interrupts
Acceptance of hardware interrupt requests is suppressed under the following conditions.
❍ Suppressing hardware interrupts when writing to peripheral function control register area
When writing to the peripheral function control register area, hardware interrupt requests are not
accepted. This avoids incorrect interrupt-related operations by the CPU when rewriting the
interrupt control registers with each peripheral function. The peripheral function control register
area is not the I/O addressing area from "000000H" to "0000FFH", but the area allocated for the
control registers among the peripheral function control registers and data register.
Figure 3.4-1 "Hardware interrupt requests when writing to the peripheral function control register
area" shows the hardware interrupt operations when writing to the peripheral function control
register area.
Figure 3.4-1 Hardware interrupt requests when writing to the peripheral function control register area
Instruction for writing to peripheral function control register area
.....
MOV A, #08
MOV io, A
Interrupt request
occurs at this point
MOV A, 2000H
Not branched
to interrupt
Interrupt process
Branched to
interrupt
71
CHAPTER 3 INTERRUPTS
❍ Suppressing a hardware interrupts by interrupt suppress instructions
The 10 types of hardware interrupt suppress instruction shown in Table 3.4-2 "Hardware
interrupt suppress instructions" will suppress detection of hardware interrupt requests and
ignore any such interrupt request. Even if a valid hardware interrupt request is issued when
these instructions are being executed, interrupt handling is not executed until another type of
instruction is executed.
Table 3.4-2 Hardware interrupt suppress instructions
Prefix code
Instruction that
rejects interrupts and
hold requests
Interrupt/hold suppress instruction
(instruction to delay the effect of a prefix code)
PCB
MOV ILM, #imm8
DTB
OR CCR, #imm8
ADB
AND CCR, #imm8
SPB
POPW PS
CMR
NCC
❍ Hardware interrupt suppression during the execution of software interrupts
When software interrupt processing starts, the I flag is cleared to "0" and other interrupt
requests are rejected.
72
3.4 Hardware Interrupts
3.4.1
Hardware Interrupt Operation
This section describes the operation from generation of a hardware interrupt request
to the completion of interrupt handling.
■ Starting of Hardware Interrupt Processing
❍ Operation of peripheral function (generating an interrupt request)
A peripheral function that uses hardware interrupt requests has an interrupt request flag to
indicate whether an interrupt request is present and an interrupt enable flag to enable or disable
interrupt requests to the CPU. The interrupt request flag is set when a peripheral functionspecific event is generated, and an interrupt request is issued to the interrupt controller if the
interrupt enable flag is set to "enable".
❍ Operation of interrupt controller (control of interrupt requests)
The interrupt controller compares interrupt levels (IL) in interrupt requests that are received at
the same time, selects the request with the highest priority level (the lowest IL value) and
reports it to the CPU. If multiple requests have the same priority level, the request with the lower
interrupt number has priority.
❍ CPU operation (acceptance of interrupt requests and interrupt handling)
The CPU compares the interrupt level (ICR: IL2 to IL0) received with the interrupt level mask
register (ILM). If IL < ILM and interrupts are enabled (I bit in the PS register is set to "1"),
processing of the interrupt handling microcode starts after the instruction currently being
executed is completed. If the ISE bit of the interrupt control register (ICR) is referenced and
found to be "0" during processing of the start of the interrupt handling microcode, interrupt
handling will executed continuously (If ISE is set to "1", EI2OS will start).
During interrupt handling, the contents of dedicated registers (12 bytes of A, DPR, ADB, DTB,
PCB, PC and PS) are first swapped out to the system stack (into the system stack area
indicated by SSB and SSP). Then, the interrupt vector is loaded into the program counter (PC,
PC), ILM is updated and the stuffing (S) flag is set (i.e., the CCR’s S flag is set to "1" and the
system stack becomes enabled).
■ Return From Hardware Interrupts
If, in the interrupt handling program, the interrupt request flag of the peripheral function, which is
an interrupt source, is cleared and the RETI instruction is executed, the 12 bytes of data
swapped out to the system stack are returned to the dedicated registers to restart the
processing that was being executed before the interrupt branch. By clearing the interrupt
request flag, the interrupt request that was output to the interrupt controller by a peripheral
function is automatically withdrawn.
73
CHAPTER 3 INTERRUPTS
■ Hardware Interrupt Operation
Figure 3.4-2 "Operation of hardware interrupts" shows the operation from the generation of a
hardware interrupt to when interrupt handling is completed.
Figure 3.4-2 Operation of hardware interrupts
Internal data bus
(7)
PS
PS, PC . .
Microcode
IR
F2MC-16LX CPU
I
ILM
Check
(6)
Comparator
(5)
(3)
Other peripheral
function
Peripheral function that generates
an interrupt request
Enable FF
AND
Factor FF
(8)
(4)
..
.
Interrupt
Level
comparator level IL
(2)
(1)
Interrupt controller
RAM
IL :
PS :
:
I
ILM :
IR :
FF :
Interrupt level setting bit for interrupt controller register (ICR)
Processor status register
Interrupt enable flag
Interrupt level mask register
Instruction register
Flip-flop
1. An interrupt source is generated by the peripheral function.
2. If a reference to the interrupt enable bit by the peripheral function indicates that interrupts are
enabled, the interrupt request is issued from the peripheral to the interrupt controller.
3. The interrupt controller that receives the interrupt request also checks the priority of interrupt
requests, then transfers the interrupt level (IL) corresponding to the interrupt request to the
CPU.
4. The CPU compares the interrupt level (IL) requested from the interrupt controller with the
interrupt level mask register (ILM).
5. If the comparison shows that the priority of the interrupt is higher than the current interrupt
handling level, the I flag of the condition code register (CCR) is checked.
6. If the check in 5) indicates that the I flag is set to interrupt enabled (I bit set to "1"), ILM is set
to the requested level (IL) after the instruction currently being executed is completed.
7. The register content is swapped out and processing branches to the interrupt handling
routine.
8. The user’s interrupt handling routine clears the interrupt source generated in 1) for executing
the RETI instruction. This completes interrupt handling.
74
3.4 Hardware Interrupts
3.4.2
Operation Flow for Hardware Interrupts
If an interrupt request is generated from a peripheral function, the interrupt controller
transfers the respective interrupt level to the CPU. If the CPU state allows for
acceptance of interrupts, the instruction currently being executed is temporarily
suspended to execute the interrupt handling routine or start the extended intelligent I/
O service (EI2OS). If a software interrupt is thrown by the INT instruction, the interrupt
handling routine is executed irrespective of the CPU state. Moreover, if a software
interrupt is thrown by an INT instruction, hardware interrupts are disabled.
■ Operation Flow for Hardware Interrupts
Figure 3.4-3 "Operational flow for hardware interrupts" shows the operation flow for hardware
interrupts.
Figure 3.4-3 Operational flow for hardware interrupts
START
Main program
I&IF&IE = 1
AND
ILM > IL
String type
instruction being
NO
executed*1
YES
Interrupt start/return handling
YES
ISE = 1
Reading and decoding
next instruction
EI2OS
NO
YES
INT instruction?
NO
EI2OS processing
Software interrupt/
exception handling
Hardware
interrupt
Swapping out contents
of dedicated registers
to system stack
YES
I
0
(hardware interrupt
acceptance disabled)
Specified
count completed?
Or, end request from
peripheral function?
Swapping out contents
of dedicated registers to
system stack
NO
ILM
IL
(transfer to ILM the interrupt
level of the accepted interrupt
request)
YES
RETI instruction?
NO
Executing normal
instruction
(including interrupt handling)
NO
Interrupt return
handling
Contents of dedicated
registers returned from
system stack, then return
to the routine before the
interrupt routine
S
1
(Enabling system
stack)
PCB, PC
Interrupt vector
(Branch to interrupt handling
routine)
Completed
reiteration of string type
instruction*
YES
Moving pointer to next
instruction if PC updated
*1
I
IF
IE
ILM
ISE
IL
S
PCB
PC
:
:
:
:
:
:
:
:
:
:
When a string type instruction is being executed, the interrupt condition is checked in each step.
interrupt enable flag of condition code register (CCR)
interrupt request flag of peripheral function
interrupt enable flag of peripheral function
interrupt level mask register (in PS)
EI2OS enable flag in interrupt control register (ICR)
interrupt level setting bit in interrupt control register (ICR)
stack flag in condition code register (CCR)
program bank register
program counter
75
CHAPTER 3 INTERRUPTS
3.4.3
Procedure for Using Hardware Interrupts
To use an hardware interrupt, the system stack area, peripheral function, and interrupt
control register (ICR) must be specified in advance.
■ Procedure for Using Hardware Interrupts
An example procedure for using hardware interrupts is shown in Figure 3.4-4 "Procedure for
using hardware interrupts".
Figure 3.4-4 Procedure for using hardware interrupts
Start
(1)
Setting the system stack area
(2)
Initial setting of peripheral function
(3)
ICR setting in interrupt
controller
(4)
Setting for start of peripheral
function
Setting the interrupt permission bit to "enable"
(5)
Interrupt handling program
Branching to stack handl- (8)
ing interrupt vector
(7)
Processing
by hardware
Setting ILM and I in PS
(9)
Handling of interrupt to
peripheral function
(executing interrupt
handling routine)
Clearing the interrupt source
(10) Interrupt return instruction
(RETI)
Main program
(6)
Interrupt request generated
Main program
1. Specifying the system stack area.
2. Initial setting of the peripheral function for generating interrupt requests.
3. Specifying the interrupt control register (ICR) in the interrupt controller.
4. Setting the peripheral function into operation start state and the interrupt enable bit to
"permit".
5. Setting the interrupt level mask register (ILM) and interrupt enable flag (I) to "interrupts can
be accepted".
6. Generating a hardware interrupt request by generation of interrupt for the peripheral function.
7. Hardware for interrupt handling swaps out register contents for branching to the interrupt
handling program.
8. Interrupt handling program performs the processing for the peripheral function as far as
required due to interrupt generation.
9. Clears the interrupt request from the peripheral function.
10.Executes the interrupt return instruction and returns to the program being executed before
branching.
76
3.4 Hardware Interrupts
3.4.4
Multiple Interrupts
For hardware interrupts, multiple interrupts are realized by setting different interrupt
levels to a interrupt level setting bit (IL0, IL1, IL2) in the interrupt control register (ICR)
for multiple interrupt requests from the peripheral function. Multiple starts are however
not allowed in extended intelligent I/O services.
■ Operation for Multiple Interrupts
If, when an interrupt handling routine is being executed, an interrupt request with a higher
priority level is issued, the interrupt request with the higher priority level is accepted by
interrupting the current interrupt handling. After processing the interrupt with the higher level has
been completed, the processing of the original interrupt is restarted after return. The interrupt
level can be set to a value from 0 to 7. When set to level 7, the CPU will not accept the interrupt
request.
If, when interrupt handling is being executed, another interrupt is thrown which has the same
level as the interrupt currently being processed or a lower level, the new interrupt request will be
retained until processing of the current interrupt is completed as long as neither the I flag or ILM
are changed. By setting in the interrupt handling routine the I flag in the condition code register
(CCR) to "interrupt disabled" (I in CCR set to "0") or the interrupt level mask register (ILM) to
"interrupt disabled" (ILM set to "000"), starting multiple interrupts can be temporarily prohibited.
Note:
Starting multiple instances of the extended intelligent I/O service (EI2OS) is prohibited. If an
extended intelligent I/O service (EI2OS) is being processed, all other interrupt requests and
extended intelligent I/O service requests are withheld.
77
CHAPTER 3 INTERRUPTS
■ Example of Multiple Interrupts
In the following example for processing multiple interrupts, the timer interrupt has priority over A/
D converter interrupts: the interrupt level of the A/D converter is set to 2, and the timer interrupt
level is set to 1. When a timer interrupt is generated while an A/D converter interrupt is being
processed with this setting, the processing shown in Figure 3.4-5 "Example of multiple
interrupts" is performed.
Figure 3.4-5 Example of multiple interrupts
Main program
A/D interrupt handling
Interrupt level 2
(ILM = 010)
Peripheral initialized (1)
A./D interrupt generated (2)
Timer interrupt handling
Interrupt level 1
(ILM = 001)
(3) Timer interrupt
generated
Interrupt
(4) Timer interrupt handling
Restart
Main process restart (8)
(6) A/D interrupt handling
(5) Timer interrupt return
(7) A/D interrupt return
❍ A/D interrupt generation
When A/D converter interrupt handling starts, the interrupt level mask register (ILM) is
automatically set to the same interrupt level (IL2 to IL0 in ICR) as that for the A/D converter (in
this example, 2). If a new interrupt request of level 1 or 0 is generated in this case, the new
interrupt is processed with priority.
❍ End of interrupt handling
If, after an interrupt handling is completed, a return instruction (RETI) is executed, the contents
of dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) that were swapped out to the stack
are returned, while the interrupt level mask register (ILM) is set to the value immediately before
the interrupt.
78
3.4 Hardware Interrupts
3.4.5
Time for Handling Hardware Interrupts
The time until the interrupt handling routine starts the execution after a hardware
interrupt request is generated is the time until the instruction currently being executed
is completed plus the interrupt handling time.
■ Time for Handling Hardware Interrupts
Until the interrupt handling routine starts the execution after an interrupt request is generated
and the interrupt is accepted, the interrupt request sample wait time and interrupt handling time
(time required for preparing for interrupt handling) are required. Figure 3.4-6 "Interrupt handling
time" shows the time for handling interrupts.
Figure 3.4-6 Interrupt handling time
CPU operation
Interrupt wait time
Normal instruction execution
Interrupt request
sample wait time
Interrupt handling
Interrupt handling routine
Interrupt handling time
( machine cycle) *1
Interrupt request generated
: final instruction cycle during interrupt request sampling.
*1 : One machine cycle corresponds to one clock interval of the machine clock ( )
❍ Interrupt request sample wait time
The time from when an interrupt request is generated until the instruction currently being
executed is completed. Whether an interrupt request is generated is determined by sampling
the interrupt requests in the final cycle of each instruction. Therefore, the CPU cannot detect an
interrupt request while an instruction is still being executed, which results in wait time.
The interrupt request sample wait time reaches its maximum value if an interrupt request occurs
immediately after the start of a sequence of the type "POPW RW0, ... RW7 instruction" (45
machine cycles), because these sequences have the longest execution cycle.
❍ Interrupt handling time (θ
θ machine cycle)
After an interrupt request is accepted, the CPU performs such operations as swapping out the
contents of the dedicated registers to the system stack, acquiring the interrupt vector, and so
on. This requires an interrupt handling time of θ machine cycles. The interrupt handling time can
be obtained from the following formulas:
At the start of interrupt processing: θ = 24 + 6 x Z machine cycles
At the return from an interrupt: θ = 11 + 6 x Z machine cycles (RETI instruction)
The interrupt handling time depends on the address the stack pointer points to. Table 3.4-3
"Correction values (Z) for the interrupt handling time" indicates the required correction value (Z)
for the interrupt handling time.
One machine cycle corresponds to one clock interval of the machine clock (φ).
79
CHAPTER 3 INTERRUPTS
Table 3.4-3 Correction values (Z) for the interrupt handling time
Address the stack pointer points to
80
Correction value (Z)
External 8 bits
+4
External even address
+1
External odd address
+4
Internal even address
0
Internal odd address
+2
3.5 Software Interrupts
3.5
Software Interrupts
Software interrupts have the function to transfer control from the program currently
executed by the CPU to the interrupt handling program defined by the user when a
software interrupt instruction (INT instruction) is executed. Hardware interrupts are
disabled while a software interrupt is being executed.
■ Start of Software Interrupt Processing
❍ Start of software interrupt processing
To issue a software interrupt, use the INT instruction. Software interrupt requests have no
interrupt request flag or enable flag, but always generate an interrupt request if the INT
instruction is executed.
❍ Disabling hardware interrupts
The INT instruction has no interrupt level, so the interrupt level mask register (ILM) is not
updated. During the execution of the INT instruction, the I flag in the condition code register
(CCR) is set to "0" to mask the hardware interrupt. To enable hardware interrupts during
software interrupt handling, set the I flag to "1" in the software interrupt handling routine.
❍ Operation for handling software interrupts
When the CPU receives and executes an INT instruction, it starts execution of the microcode for
software interrupt handling. Use this microcode for swapping out the contents of the CPU
internal registers to the system stack, masking hardware interrupts (I flag in CCR set to "0") and
branching to the corresponding interrupt vector.
For the assignment of interrupt numbers and interrupt vectors, see Section 3.2 "Interrupt
sources and Interrupt Vectors."
■ Return from Software Interrupts
When an interrupt return instruction (RETI instruction) is executed in the interrupt handling
program, the 12 byte of data swapped out to the system stack are restored to the dedicated
registers. Moreover, control returns to the processing that was being executed immediately
before the interrupt branch.
81
CHAPTER 3 INTERRUPTS
■ Operation for Software Interrupt Processing
Figure 3.5-1 "Operation of software interrupts" shows the operation performed from software
interrupt generation to completion of interrupt handling.
Figure 3.5-1 Operation of software interrupts
Internal data bus
PS, PC ...
(2) Microcode
(1)
PS
I
S
IR
Queue
Fetch
RAM
PS :
I :
S :
IR :
Processor status register
Interrupt enable flag
Stack flag
Instruction register
1. Execute the software interrupt instruction.
2. Based on the microcode for the software interrupt instruction, perform the necessary
processing, such as swapping out the contents of the dedicated registers, and perform
branch processing.
3. Execute the RETI instruction in the user’s interrupt handling routine to end interrupt handling.
■ Precautions for Software Interrupts
If the program bank register (PCB) is set to "FFH", the CALLV instruction’s vector area overlaps
the table for INT #vct8 instructions. When creating the software, make sure that the addresses
for the CALLV instruction and INT #vct8 instruction do not overlap.
82
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.6
Interrupt by Extended Intelligent I/O Service (EI2OS)
The extended intelligent I/O service (EI2OS) is a function used to automatically transfer
data between the peripheral function (I/O) and memory and generate a hardware
interrupt when the data transfer is completed.
■ Extended intelligent I/O Service (EI2OS)
The extended intelligent I/O service is processed as a type of hardware interrupt. It provides a
function to automatically transfer data between the peripheral function (I/O) and memory. Data
transfer as far as previously performed by the interrupt-handling program is provided in the
same way as via DMA (direct memory access). After completion, the end condition is set
followed by an automatic branch to the interrupt handling routine. The user only has to create
the program for starting and ending EI2OS, it is not necessary to provide a program for data
transfer while the service is being processed.
❍ Benefits from using the extended intelligent I/O service (EI2OS)
Compared with data transfer as provided by the interrupt handling routine, using EI2OS provides
the benefits listed below:
•
No transfer program is required, which reduces overall program size.
•
Transfer may be suspended based on the state of the peripheral function (I/O), which
eliminates the need to transfer unnecessary data.
•
Either incrementing or not updating the buffer address may be selected.
•
Either incrementing or not updating the I/O register address may be selected.
❍ Completion interrupt for the extended intelligent I/O service (EI2OS)
When data transfer by EI2OS is completed, the end condition is stored in the S1 and S0 bits of
the interrupt control register (ICR). After this, the system automatically branches to the interrupt
handling routine.
The completion cause for EI2OS can be determined by using the interrupt handling program to
check the EI2OS status (S1 and S0 bits in ICR).
The interrupt number and interrupt vector for each peripheral are fixed. For detailed information,
see Section 3.2 "Interrupt Sources and Interrupt Vectors".
❍ Interrupt control register (ICR)
This register is located in the interrupt controller and used to start the EI2OS, specify EI2OS
channels, and indicate the state when EI2OS ends.
83
CHAPTER 3 INTERRUPTS
❍ Extended intelligent I/O service (EI2OS) descriptor (ISD)
This is a data item of 8 byte, which is located in the RAM at the addresses 000100H to
00017FH, provided for 16 channels. It stores the transfer mode, I/O address and transfer
counts, and buffer addresses. The corresponding channel is specified by the interrupt control
register (ICR).
Note:
During execution of the extended intelligent I/O service (EI2OS), program execution of the
CPU is stopped.
■ Operation of the Extended intelligent I/O Service (EI2OS)
Figure 3.6-1 "Operation of the extended intelligent I/O service (EI2OS)" shows EI2OS operation.
Figure 3.6-1 Operation of the extended intelligent I/O service (EI2OS)
Memory space
Peripheral
by IOA
I/O register function (I/O)
(5)
I/O register
CPU
Interrupt request
(3)
ISD
by ICS
(2)
Interrupt control register (ICR)
(3)
Interrupt controller
by BAP
(4)
ISD :
IOA :
BAP :
ICS :
DCT :
Buffer
by DCT
EI2OS descriptor
I/O address pointer
Buffer address pointer
EI2OS channel selection bit in the interrupt control register (ICR)
Data counter
1. I/O requests the transfer.
2. Interrupt controller selects the descriptor.
3. Transfer source/destination are read from the descriptor.
4. Data transfer between I/O and memory is performed.
5. Interrupt source is automatically cleared.
84
(1)
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.6.1
Extended Intelligent I/O Service (EI2OS) Descriptor (ISD)
The extended intelligent I/O service (EI2OS) descriptor (ISD) is located in the internal
RAM at the addresses 000100H to 00017FH and consists of 8 bytes × 16 channels.
■ Configuration of the Extended intelligent I/O Service (EI2OS) Descriptor (ISD)
The ISD consists of 8 bytes x 16 channels. Each ISD has the structure shown in Figure 3.6-2
"Configuration of EI2OS descriptor (ISD)". The relationship between channel number and ISD
address is indicated in Table 3.6-1 "Relationship between channel number and descriptor
address".
Figure 3.6-2 Configuration of EI2OS descriptor (ISD)
MSB
LSB
Data counter: upper 8 bits (DCTH)
H
Data counter: lower 8 bits (DCTL)
I/O register address pointer: upper 8 bits (IOAH)
I/O register address pointer: lower 8 bits (IOAL)
EI2OS status register (ISCS)
Buffer address pointer: upper 8 bits (BAPH)
Buffer address pointer: middle 8 bits (BAPM)
ISD heading address
(000100H 8 ICS)
Buffer address pointer: lower 8 bits (BAPL)
L
85
CHAPTER 3 INTERRUPTS
Table 3.6-1 Relationship between channel number and descriptor address
86
Channel
Descriptor address
0
000100H
1
000108H
2
000110H
3
000118H
4
000120H
5
000128H
6
000130H
7
000138H
8
000140H
9
000148H
10
000150H
11
000158H
12
000160H
13
000168H
14
000170H
15
000178H
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.6.2
Registers of the Extended intelligent I/O Service (EI2OS)
Descriptor (ISD)
The extended intelligent I/O service (EI2OS) descriptor (ISD) consists of the registers
listed below.
• Data counter (DCT)
• I/O register address pointer (IOA)
• EI2OS status register (ISCS)
• Buffer address pointer (BAP)
Note that the initial value of each register is unspecified at reset.
■ Data Counter (DCT)
The data counter (DCT) is a register with a length of 16 bits for storing the transfer data count.
Whenever an item of data is transferred, the counter is decremented by one. When this counter
reaches zero, EI2OS operation ends. The maximum transfer count that can be specified by the
data counter (DCT) is 65,536 (64 KB). Figure 3.6-3 "Configuration of data counter (DCT)" shows
the configuration of the DCT.
Figure 3.6-3 Configuration of data counter (DCT)
DCTH
DCTL
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 XXXXXXXXXXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: Reading and writing permitted
X : Unspecified
■ I/O Register Address Pointer (IOA)
The I/O register address pointer (IOA) is a register with a length of 16 bits to indicate the lower
address (A15 to A0) of the I/O register for data transfer with the buffer. The upper address (A23
to A16) is set to all 0’s, allowing I/O addresses from 000000H to 00FFFFH to be specified.
Figure 3.6-4 "Configuration of I/O register address pointer (IOA)" shows the configuration of the
IOA.
Figure 3.6-4 Configuration of I/O register address pointer (IOA)
IOAH
IOAL
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Initial value
IOA A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 XXXXXXXXXXXXXXXXB
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W: Reading and writing permitted
X : Unspecified
87
CHAPTER 3 INTERRUPTS
■ Extended intelligent I/O Service (EI2OS) Status Register (ISCS)
The extended intelligent I/O service (ISCS) consists of 8 bits indicating whether buffer address
pointer and I/O register address pointer can be updated or are fixed. They also indicate the type
of data transfer (in bytes or in words) as well as the direction of transfer. Figure 3.6-5
"Configuration of EI2OS status register (ISCS)" shows the configuration of the ISCS.
Figure 3.6-5 Configuration of EI2OS status register (ISCS)
bit7
bit6
bit5
RESV RESV RESV
bit4
bit3
bit2
bit1
bit0
Initial value
IF
BW
BF
DIR
SE
XXXXXXXX B
R/W R/W R/W R/W R/W R/W R/W R/W
EI2OS completion control bit
SE
0
Not completed by request from a peripheral function
1
Completed by request from peripheral function
Data transfer direction bit
DIR
0
I/O register address pointer --> Buffer address pointer
1
Buffer address pointer --> I/O register address pointer
Bit indicating BAP can be updated/is fixed
BF
0
1
Buffer address pointer is updated after data transfer *1
Buffer address pointer are not updated after data transfer
BW
Transfer data length bit
0
Byte
1
Word
IF
Bit indicating IOA can be updated/ is fixed
0
I/O register address pointer is updated after data transfer *2
1
I/O register address pointers are not updated after data transfer.
RESV
Reserved bit
This bit must be set to 0.
R/W
X
*1
*2
88
:
:
:
:
Reading and writing permitted
Unspecified
Buffer address pointer varies only in the lower 16 bits and can only be incremented.
Address pointer allows only incrementing.
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
■ Buffer Address Pointer (BAP)
The buffer address pointer (BAP) is a register consisting of 24 bits. It is used to store the
address for the next EI2OS data transfer. A separate BAP is assigned for each EI2OS channel;
each EI2OS channel is used to transfer data between any 16 MB address and the I/O. If the BF
bit of the EI2OS status register (ISCS) (Bit in the EI2OS status register indicating whether BAP
can be updated or is fixed) is set to "can be updated", the BAP varies only in the lower 16 bits
(BAPH, BAPL), while the upper 8 bits (BAPH) will not be changed.
The buffer address pointer (BAP) can only specify an address in the area 000000H to FFFFFFH.
Figure 3.6-6 "Configuration of buffer address pointer (BAP)" shows the configuration of the
buffer address pointer (BAP).
Figure 3.6-6 Configuration of buffer address pointer (BAP)
BAP
BAPH
(R/W)
bit0
bit8 bit7
bit16 bit15
bit23
BAPM
(R/W)
BAPL
Initial value
XXXXXXB
(R/W)
R/W : Reading and writing permitted
X : Unspecified
89
CHAPTER 3 INTERRUPTS
3.6.3
Operation of the Extended intelligent I/O Service (EI2OS)
If a peripheral function issues an interrupt request and the corresponding interrupt
control register (ICR) is set to start EI2OS, the CPU allows EI2OS data transfer. After
the data transfer is completed for the count specified, the system will automatically
perform the hardware interrupt.
■ Processing Sequence for the Extended Intelligent I/O Service (EI2OS)
Figure 3.6-7 "Operation flow for the extended intelligent I/O service (EI2OS)" shows the
operational flow of EI2OS processing using the CPU-internal microcode.
Figure 3.6-7 Operation flow for the extended intelligent I/O service (EI2OS)
Interrupt request from
peripheral function
ISE = 1
NO
YES
Interrupt sequence
Read ISD/ISCS
Completion
request from peripheral
function
YES
YES
SE = 1
NO
DIR = 1
NO
YES
NO
Data indicated by IOA
(Data transfer)
Memory area indicated by BAP
IF = 0
YES
NO
BF = 0
DCT = 00
NO
Set S1/S0 to "00"
Peripheral function
interrupt request cleared
CPU operation resumes
:
ISD
ISCS :
:
IF
:
BW
:
BF
:
DIR
:
SE
DCT :
:
IOA
:
BAP
:
ISE
S1, S0 :
90
Update value
depends on BW
Update IOA
Update value
depends on BW
Update BAP
YES
NO
Decrement DCT
Data indicated by BAP
(Data transfer)
Memory area indicated by IOA
(-1)
YES
EI2OS completion processing
Set S1/S0 to "01"
Set S1/S0 to "11"
Set ISE to "0"
Interrupt sequence
EI2OS descriptor
EI2OS status register
IOA update/fixed selection bit for EI2OS status register (ISCS)
Transfer data length set bit for EI2OS status register (ISCS)
Bit indicating BAP can be updated/is fixed for EI2OS status register (ISCS)
Data transfer direction bit for EI2OS status register (ISCS)
EI2OS completion control bit for EI2OS status register (ISCS)
Data counter
I/O register address pointer
Buffer address pointer
EI2OS enable bit for interrupt control register (ICS)
EI2OS status of interrupt control register (ICS)
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
3.6.4
Procedure for Using the Extended Intelligent I/O Service
(EI2OS)
Using the extended intelligent I/O service (EI2OS) requires setting the system stack
area, extended intelligent I/O service (EI2OS) descriptor, peripheral function, and
interrupt control register (ICR).
■ Procedure for Using the Extended Intelligent I/O Service (EI2OS)
Figure 3.6-8 "Procedure for using the extended intelligent I/O service (EI2OS)" shows EI2OS
processing by software and hardware.
Figure 3.6-8 Procedure for using the extended intelligent I/O service (EI2OS)
Processing by software
Processing by hardware
Start
Specifying the system stack area
Initial
setting
Setting the EI2OS descriptor
Initial setting of peripheral
function
Setting of interrupt control
register (ICR)
Specify the operation
start interrupt enable
bit for the built-in resource
Set ILM and I in PS
S1,S0="00"
Run the user program
(Interrupt request) and (ISE=1)
Data transfer
Determining whether interrupt
NO
branching was performed because
of count-out or because of a
completion request from the
resource
(Branch to interrupt vector)
YES
S1,S0="01"or S1,S0="11"
Resetting the extended
intelligent I/O service
(such as by channel
switching)
Processing buffer data
RETI
ISE : EI2OS enable flag in interrupt control register (ICR)
S1, S0: EI2OS status bits in the in interrupt control register (ICR)
91
CHAPTER 3 INTERRUPTS
3.6.5
Processing Time for the Extended intelligent I/O Service
(EI2OS)
The time for processing the extended intelligent I/O service (EI2OS) depends on the
following factors:
Setting of EI2OS status register (ISCS)
Address (area) indicated by I/O register address pointer (IOA)
Address (area) indicated by buffer address pointer (BAP)
Bus width of external data bus for external access
Data length of data to be transferred
•
•
•
•
•
At the end of data transfer by EI2OS, the interrupt handling time is added to the total
time for processing, because a hardware interrupt occurs.
■ Processing Time for the Extended Intelligent I/O Service (EI2OS) (Time Consumed per Transfer)
❍ Time before data transfer continues
The EI2OS process time required for data transfer is shown in Table 3.6-2 "Execution time for
the extended intelligent I/O service" based on the setting of the EI2OS status register (ISCS).
Table 3.6-2 Execution time for the extended intelligent I/O service
Setting of EI 2OS completion control bit
(SE)
Setting of bit indicating IOA can be
updated/ is fixed (IF)
Setting of bit indicating BAP
can be updated/is fixed (BF)
Completion by completion
request from peripherals
Ignore completion
requests from peripherals
Fixed
Can be
changed
Fixed
Can be
changed
Fixed
32
34
33
35
Can be
changed
34
36
35
37
Unit: Machine cycles (1 machine cycle corresponds to one clock interval of the machine clock(φ)).
As shown in Table 3.6-3 "Correction values for data transfer during EI2OS execution", settings
must be corrected depending on the conditions under which EI2OS is executed.
92
3.6 Interrupt by Extended Intelligent I/O Service (EI2OS)
Table 3.6-3 Correction values for data transfer during EI2OS execution
Internal access
External access
I/O register address pointer
Buffer address
pointer
B/even
Odd
B/even
8/odd
Internal
access
B/even
0
+2
+1
+4
Odd
+2
+4
+3
+6
External
access
B/even
+1
+3
+2
+5
8/odd
+4
+6
+5
+8
B: Byte data transfer
8: External bus width for 8-bit word transfer
Even: Even address word transfer
Odd: Odd address word transfer
❍ When the data counter (DCT) stops counting (after the final data transfer is completed)
When data transfer by EI2OS is completed, the interrupt handling time is added to the total
processing time, since a hardware interrupt is generated in this case The EI2OS processing
time required when counting ends can be obtained from the following formula.
EI2OS processing time when counting ends =
EI2OS processing time by the end of data transfer + (21 + 6
Z) machine cycles
Interrupt handling time
One machine cycle corresponds to one clock interval of the machine clock (φ).
Interrupt handling time depends on the address the stack pointer points to. Table 3.6-4
"Correction value (Z) to the interrupt handling time" shows the applicable correction values (Z)
for the interrupt handling time.
Table 3.6-4 Correction value (Z) to the interrupt handling time
Address indicated by stack pointer
Correction value (Z)
External: 8 bit
+4
External: even address
+1
External: odd address
+4
Internal: even address
0
Internal: odd address
+2
93
CHAPTER 3 INTERRUPTS
❍ When data transfer is ended by completion request from the peripheral function (I/O)
If EI2OS data transfer ends prematurely (ICR: S1, S0 = 11) because of receiving a completion
request from the peripheral function (I/O), data transfer is not executed and a hardware interrupt
is generated The EI2OS processing time can in this case be obtained from the formula shown
below The parameter Z in the formula represents a correction value for the interrupt handling
time (see Table 3.6-4 "Correction value (Z) to the interrupt handling time").
EI2OS processing time if transfer ends prematurely: 36 + 6 × Z machine cycles
One machine cycle corresponds to one clock interval of the machine clock (φ).
94
3.7 Exception Interrupt Because of Undefined Instruction
3.7
Exception Interrupt Because of Undefined Instruction
F2MC-16LX handles undefined instructions by exception processing Exception
handling is basically performed in the same was as interrupt handling, i.e., the normal
flow of processing is interrupted for starting exception handling if an exception event
is detected at the instruction boundary.
Generally, exception processing is performed when an unexpected operation is
executed Therefore, it should only be used for debugging or by recovery software for
emergency use.
■ Exception Interrupt Because of Undefined Instruction
❍ Exception handling operation
F2MC-16LX treats all codes not defined in the instruction map as undefined instructions If
undefined instructions are executed, the same processing as for a software interrupt instruction
such as "INT # 10" is performed.
For exceptions, the following processing is performed before branching to the interrupt routine.
•
The contents of the A, DPR, ADB, DTB, PCB, PC, and PS registers is swapped out to the
system stack.
•
The I flag of the condition code register (CCR) is cleared to "0", masking hardware interrupts.
•
The S flag of the condition code register (CCR) is set to "1", enabling the use of the system
stack.
The program counter (PC) value swapped out to the stack represents the address under which
the undefined instruction is stored In other words, the address at which an instruction code of 2
bytes or more is stored which has been identified as "undefined." If the type of the exception
cause needs to be identified from the exception handling routine, use this PC value.
❍ Return from exception handling
After returning from exception handling with the RETI instruction, exception handling will start
again, since the PC points to an undefined instruction Take appropriate action, for example,
perform a software reset.
95
CHAPTER 3 INTERRUPTS
3.8
Stack Operations of Interrupt Handling
If an interrupt is accepted, the contents of the dedicated register is automatically
swapped out to the system stack before processing branches to interrupt handling
Return from the stack is also automatically performed after interrupt handling is
completed.
■ Stack Operation When Interrupt Handling Starts
When an interrupt is accepted, the CPU automatically swaps the current contents of the
dedicated registers out to the system stack, in the following order:
1. Accumulator (A)
2. Direct page register (DPR)
3. Additional data bank register (ADB)
4. Data bank register (DTB)
5. Program bank register (PCB)
6. Program counter (PC)
7. Processor status register (PS)
Figure 3.8-1 "Stack operation at the start of interrupt handling" shows stack operation at the
beginning of interrupt handling.
Figure 3.8-1 Stack operation at the start of interrupt handling
Immediately
before interrupt
SSB
SSP
A
Address
00H
Immediately
after interrupt
Memory
SSB
08FF H
08FE H
08FE H
0000 H
08FE H
AH
AL
DPR 0 1 H
ADB 0 0 H
DTB
PCB F F H
00H
PC
803FH
PS
20E0H
08F2H
Address
00H
08FF H
08FE H
SP
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
XX H
H
SSP
08F2H
A
0000 H
AH
08FE H
AL
DPR 0 1 H
ADB 0 0 H
DTB
PCB F F H
00H
L
PC
803FH
PS
20E0H
Byte
Memory
08F2H
SP
00H
00H
08H
FE H
01H
00H
00H
FFH
80H
3FH
20H
E0H
Byte
AH
AL
DPR
ADB
DTB
PCB
PC
PS
SP after
updated
■ Stack operation after return from interrupt handling
When the interrupt return instruction (RETI) is executed at the end of interrupt handling, the
values of PS, PC, PCB, DTB, ADB, DPR, and A are returned from the stack in the reverse order
of how they were swapped out at the start of interrupt handling This will restore the dedicated
registers to their state immediately before the interrupt started.
96
3.8 Stack Operations of Interrupt Handling
■ Stack Area
❍ Allocation of the stack area
The stack area is used for swapping out/returning the program counter (PC) as required for
executing subroutine call instructions (CALL) and vector call instructions (CALLV) in addition to
interrupt handling Moreover, it is used for temporarily swapping out/ returning the contents of
registers by PUSHW and POPW instructions The stack area is allocated in RAM in addition to
the data area.
Figure 3.8-2 "Stack area" shows the allocation of the stack area.
Figure 3.8-2 Stack area
Vector table
(Reset/interrupt vector
call instructions)
FFFFFF H
FFFC00 H
ROM area
FF0000H *1
000D00H *2
Built-in RAM area
Stack area
000380 H
General-purpose
register bank
area
000180 H
000100 H
0000C0H
000000 H
Built-in I/O area
*1: Built-in ROM capacity depends on product type.
*2: Built-in RAM capacity depends on product type.
Notes:
•
In ordinary cases, use even addresses for setting the addresses of stack pointers (SSP,
USP).
•
Avoid overlapped allocation of the system stack area, user stack area, and data area.
❍ System stack and user stack
For interrupt handling, the system stack area is used Even if the user stack area is being used
when an interrupt occurs, processing forcibly switches to the system stack Thus, the system
stack area must also be correctly prepared in a system where mainly the user stack area is
used Unless it is necessary to separate the available free stack space, use the system stack.
97
CHAPTER 3 INTERRUPTS
3.9
Example Program for Interrupt Handling
An example program for interrupt handling is shown below.
■ Example Program for Interrupt Handling
A coding example for an interrupt handling program that uses the external interrupt 0 (INT0)
instruction is listed below.
[Coding example]
DDR1
ENIR
EIRR
ELVR
ICR00
STACK
EQU
000011H
; Port 1 direction register
EQU
000030H
; Interrupt/DTP enable register
EQU
000031H
; Interrupt/DTP source register
EQU
000032H
; Request level register
EQU
0000B0H
; Interrupt control register 00
SSEG
; Stack
RW
100
STACK_T RW
1
STACK
ENDS
;----------Main program-----------------------------------------------------CODE
CSEG
START:
MOV
RP, #0
; General-purpose register uses heading bank
MOV
ILM, #07H
; Set ILM in PS to level 7
MOV
A, #!STACK_T
; System stack setting
MOV
SSB, A
MOVW A, #STACK_T
; Stack pointer setting. Because the S-flag
MOVW SP, A
; is 1 here, the stack pointer is set to SSP.
MOV
DDR1,#00000000B
; Set P10/INT0 pin to input
AND
CCR, #0E0H
; Clear bits 0 to 4 in CCR within PS
OR
CCR, #40H
; Set I-flag in CCR within PS for enabling
interrupts
MOV
I:ICR00, #00H
; Interrupt level 0 (highest)
MOV
I:ELVR, #00000001B ; Specify INT0 to be an H-level
request
MOV
I:EIRR, #00H
; INT0 interrupt source is cleared
MOV
I:ENIR, #01H
; INT0 input enabled
:
LOOP:
NOP
; Dummy loop
NOP
NOP
NOP
BRA
LOOP
; Unconditional jump
;----------Interrupt program------------------------------------------------ED_INT1:
MOV
I:EIRR, #00H
; Newly accepting INT0 is prohibited
NOP
NOP
NOP
NOP
NOP
NOP
RETI
; Return from interrupt
CODE
ENDS
98
3.9 Example Program for Interrupt Handling
;----------Vector setting---------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FFD0H
; Specify a vector for interrupt #11(0BH)
DSL
ED_INT1
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set to single-chip mode
VECT
ENDS
END
START
99
CHAPTER 3 INTERRUPTS
■ Specification of Processing for the Sample Program of the Extended Intelligent I/O Service (EI2OS)
1. If H level is detected for the signal input to the INT0 pin, the extended intelligent I/O service
(EI2OS) will start.
2. If the INT0 pin enters H level, EI2OS starts and transfers the data in port 0 to the memory at
address "3000H".
3. After transferring 100-byte data is completed, an interrupt is generated due to the end of
EI2OS transfer.
The code of the example program is listed below.
[Coding example]
DDR1
ENIR
EIRR
ELVR
ICR00
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
.SECTION
.ORG
.RES.B
.ORG
.RES.B
.RES.B
.RES.B
.ORG
.RES.B
.ORG
.RES.B
.RES.B
.RES.B
.RES.B
.RES.B
.RES.B
.RES.B
.RES.B
IO,IO, LOCATE=0x000000
0011H
01H
; Port 1 direction register
0030H
01H
; DTP/Interrupt enable register
01H
; DTP/Interrupt source register
01H
; Request level set register
00B0H
01H
; Interrupt control register 00
0100H
01H
; Lower byte of buffer address pointer
01H
; Middle byte of buffer address pointer
01H
; Upper byte of buffer address pointer
01H
; EI2OS status
01H
; Lower byte of I/O address pointer
01H
; Upper byte of I/O address pointer
01H
; Lower byte of data counter
01H
; Upper byte of data counter
.SECTION STACK,STACK
; Stack
.RES.B
0FEH
STACKT .RES.B
01H
;----------Main program-----------------------------------------------------.SECTION PROG,CODE
START:
AND
CCR,#0BFH
; Clear the I-flag in CCR within PS for
disabling interrupts
MOV
RP,#00
; Set the register bank pointer
MOV
A,#bnksym STACKT
; Specify the system stack
MOV
SSB,A
MOVW
A,#STACKT
; Set the stack pointer.
MOVW
SP,A
; Here, SSP is set, because the S-flag is
set to "1".
MOV
I:DDR1,#00000000B ; Set the P10/INT0 pin to "input"
MOV
BAPL,#00H
; Set the buffer address to 003000H
MOV
BAPM,#30H
MOV
BAPH,#00H
100
3.9 Example Program for Interrupt Handling
MOV
ISCS,#00010001B
MOV
IOAL,#00H
MOV
MOV
IOAH,#00H
DCTL,#064H
MOV
MOV
MOV
MOV
MOV
MOV
AND
OR
; I/O addresses not updated, but byte
transfer and buffer address updated
; Transferred from I/O to buffer,
completed by peripheral function
(resource)
; Set the transfer source address
(Port 0:000000H)
; Specify the transfer byte count
(100 bytes)
DCTH,#00H
I:ICR00,#00001000B ; EI2OS channel 0, EI2OS enabled
Interrupt level 0 (highest level)
I:ELVR,#00000001B
; Use INT0 as "H" level request
I:EIRR,#00H
; Clear INT0 interrupt source
I:ENIR,#01H
; INT0 interrupt enabled
ILM,#07H
; Set ILM within PS to level 7
CCR,#0E0H
; Clear bits 0 to 4 in CCR within PS
CCR,#040H
; Set the I-flag in CCR within PS for
enabling interrupts
:
LOOP: BRA
LOOP
; Infinite loop
;----------Interrupt program------------------------------------------------WARI
CLRB
EIRR:0
; Release interrupt/clear DTP
request flag
:
User processing
; Check of EI2OS completion
source, processing of data in
:
; the buffer, EI2OS reset, etc.
RETI
----------Vector setting----------------------------------------------------.SECTION
VECT,CODE, LOCATE=0xFFFF54
.ORG
0FFFFD0H
; Set vector to interrupt #25(19H)
.DATA.E
WARI
.ORG
0FFFFDCH
; Reset vector setting
.DATA.E
START
;
.DATA.B
00H
; Mode data setting
.END
START
101
CHAPTER 3 INTERRUPTS
102
CHAPTER 4
RESET
This chapter describes the reset operation.
4.1 "Outline of Reset Operation"
4.2 "Reset Source and Oscillation Stabilization Wait Time"
4.3 "External Reset Pin"
4.4 "Reset Operation"
4.5 "Reset Source Bit"
4.6 "State of Each Pin by Resetting"
103
CHAPTER 4 RESET
4.1
Outline of Reset Operation
If a reset source occurs, the CPU immediately interrupts the processing currently
being executed and enters the reset clear wait state. After the reset is cleared,
processing starts at the address indicated by the reset vector.
There are six reset sources:
• Supplying power to the system (power-on)
• External reset request from RST pin
• Software reset request
• Watchdog timer overflow
• Lower power voltage detected
• Counter overflow of CPU operation detection function
■ Reset Sources
The reset sources are shown in Table 4.1-1 "Reset source".
Table 4.1-1 Reset source
Reset type
Cause responsible
Used machine
clock
Status of
watchdog
timer
Oscillation
stabilization
wait
Power-on reset
System powered on
Main clock (MCLK)
Stopped
Used
External pin reset
"L" level input to RST pin
Main clock (MCLK)
Stopped
None
Software reset
Set the internal reset signal
generation bit (RST) in the lowpower consumption mode
control register (LPMCR) to "0".
Main clock (MCLK)
Stopped
None
Watchdog timer
reset
Watchdog timer overflow
Main clock (MCLK)
Stopped
Used
Low-voltage
detection reset (*1)
Low-voltage of power supply
detected
Main clock (MCLK)
Stopped
Used
CPU operation
detection function
reset (*1)
Counter overflow of CPU
operation detection function
Main clock (MCLK)
Stopped
None
MCLK: Main clock (divide-by-2 clock of oscillator clock)
*1: This source causes a reset only in the MB90F423GA/GB, MB90F428GA/GB, MB90423GA/GB,
MB90427GA/GB, MB90428GA/GB.
104
4.1 Outline of Reset Operation
❍ Power-on reset
Power-on reset is a reset that occurs when the power is turned on. The oscillation stabilization
wait time is fixed to 218 oscillation clock cycles (218/HCLK). After the oscillation stabilization wait
time has elapsed, the reset operation is performed.
❍ External reset
External reset is a reset that occurs when L level is input to the external reset pin (RST pin). For
this reset to be performed, "L" level input to the RST pin must be applied for at least 16 machine
cycles (16/φ). For an external reset, no oscillation stabilization wait time applies.
Notes:
Only if the RST pin generates a reset request when a reset source occurs during a write
operation (while a transfer type instruction such as MOV is executed), the system enters
reset clear wait state after the end of the instruction. This ensures that the write operation
completes normally when a reset occurs during the write operation.
However, string type instructions (such as MOVS) accept resets before the transfer for the
specified count is completed. For this reason, it cannot be assured that all data will be
transferred in this case.
❍ Software resets
In a software reset, an internal reset is performed if the internal reset signal generation bit (RST)
in the low-power consumption mode control register (LPMCR) is cleared to "0". A oscillation
stabilization wait time does not apply for software resets.
❍ Watchdog resets
In a watchdog reset, a reset is performed when the watchdog timer overflows, if the watchdog
control bit (WTE) in the watchdog timer control register (WDTC) is not cleared to "0" within the
specified time after starting the watchdog timer. A oscillation stabilization wait time does not
apply for watchdog resets.
❍ Low-voltage detection resets
In a low-voltage detection reset, a reset occurs if the voltage of the power supply is lower than
specified. The oscillation stabilization wait time for this case is fixed to 218 oscillation clock
cycles (218/HCLK). After the oscillation stabilization wait time has elapsed, the reset operation is
performed.
This reset is only available in MB90F423GA/GB, MB90F428GA/GB, MB90423GA/GB,
MB90427GA/GB, MB90428GA/GB models, in which a low-voltage/CPU operation detection
reset circuit is mounted. This reset can be used starting with the time the system is powered on.
105
CHAPTER 4 RESET
❍ CPU operation detection resets
In CPU operation detection resets, a reset is generated as soon as the CPU operation detection
function counter overflows, if the CPU operation detection circuit clear bit (CL) in the lowvoltage/CPU operation detection reset control register (LVRC) is not cleared to "0" within the
specified time after power-on.
This reset is only available in MB90F423GA/GB, MB90F428GA/GB, MB90423GA/GB,
MB90427GA/GB, MB90428GA/GB models, in which a low-voltage/CPU operation detection
reset circuit is mounted. This reset can be used starting with the time the system is powered on.
Terms defined for use in explanations related to the clock:
HCLK: Oscillation clock frequency
MCLK: Main clock frequency
SCLK: Sub-clock frequency
φ: Machine clock frequency (CPU operation clock)
1/φ: Machine cycle (CPU operation clock cycle)
For detailed information, see Section 5.1 "Outline of Clock Unit"
Note:
If a reset is generated in stop mode or sub-clock mode, 217/HCLK (about 32.77 ms when
using an oscillation of HCLK = 4 MHz) is used as the oscillation stabilization wait time.
For further information, see Section 5.1 "Outline of the Clock".
106
4.2 Reset Sources and Oscillation Stabilization Wait Time
4.2
Reset Sources and Oscillation Stabilization Wait Time
The MB90420G/425G series has six types of reset sources. The oscillation stabilization
wait time at reset depends on the reset source.
■ Reset Sources and Oscillation Stabilization Wait Time
Table 4.2-1 "Reset sources and oscillation stabilization wait time" shows the reset sources and
oscillation stabilization wait time of the MB90420G/425G series.
Table 4.2-1 Reset sources and oscillation stabilization wait time
Reset type
Reset source
Oscillation stabilization wait time
( ): for an oscillation clock
frequency of 4 MHz
Power-on reset
Power-on
218/HCLK (about 65.536 ms)
Note:
The stabilization time of the stepdown circuit is included.
Watchdog reset
Watchdog timer overflow
Used: WS1 and WS0 bits initialized to
"11"
External reset
"L" input from RST pin
Not used: WS1 and WS0 bits
initialized to "11"
Low-voltage detection
reset (*1)
Low-power voltage detected
217/HCLK (about 32.768 ms)
CPU operation detection
reset (*1)
CPU operation detection timer
overflow
Not used: WS1 and WS0 bits
initialized to "11"
Software
RST bit in the low-power consumption
mode control register (LPMCR) set to
"1"
Not used: WS1 and WS0 bits
initialized to "11"
*1: This reset source causes a reset only for MB90F423GA/GB, MB90F428GA/GB, MB90423GA/GB,
MB90427GA/GB, MB90428GA/GB models.
HCLK: Oscillation clock frequency
WS1, WS0: Oscillation stabilization wait time selection bit in the clock selection register CKSCR
Figure 4.2-1 "Oscillation stabilization wait time for power-on reset" shows the oscillation
stabilization wait time when a power-on reset occurs.
107
CHAPTER 4 RESET
Figure 4.2-1 Oscillation stabilization wait time for power-on reset
Vcc
217/HCLK
217/HCLK
CLK
CPU operation
Stabilization wait
time of step-down
circuit
Oscillation
stabilization
wait time
HCLK: Oscillation clock frequency
Table 4.2-2 Oscillation stabilization wait time depending on clock selection register
(CKSCR) settings
WS1
WS0
Oscillation stabilization wait time
( ) for an Oscillation clock frequency of 4MHz
0
0
210/HCLK (about 0.256 ms)
0
1
213/HCLK (about 2.05 ms)
1
0
215/HCLK (about 8.19 ms)
1
1
217/HCLK (about 32.77 ms)
HCLK: Oscillation clock frequency
Note:
Ceramic and crystal resonators generally need several to a few dozen milliseconds until they
reach their natural frequency. Set an appropriate value for the resonator used. For further
information, see Section 5.1 "Outline of Clock Unit".
■ Oscillation Stabilization Wait Reset State
Power-on reset in stop mode and sub-clock mode is performed after the oscillation stabilization
wait time set by the timebase timer has elapsed. If, in this case, the external reset input is not
cleared, the reset operation will be performed after the external reset is released.
108
4.3 External Reset Pin
4.3
External Reset Pin
The external reset pin (RST pin) is a reset-input dedicated pin which generates an
internal reset if "L" level is input. The MB90420G/425G series normally start reset
operations based on the timing of the CPU operation clock, and only resets through
external pins are performed asynchronously.
■ Block Diagram of External Reset Pin
Figure 4.3-1 Block diagram for internal reset
CPU operation clock
(PLL multiplication circuit, divide-by-2 of HLCK)
RST
Pch
Synchronization
circuit
Pin
Nch
Internal reset signal
in synch with the clock
Input buffer
HLCK: Oscillation clock
Notes:
In order to prevent damage to memory due to a reset during write operations, be sure to
select an appropriate cycle for accepting RST pin input.
For initializing the internal circuit, a clock is required. Operation with an external clock
requires clock input at reset input.
109
CHAPTER 4 RESET
4.4
Reset Operation
If a reset is released, the target for reading mode data and the reset vector is selected
based on the setting of the mode pins, and a mode fetch is performed. With this mode
fetch operation, the CPU operation mode and the execution start address after the
reset operation is completed are determined. At power-on, as well as at return from
sub-clock mode or stop mode by reset, mode fetch is performed after the oscillation
stabilization wait time has elapsed.
■ Outline of Reset Operation
Figure 4.4-1 "Operation flow for reset" shows the operation flow for reset.
Figure 4.4-1 Operation flow for reset
Power-on reset
Stop mode
Sub-clock mode
Low-voltage detection reset
Reset mode
Mode fetch
(Reset operation)
External reset
Software reset
Watchdog timer reset
CPU operation detection
reset
Oscillation stabilization wait
reset state
Obtain the mode data
Obtain the reset vector
Normal operation
(RUN mode)
Obtain and execute instruction
code from address indicated
by reset vector
■ Mode Pins
The mode pins (MD0 to MD2) specify how to obtain the reset vector and mode data. Reset
vector and mode data are read during the reset sequence. For further information about mode
pins, see Section 7.2 "Mode pins".
110
4.4 Reset Operation
■ Mode Fetch
If a reset is released, the CPU performs a hardware-based transfer of the reset vector and
mode data to the relevant register inside the CPU core. Reset vector and mode data are
allocated in a 4-byte area at the addresses FFFFDCH to FFFFDFH. The CPU outputs these
addresses to the bus immediately after the reset is released to obtain the reset vector and mode
data. With this mode fetch operation, the CPU starts processing from the address indicated by
the reset vector.
Figure 4.4-2 "Transferring reset vector and mode data" shows the transfer of reset vector and
mode data.
Figure 4.4-2 Transferring reset vector and mode data
2
F MC-16LX CPU core
Memory space
Mode
register
FFFFDFH
Mode data
FFFFDEH
Reset vector bits 23 to 16
FFFFDDH
Reset vector bits 15 to 8
FFFFDCH
Reset vector bits 7 to 0
Micro ROM
Reset sequence
PCB
PC
❍ Mode data (Address: FFFFDFH)
The mode register setting can be changed only by a reset operation, and the setting becomes
effective after the reset. For further information about mode data, see Section 7.3 "Mode Data".
❍ Reset vector (Address: FFFFDCH to FFFFDEH)
The start address for the processing to be started after the reset is written to this area.
Execution will start from the address in this vector.
111
CHAPTER 4 RESET
4.5
Reset Source Bit
The source for reset generation can be identified by reading the watchdog timer
control register (WDTC) and the low-voltage/CPU operation detection reset control
register (LVRC).
■ Reset Source Bit
Figure 4.5-1 "Reset source bit block diagram" shows the flip-flops corresponding to each reset
source. The contents of the flip-flop can be obtained by reading the watchdog timer control
register (WDTC). If, after the reset is released, the reset source must be identified, read the
value of the watchdog timer control register (WDTC) by software and branch to the relevant
program.
Figure 4.5-1 Reset source bit block diagram
CPU operation
detection
reset request
detection circuit
RST pin
HST = internally fixed to "H"
(Hardware stand-by mode not used)
Power supply
voltage lowered
Power-on
Watchdog
timer reset
detection
circuit
External reset
request
detection
circuit
Hardware
stand-by clear
detection
circuit
Low-voltage
detection
circuit
Power-on
detection
circuit
Not cleared
regularly
RST=L
RST bit set
LPMCR/RST
bit write
detection
circuit
Clear
Watchdog timer
control register
(WDTC)
S
F/F
Q
R
S
F/F
Q
R
S
R
F/F
Q
S
F/F
Q
R
S
F/F
Q
R
Delay
circuit
Read the watchdog
timer control
register (WDTC)
Internal data bus
S
R
Q
F/F
112
:
:
:
:
Set
Reset
Out put
Flip Flop
4.5 Reset Source Bit
■ Correspondence Between Reset Source Bit and Reset Source
The configuration of reset source bits in the watchdog timer control register (WDTC) is shown in
Figure 4.5-2 "Configuration of reset source bits (watchdog timer control register". The
correspondence between the contents of reset source bits and reset sources is shown in Table
4.5-1 "Correspondence between the contents of reset source bits and reset source". For further
information, see Section 9.3.1 "Watchdog Timer Control Register (WDTC)".
Figure 4.5-2 Configuration of reset source bits (watchdog timer control register
Watchdog Timer Control Register (WDTC)
Address
0000A8 H
bit8
bit15
(TBTC)
bit7
bit6
PONR
-
R
-
bit5 bit4 bit3
bit2
WRST ERST SRST WTE
R
R
R
W
bit1
bit0
Initial value
WT1 WT0
X-XXX111B
W
W
R : Read only
W : Write only
X : Unspecified
Table 4.5-1 Correspondence between the contents of reset source bits and reset source
Reset source
PONR
WRST
ERST
SRST
Power-on reset request generated
Low-voltage detection reset request generated (*1)
1
X
X
X
Reset request generated due to watchdog timer
overflow
Y
1
Y
Y
External reset requested by RST pin
CPU operation detection reset request generated *2
Y
Y
1
Y
Software reset request generated
Y
Y
Y
1
Y: Retains the previous state
X: unspecified
*1: If a low-voltage detection reset request is generated, the LVRF bit in the low-voltage/CPU
operation detection reset control register (LVRC) is set to "1".
*2: If a CPU operation detection reset request is generated, the CPUF bit in the low-voltage/
CPU operation detection reset control register (LVRC) is set to "1".
113
CHAPTER 4 RESET
■ State of Reset Source Bits
Figure 4.5-3 State of reset source bits
(1)
At power-on
(2)
Bit clearing
(3)
If low voltage is detected
(4)
Bit clearing
(1)
(2)
(3)
(4)
PONR bit
(Power-on or LVRF=1)
1
0
1
0
ERST bit
(External reset input,
CPU operation detection)
0
0
0
0
1 or 0
0
1
0
Vcc=4V
Vcc
LVRF bit (*1)
(Low voltage detection,
4V+0.3V)
*1: The LVRF bit is in the low voltage and CPU operation detection reset control register
(LVRC 6EH).
(1) At power-on
When power is turned on, the power-on reset bit (PONR) and LVRF are set to "1".
However, if power is turned on without an ordinary startup, LVRF may be set to "0".
(2) Bit clearing (Clearing bits by reading the WDTC register and writing "0" to LVRF)
(3) If low voltage (4V+0.3V) is detected
If low voltage (Vcc = 4V+0.3V) is detected, the LVRF and PONR bits are set to "1".
(4) Bit clearing (Clearing bits by reading the WDTC register and writing "0" to LVRF)
114
4.5 Reset Source Bit
■ Notes on the Reset Source Bit
❍ If there are multiple reset sources at the same time
If there are multiple reset sources at the same time, the corresponding reset source bits in the
watchdog timer control register (WDTC) are set to "1". For example, if there is an external reset
request from the RST pin at the same time as an overflow of the watchdog timer, the ERST and
WRST bits are both set to "1".
❍ Clearing the reset source bit
The reset source bit is cleared only if the watchdog timer control register (WDTC) is read out. A
flag that is set due to the corresponding reset source will not be cleared and will remain set to
"1" even if other reset sources cause a reset thereafter.
Note:
If the power is turned on without a power-on reset, the value in this register cannot be
assured.
115
CHAPTER 4 RESET
4.6
State of Each Pin After Reset
This section describes the state of each pin after reset.
■ State of Pins in Reset Mode
The state of a pin while a reset is being in progress is specified by the setting of the mode pins
(MD2 to MD0 are set to "011").
For the reset mode of each pin, see Section 6.7 "Pin State in Standby Mode and During Reset".
❍ Setting internal vector mode
With this setting, I/O pins (peripheral function pins) are set to high-impedance and internal ROM
becomes the target for reading the mode data.
■ State of Pin After Reading the Mode Data
The state of a pin after reading the mode data is specified by the mode data (M1, M0 = "00").
❍ If single-chip mode is selected (M1, M0 = 00B)
The I/O pins (peripheral function pins) are all set to high-impedance, and the internal ROM
becomes the target for reading mode data.
Note:
Make sure that, if a pin is at high-impedance because a reset source occurred, this does not
cause incorrect operation of external devices connected to the pin.
116
CHAPTER 5
CLOCK
This chapter describes the clock of the MB90420G/425G series.
5.1 "Outline of Clock Unit"
5.2 "Block Diagram of the Clock Generation Section"
5.3 "Clock Selection Register (CKSCR)"
5.4 "Clock Modes"
5.5 "Oscillation Stabilization Wait Time"
5.6 "Connection of Resonator with External Clock"
117
CHAPTER 5 CLOCK
5.1
Outline of Clock Unit
The clock generation section controls operation of the internal clock that drives the
CPU and peripheral functions. This internal clock is called the machine clock. One
clock interval is called a machine cycle. The clock that uses this oscillation is called
the oscillation clock, and the clock that uses the internal PLL oscillation is called the
PLL clock.
■ Outline of Clock Unit
The clock generation section has a built-in oscillation circuit and becomes an oscillation clock by
connection with an external resonator. Input from an external clock may also be used as
oscillation clock signal. The section has a built-in PLL clock multiplication circuit to generate four
types of multiplication clock signals from the oscillation clock. The clock generation section
controls the oscillation stabilization wait time and the PLL clock multiplication, and also controls
the internal clock operation by switching the clock with the clock selector.
❍ Oscillation clock (HCLK)
Either a clock created by connecting a resonator to the X0 and X1 pins or input from an external
device.
❍ Sub-clock (SCLK)
Either a clock created by connecting a resonator to the X0A and X1A pins or internal input from
the divide-by-4 clock. It is used as an input clock to the watch timer and low-speed machine
clock in sub-clock mode.
❍ Main clock (MCLK)
A clock created from the oscillation clock by using a divide-by-2 circuit. It is used as an input
clock to the timebase timer and clock selector.
❍ PLL clock (PCLK)
A clock obtained by multiplying the signal from the oscillation clock through the built-in PLL
clock multiplication circuit. One of four types of multiplication clock can be selected.
❍ Machine clock (φ
φ)
A clock used to drive the CPU and peripheral functions. One interval of this clock is called a
machine cycle(1/φ). The main clock (divide-by-2 clock from the oscillation clock) or one of four
multiplication clocks can be selected.
Notes:
With an operation voltage of 5 V, the oscillation clock can be 4 MHz. Note, however, that the
CPU and peripheral functions are limited to a maximum operation frequency of 16 MHz. If
multiplication is specified in such a way that the maximum operation frequency would be
exceeded, devices will not operate normally. If, for example, the oscillation frequency is 16
MHz, only multiplication by one can be specified.
Oscillation of the PLL clock multiplication circuit ranges from 3 to 16 MHz and is changed by
selecting the operation voltage and multiplication count. For further information, refer to the
"Data Sheet".
118
5.1 Outline of Clock Unit
■ Clock Supply Map
As an operation clock for the CPU and peripheral function, the supplied machine clock is
generated in the clock generation section. Therefore, the operation of the CPU and peripheral
functions are affected by switching between main clock and PLL clock (clock mode) and by the
PLL clock multiplication rate. An output from the timebase timer through a division circuit is
supplied to some of the peripheral functions, allowing selecting a separate operation clock for
each peripheral. Figure 5.1-1 "Clock supply map" shows the clock supply map.
119
CHAPTER 5 CLOCK
Figure 5.1-1 Clock supply map
Peripheral function
Low-voltage detection
circuit/CPU operation
detection circuit
4
Watchdog timer
TRG
Pin
16-bit PPG timer 0/1/2
PPG0 to 2
Pin
RX0(,1)
Clock generation section
CAN controller 0(/1)
Timebase timer
Pin
X0A
Pin
X1A
Pin
Clock
generation
circuit
X0
Pin
X1
Pin
Pin
TX0(,1)
Clock
generation
circuit
SCLK
(Sub-clock)
SGA,SGO
1 2 3 4
Sound generator
Pin
V0 to V3
PLL multiplication
circuit
PCLK
(PLL clock)
LCD controller/
driver
Divideby-4
DivideClock selector
by-2
MCLK
HCLK
(Oscillation
(Main clock)
(Machine
clock)
clock)
Pin
COM0 to COM3
SEG0 to SEG23
Pin
SCK0,1
Pin
UART0/1
SIN0,1
Pin
SOT0,1
Pin
CPU
Prescaler 0/1
TIN0,1
16-bit reload timer
0/1
Pin
TOT0,1
Pin
Real-time clock
timer
WOT
Pin
INT0 to INT7
External interrupt
HCLK : Oscillation clock
MCLK : Main clock
PCLK : PLL clock
: Machine clock
Pin
16-bit free-run timer
IN0 to IN3
16-bit input
capture 0/1/2/3
10-bit A/D converter
Pin
AN0 to AN7
Pin
ADTG
Pin
PWM1P0 to 3
Stepping motor
controller 0/1/2/3
Pin
PWM1M0 to 3
Pin
PWM2P0 to 3
Pin
4
120
PWM2M0 to 3
Oscillation
stabilization wait
control
Pin
5.2 Block Diagram of the Clock Generation Section
5.2
Block Diagram of the Clock Generation Section
The clock generation section consists of the following five blocks:
• System clock generation circuit
• PLL multiplication circuit
• Clock selector
• Clock selection register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of the Clock Generation Section
Figure 5.2-1 "Block diagram of the clock generation section" shows the block diagram of the
clock generation section, including the standby control circuit and timebase timer circuit.
Figure 5.2-1 Block diagram of the clock generation section
Power saving mode control register (LPMCR)
Pin
Pin highimpedance
control circuit
Pin high-impedance control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selector
Intermittent cycle selection
CPU clock
control circuit
CPU clock
Stop and sleep signals
Standby
control circuit
Stop signal
Machine clock
Oscillation stabilization
wait clear
Clock generation
section
Peripheral
clock control
circuit
Peripheral clock
Oscillation
stabilization
wait timer
selector
Clock selector
Divideby-4
PLL multiplication
circuit
System
clock
generation
circuit
Pin
Clock selection register (CKSCR)
Pin
Divideby-2
Pin
Divide-by1024
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Divideby-2
Timebase timer
Pin
HCLK: Oscillation clock
To watchdog timer
MCLK: Main clock
SCLK: Sub-clock
121
CHAPTER 5 CLOCK
❍ System clock generation circuit
Uses an externally connected resonator to create the oscillation clock (HCLK). Also, allows
input from an external clock.
❍ Sub-clock generation circuit
Uses an externally connected resonator to create the sub-clock (SCLK). Also, allows input from
an external clock.
❍ PLL multiplication circuit
Uses the PLL oscillation to multiply the oscillation clock and input the resulting clock signal it to
the CPU clock selector.
❍ Clock selector
Selects the main clock or one of four PLL clocks for input to the CPU-based clock control circuit
and peripheral based clock control circuit.
❍ Clock selection register (CKSCR)
Switches between the oscillation clock and PLL clock, selects the oscillation stabilization wait
time, and also selects the multiplication ratio of the PLL clock.
❍ Oscillation stabilization wait time selector
A circuit to select the oscillation stabilization wait time for the oscillation clock when the stop
mode is cleared and the watchdog timer is reset. Also selects one of four timebase timer
outputs.
122
5.3 Clock Selection Register (CKSCR)
5.3
Clock Selection Register (CKSCR)
The clock selection register (CKSCR) is used to switch between the main clock and
PLL clock, selecting the oscillation stabilization wait time, and the PLL clock’s
multiplication ratio.
■ Configuration of the Clock Selection Register (CKSCR)
Figure 5.3-1 "Configuration of clock selection register (CKSCR)" shows the configuration of the
clock selection register (CKSCR) configuration, and Table 5.3-1 "Descriptions of functions of
each bit in the clock selection register (CKSCR)" describes the functions of each bit in the clock
selection register (CKSCR).
Figure 5.3-1 Configuration of clock selection register (CKSCR)
Address
0000A1H
bit15 bit14 bit13 bit12 bit11 bit10
bit9
SCM MCM WS1 WS0
SCS MCS CS1
R/W
R/W R/W
R
R/W
R/W
bit8
bit7
CS0
bit0
(LPMCR)
Initial value
11111100B
R/W R/W
CS1 CS0
Multiplication ratio selection bit
( ): Oscillation clock frequency at 4 kHz
0
0
1
HCLK (4MHz)
0
1
2
HCLK (8MHz)
1
0
3
HCLK (12MHz)
1
1
4
HCLK (16MHz)
MCS
Machine clock selection bit
0
PLL clock selection
1
Main clock selection
0
Machine clock selection bit
(sub-clock or main clock)
Sub-clock selection*2
1
Main clock selection
SCS
WS1 WS0
Oscillation stabilization wait time selection bit
( ): Oscillation clock at 4 kHz
0
0
210/HCLK (about 256 s)
0
1
213/HCLK (about 2.05ms)
1
0
215/HCLK (about 8.19ms)
1
1
217/HCLK (about 32.77ms) *1
MCM
Machine clock indication bit
0
Driven by PLL clock
1
Driven by main clock
SCM
Machine clock indication bit
(sub-clock or main clock)
Driven by sub-clock *2
HCLK : Oscillation clock
0
R/W : Reading and writing permitted
Driven by main clock
1
: Only reading permitted
R
: Not used
: Initial value
: 218/HCLK (about 65.54 ms) at power-on reset
*1
: In the MB90420GA/425GA series, sub-clock cannot be selected.
*2
Reset occurs if SCS bit is set to "0".
Note:
At reset, the machine clock selection bit is initialized to selection of the main clock.
123
CHAPTER 5 CLOCK
Table 5.3-1 Descriptions of functions of each bit in the clock selection register (CKSCR)
Bit name
Function
•
•
bit15
SCM: Machine clock
indication bit
•
•
bit14
MCM: Machine clock
indication bit
•
•
Indicates whether the main clock or sub-clock is selected as the
machine clock
The sub-clock is selected if this bit is set to "0", and the machine
clock is selected if this bit is set to "1".
When the SCS bit is 0 and the SCM bit is 1, this is an indication
that the machine clock is being switched from the main clock to the
sub-clock. When the SCS bit is 1 and the SCM bit is 0, this is an
indication that the machine clock is being switched from the subclock to the main clock.
Indicates whether the main clock or PLL clock is selected as the
machine clock.
If this bit set to "0", the PLL clock is selected. If this bit is set to "1",
the main clock is selected.
If MCS is set to "0" and MCM is set to "1", this bit indicates that
operation is currently subject to PLL clock oscillation stabilization
wait time.
•
bit13
bit12
WS1, WS0: Oscillation
stabilization wait time
selection bit
Selects the oscillation stabilization wait time of the oscillation clock
applicable when a) the stop mode is cleared, b) operation changes
from sub-clock mode to main clock mode, or c) operation changes
from sub-clock mode to PLL clock mode.
• Initialized to 11B by all reset sources.
Notes:
The oscillation stabilization wait time must be suitable for the
resonator used. Refer to Section 4.2 "Reset Sources and
Oscillation Stabilization Wait Time". 00B can be set only in main
clock mode.
In PLL clock mode, the oscillation stabilization wait time must be
fixed to 214/HCLK.
•
•
bit11
SCS: Machine clock
selection bit (sub-clock
or main clock)
•
•
124
Specifies whether the main clock or sub-clock is selected as the
machine clock.
If this bit is set from "0" to "1", operation becomes automatically
subject to main clock oscillation stabilization wait time, and the
timebase timer is cleared.
The operation clock in the sub-clock selection mode uses a divideby-4 frequency of the sub-clock (i.e., the machine clock is 8 kHz if
the sub-oscillation is 32 kHz).
If both SCS and MCS are set to "0", SCS has priority and the subclock is selected. All reset sources initialize to "1".
5.3 Clock Selection Register (CKSCR)
Table 5.3-1 Descriptions of functions of each bit in the clock selection register (CKSCR) (Continued)
Bit name
Function
•
bit10
bit9
bit8
MCS: Machine clock
selection bit
Specifies whether the main clock or PLL clock is selected as the
machine clock.
• Selects the PLL clock if this bit is set to "0", or selects the main
clock if it is set to "1".
• If this bit is set from "1" to "0", the operation becomes subject to the
PLL clock’s oscillation stabilization wait time and the timebase timer
is cleared. Moreover, the TBOF bit in the timebase timer control
register (TBTC) is cleared as well.
• The PLL clock’s oscillation stabilization wait time is fixed to 214/
HCLK (i.e., if the oscillation clock frequency is 4 MHz, the
oscillation stabilization wait time is set to approximately 4.1 ms).
• During main clock selection, the frequency of the operation clock is
the divide-by-2 frequency of the oscillation clock (i.e., if the
frequency of the oscillation clock is 4 MHz, the frequency of the
operation clock becomes 2 MHz).
• Initialized to "1" by all reset sources.
Note:
To set the MCS bit from "1" to "0", use either the timebase timer
control register (TBTC) TBIE bit or interrupt level register (ILM)
while timebase timer interrupts are masked.
CS1, CS0:
Multiplication ratio
selection bit
• Selects the PLL clock’s multiplication ratio.
• Selects one of four multiplication ratios.
• Initialized to 00B by all reset sources.
Note:
If the MCS bit or MCM bit is set to "0", write operation is
suppressed. Once the MCS bit is set to "1"(main clock mode),
rewrite the CS1 and CS0 bits.
HCLK: Oscillation clock frequency
125
CHAPTER 5 CLOCK
5.4
Clock Mode
The clock modes are main clock mode, PLL clock mode, and sub-clock mode.
■ Main Clock Mode, PLL Clock Mode, and Sub-clock Mode
❍ Main clock mode
In main clock mode, a divide-by-2 frequency of the oscillation clock is used as operation clock of
the CPU and peripheral functions, and the PLL clock is stopped.
❍ PLL clock mode
In PLL clock mode, the PLL clock is used as operation clock of the CPU and peripheral
functions. The PLL clock’s multiplication ratio can be is selected via the clock selection register
(CKSCR CS1, CS0).
❍ Sub-clock mode
In sub-clock mode, a divide-by-4 frequency of sub-clock is used as operation clock of the CPU
and peripheral functions, while main clock and PLL clock are stopped.
Note:
The sub-clock mode is only available in the MB90F423GB/GC, MB90F428GB/GC,
MB90423GB/GC, MB90427GB/GC, MB90428GB/GC.
■ Transition of Clock Mode
Setting the MCS bit and SCS bit of the clock selection register (CKSCR) allows changing the
clock mode to main clock mode, PLL clock mode, or sub-clock mode.
❍ Transition from main clock mode to PLL clock mode
If, in main clock mode, the clock selection register (CKSCR) MCS bit is set from "1" to "0",
operation switches from main clock mode to PLL clock mode after the PLL clock’s oscillation
stabilization wait time has elapsed (214/HCLK).
❍ Transition from PLL clock mode to main clock mode
If, in the PLL clock mode, the clock selection register (CKSCR) MCS bit is set from "0" to "1",
operation switches from PLL clock mode to main clock mode when the PLL clock and main
clock have edges that match each other (after 1 to 8 PLL clocks).
❍ Transition from main clock mode to sub-clock mode
If, in the main clock mode, the clock selection register (CKSCR) SCS bit is set from "1" to "0",
the operation switches from main clock mode to sub-clock mode.
❍ Transition from sub-clock mode to main clock mode
If, in sub-clock mode, the clock selection register (CKSCR) SCS bit is set from "0" to "1", the
operation switches from sub-clock mode to main clock mode after the main clock’s oscillation
stabilization wait time has elapsed. The oscillation stabilization wait time can be selected using
the WS1 or WS0 bit of the clock selection register (CKSCR).
126
5.4 Clock Mode
❍ Transition from PLL clock mode to sub-clock mode
If, in PLL clock mode, the clock selection register (CKSCR) SCS bit is set from "1" to "0", the
operation switches from PLL clock mode to sub-clock mode.
❍ Transition from sub-clock mode to PLL clock mode
If, in sub-clock mode, the clock selection register (CKSCR) SCS bit is set from "0" to "1", the
operation switches to PLL clock mode after the main clock’s oscillation stabilization wait time
has elapsed. The oscillation stabilization wait time can be selected by the WS1 or WS0 bit of the
clock selection register (CKSCR).
Notes:
Even if the MCS bit or SCS bit of the clock selection register (CKSCR) is rewritten, the
machine clock mode does not change immediately. For the operation of machine clock
based peripheral functions, reference the clock selection register (CKSCR) MCM and SCM
bits to confirm that the switch of the machine clock mode has been completed, then start to
operate the function.
In attempting to switch the clock mode, do not attempt to switch to another clock mode or
low-power consumption mode until the first switching is completed. The MCM and SCM bits
of the clock selection register (CKSCR) indicate that switching is completed.
If the SCS and MCS bits are both set to "0", SCS has priority, and the sub-clock mode
becomes enabled.
■ Selecting the PLL Clock Multiplication Ratio
By setting the CS1 and CS0 bits of the clock selection register (CKSCR) to 00B to 11B, one of
four PLL clock multiplication ratios (1 to 4) can be selected.
■ Machine Clock
The PLL clock oscillator’s divide-by-2 clock or sub-clock’s divide-by-4 clock, which is supplied
via the PLL multiplication circuit, is used as the machine clock. The clock pulses of the selected
machine clock are input to the CPU and peripheral functions. The main clock, PLL clock, or subclock can be selected by setting the MCS or SCS bits of the clock selection register (CKSCR).
Figure 5.4-1 "State transition diagram for the machine clock selection" shows the state
transitions by switching the machine clock.
127
CHAPTER 5 CLOCK
Figure 5.4-1 State transition diagram for the machine clock selection
Main
Sub
MCS =1
MCM =1
(9)
(10) SCS = 0
SCM = 1
CS1, CS0 = xx
(8)
Main
MCS = 1
MCM =1
SCS =1
SCM =1
(1)
CS1, CS0 = xx
(11)
(6)
Main
PLLx
MCS= 0
MCM =1
SCS = 0
SCM =1
(7) CS1, CS0=xx
PLL1
Main
MCS =1
MCM = 0
SCS =1
SCM =1
(7) CS1, CS0=00
PLL2
Main
MCS= 1
MCM =0
SCS =1
SCM =0
(7)
CS1, CS0 =01
(2)
(3)
(4)
Sub
Main
(9)
MCS= 1
MCM =1
SCS = 1
SCM =0
CS1, CS0 =xx
(5)
PLL1 multiplied
MCS =0
MCM = 0
(6)
CS1, CS0 =00 (16)
PLL2 multiplied
MCS =0
MCM =0
(6) CS1, CS0=01 (16)
PLL3
Main
MCS =1
MCM =0
SCS =1
SCM =0
(7)
CS1, CS0=10
PLL3 multiplied
MCS =0
MCM =0
(6) CS1, CS0 =10 (16)
Main
PLL4
MCS =1
MCM =0
SCS =1
(7) SCM =0
CS1, CS0 =11
PLL4 multiplied
MCS= 0
MCM =0
(6) CS1, CS0 =11 (16)
(16)
Sub
MCS = 1
MCM =1
(10) SCS =0
SCM =0
CS1, CS0 =xx
(12) Sub
PLLx
MCS =0
MCM= 1
(14) SCS =0
(15) SCM =1
CS1, CS0 = xx (17)
(13)
PLL1
Sub
MCS =1
MCM= 0
SCS =1
SCM= 1
CS1, CS0= 00 (17)
PLL2
Sub
MCS =1
MCM =0
SCS =1
SCM =0
CS1, CS0 =01
Sub
PLL3
MCS =1
MCM =0
SCS =1
SCM = 0
CS1, CS0 =10
(17)
(17)
PLL4
Sub
MCS = 1
MCM= 0
SCS =1
SCM =0
(17)
CS1, CS0 =11
(1) MCS bit set to "0"
(2) PLL clock oscillation stabilization wait completed. CS1, CS0=00
(3) PLL clock oscillation stabilization wait completed. CS1, CS0=01
(4) PLL clock oscillation stabilization wait completed. CS1, CS0=10
(5) PLL clock oscillation stabilization wait completed. CS1, CS0=11
(6) MCS bit: Set to "0" (including hardware standby and watchdog timer reset)
(7) Synchronous timing of PLL clock and main clock
(8) SCS bit set to "0"
(9) Synchronous timing of main clock and sub-clock
(10) SCS bit set to "1"
(11) Main clock oscillation stabilization wait completed
(12) Main clock oscillation stabilization wait completed. CS1, CS0=00
(13) Main clock oscillation stabilization wait completed. CS1, CS0=01
(14) Main clock oscillation stabilization wait completed. CS1, CS0=10
(15) Main clock oscillation stabilization wait completed. CS1, CS0=11
(16) SCS bit set to "0"
(17) Synchronous timing of PLL clock and sub-clock
: Machine clock selection bit in the clock selection register (CKSCR)
MCS
: Machine clock indication bit in the clock selection register (CKSCR)
MCM
: Machine clock indication bit (sub-clock or main clock) in the clock selection register (CKSCR)
SCM
: Machine clock selection bit (sub-clock or main clock) in the clock selection register (CKSCR)
SCS
CS1, CS0 : Multiplication ratio selection bit in the clock selection register (CKSCR)
Notes:
The machine clock is initially set to the main clock (CKSCR MCS=1, SCS=1).
If SCS and MCS are both set to "0", SCS has priority and the sub-clock is selected.
128
5.5 Oscillation stabilization wait time
5.5
Oscillation stabilization wait time
If, when the power is turned on or the stop mode is cancelled, clock mode switches
from the sub-clock to the main clock or PLL clock, an oscillation stabilization wait time
applies after oscillation starts because the oscillation clock is stopped. If the clock
mode is switched from the main clock to the PLL clock, an oscillation stabilization wait
time applies also after PLL oscillation starts.
■ Oscillation stabilization wait time
Ceramic and crystal resonators generally need a few to several dozen milliseconds before they
reach stable oscillation. Immediately after oscillation starts, CPU operation must be inhibited
until the oscillation stabilization wait time has elapsed. The clock can be supplied to the CPU
after the oscillation is stabilized. The stabilization time depends on the resonator type (e.g.,
crystal or ceramic). Select an appropriate oscillation stabilization wait time for the resonator
used by setting the clock selection register (CKSCR).
To switch from the main clock to the PLL clock, the main clock must be supplied to the CPU
until the PLL oscillation stabilization wait time has elapsed. Then, switch to the PLL clock.
Figure 5.5-1 "Operation soon after oscillation starts" shows the operation soon after oscillation
starts.
Figure 5.5-1 Operation soon after oscillation starts
Oscillation time of
resonator
Oscillation stabilization
wait time
(
Start of normal operation
or switching to PLL clock
)
X1
Oscillation start
Oscillation stabilization
129
CHAPTER 5 CLOCK
5.6
Connection of Resonator and External Clock
The MB90420G/425G series has a built-in system clock generation circuit and
generates a clock signal using an external resonator. It can also accept an external
clock.
■ Connection of Resonator and External Clock
❍ Example of connecting with crystal or ceramic resonator
Connect a crystal or ceramic resonator as shown in Figure 5.6-1 "Example of connecting with
crystal or ceramic resonator".
Figure 5.6-1 Example of connecting with crystal or ceramic resonator
X0 (X0A)
MB90420G/425G Series
X1 (X1A)
❍ Example of connecting an external clock
As shown in the example in Figure 5.6-2 "Example of connecting with external clock", connect
an external clock to the X0 (X0A) pin and keep the X1 (X1A) pin open.
Figure 5.6-2 Example of connecting with external clock
X0(X0A)
MB90420G/425G Series
Open
130
X1(X1A)
CHAPTER 6
LOW-POWER CONSUMPTION MODE
This chapter describes the low-power consumption mode.
6.1 "Outline of Low-Power Consumption Mode"
6.2 "Block Diagram of Low-Power Consumption Control Circuit"
6.3 "Low-Power Consumption Mode Control Register (LPMCR)"
6.4 "CPU Intermittent Operation Mode"
6.5 "Standby Mode"
6.6 "State Transition Diagram"
6.7 "Pin State in Standby Mode and During Reset"
6.8 "Notes on Using the Low-Power Consumption Mode"
131
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.1
Outline of Low-Power Consumption Mode
This mode is one of the CPU operation modes, as shown below. The mode is selected
by the operation clock selection and clock operation control.
• Clock mode (PLL clock, main clock, and sub-clock)
• CPU intermittent operation mode (PLL clock intermittent operation, main clock
intermittent operation, and sub-clock intermittent operation)
• Standby mode (sleep, timebase timer, clock, and stop)
■ CPU Operation Mode and Current Consumption
The relationship between the CPU operation mode and current consumption is shown in Figure
6.1-1 "CPU operation mode and current consumption".
Figure 6.1-1 CPU operation mode and current consumption
Current consumption
Several
dozen
milliampere
CPU operation
mode
PLL clock mode
Multiply-by-4 clock
Multiply-by-3 clock
Multiply-by-2 clock
Multiply-by-1 clock
Multiply-by-4 clock
PLL clock intermittent operation mode
Multiply-by-3 clock
Multiply-by-2 clock
Multiply-by-1 clock
Main clock mode (1/2 clock mode)
Main clock intermittent operation mode
Sub-clock mode
Sub-clock intermittent operation mode
Several
milliampere
Standby mode
Sleep mode
Timebase timer mode
Watch mode
Several
milliampere
Low-power consumption mode
Stop mode
Note: This diagram only shows a general representation of each mode. The actual current consumption may differ.
132
6.1 Outline of Low-Power Consumption Mode
■ Clock Modes
❍ PLL clock mode
Uses the PLL multiplication clock of the oscillation clock (HCLK) to drive the CPU and peripheral
functions.
❍ Main clock mode
Uses the divide-by-2 frequency of the oscillation clock (HCLK) to drive the CPU and peripheral
functions. In this mode, the PLL multiplication circuit stops operation.
❍ Sub-clock mode
Uses the divide-by-4 of the sub-clock (SCLK) to drive the CPU and peripheral functions. In this
mode, the main clock and PLL multiplication circuit stop operation.
Reference:
For the clock modes, see Section 5.4 "Clock Modes".
Note:
In attempting to switch the clock mode, do not attempt to switch to another clock mode or
low-power consumption mode until the first switching is completed. The MCM and SCM bits
of the clock selection register (CKSCR) indicate that switching is completed.
■ CPU Intermittent Operation Mode
This mode reduces the power consumption by running the CPU in the intermittent operation
mode while the clock pulses from the high-speed clock remain input to the peripheral functions.
In this mode, the CPU only receives the signals from the intermittent clock when it accesses the
registers, built-in memory, and peripheral function and makes external accesses.
133
CHAPTER 6 LOW-POWER CONSUMPTION MODE
■ Standby Mode
In standby mode, to reduce the power consumption, the low-power consumption control circuit
stops supplying the CPU with a clock signal (sleep mode), stops supplying the CPU and
peripheral function with a clock signal (timebase timer mode), or stops the oscillation clock (stop
mode).
❍ PLL sleep mode
The PLL sleep mode is used to stop the operation clock supplied to the CPU in PLL clock mode.
Signals from the PLL clock are input to devices other than the CPU.
❍ Main sleep mode
The main sleep mode is used to stop the CPU operation clock in main clock mode. Signals from
the main clock are input to devices other than the CPU.
❍ Sub-sleep mode
The sub-sleep mode is used to stop the CPU operation clock in sub-clock mode. Signals from
the sub-clock’s divide-by-4 clock are input to devices other than the CPU.
❍ Timebase timer mode
The timebase timer mode is used to stop operations other than the oscillation clock and
timebase timer. Functions other than the timebase timer and watch timer are stopped.
❍ Watch mode
This mode is used to operate the watch timer only. The sub-clock operates, while the main clock
and PLL multiplication circuit are stopped.
❍ Stop mode
The stop mode is used to stop the oscillator, causing all functions to stop.
Note:
In stop mode, the oscillation clock is stopped, and data can be saved with the lowest power
consumption possible.
134
6.2 Block Diagram of Low-Power Consumption Control Circuit
6.2
Block Diagram of Low-Power Consumption Control Circuit
The low-power consumption control circuit consists of seven blocks:
• CPU intermittent operation selector
• Standby control circuit
• CPU clock control circuit
• Peripheral clock control circuit
• Pin high-impedance control circuit
• Internal reset generation circuit
• Low-power consumption mode control register (LPMCR)
■ Block Diagram of the Low-Power Consumption Control Circuit
Figure 6.2-1 "Block diagram of low-power consumption control circuit" shows the block diagram
of the low-power consumption control circuit.
Figure 6.2-1 Block diagram of low-power consumption control circuit
Power saving mode control register (LPMCR)
Pin
Pin highimpedance
control circuit
Pin high-impedance control
Internal reset
generation
circuit
Internal reset
CPU intermittent
operation selector
Intermittent cycle selection
CPU clock
control circuit
CPU clock
Stop and sleep signals
Standby
control circuit
Stop signal
Machine clock
Oscillation stabilization
wait clear
Clock generation
section
Peripheral
clock control
circuit
Peripheral clock
Oscillation
stabilization
wait timer
selector
Clock selector
Divideby-4
PLL multiplication
circuit
System
clock
generation
circuit
Pin
Clock selection register (CKSCR)
Pin
Divideby-2
Pin
Divide-by1024
Divideby-2
Divideby-4
Divideby-4
Divideby-4
Divideby-2
Timebase timer
Pin
HCLK: Oscillation clock
To watchdog timer
MCLK: Main clock
SCLK: Sub-clock
135
CHAPTER 6 LOW-POWER CONSUMPTION MODE
❍ CPU intermittent operation selector
This circuit is used to select the temporary stop clock count for CPU intermittent operation
mode.
❍ Standby control circuit
This circuit is used to control the CPU clock control circuit and peripheral clock control circuit to
enter the low-power consumption mode or cancel it.
❍ CPU clock control circuit
This circuit is used to control the clock supplied to the CPU and peripheral clock control circuit
peripheral function.
❍ Peripheral clock control circuit
This circuit is used to control the clock supplied to the peripheral function.
❍ Pin high-impedance control circuit
This circuit is used to set the external pin to high-impedance in timebase timer mode and stop
mode. For a pin for which the pull-up option was selected, the pull-up resistor is disconnected in
stop mode.
❍ Internal reset generation circuit
This circuit is used to generate an internal reset signal.
❍ Low-power consumption mode control register (LPMCR)
This register is used to enter or cancel the standby mode and set the CPU intermittent operation
function.
136
6.3 Low-Power Consumption Mode Control Register (LPMCR)
6.3
Low-Power Consumption Mode Control Register (LPMCR)
The low-power consumption mode control register (LPMCR) is used to enter or cancel
the low-power consumption mode and set the CPU clock temporary stop cycle count
in CPU intermittent operation mode.
■ Low-Power Consumption Mode Control Register (LPMCR)
Figure 6.3-1 "Configuration of the low-power consumption mode control register (LPMCR)"
shows the configuration of the low-power consumption mode control register (LPMCR). Table
6.3-1 "Functional description of each bit in the low-power consumption mode control register
(LPMCR)" shows the functions of each bit.
Figure 6.3-1 Configuration of the low-power consumption mode control register (LPMCR)
Address bit15
0000A0H
bit8 bit7
(CKSCR)
STP
W
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
SLP SPL RST TMD CG1 CG0 RESV 00011000 B
W
R/W
W
R/W R/W R/W
Reserved bit
Always set this bit to "0".
RESV
CPU temporary stop clock count
selection bit
CG1 CG0
0
0
1
1
TMD
0
1
0
1
0
1
0-clock (CPU clock = peripheral clock)
8-clock (CPU clock: peripheral clock = 1: about 3 to 4)
16-clock (CPU clock: peripheral clock = 1: about 5 to 6)
32-clock (CPU clock: peripheral clock = 1: about 9 to 10)
Timebase timer mode bit
Puts operation into timebase timer mode
No action; does not affect other functions.
RST
Internal reset signal generation bit
0
1
Generates internal reset signal of 3 machine cycles
SPL
0
1
SLP
0
1
STP
0
1
R/W : Reading and writing permitted
W
: Only reading permitted
: Initial value
R/W
No action; does not affect other functions.
Pin state specification bit
For timebase timer, watch and stop modes
Retained
High impedance
Sleep bit
No action; does not affect other functions.
Puts operation into sleep mode
Stop bit
No action; does not affect other functions.
Puts operation into stop mode
137
CHAPTER 6 LOW-POWER CONSUMPTION MODE
Table 6.3-1 Functional description of each bit in the low-power consumption mode control register
(LPMCR)
Bit name
bit7
STP: Stop mode bit
Function
•
•
•
•
•
bit6
SLP: Sleep mode bit
bit5
SPL: Pin state setting bit
(Clock/timebase timer/stop
modes)
bit4
RST: Internal reset signal
generation bit
•
•
•
•
•
Indicates a transition to sleep mode.
Set this bit to "1" to enter sleep mode.
If set to "0", does not affect operation.
Cleared to "0" by reset, sleep clearing, or stop clearing. If the
STP bit and SLP bit are set to "1" at the same time, a transition
to stop mode occurs.
Read operations always return "0".
•
•
•
•
Only valid in timebase timer mode or stop mode.
If set to "0", the external pin level is retained.
If set to "1", the external pin is set to high-impedance.
Initialized to "0" by reset.
•
If set to "0", an internal reset signal of 3 machine cycles is
generated.
If set to "1", does not affect operation.
Read operations always return "1".
•
•
•
•
bit3
TMD: Watch/timebase
timer mode bit
•
•
•
•
bit2
bit1
bit0
CG1, CG0: Temporary stop
of CPU clock
Cycle count selection bit
RESV: Reserved bit
Indicates a transition to stop mode.
Set this bit to "1" to enter the stop mode.
If set to "0", does not affect operation.
Set to "0" by reset, timebase timer canceling, or stop
canceling.
Read operations always return "0".
•
•
•
Indicates a transition to watch mode or timebase timer mode.
If set to "0" in main clock mode or PLL clock mode, a transition
to timebase timer mode occurs.
If set to "0" in sub-clock mode, a transition to watch mode
occurs.
Initialized to "1" at reset or if an interrupt request is generated.
Read operations always return "1".
This bit is used to set the CPU clock’s temporary stop cycle
count of the CPU intermittent operation function.
Stops supplying signals from the CPU clock for the cycle count
specified for the individual instruction.
Selects one of four clock counts
Initialized to 00B at reset.
Always set this bit to "0".
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
stop mode, watch mode, or timebase timer mode, disable the output of peripheral functions,
and set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control
register (LPMCR).
The applicable pins are listed below.
P01/SOT0/INT5, P02/SCK0/INT6, P04/SOT1, P05/SCK1/TRG, P06/PPG0/TOT1,
P07/PPG1/TIN1, P10/PPG2, P11/TOT0/WOT
138
6.3 Low-Power Consumption Mode Control Register (LPMCR)
■ Accessing the Low-Power Consumption Mode Control Register
Writing to the low-power consumption mode control register causes a transition to a low-power
consumption mode (stop mode, sleep mode, timebase timer mode, or watch mode). For the
instructions used for transition to the low-power consumption mode, see Table 6.3-2
"Instructions applicable in transition to low-power consumption mode".
If instructions other than those in Table 6.3-2 "Instructions applicable in transition to low-power
consumption mode" are used for transition to the low-power consumption mode, operation is not
guaranteed. To control functions other than those in Table 6.3-1 "Functional description of each
bit in the low-power consumption mode control register (LPMCR)", any instruction can be used.
When writing to the low-power consumption mode control register with a length of words, use
even addresses only. Performing transition by using an odd address for writing may result in
operation errors.
❍ Priority of STP, SLP, and TMD bits
If a stop mode request, sleep mode request, and timebase timer mode request are executed at
the same time, the following priority is applied for processing.
Stop mode request > timebase timer mode request > sleep mode request
Table 6.3-2 Instructions applicable in transition to low-power consumption mode
MOV io, #imm8
MOV dir, #imm8
MOV eam, #imm8
MOV eam, Ri
MOV io, A
MOV dir, A
MOV addr, A
MOV eam, A
MOV @RLi+disp8, A
MOVP addr24, A
MOVW io, #imm16
MOVW dir, #imm16
MOVW eam, #imm16
MOVW eam, RWi
MOVW io, A
MOVW dir, A
MOVW addr16, A
MOVW eam, A
MOVW @RLi+disp8, A
MOVPW addr24, A
139
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.4
CPU Intermittent Operation Mode
The CPU intermittent operation mode reduces the power consumption by maintaining
high-speed operation for the external bus and peripheral functions while the CPU
operates in intermittent operation mode.
■ CPU Intermittent Operation Mode
In the CPU intermittent operation mode, the internal bus cycle start is delayed by stopping the
clock supply to the CPU for the time specified for the individual instruction when accessing a
register, built-in memory (ROM, RAM), I/O, peripheral function, or external bus. Maintaining high
clock speed for supply to the peripheral functions while reducing the operation speed of the
CPU enables processing with reduced power consumption.
Use the low-power consumption mode control register (CG1, CG0 of LPMCR) to select the
temporary stop cycle count for the CPU clock.
For operating the external bus, the same clock as for peripheral functions is used.
To obtain the instruction execution time when using the CPU intermittent operation mode, add
the normal execution time to an correction value obtained by multiplying the temporary stop
cycle count with the instruction execution count for accessing the register, built-in memory, builtin peripheral function, and external bus.
Figure 6.4-1 "Clock for CPU intermittent operation" shows the operation clock used in CPU
intermittent operation mode.
Figure 6.4-1 Clock for CPU intermittent operation
Peripheral clock
CPU clock
Temporary stop cycle
One
instruction
execution
cycle
Internal bus started
140
6.5 Standby Modes
6.5
Standby Modes
The standby modes consist of the sleep (PLL sleep, main sleep, and sub-sleep), clock,
and stop modes.
■ Operation in Standby Mode
Table 6.5-1 "Operation states in standby mode" shows the operation states in standby mode.
Table 6.5-1 Operation states in standby mode
Standby mode
Sleep
mode
PLL sleep
mode
SCS="1"
MCS="0"
SLP="1"
Main sleep
mode
SCS="1"
MCS="0"
SLP="1"
Subsleep
mode
SCS="0"
SLP="1"
Timebase
timer mode
Timebase (SPL = "0")
timer
Timebase
mode
timer mode
(SPL = "1")
Watch
mode
Stop
mode
Transition
condition
Main clock
Sub-clock
Machine
clock
CPU
Peripheral
Pin
Operation
Operation
Operation
Operation
Stop
SCS="1"
TMD="0"
Operation
Hold
Operation
Stop
SCS="0"
TMD="0"
Watch mode
(SPL = "1")
SCS="0"
TMD="0"
Stop mode
(SPL = "0")
STP="1"
Stop mode
(SPL = "1")
STP="1"
Reset
interrupt
Stop (*1)
SCS="1"
TMD="0"
Watch mode
(SPL = "0")
Cancel
method
Hi-z
Hold
Stop
Stop (*2)
Hi-z
Stop
Hold
Stop
Stop
Hi-z
*1: Timebase timer and watch timer operate.
*2: Watch timer operates.
SPL: Pin state specification bit in the low-power consumption mode control register (LPMCR)
SLP: Sleep bit in the low-power consumption mode control register (LPMCR)
STP: Clock stop bit in the low-power consumption mode control register (LPMCR)
TMD: Clock/timebase timer mode bit in the low-power consumption mode control register (LPMCR)
MCS: Machine clock selection bit in the clock selection register (CKSCR)
SCS: Machine clock selection bit (sub) in the clock selection register (CKSCR)
Hi-z: High-impedance
141
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.1
Sleep Mode
In sleep mode, the CPU operation clock stops and functions other CPU operations are
resumed. Specifying a transition to sleep mode via the low-power consumption mode
control register (LPMCR) changes the operation state to PLL sleep mode if the PLL
clock mode is set; to the main sleep mode, if the main clock mode is set; or to subsleep mode if the sub-clock mode is set.
■ Transition to Sleep Mode
Setting the low-power consumption mode control register (LPMCR) SLP bit to "1", the TMD bit
to "1", and the STP bit to "0" causes a transition to sleep mode. Transition to sleep mode
changes to PLL sleep mode if the clock selection register (CKSCR) is set to MCS=0; to PLL
sleep mode if set to SCS=1; to main sleep mode if set to MCS=1 and SCS=1; or to sub-sleep
mode if set to SCS=0.
Note:
When the SLP bit and STP bit are set to "1" at the same time, the STP bit has priority,
causing a transition to stop mode. When the SLP bit is set to "1" and the TMD bit is set to "0"
at the same time, the TMD bit has priority, causing a transition to timebase timer mode or
watch mode.
❍ Data hold function
In sleep mode, the contents of dedicated registers, such as the accumulator, and the internal
RAM contents are retained.
❍ Operation when an interrupt request occurs
Even if the low-power consumption mode control register (LPMCR) SLP bit is set to "1", no
transition occurs when an interrupt request is generated. In this case, the CPU executes the
next instruction when interrupts are disabled or immediately branches to the interrupt handling
routine when interrupts are enabled.
❍ Pin state
Pins retain their state in sleep mode.
■ Canceling Sleep Mode
The low-power consumption control circuit cancels sleep mode if a reset or an interrupt occurs.
❍ Return by reset
Reset initializes to main clock mode.
142
6.5 Standby Modes
❍ Return by interrupt
When in sleep mode an interrupt with a level of 7 or higher occurs, e.g. from a peripheral circuit,
sleep mode is cancelled. After the sleep mode is cancelled, the same processing as for a
normal interrupt is performed. When interrupts are enabled depending on the settings of the Iflag of the condition code register (CCR), the interrupt level mask register (ILM), and the
interrupt control register (ICR), the CPU performs interrupt processing. When interrupts
disabled, processing continues with the next instruction after the instruction by which sleep
mode was entered.
Figure 6.5-1 "Sleep mode canceled due to interrupt generation" shows the canceling of the
sleep mode by an interrupt generation.
Figure 6.5-1 Sleep mode canceled due to interrupt generation
Interrupt enable flag set
by the peripheral function
INT generated (IL<7)
NO
Sleep mode
not canceled
Sleep mode not canceled
YES
I
0
YES
Executing the next instruction
Sleep mode canceled
NO
ILM
IL
YES
Executing the next instruction
NO
Executing the interrupt
Note:
When interrupt processing is performed, processing will in ordinary cases continue with
interrupt handling after executing the instruction following the instruction by which sleep
mode was entered.
Figure 6.5-2 "Canceling sleep mode (external reset)" shows the operation for return from sleep
mode.
Figure 6.5-2 Canceling sleep mode (external reset)
RST pin
Sleep mode
Main clock
Oscillation mode
PLL clock
Oscillation mode
CPU clock
PLL clock
CPU operation
Stop mode
Sleep mode canceled
Reset sequence
Processing
Reset canceled
143
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.2
Timebase Timer Mode
The timebase timer mode is used to stop operations other than the operation of the
oscillator, timebase timer, and watch timer. All functions except for the timebase timer
and watch timer are stopped.
■ Transition to Timebase Timer Mode
If, in PLL clock mode or main clock mode (CKSCR SCS=1), the low-power consumption mode
control register (LPMCR) TMD bit is set to "0", a transition to timebase timer mode occurs.
❍ Data retention function
In timebase timer mode, the contents of dedicated registers such as the accumulator and the
internal RAM are retained.
❍ Operation during generation of an interrupt request
If the low-power consumption mode control register (LPMCR) TMD bit is set to "0", no transition
to timebase timer mode occurs when an interrupt request is generated.
❍ Pin state
Whether the external pin in the timebase timer mode retains the previous state or is set to highimpedance state can be controlled by the low-power consumption mode control register
(LPMCR) SPL bit.
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
timebase timer mode, disable the output of peripheral functions, and set the TMD bit to "0" in
the low-power consumption mode control register (LPMCR).
The applicable pins are listed below.
P01/SOT0/INT5, P02/SCK0/INT6, P04/SOT1, P05/SCK1/TRG, P06/PPG0/TOT1, P07/
PPG1/TIN1, P10/PPG2, P11/TOT0/WOT
144
6.5 Standby Modes
■ Canceling Timebase Timer Mode
The low-power consumption control circuit is used to cancel the timer-base timer mode when a
reset or an interrupt occurs.
❍ Return by reset
Reset initializes to main clock mode.
❍ Return by interrupt
When in sleep mode an interrupt with a level of 7 or higher occurs, e.g. from a peripheral circuit,
(interrupt control register ICR: IL2, IL1, and IL0 are other than 111B), the low-power
consumption control circuit will cancel the timebase timer mode. The operation performed after
the timebase timer mode is canceled is the same as for normal interrupt handling. When
interrupts are enabled depending on the settings of the I-flag of the condition code register
(CCR), the interrupt level mask register (ILM), and the interrupt control register (ICR), interrupt
processing is performed. If interrupts are disabled, processing continues from the next
instruction before entering the timebase timer mode.
Note:
When interrupt processing is performed, processing will in ordinary cases continue with
interrupt handling after executing the instruction following the instruction by which timebase
timer mode was entered. If, however, transition to timebase timer mode and the acceptance
of an external bus hold request occur at the same time, a transition to interrupt handling may
occur prior to the execution of the next instruction.
Figure 6.5-3 "Canceling the timebase timer mode (external reset)" shows the operation for
return from timebase timer mode.
Figure 6.5-3 Canceling the timebase timer mode (external reset)
RST pin
Timebase timer mode
Main clock
Oscillation mode
PLL clock
Oscillation stabilization wait
CPU clock
Main clock
CPU operation
Stop mode
Reset sequence
Oscillation mode
PLL clock
Processing
Reset cleared
Watch mode canceled
145
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.3
Watch Mode
This mode is used to stop operations other than operations of the sub-clock and watch
timer. Most chip functions are stopped in this mode.
This mode is only available for the MB90F423GB/GC, MB90F428GB/GC, MB90423GB/
GC, MB90427GB/GC, MB90428GB/GC series.
■ Transition to Watch Mode
A transition to watch mode occurs if, in sub-clock mode (CKSCR: SCS=0), the low-power
consumption mode control register (LPMCR) TMD bit is set to "0".
❍ Data retention function
In watch mode, the contents of dedicated registers, such as the accumulator, and the contents
of internal RAM are retained.
❍ Operation during generation of an interrupt request
If the low-power consumption mode control register (LPMCR) TMD bit is set to "0", no transition
to the watch mode occurs when an interrupt request is generated.
❍ Pin states
Whether the external pin retains in watch mode its previous state or enters high-impedance
state can be controlled by the SPL bit of the low-power consumption mode control register
(LPMCR).
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
watch mode, disable the output of peripheral functions, and set the TMD bit to "0" in the lowpower consumption mode control register (LPMCR).
The applicable pins are listed below.
P01/SOT0/INT5, P02/SCK0/INT6, P04/SOT1, P05/SCK1/TRG, P06/PPG0/TOT1, P07/
PPG1/TIN1, P10/PPG2, P11/TOT0/WOT
146
6.5 Standby Modes
■ Canceling Watch Mode
The low-power consumption control circuit is used to cancel watch mode when a reset or an
interrupt occurs.
❍ Return by reset
Canceling the watch mode by a reset causes a transition to the oscillation stabilization wait
reset state after the watch mode is canceled. The reset sequence is executed after the
oscillation stabilization wait time has elapsed.
❍ Return by interrupt
If, in watch mode, an interrupt request with an interrupt level of 7 or higher occurs, e.g. from a
peripheral circuit, (interrupt control register ICR: IL2, IL1, and IL0 are other than 111B), the lowpower consumption control circuit will cancel the watch mode and immediately enter sub-clock
mode. The operation performed after entering sub-clock mode is the same as in normal
interrupt handling. When interrupts are enabled depending on the settings of the I-flag of the
condition code register (CCR), the interrupt level mask register (ILM), and the interrupt control
register (ICR), interrupt processing is performed. If interrupts are disabled, processing continues
from the next instruction before entering the timebase timer mode.
Note:
When interrupt processing is performed, processing will in ordinary cases continue with
interrupt handling after executing the instruction following the instruction by which watch
mode was entered.
Figure 6.5-4 "Canceling the watch mode (external reset)" shows the operation for return from
watch mode.
Figure 6.5-4 Canceling the watch mode (external reset)
RST pin
Watch mode
Main clock
Oscillation stabilization wait
PLL clock
Stop mode
Sub-clock
Oscillation mode
Main clock
CPU clock
CPU operation
Oscillation mode
Stop mode
Reset sequence Processing
Reset cleared
Watch mode canceled
147
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.5.4
Stop Mode
The stop mode is used to stop the oscillator and stop all functions. It allows retaining
the data with the lowest power consumption possible.
■ Transition to Stop Mode
Setting the low-power consumption mode control register (LPMCR) STP bit to "1" causes a
transition to the stop mode.
❍ Data hold function
In stop mode, the contents of dedicated registers, such as the accumulator, and the contents of
internal RAM are retained.
❍ Operation during generation of an interrupt request
If the low-power consumption mode control register (LPMCR) STP bit is set to "1", no transition
to stop mode occurs when an interrupt request is generated.
❍ Pin states
Whether the external pin retains its previous state in stop mode or enters high-impedance state
can be controlled by the SPL bit of the low-power consumption mode control register (LPMCR).
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
stop mode, disable the output of peripheral functions, and set the STD bit to "1" in the lowpower consumption mode control register (LPMCR).
The applicable pins are listed below.
P01/SOT0/INT5, P02/SCK0/INT6, P04/SOT1, P05/SCK1/TRG, P06/PPG0/TOT1, P07/
PPG1/TIN1, P10/PPG2, P11/TOT0/WOT
148
6.5 Standby Modes
■ Canceling Stop Mode
The low-power consumption control circuit is used to cancel the stop mode when a reset or
interrupt occurs. At return from stop mode, since the operation clock has stopped, the lowpower consumption control circuit changes to the oscillation stabilization wait state and then
cancels the stop mode.
❍ Return by reset
Canceling the stop mode by a reset causes a transition to the oscillation stabilization wait reset
state after the stop mode is canceled. The reset sequence is executed after the oscillation
stabilization wait time has elapsed.
❍ Return by interrupt
If, in the stop mode, an interrupt request with an interrupt level of 7 or higher occurs (interrupt
control register ICR: IL2, IL1, and IL0 are other than 111B), the low-power consumption control
circuit cancels the stop mode. Then, after the oscillation stabilization wait time specified by the
WS1/WS0 bits of the clock selection register (CKSCR) has elapsed, the same operation as in
normal interrupt handling is performed. When interrupts are enabled depending on the settings
of the I-flag of the condition code register (CCR), the interrupt level mask register (ILM), and the
interrupt control register (ICR), interrupt processing is performed. If interrupts are disabled,
processing continues from the next instruction before entering the stop mode.
Note:
When interrupt processing is performed, processing will in ordinary cases continue with
interrupt handling after executing the instruction following the instruction by which stop mode
was entered. If, however, transition to stop mode and acceptance of an external bus hold
request occur at the same time, transition to interrupt handling may occur before the next
instruction is executed.
Figure 6.5-5 "Canceling the stop mode (external reset)" shows the operation for return from stop
mode.
Figure 6.5-5 Canceling the stop mode (external reset)
RST pin
Stop mode
Main clock
Oscillation stabilization wait
PLL clock
Stop mode
Main clock
CPU clock
CPU operation
Oscillation mode
Stop mode
Reset sequence Processing
Reset cleared
Stop mode canceled
149
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.6
State Transition Diagram
Figure 6.6-1 "State transition diagram" shows the transition diagram for the operation
mode and the transition conditions for the MB90420G/425G series.
■ State Transition Diagram
Figure 6.6-1 State transition diagram
Power applied
Power-on reset
Power voltage lowered
External reset, watchdog timer reset, CPU
operation detection reset, software reset
Low-voltage
detection reset
*1
Reset
End of oscillation
stabilization wait
SCS=1
SCS=0
End of oscillation
stabilization wait
SCS=0
MCS=0
Main clock mode
MCS=1
SLP=1
Interrupt
Main sleep mode
TMD=0
Interrupt
Timebase timer mode
SCS=1
SLP=1
Interrupt
PLL sleep mode
TMD=0
Interrupt
Timebase timer mode
Main stop mode
End of oscillation
stabilization wait
Main clock oscillation
stabilization wait
PLL stop mode
Interrupt
SLP=1
Interrupt
Subsleep mode
TMD=0
Interrupt
Watch mode
STP=1
STP=1
STP=1
Interrupt
Sub-clock mode
PLL clock mode
End of oscillation
stabilization wait
PLL clock oscillation
stabilization wait
Subsleep mode
Interrupt
End of oscillation
stabilization wait
Sub-clock oscillation
stabilization wait
*1: This mode is only available for the MB90F423GB/GC, MB90F428GB/GC, MB90423GB/GC, MB90427GB/GC, MB90428GB/GC.
150
6.6 State Transition Diagram
■ Operation States of the Low-Power Consumption Mode
Table 6.6-1 "Operation states of the low-power consumption mode" shows the operation states
of the low-power consumption mode.
Table 6.6-1 Operation states of the low-power consumption mode
Operation state
Main
clock
Subclock
PLL
clock
PLL
CPU
Peripheral
Clock
timebase
timer
clock
Operation
Operation
Stop
Stop
Operation
Operation
Operation
Operation
Clock
source
Operation
Operation
PLL sleep
Operation
Operation
Operation
Stop
Stop
Stop
Operation
Operation
Operation
Timebase timer (*1)
PLL stop
PLL oscillation
stabilization wait
PLL clock
Stop
Stop
Operation
Main
Operation
Main sleep
Operation
Operation
Timebase timer (*2)
Main stop
Main oscillation
stabilization wait
Main
clock
Stop
Stop
Stop
Operation
Operation
Stop
Stop
Sub
Stop
Stop
Operation
Operation
Operation
Operation
Subsleep
Clock
Operation
Stop
Sub stop
Stop
Stop
Stop
Sub oscillation
stabilization wait
Stop
Operation
Power-on reset
Stop
Sub-clock
Operation
Main
clock
Stop
Operation
Stop
Operation
Reset
Operation
Operation
Stop
Operation
Stop
Operation
*1: PLL clock mode
*2: Main clock mode
151
CHAPTER 6 LOW-POWER CONSUMPTION MODE
6.7
Pin States in Standby Mode and During Reset
This section shows the pin states in standby mode and during reset for each memory
access mode.
■ Pin States in Single-Chip Mode
Table 6.7-1 "Pin states in single-chip mode" shows the pin states in single-chip mode.
Table 6.7-1 Pin states in single-chip mode
Standby mode
Pin name
Sleep mode
Stop mode/watch mode/timebase timer
mode
SPL=0
P00 to P07
P10 to P15
P36 to P37
P40 to P47
P50 to P57
P60 to P67
P90 to P91
Retaining the
previous state (*2)
Retaining the
previous state (*2)
During a Reset
SPL=1
Input cutoff (*3)/
output Hi-z
Input disabled (*4)/
output Hi-z
Input disabled (*4)/
output "L"
P70 to P77
P80 to P87
Input allowed (*1)
(allowed during external interrupt)
P00 to P03
P50 to P53
Input disabled (*4)/
output Hi-z
*1: "Input allowed" means that the input function is available and selection of pull-up/pull-down options or an
external input is required. When used as an output port, the same operation as for other ports applies.
*2: "Retaining the previous state" means that the output state immediately before entering this mode is
retained. However, note that input may become disabled even if inputs were enabled before entering this
mode. "Retaining the output state as is" means retaining the value for a built-in peripheral circuit that was
in operation at the time of the output, retaining the state of ports that were in operation for the output etc..
*3: "Input cutoff " means that operation of an input gate adjacent to the pin is prohibited. "Output Hi-z" means
that the pin-drive transistor is set to the drive-prohibited state and the pin is set to high-impedance.
*4: "Input disabled" means that operation of the input gate adjacent to the pin is permitted, but because the
internal circuits are not operating, the input to the pin is not accepted internally.
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
stop mode, watch mode, or timebase timer mode, disable the output of peripheral functions,
and set the STP bit to "1" or TMD bit to "0" in the low-power consumption mode control
register (LPMCR).
The applicable pins are listed below.
P01/SOT0/INT5, P02/SCK0/INT6, P04/SOT1, P05/SCK1/TRG, P06/PPG0/TOT1,
P07/PPG1/TIN1, P10/PPG2, P11/TOT0/WOT
152
6.8 Notes on Using the Low-Power Consumption Mode
6.8
Notes on Using the Low-Power Consumption Mode
Pay special attention on the following items when using the low-power consumption
mode:
• Transition to standby mode and interrupts
• Notes on Transition to Standby Mode
• Canceling the standby mode by interrupt
• Canceling the stop mode
• Oscillation stabilization wait time
• Switching the clock mode
■ Transition to Standby Mode and Interrupts
If a peripheral function generates an interrupt request to the CPU, the settings in the low-power
consumption mode control register (LPMCR: STP=1, SLP=1) or (LPMCR: TMD=0) are ignored,
and no transition to standby mode occurs (not even after interrupt handling). Provided the
interrupt level is higher than 7, it does not matter whether the interrupt request is accepted by
the CPU.
Even if the CPU is currently processing interrupt handling, a transition to standby mode is
allowed as long as the interrupt request flag bit is cleared and there are no other interrupt
requests.
■ Notes on Transition to Standby Mode
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
stop mode, watch mode, or timebase timer mode, follow the procedure below.
1. Disable the output of peripheral functions.
2. Set the SPL bit to "1", STP bit to "1", or TMD bit to "0" in the low-power consumption mode
control register (LPMCR).
153
CHAPTER 6 LOW-POWER CONSUMPTION MODE
■ Canceling the Standby Mode by an Interrupt
In sleep mode, timebase timer mode, or stop mode, the standby mode is canceled if a
peripheral function generates an interrupt request with an interrupt level of 7 or higher. Whether
the CPU accepts the interrupt does not matter.
After canceling the standby mode, branching to the interrupt handling routine occurs under the
same conditions as for a normal interrupt operation: Branching occurs if the interrupt request’s
priority as specified in the corresponding interrupt level setting bits (ICR: IL2, IL1, IL0) is higher
than the priority specified in the interrupt level mask register (ILM) and the condition code
register’s interrupt enable flag is set to "enabled" (CCR: I=1).
If interrupts are not accepted, the operation resumes with the instruction after the one specifying
standby mode.
When interrupt processing is performed, processing will in ordinary cases continue with interrupt
handling after executing the instruction following the instruction by which the standby mode was
entered.
However, depending on the condition causing the transition to standby mode, transition to
interrupt handling may occur before that instruction is executed.
In cases where branching to the interrupt handling routine does not occurs immediately after the
return, measures must be established to disable interrupts before the standby mode is set.
■ Canceling the Stop Mode
Before the stop mode is entered, it can be cancelled by an input according to the settings for
external interrupt sources. H level, L level, rising edge or falling edge can be selected for input.
■ Oscillation stabilization wait time
❍ Oscillation stabilization wait time of the oscillation clock
Because the oscillator stops operation in stop mode, it is necessary to specify an oscillation
stabilization wait time via the WS1/WS0 bits of the clock selection register (CKSCR). Set the
WS1 and WS0 bits to 00B only if main clock mode is used.
❍ PLL clock oscillation stabilization wait time
If the CPU is driven by the main clock, the PLL clock is stopped. If it is necessary to enter the
mode in which CPU or peripherals are driven by the PLL clock, operation first enters the PLL
clock oscillation stabilization wait state. During PLL clock oscillation stabilization wait, operation
is still driven by the main clock.
The PLL clock oscillation stabilization wait time is fixed to 214/HCLK (HCLK: Oscillation clock
frequency).
■ Switching the clock mode
In attempting to switch the clock mode, do not attempt to switch to another clock mode or lowpower consumption mode until the first switching is completed. The MCM and SCM bits of the
clock selection register (CKSCR) indicate that switching is completed.
154
CHAPTER 7
MODE SETTINGS
This chapter describes the operation mode and memory access mode.
7.1 "Setting the Mode"
7.2 "Mode Pins (MD2 to MD0)"
7.3 "Mode Data"
155
CHAPTER 7 MODE SETTINGS
7.1
Setting the Mode
F2MC-16LX provides several modes with respect to access methods and access areas.
Each mode can be set by setting mode pins during a reset and fetching mode data in a
mode fetching operation.
■ Mode Setting
F2MC-16LX provides several modes with respect to access methods and access areas. The
modes of this module can be classified as shown in Figure 7.1-1 "Mode classification".
Figure 7.1-1 Mode classification
Operation modes
Bus modes
RUN mode
Single chip mode
FLASH write mode
■ Operation Modes
The operation modes control the device operation states, which are specified by a pin for setting
the mode (MDx) and the Mx bits in the mode data. Selecting the operation mode allows normal
operation to start.
■ Bus Mode
The bus mode controls the operations of the internal ROM and the external access function,
which are specified by a pin (MDx) for setting the mode and the Mx bits in the mode data. The
pin for setting the mode (MDx) is used to specify the bus mode for reading the reset vector and
mode data. The Mx bit in the mode data is used to specify the bus mode for normal operation.
■ RUN Mode
The run mode is the CPU operation mode. It includes various low-power consumption modes in
addition to the main clock mode and PLL clock mode. For further information, refer to Chapter 6,
"LOW-POWER CONSUMPTION MODE."
156
7.2 Mode pins (MD2 to MD0)
7.2
Mode pins (MD2 to MD0)
The mode pins are three external pins, MD2 to MD0, which are used to specify how to
acquire the reset vector and mode data.
■ Mode pins (MD2 to MD0)
The mode pins are used to select whether the external or internal data bus is used to read the
reset vector and for selecting the bus width during selection of the external data bus. In case of
a FLASH ROM built-in product, the mode pins are used to specify the FLASH ROM write mode
for writing information such as a program to the built-in ROM. The settings of the mode pins are
shown in Table 7.2-1 "Mode pin settings".
Table 7.2-1 Mode pin settings
MD2
MD1
MD0
0
0
0
0
0
1
0
1
1
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Mode name
Reset vector
access area
External
data bus
width
Description
Setting prohibited
Internal
vector mode
Internal
Mode data
Controlled by mode data after
reset sequence
Setting prohibited
Flash writer
write mode
−
−
−
MD2 to MD0: Set to 0 = VSS and 1= VCC.
Note:
In the MB90420G/425G series, only single-chip mode is used. Set MD2, 1 and 0 to "011".
157
CHAPTER 7 MODE SETTINGS
7.3
Mode Data
The mode data, which is used to specify the operation during the reset sequence, is
located in the memory at FFFFDFH. The mode data is automatically loaded into the
CPU with a mode fetch operation.
■ Mode Data
During the reset sequence, the mode data at FFFFDFH is read into the mode register of the
CPU core. The mode data is used to specify the memory access mode. The contents of the
mode register can be modified only by the reset sequence. Mode data becomes valid after the
reset sequence. Figure 7.3-1 "Configuration of mode data" shows the configuration of mode
data.
Figure 7.3-1 Configuration of mode data
Mode data
7
6
5
4
3
2
1
0
M1
M0
0
0
0
0
0
0
Function extension bits (reserved area)
Bus mode set bits
■ Bus Mode Setting Bits
These bits are used to specify the operation mode after the reset sequence has been
completed. The functions of these bits are shown inTable 7.3-1 "Functions of bus mode setting
bits".
Table 7.3-1 Functions of bus mode setting bits
M1
M0
Function
0
0
Single-chip mode
0
1
1
0
1
1
Description
(Setting prohibited)
Note:
For the MB90420G/425G series, only used in the single-chip mode. Set M1 and 0 to "00".
The relationship between the access area and physical address in single-chip mode is shown in
Figure 7.3-2 "Relationship between access area and physical address in single-chip mode".
158
7.3 Mode Data
Figure 7.3-2 Relationship between access area and physical address in single-chip mode
ROM
ROM
If the ROM mirroring function is selected
RAM
: No access
: Internal access
Note : "#x depending on product type" indicates an address specified
depending on the product type.
■ Relationship Between Mode Pins and Mode Data
Table 7.3-2 "Relationship between mode pins and mode data" shows the relationship between
the mode pins and mode data.
Table 7.3-2 Relationship between mode pins and mode data
Mode
MD2
MD1
MD0
M1
M0
Single-chip mode
0
1
1
0
0
Note:
For the MB90420G/425G series, used only in single-chip mode.
159
CHAPTER 7 MODE SETTINGS
160
CHAPTER 8
I/O PORTS
This chapter describes the functions and operation of the I/O ports.
8.1 "I/O Ports"
8.2 "Assignment of Registers and Pins Shared with External Pins"
8.3 "Port 0"
8.4 "Port 1"
8.5 "Port 3"
8.6 "Port 4"
8.7 "Port 5"
8.8 "Port 6"
8.9 "Port 7"
8.10 "Port 8"
8.11 "Port 9"
8.12 "Example Program for I/O Ports"
161
CHAPTER 8 I/O PORTS
8.1
I/O Ports
The I/O ports are used as general-purpose input/output ports (parallel I/O ports). The
number of ports for the MB90420G/425G series is 9 (58 pins). Each port is used both
for peripheral functions and for providing input/output pins.
■ I/O Port Functions
The I/O ports use the port data register (PDR) to receive data from the CPU and then outputting
it to the I/O pins or to obtain the input from the I/O pins and then write it to the CPU. The port
uses the port direction register (DDR) to set the I/O pins’ input/output direction in units of
individual bits. The functions of each port/ peripheral function are listed below.
•
Port 0:
Used as general-purpose input/output port or for peripheral functions (external interrupt input
pin/UART/PPG)
•
Port 1:
Used as general-purpose input/output port or for peripheral functions (PPG/reload timer/
watch timer/ICU)
•
Port 3:
Used as general-purpose input/output port or for peripheral functions (LCD)
•
Port 4:
Used as general-purpose input/output port or for peripheral functions (LCD)
•
Port 5:
Used as general-purpose input/output port or for peripheral functions (external interrupt input
pin/CAN/sound generator)
•
Port 6:
Used as general-purpose input/output port or for peripheral functions (analog input pin)
•
Port 7:
Used as general-purpose input/output port or for peripheral functions (stepping motor
controller)
•
Port 8:
Used as general-purpose input/output port or for peripheral functions (stepping motor
controller)
•
Port 9:
Used as general-purpose input/output port or for peripheral functions (LCD)
162
8.1 I/O Ports
Table 8.1-1 "Port functions" shows the functions of each port.
Table 8.1-1 Port functions
Port
name
Pin
name
Port 0
P00/SIN0/INT4
to
P07/PPG1
Port 1
Port 3
Port 4
Port 5
P10/PPG2
to
P15/IN0
P36/SEG12
to
P37/SG13
P40/SEG14
to
P47/SEG21
Type
of
output
Type of
input
Function
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
General-purpose input/output port
Peripheral function
General-purpose input/output port
CMOS
(hysteresis)
(automotive
level*)
Peripheral function
General-purpose input/output port
Peripheral function
P37
P36
SEG13
SEG12
P15
P14
P13
IN0
IN1
IN2
P12
P11
P10
IN3
WOT
PPG2
TIN
TOT
General-purpose input/output port
Peripheral function
General-purpose input/output port
P50/INT0
to
P57/SGA
CMOS
analog
P60/AN0
CMOS
(hysteresis)
to
(automotive
level*)
67/AN7
P70/PWM1P0
Port 7
to
P77/PWM2M1
P80/PWM1P2
CMOS
Port 8
to
(hysteresis)
P87/PWM2M3 (automotive
level*)
P90/SEG22
Port 9
to
P91/SEG23
Port 6
Peripheral function
P57
P56
P55
P54
P53
P52
P51
P50
SGA
SGO
RX0
TX0
INT3
INT2
INT1
INT0
TX1
RX1
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P07
P06
P05
P04
P03
P02
P01
P00
PPG1
PPG0
SCK1
SOT1
SIN1
SCK0
SOT0
SIN0
INT7
INT6
INT5
INT4
P47
P46
P45
P44
P43
P42
P41
P40
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
General-purpose input/output port
P67
P66
P65
P64
P63
P62
P61
P60
Peripheral function
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
P87
P86
P85
P84
P83
P82
P81
P80
General-purpose input/output port
Peripheral function
P77
P76
P75
P74
P73
P72
P71
P70
PWM2M1 PWM2P1 PWM1M1 PWM1P1 PWM2M0 PWM2P0 PWM1M0 PWM1P0
General-purpose input/output port
PWM2M3 PWM2P3 PWM1M3 PWM1P3 PWM2M2 PWM2P2 PWM1M2 PWM1P2
Peripheral function
General-purpose input/output port
Peripheral function
P91
P90
SEG23
SEG22
* : "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL CHARACTERISTICS").
Note:
Port 6 is also used as analog input pin. If used as a general-purpose port, always set the
corresponding analog input enable register (ADER) bit to "0". At a reset, the ADER bit is
initialized to "1".
163
CHAPTER 8 I/O PORTS
8.2
Assignment of Registers and Pins Shared with External
Pins
The registers related to I/O port setting are listed below.
■ I/O Port Registers
Table 8.2-1 "Port registers" shows the port registers.
Table 8.2-1 Port registers
Register name
Read/write
Address
Initial value
Port 0 data register (PDR0)
R/W
000000H
XXXXXXXXB
Port 1 data register (PDR1)
R/W
000001H
--XXXXXXB
Port 3 data register (PDR2)
R/W
000003H
XX------B
Port 4 data register (PDR3)
R/W
000004H
XXXXXXXXB
Port 5 data register (PDR5)
R/W
000005H
XXXXXXXXB
Port 6 data register (PDR6)
R/W
000006H
XXXXXXXXB
Port 7 data register (PDR7)
R/W
000007H
XXXXXXXXB
Port 8 data register (PDR8)
R/W
000008H
XXXXXXXXB
Port 9 data register (PDR9)
R/W
000009H
------XXB
Port 0 direction register (DDR0)
R/W
000010H
00000000B
Port 1 direction register (DDR1)
R/W
000011H
--000000B
Port 3 direction register (DDR3)
R/W
000013H
00------B
Port 4 direction register (DDR4)
R/W
000014H
00000000B
Port 5 direction register (DDR5)
R/W
000015H
00000000B
Port 6 direction register (DDR6)
R/W
000016H
00000000B
Port 7 direction register (DDR7)
R/W
000017H
00000000B
Port 8 direction register (DDR8)
R/W
000018H
00000000B
Port 9 direction register (DDR9)
R/W
000019H
------00B
Analog input enable register (ADER)
R/W
00001AH
11111111B
R/W: Reading and writing permitted
R: Read-only
X: Unspecified value
-: Undefined
164
8.3 Port 0
8.3
Port 0
Port 0 is a general-purpose input/output port and also used for input/output of the
peripheral functions. For each pin, use for a peripheral function or as port is switched
in units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 0.
■ Configuration of Port 0
Port 0 consists of three elements:
•
General-purpose input/output pins and peripheral function input/output pins (P00/SIN0/INT4
to P07/PPG1/TIN1)
•
Port 0 data register (PDR0)
•
Port 0 direction register (DDR0)
■ Port 0 pins
Port 0 pins are used both for peripheral functions and as general-purpose input/output pins. If
these pins are used as peripheral function input/output pins, they must not be used as generalpurpose input/output ports. Table 8.3-1 "Port 0 pins" shows the pins of Port 0.
Table 8.3-1 Port 0 pins
Port
name
Port 0
Type of Input/Output
Pin name
Port function
Input
P00/SIN0/INT4
P00
SIN0
P01/SOT0/INT5
P01
SOT0
P02/SCK0/INT6
P02
SCK0
INT6
P03/SIN1/INT7
P03
SIN1
INT7
P04/SOT1
P04
P05/SCK1/TRG
P05
SCK1
P06/PPG0/
TOT1
P06
PPG0
P07/PPG1/TIN1
P07
Generalpurpose
input/output
Output
Circuit
type
CMOS
G
Peripheral function
SOT1
INT4
UART0
UART1
INT5
−
−
TRG
PPG
TOT1
Reload
timer
PPG
PPG1
External
interrupt
input
CMOS
(hysteresis)
(automotive
level (*))
TIN1
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the circuit type, refer to Section 1.7 "Types of Input/Output Circuits".
165
CHAPTER 8 I/O PORTS
■ Pin Block Diagram for Port 0
Figure 8.3-1 "Pin block diagram for Port 0" shows the pin block diagram for Port 0.
Figure 8.3-1 Pin block diagram for Port 0
Peripheral function output
Peripheral function input
Peripheral function output enabled
PDR (Port data register)
Internal data bus
PDR read
Output
latch
PDR write
Pin
DDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
■ Registers for Port 0
The Port 0 registers are PDR0 and DDR0. The register bits have a one-to-one correspondence
with the pins of Port 0. Table 8.3-2 "Correspondence between registers and pins for Port 0"
shows the correspondence between the registers and pins for Port 0.
Table 8.3-2 Correspondence between registers and pins for Port 0
Port name
Bit of related register and its corresponding pin
PDR0,DDR0
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P07
P06
P05
P04
P03
P02
P01
P00
Port 0
166
8.3 Port 0
8.3.1
Port 0 registers (PDR0, DDR0)
This section describes the registers for Port 0.
■ Function of Port 0 Register
❍ Port 0 data register (PDR0)
The PDR0 register indicates the pin states.
❍ Port 0 direction register (DDR0)
The DDR0 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0".
Notes:
•
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," the pin works as a peripheral
function output pin whatever the DDR0 register’s setting.
•
If a peripheral function with an input pin is used, set the DDR0 register bit corresponding to
each peripheral function’s input pin to "0" to make it work as an input pin.
Table 8.3-3 Functions of Port 0 registers
Register
name
Data
At writing
Pin state: L
level
Sets the output latch to "0."
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1."
Outputs H level if used as an
output port.
0
Direction latch
set to "0"
Sets the output level to OFF
to use it as an input port.
1
Direction latch
set to "1"
Sets the output level to ON
to use it as an output port.
0
Port 0 data
register
(PDR0)
Port 0
direction
register
(DDR0)
At reading
Initial value
R/W
Address
R/W
000000H
XXXXXXXXB
R/W
000010H
00000000B
R/W: Reading and writing permitted
X: Unspecified value
167
CHAPTER 8 I/O PORTS
8.3.2
Description of Port 0 Operation
This section describes the operation of Port 0.
■ Operation of Port 0
❍ Operation as an output port
With the corresponding DDR0 register bit set to "1," the port works as an output port.
When used as an output port, any data written to the PDR0 register is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR0 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, write the output data to the PDR register and then write "1" to the DDR register.
❍ Operation as an input port
With the corresponding DDR0 register bit set to "0", the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR0 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR0 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR0 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Operation for peripheral function input
For a port that is also used for peripheral function input, the pin value is always used as input to
the peripheral function. To use an external signal as input for the peripheral function, set the
DDR0 register for the input port to "0."
❍ Reset operation
At CPU reset, the value of the DDR0 register is initialized to "0". Thus, all the output buffers are
set to "OFF" (input port) and the pins are set to "high-impedance."
In a reset operation, the PDR0 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR0 register and then set the corresponding DDR0 register to output.
168
8.3 Port 0
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR0 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.3-4 "States of Port 0 pins" shows the states of Port 0 pins.
Table 8.3-4 States of Port 0 pins
Pin name
P00/SIN0/INT4 to
P07/PPG1/TIN1
P00/SIN0/INT4 to
P03/SIN1/INT7
(Set to external
interrupt)
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Input cut-off/
output Hi-z
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Input enabled/
output Hi-z
Stop mode,
timebase timer
mode (SPL=1)
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
stop mode, watch mode, or timebase timer mode, disable the output of peripheral functions,
and set the STP bit to "1" or TMD bit to 0 in the low-power consumption mode control
register (LPMCR).
The applicable pins are listed below.
P01/SOT0/INT5, P02/SCK0/INT6, P04/SOT1, P05/SCK1/TRG, P06/PPG0/TOT1, P07/
PPG1/TIN1
169
CHAPTER 8 I/O PORTS
8.4
Port 1
Port 1 is used as both a general-purpose input/output port and for peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 1.
■ Port 1 configuration
Port 1 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P10/PPG2 to P15/IN0)
•
Port 1 data register (PDR1)
•
Port 1 direction register (DDR1)
■ Port 1 pins
Port 1 pins are used both for peripheral functions and as general-purpose input/output pins. If
used as peripheral function input/output pins, they must not be used as general-purpose input/
output ports. Table 8.4-1 "Port 1 pins" shows the pins of Port 1.
Table 8.4-1 Port 1 pins
Port
name
Port 1
Type of input/output
Pin name
Port function
Input
P10/PPG2
P10
P11/TOT0/
WOT
P11
P12/TIN0/
IN3
P12
P13/IN2
P13
P14/IN1
P14
P15/IN0
P15
PPG2
PPG
TOT0
Generalpurpose
input/output
Output
Circuit
type
CMOS
G
Peripheral function
TIN0
−
WOT
Reload
timer
watch
timer
IN3
IN2
−
−
−
Input
capture
CMOS
(hysteresis)
(automotive
level (*))
IN1
IN0
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
Note:
To set a pin to high-impedance when the pin is shared by a peripheral function and a port in
stop mode, watch mode, or timebase timer mode, disable the output of peripheral functions,
and set the STP bit to "1" or TMD bit to 0 in the low-power consumption mode control
register (LPMCR).
The applicable pins are listed below.
P10/PPG2 and P11/TOT0/WOT
170
8.4 Port 1
■ Pin block diagram for Port 1
Figure 8.4-1 "Pin block diagram for Port 1" shows the pin block diagram for Port 1.
Figure 8.4-1 Pin block diagram for Port 1
Peripheral function output
Peripheral function input
Peripheral function output enabled
PDR (Port data register)
Internal data bus
PDR read
Output
latch
PDR write
Pin
DDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
■ Registers for Port 1
The Port 1 registers are PDR1 and DDR1. The register bits have a one-to-one correspondence
with the Port 1 pins. Table 8.4-2 "Correspondence between registers and pins for Port 1" shows
the correspondence between the registers and pins for Port 1.
Table 8.4-2 Correspondence between registers and pins for Port 1
Port name
Bit of related register and its corresponding pin
PDR1,DDR1
Port 1
Corresponding pin
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
−
−
P15
P14
P13
P12
P11
P10
171
CHAPTER 8 I/O PORTS
8.4.1
Port 1 Registers (PDR1, DDR1)
This section describes the registers for Port 1.
■ Functions of Port 1 Registers
❍ Port 1 data register (PDR1)
The PDR1 register indicates the pin states.
❍ Port 1 direction register (DDR1)
The DDR1 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0".
Notes:
•
When a peripheral function with an output pin is used, if the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," the pin works as a peripheral
function output pin whatever the DDR1 register’s setting.
•
If a peripheral function with an input pin is used, set the DDR1 register bit corresponding to
each peripheral function’s input pin to "0" to make it work as an input pin.
Table 8.4-3 Function of Port 1 registers
Register
name
Data
At reading
0
Pin state: L
level
Sets the output latch to "0."
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1."
Outputs H level if used as an
output port.
0
Direction
latch set to
"0"
Sets the output level to OFF to
use it as an input port.
1
Direction
latch set to
"1"
Port 1 data
register
(PDR1)
Port 1
direction
register
(DDR1)
R/W: Reading and writing permitted
X: Unspecified value
172
At writing
Sets the output level to ON to
use it as an output port.
Initial value
R/W
Address
R/W
000001H
XXXXXXXXB
R/W
000011H
00000000B
8.4 Port 1
8.4.2
Description of Port 1 Operation
This section describes the operation of Port 1.
■ Operation of Port 1
❍ Operation as an Output Port
With the corresponding DDR1 register bit set to "1," the port works as an output port.
When used as an output port, if data is written to the PDR1 register, it is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR1 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR1 register writes the input value
from the pin to the output latch, and the value is output. Therefore, to switch the input bit to
the output bit, specify to write the output data to the PDR register before performing the
actual output.
❍ Operation as an input port
With the corresponding DDR1 register bit set to "0," the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR1 register, it is retained in the PDR1 output latch but not output to
the pins.
Reading the PDR1 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR1 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Operation for peripheral function input
For a port that is also used for peripheral function input, the pin value is always used as input to
the peripheral function. To use an external signal as input for the peripheral function, set the
DDR1 register for the input port to "0."
❍ Reset operation
At CPU reset, the DDR1 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port) and the pins are set to "high-impedance."
In a reset operation, the PDR1 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR1 and then set the corresponding DDR1 register to "1."
173
CHAPTER 8 I/O PORTS
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR1 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.4-4 "States of Port 1 pins" shows the pin states of Port 1.
Table 8.4-4 States of Port 1 pins
Pin name
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
P10/PPG2 to P15/
IN0
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Stop mode,
timebase timer
mode (SPL=1)
Input cut-off/
output Hi-z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
Note:
Shift to stop mode, watch mode, and timebase timer mode after disabling the output of
peripheral functions, when control the pin which shares aport and a peripheral function in
high-impedance.
Indicates an object and pins in the following.
Object pins: P10/PPG2. P11/TOT0/WOT
174
8.5 Port 3
8.5
Port 3
Port 3 is a general-purpose input/output port that is also used as peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 3.
■ Port 3 Configuration
Port 3 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P36/SEG12 to P37/
SEG13)
•
Port 3 data register (PDR3)
•
Port 3 direction register (DDR3)
■ Port 3 pins
Port 3 pins are used both for peripheral functions and as general-purpose input/output pins. If
used as peripheral function input/output pins, they must not be used as general-purpose input/
output ports. Table 8.5-1 "Port 3 pins" shows the pins of Port 3.
Table 8.5-1 Port 3 pins
Port
name
Type of input/output
Pin name
P36/SEG12
Port 3
P37/SEG13
Port function
P36
P37
Generalpurpose
output/input
Input
Output
Circuit
type
CMOS
(hysteresis)
(automotive
level (*))
CMOS
E
Peripheral function
SEG12
LCDC
SEG13
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
175
CHAPTER 8 I/O PORTS
■ Pin block diagram for Port 3
Figure 8.5-1 "Pin block diagram for Port 3" shows the pin block diagram for Port 3.
Figure 8.5-1 Pin block diagram for Port 3
Peripheral function output
Peripheral function output enabled
PDR (Port data register)
Internal data bus
PDR read
Output latch
PDR write
Pin
PDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or LCD output enabled
■ Registers for Port 3
The Port 3 registers are PDR3 and DDR3. The register bits have a one-to-one correspondence
with the Port 3 pins. Table 8.5-2 "Correspondence between registers and pins for Port 3" shows
the correspondence between the registers and pins for Port 3.
Table 8.5-2 Correspondence between registers and pins for Port 3
Port
name
Bit of related register and its corresponding pin
PDR3, DDR3
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P37
P36
−
−
−
−
−
−
Port 3
176
8.5 Port 3
8.5.1
Port 3 Registers (PDR3, DDR3)
This section describes the registers for Port 3.
■ Function of Port 3 Registers
❍ Port 3 data register (PDR3)
The PDR3 register indicates the pin states.
❍ Port 3 direction register (DDR3)
The DDR3 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0".
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," the pin works as a peripheral
function output pin whatever the DDR3 register’s setting.
Table 8.5-3 Functions of Port 3 registers
Register
name
Data
At reading
0
Pin state: L
level
Sets the output latch to "0".
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1".
Outputs H level if used as an
output port.
0
Direction
latch set to
"0"
Sets the output level to OFF to
use it as an input port.
1
Direction
latch set to
"1"
Port 3 data
register
(PDR3)
Port 3
direction
register
(DDR3)
At writing
Initial value
R/W
Address
R/W
000003H
XX------B
R/W
000013H
00------B
Sets the output level to ON to
use it as an output port.
R/W: Reading and writing permitted
X: Unspecified value
-: Undefined
177
CHAPTER 8 I/O PORTS
8.5.2
Description of Port 3 Operation
This section describes the operation of Port 3.
■ Operation of Port 3
❍ Operation as an output port
With the corresponding DDR3 register bit set to "1," the port works as an output port.
When used as an output port, if data is written to the PDR3 register, it is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR3 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, specify to write the output data to the PDR register before performing the actual
output.
❍ Operation as an input port
With the corresponding DDR3 register bit set to "0," the port works as an input port setting the
output buffer to "OFF" and the pins to "high-impedance."
If data is written to the PDR3 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR3 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR3 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Reset operation
At CPU reset, the DDR3 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and the pins are set to "high-impedance."
In a reset operation, the PDR3 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR3 register and then set the corresponding DDR3 register to "1".
178
8.5 Port 3
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR3 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.5-4 "States of Port 3 pins" shows the pin states of Port 3.
Table 8.5-4 States of Port 3 pins
Pin name
P36/SEG12 to
P37/SEG13
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Stop mode,
timebase timer
mode (SPL=1)
Input cut-off/
output Hi-z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
179
CHAPTER 8 I/O PORTS
8.6
Port 4
Port 4 is a general-purpose input/output port that is also used as peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 4.
■ Port 4 Configuration
Port 4 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P40/SEG14 to P47/
SEG21)
•
Port 4 data register (PDR4)
•
Port 4 direction register (DDR4)
■ Port 4 Pins
Port 4 pins are used both for peripheral functions and as general-purpose input/output pins. If
used as peripheral function input/output pins, they must not be used as general-purpose input/
output ports. Table 8.6-1 "Port 4 pins" shows the pins of Port 4.
Table 8.6-1 Port 4 pins
Port
name
Pin name
Port function
Peripheral
function
P40/SEG14
P40
SEG14
P41/SEG15
P41
SEG15
P42/SEG16
P42
SEG16
P43/SEG17
P43
P44/SEG18
P44
P45/SEG19
P45
SEG19
P46/SEG20
P46
SEG20
P47/SEG21
P47
SEG21
Port 4
Generalpurpose
input/output
SEG17
LCDC
SEG18
Type of input/output
Input
Output
Circuit
type
CMOS
(hysteresis)
(automotive
level (*))
CMOS
E
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
180
8.6 Port 4
■ Pin Block Diagram for Port 4
Figure 8.6-1 "Pin block diagram for Port 4" shows the pin block diagram for Port 4.
Figure 8.6-1 Pin block diagram for Port 4
Peripheral function output
Peripheral function output enabled
PDR (Port data register)
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or
LCD output enabled
Note:
If the peripheral function’s output enable bit is set to "enabled," the corresponding pin is
forced to work as peripheral function output irrespective of the DDR4 register settings.
■ Registers for Port 4
The Port 4 registers are PDR4 and DDR4. The register bits have a one-to-one correspondence
with the Port 4 pins. Table 8.6-2 "Correspondence between registers and pins for Port 4" shows
the correspondence between the registers and pins for Port 4.
Table 8.6-2 Correspondence between registers and pins for Port 4
Port
name
Bit of related register and its corresponding pin
PDR4, DDR4
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P47
P46
P45
P44
P43
P42
P41
P40
Port 4
181
CHAPTER 8 I/O PORTS
8.6.1
Port 4 Registers (PDR4, DDR4)
This section describes the registers for Port 4.
■ Function of Port 4 Registers
❍ Port 4 data register (PDR4)
The PDR4 register indicates the pin states.
❍ Port 4 direction register (DDR4)
The DDR4 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0."
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," it works as a peripheral
function output pin whatever the DDR4 register’s setting.
Table 8.6-3 Functions of Port 4 registers
Register
name
Data
Sets the output latch to "0".
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1".
Outputs H level if used as an
output port.
0
Direction latch
set to "0"
Sets the output level to OFF to
use it as an input port.
1
Direction latch
set to "1"
Sets the output level to ON to
use it as an output port.
Port 4 data
register
(PDR4)
R/W: Reading and writing permitted
X: Unspecified value
182
At writing
Pin state: L
level
0
Port 4
direction
register
(DDR4)
At reading
Initial value
R/W
Address
R/W
000004H
XXXXXXXXB
R/W
000014H
00000000B
8.6 Port 4
8.6.2
Description of Port 4 Operation
This section describes the operation of Port 4.
■ Operation of Port 4
❍ Operation as an Output Port
With the corresponding DDR4 register bit set to "1," the port works as an output port.
When used as an output port, data is written to the PDR4 register, retained in the PDR output
latch, and then output to the pins as is.
Reading the PDR4 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, specify to write the output data to the PDR register before performing the actual
output.
❍ Operation as an input port
With the corresponding DDR4 register bit set to "0," the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR4 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR4 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR4 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Reset operation
At CPU reset, the DDR4 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and the pins are set to "high-impedance."
In a reset operation, the PDR4 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR4 register and then set the corresponding DDR4 register to "1".
183
CHAPTER 8 I/O PORTS
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR4 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.6-4 "States of Port 4 pins" shows the pin states of Port 4.
Table 8.6-4 States of Port 4 pins
Pin name
P40/SEG14 to
P47/SEG21
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Stop mode,
timebase timer
mode (SPL=1)
Input cut-off/
output Hi-z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
184
8.7 Port 5
8.7
Port 5
Port 5 is a general-purpose input/output port that is also used as peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 5.
■ Port 5 Configuration
Port 5 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P50/INT0/ADTG to P57/
SGA)
•
Port 5 data register (PDR5)
•
Port 5 direction register (DDR5)
■ Port 5 Pins
Port 5 pins are used both for peripheral functions and as general-purpose input/output pins. If
used as peripheral function input/output pins, they must not be used as general-purpose input/
output ports.
Table 8.7-1 "Port 5 pins" shows the pins of Port 5.
Table 8.7-1 Port 5 pins
Port
name
Port 5
Type of input/output
Pin name
Port function
P50/INT0/
ADTG
P50
INT0
P51/INT1/
RX1
P51
INT1
P52/INT2/
TX1
P52
P53/INT3
P53
P54/TX0
P54
ADTG
External
interrupt
input
INT2
Generalpurpose
input/output
Input
Output
Circuit
type
CMOS
(hysteresis)
(automotive
level (*))
CMOS
G
Peripheral function
A/D
converter
RX1
CAN1
TX1
INT3
TX0
CAN0
P55/RX0
P55
RX0
P56/SGO/
FRCK
P56
SGO
P57/SGA
P57
SGA
Sound
generator
−
−
FRCK
Free-run
timer
−
−
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
185
CHAPTER 8 I/O PORTS
■ Pin Block Diagram for Port 5
Figure 8.7-1 "Pin block diagram for Port 5" shows the pin block diagram for Port 5.
Figure 8.7-1 Pin block diagram for Port 5
Peripheral function output
Peripheral function input
Peripheral function output enabled
PDR(Port data register)
Internal data bus
PDR read
Output
latch
PDR write
Pin
DDR(Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
■ Registers for Port 5
The Port 5 registers are PDR5 and DDR5. The register bits have a one-to-one correspondence
with the Port 5 pins. Table 8.7-2 "Correspondence between registers and pins for Port 5" shows
the correspondence between the registers and pins for Port 5.
Table 8.7-2 Correspondence between registers and pins for Port 5
Port
name
Bit of related register and its corresponding pin
PDR5, DDR5
bit15
bit14
bit13
bit12
Bit11
bit10
bit9
bit8
Corresponding pin
P57
P56
P55
P54
P53
P52
P51
P50
Port 5
186
8.7 Port 5
8.7.1
Port 5 Registers (PDR5, DDR5)
This section describes the registers for Port 5.
■ Functions of Port 5 Registers
❍ Port 5 data register (PDR5)
The PDR5 register indicates the pin states.
❍ Port 5 direction register (DDR5)
The DDR5 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0."
Notes:
•
When a peripheral function with an output pin is used, if the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," the pin works as a peripheral
function output pin whatever the DDR5 register’s setting.
•
If a peripheral function with an input pin is used, set the DDR5 register bit corresponding to
each peripheral function’s input pin to "0" to make it work as an input pin.
Table 8.7-3 Functions of Port 5 registers
Register
name
Data
At reading
0
Pin state: L
level
Sets the output latch to "0."
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1."
Outputs H level if used as an
output port.
0
Direction
latch set to
"0"
Sets the output level to OFF to
use it as an input port.
1
Direction
latch set to
"1"
Port 5 data
register
(PDR5)
Port 5
direction
register
(DDR5)
At writing
Initial value
R/W
Address
R/W
000005H
XXXXXXXXB
R/W
000015H
00000000B
Sets the output level to ON to
use it as an output port.
R/W: Reading and writing permitted
X: Unspecified value
187
CHAPTER 8 I/O PORTS
8.7.2
Description of Port 5 Operation
This section describes the operation of Port 5.
■ Operation of Port 5
❍ Operation as an output port
With the corresponding DDR5 register bit set to "1," the port works as an output port.
When used as an output port, if data is written to the PDR5 register, it is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR5 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, specify to write the output data to the PDR register before performing the actual
output.
❍ Operation as an input port
With the corresponding DDR5 register bit set to "0", the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR5 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR5 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR5 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Operation for peripheral function input
For a port that is also used for peripheral function input, the pin value is always used as input to
the peripheral function. To use an external signal as input for the peripheral function, set the
DDR5 register for the input port to "0".
❍ Reset operation
At CPU reset, the DDR5 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and the pins are set to "high-impedance."
In a reset operation, the PDR5 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR5 register and then set the corresponding DDR5 register to "1".
188
8.7 Port 5
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR5 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.7-4 "States of Port 5 pins" shows the pin states of Port 5.
Table 8.7-4 States of Port 5 pins
Pin name
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
P50/INT0/ADTG to
P57/SGA
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Input cut-off/
output Hi-z
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Input enabled/
output Hi-z
P50/INT0 to P53/
INT3
(External interrupt
being set)
Stop mode,
timebase timer
mode (SPL=1)
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
189
CHAPTER 8 I/O PORTS
8.8
Port 6
Port 6 is a general-purpose input/output port that is also used as peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 6.
■ Port 6 Configuration
Port 6 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P60/AN0 to P67/AN7)
•
Port 6 data register (PDR6)
•
Port 6 direction register (DDR6)
•
Analog input enable register (ADER)
■ Port 6 Pins
The Port 6 input/output pins are also used as analog input pins. If a pin is used for analog input,
it cannot be used as a general-purpose input/output port, and vice versa.
Table 8.8-1 "Port 6 pins" shows the Port 6 pins.
Table 8.8-1 Port 6 pins
Port
name
Type of input/output
Pin name
Port function
Input
P60/AN0
P60
AN0
Analog input 0
P61/AN1
P61
AN1
Analog input 1
P62/AN2
P62
AN2
Analog input 2
P63/AN3
P63
AN3
Analog input 3
P64/AN4
P64
AN4
Analog input 4
P65/AN5
P65
AN5
Analog input 5
P66/AN6
P66
AN6
Analog input 6
P67/AN7
P67
AN7
Analog input 7
Port 6
Generalpurpose
input/output
Output
Circuit
type
CMOS
F
Peripheral function
CMOS
(hysteresis)
(automotive
level (*))
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
190
8.8 Port 6
■ Pin Block Diagram for Port 6
Figure 8.8-1 "Pin block diagram for Port 6" shows the pin block diagram for Port 6.
Figure 8.8-1 Pin block diagram for Port 6
ADER
Analog input
PDR (Port data register)
PDR read
Internal data bus
Output latch
PDR write
Pin
DDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
Note:
For pins that are to be used as input ports, set the corresponding DDR6 register bit to "0"
and the corresponding ADER register bit to "0."
For pins to be used as analog input pins, set the corresponding DDR6 register bit to "0" and
the ADER register bit to "1." In this case, reading the PDR6 register returns "0."
■ Registers for Port 6
The Port 6 registers are PDR6 and DDR6. The register bits have a one-to-one correspondence
with the Port 6 pins. Table 8.8-2 "Correspondence between registers and pins for Port 6" shows
the correspondence between the registers and pins for Port 6.
Table 8.8-2 Correspondence between registers and pins for Port 6
Port
name
Bit of related register and its corresponding pin
PDR6,DDR6,ADER
Bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Corresponding pin
P67
P66
P65
P64
P63
P62
P61
P60
Port 6
191
CHAPTER 8 I/O PORTS
8.8.1
Port 6 Registers (PDR6, DDR6, ADER)
This section describes the registers for Port 6.
■ Functions of Port 6 Registers
❍ Port 6 data register (PDR6)
The PDR6 register indicates the pin states.
❍ Port 6 direction register (DDR6)
The DDR6 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0."
❍ ADER register (ADER)
The ADER register specifies whether a pin is to be used as a port or as an analog input in units
of individual bits. The pin works as analog input if the bit corresponding to the pin is set to "1" or
as an input/output port if the bit is set to "0."
Notes:
192
•
When used as port input/output, if a medium level signal is input, an input leak current flows.
To avoid this, pins used for analog input must have their corresponding ADER bits set to "1."
•
At a reset, the DDR6 register is cleared and the ADER register is set in such a way as to
specify analog input.
8.8 Port 6
Table 8.8-3 Functions of Port 6 registers
Register
name
Data
At reading
At writing
Pin state: L
level
With DDR="0," high-impedance
state is assumed.
With DDR="1," L level is output.
1
Pin state: H
level
With DDR="0," high-impedance
state is assumed.
With DDR="1," H level is
output.
Port 6
direction
register
(DDR6)
0
Direction
latch set to
"0"
Sets the output level to OFF to
use the pin as an input port.
1
Direction
latch set to
"1"
Analog input
enable
register
(ADER)
0
Port input. Output mode
1
Analog input mode
0
Port 6 data
register
(PDR6)
Initial value
R/W
Address
R/W
000006H
XXXXXXXXB
R/W
000016H
00000000B
R/W
00001AH
11111111B
Sets the output level to ON to
use the pin as an output port.
R/W: Reading and writing permitted
X: Unspecified value
193
CHAPTER 8 I/O PORTS
8.8.2
Description of Port 6 Operation
This section describes the operation of Port 6.
■ Operation of Port 6
❍ Operation as an output port
With the corresponding DDR6 register bit set to "1," the port works as an output port.
When used as an output port, if data is written to the PDR6 register, it is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR6 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, write the output data to the PDR register and then write "1" to the DDR register.
❍ Operation as an input port
With the corresponding DDR6 register bit set to "0", the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR6 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR6 register returns the pin levels ("L" or "H").
❍ Operation for analog input
If the port is to be used for analog input, set the ADER register bit corresponding to the analog
input pin to "1." Then, general-purpose port operation is prohibited and the pin will work as
analog input pin. Reading PDR6 in this state returns "0."
❍ Reset operation
At CPU reset, the DDR6 register value is cleared and ADER register value is set in such a way
as to operate the port to operate in analog input mode. For use as a general-purpose port, set
the ADER register to "0" in advance to operate the port in input/output mode.
194
8.8 Port 6
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because the output buffer is forcibly set to "OFF." To avoid
leakage due to the open input, the input value is fixed.
Table 8.8-4 "States of Port 6 pins" shows the states of Port 6.
Table 8.8-4 States of Port 6 pins
Pin name
P60/AN0 to P67/
AN7
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Stop mode,
timebase timer
mode (SPL=1)
Input cut-off/
output Hi-z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
195
CHAPTER 8 I/O PORTS
8.9
Port 7
Port 7 is a general-purpose input/output port that is also used as peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 7.
■ Port 7 Configuration
Port 7 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P70/PMW1P0 to P77/
PWM2M1)
•
Port 7 data register (PDR7)
•
Port 7 direction register (DDR7)
■ Port 7 Pin
The Port 7 pins are used both for peripheral functions and as general-purpose input/output pins.
If used as peripheral function input/output pins, they must not be used as general-purpose input/
output ports. Table 8.9-1 "Port 7 pins" shows the pins of Port 7.
Table 8.9-1 Port 7 pins
Port
name
Type of input/output
Pin name
Port function
Input
P70/ PWM1P0
P70
PWM1P0
P71/ PWM1M0
P71
PWM1M0
P72/ PWM2P0
P72
PWM2P0
P73/ PWM2M0
P73
P74/ PWM1P1
P74
P75/ PWM1M1
P75
PWM1M1
P76/ PWM2P1
P76
PWM2P1
P77/ PWM2M1
P77
PWM2M1
Port 7
Generalpurpose
input/output
Output
Circuit
type
CMOS
H
Peripheral function
PWM2M0
PWM1P1
Stepping motor
controller
CMOS
(hysteresis)
(automotive
level (*))
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
196
8.9 Port 7
■ Pin Block Diagram for Port 7
Figure 8.9-1 "Pin block diagram for Port 7" shows the pin block diagram for Port 7.
Figure 8.9-1 Pin block diagram for Port 7
Internal data bus
PDR(Port data register)
Peripheral function output
Peripheral function output enabled
PDR read
Output latch
PDR write
Pin
DDR(Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
If the peripheral function output enable bit is set to "enabled, the pin is made to operate as a
peripheral function input pin irrespective of the DDR7 register value.
■ Registers for Port 7
The Port 7 registers are PDR7 and DDR7. The register bits have a one-to-one correspondence
with the Port 7 pins. Table 8.9-2 "Correspondence between registers and pins for Port 7" shows
the correspondence between the registers and pins for Port 7.
Table 8.9-2 Correspondence between registers and pins for Port 7
Port
name
Bit of related register and its corresponding pin
PDR7,DDR7
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Corresponding pin
P77
P76
P75
P74
P73
P72
P71
P70
Port 7
197
CHAPTER 8 I/O PORTS
8.9.1
Port 7 Registers (PDR7, DDR7)
This section describes the registers for Port 7.
■ Functions of Port 7 Registers
❍ Port 7 data register (PDR7)
The PDR7 register indicates the pin states.
❍ Port 7 direction register (DDR7)
The DDR7 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0".
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," the pin works as a peripheral
function output pin whatever the DDR0 register’s setting.
Table 8.9-3 Function of Port 7 registers
Register
name
Data
At reading
0
Pin state: L
level
Sets the output latch to "0".
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1".
Outputs H level if used as an
output port.
0
Direction
latch set to
"0"
Sets the output level to OFF to
use it as an input port.
1
Direction
latch set to
"1"
Port 7 data
register
(PDR7)
Port 7
direction
register
(DDR7)
R/W: Reading and writing permitted
X: Unspecified value
198
At writing
Sets the output level to ON to
use it as an output port.
Initial value
R/W
Address
R/W
000007H
XXXXXXXXB
R/W
000017H
00000000B
8.9 Port 7
8.9.2
Description of Port 7 Operation
This section describes the operation of Port 7.
■ Operation of Port 7
❍ Operation as an output port
With the corresponding DDR7 register bit set to "1," the port works as an output port.
When used as an output port, if data is written to the PDR7 register, it is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR7 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, specify to write the output data to the PDR register before performing the actual
output.
❍ Operation as an input port
With the corresponding DDR7 register bit set to "0", the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR7 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR7 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR7 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Reset operation
At CPU reset, the DDR7 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and the pins are set to "high-impedance."
In a reset operation, the PDR7 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR7 register and then set the corresponding DDR7 register to "1".
199
CHAPTER 8 I/O PORTS
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR7 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.9-4 "States of Port 7 pins" shows the pin states of Port 7.
Table 8.9-4 States of Port 7 pins
Pin name
P70/PWM1P0 to
P77/PWM2M1
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Stop mode,
timebase timer
mode (SPL=1)
Input cut-off/
output Hi-z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
200
8.10 Port 8
8.10 Port 8
Port 8 is a general-purpose input/output port that is also used as peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 8.
■ Port 8 Configuration
Port 8 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P80/PMW1P2 to P87/
PWM2M3)
•
Port 8 data register (PDR8)
•
Port 8 direction register (DDR8)
■ Port 8 Pins
Port 8 pins are used both for peripheral functions and as general-purpose input/output pins. If
used as peripheral function input/output pins, they must not be used as general-purpose input/
output ports. Table 8.10-1 "Port 8 pins" shows the pins of Port 8.
Table 8.10-1 Port 8 pins
Port
name
Type of input/output
Pin name
Port function
Input
P80/PWM1P2
P80
PWM1P2
P81/PWM1M2
P81
PWM1M2
P82/PWM2P2
P82
PWM2P2
P83/PWM2M2
P83
P84/PWM1P3
P84
P85/PWM1M3
P85
PWM1M3
P86/PWM2P3
P86
PWM2P3
P87/PWM2M3
P87
PWM2M3
Port 8
Generalpurpose
input/output
Output
Circuit
type
CMOS
H
Peripheral function
PWM2M2
PWM1P3
Stepping motor
controller
CMOS
(hysteresis)
(automotive
level (*))
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
201
CHAPTER 8 I/O PORTS
■ Pin Block Diagram for Port 8
Figure 8.10-1 "Pin block diagram for Port 8" shows the pin block diagram for port 8.
Figure 8.10-1 Pin block diagram for Port 8
PDR(Port data register)
Peripheral function output
Peripheral function output enabled
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR(Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
If the peripheral function’s output enable bit is set to "enabled," the pin is made to operate as a
peripheral function input pin irrespective of the DDR8 register value.
■ Registers for Port 8
The Port 8 registers are PDR8 and DDR8. The register bits have a one-to-one correspondence
with the port 8 pins. Table 8.10-2 "Correspondence between registers and pins for Port 8"
shows the correspondence between the registers and pins for port 8.
Table 8.10-2 Correspondence between registers and pins for Port 8
Port
name
Bit of related register and its corresponding pin
PDR8, DDR8
bit7
bit6
bit5
Bit4
bit3
bit2
bit1
bit0
Corresponding pin
P87
P86
P85
P84
P83
P82
P81
P80
Port 8
202
8.10 Port 8
8.10.1 Port 8 Registers (PDR8, DDR8)
This section describes the registers for port 8.
■ Functions of Port 8 Registers
❍ Port 8 data register (PDR8)
The PDR8 register indicates the pin states.
❍ Port 8 direction register (DDR8)
The DDR8 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0".
Note:
When a peripheral function with an output pin is used, if the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," the pin works as a peripheral
function output pin whatever the DDR0 register’s setting.
Table 8.10-3 Functions of Port 8 registers
Register
name
Data
At reading
0
Pin state: L
level
Sets the output latch to "0".
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1".
Outputs H level if used as an
output port.
0
Direction
latch set to
"0"
Sets the output level to OFF to
use it as an input port.
1
Direction
latch set to
"1"
Port 8 data
register
(PDR8)
Port 8
direction
register
(DDR8)
At writing
Initial value
R/W
Address
R/W
000008H
XXXXXXXXB
R/W
000018H
00000000B
Sets the output level to ON to
use it as an output port.
R/W: Reading and writing permitted
X: Unspecified value
203
CHAPTER 8 I/O PORTS
8.10.2 Description of Port 8 Operation
This section describes the operation of Port 8.
■ Operation of Port 8
❍ Operation as an output port
With the corresponding DDR8 register bit set to "1," the port works as an output port.
When used as an output port, if data is written to the PDR8 register, it is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR8 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, specify to write the output data to the PDR register before performing the actual
output.
❍ Operation as an input port
With the corresponding DDR8 register bit set to "0", the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR8 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR8 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR8 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Reset operation
At CPU reset, the DDR8 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and the pins are set to "high-impedance."
In a reset operation, the PDR8 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR8 register and then set the corresponding DDR8 register to "1".
204
8.10 Port 8
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR8 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.10-4 "States of Port 8 pins" shows the pin states of Port 8.
Table 8.10-4 States of Port 8 pins
Pin name
P80/PWM1P2 to
P87/PWM2M3
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Stop mode,
timebase timer
mode (SPL=1)
Input cut-off/
output Hi-z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
205
CHAPTER 8 I/O PORTS
8.11 Port 9
Port 9 is a general-purpose input/output port that is also used for peripheral function
input/output. The use of each pin for a peripheral function or as port is switched in
units of individual bits. This section mainly describes the function of this port as a
general-purpose input/output port and indicates the configuration, pins, and block
diagrams of pins and registers for Port 9.
■ Port 9 Configuration
Port 9 consists of three elements:
•
General-purpose input/output pins and external interrupt input pins (P90/SEG22 to P91/
SEG23)
•
Port 9 data register (PDR9)
•
Port 9 direction register (DDR9)
■ Port 9 pins
Port 9 pins are used both for peripheral functions and as general-purpose input/output pins. If
used as peripheral function input/output pins, they must not be used as general-purpose input/
output ports. Table 8.11-1 "Port 9 pins" shows the pins of Port 9.
Table 8.11-1 Port 9 pins
Port
name
Type of input/output
Pin name
Port function
Input
P90/SEG22
P90
P91/SEG23
P91
Port 9
Generalpurpose
input/output
Output
Circuit
type
CMOS
E
Peripheral function
SEG22
SEG23
LCD
controller
CMOS
(hysteresis)
(automotive
level (*))
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
For the type of circuit, refer to Section 1.7 "Type of Input/Output Circuit".
206
8.11 Port 9
■ Pin Block Diagram for Port 9
Figure 8.11-1 "Pin block diagram for Port 9" shows the pin block diagram for Port 9.
Figure 8.11-1 Pin block diagram for Port 9
Peripheral function output
Peripheral function output enabled
PDR (Port data register)
Internal data bus
PDR read
Output latch
PDR write
Pin
DDR (Port direction register)
Direction
latch
DDR write
DDR read
Standby control (SPL=1) or
LCD output enabled
If the peripheral function’s output enable bit is set to "enabled," the pin is made to operate as a
peripheral function’s input pin irrespective of the DDR9 register value.
■ Registers for Port 9
The Port 1 registers are PDR9 and DDR9. The register bits have a one-to-one correspondence
with the Port 9 pins. Table 8.11-2 "Correspondence between registers and pins for Port 9"
shows the correspondence between the registers and pins for Port 9.
Table 8.11-2 Correspondence between registers and pins for Port 9
Port
name
Bit of related register and its corresponding pin
PDR9, DDR9
Port 9
Corresponding pin
Bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
−
−
−
−
−
−
P91
P90
207
CHAPTER 8 I/O PORTS
8.11.1 Functions of Port 9 Registers (PDR9, DDR9)
This section describes the registers for port 9.
■ Function of Port 9 Registers
❍ Port 9 data Register (PDR9)
The PDR9 register indicates the pin states.
❍ Port 9 Direction Register (DDR9)
The DDR9 register is used to set the pin input/output direction for each bit. The pin works as an
output port if the bit corresponding to the port (pin) is set to "1" or as an input port if the bit is set
to "0."
Note:
When a peripheral function with an output pin is used, and the output enable bit of each
peripheral function corresponding to the pin is set to "enabled," the pin works as a peripheral
function output pin whatever the DDR0 register’s setting.
Table 8.11-3 Function of Port 9 registers
Register
name
Data
At reading
0
Pin state: L
level
Sets the output latch to "0."
Outputs L level if used as an
output port.
1
Pin state: H
level
Sets the output latch to "1."
Outputs H level if used as an
output port.
0
Direction
latch set to
"0"
Sets the output level to OFF to
use it as an input port.
1
Direction
latch set to
"1"
Port 9 data
register
(PDR9)
Port 9
direction
register
(DDR9)
R/W: Reading and writing permitted
X: Unspecified value
–: Undefined
208
At writing
Sets the output level to ON to
use it as an output port.
Initial value
R/W
Address
R/W
000009H
------XXB
R/W
000019H
------00B
8.11 Port 9
8.11.2 Description of Port 9 Operation
This section describes the operation of port 9.
■ Operation of Port 9
❍ Operation as an output port
With the corresponding DDR9 register bit set to "1," the port works as an output port.
When used as an output port, if data is written to the PDR9 register, it is retained in the PDR
output latch and then output to the pins as is.
Reading the PDR9 register allows the pin values (same values as in the PDR output latch) to be
read.
Note:
If the port data register uses a read-modify-write type instruction (e.g., a bit set instruction),
the target bit is set to the value specified and the output bit specified by the DDR register is
not affected. However, the input bit specified by the DDR register writes the input value from
the pin to the output latch, and the value is output. Therefore, to switch the input bit to the
output bit, write the output data to the PDR register and then write "1" to the DDR register.
❍ Operation as an input port
With the corresponding DDR9 register bit set to "0", the port works as an input port. In this case,
the output buffer is set to "OFF" and the pins to "high-impedance."
If data is written to the PDR9 register, it is retained in the PDR output latch but not output to the
pins.
Reading the PDR9 register returns the pin levels ("L" or "H").
❍ Operation for peripheral function output
To use the port for peripheral function output, specify it with the peripheral function’s output
enable bit. Switching the input/output has priority over the peripheral function’s output enable
bit. Therefore, even if the DDR9 register bit is set to "0", the port is used as a peripheral function
output as long as the corresponding peripheral function is output enabled. Even if a peripheral
function is output enabled, the pin value can be read, allowing the peripheral function’s output
value to be detected.
❍ Reset operation
At CPU reset, the DDR9 register value is cleared. Thus, all the output buffers are set to "OFF"
(input port), and the pins are set to "high-impedance."
In a reset operation, the PDR9 register is not initialized. Therefore, if used as an output port, set
the output data in the PDR9 register and then set the corresponding DDR9 register to "1".
209
CHAPTER 8 I/O PORTS
❍ Operation for the stop and timebase timer modes
When a transition to the stop mode or timebase timer mode occurs, and the low-power
consumption mode control register’s pin state specification bit (SPL in LPMCR) is "1", the pins
are set to "high-impedance." This is because, irrespective of the DDR9 register’s value, the
output buffer is forcibly set to "OFF." To avoid leakage due to the open input, the input value is
fixed.
Table 8.11-4 "States of Port 9 pins" shows the port 9 pin states.
Table 8.11-4 States of Port 9 pins
Pin name
P90/SEG22 to
P91/SEG23
Normal
operation
Sleep mode
Stop mode,
timebase
timer mode
(SPL=0)
Generalpurpose input/
output port
Generalpurpose input/
output port
Generalpurpose input/
output port
Stop mode,
timebase timer
mode (SPL=1)
Input cut-off/
output Hi-z
SPL: Pin state specification bit of low-power consumption mode control register (SPL in
LPMCR)
Hi-z: High-impedance
210
8.12 Example Program for I/O Port
8.12 Example Program for I/O Port
An example program that uses the I/O port is shown below.
■ Example Program for I/O Port
❍ Specification of processing
On ports 0 and 1, all 7-segment LEDs (8-segment if Dp is included) are on.
The P00 pin corresponds to the LED’s common anode pin, and the P10 to P17 pins correspond
to the segment pins.
Figure 8.12-1 "Example of 8-segment LED connection" shows an example 8-segment LED
connection.
Figure 8.12-1 Example of 8-segment LED connection
MB90420G/MB90425G (A) series
P10
P07
P06
P05
P04
P03
P02
P01
P00
❍ Coding example
PDR0
EQU
000000H
PDR1
EQU
000001H
DDR0
EQU
000010H
DDR1
EQU
000011H
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;Initial setting completed
MOV
I:PDR1, #00000000B
;P10 set to "L" level,
#xxxxxxx0B
MOV
I:DDR1, #11111111B
;All bits in Port 1 set as
outputs
MOV
I:PDR0, #11111111B
;All bits in Port 0 set to "1"
MOV
I:DDR0, #11111111B
;All bits in Port 0 set as
outputs
CODE
ENDS
;---------------------------------------------------------------------------END
START
211
CHAPTER 8 I/O PORTS
212
CHAPTER 9
WATCHDOG TIMER/TIMEBASE TIMER/
WATCH TIMER (SUB-CLOCK)
This chapter describes the functions and operation of the watchdog timer, timebase
timer, and watch timer (used as sub-clock).
9.1 "Outline of Watchdog Timer/Timebase Timer/Watch Timer"
9.2 "Block Diagram of Watchdog Timer/Timebase Timer/Watch Timer"
9.3 "List of Registers for Watchdog Timer/Timebase Timer/Watch Timer"
9.4 "Operation of Watchdog Timer/Timebase Timer/Watch Timer"
9.5 "Notes on Using Watchdog Timer/Timebase Timer"
9.6 "Example Program for Watchdog Timer/Timebase Timer"
213
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
9.1
Outline of Watchdog Timer/Timebase Timer/Watch Timer
The circuit configuration of the watchdog timer, timebase timer, and watch timer is
shown below.
• Watchdog timer: watchdog counter, control register and watchdog reset circuit
• Timebase timer: 18-bit timer, circuit to generate interrupts in intervals
• Watch timer: 15-bit timer, circuit to generate interrupts in intervals.
■ Functions of the Watchdog Timer
The watchdog timer consists of a 2-bit watchdog counter, control register, and watchdog reset
control section, and has a clock source that uses the carry-over signal from a 18-bit timebase
timer or 15-bit watch timer. If the timer is not cleared within a certain time after the start, it resets
the CPU is reset.
■ Functions of Timebase Timer
The timebase timer is an 18-bit free-run counter (timebase counter) that counts up
synchronously with an internal count clock (in divide-by-2 oscillation). It has an interval timer
function to select one of four interval times. It also has a function to supply to other circuits the
output of the oscillation stabilization wait timer and operation clocks such as the watchdog timer.
The timebase timer uses the main clock irrespective of the MCS and SCS bits in CKSCR.
■ Watch timer Function
The watch timer provides the watchdog timer’s clock source, and acts as sub-clock oscillation
stabilization wait timer and interval timer by regularly generating an interrupt. It uses the subclock irrespective of the MCS and SCS bits in CKSCR.
214
9.2 Block Diagrams of Watchdog Timer/Timebase Timer/Watch Timer
9.2
Block Diagrams of Watchdog Timer/Timebase Timer/Watch
Timer
The block diagrams of the watchdog timer/timebase timer/watch timer are shown
below.
■ Block Diagrams of Watchdog Timer/Timebase Timer/Watch Timer
Figure 9.2-1 Block diagram of watchdog timer, timebase timer and watch timer
Divide-by-2
main oscillation
TBTC
TBC1
Selector
TBC0
2 11
2 13
2 15
2 18
TBTRES
Clock input
Timebase timer
2
11
2
13
2 15 2
18
TBR
TBIE
AND
Q
TBOF
S
R
Timebase
interrupt
WDTC
F2MC-16LX bus
WT1
Selector
WT0
2-bit counter
OF
CLR
Watchdog reset
generation circuit
CLR
WTE
To WDGRST
internal reset
generation
circuit
WTC
WDCS
AND
SCE
Q
SCM
Power-on reset,
sub-clock stop
S
R
WTC2
Selector
WTC0
WTR
WTIE
WTOF
Clock
interrupt
AND
Q
S
R
28
29
2 10
2 11
212
2 13
2 14
2 15
WTRES
210
14
2 13 2
215
Watch timer
Clock input
Divide-by-4
suboscillation
WDTC
PONR
From power-on
generation
WRST
ERST
RST pin
SRST
From LPMCR
register's RST
bit
215
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
9.3
List of Registers for Watchdog Timer/Timebase Timer/
Watch Timer
This section describes the registers used for the watchdog timer, timebase timer and
watch timer.
■ List of Registers for Watchdog Timer/TimeBase Timer/Watch Timer
Figure 9.3-1 lists the registers used for the watchdog timer, timebase timer and watch timer.
Figure 9.3-1 Registers for watchdog timer, timebase timer and watch timer
Watchdog control register
7
Address: 0000A8 H
PONR
Read/write =>
(R)
(X)
Initial value =>
Timebase timer control register
15
Address: 0000A9H
Reserved
(-)
Read/write =>
(1)
=>
Initial value
6
4
ERST
(R)
(X)
3
SRST
(R)
(X)
2
WTE
(W)
(1)
1
WT1
(W)
(1)
0
WT0
(W)
(1)
<= Bit position
WDTC
(-)
(-)
5
WRST
(R)
(X)
14
13
(-)
(-)
11
TBOF
(R/W)
(0)
10
TBR
(W)
(1)
9
TBC1
(R/W)
(0)
8
TBC0
(R/W)
(0)
<= Bit position
TBTC
(-)
(-)
12
TBIE
(R/W)
(0)
6
SCE
(R)
(0)
5
WTIE
(R/W)
(0)
4
WTOF
(R/W)
(0)
3
WTR
(W)
(1)
2
WTC2
(R/W)
(0)
1
WTC1
(R/W)
(0)
0
WTC0
(R/W)
(0)
<= Bit position
WTC
Watch timer control register
Address: 0000AA H
Read/write =>
Initial value =>
216
7
WDCS
(R/W)
(1)
9.3 List of Registers for Watchdog Timer/Timebase Timer/Watch Timer
9.3.1
Watchdog Timer Control Register (WDTC)
The watchdog timer control register (WDTC) indicates the watchdog timer start, clear,
and reset sources.
■ Bit Configuration for Watchdog Timer Control Register (WDTC)
Figure 9.3-2 shows the bit configuration of the watchdog timer control register (WDTC).
Figure 9.3-2 Bit configuration for watchdog timer control register (WDTC)
Address: 0000A8 H
Read/write =>
Initial value =>
7
PONR
6
(R)
(X)
(-)
(-)
5
4
WRST ERST
(R)
(R)
(X)
(X)
3
SRST
2
WTE
1
WT1
(R)
(X)
(W)
(1)
(W)
(1)
0
WT0
(W)
(1)
<= Bit position
WDTC
Note:
Do not access using read-modify type instructions, since they may cause an error in
operation.
[Bit 7 to 3] PONR, WRST, ERST, SRST
PONR, WRST, ERST, and SRST are flags indicating reset sources. They are set as shown
in Table 9.3-1 "PONR, WRST, ERST, and SRST (reset source bits)" by a reset. All bits are
cleared when reading the WDTC register.
These bits are read-only.
Table 9.3-1 PONR, WRST, ERST, and SRST (reset source bits)
Reset source
PONR
WRST
ERST
SRST
Power-on
1
−
−
−
Watchdog timer
*
1
*
*
External pin (RST input)
*
*
1
*
RST bit (software reset)
*
*
*
1
*: Previous value is retained.
[Bit 2] WTE
If the watchdog timer is in stop mode, WTE is set to "0" and the watchdog timer is operating.
By writing "0" twice or more, the watchdog timer counter is cleared. Writing "1" has no effect.
The watchdog timer enters the stop mode if any reset source is generated. "1" is output in
read operations.
217
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
[Bit 1, 0] WT1, 0
WT1 and WT0 are bits used to select the watchdog timer’s interval time. Data is valid only
when it is written at watchdog timer start; otherwise, writing is ignored. These bits can only
be written.
Use three bits to select the clock that is input to the watchdog timer: The watchdog timer is
selected based on the result of a logical AND between the watch timer control register WTC
WDCS bit and the clock selection register LPMCR SCM bit in the low-power consumption
control circuit, WT1, and WT0.
With WDCS set to "1," if the main clock and PLL clock are selected as the machine clock,
the output of the timebase timer is selected as clock input of the watchdog timer.
Alternatively, if the sub-clock timer is selected, output of the watch timer is selected as clock
input of the watchdog timer.
Setting the interval time with the WT1/WT0 bits is shown in Table 9.3-2 "WT1/0 (interval time
selection bit)".
Table 9.3-2 WT1/0 (interval time selection bit)
Interval time (Oscillation: 4 MHz)
WDCS•S
CM
WT1
1
0
1
WT0
Minimum
Maximum (*1)
0
Approx. 3.58 ms
Approx. 4.61 ms
0
1
Approx. 14.33 ms
Approx. 18.43 ms
1
1
0
Approx. 57.23 ms
Approx. 73.73 ms
1
1
1
Approx. 458.75 ms
Approx. 589.82 ms
0
0
0
Approx. 436 ms
Approx. 563 ms
0
0
1
Approx. 3.50 s
Approx. 4.50s
0
1
0
Approx. 7.0 s
Approx. 9.0 s
0
1
1
Approx. 14.0 s
Approx. 18.0 s
*1: The maximum interval is the value available when the watchdog timer is operating and
the timebase timer or watch timer is not reset.
218
9.3 List of Registers for Watchdog Timer/Timebase Timer/Watch Timer
9.3.2
Timebase Timer Control Register (TBTC)
The timebase timer control register (TBTC) is used to control interrupts by the
timebase timer and clear the timebase counter.
■ Bit Configuration of the Timebase Timer Control Register (TBTC)
Figure 9.3-3 shows the bit configuration for the timebase timer control register (TBTC.)
Figure 9.3-3 Bit configuration of the timebase timer control register (TBTC)
15
Reserved
Address: 0000A9 H
Read/write =>
(-)
(1)
Initial value =>
14
13
12
TBIE
11
TBOF
10
TBR
9
TBC1
(-)
(-)
(-)
(-)
(R/W)
(0)
(R/W)
(0)
(W)
(1)
(R/W)
(0)
8
<= Bit position
TBC0
TBTC
(R/W)
(0)
Note:
Do not use read-modify type instructions for accessing, since they may cause an error in
operation.
[Bit 15] Reserved
Bit 15 is a reserve bit. Always set it to "1".
[Bit 12] TBIE
The TBIE bit is used to enable interval interrupts by the timebase timer. If set to "1",
interrupts are enabled, if set to "0", interrupts are disabled. This bit can be read and written
and is cleared by a reset.
[Bit 11] TBOF
TBOF is an interrupt request flag of the timebase timer. If the TBIE bit set to "1", an interrupt
request is generated. Set it to "1" in intervals specified by the bits TBC1 and TBC0.
The TBOF bit is cleared by the conditions listed below.
- Writing "0"
- Transition to stop mode
- Transition from sub-clock mode to main clock mode
- Transition from main clock mode to PLL clock mode
- Reset
Writing "1" has no effect.
Reading by read-modify-write type instructions always returns "1."
219
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
[Bit 10] TBR
The TBR bit is used to clear all bits in the timebase timer’s counter to 0. Writing "0" will clear
the timebase counter. Writing "1" has no effect. "1" is always returned in read operations.
Note:
To clear the TBOF bit, use the TBIE bit or the CPU’s ILM bit when timebase timer interrupts
are masked.
[Bit 9, 8] TBC1 and TBC0
TBC1 and TBC0 are bits used to set the timebase timer’s interval.
At a reset, they will be initialized to 00B. These bits can be read and written.
Table 9.3-3 Interval time and cycle count of TBC1 and TBC0
220
TBC1
TBC0
Interval time for
oscillation: 4 MHz
Oscillation clock (oscillation)
cycle count
0
0
1.024 ms
212 cycles
0
1
4.096 ms
214 cycles
1
0
16.384 ms
216 cycles
1
1
131.072 ms
219 cycles
9.3 List of Registers for Watchdog Timer/Timebase Timer/Watch Timer
9.3.3
Watch Timer Control Register (WTC)
The watch timer control register (WTC) is used to select the clock signal, control
interrupts and intervals, and clear the counter.
The watch timer is a function only available in the MB90F423GB/GC, MB90F428GB/GC,
MB90423GB/GC, MB90427GB/GC, MB90428GB/GC.
■ Watch Timer Control Register (WTC)
Figure 9.3-4 shows the bit configuration of the watch timer control register (WTC).
Figure 9.3-4 Bit configuration of the watch timer control register
7
WDCS
Read/write => (R/W)
(1)
Initial value =>
Address: 0000AA H
6
SCE
(R)
(0)
5
WTIE
(R/W)
(0)
4
WTOF
(R/W)
(0)
3
WTR
(W)
(1)
2
WTC2
(R/W)
(0)
1
WTC1
(R/W)
(0)
0
<= Bit position
WTC0
WTC
(R/W)
(0)
[Bit 7] WDCS
The WDCS bit is used to select the watchdog timer’s clock source. If set to "0", the watch
timer’s clock output is selected as the watchdog timer’s clock source. If set to "1", the
timebase timer’s clock output is selected.
At reset, the bit is initialized to "1".
Note:
If WDCS is modified, the timebase timer and watch timer operate asynchronously with each
other, which means that the watchdog count may be shorter by 1 count. Therefore, to modify
WDCS, clear the watchdog timer immediately before the clock mode is modified.
[Bit 6] SCE
This bit is set to "1" when the sub-clock’s oscillation stabilization wait time has elapsed. The
sub-clock oscillation stabilization time is fixed to 214 cycles. This bit is initialized to "0" at
power-on reset and stop.
[Bit 5] WTIE
This bit is set to "1" to enable interval interrupts by the watch timer or set to "0" to disable
them. This bit can be read and written and is initialized to "0" by reset.
221
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
[Bit 4] WTOF
This bit is the watch timer’s interrupt request flag. If this bit is set to "1", an interrupt request
is generated. The WTOF bit is set to "1" in intervals set by bits WTC2 to WTC0.
The WTOF bit is cleared by the following conditions.
- Writing "0"
- Transition to stop mode
- Reset
Writing "1" has no effect.
Reading by a read-modify-write instruction always returns "1".
[bit 3] WTR
The WTR bit is used to clear the watch timer’s counter to all 0’s. If the WTR bit is set to "0",
the clock counter is cleared. Writing "1" has no effect. Reading this bit always returns "1."
[Bit 2, 1, 0] WTC2, WTC1, WTC0
The WTC2, WTC1, and WTC0 bits are used to set the watch timer’s interval. The settings for
the interval are shown in Table 9.3-4 "Selection of the watch timer interval". Reset initializes
bits WTC2 to WTC0 to 000B. This bit can be read and written.
Setting bits WTC2 to WTC0 requires setting the WTOF bit to "0".
Table 9.3-4 Selection of the watch timer interval
WTC2
WTC1
WTC0
Interval time *1
0
0
0
31.25 ms
0
0
1
62.5 ms
0
1
0
125 ms
0
1
1
250 ms
1
0
0
500 ms
1
0
1
1.00 s
1
1
0
2.00 s
1
1
1
4.00 s
*1: The value of the interval time applies for a sub-clock oscillation of 32.768 kHz.
222
9.4 Operation of Watchdog Timer/Timebase Timer/Watch Timer
9.4
Operation of Watchdog Timer/Timebase Timer/Watch Timer
This section describes the operation of the watchdog timer, timebase timer and watch
timer.
■ Operation
❍ Watchdog timer
The watchdog timer issues a reset request if, for example, due to the program running out of
control, the WDTC register’s WTE bit is not set to "0" in the specified time.
❍ Timebase timer
The timebase timer provides such timer functions as acting the watchdog timer’s clock source,
and providing the stabilization wait time for main clock and the PLL clock oscillation stabilization.
In addition, it provides an interval interrupt function by throwing interrupts in pre-defined
intervals.
❍ Watch timer
The watch timer acts as the watchdog timer’s clock source, provides the sub-clock’s oscillation
stabilization wait time, and also provides an interval interrupt function by generating interrupts in
pre-defined intervals.
223
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
9.4.1
Watchdog Timer Operation
The watchdog timer issues a reset request if, for example due to a program that ran
out of control, the WDTC register WTE bit is not set to "0" in the specified time.
■ Method of Starting the Watchdog Timer
When in stop mode, the watchdog timer can be started by setting the WDTC register WTE bit to
"0". After that, the reset generation interval of the watchdog timer is specified in the bits WT1
and WT0. Only the data at the time of the start of the watchdog timer is valid to set the interval.
■ Inhibiting Watchdog Timer Reset
After the start of the watchdog timer, the 2-bit watchdog counter must be regularly cleared by
the program. Concretely, the WDTC register WTE bit must be regularly set to "0". The watchdog
counter is a 2-bit counter that uses the timebase timer’s carry-over signal as clock source.
Therefore, if the timebase timer is cleared, the time before generation of a watchdog reset may
become longer than according to the original settings.
Figure 9.4-1 Watchdog timer operation
Timebase
Watchdog
00
01
10
00
01
10
11
00
WTE write
Watchdog start
Watchdog clear
Watchdog reset generated
■ Watchdog Stop
The watchdog timer can be stopped by various reset sources.
■ Clearing the Watchdog Timer
The watchdog timer is cleared by writing the WTE bit as well as by a reset or transition to sleep
mode, stop mode or watch mode.
In watch mode, the watchdog timer’s counter is cleared and then the count stops.
■ Confirming Reset Sources
After a reset, the reset source can be determined by checking the watchdog timer control
register (WDTC) PONR, WRST, ERST, and SRST bits.
224
9.4 Operation of Watchdog Timer/Timebase Timer/Watch Timer
■ Watchdog Timer’s Interval Time
Figure 9.4-2 shows the relationship between the timing the watchdog timer is cleared and its
interval time. The interval time varies depending on the timing for clearing the watchdog timer,
which requires 3.5 to 4.5 times the count clock interval.
Figure 9.4-2 Clear timing and interval time of watchdog timer
[WDG timer block diagram]
2-bit counter
Clock
selector
a
WTE bit
Divide-by-2 b
circuit
Count
enable
output circuit
Divide-by-2
circuit
c
Reset circuit
d
Reset
signal
Count enable and clearing
[Minimum interval time] If the WTE bit is cleared immediately before incrementing the
counter clock
Count start
Counter clear
Count clock a
Divide-by-2 interval b
Divide-by-2 interval c
Count enabled
Reset signal d
7x (count clock interval/2)
WTE bit clear
Watchdog reset occurred
[Maximum interval time] If WTE bit is cleared immediately after count clock starts
Count start
Counter clear
Count clock a
Divide-by-2 interval b
Divide-by-2 interval c
Count enabled
Reset signal d
WTE bit clear
9x(count clock interval/2)
Watchdog reset occurred
225
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
9.4.2
Timebase Timer Operation
The timebase timer provides such timer functions as acting the watchdog timer’s clock
source, and providing the stabilization wait time for main clock and the PLL clock
oscillation stabilization. In addition, it provides an interval interrupt function by
throwing interrupts in pre-defined intervals.
■ Timebase Timer Operation
The timebase timer consists of an 18-bit counter and uses a main clock as a count clock. While
a main clock is input, count operation continues.
Timebase counter is cleared by the following conditions:
•
Power-on reset
•
Transition to stop mode
•
Transition from the main clock mode to PLL clock mode by the CKSCR register’s MCS bit
•
Transition from the main clock mode to sub-clock mode by the CKSCR register’s SCS bit
•
Setting the TBTC register’s TBR bit to "0".
The watchdog timer and interval interrupt functions, which use the output of the timebase timer,
are affected by clearing the timebase timer.
■ Interval Interrupt Function
This function is used to create interrupts in constants intervals using the timebase counter’s
carry-over signal. It sets the TBOF flag each time the interval set by the bits TBC0 and TBC1 in
the TBTC register elapses. This flag is set based on the time the timebase timer is finally
cleared.
If a transition from main clock mode to PLL clock mode occurs, the timebase timer is cleared,
since the timebase timer is used as a timer for waiting for a stabilization of the PLL clock’s
oscillation.
If a transition to stop mode occurs, the timebase timer is used as a timer for waiting for
oscillation stabilization when operation resumes. For this reason, the TBOF flag is cleared at the
same time as the mode transition.
■ Timebase Timer Interrupts
If the timebase timer counter counts up with the internal count clock and the bit of the selected
interval timer overflows, the interrupt request flag bit (TBOF bit of the TBTC register) is set to
"1". Therefore, if the interrupt request enable bit is set to enabled (TBTC register TBIE=1), an
interrupt request is sent to the CPU (#35). In the interrupt handling routine, set the TBOF bit to
"0" to clear the interrupt request. The TBOF bit is set if the specified bit overflows, irrespective of
the TBIE bit value.
When the TBOF bit is set to "1" and the TBIE bit is switched from "disabled" to "enabled" ("0" to
"1"), an interrupt request is generated immediately.
Note:
To clear the interrupt request flag bit (TBTC: TBOF), set the TBIE bit or ILM bit in the
processor status register (PS) so that timebase timer interrupts are disabled.
226
9.4 Operation of Watchdog Timer/Timebase Timer/Watch Timer
■ Timebase Timer Interrupts and EI2OS
Table 9.4-1 "Timebase timer interrupts and EI2OS" shows the relationship between timebase
timer’s interrupts and EI2OS.
Table 9.4-1 Timebase timer interrupts and EI2OS
Interrupt level set register
Vector table address
Interrupt
number
Register name
Address
Lower bits
Higher bits
Bank
#35(23H)
ICR12
0000BCH
FFFF70H
FFFF71H
FFFF72H
EI2OS
×
×: Not available
Notes:
•
ICR12 is commonly used by timebase timer interrupts and watch timer (sub-clock) interrupts.
The interrupt is therefore used for two purposes, but the interrupt level is the same.
•
The timebase timer cannot use the extended intelligent I/O service (EI2OS)
■ Timer Function for the Oscillation stabilization Wait Time
The timebase timer is used to provide the stabilization wait time of the oscillation clock and the
PLL clock’s oscillation. Oscillation stabilization wait time is counted starting from a counter set to
"0" (count clear) and ends when the oscillation stabilization wait time bit overflows. If, however,
a return from the timebase timer mode to the PLL clock mode occurs, the timebase timer
counter is not cleared and indicates a time in between after counting started. Table 9.4-2
"Clearing the timebase timer counter and oscillation stabilization wait time" shows the
relationship between clearing the timebase counter and the oscillation stabilization wait time.
Table 9.4-2 Clearing the timebase timer counter and oscillation stabilization wait time
Counter
clear
TBOF
clear
Writing "0" to TBR in TBTC
Y
Y
Power-on reset
Y
Y
Oscillation stabilization wait time of the
oscillation clock
Releasing stop mode
Y
Y
Oscillation stabilization wait time of the
oscillation clock (at return to main clock
mode)
Transition from oscillation clock mode
to PLL clock mode (MCS= 1 -->0)
Y
Y
Oscillation stabilization wait time of the PLL
clock
Releasing timebase timer mode
N
N
Oscillation stabilization wait time of the PLL
clock (at return to PLL clock mode)
Releasing sleep mode
N
N
Operation
Oscillation stabilization wait time
Y: used
N: not used
227
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
9.4.3
Watch Timer Operation
The watch timer acts as the watchdog timer’s clock source, provides the sub-clock’s
oscillation stabilization wait time, and also provides an interval interrupt function by
generating interrupts in pre-defined intervals.
■ Watch Timer Operation
The watch timer consists of a 15-bit counter and uses a sub-clock as a count clock. While a
sub-clock is input, count operation continues. The watch timer is cleared by a transition to
power-on reset and stop mode and by setting the writing WTC register’s WTR bit to "0".
The watchdog timer and interval interrupt, which use the watch timer’s output, are affected by
clearing the watch timer.
■ Interval Interrupt Function of the Watch Timer
The interval interrupt function generates interrupts in constant intervals based on carry-over
signals of the watch timer. It sets the WTOF flag at regular intervals that are specified by the
WTC2 to WTC0 bits of the WTC register. This timing, which is set by flags, determines the time
when the watch timer is finally cleared.
In a transition to stop mode, the watch timer is used to provide the oscillation stabilization wait
time before operation resumes. For this reason, the WTOF flag is also cleared at a mode
transition.
■ Watch Timer Interrupts and EI2OS
Table 9.4-3 "Watch timer interrupts and EI2OS" shows the relationship between watch timer
interrupts and EI2OS.
Table 9.4-3 Watch timer interrupts and EI2OS
Interrupt level set register
Vector table address
Interrupt
number
Register name
Address
Lower bits
Higher bits
Bank
#36(24H)
ICR12
0000BCH
FFFF6CH
FFFF6DH
FFFF6EH
×: Not available
228
EI2OS
×
9.5 Notes on Using The Watchdog Timer/Timebase Timer
9.5
Notes on Using The Watchdog Timer/Timebase Timer
This section provides notes on using the watchdog timer and clearing an interrupt
request when using a timebase timer. It also describes the effects of clearing the
timebase timer on peripheral functions.
■ Notes on Using the Watchdog Timer
❍ Stopping the watchdog timer
The watchdog timer is stopped by any of the reset sources.
❍ Interval time
The interval time is determined by a count clock that uses a carry-over of the timebase timer or
watch timer. For this reason, the watchdog timer’s interval time may be longer than according to
the original setting when the counter of the clock source is cleared in between.
❍ Selection of interval time
The interval time can only be set at the start of the watchdog timer. Data written after the
watchdog timer has started is ignored.
❍ Notes on program creation
To create a program that repeatedly clears the watchdog timer in the main loop, the processing
time of the main loop, including interrupt handling, may not exceed the minimum interval time of
the watchdog timer.
❍ Watchdog timer operation in timebase timer mode
In timebase timer mode, the timebase timer operates while the watchdog timer stops.
■ Notes on Using the Timebase Timer
❍ Clearing an interrupt request
Clearing the TBOF bit of the timebase timer control register must be performed via the TBIE bit
of the interrupt level mask register (ILM) of the processor status register (PS) while timebase
timer interrupts are masked.
❍ Effects of clearing the timebase timer
The following operations are affected by clearing the timebase timer’s counter.
•
Use of an interval timer function (interval interrupt) by the timebase timer
•
Use of the watchdog timer
229
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
❍ Using the oscillation stabilization wait timer
In main stop mode, the main clock oscillation stops at power-on. Therefore, the main clock,
which uses the operation clock provided from the timebase timer, requires an oscillation
stabilization wait time after the oscillator has started operation. Select an appropriate oscillation
stabilization wait time for the type of resonator connected to the main clock’s oscillator (clock
generation section). For details, refer to Section 5.5 "Oscillation stabilization wait time".
❍ Notes on peripheral functions whose clock is provided by the timebase timer
In the mode in which main clock oscillation stops, the counter is cleared and the timebase timer
stops. The clock is input from the timebase timer in the state after initialization if the timebase
timer’s counter is cleared. Therefore, the "H" level may be shortened or the "L" level may be
prolonged by 1/2 an interval at maximum. Although the watchdog timer’s clock is also supplied
in the state after initialization, the watchdog timer’s counter is cleared as well, causing the
watchdog timer to operate with the standard interval length.
■ Operation of the Timebase Timer
Figure 9.5-1 shows the operation in the following states:
•
When a power-on reset occurs
•
Transition to sleep mode occurs during operation of the interval timer function.
•
Transition to stop mode occurs.
•
A counter clear request occurs.
Transition to stop mode clears the timebase timer, and operation stops. At the return from the
stop mode, the timebase timer counts the oscillation stabilization wait time.
Figure 9.5-1 Operation of timebase timer
Counter value
3FFFFH
Clearing by transition
to stop mode
Oscillation
stabilization
wait overflow
00000H
CPU operation
started
Power-on reset
(option)
Interval
Counter cleared
(TBTC: TBR=0)
(TBTC: TBC1, TBC0=11H)
Cleared by interrupt handling routine
TBOF bit
TBIE bit
SLP bit
(LPMCR register)
Sleep
Interval interrupt sleep released
Stop
STP bit
(LPMCR register)
Stop cleared by external interrupt
If the timebase timer control register's interval time selection bit (TBTC TBC1, TBC0) is
set to 11B (219/HCLK).
: Oscillation stabilization wait time
230
9.6 Example Program for Watchdog Timer/Timebase Timer
9.6
Example Program for Watchdog Timer/Timebase Timer
An example program for the watchdog timer/timebase timer is shown below.
■ Example Program for Watchdog Timer
❍ Specification of processing
The watchdog timer is cleared with every loop in the main program.
One cycle of the main loop may not take more than the minimum interval time of the watchdog
timer.
[Coding example]
WDTC
EQU
0000A8H
;Watchdog timer control register
WTE
EQU
WDTC:2
;Watchdog control bit
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer register (SP) ends
;the initialization
WDG_START:
MOV
WDTC,#00000011B ;Watchdog timer started
;Interval time of 221 ± 218 cycles selected
;----------Main loop--------------------------------------------------------MAIN: CLRB
I:WTE
;Watchdog timer cleared
;
:
;2 bits regularly cleared
;
User process
;
:
JMP
MAIN
;One cycle of the loop completes
;within the interval time of the
;watchdog timer
CODE
ENDS
;----------Vector setting---------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFDCH
;Reset vector setting
DSL
START
DB
00H
;Set to single-chip mode
VECT
ENDS
END
START
231
CHAPTER 9 WATCHDOG TIMER/TIMEBASE TIMER/WATCH TIMER (SUB-CLOCK)
■ Example Program of Timebase Timer
❍ Specification of processing
Interval interrupts are repeated with an interval of 212/HCLK (HCLK: oscillation clock). The
resulting interval time is about 1.0 ms (at 4 MHz operation).
[Coding example]
ICR12
;Interrupt control register for
;timebase timer
TBTC
EQU
0000A9H
;Timer base timer control register
TBOF
EQU
TBTC:3
;Interrupt request flag bit
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer register (SP) ends
;the initialization
AND
CCR, #0BFH
;Interrupt disabled
MOV
I:ICR12, #00H
;Interrupt level 0 (highest)
MOV
I:TBTC, #10010000B ;Higher 3 bits are fixed
;Interrupts enabled, TBOF clear
;Counter clear
;Selection of 212/HCLK interval time
MOV
ILM, #07H
;ILM in PS is set to level 7
OR
CCR, #40H
;Interrupt enabled
LOOP: MOV
A,#00H
;Infinite loop
MOV
A,#01H
BRA
LOOP
;----------Interrupt--------------------------------------------------------WARI:
CLRB
I:TBOF
;Clear interrupt request program
;
:
;
User process
;
:
RETI
;Return from interrupt
CODE
ENDS
;----------Vector setting---------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FF70H
;Setting vector to interrupt #35(23H)
DSL
WARI
ORG
0FFDCH
;Reset vector setting
DSL
START
DB
00H
;Setting to single-chip mode
VECT
ENDS
END
START
232
EQU
0000BCH
CHAPTER 10
INPUT CAPTURE
This chapter describes the input capture operation.
10.1 "Outline of Input Capture"
10.2 "Block Diagram of Input Capture"
10.3 "List of Input Capture Registers"
10.4 "Description of Operation"
233
CHAPTER 10 INPUT CAPTURE
10.1 Outline of Input Capture
The input capture unit consists of one 16-bit free-run timer and four 16-bit input
captures.
■ Configuration
❍ Input capture (x 4)
The input capture consists of four independent external input pins and their corresponding
capture registers and control registers. Based on detection of any of the edges of signals input
from external input pins, the 16-bit free-run timer value can be stored in the capture register and
an interrupt can be generated at the same time.
Any valid edge (both rising and falling edges) of the external input signal can be selected.
Four input captures can operate independently.
Interrupts can be generated at any valid edge of the external input signal.
❍ 16-bit free-run timer (x 1)
The 16-bit free-run timer consists of a 16-bit up-counter, a control register, a 16-bit compare
clear register, and a prescaler. The output value of this counter is used to provide the basic time
for the input capture. (In this case, the counter becomes the base timer)
The frequency of the counter operation clock can be selected from among eight types. There
are eight internal clock frequencies:
Φ, Φ/2, Φ/4, Φ/8, Φ/16, Φ/32, Φ/64 and Φ/128 (Φ: Machine clock frequency).
An interrupt can be generated by compare matching overflows of the counter value with the
compare clear register (use of compare matching requires a mode setting).
The counter value is initialized to 0000H using a compare matching with reset, software clear,
and the compare clear register.
234
10.2 Block Diagram of Input Capture
10.2 Block Diagram of Input Capture
This section provides a block diagram of the input capture.
■ Block Diagram
Figure 10.2-1 Block diagram of the input capture
Interrupt
#31(1FH)
IVF
IVFE
STOP MODE SCLR CLK2 CLK1 CLK0
Divider
Clock
16-bit free-run timer
FFMC-16LX Bus
16-bit compare clear register
Interrupt
#33(21H)
Compare circuit
MSI3 to 0
ICLR
ICRE
A/D start
Capture data register 0/2
Edge detection
IN0/2
EG11 EG10 EG01 EG00
Edge detection
Capture data register 1/3
ICP0
ICP1
ICE0
IN1/3
ICE1
Interrupt
#19, #23
#15,#21
235
CHAPTER 10 INPUT CAPTURE
10.3 List of Input Capture Registers
This section lists the input capture registers.
■ 16-Bit Free-run Timer Section Registers
Figure 10.3-1 "16-bit free-run timer section registers" lists the 16-bit free-run timer section
registers.
Figure 10.3-1 16-bit free-run timer section registers
Higher 8 bits of compare clear register Bit15
Address : 000025H
Lower 8 bits of compare clear register
Address : 000024H
Higher 8 bits of timer data register
Address : 000027H
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
CL15 CL14 CL13 CL12
CL11 CL10 CL09 CL08
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CL07 CL06 CL05
CL04 CL03 CL02 CL01 CL00
R/W
CPCLR
Read/write
Initial value
CPCLR
R/W
R/W
Read/write
(X)
(X)
Initial value
R/W
R/W
R/W
R/W
R/W
(X)
(X)
(X)
(X)
(X)
(X)
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
T15
T14
T13
T12
T11
T10
T09
T08
TCDT
Read/write
Initial value
R/W
(0)
Lower 8 bits of timer data register lower
Bit7
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
T07
T06
T05
T04
T03
T02
T01
T00
TCDT
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/write
Initial value
Bit15
Bit14
Bit13
Address : 000026H
Timer control status register
Address : 000029H
ECKE
(-)
(-)
Bit7
Bit6
Bit5
IVF
IVFE
R/W
(0)
Timer control status register
Address : 000028H
R/W
(0)
236
Bit14
R/W
(0)
Bit12
Bit11
Bit10
Bit9
Bit8
MSI2
MSI1 MSI0 ICLR ICRE
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Bit4
Bit3
Bit2
Bit1
Bit0
STOP MODE SCLR CLK2 CLK1 CLK0
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
TCCS
Read/write
Initial value
TCCS
Read/write
Initial value
10.3 List of Input Capture Registers
■ Input Capture Section Registers
Figure 10.3-2 "Input capture section registers" lists the input capture section registers.
Figure 10.3-2 Input capture section registers
Higher 8 bits of input capture data register
Address:
Address:
Address:
Address:
ch0 000061 H
ch1 000063 H
ch2 000065 H
ch3 000067 H
Lower 8 bits of input capture data register
Address: ch0 000060 H
Address: ch1 000062 H
Address: ch2 000064 H
Address: ch3 000066 H
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
IPCP0-3
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R
(X)
R
(X)
Bit 7
R
(X)
Bit 6
R
(X)
Bit 5
R
(X)
Bit 4
R
(X)
Bit 3
R
(X)
R
(X)
Bit 2
Bit 1
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICP3
ICP2
ICE3
ICE2 EG31 EG30 EG21 EG20
R/W
(O)
R/W
(O)
R/W
(O)
R/W
(O)
R/W
(O)
R/W
(O)
R/W
(O)
R/W
(O)
Lower 8 bits of capture control register
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
ICP1
ICP0
ICE1
ICE0
EG11 EG10 EG01 EG00
R/W
(O)
R/W
(O)
R/W
(O)
R/W
(O)
00006A H
000068H
Bit 0
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
R
(X)
Address:
Read/write
Initial value
IPCP0-3
R
(X)
Higher 8 bits of capture control register
Bit 8
R/W
(O)
R/W
(O)
R/W
(O)
R/W
(O)
Read/write
Initial value
ICS23
Read/write
Initial value
ICS01
Read/write
Initial value
237
CHAPTER 10 INPUT CAPTURE
10.3.1 Detailed Description of the Input Capture Registers
There are two types of input capture data registers:
• Input capture data register (IPCP0 to 3)
• Input capture control registers (ICS01/23)
■ Input capture data register (IPCP0-3)
The IPCP register is used to store the value of the 16-bit free-run timer at detection of a valid
edge of the corresponding external pin input waveform (word access allowed; writing not
allowed).
Figure 10.3-3 Configuration of input capture data register (IPCP0-3)
higher 8 bits of input capture data register
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Address:
Address:
Address:
Address:
ch0 000061 H
ch1 000063H
ch2 000065 H
ch3 000067 H
Bit 8
IPCP0-3
CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
R
(X)
Read/write
Initial value
Lower 8 bits of input capture data register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Address: ch0 000060 H
IPCP0-3
Address: ch1 000062H
CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00
Address: ch2 000064 H
R
R
R
R
R
R
R
R
Address: ch3 000066 H
Read/write
(X)
(X)
(X)
(X)
(X)
(X)
(X)
(X)
Initial value
■ Input Capture Control Status Register (ICS01, ICS23)
Figure 10.3-4 Configuration of input capture control status register (ICS01, ICS23)
Higher 8 bits of capture control register
Address: 00006A H
Lower 8 bits of capture control register
Address: 000068 H
238
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICP3
ICP2
ICE3 ICE2
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ICP1
ICP0
ICE1
ICE0
EG11 EG10 EG01 EG00
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
EG31 EG30 EG21 EG20
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
ICS23
Read/write
Initial value
ICS01
Read/write
Initial value
10.3 List of Input Capture Registers
[bit 7, 6]: ICP3, ICP2, ICP1, ICP0
These bits are input capture interrupt flags. When a valid edge is detected at the external
input pin, the corresponding bit is set to "1". In combination with the interrupt enable bits
(ICE3, ICE2, ICE1, ICE0) set, an interrupt can be generated at detection of a valid edge. The
corresponding bits are cleared by writing "0". Writing "1" has no effect. In read-modify-write
type instructions, "1" is returned.
0
No valid edge detected (initial value)
1
Valid edge detected
ICPn: n indicates the channel number of the input capture.
[bit 5, 4]: ICE3, ICE2, ICE1, ICE0
These bits are input capture interrupt enable bits. With the ICE bit set to "1," an input capture
interrupt is generated if the corresponding interrupt flag (ICP3, ICP2, ICP1, or ICP0) is set to
"1."
0
Interrupt prohibited (initial value)
1
Interrupt enable
ICEn: n indicates the channel number of the input capture.
[bit 3 to 0]: EG31/30, EG21/20, EG11/10, EG01/00
These bits are used to select the polarity of a valid edge from the external input. They are
also used for enabling input capture operation.
EG31
EG30
Edge detection polarity
0
0
No edge detected (stop state) (initial value)
0
1
Rising edge detected
1
0
Falling edge detected
1
1
Both edges detected
and
EGn1/EGn0: n indicates the channel number of the input capture.
239
CHAPTER 10 INPUT CAPTURE
10.3.2 Detailed Description of 16-Bit Free-run Timer Register
There are three types of 16-bit free-run timer registers:
• Data register (TCDT)
• Compare clear register (CPCLR)
• Timer control status register (TCCS)
■ Data Register (TCDT)
Figure 10.3-5 Configuration of the data register (TCDT)
Higher 8 bits of the timer data register
Address: 0000 27H
Lower 8 bits of the timer data register
Address: 000026 H
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
T15
T14
T13
T12
T11
T10
T09
T08
TCDT
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Read/write
Initial value
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
T07
T06
T05
T04
T03
T02
T01
T00
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
TCDT
Read/write
Initial value
This is a register used to read the count value for the 16-bit free-run timer. The counter value is
cleared to "0000" at reset. The timer value can be set by writing to this register. Be sure the
write operation is always performed in stop (STOP=1) state. This register only allows word
access. The 16-bit free-run timer is initialized by the following:
240
•
Reset
•
Clearing (CLR) the control/status registers
•
Matching the compare clear register value and timer counter value (this requires to set a
mode)
10.3 List of Input Capture Registers
■ Compare Clear Register (CPCLR)
Figure 10.3-6 Configuration of the compare clear register (CPCLR)
Higher 8 bits of the compare clear register
Bit15
Address: 0000 25 H
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
CL15 CL14 CL13 CL12
CL11 CL10 CL09 CL08
R/W
(X)
Lower 8 bits of the compare clear register
Bit7
Address: 0000 24H
Bit14
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
CL07 CL06 CL05 CL04 CL03 CL02 CL01 CL00
R/W
R/W
R/W
R/W
R/W
(X)
(X)
(X)
(X)
(X)
R/W
(X)
R/W
R/W
(X)
(X)
CPCLR
Read/write
Initial value
CPCLR
Read/write
Initial value
This compare register is a 16-bit compare register used for comparison with a free-run timer.
The register value at initialization is not specified. Thus, its operation is enabled after a value
has been set. This register allows only word access. If the register value matches the value of
the 16-bit free-run timer value, the 16-bit free-run timer value is initialized to 0000H to set the
compare clear interrupt flag. If interrupts are enabled, an interrupt request is issued to the CPU.
241
CHAPTER 10 INPUT CAPTURE
■ Timer Control Status Register (TCCSH, TCCSL)
Figure 10.3-7 Configuration of the timer control status register (TCCSH, TCCSL)
Timer control status register
Bit15
Address: 000029 H
Bit14
Timer control status register Bit7
Bit12
Bit11
Bit10
Bit9
Bit8
MSI2 MSI1 MSI0 ICLR ICRE
ECKE
R/W
( 0)
Address: 000028 H
Bit13
(- )
(- )
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
IVF
IVFE STOP MODE SCLR CLK2 CLK1 CLK0
R/W
R/W
(0)
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
R/W
(0)
TCCS
Read/write
Initial value
TCCS
Read/write
Initial value
[Bit 15]: ECKE
This bit is used to select whether to use an internal or external source for the count clock the
16-bit free-run timer. The clock is updated immediately after setting or clearing the ECKE bit.
For this reason, be sure to change this bit only while output compare and input capture are
stopped.
0
Internal clock source is selected (initial value)
1
Clock is input from the external pin (FRCK)
Note:
With the internal clock selected, specify the count clock in bit 2 to bit 0 (CLK2 to CLK0). This
count clock works as a base clock. If the clock is input from FRCK, set bit 7 of DDR1 to "0".
[Bit 14, 13]: Undefined bit
These bits are undefined. (An unspecified value is read from these bits. Writing these bits
has no effect.)
[Bit 12, 11, 10]: MSI2, MSI1, MSI0
These bits are used to set a count for masking compare clear interrupts. They are set with
the 3-bit reload counter: Every time the counter value is set to 000B, the count value is
reloaded. The counter value is also reloaded by writing to the register of these bits. Set these
bits so that the mask count equals the setting count. (For example, for masking twice and
throwing an interrupt the third time, set these bits to 010B.) However, note that setting these
bits 000B effectively disables masking interrupt sources.
[Bit 9]: ICLR
This bit is an interrupt request flag for compare clear. The ICLR bit is set to "1" if the
compare clear register value and the value of the 16-bit free-run timer value match, and the
counter is cleared. An interrupt occurs if the interrupt request enable bit (bit 8: ICRE) is set.
The ICLR bit is cleared by writing "0". Writing "1" has no effect. A read-modify-write type
instruction always returns "1."
242
0
No interrupt requested (initial value)
1
Interrupt requested
10.3 List of Input Capture Registers
[Bit 8]: ICRE
This bit is an interrupt enable bit for compare clear. If, with the ICRE bit set to "1," the
interrupt flag (bit 9: ICLR) is set to "1," an interrupt is generated.
0
Interrupt disabled (initial value)
1
Interrupt enabled
[Bit 7]: IVF
This bit is an interrupt request flag for the 16-bit free-run timer. If the 16-bit free-run
overflows, the IVF bit is set to "1". If the interrupt request enable bit (bit 6: IVFE) is set, an
interrupt is generated. The IVF bit is cleared by writing "1". Writing "1" has no effect. Readmodify-write type instructions always return "1".
0
No interrupt requested (initial value)
1
Interrupt requested
[bit 6]: IVFE
This bit is an interrupt enable bit for the 16-bit free-run timer. If, with the IVFE bit set to "1,"
the interrupt flag (bit 7: IVF) is set to "1," an interrupt is generated.
0
Interrupt disabled (initial value)
1
Interrupt enabled
[bit 5]: STOP
This bit is used to stop counting the 16-bit free-run timer. Writing "1" will stop counting the
timer. Writing "0" starts counting the timer. If the 16-bit free-run timer stops, the output
compare operation also stops.
0
Count enabled (operation) (initial value)
1
Interrupt enabled
[bit 4]: MODE
This bit is used to set the initialization condition of the 16-bit free-run timer. If set to "0", the
counter is initialized by reset and setting the clear bit (bit 3: CLR). If set to "1", the counter is
initialized by matching with the compare clear register value in addition to reset and setting
the clear bit (bit 3: CLR).
The counter value is initialized when the count value changes.
0
Initialized by reset or clear bit (initial value)
1
Initialized by reset and setting the clear bit or by matching with the
compare clear register
243
CHAPTER 10 INPUT CAPTURE
[bit 3]: SCLR
This bit is used to initialize the 16-bit free-run timer during operation to 0000H. Writing "1"
initializes the counter to 0000H. Writing "0" has no effect. Read operations always return "0".
The counter is initialized when the count value changes.
To initialize in timer stop mode, write 0000H to the data register.
SCLR
Meaning of flag
0
No meaning (initial value)
1
Counter initialized to 0000H
[bit 2, 1, 0]: CLK2, CLK1, CLK0
These bits are used to select a counter clock for the 16-bit free-run timer. Because the clock
changes immediately after setting the CLK bit, change the bit only when output compare and
input capture are in the stop mode.
CLK2
CLK1
CLK0
Count clock frequency
0
0
0
Φ
62.5 ns
125 ns
0.25 µs
1 µs
0
0
1
Φ/2
125 ns
0.25 µs
0.5 µs
2 µs
0
1
0
Φ/4
0.25 µs
0.5 µs
1 µs
4 µs
0
1
1
Φ/8
0.5 µs
1 µs
2 µs
8 µs
1
0
0
Φ/16
1 µs
2 µs
4 µs
16 µs
1
0
1
Φ/32
2 µs
4 µs
8 µs
32 µs
1
1
0
Φ/64
4 µs
8 µs
16 µs
64 µs
1
1
1
Φ/128
8 µs
16 µs
32 µs
128 µs
Φ = Machine clock frequency
244
F=16MHz
F=8MHz
F=4MHz
F=1MHz
10.4 Description of Operations
10.4 Description of Operations
This section describes the operations of the input capture.
■ Description of Operations
❍ 16-bit free-run timer
The 16-bit free-run timer starts counting from 0000H after a reset is released. This counter value
is used as the reference value for 16-bit output compare and 16-bit input capture.
❍ 16-bit input capture
The 16-bit input capture is used to capture a 16-bit free-run timer value into the capture register
to generate an interrupt when a pre-specified valid edge is detected.
■ Input Capture Interrupts and EI2OS
Table 10.4-1 "Input capture interrupts and EI2OS" shows the relationship between input capture
interrupts and EI2OS.
Table 10.4-1 Input capture interrupts and EI2OS
Channel
Interrupt
number
Interrupt level set
register
Register
name
Vector table address
EI2OS
Address
Lower
bits
Higher
bits
Bank
Input capture 0
#15(0FH)
ICR02
0000B2H
FFFFC0H
FFFFC1H
FFFFC2H
*
Input capture 1
#19(13H)
ICR04
0000B4H
FFFFB0H
FFFFB1H
FFFFB2H
*
Input capture 2
#21(15H)
ICR05
0000B5H
FFFFA8H
FFFFA9H
FFFFAAH
*
Input capture 3
#23(17H)
ICR06
0000B6H
FFFFA0H
FFFFA1H
FFFFA2H
*
Free-run timer
overflow
#31(1FH)
ICR10
0000BAH
FFFF80H
FFFF81H
FFFF82H
×
Free-run timer
clear
#33(21H)
ICR11
0000BBH
FFFF78H
FFFF79H
FFFF7AH
×
×: cannot be used
*: Available when not using interrupt sources sharing ICR02, ICR04, ICR05, ICR06, and the interrupt vector.
245
CHAPTER 10 INPUT CAPTURE
10.4.1 16-bit Input Capture
The 16-bit input capture is used to capture a 16-bit free-run timer value into the capture
register to generate an interrupt if a pre-specified valid edge is detected.
■ Operation of 16-bit Input Capture
Figure 10.4-1 Example of input capture
Counter value
FFFFh
BFFFh
7FFFh
3FFFh
0000 h
Time
IN0
IN1
IN example
Data register 0
Unspecified
3FFFh
Data register example
BFFFh
Unspecified
Data register 1
Unspecified
BFFFh
7FFFh
Capture 0 interrupt
Capture 1 interrupt
Capture example interrupt
Capture 0= rising edge
Capture 1= falling edge
Capture example = both edges (example)
246
Repeated interrupt by valid edge
Interrupt by software
10.4 Description of Operations
■ Input Timing for 16-bit Input Capture
Figure 10.4-2 Capture timing for input signal
Counter value
Input capture input
Edge
Capture signal
Capture register value
Interrupt
247
CHAPTER 10 INPUT CAPTURE
10.4.2 16-bit Free-run Timer Section
The 16-bit free-run timer is used to start the counter from 0000H after a reset is cleared.
This counter value is used as a reference time for 16-bit output compare and 16-bit
input capture.
■ Explanation of 16-bit Free-run Timer Operation
The counter value is cleared in the following conditions:
•
Overflow occurs
•
Compare-match with compare clear register value successful (this requires to set a mode)
•
Setting the SCLR bit of the TCCS register to "1" during operation
•
Writing 0000H to TCDT in timer stop mode
An interrupt may occur if an overflow is generated or the counter is cleared by matching with the
compare clear register value (for using a compare match interrupts, a mode setting is required.)
Figure 10.4-3 Clearing the counter at an overflow
Counter
FFFFh
BFFFh
7FFFh
3FFFh
Time
0000 h
Reset
Interrupt
Figure 10.4-4 Clearing the counter by matching with the compare clear register value
Counter
Matched
Matched
3FFFh
Time
0000 h
Reset
Compare register
Interrupt
248
BFFFh
10.4 Description of Operations
■ Clear Timing for the 16-bit Free-run Timer
The counter is cleared by reset, by software, and matching with the compare clear register.
Counter clearing by reset and by software is performed as soon as the clear source occurs,
while counter clearing by matching with the compare clear register is performed after
synchronizing with the count timing.
Figure 10.4-5 Clear timing for free-run timer
Compare clear register value
Compare latch
Counter value
■ Count Timing for the 16-bit Free-run Timer
The 16-bit free-run timer counts up using the clock (internal or external clock) input. If an
external clock is selected, counting occurs at the rising edge.
Figure 10.4-6 Count timing for the 16-bit free-run timer
External clock input
Count clock
Counter value
249
CHAPTER 10 INPUT CAPTURE
250
CHAPTER 11
16-BIT RELOAD TIMER
This chapter describes the functions and operations of the 16-bit reload timer.
11.1 "Overview of 16-Bit Reload Timer"
11.2 "Configuration of 16-Bit Reload Timer"
11.3 "Pins of 16-Bit Reload Timer"
11.4 "Registers of 16-Bit Reload Timer"
11.5 "Interrupts of 16-Bit Reload Timer"
11.6 "Operation of 16-Bit Reload Timer"
11.7 "Notes on Using the 16-Bit Reload Timer"
11.8 "Sample Programs for the 16-Bit Reload Timer"
251
CHAPTER 11 16-BIT RELOAD TIMER
11.1 Overview of 16-Bit Reload Timer
The 16-bit reload timer has two modes: Internal clock mode (with countdown
performed in synchronization with three types of internal clock), and event count mode
(with countdown performed by detecting any pulse edge input to the external pin).
Either mode may be selected. The timer defines an underflow when the counter value
is in the range from 0000H to FFFFH. In other words, an underflow occurs at a count of
[reload register’s setting value +1].
The counter can be used to select either reload mode, in which an underflow causes
the count set value to be reloaded for repeated counting, or one-shot mode, in which
counting is stopped when an underflow occurs. Counter underflow may generate an
interrupt and supports the extended intelligent I/O service (EI2OS).
■ Operation Mode of 16-Bit Reload Timer
Table 11.1-1 "Operation modes of 16-bit reload timer" lists the operation modes of the 16-bit
reload timer.
Table 11.1-1 Operation modes of 16-bit reload timer
Clock mode
Counting
Reload mode
Internal clock mode
One-Shot mode
Event count mode
(External clock mode)
16-bit reload timer operation
Software trigger operation
External trigger operation
External gate input operation
Reload mode
Software trigger operation
One-Shot mode
■ Internal Clock mode
One type of count clock is selected among three types of internal clocks to operate as follows:
❍ Software trigger operation
Sets the Timer control status register (TMCSR0/1): TRG bit to "1" to start count operation.
Trigger input by using the TRG bit is also enabled for external trigger input and external gate
input.
❍ External trigger operation
Starts counting when the edge selected (leading, trailing, or both) is input to the TIN0/1 pin.
❍ External gate input operation
Continues counting when the signal level selected ("L" or "H") is input to the TIN0/1 pin.
252
11.1 Overview of 16-Bit Reload Timer
■ Event Count mode (External Clock Mode)
Event count mode provides a function for starting countdown when a valid edge selected
(leading, trailing, or both) is input to the TIN0/1 pin. It is also used as an interval timer when
using an external clock with a constant interval.
■ Counter operation
❍ Reload mode
If the countdown causes an underflow, and a transfer of the type 0000H --> FFFFH occurs, the
setting value for counting is reloaded so that counting can continue. An underflow can trigger an
interrupt request, which may be used for providing an interval timer. A toggled waveform, which
reverses itself at every underflow, is output from the TOT0/1 pin. Table 11.1-2 "Interval time of
16-bit reload timer" lists the interval time for the 16-bit reload timer.
Table 11.1-2 Interval time of 16-bit reload timer
Count clock
Internal clock
External clock
Count clock interval
Interval time
21/Φ (0.125 µs)
0.125 µs to 8.192 ms
23/Φ (0.5 µs)
0.5 µs to 32.768 ms
25/Φ (2.0 µs)
2.0 µs to 131.1 ms
23/Φ or more (0.5 µs)
0.5 µs or more
Φ: Machine clock frequency ( ) indicates the value for 16-MHz machine clock operation.
❍ One-shot mode
If countdown leads to an underflow (0000H --> FFFFH), count operation will stop. Underflow may
also trigger an interrupt. During counter operation, the square wave that indicates counting is
output from the TOT0 and TOT1 pins.
References:
•
The 16-bit reload timer is used to generate the UART baud rate.
•
The 16-bit reload timer is used to trigger A/D converter operation.
253
CHAPTER 11 16-BIT RELOAD TIMER
■ Interrupts and use of EI2OS from 16-bit reload timer
Table 11.1-3 "Interrupts and use of EI2OS from 16-bit reload timer" lists the interrupts and
EI2OS from the16-bit reload timer.
Table 11.1-3 Interrupts and use of EI2OS from 16-bit reload timer
Channel
Interrupt
number
Interrupt control
register
Vector table address
EI2OS
Register
name
Address
Lower
bits
Upper
bits
Bank
16-Bit Reload
Timer 0
#17(11H)
ICR03
0000B3H
FFFFB8H
FFFFB9H
FFFFBAH
*
16-Bit Reload
Timer 1
#28(1CH)
ICR08
0000B8H
FFFF8CH
FFFF8DH
FFFF8EH
*
*: Available when not using interrupt sources sharing ICR03, ICR08, and the interrupt vector.
254
11.2 Configuration of 16-Bit Reload Timer
11.2 Configuration of 16-Bit Reload Timer
The 16-bit reload timer consists of the following seven blocks:
• Count clock generation circuit
• Reload control circuit
• Output control circuit
• Operation control circuit
• 16-bit timer registers (TMR0/1L, TMR0/1H)
• 16-bit reload registers (TMRLR0/1L, TMRLR0/1H)
• Timer control status registers (TMCSR0/1L, TMCSR0/1H)
■ Block Diagram of 16-Bit Reload Timer
Figure 11.2-1 "Block diagram of 16-bit reload timer" shows a block diagram of the 16-bit reload
timer.
Figure 11.2-1 Block diagram of 16-bit reload timer
Internal data bus
TMRLR0*1
<TMRLR1>
16-bit reload register
Reload signal
TMR0*1
<TMR1>
16-bit timer register (down-counter)
Reload
control
circuit
UF
CLK
Count clock generation circuit
Machine
clock
Prescaler
Gate
input
3
Clock
judgement
circuit
Wait signal
to UART0/1*1
<to A/D converter>
CLK
Input
control
circuit
Pin
P12/TIN0*1
<P07/TIN1>
Output control circuit
Internal
clock
Clock
selector
Clear
2
Output signal
generation
circuit
Pin
P11/TOT0*1
< P06/TOT1 >
EN
External clock
3
Reversed
Select
signal
Function select
Operation
control
circuit
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
Timer control status register (TMCSR0) *1
<TMCSR1 >
*1: Used for channel 0/1. <> indicates channel 1.
*2: Interrupt number
Interrupt request signal
#17 (11H)*2
< #28 (1CH) >
255
CHAPTER 11 16-BIT RELOAD TIMER
❍ Count clock generation circuit
The count clock generation circuit generates the count clock for the 16-bit reload timer from the
machine clock or external input clock.
❍ Reload control circuit
Controls reload operation when the timer starts and when underflow occurs.
❍ Output control circuit
Controls the reversal of TOT pin output due to 16-bit timer register underflow and the enable or
disable states of TOT pin output.
Operation control circuit
Controls starting and stopping of the16-bit reload timer.
16-bit timer registers (TMR0/1L, TMR0/1H)
These registers are used to read the current counter value for the 16-bit down counter.
16-bit reload registers (TMRLR0/1L, TMRLR0/1H)
These registers are used to set the interval time of the 16-bit reload timer, which is loaded
into the 16-bit timer registers for countdown.
Timer control status registers (TMCSR0/1L, TMCSR0/1H)
These registers are used to select the count clock and operation mode of the 16-bit reload
timer, set operating conditions, activating a trigger by software, enabling/disabling count
operation, select reload or one-shot mode, select the pin output level, enable or disable timer
output, control interrupts, and check the state of operation.
256
11.3 Pins of 16-Bit Reload Timer
11.3 Pins of 16-Bit Reload Timer
This section describes the pins of the 16-bit reload timer, and shows its block diagram.
■ Pins of 16-Bit Reload Timer
The pins of the 16-bit reload timer can also be used for general-purpose ports. Table 11.3-1
"Pins of the 16-bit reload timer" lists the pin functions, type of I/O, and settings for using the 16bit reload timer.
Table 11.3-1 Pins of the 16-bit reload timer
Pin name
Pin function
Type of I/O
Pull-up
selection
Standby
control
Setting to use pin
P12/TIN0/
IN3
I/O and timer
input of port 1
Set to input port.
(DDR1:bit2=0)
P11/TOT0/
WOT
I/O and timer
input of port 1
Setting to timer output enabled
(TMCSR0L:OUTE=1)
Sound generator output
disabled
P07/PPG1/
TIN1
I/O and timer
output of port 0
P06/PPG0/
TOT1
I/O and timer
output of port 0
CMOS
output and
CMOS
hysteresis
input
Not used
Used
Set to input port
(DDR0:bit7=0)
PPG1 output disabled
Setting to timer output enabled
(TMCSR1L:OUTE=1)
PPG0 output disabled
257
CHAPTER 11 16-BIT RELOAD TIMER
■ Block diagram of 16-bit reload timer pins
Figure 11.3-1 "Block diagram of 16-bit reload timer pins" shows a block diagram of the pins of
the 16-bit reload timer.
Figure 11.3-1 Block diagram of 16-bit reload timer pins
Peripheral function input*1
Peripheral function output*1
Internal data bus
PDR (Port data register)
Peripheral function output
enabled*1
PDR read
Pch
Output latch
PDR write
Pin
DDR (Port direction register)
Nch
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Standby control: stop, watch mode and SPL=1
*1: Peripheral function I/O is only applicable to pins for a peripheral function.
258
11.4 Registers of 16-Bit Reload Timer
11.4 Registers of 16-Bit Reload Timer
This section lists the registers of the 16-bit reload timer.
■ List of Registers of 16-Bit Reload Timer
Figure 11.4-1 "Registers of 16-bit reload timer" lists the registers of the 16-bit reload timer.
Figure 11.4-1 Registers of 16-bit reload timer
Address
bit8
bit7
000051
50 H
TMCSR0 (Timer control status register)
000053
52 H
TMR0 TMRLR0 (16-bit timer register/16-bit reload register)
000055
54 H
TMCSR1 (Timer control status register)
000057
56 H
TMR1 TMRLR1 (16-bit timer register/16-bit reload register)
16-Bit Reload Timer 0
16-Bit Reload Timer 1
bit15
bit0
1
1
*1: Functions as a 16-bit timer register (TMR) for reading and as a 16-bit reload register (TMRLR) for writing.
259
CHAPTER 11 16-BIT RELOAD TIMER
11.4.1 Upper Bits of Timer Control Status Registers
(TMCSR0/1H)
Upper bits 11-8 and lower bit 7 in the timer control status registers (TMCSR0/1) are
used to select the 16-bit reload timer operation mode and set the operating conditions.
Use of the last lower bit 7 (MOD0 bit) is also described here.
■ Upper Bits and Bit 7 of Timer Control Status Registers (TMCSR0/1H)
Figure 11.4-2 Upper bits and bit 7 of timer control status registers (TMCSR0/1H)
Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6
bit0
Initial value
TMCSR0
(TMCSR:
L)
----00000B
CSL1 CSL0 MOD2 MOD1 MOD0
000051 H
TMCSR1
-
-
-
-
R/W R/W R/W R/W R/W
000055 H
MOD2 MOD1 MOD0
0
0
0
0
0
1
0
1
0
0
1
1
1
X
0
1
X
1
Input pin function
Trigger prohibited
0
0
X
0
1
X
1
0
X
1
1
CSL1 CSL0
Valid edge, level
Leading edge
Trailing edge
Both edges
L level
H level
Trigger input
Gate input
MOD2 MOD1 MOD0
X
Operation mode selection bit
(in internal clock mode)
Operation mode selection bit
(in event count mode)
Input pin function
Valid edge
Leading edge
Trailing edge
Both edges
Trigger input
Count clock selection bit
Function
Count clock
0
0
21/ (0.125 s)
0
1
23/
1
0
1
1
Internal clock mode
(0.5 s)
25/ (2.0 s)
Event count mode
External event input
R/W : Reading and writing permitted
: Undefined
x : Unspecified value
: Initial value
: Machine clock, ( )indicates the value for 16-MHz machine clock operation.
260
11.4 Registers of 16-Bit Reload Timer
Table 11.4-1 Function of the upper bits and bit 7 of timer control status registers: (TMCSR0, TMCSR1:
H)
Bit name
bit15
bit14
bit13
bit12
Bit undefined
bit11
bit10
CSL1, CSL0:
Count clock
selection bit
bit9
bit8
bit7
MOD2, MOD1,
MOD0:
Operation mode
selection bit
Function
•
•
Value at reading is not specified.
Writing does not affect operation.
•
•
Selects the count clock.
Internal clock mode to count the internal clock is selected if these
bits are other than 11B.
When these bits are set to 11B, event count mode is set to count
the external clock edges.
•
Internal clock mode
• The MOD2 bit is used to select the function of the input pin.
• When the MOD2 bit is set to "0", the input pin is used as a trigger
input pin. When a valid edge is input, reload register data is loaded
into the counter to continue with count operation. Valid edge types
are selected by using the MOD1/0 bits.
• With the MOD2 bit set to "1", the input pin is used for gate input for
counting only when a valid level is being input. The MOD0 bit
enables selection of a valid level.
• Because the value of the MOD1 bit has no effect on operation,
either value (0 or 1) can be set.
Event Count mode
• Because the value of the MOD2 bit has no effect on operation,
either value (0 or 1) can be set.
• The input pin is used as a trigger input pin for event input. A valid
edge is selected by using the MOD1/0 bits.
261
CHAPTER 11 16-BIT RELOAD TIMER
11.4.2 Lower Bits of Timer Control Status Registers
(TMCSR0/1L)
Bit 7 of the timer control status registers (TMCSR0/1), which is part of the lower bits, is
used to set the operating conditions of the 16-bit reload timer, enable or disable
operation, control interrupts, and check the state of operation.
■ Lower Bits of Timer Control Status Registers (TMCSR0/1L)
Figure 11.4-3 Lower bits of timer control status registers (TMCSR0/1L)
*1
Address
bit15
TMCSR0
000050H
bit8
(TMCSR:H)
TMCSR1
bit7
bit6
bit5
bit4
bit3
MOD0 OUTE OUTL RELD INTE
R/W
R/W
R/W
R/W
R/W
bit0
Initial value
CNTE TRG
00000000
bit2
UF
bit1
R/W
R/W
B
R/W
000054H
TRG
0
1
CNTE
0
1
UF
0
1
INTE
0
1
RELD
0
1
Software trigger bit
Does not change and has no effect
Starts counting after reload
Count enable bit
Count stop
Count enabled (waiting for start trigger)
Underflow flag bit for interrupt request
Reading
Writing
No counter underflow
Bit cleared
Counter underflow generated
Does not change and has
no effect
Enable bit for interrupt requests
Interrupt request output disabled
Interrupt request output enabled
Reload selection bit
One-shot mode
Reload mode
Selection bit for pin output level
OUTL
0
1
OUTE
One-shot mode
(RELD=0)
Reload mode
(RELD=1)
Rectangle wave at H level
during counting
Rectangle wave at L level
during counting
Toggle output at L level when
counting starts
Toggle output at H level when
counting starts
Timer output enable bit
Register and pin for each channel
Pin function
TMCSR0
R/W : Reading and writing permitted
: Initial value
0
General-purpose
port
1
Timer output
TMCSR1
P11
P06
TOT0
TOT1
*1 : For details about the M0D0 (bit 7), see Section 11.4.1, "Upper Bits of Timer Control Status Registers (TMCSR0,
TMCSR1: H)."
262
11.4 Registers of 16-Bit Reload Timer
Table 11.4-2 Function of the lower bits of the timer control status registers (TMCSR0/1L)
Bit name
bit6
OUTE:
Timer output enable
bit
Function
•
•
•
Enables or disables output via the timer output pin.
When this bit is "0", the pin is used as a general-purpose port;
when this bit is "1", the pin is used as a timer output pin.
The waveform output from the timer output pin becomes toggle
output in reload mode. In one-shot mode, a rectangular wave is
output, which indicates that counting is in progress.
bit5
OUTL:
Selection bit for pin
output level
•
•
A register used to select the output level of the timer output pin.
Toggle this bit to "0" or "1" to reverse the pin level.
bit4
RELD:
Reload selection bit
•
•
Enables reload operation.
Reload mode is entered when this bit is set to "1". If underflow
occurs, reload register data is loaded into the counter to continue
count operation.
One-Shot mode is entered when this bit is se to "0". If underflow
occurs, count operation will stop.
•
bit3
INTE:
Enable bit for
interrupt requests
•
•
Enables or disables interrupt requests to the CPU.
When this bit and the flag bit for interrupt request (UF) are set to
"1", an interrupt request is output.
bit2
UF:
Underflow flag bit for
interrupt request
•
•
•
Set to "1" if counter underflow occurs.
Cleared by writing "0". Writing "1" has no effect.
Also cleared at EI2OS startup.
bit1
CNTE:
Count enable bit
•
•
Enables or disables count operation.
When this bit is set to "1", start trigger wait state is entered. As
soon as the start trigger occurs, the actual counting will begin.
bit0
TRG:
Software trigger bit
•
Used to start the interval timer function or counter function by
software.
Set this bit to "1" to activate the software trigger and load the
reload register value into the counter to start counting. Writing "0"
has no effect.
When CNTE=1, trigger input is always enabled by this but
regardless of the mode.
•
•
263
CHAPTER 11 16-BIT RELOAD TIMER
11.4.3 16-Bit Timer Registers (TMR0/1)
The 16-bit timer registers (TMR0/1) are used to continuously read the current count
value of the 16-bit down counter.
■ 16-Bit Timer Registers (TMR0/1)
Figure 11.4-4 "Bit configuration of 16-bit timer registers (TMR0/1)" shows the bit configuration of
the 16-bit timer registers (TMR0/1).
Figure 11.4-4 Bit configuration of 16-bit timer registers (TMR0/1)
Address
TMR0:
TMR1:
000053 H
000057 H
D15 D14
R
Address
TMR0:
TMR1:
000052 H
000056 H
bit8
Initial value
D9
D8
XXXXXXXX B
R
R
bit15 bit14 bit13 bit12 bit11 bit10 bit9
D13
R
D12 D11 D10
R
R
R
R
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R
R
R
R
R
R
R
R
R: Read only
X: Not specified
These registers are used to read the current counter value of the 16-bit down counter. When
counter operation is allowed (TMCSR0/1: CNTE=1) to start counting, the value written to the 16bit reload register is loaded into these registers to start the countdown. In counter stop mode
(CNTE=0 for TMCSR0/1), the register value is retained.
Notes:
264
•
These registers may be read in counter operation mode by using a word transfer instruction
(e.g. MOVW A,003AH).
•
This register requires access in units of words.
•
The 16-Bit Timer Registers (TMR0/1) are read-only registers, and assigned the same
address as the 16-bit write-only reload registers (TMRLR0/1L,TMRLR0/1H). Therefore,
writing does not affect TMR values, though writing is performed to TMRLR0/1L and
TMRLR0/1H.
11.4 Registers of 16-Bit Reload Timer
11.4.4 16-Bit Reload Registers (TMRLR0/1L, TMRLR0/1H)
The 16-bit reload registers (TMRLR0/1L, TMRLR0/1H) are used to set the 16-bit down
counter to a reload value. The value written to these registers is loaded into the down
counter for countdown.
■ 16-Bit Reload Registers (TMRLR0/1L, TMRLR0/1H)
Figure 11.4-5 "Bit configuration of 16-bit reload registers (TMRLR0/1L, TMRLR0/1H)" shows the
bit configuration of the 16-bit reload registers (TMRLR0/1L,TMRLR0/1H).
Figure 11.4-5 Bit configuration of 16-bit reload registers (TMRLR0/1L, TMRLR0/1H)
Address
TMRLR0H: 000053 H
TMRLR1H: 000057 H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
D15 D14
W
Address
TMRLR0L: 000052 H
TMRLR1L: 000056 H
D13
W
D12 D11 D10
W
W
W
W
bit8
D9
D8
W
W
Initial value
XXXXXXXX B
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
W
W
W
W
W
W
W
W
W: Write-only
X: Not specified
Regardless of the 16-bit reload timer operation mode, if counter operation is prohibited
(TMCSR0/1: CNTE=0), these registers are set to the initial value of the counter. When counter
operation is allowed (TMCSR0/1: CNTE=1) to start the counter, the countdown starts from the
value written to these registers.
The value set in the 16-bit reload registers (TMRLR0/1L, TMRLR0/1H) is reloaded into the
counter in reload mode if underflow occurs, then the countdown continues. In one-shot mode,
the counter stops at FFFFH if underflow occurs.
Notes:
•
Writing to the registers is always performed in counter stop mode (TMCSR0/1: CNTE=0).
Write operations always use a word transfer instruction (e.g. MOVW 003AH,A).
•
This register requires access in units of words.
•
The 16-bit reload registers (TMRLR0/1L, TMRLR0/1H) are functionally write-only registers
that are allocated under the same address as the read-only 16-bit timer registers (TMR0/1).
Therefore, the value read is the value of TMR0/1. Consequently, an instruction such as INC/
DEC for read-modify-write (RMW) operation cannot be used.
265
CHAPTER 11 16-BIT RELOAD TIMER
11.5 Interrupts of 16-Bit Reload Timer
The16-bit reload timer may generate an interrupt due to counter underflow. The timer
also supports the extended intelligent I/O service (EI2OS).
■ Interrupts Generated by 16-Bit Reload Timer
Table 11.5-1 "Interrupt control bits and interrupt sources of 16-bit reload timer" lists the interrupt
control bits and interrupt sources of the 16-bit reload timer.
Table 11.5-1 Interrupt control bits and interrupt sources of 16-bit reload timer
16-bit reload timer
Flag bit for interrupt requests
TMCSR0/1:UF
Enable bit for interrupt requests
TMCSR0/1:INTE
Interrupt source
Underflow of 16-bit down counter (TMR0/1)
Down counter underflow (0000H --> FFFFH) of the 16-bit reload timer will set the UF bit in the
timer control status registers (TMCSR0/1L, TMCSR0/1H) to "1". When interrupt requests are
enabled (TMCSR0/1: INTE=1), an interrupt request is output to the interrupt controller.
■ Interrupts of 16-Bit Reload Timer and EI2OS
Table 11.5-2 "Interrupts of 16-bit reload timer and EI2OS" lists the interrupts of the 16-bit reload
timer and their relationship to EI2OS.
Table 11.5-2 Interrupts of 16-bit reload timer and EI2OS
Channel
Interrupt
number
Interrupt control
register
Register
name
Vector table address
EI2OS
Address
Lower
bits
Upper
bits
Bank
16-Bit Reload
Timer 0
#17(11H)
ICR03
0000B3H
FFFFB8H
FFFFB9H
FFFFBAH
*
16-Bit Reload
Timer 1
#28(1CH)
ICR08
0000B8H
FFFF8CH
FFFF8DH
FFFF8EH
*
*: Available when not using interrupt sources sharing ICR03, ICR08, and the interrupt vector.
■ EI2OS Function of 16-Bit Reload Timer
The 16-bit reload timer has a circuit supporting EI2OS. Therefore, a counter underflow will start
EI2OS. Note that EI2OS is only available when no other peripheral function that shares the
interrupt control register (ICR) uses an interrupt. The 16-bit reload timer 0 uses EI2OS. DTP/
external interrupt circuit interrupts must be disabled. The 16-bit reload timer 1 uses EI2OS. PPG
timer interrupts must be disabled.
266
11.6 Operation of 16-Bit Reload Timer
11.6 Operation of 16-Bit Reload Timer
This section describes how to set the 16-Bit Reload Timer and counter operation state.
■ 16-Bit Reload Timer Settings
❍ Setting internal clock mode
To operate the interval timer, the settings listed in Figure 11.6-1 "Internal clock mode settings"
are required.
Figure 11.6-1 Internal clock mode settings
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
CSL1 CSL0 MOD2 MOD1 MOD0 OUTEOUTL RELD INTE UF CNTE TRG
TMCSR
1
Other than "11"
TMRLR
Setting of the initial counter value (reload value)
: Bit used
1 : Set to 1.
❍ Setting event count mode
To operate the event counter, the settings listed in Figure 11.6-2 "Event count mode settings"
are required.
Figure 11.6-2 Event count mode settings
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8
TMCSR
bit4 bit3 bit2
bit1 bit0
CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG
1
TMRLR
bit7 bit6 bit5
1
1
Setting of the initial counter value (reload value)
DDR1
DDR0
: Bit used
1 : Set to 1.
: Set the bit corresponding to the pin used to "0".
267
CHAPTER 11 16-BIT RELOAD TIMER
■ States of Counter Operation
The counter’s operation state is determined by the CNTE bit of the timer control status registers
(TMCSR0/1L,TMCSR0/1H) and the internal WAIT signal. States that can be set include the stop
state (STOP state), start trigger wait state (WAIT state), and operation state (RUN state). Figure
11.6-3 "State transition diagram of counter states" shows a state transition diagram for the
counter.
Figure 11.6-3 State transition diagram of counter states
STOP state CNTE=0, WAIT=1
TIN pin: Input disabled
TO pin: General-purpose port
Counter: Retains the value at stop.
Not specified immediately
after reset
Reset
CNTE=0
CNTE=0
CNTE=1
TRG=0
WAIT state CNTE=1, WAIT=1
TIN pin: Valid for trigger input only
TO pin: Initial value output
Counter: Retains the value at stop.
Not specified until loading
after reset
TRG=1
(Software trigger)
External trigger from TIN
CNTE=1
TRG=1
UF=1 &
RELD=0
(One-shot mode)
RUN state CNTE=1, WAIT=0
TIN pin: Functions as TIN pin.
TO pin: Functions as TO pin.
Counter: operating
UF=1 &
RELD=1
TRG=1
(Reload mode)
(Software trigger)
LOAD
CNTE=1, WAIT=0
Loads the reload register value into
Load end
the counter.
: State transition by hardware
: State transition by register access
WAIT : WAIT signal (internal signal)
TRG : Software trigger bit of timer control status register (TMCSR)
CNTE : Count enable bit of timer control status register (TMCSR)
: Underflow flag bit for interrupt request of timer control status register (TMCSR)
UF
RELD : Reload selection bit of timer control status register (TMCSR)
268
11.6 Operation of 16-Bit Reload Timer
11.6.1 Internal Clock Mode (Reload Mode)
The counter operates in sync with the internal count clock to count down the 16-bit
counter and generate an interrupt request in case of counter underflow. The counter
also outputs a toggle waveform from the timer output pin.
■ Operation in Internal Clock Mode (Reload mode)
When count operation is allowed (TMCSR0/1: CNTE=1) and the timer is started by the software
trigger bit (TMCSR: TRG) or external trigger, counter operation will start by loading the data of
the 16-bit reload registers (TMRLR0/1L, TMRLR0/1H) into the counter. When both the count
enable bit and software trigger bit are set to "1", counting will begin as soon as the counter is
enabled.
If the counter value causes an underflow (0000H --> FFFFH), the value of the16-bit reload
registers (TMRLR0/1L, TMRLR0/1H) is loaded into the counter to continue counting. Note that if
the underflow flag bit for interrupt request (UF) and enable bit for interrupt request (INTE) are
set to "1", an interrupt request is generated.
The TOT pin outputs a toggle waveform that is reversed at every underflow.
❍ Software trigger operation
When the TRG bit of the timer control status registers (TMCSR0/1L, TMCSR0/1H) is set to "1",
the counter starts operation. Figure 11.6-4 "Count operation (software trigger operation) in
reload mode" shows the software trigger operation in reload mode.
Figure 11.6-4 Count operation (software trigger operation) in reload mode
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
T : Machine cycle
*1 : It takes 1T from trigger input to loading reload data.
269
CHAPTER 11 16-BIT RELOAD TIMER
❍ External trigger operation
When a valid edge (leading, trailing, or both can be selected) is input to the TIN pin, the counter
will start operation. Figure 11.6-5 "Count operation in reload mode (external trigger operation)"
shows the external trigger operation in reload mode.
Figure 11.6-5 Count operation in reload mode (external trigger operation)
Count clock
Counter
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TIN pin
2T to 2.5T
TO pin
T: Machine cycle
*1: It takes 2T to 2.5T from trigger input to loading reload data.
Note:
The pulse width of trigger pulses input to the TIN pin must be 2/Φ or more.
❍ Gate input operation
As soon as a valid level ("H" level or "L" level can be selected) is input to the TIN pin, the
counter will start operation. Figure 11.6-6 "Count operation in reload mode (software trigger,
gate input operation)" shows the gate input operation in reload mode.
Figure 11.6-6 Count operation in reload mode (software trigger, gate input operation)
Count clock
Counter
Reload data
-1
-1
-1
0000H
Reload
data
-1
-1
Data load signal
UF bit
CNTE bit
TRG bit
TIN pin
TO pin
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
The pulse width of pulses input to TIN0/1 must be 2/Φ or more.
270
11.6 Operation of 16-Bit Reload Timer
11.6.2 Internal Clock Mode (One-Shot Mode)
The counter is in synchronization with the internal count clock in this mode to count
down the 16-bit counter and generate an interrupt request to the CPU at counter
underflow. It also outputs a square wave from the TOT0/1 pin to indicate that counting
is in progress.
■ Operation of Internal Clock mode (One-Shot Mode)
When count operation is allowed (TMCSR0/1: CNTE=1) and the timer is started by the software
trigger bit (TMCSR0/1: TRG) or external trigger, count operation will start. When both the count
enable bit and software trigger bit are set to "1", counting will start at the same time counting
becomes enabled. If the counter value causes an underflow (0000H --> FFFFH), the counter
stops at FFFFH, and the underflow flag bit for interrupt requests (UF) is set to "1". If the enable
bit for interrupt request (INTE) is set to "1", an interrupt request is generated.
The TOT pin outputs a square wave to indicate that counting is in progress.
❍ Software trigger operation
The counter will start as soon as the TRG bit of the timer control status registers (TMCSR0/
1L,TMCSR0/1H) is set to "1". Figure 11.6-7 "Count operation in one-shot mode (software trigger
operation)" shows the software trigger operation in one-shot mode.
Figure 11.6-7 Count operation in one-shot mode (software trigger operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
-1
Reload
data
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Waiting for start trigger input
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
271
CHAPTER 11 16-BIT RELOAD TIMER
❍ External trigger operation
When a valid edge (leading, trailing, or both can be selected) is input to the TIN0/1 pins, the
counter will start operation. Figure 11.6-8 "Count operation in one-shot mode (external trigger
operation)" shows the external trigger operation in one-shot mode.
Figure 11.6-8 Count operation in one-shot mode (external trigger operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TIN bit
2T to 2.5T
TO pin
Waiting for start trigger input
T: Machine cycle
*1: It takes 2T to 2.5T from trigger input to loading reload data.
Note:
The pulse width of trigger pulses input to the TIN pin must be 2/Φ or more.
❍ Gate input operation
When a valid level ("H" and "L" level can be selected) is input to the TIN pin, the counter starts
operation. Figure 11.6-9 "Count operation in one-shot mode (software trigger, gate input
operation)" shows the gate input operation in one-shot mode.
Figure 11.6-9 Count operation in one-shot mode (software trigger, gate input operation)
Count clock
Counter
Reload
data
-1
0000H FFFFH
Reload
data
-1
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
TO pin
Waiting for start trigger input
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
The pulse width for gate input to the TIN pin must be 2/Φ or more.
272
11.6 Operation of 16-Bit Reload Timer
11.6.3 Event Count Mode
In this mode, the counter counts input edges from the TIN pin to count down the 16-bit
counter and generate an interrupt request to the CPU when a counter underflow
occurs. The TOT0/1 pin can output either a toggle waveform or a square wave.
■ Event Count mode
When count operation is allowed (TMCSR0/1: CNTE=1) to start the counter (TMCSR0/1:
TRG=1), data from the 16-bit reload registers (TMRLR0/1L, TMRLR0/1H) is loaded into the
counter for a countdown whenever a valid edge (leading or trailing can be selected) of pulses
(external count clock) input to the TIN0/1 pin is detected. When both the count enable bit and
software trigger bit are set to "1", counting will start as soon as counting becomes enabled.
Operation in reload mode
If the counter value has an underflow (0000H --> FFFFH), data from the 16-bit reload registers
(TMRLR0/1L, TMRLR0/1H) is loaded into the counter to continue counting. In this case, an
interrupt request is issued when the underflow flag bit for interrupt requests (UF) and enable bit
for interrupt requests (TMCSR0/1: INTE) are both set to "1". The TOT0/1 pin outputs a toggle
waveform, which is reversed at every occurrence of underflow. Figure 11.6-10 "Count operation
in reload mode (event count mode)" shows the counting operation in reload mode.
Figure 11.6-10 Count operation in reload mode (event count mode)
TIN pin
Reload
data
Counter
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
0000H
Reload
data
-1
Data load signal
UF bit
CNTE bit
TRG bit
*1
T
TO pin
T: Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width of clock input to ITN0/1 must be 4/Φ or more.
273
CHAPTER 11 16-BIT RELOAD TIMER
❍ Operation in one-shot mode
If the counter value causes an underflow (0000H --> FFFFH), the counter stops at FFFFH. In this
case, the underflow request flag bit (UF) is set to "1". If the interrupt request output enable bit
(INTE) is also set to "1", an interrupt request is generated. The TOT0/1 pin outputs a square
wave that indicates counting in progress. Figure 11.6-11 "Counter operation in one-shot mode
(event count mode)" shows the counter operation in one-shot mode.
Figure 11.6-11 Counter operation in one-shot mode (event count mode)
TIN pin
Reload
data
Counter
-1
0000H FFFFH
-1
Reload
data
0000H FFFFH
Data load signal
UF bit
CNTE bit
TRG bit
{1
T
TO pin
Waiting for start trigger input
T : Machine cycle
*1: It takes 1T from trigger input to loading reload data.
Note:
Both the "H" width and "L" width for the input clock to TIN0/1 must be 4/Φ or more.
274
11.7 Notes on Using the 16-Bit Reload Timer
11.7 Notes on Using the 16-Bit Reload Timer
This section provides notes on using the 16-bit reload timer.
■ Notes on using the 16-bit reload timer
❍ Notes on setup by program
Writing to the 16-bit reload registers (TMRLR0/1L, TMRLR0/1H) must be performed in counter
operation stop (TMCSR0/1: CNTE=0) mode. Reading of the 16-bit timer registers (TMR0/1) may
be performed while the counter is in operation, but a word transfer instruction (e.g., MOVW A,
dir) must be used in this case.
The contents of the CSL1/CSL0 bits of the timer control status registers (TMCSR0/1L,
TMCSR0/1H) can only be changed in counter operation stop mode (TMCSR0/1: CNTE=0).
Notes on interrupts
If the UF bit of the timer control status registers (TMCSR0/1L, TMCSR0/1H) is set to "1" in
interrupt enabled state (TMCSR0/1:INTE=1), return from interrupt handling cannot be
performed. Ensure that the UF bit is always cleared.
Since the 16-bit reload timer and watch timer share the same interrupt vector, interrupt sources
must be checked in the interrupt-handling routine to enable using interrupts.
If the 16-Bit Reload Timer uses EI2OS, the watch timer must disable the use of interrupts during
that time.
275
CHAPTER 11 16-BIT RELOAD TIMER
11.8 Sample Programs for the 16-Bit Reload Timer
The sample programs listed below uses the 16-bit reload timer in internal clock mode
and event count mode.
■ Sample Program for Internal Clock Mode
Process specifications
Uses the 16-bit reload timer to generate a 25 ms interval timer interrupt.
Uses reload mode to generate interrupts repeatedly.
Uses no external trigger input, but uses a software trigger to start the timer.
Does not use EI2OS.
Uses a 16-MHz machine clock with a count clock of 2 µs.
[Coding example]
ICR03 EQU
0000B3H
;Interrupt Control Register 03
TMCSR EQU
000050H
;Timer control status register
TMR
EQU
000052H
;16-bit timer register
TMRLR EQU
000052H
;16-bit reload register
UF
EQU
TMCSR:2
;Flag bit for interrupt requests
CNTE
EQU
TMCSR:1
;Counter operation enable bit
TRG
EQU
TMCSR:0
;Software trigger bit
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer (SP) already
;initialized
AND
CCR, #0BFH
;Interrupt disabled
MOV
I:ICR03, #00H
;Interrupt level 0 (highest)
CLRB
I:CNTE
;Counter temporary stopped
MOVW
I:TMRLR, #30D4H ;Setting the data for the 25-ms timer
MOVW
I:TMCSR, #00001000000011011B
;Interval timer operation, clock 2ms
;External trigger disabled, external
;output disabled
;Reload mode selection, enabling interrupts
MOV
ILM, #07H
;ILM in PS set to level 7
OR
CCR, #40H
;Interrupts enabled
;Interrupt flag clear, counter start
LOOP: MOV
A, #00H
;Infinite loop
MOV
A, #01H
;
BRA
LOOP
;
;----------Interrupt program------------------------------------------------WARI:
CLRB
I:UF
;Interrupt request flag cleared
;
:
;
User processing;
:
RETI
;Return from interrupt
CODE
ENDS
276
11.8 Sample Programs for the 16-Bit Reload Timer
;----------Vector settings--------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFB8H
;Set the vector to interrupt #17 (11H)
DSL
WARI
ORG
0FFDCH
;Reset the vector setting
DSL
START
DB
00H
;Set Single-Chip mode
VECT
ENDS
END
START
277
CHAPTER 11 16-BIT RELOAD TIMER
■ Sample Program for Event Count Mode
Specification of processing
The 10,000th time the 16-bit reload timer/counter counts a leading edge in the pulses input to
the external event input pin, an interrupt is generated.
The device operates in one-shot mode.
In case of external trigger input, the leading edge is selected.
This program does not use EI2OS.
[Coding example]
ICR03
;Interrupt control register for 16-bit
;reload timer
TMCSR EQU
000050H
;Timer control status register
TMR
EQU
000052H
;16-bit timer register
TMRLR EQU
000052H
;16-bit reload register
DDR1
EQU
000011H
;Port data register
UF
EQU
TMCSR:2
;Flag bit for interrupt request
CNTE
EQU
TMCSR:1
;Counter operation enable bit
TRG
EQU
TMCSR:0
;Software trigger bit
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;
:
;Stack pointer (SP) already initialized
AND
CCR, #0BFH
;Interrupt disabled
MOV
I:ICR09, #00H
;Interrupt level 0 (highest)
MOV
I:DDR1, #00H
;P12/TIN0 pin set to input
CLRB
I:CNTE
;Counter temporarily stopped
MOVW
I:TMRLR, #2710H ;Reload value set to 10000
MOVW
I:TMCSR, #0000110010001011B
;Counter operation, external trigger,
;leading edge, External output disabled
;Selection of one-shot mode,
;interrupts enabled, Interrupt flag cleared,
;counter start
MOV
ILM, #07H
;ILM in PS set to level 7
OR
CCR, #40H
;Interrupts enabled
LOOP: MOV
A, #00H
;Infinite loop
MOV
A, #01H
;
BRA
LOOP
;
278
EQU
0000B3H
11.8 Sample Programs for the 16-Bit Reload Timer
;----------Interrupt program------------------------------------------------WARI:
CLRB
I:UF
;Interrupt request flag cleared
;
:
;
User processing
;
:
RETI
;Return from interrupt
CODE
ENDS
;----------Vector settings--------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FF84H
;Set the vector to interrupt #30 (1EH)
DSL
WARI
ORG
0FFDCH
;Reset vector settings
DSL
START
DB
00H
;Set Single-Chip mode
VECT
ENDS
END
START
279
CHAPTER 11 16-BIT RELOAD TIMER
280
CHAPTER 12
REAL-TIME WATCH TIMER
This chapter describes the functions and operations of the real-time watch timer.
12.1 "Overview of Real-Time Watch Timer"
12.2 "Registers of Real-Time Watch Timer"
281
CHAPTER 12 REAL-TIME WATCH TIMER
12.1 Overview of Real-Time Watch Timer
The real-time watch timer consists of the real-time watch timer control register, subsecond data register, second/minute/hour data registers, 1/2 clock divider, 21-bit
prescaler, and second/minute/hour counters. An MCU oscillation frequency of 4 MHz is
used to operate the real-time watch timer specified. The real-time watch timer operates
as a real-world timer, providing information on real-world time.
■ Block Diagram of Real-Time Watch Timer
Figure 12.1-1 "Block diagram of real-time watch timer" shows a block diagram of the real-time
watch timer.
Figure 12.1-1 Block diagram of real-time watch timer
Oscillation clock
OE
21-bit prescaler
1/2 clock
divider
OE
WOT
CO
EN
Sub-second
register
UPDT
ST
Second counter
CI
EN
LOAD
Minute counter
CO
Hour counter
CO
6 bits
6 bits
CO
5 bits
Second/minute/hour register
INTE0 INT0
INTE1 INT1
INTE2 INT2
INTE3 INT3
IRQ #30
282
12.2 Registers of Real-Time Watch Timer
12.2 Registers of Real-Time Watch Timer
The five types of registers of the real-time watch timer are as follows:
• Real-time watch timer control register (WTCR)
• Sub-second data register (WTBR)
• Second data register (WTSR)
• Minute data register (WTMR)
• Time data register (WTHR)
■ List of registers of Real-Time Watch Timer
Figure 12.2-1 "Registers of real-time watch timer" lists the registers of the real-time watch timer.
Figure 12.2-1 Registers of real-time watch timer
Real-time watch timer
Upper bits of control register
Address : 000059 H
Reading/writing =>
Initial value =>
Real-time watch timer
Lower bits of control register
Address : 000058 H
Reading/writing =>
Initial value =>
Sub-second data register
Address : 00395C H
Reading/writing =>
=>
Sub-second data register
Address : 00395B H
Reading/writing =>
Initial value =>
Sub-second data register
Address : 00395A H
Reading/writing =>
Initial value =>
Second data register
Address : 00395D H
Reading/writing =>
Initial value =>
Minute data register
Address : 00395E H
Reading/writing =>
Initial value =>
Hour data register
Address : 00395FH
Reading/writing =>
Initial value =>
15
14
13
12
11
10
9
8
<= Bit number
INTE3
INT3
INTE2
INT2
INTE1
INT1
INTE0
INT0
WTCRH
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
TST2
6
TST1
5
TST0
4
-
3
-
2
UPDT
1
OE
0
ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
-
-
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
-
6
-
5
-
4
D20
3
D19
2
D18
1
D17
0
D16
-
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D15
14
D14
13
D13
12
D12
11
D11
10
D10
9
D9
8
D8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
-
14
-
13
S5
12
S4
11
S3
10
S2
9
S1
8
S0
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
-
6
-
5
M5
4
M4
3
M3
2
M2
1
M1
0
M0
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
-
14
-
13
-
12
H4
11
H3
10
H2
9
H1
8
H0
-
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
<= Bit number
WTCRL
<= Bit number
WTBR
<= Bit number
WTBR
<= Bit number
WTBR
<= Bit number
WTSR
<= Bit number
WTMR
<= Bit number
WTHR
283
CHAPTER 12 REAL-TIME WATCH TIMER
12.2.1 Real-Time Watch Timer Control Register
The real-time watch timer control register is used to start and stop the real-time watch
timer, control interrupts, and set external output pins.
■ Bit configuration of timer control register
Figure 12.2-2 "Bit configuration of timer control register" shows the bit configuration of the timer
control register.
Figure 12.2-2 Bit configuration of timer control register
Real-time watch timer
Upper bits of control register
Address : 000059 H
Reading/writing =>
Initial value =>
Real-time watch timer
Lower bits of control register
Address : 000058 H
Reading/writing =>
Initial value =>
15
14
13
12
11
INTE3
INT3
(R/W)
(0)
(R/W)
(0)
7
6
10
9
INTE2
INT2
(R/W)
(0)
(R/W)
(0)
5
4
INTE1
INT1
(R/W)
(0)
(R/W)
(0)
3
2
TST2
TST1
TST0
-
-
UPDT
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
-
-
(R/W)
(0)
8
<= Bit number
INTE0
INT0
WTCRH
(R/W)
(0)
(R/W)
(0)
1
0
<= Bit number
OE
ST
WTCRL
(R/W)
(0)
(R/W)
(0)
[bits 15 to 8] INT3 to 0, INTE3 to 0: Interrupt flag, and interrupt enable flag
INT3 to INT0 are interrupt flags, which are set in case of overflow in the Sub-second counter,
second counter, minute counter, or hour counter. When the corresponding INTE bit is "1" at
the time the INT bit is set to "1", the real-time watch timer generates an interrupt signal.
These flags are used to generate an interrupt signal with the timing specified in minute/hour/
day.
By setting the INT bit set to "0", the corresponding flag is cleared. Setting the bit to "1" has
no effect. In read-modify-write instructions executed for the INT bit, "1" is read out.
[bit 7 to 5] TST2 to 0: Test bit
These bits are provided for device testing. For user application, these bits must be set to
"000".
[bit 2] UPDT: Rewrite bit
he UPDT bit is provided for changing the values of the second/minute/hour counter.
To change counter values, write the new data to the second/minute/hour register. Then set
the UPDT bit to "1". The register value is loaded into the counter when the next C0 signal is
generated from the 21-bit prescaler. The UPDT bit is reset by hardware if the counter value
is rewritten. In case reset operations be performed by both software and hardware at the
same time, however, the UPDT bit is not reset.
Clearing the UPDT bit to "0" has no effect. In read-modify-write instructions, "0" will be read.
Note:
If the second counter indicates 59 seconds, setting the UPDT bit will not change the counter
value or clear this bit. Therefore, use the ST bit to change the counter value.
284
12.2 Registers of Real-Time Watch Timer
[bit 1] OE: Output Enable bit
When the OE bit is set to "1", the WOT external pin functions as output for the real-time
watch timer. In other cases, it is used for general-purpose I/O or I/ output pin for another
peripheral block.
[bit 0] ST: Start bit
When the ST bit is set to "1", the real-time watch timer loads the second/minute/hour values
from each register to start the corresponding operation. Note that resetting the ST bit to "0"
also resets all counters and prescalers to "0" and stops operation.
285
CHAPTER 12 REAL-TIME WATCH TIMER
12.2.2 Sub-Second Data Register
The sub-second data register stores the reload values of the 21-bit prescaler used for
dividing the frequency of the oscillation clock. Reload values are specified in such a
way that 21-bit prescaler output takes an interval of precisely one second.
■ Bit Configuration of Sub-Second Data Register
Figure 12.2-3 "Bit configuration of sub-second data register" shows the bit configuration of the
Sub-second Data Register.
Figure 12.2-3 Bit configuration of sub-second data register
Sub-second data register
Address : 00395C H
Reading/writing =>
Initial value =>
Sub-second data register
Address : 00395B H
Reading/writing =>
Initial value =>
Sub-second data register
Address : 00395A H
Reading/writing =>
Initial value =>
7
-
6
-
5
-
4
D20
3
D19
2
D18
1
D17
0
D16
-
-
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D15
14
D14
13
D13
12
D12
11
D11
10
D10
9
D9
8
D8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
<= Bit number
WTBRH
<= Bit number
WTBRM
<= Bit number
WTBRL
[bit 20 to 0] D20 to D0
The sub-second data register is used to store a reload value for the 21-bit prescaler. This
value is reloaded after the reload counter reaches "0". Confirm that reload operation is not
executed between write instructions after changing all 3 bytes. Otherwise, the 21-bit
prescaler may load an incorrect value that combines bytes from new and old data. We
recommend rewriting the contents of the sub-second register in ordinary cases (with the start
bit set to "0"). If the sub-second register is set to "0", the 21-bit prescaler does not operate.
The frequency of the input clock is designed to be always the same as the oscillation clock
frequency (4 MHz). The 21-bit prescaler has a reload value (typically the hexadecimal
number "1E847F") that is equal to "27 × 56-1". For this reason, a combination of these two
prescaler values will result in a time between clock signals that is exactly one second.
286
12.2 Registers of Real-Time Watch Timer
12.2.3 Second/Minute/Hour Data Registers
The second/minute/hour data registers are used to store time information. The data of
second, minute, and hour is indicated in binary notation. When these registers are
read, the unit simply returns the counter values. These registers allow writing, and as
soon as the UPDT bit is set to "1", the written data will be loaded into the
corresponding counter.
■ Bit Configuration of Second/Minute/Hour Data Registers
Figure 12.2-4 "Bit configuration of second/minute/hour data registers" shows the bit
configuration of the second/minute/hour data registers.
Figure 12.2-4 Bit configuration of second/minute/hour data registers
Second data register
15
-
14
-
13
S5
12
S4
11
S3
10
S2
9
S1
8
S0
-
-
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
Minute data register
Address : 00395E H
Reading/writing =>
Initial value =>
7
-
6
-
5
M5
4
M4
3
M3
2
M2
1
M1
0
M0
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
Hour data register
15
-
14
-
13
-
12
H4
11
H3
10
H2
9
H1
8
H0
-
-
-
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
R/W
(X)
Address : 00395D H
Reading/writing =>
Initial value =>
Address : 00395FH
Reading/writing =>
Initial value =>
<= Bit number
WTSR
<= Bit number
WTMR
<= Bit number
WTHR
Because these are three single-byte registers, ensure that the values obtained from all registers
is consistent: If a value of "1 hour, 59 minutes, 59 seconds" is obtained, it may actually
represent "0 hours, 59 minutes, 59 seconds", "1 hour, 0 minutes, 0 seconds," or "2 hours, 0
minutes, 0 seconds".
If the frequency of the MCU’s operation clock is half that of the oscillation clock (when PLL
stops), the results read from these registers may be wrong, because read and count operations
are performed in synchronization. It is therefore recommended to use an interrupt that is issued
every second for triggering the read instruction.
287
CHAPTER 12 REAL-TIME WATCH TIMER
288
CHAPTER 13
PPG TIMER
This chapter describes the PPG timer.
13.1 "Overview of PPG Timer"
13.2 "Block Diagram of PPG Timer"
13.3 "Registers of PPG Timer"
13.4 "Operation of PPG Timer"
289
CHAPTER 13 PPG TIMER
13.1 Overview of PPG Timer
The PPG Timer consists of the prescaler, 16-bit down counter (x1), 16-bit data register
for the interval set buffer, 16-bit compare register with a duty setting buffer, and a pin
control section.
It outputs a pulse in synchronization with an external or software trigger. The interval
and duty cycle of pulse output can be freely selected by changing the value of the two
16-bit registers.
■ Overview
❍ PWM function
Allows outputting pulses in synchronization with a trigger as specified by the program via
rewriting the values in the registers above.
This function can be used to provide a D/A converter depending on the external circuit.
❍ One-shot function
Outputs a single pulse based on edge-detection in the trigger input signal.
❍ Pin control
The PPG Timer is used for pin control as follows:
•
Set to "1" if duty cycle matching was successful (priority).
•
Reset to "0" by counter borrow.
•
Uses output value fixed mode to simply output all "L" (or all "H").
•
Polarity can be specified.
❍ 16-bit down counter
Specifies the counter operation clock among the four types of internal clocks (φ, φ/4, φ/16, φ/64):
φ: Machine clock frequency
The counter value may be initialized to FFFFH by a reset or by counter borrow.
❍ Interrupt requests
The PPG timer generates an interrupt request under the following conditions:
•
Timer start
•
Counter borrow (interval matched)
•
Duty cycle matched
•
Counter borrow (interval matched), or duty cycle matched.
❍ An external trigger can be used to specify activation of multiple channels simultaneously.
Restart during operation may also be specified.
290
13.1 Overview of PPG Timer
■ PPG Timer interrupts and EI2OS
Table 13.1-1 "Interrupts of PPG timer and EI2OS" lists the interrupts and EI2OS of the PPG
Timer.
Table 13.1-1 Interrupts of PPG timer and EI2OS
Channel
Interrupt
number
Interrupt level setting
register
Register
name
Vector table address
EI2OS
Address
Lower
bits
Upper
bits
Bank
PPG timer 0
#25(19H)
ICR07
0000B7H
FFFF98H
FFFF99H
FFFF9AH
partly(*2)
PPG timer 1
#27(1BH)
ICR08
0000B8H
FFFF90H
FFFF91H
FFFF92H
partly(*2)
PPG timer 2
#29(1DH)
ICR09
0000B9H
FFFF88H
FFFF89H
FFFF8AH
available(*1)
*1: available
*2: Available when not using interrupt sources sharing ICR07, ICR08 and the interrupt vector.
291
CHAPTER 13 PPG TIMER
13.2 Block Diagram of PPG Timer
This section shows a block diagram of the PPG Timer.
■ Block Diagram of PPG Timer
Figure 13.2-1 "Block diagram of PPG timer" shows a block diagram of the PPG Timer.
Figure 13.2-1 Block diagram of PPG timer
PDUT
PCSR
Prescaler
1/1
1/4
1/16
1/32
Load
CK
PCNT
CMP
16-bit down-counter
Start
Borrow
PPG mask
Machine clock
S
Q
PPG output
R
Reverse bit
Enable
Trigger input
P05/SCK1/TRG
Edge detect
Software trigger
292
Interrupt
selection
Interrupt IRQ#25,#27,#29
13.3 Registers of PPG Timer
13.3 Registers of PPG Timer
This sections describes the registers of the PPG Timer.
■ List of PPG Timer Registers
Figure 13.3-1 "Registers of the PPG timer" lists the registers of the PPG Timer.
Figure 13.3-1 Registers of the PPG timer
Upper bits of PPG control status register
Address
Address
Address
Reading/writing
Initial value
Lower bits of PPG control status register
Address
Address
Address
Reading/writing
Initial value
Upper bits of PPG down counter register
Address
Address
Address
Reading/writing
Initial value
Lower bits of PPG down counter register
Address
Address
Address
Reading/writing
Initial value
Upper bits of PPG interval setting register
Address
Address
Address
Reading/writing
Initial value
Lower bits of PPG interval setting register
Address
Address
Address
Reading/writing
Initial value
Upper bits of PPG duty setting register
Address :
Address :
Address :
Reading/writing
Initial value
Lower bits of PPG duty setting register
Address :
Address :
Address :
Reading/writing
Initial value
293
CHAPTER 13 PPG TIMER
13.3.1 Detailed Description of the PPG Timer
The PPG Timer has the following four registers:
• PPG control status registers (PCNT0 to 2)
• PPG down counter registers (PDCR0 to 2)
• PPG interval setting registers (PCSR0 to 2)
• PPG duty setting registers (PDUT0 to 2)
■ PPG Control Status Register (PCNT)
Figure 13.3-2 "Bit configuration of PPG control status registers (PCNT0 to 2)" shows the bit
configuration of the PPG Control Status Registers (PCNT0 to 2).
Figure 13.3-2 Bit configuration of PPG control status registers (PCNT0 to 2)
Upper bits of PPG control status register
Address:
Address:
Address:
Reading/writing
Initial value
Lower bits of PPG control status register
Address:
Address:
Address:
Reading/writing
Initial value
[bit 15] CNTE: Timer enable bit
This bit is provided for 16-bit down counter operation.
CNTE
Timer enable
0
Stop (initial value)
1
Enabled
[bit 14] STGR: Software trigger bit
Setting this bit to "1" enables issuing a software trigger.
The STGR bit is always read as "0".
[bit 13] MDSE: Mode selection bit
Enables the selection of PWM operation (to continuously output pulses) or one-shot
operation (to output a single pulse). This bit cannot be rewritten during operation.
MDSE
294
Mode selection
0
PWM operation (initial value)
1
One-shot operation
13.3 Registers of PPG Timer
[bit 12] RTRG: Restart enable bit
This bit is used to restart based on a software trigger. This bit cannot be rewritten during
operation.
RTRG
Restart enable
0
Restart disabled (initial value)
1
Restart enabled
[bits 11, 10] CKS1, CKS0: Counter clock selection bits
These bits are used to select a counter clock for the 16-bit down counter. These bits cannot
be rewritten during operation.
CKS1
CKS0
Interval
0
0
φ (Initial value)
0
1
φ/4
1
0
φ/16
1
1
φ/64
φ: Machine clock frequency
[bit 9] PGMS: PPG output mask selection bit
By setting this bit, PPG output can be masked to either "0" or "1" regardless of mode setting,
interval setting value, and duty setting value.
The table below shows the PPG Timer output level (with PGMS set to "1").
Polarity
PPG output
Normal polarity
L
Reverse polarity
H
To output all H at normal polarity, or all L at reverse polarity, write the same value to the interval
setting register and duty setting register for enabling reverse output of the masked value above.
[bit 8] Bit undefined.
Value at reading is not specified. Writing does not affect operation.
[bits 7, 6] EGS1, EGS0: trigger input edge selection bit
Set the software trigger bit to "1" to enable software triggers regardless of the mode
selected.
EGS1
EGS0
Edge selection
0
0
Disabled (initial value)
0
1
Leading edge
1
0
Trailing edge
1
1
Both edges
295
CHAPTER 13 PPG TIMER
[bit 5] IREN: Enable bit for interrupt requests
This bit is used as the PPG Timer interrupt enable bit. When both the IREN bit and interrupt
flag (bit 4: IRQF) are set to "1", an interrupt is generated.
IREN
Interrupt request enable
0
Interrupt disabled (initial value)
1
Interrupt enabled
[bit 4] IRQF: Interrupt request flag
When IREN (bit 5) is set to "enabled" and the interrupt sources selected by IRS1/0 (bits 3/2)
occur, the IRQF bit is set and the interrupt request is issued to the CPU.
The IRQF bit enables reading and writing. It can only be cleared, by writing "0"; writing "1"
will not change the bit value. Reading with a read-modify-write type instruction will return "1"
independent of the actual value of the bit.
[bits 3, 2] IRS1, IRS0: Interrupt source selection bits
These bits enables selection of a cause to set bit 4 (IRQF).
IRS1
IRS0
Edge selection
0
0
Software trigger or any valid trigger input (initial value)
0
1
Counter borrow (interval matching)
1
0
Normal polarity PPG
cycle matching)
1
1
Counter borrow, or normal polarity PPG
polarity PPG
, or reverse polarity PPG
[bit 1] POEN: PPG output enable bit
Set to "1" to enable PPG output from the pin.
POEN
PPG output enable
0
General-purpose port (initial value)
1
PPG output pin
[bit 0] OSEL: PPG output polarity specification bit
Used to set the PPG output polarity.
POEN
296
PPG output polarity
0
Normal polarity (initial value)
1
Reverse polarity
(duty
, or reverse
13.3 Registers of PPG Timer
The following operations can be performed using bit 9 (PGMS):
PGMS
OSEL
0
0
Normal polarity (initial value)
0
1
Reverse polarity
1
0
Output fixed to "L"
1
1
Output fixed to "H"
Polarity
PPG output
After reset
Normal polarity
"L" output
Reverse polarity
"H" output
Duty cycle
matched
Counter matched
■ PPG Down Counter Registers (PDCR)
PDCR is used to read the value of the 16-bit down counter.
PDCR can be accessed in word unit access.
Figure 13.3-3 "Bit configuration of PPG down counter register (PDCR)" shows the bit
configuration of the PPG down counter register (PDCR).
Figure 13.3-3 Bit configuration of PPG down counter register (PDCR)
Upper Bits of PPG Down Counter Register Bit15 Bit14
Address: ch0 003921 H
Address: ch1 003929 H
Address: ch2 003931 H
Bit9
Bit8
PDCRH0- 2
DC15
DC14
DC13
DC12
DC11
DC10
DC09
DC08
R
R
R
R
R
R
R
R
( 1)
( 1)
( 1)
( 1)
( 1)
( 1)
( 1)
( 1)
Lower bits of PPG down counter register
Address: ch0 003920 H
Address: ch1 003928 H
Address: ch2 003930 H
Bit13 Bit12 Bit11 Bit10
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Reading/writing
Initial value
Bit0
PDCRH0- 2
DC07
DC06
DC05
DC04
DC03
R
( 1)
R
( 1)
R
( 1)
R
( 1)
R
( 1)
DC02
DC01
DC00
R
( 1)
R
( 1)
R
( 1)
Reading/writing
Initial value
297
CHAPTER 13 PPG TIMER
■ PPG Interval Setting Register (PCSR)
PCSR is a register with a buffer for setting the interval. Transfer from the buffer is executed by
counter borrow. For initializing the PCSR or for changing the setting later on, first write to the
interval setting register, then to the duty setting register as required.
PCSR is accessed in word unit accesses.
Figure 13.3-4 "Bit configuration of PPG interval setting register (PCSR)" shows the bit
configuration of the PPG interval setting register (PCSR).
Figure 13.3-4 Bit configuration of PPG interval setting register (PCSR)
Upper bits of PPG interval setting register
Address: ch0 003923 H
Address: ch1 00392BH
Address: ch2 003933 H
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Bit8
PC SRH 0- 2
CS15 CS14 CS13 CS12 CS11 CS10 CS09 CS08
W
(X)
Lower bits of PPG interval setting register
Address: ch0 003922 H
Address: ch1 00392AH
Address: ch2 003932 H
Bit9
W
(X )
Bit7
W
(X)
Bit6
W
(X)
Bit5
W
(X )
Bit4
W
(X )
Bit3
W
(X)
Bit2
W
(X)
Bit1
Reading/writing
Initial value
Bit0
PC SRH 0- 2
CS07 CS06 CS05 CS04 CS03 CS02 CS01 CS00
W
(X)
W
(X)
W
( X)
W
(X )
W
(X )
W
(X )
W
(X)
W
(X)
Reading/writing
Initial value
■ PPG Duty Setting Registers (PDUT)
PDUT is a register with a buffer for setting the duty cycle. Transfer from the buffer is executed
by counter borrow.
Set both the interval setting register and the duty setting register to the same value to output all
H for normal polarity, or all L for reverse polarity.
Do no make settings in such a way that PCSR < PDUT applies. Otherwise, PPG output will
become undefined.
PDUT is accessed in word unit access.
Figure 13.3-5 "Bit configuration of PPG duty setting register (PDUT)" shows the bit configuration
of the PPG duty setting register (PDUT).
Figure 13.3-5 Bit configuration of PPG duty setting register (PDUT)
Upper bits of PPG duty setting register
Address: ch0 00 3925 H
Address: ch1 00 392DH
Address: ch2 00 3935 H
Bit15
Bit12
Bit11
Bit10
Bit9
DU14
DU13
DU12
DU11
DU10
DU09
Bit8
DU08
W
W
W
W
W
W
W
W
( X)
( X)
( X)
( X)
( X)
( X)
( X)
( X)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Reading/writing
Initial value
Bit0
P DUTL0- 2
DU07
W
( X)
298
Bit13
P DUTH 0- 2
DU15
Lower bits of PPG interval setting register
Address: ch0 00 3924 H
Address: ch1 0 0392C H
Address: ch2 00 3934 H
Bit14
DU06
W
( X)
DU00
DU04
DU03
W
W
W
W
W
W
( X)
( X)
( X)
( X)
( X)
( X)
DU02
DU01
DU05
Reading/writing
Initial value
13.4 Operation of PPG Timer
13.4 Operation of PPG Timer
This section describes the operation of the PPG Timer.
■ PWM Operation
In PWM operation, pulses are continuously output after a start trigger was detected. Change the
PCSR value to control the interval between output pulses. Change the PDUT value to control
the duty ratio.
❍ When restart is disabled
Figure 13.4-1 Timing of PWM operation when restart is disabled
Leading edge detected
Trigger ignored
Start trigger
m
n
0
PPG
T(n-1) s
T(m-1)
s
T: Count clock interval
m: PCSR value
n: PDUT value
299
CHAPTER 13 PPG TIMER
❍ When restart is enabled
Figure 13.4-2 Timing of PWM operation when restart is enabled
Start trigger
Leading edge detected
Restart by trigger
m
n
o
PPG
Notes:
•
After writing data to PCSR, also write to PDUT as required.
•
When external TRG input is selected as start trigger, a pulse having at least the minimum
pulse width must be input.
Minimum pulse width: 2 machine cycles
However, even if a pulse with a smaller pulse width than quoted above is input, it may be
recognized as valid. Because the MB90420G/425G series provides no filter functions for
external TRG input, add an external filter as required.
300
13.4 Operation of PPG Timer
■ One-Shot Operation
In one-shot operation, a single pulse of any width can be output base on a trigger. When restart
is enabled, reload the counter value if a start trigger is detected during operation.
❍ When restart is disabled
Figure 13.4-3 Timing of one-shot operation when restart is disabled
Leading edge detected
Trigger ignored
Start trigger
m
n
0
PPG
❍ When restart is enabled
Figure 13.4-4 Timing of one-shot operation when restart is enabled
Leading edge detected
Restart by trigger
Start trigger
m
n
0
PPG
301
CHAPTER 13 PPG TIMER
■ Timing of Interrupt Sources
It takes up to 2.5T (T: count clock interval) after a start trigger before the count value is loaded.
Figure 13.4-5 Timing of interrupt sources
Start trigger
Up to 2.5T
Load
Clock
XXXXh
Count value
0003h
0002h
0001h
0000h
0003h
PPG
Interrupt
Software trigger
Compare match
Borrow
■ Example of PWM output for all "L" or all "H"
Figure 13.4-6 Example of PWM output of all "L" or all "H"
PPG
Gradual
decrease in
duty ratio
Set the mask bit of PGMS to "1" in
response to an interrupt because
of a borrow. Alternatively, set the
mask bit of PGMS to "0" to enable
PPG waveform output without actual
output.
PPG
Gradual
increase in
duty ratio
302
When an interrupt due to matching occurs,
write the same value as stored in the interval
set register to the duty ratio set register.
CHAPTER 14
DELAY INTERRUPT GENERATION
MODULE
This chapter describes the functions and operations of the delay interrupt generation
module.
14.1 "Overview of Delay Interrupt Generation Module"
14.2 "Operation of Delay Interrupt Generation Module"
303
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE
14.1 Overview of Delay Interrupt Generation Module
The delay interrupt generation module is used to generate an interrupt for task
switching. Use this module to enable software to issue or cancel an interrupt request
to the F2MC-16LX CPU.
■ Block Diagram of Delay Interrupt Generation Module
Figure 14.1-1 "Block diagram of delay interrupt generation module" shows a block diagram of
the Delay Interrupt Generation Module.
Figure 14.1-1 Block diagram of delay interrupt generation module
Internal data bus
Generating/clearing delayed interrupt source
Source latch
■ List of Registers of Delay Interrupt Generation Module
The following figure shows the register configuration of the delay interrupt source generation/
clear register [Delayed Interrupt Request Register (DIRR)] of the delay interrupt generation
module.
Figure 14.1-2 Register configuration of delay interrupt generation module
bit
DIRR Address 00009FH
15
14
13
12
11
10
9
8
R0
Initial value
-------0 H
R/W
At reset, DIRR is set to source clear state.
DIRR is used to generate or cancel a delay interrupt request. Set the register to "1" to generate
a delay interrupt request; set to "0" to cancel the request. At reset, DIRR is set to source clear
state. The undefined bit can be set to either "0" or "1" by a write operation; however, considering
future extensions, we recommend using the set bit and clear bit instructions to access the
register.
304
14.1 Overview of Delay Interrupt Generation Module
■ Interrupts for Delay Interrupt Generation Module and EI2OS
Table 14.1-1 "Block diagram of delay interrupt generation module" lists the interrupts and EI2OS
for the Delay Interrupt Generation Module.
Table 14.1-1 Interrupts of delay interrupt generation module and EI2OS
Interrupt level set register
Interrupt
number
#42(2AH)
Vector table address
Register
name
Address
Lower bits
Upper bits
Bank
EI2OS
ICR15
0000BFH
FFFF54H
FFFF55H
FFFF56H
*
*: Cannot be used
305
CHAPTER 14 DELAY INTERRUPT GENERATION MODULE
14.2 Operation of Delay Interrupt Generation Module
When the CPU sets the relevant bit in DIRR to "1" by software, the request latch in the
delay interrupt generation module is set to generate an interrupt request to the
interrupt controller.
■ Operation of Delay Interrupt Generation Module
When the CPU sets the relevant bit in DIRR to "1" by software, the request latch in the delay
interrupt generation module is set to generate an interrupt request to the interrupt controller. If
any other interrupt request has a priority lower than that of the interrupt in the delay interrupt
generation module, or if there are no other interrupt requests, the interrupt controller issues an
interrupt request to the F2MC-16LX CPU.
The F2MC-16LX CPU compares the ILM bit in its internal CCR register and the interrupt
request. If the request level is higher than that indicated in the ILM bit, the CPU starts a
hardware interrupt-handling microprogram immediately after the current instruction being
executed is completed. As a result, the interrupt-handling routine is run in response to an
interrupt generated by the delay interrupt generation module.
Setting the relevant bit in DIRR used by the interrupt-handling routine to "0" clears the interrupt
source generated in the delay interrupt generation module, and also switches the task.
Figure 14.2-1 "Operation of delay interrupt generation module" shows the operation of the delay
interrupt generation module.
Figure 14.2-1 Operation of delay interrupt generation module
Delay interrupt generation module
F 2MC- 16LX
Delay interrupt controller
WRITE
Other
requests
ICR yy
ICR yy
CMP
CMP
DIRR
ICR xx
ICR xx
NTA
■ Notes on Using the Delay Interrupt Generation Module
❍ Delay interrupt request latch
This latch is set by setting the relevant bit in DIRR to "1", and cleared by clearing the bit to "0".
Therefore, note that unless the software is written in such a way that internal factors are cleared
in the interrupt-handling routine, interrupt handling will start again immediately after the return
from interrupt handling.
306
CHAPTER 15
DTP/EXTERNAL INTERRUPT CIRCUIT
This chapter describes the functions and operations of the DTP/external interrupt
circuit.
15.1 "Overview of DTP/External Interrupt Circuit"
15.2 "Configuration of DTP/External Interrupt Circuit"
15.3 "Pins of DTP/External Interrupt Circuit"
15.4 "Registers of DTP/External Interrupt Circuit"
15.5 "Operation of the DTP/External Interrupt Circuit"
15.6 "Notes on Using the DTP/External Interrupt Circuit"
15.7 "Sample Programs for the DTP/External Interrupt Circuit"
307
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.1 Overview of DTP/External Interrupt Circuit
The Data Transfer Peripheral (DTP)/external interrupt circuit is located between
externally connected peripheral units and the F2MC-16LX CPU. This circuit is used to
transfer an interrupt request or data transfer request generated by a peripheral unit to
the CPU, generate an external interrupt request, or start the extended intelligent I/O
service (EI2OS).
■ DTP/External Interrupt Function
The DTP/external interrupt function uses a signal input to the DTP/external interrupt pin as a
start source, which is then received by the CPU according to the same procedure as for a
normal hardware interrupt. This function is used to generate an external interrupt or start the
extended intelligent I/O service (EI2OS).
When an interrupt request is received by the CPU, and the corresponding extended intelligent I/
O service (EI2OS) is disabled, the DTP/external interrupt function operates as an external
interrupt function and branches to an interrupt routine. Otherwise, if EI2OS is enabled, the DTP/
external interrupt function operates as the DTP function with automatic data transfer executed
by EI2OS, then branches to an interrupt-handling routine when data transfer for the specified
number of times is completed.
Table 15.1-1 "Overview of DTP/external interrupt function" shows an overview of the DTP/
external interrupt function.
Table 15.1-1 Overview of DTP/external interrupt function
External interrupt
DTP function
Input pin
x 8 (P50/INT0/ADTG - P53/INT3,P00/SIN0/INT4 - P03/SIN1/INT7)
Interrupt source
Selects the detection level or edge for each pin with the request level setting register
(ELVR).
Inputs either "H" level, "L" level,
leading edge or trailing edge.
"H" level/"L" level input
Interrupt number
#16(10H), #18(12H), #20(14H), #22(16H), #24(18H), #26(1AH)
Interrupt control
Enables or disables interrupt request output by DTP/interrupt enable register (ENIR).
Interrupt flag
Holds the interrupt source in DTP/interrupt source register (EIRR).
Selection of
processing
Sets EI2OS to "disabled"
(ICR:ISE=0)
Sets EI2OS to "enabled" (ICR: ISE=1)
Processing
Branches to the external interrupt
process routine.
Branching to the input routine after automatic data
transfer and for specified processing based on the
specified count is performed by EI2OS.
ICR: Interrupt control register
308
15.1 Overview of DTP/External Interrupt Circuit
■ Interrupts of DTP/external interrupt circuit and EI2OS
Table 15.1-2 Interrupts of DTP/external interrupt circuit and EI2OS
ICR
Channel
Interrupt
number
Vector table address
Register
name
Address
Lower bits
Upper bits
Bank
INT0
#16(10H)
ICR02
0000B2H
FFFFC0H
FFFFC1H
FFFFC2H
INT1
#18(12H)
ICR03
0000B3H
FFFFB4H
FFFFB5H
FFFFB6H
INT2
#20(14H)
ICR04
0000B4H
FFFFACH
FFFFADH
FFFFAEH
INT3
#22(16H)
ICR05
0000B5H
FFFFA4H
FFFFA5H
FFFFA6H
#24(18H)
ICR06
0000B6H
FFFF9CH
FFFF9DH
FFFF9EH
#26(1AH)
ICR07
0000B7H
FFFF94H
FFFF95H
FFFF96H
EI2OS
*
INT4
INT5
INT6
INT7
*: Available when not using interrupt sources sharing ICR02 to ICR07, and the interrupt vector.
309
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.2 Configuration of DTP/External Interrupt Circuit
The DTP/external interrupt circuit consists of the following four blocks:
• DTP/Interrupt Input Detect Circuit
• Request Level Set Register (ELVR)
• DTP/Interrupt Source Register (EIRR)
• DTP/Interrupt Enable Register (ENIR)
■ Block Diagram of DTP/External Interrupt Circuit
Figure 15.2-1 "Block diagram of DTP/external interrupt circuit" shows a block diagram of the
DTP/external interrupt circuit.
Figure 15.2-1 Block diagram of DTP/external interrupt circuit
Request level setting register (ELVR)
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
Pin
Selector
Selector
Selector
Pin
Selector
P02/INT6
Pin
P51/INT1
Selector
Pin
Internal data bus
Pin
P50/INT0
P03/INT7
Selector
P01/INT5
Pin
P52/INT2
Pin
Selector
Selector
Pin
P53/INT3
P00/INT4
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
Interrupt request number
#16(10H)
#18(12H)
#20(14H)
#22(16H)
#24(18H)
#26(1AH)
EN7
310
EN6
EN5
EN4
EN3
EN2
EN1
EN0
15.2 Configuration of DTP/External Interrupt Circuit
❍ DTP/external interrupt input detection circuit
For detecting a level or edge in the input signal of a certain pin, so as to determine whether the
input signal is valid, set the IR bit of the corresponding DTP/external interrupt source register
(EIRR) to "1". (Whether to detect a level or edge can be selected by the interrupt request level
setting register (ELVR))
❍ Request level setting register (ELVR)
The request level setting register is used to select a valid level or edge for each pin.
❍ DTP/interrupt source register (EIRR)
A register used to hold a DTP/external interrupt source. Each pin has a corresponding external
flag bit for interrupt requests in this register, which is set to "1" when a valid signal is input.
❍ DTP/interrupt enable register (ENIR)
A register used to enable or disable external interrupts for each pin.
311
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.3 Pins of DTP/External Interrupt Circuit
This section describes the pins of the DTP/external interrupt circuit and shows a block
diagram.
■ Pins of the DTP/External Interrupt Circuit
The pins of the DTP/external interrupt circuit are used as both general-purpose ports and for
peripheral functions. Table 15.3-1 "Pins of the DTP/external interrupt circuit" lists the pin
functions, type of I/O, and settings for using the DTP/external interrupt circuit.
Table 15.3-1 Pins of the DTP/external interrupt circuit
Pin name
Pin function
I-O mode
Pull-up
resistor
Standby
control
Set to input port
(DDR5: bit 0=0)
P50/INT0/ADTG
P51/INT1
P52/INT2
Setting required to
use pin
Set to input port
(DDR5: bit 1=0)
I/O for Port 5 or
external interrupt
input
Set to input port
(DDR5: bit 2=0)
Set to input port
(DDR5: bit 3=0)
P53/INT3
CMOS output/
CMOS hysteresis
input
P00/SIN0/INT4
P01/SOT0/INT5
Port 0 I-O/
external interrupt
input
None
None
Set to input port
(DDR0: bit 0=0)
Set to input port
(DDR0: bit 1 =0)
(UART0 data output
disabled)
P02/SCK0/INT6
Set to input port
(DDR0: bit 2=0)
(UART0 clock output
disabled)
P03/SIN1/INT7
Set to input port
(DDR0: bit 3=0)
312
15.3 Pins of DTP/External Interrupt Circuit
■ Block Diagram of Pins of DTP/External Interrupt Circuit
Figure 15.3-1 "Block diagram of pins of DTP/external interrupt circuit" shows a block diagram of
the pins of the DTP/external interrupt circuit.
Figure 15.3-1 Block diagram of pins of DTP/external interrupt circuit
Port Data Register (PDR)
Resource input (INT)
Internal data bus
PDR read
Output latch
PDR write
Pin
Port Direction Register (DDR)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
313
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.4 Registers of DTP/External Interrupt Circuit
This section lists the registers for the DTP/external interrupt circuit.
■ Registers of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit has the three types listed below.
•
DTP/Interrupt source register (EIRR)
•
DTP/Interrupt enable register (ENIR)
•
Request level setting register (ELVR)
Figure 15.4-1 "List of registers of DTP/external interrupt circuit" lists the registers of the DTP/
external interrupt circuit.
Figure 15.4-1 List of registers of DTP/external interrupt circuit
Address
314
000031 H ,
30 H
000033 H ,
32 H
Bit15
Bit8
Bit7
Bit0
DTP/Interrupt source register (EIRR) DTP/Interrupt enable register (ENIR)
Request level setting register (ELVR)
15.4 Registers of DTP/External Interrupt Circuit
15.4.1 DTP/Interrupt source Register (EIRR)
The DTP/interrupt source register (EIRR) is used to hold or clear interrupt sources.
■ DTP/Interrupt source Register (EIRR)
Figure 15.4-2 "DTP/interrupt source register (EIRR)" shows the configuration of the DTP/
interrupt source register; Table 15.4-1 "Description of DTP/interrupt source register (EIRR)
functions" lists the functions of each bit.
Figure 15.4-2 DTP/interrupt source register (EIRR)
Address
000031 H
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10
Bit9
Bit8
ER7
ER6
ER5
ER4
ER3
ER2
ER1
ER0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ER7 to ER0
0
1
Bit7
Bit0
ENIR
Initial value
00000000 B
Flag bit for external interrupt request
Read
Write
No DTP/external interrupt input
Clear this bit.
DTP/external interrupt input
Does not change and has no effect
R/W: Reading and writing permitted
: Initial value
Table 15.4-1 Description of DTP/interrupt source register (EIRR) functions
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Function
•
ER7 to ER0:
Flag bit for external
interrupt request
•
•
•
Set to "1" if the edge or level signal selected by the request level
set register (ELVR):LB7,LA7 - LB0 or LA0 bits is input to the DTP/
external interrupt pin (which holds the interrupt source).
An interrupt request is issued to the CPU when this bit and the
corresponding bits EN7 to EN0 of the DTP/Interrupt Enable
Register (ENIR) are set to "1".
Cleared when set to "0" in write mode. Writing "1" has no effect.
When the extended intelligent I/O service (EI2OS) starts, the
corresponding external flag bit for interrupt request is automatically
cleared at data transfer.
Notes:
In read-modify-write type instructions, "1" is returned.
If multiple external interrupt request outputs are enabled (ENIR: EN7 to EN0=1), only the bits for which the
CPU accepts an interrupt (bits for which "1" was set in ER7 to ER0) are cleared. No other bits must be
cleared unconditionally.
The initial value is 00H, but the value after reset cancellation depends on the state of the DTP/external
interrupt pin.
315
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.4.2 DTP/Interrupt Enable Register (ENIR)
The DTP/interrupt enable register (ENIR) is used to enable or disable interrupt request
output to the CPU.
■ DTP/Interrupt Enable Register (ENIR)
Figure 15.4-3 "DTP/interrupt enable register (ENIR)" shows the configuration of DTP/interrupt
enable register (ENIR); Table 15.4-2 "Description of bit functions of DTP/interrupt enable
register (ENIR)" lists the functions of each bit.
Table 15.4-3 "Correspondence of channels to DTP/interrupt control registers (EIRR, ENIR)"
shows the correspondence between DTP/interrupt enable register (ENIR), DTP/Interrupt source
register (EIRR), and each channel.
Figure 15.4-3 DTP/interrupt enable register (ENIR)
Address
00003 0H
Bit 15
Bit 8
EI R R
Bit 7
Bit 6
Bit 6
Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Initial value
EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000B
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EN7 to
EN0
Enable bit for external interrupt requests
0
1
External interrupt requests disabled
External interrupt requests enabled
R/W : Reading and writing permitted
: Initial value
Table 15.4-2 Description of bit functions of DTP/interrupt enable register (ENIR)
Bit name
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
EN7 to EN0
Enable bit for
external interrupt
requests
Function
Enables or disables interrupt request output to the CPU.
When this bit and the corresponding ER7 to ER0 bits in the DTP/interrupt
source Register (EIRR) are set to "1", an interrupt request is output to the
CPU.
• The state of the DTP/external interrupt pin can be read from the port
data register, regardless of the state of external enable bit for interrupt
request.
• The ER7 to ER0 bits in the DTP/Interrupt source Register (EIRR) are set
to "1" at interrupt source detection, regardless of the value indicated by
the external enable bit for interrupt requests.
Note:
To use the DTP/external interrupt pin, set the corresponding port direction register bit to "0" and set the
pin to "input".
316
15.4 Registers of DTP/External Interrupt Circuit
Table 15.4-3 Correspondence of channels to DTP/interrupt control registers (EIRR,
ENIR)
DTP/External
interrupt pin
Interrupt
number
Flag bit for external
interrupt requests
Enable bit for external
interrupt requests
P03/INT7
#26(1AH)
ER7
EN7
P02/INT6
#26(1AH)
ER6
EN6
P01/INT5
#24(18H)
ER5
EN5
P00/INT4
#24(18H)
ER4
EN4
P53/INT3
#22(16H)
ER3
EN3
P52/INT2
#20(14H)
ER2
EN2
P51/INT1
#18(12H)
ER1
EN1
P50/INT0
#16(10H)
ER0
EN0
317
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.4.3 Request Level Setting Register (ELVR)
The request level setting register (ELVR) is used to select a signal level or edge type
for each pin for detecting whether an input signal to the DTP/external interrupt pin is a
DTP/external interrupt source.
■ Request Level Setting Register (ELVR)
Figure 15.4-4 "Request level setting register (ELVR)" shows the configuration of the request
level setting register (ELVR); Table 15.4-4 "Description of the functions of each bit in the request
level setting register (ELVR)" lists the functions of each bit.
Table 15.4-5 "Correspondence between channels and request level setting register (ELVR)"
shows the correspondence between each bit of the request level setting register (ELVR) and the
channels.
Figure 15.4-4 Request level setting register (ELVR)
Address Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
000033 H
Initial value
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 00000000 B
LB7 to LB0 LA 7 to LA0
0
0
0
1
1
0
1
1
R/W : Reading and writing permitted
: Initial value
318
Detection setting bit for external interrupt
request
L level detection
H level detection
Leading edge detection
Trailing edge detection
15.4 Registers of DTP/External Interrupt Circuit
Table 15.4-4 Description of the functions of each bit in the request level setting register (ELVR)
Bit name
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
LB7, LA7 to LB0,
LA0:
Selection bit for
request detection
Function
•
•
Used to select the signal level or edge type (i.e., DTP/
external interrupt source) input to the DTP/external
interrupt pin.
Two bits are assigned per pin.
Note:
When a selected detect signal is input to the DTP/external interrupt pin, the external flag bit for interrupt
requests is set to "1" regardless of the setting in the DTP/interrupt enable register (ENIR).
Table 15.4-5 Correspondence between channels and request level setting register
(ELVR)
DTP/external interrupt pin
Interrupt number
Bit name
P03/INT7
#26(1AH)
LB7, LA7
P02/INT6
#26(1AH)
LB6, LA6
P01/INT5
#24(18H)
LB5, LA5
P00/INT4
#24(18H)
LB4, LA4
P53/INT3
#22(16H)
LB3, LA3
P52/INT2
#20(14H)
LB2, LA2
P51/INT1
#18(12H)
LB1, LA1
P50/INT0
#16(10H)
LB0, LA0
319
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.5 Operation of the DTP/External Interrupt Circuit
The DTP/external interrupt circuit has an external interrupt function and a DTP
function. This section describes the settings and operation of each function.
■ Settings of the DTP/External Interrupt Circuit
To operate the DTP/external interrupt circuit, the settings shown in Figure 15.5-1 "DTP/external
interrupt circuit" are required.
Figure 15.5-1 DTP/external interrupt circuit
ICR13
ICR10 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ICR08
ICR07 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0 ICS3 ICS2 ICS1 ICS0 ISE IL2 IL1 IL0
ICR06
0
0
For external interrupts
ICR03
1
1
For DTP
EIRR
ENIR
ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0
ELVR
LB7 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
DDR5/0
P53 P52 P51 P50
P03 P02 P01 P00
: Bit used
: Set the bit corresponding to the pin used to "0"
: Set the bit corresponding to the pin used to "1"
: Set to "0"
: Set to "1"
Set the registers for the DTP/external interrupt circuit as follows:
1. Set the relevant bit in the DTP/Interrupt Enable Register (ENIR) to disabled.
2. Set the relevant bit in the request level setting register (ELVR).
3. Clear the relevant bit in the DTP/interrupt source register (EIRR).
4. Set the relevant bit in the DTP/interrupt enable register (ENIR) to "enable".
Set the registers for the DTP/external interrupt circuit after first setting external interrupt request
output to "disabled" (ENIR: EN7 to EN0=0). To enable external interrupt request output (ENIR:
EN7 to EN0=1), clear the corresponding flag bit for interrupt requests (EIRR: ER7 to ER0=0) in
advance to avoid accidentally generating an interrupt request when setting the register contents.
320
15.5 Operation of the DTP/External Interrupt Circuit
❍ Switching between external interrupt function and DTP function
To switch between the external interrupt function and the DTP function, set the ISE bit in the
corresponding interrupt control register (ICR). When the ISE bit is set to "1", the extended
intelligent I/O service (EI2OS) is enabled and the DTP function operates. When this bit is "0",
EI2OS is disabled and only the external interrupt function can operate.
Note:
When assigning multiple interrupt requests to only one ICR, an interrupt level (IL2 to IL0) will
be shared among all interrupt requests. Using EI2OS with an interrupt request will generally
disable the use of other interrupt requests.
■ DTP/External Interrupt Operation
Table 15.5-1 "Control bits and interrupt sources of DTP/external interrupt circuit" lists the control
bits and interrupt sources for the DTP/external interrupt circuit.
Table 15.5-1 Control bits and interrupt sources of DTP/external interrupt circuit
DTP/external interrupt circuit
Flag bit for interrupt request
EIRR: ER7 to ER0
Enable bit for interrupt requests
ENIR: EN7 to EN0
Interrupt source
Valid edge/level input to pins INT7 to INTO
After a DTP/external interrupt request is set, if a source specified by the request level setting
register (ELVR) is input to the corresponding pin, the corresponding resource generates an
interrupt request signal to the interrupt controller. Setting the ISE bit to "0" causes an interrupthandling microprogram to be run, and setting it to "1" causes an extended intelligent I/O service
processing (DTP processing) microprogram to be run. Figure 15.5-2 "Flowchart of DTP/external
interrupt circuit operation" shows a flowchart of DTP/external interrupt circuit operation.
321
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
Figure 15.5-2 Flowchart of DTP/external interrupt circuit operation
DTP/external interrupt circuit
Other requests
Interrupt controller
ELVR
ICR YY
EIRR
CMP
ICR XX
ENIR
CPU
IL
CMP
ILM
Microprogram
for interrupt
handling
Factor
DTP processing routine
(EI2OS startup)
Generation of DTP/external
interrupt request
Data transfer
Memory
Judging
interrupt controller
acceptance
Peripheral
Descriptor update
Descriptor
data counter
Judging
CPU interrupt acceptance
0
Interrupt handling routine
Resetting or stopping
Return from DTP processing
Starting interrupt handling
microprogram
ICR:ISE
CPU process return
1
0
Starting external interrupt routine
Clearing processing and interrupt flag
Return from external interrupt
322
15.5 Operation of the DTP/External Interrupt Circuit
15.5.1 External Interrupt Function
The DTP/external interrupt circuit has an external interrupt function that issues an
interrupt request to the DTP/external interrupt pin with a signal level selected.
■ External Interrupt Function
When a signal selected (edge or level) by the request level setting register (ELVR) is detected
at the DTP/external interrupt pin, the bits ER7 to ER0 of the DTP/interrupt source Register
(EIRR) are set to "1". In such case, when the enable bit for interrupt requests in the DTP/
interrupt enable register is set to "enable" (ENIR: EN7 to EN0=1), generation of an interrupt
source is reported to the interrupt controller. The interrupt controller determines the interrupt
level (ICR: IL2 to IL0) with regard to interrupt requests received from other peripheral functions
and the interrupt priority (when multiple interrupts are issued at the same time). The CPU also
checks the interrupt level mask register (PS: ILM2 to ILM0), interrupt level, and interrupt enable
bit (PS: CCR=1).
When an interrupt request is accepted by the CPU, an interrupt-handling microprogram is run in
internal CPU operation to branch to an interrupt-handling routine.
The interrupt-handling routine sets the corresponding flag bit for interrupt request to "0" to clear
the interrupt request.
Notes:
The ER bit is set to "1" regardless of the state of the corresponding EN bit when the DTP/
external interrupt start source occurs.
When the interrupt routine starts, the ER bit that was the start source is cleared. If the ER bit
remains set to "1", processing cannot return from the interrupt. In such case, be sure not to
unconditionally clear a flag bit other than that for the interrupt source.
323
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.5.2 DTP Function
The DTP/external interrupt circuit has a DTP function that detects a signal from the
external peripheral unit at the DTP/external interrupt pin to start the extended
intelligent I/O service.
■ Operation of DTP Function
The DTP function detects a data transfer request signal from an external peripheral unit, then
automatically transfers data between memory and the peripheral unit.
An external interrupt function (level detection) will start the extended intelligent I/O service
(EI2OS). This function operates in the same way as an external interrupt function (before the
CPU receives an interrupt request). When EI2OS operation is allowed (ICR: ISE=1), EI2OS
starts up when the interrupt request is accepted to start data transfer.
When data transfer ends, the descriptor is updated, the flag bit for interrupt request is cleared,
and the pin is ready to receive the next request. EI2OS completes all transfers, then branches to
the interrupt-handling routine.
Figure 15.5-3 "Example of interface with external peripheral unit" shows an example of the
interface used between memory and an external peripheral unit.
324
15.5 Operation of the DTP/External Interrupt Circuit
Figure 15.5-3 Example of interface with external peripheral unit
Input to INT0 pin
(DTP factor)
H level request (ELVR:LB0, LA0=01B)
CPU-internal operation
Descriptor
(microprogram)
selection/reading
Descriptor update
Read address
Address bus pin
Write address
Read data
Data bus pin
Write data
Read signal
Write signal
*1
Peripheral
unit externally
connected
Internal data bus
Write operation *3
Register
Read operation *1
Data transfer
request
DTP factor*2
INT DTP/external
interrupt
circuit
Interrupt
request
CPU
(EI2OS)
Internal
memory
*1,*2 : Cancelled within three machine clocks after transfer starts.
*3
: If the extended intelligent I/O service performs a transfer of the type "Peripheral
Memory".
Note:
The external peripheral unit must clear the level of the data transfer request signal (DTP
factor) within three machine clocks after initial transfer starts.
325
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.6 Notes on Using the DTP/External Interrupt Circuit
This section provides notes on the signals input to the DTP/external interrupt circuit,
and explains how to clear standby mode and interrupts.
■ Notes on using the DTP/External Interrupt Circuit
❍ Conditions for peripheral units externally connected when using the DTP function
The DTP function supports only externally connected peripheral units that automatically cancel
a data transfer request after data transfer. Unless a transfer request is cancelled within three
machine cycles after transfer operation starts, the DTP/external interrupt circuit assumes that a
new transfer request has been generated.
❍ Input polarity of external interrupts
When the request level setting register (ELVR) is set to "detect edges", the pulse width for
detecting an edge must be at least three machine clocks. When set to "detect level" and a level
that is valid as interrupt source is input, the source flip-flop in the DTP/interrupt source Register
(EIRR) is set to "1" and the source is held as shown in Figure 15.6-1 "Clearing the source hold
circuit when setting a level". Therefore, even if the source is cleared, the request to the interrupt
controller remains valid as long as the device remains in interrupt request output enabled state.
To cancel a request to the interrupt controller, clear the external flag bit for interrupt requests to
clear the source flip-flop, as shown in Figure 15.6-2 "Relationship between DTP/external
interrupt sources and interrupt requests with interrupt request output enabled".
Figure 15.6-1 Clearing the source hold circuit when setting a level
DTP/external
interrupt source
DTP/interrupt
input detection
circuit
Source flip-flop
(EIRR register)
Enable state
To interrupt controller
(interrupt request)
Keeps the source unless cleared
Figure 15.6-2 Relationship between DTP/external interrupt sources and interrupt requests with interrupt
request output enabled
DTP/external interrupt
source
(at H level detection)
Interrupt source cleared
Interrupt request to
interrupt controller
Inactivated by clearing source flip-flop
326
15.6 Notes on Using the DTP/External Interrupt Circuit
❍ Notes on interrupts
When the external interrupt function is active, the external flag bit for interrupt requests is set to
"1," and interrupt request output is enabled, processing cannot return from interrupt handling.
Always clear the external flag bit for interrupt requests in the interrupt-handling routine. When
the DTP function is active, EI2OS automatically clears this flag. When a level interrupt is
detected, the external flag bit for interrupt requests is immediately set again, even if it was
already cleared, as long as the level that caused the interrupt is kept. Set interrupt request
output to "disabled" or clear the interrupt source as required.
❍ CAN WAKE UP function
When the CAN WAKE UP function is used, the INT0 function cannot be used since the internal
connection to the INT0 and RX pins is switched.
327
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
15.7 Sample Programs for the DTP/External Interrupt Circuit
Sample programs for the external interrupt function and DTP function are listed below.
■ Sample Program for External Interrupt Function
❍ Specification of processing
The function detects the leading edge of pulses input to the INT0 pin to generate an external
interrupt.
[Coding example]
ICR02
; Interrupt control register for DTP/external
; interrupt circuit
DDR5
EQU
000015H
; Port 5 direction register
ENIR
EQU
000030H
; DTP/interrupt enable register
EIRR
EQU
000031H
; DTP/interrupt source register
ELVRL EQU
000032H
; Request level set register
ELVRH EQU
000033H
; Request level set register
ER0
EQU
EIRR:0
; Flag bit for INT0 interrupt
EN0
EQU
ENIR:0
; Enable bit for INT0 interrupt
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;
:
; Stack pointer (SP) already initialized
MOV
I:DDR5, #00000000B ; DDR5 set to "input"
AND
CCR,#0BFH
; Interrupt disabled
MOV
I:ICR02, #00H
; Interrupt level 0 (highest), EI2OS disabled
CLRB
EN0
; ENIR disables INT0
MOV
I:ELVR, #00000010B ; INT0 selects "leading edge"
CLRB
I:ER0
; EIRR clears INT0 factor
SETB
I:EN0
; ENIR enables INT0
MOV
ILM, #07H
; ILM in PS set to level 7
OR
CCR, #40H
; Interrupt enabled
LOOP: MOV
A,#00H
; Infinite loop
MOV
A,#01H
BRA
LOOP
;----------Interrupt program------------------------------------------------WARI:
CLRB
ER0
; Interrupt request flag cleared
;
:
;
User processing
;
:
RETI
; Return from interrupt
CODE
ENDS
328
EQU
0000B2H
15.7 Sample Programs for the DTP/External Interrupt Circuit
;----------Vector setting---------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFC0H
; Set the vector to interrupt #16 (10H)
DSL
WARI
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set Single-Chip mode
VECT
ENDS
END
START
329
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
■ Sample Program for DTP Function
❍ Specification of processing
Detects H level of the input signal input to the INT0 pin to activate channel 0 for the extended
intelligent I/O service (EI2OS).
DTP processing (EI2OS) outputs the data in RAM to port 0.
[Coding example]
ICR02
; Interrupt control register for DTP/external
; interrupt circuit
DR0
EQU
000010H
; Port 0 direction register
DDR5
EQU
000015H
; Port 5 direction register
ENIR
EQU
000030H
; DTP/interrupt enable register
EIRR
EQU
000031H
; DTP/interrupt source register
ELVRL EQU
000032H
; Request level set register
ELVRH EQU
000033H
; Request level set register
ER0
EQU
EIRR:0
; Flag bit for INT0 interrupt
EN0
EQU
ENIR:0
; Enable bit for INT0 interrupt
BAPL
EQU
000100H
; Lower bits of buffer address pointer
BAPM
EQU
000101H
; Middle bits of buffer address pointer
BAPH
EQU
000102H
; Upper bits of buffer address pointer
ISCS
EQU
000103H
; EI2OS status register
IOAL
EQU
000104H
; Lower bits of I/O address register
IOAH
EQU
000105H
; Lower bits of I/O address register
DCTL
EQU
000106H
; Lower bits of data counter
DCTH
EQU
000107H
; Lower bits of data counter
;----------Main program-----------------------------------------------------CODE
CSEG
START:
;
:
; Stack pointer (SP) already initialized
MOV
I:DDR0, #11111111B ; DDR0 set to "output"
MOV
I:DDR5, #00000000B ; DDR5 set to "input"
AND
CCR,#0BFH
; Interrupt disabled
MOV
I:ICR02, #08H
; Interrupt level 0 (highest)
; EI2OS enable, channel 0
MOV
BAPL,#00H
; Set output data address
MOV
BAPM,#06H
;
MOV
BAPH,#00H
;
MOV
ISCS,#12H
; byte transfer, I/O address fixed
MOV
IOAL,#00H
; As transfer destination address
MOV
IOAH,#00H
; pointer, specify port 0 (PDR0)
MOV
DCTL,#0AH
; Transfer count: 10 times
MOV
DCTH,#00H
;
CLRB
I:EN0
; ENIR disables INT0
MOV
I:ELVR, #00000001B ; INT0 selects "H" level
CLRB
I:ER0
; EIRR clears INT0 factor
SETB
I:EN0
; ENIR enables INT0
MOV
ILM, #07H
; ILM in PS set to level 7
OR
CCR, #40H
; Interrupt enabled
LOOP: MOV
A,#00H
; Infinite loop
MOV
A,#01H
;
BRA
LOOP
;
330
EQU
0000B2H
15.7 Sample Programs for the DTP/External Interrupt Circuit
;----------Interrupt program------------------------------------------------WARI:
CLRB
I:ER0
; Interrupt request flag cleared Channel
; switch and transfer address changed
; as required
;
User processing
; To end EI2OS, prohibit also interrupts
RETI
; Return from interrupt
CODE
ENDS
;----------Vector setting---------------------------------------------------VECT
CSEG
ABS=0FFH
ORG
0FFC0H
; Set the vector to interrupt #16 (10H)
DSL
WARI
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set to single-chip mode
VECT
ENDS
END
START
331
CHAPTER 15 DTP/EXTERNAL INTERRUPT CIRCUIT
332
CHAPTER 16
8/10-BIT A/D CONVERTER
This chapter describes the functions and operations of the 8/10-bit A/D converter.
16.1 "Overview of 8/10-Bit A/D Converter"
16.2 "Configuration of 8/10-Bit A/D Converter"
16.3 "Pins of 8/10-Bit A/D Converter"
16.4 "Registers of 8/10-Bit A/D Converter"
16.5 "Interrupts of 8/10-Bit A/D Converter"
16.6 "Operation of 8/10-Bit A/D Converter"
16.7 "Notes on Using the 8/10-Bit A/D Converter"
16.8 "Sample Program 1 for the 8/10-Bit A/D Converter (Example of EI2OS
Start in Single Mode)"
16.9 "Sample Program 2 for the 8/10-Bit A/D Converter (Example of EI2OS
Start in Continuous Mode)"
16.10 "Sample Program 3 for the 8/10-Bit A/D Converter (Example of EI2OS
Start in Stop Mode)"
333
CHAPTER 16 8/10-BIT A/D CONVERTER
16.1 Overview of 8/10-Bit A/D Converter
The 8/10-bit A/D converter uses an RC sequential compare conversion method to
convert analog input voltage to a 10-bit or 8-bit digital value. The input signal is
selected from eight channels of analog input pins. Conversion can be started through
selection by: software, 16-Bit Reload Timer 1, or trigger input from an external pin.
■ Features of 8/10-Bit A/D Converter
This converter performs A/D conversion of analog voltage input to an analog input pin into a
digital value, and provides the following features:
•
Minimum conversion time of 6.13 µs (for 16-MHz machine clock, including sampling time)
•
Minimum sampling time of 3.75 µs (for 16-MHz machine clock)
•
Conversion scheme based on RC sequential conversion compare method using sample hold
circuit.
•
10-bit or 8-bit resolution selectable
•
Analog input pin selectable by program from eight channels
•
Interrupt request may be generated to start EI2OS at end of A/D conversion.
•
In interrupt enabled mode with an active conversion data protect function, no data loss
during continuous conversion.
•
Selection of conversion startup source by software, 16-bit reload timer 1 (leading edge), and
external trigger input (trailing edge).
Table 16.1-1 "Conversion modes of 8/10-bit A/D converter" lists the three types of conversion
mode.
Table 16.1-1 Conversion modes of 8/10-bit A/D converter
Conversion mode
Single conversion
Scan conversion
Single conversion
mode
Converts the channel (one
channel only) specified, then
ends.
Continuously converts multiple channels (up to
eight channels specified) once, then ends.
Continuous
conversion mode
Repeats the conversion of the
channel (one channel only)
specified
Continuously converts multiple channels (up to
eight channels specified) repeatedly.
Stop conversion
mode
Converts channel (one channel
only) once, then stops
temporarily to await next start.
Continuously converts multiple channels (up to
eight channels specified). Temporarily stops per
channel conversion to await next start.
334
16.1 Overview of 8/10-Bit A/D Converter
■ Interrupts of 8/10-Bit A/D Converter and EI2OS
Table 16.1-2 Interrupts of 8/10-bit A/D converter and EI2OS
Interrupt control register
Vector table address
Interrupt
number
Register name
Address
Lower bits
Upper bits
Bank
#32(20H)
ICR10
0000BAH
FFFF7CH
FFFF7DH
FFFF7EH
EI2OS
*
*: Can be used
335
CHAPTER 16 8/10-BIT A/D CONVERTER
16.2 Configuration of 8/10-Bit A/D Converter
The 8/10-bit A/D converter consists of the following eight circuit blocks:
• A/D Control Status Register (ADCS)
• A/D Data Register (ADCR)
• Decoder
• Analog Channel Selector
• Sample Hold Circuit
• D/A Converter
• Comparator
• Control Circuit
■ Block Diagram of 8/10-Bit A/D Converter
Figure 16.2-1 "Block diagram of 8/10-bit A/D converter" shows a block diagram of the 8/10-bit A/
D converter. A description of each circuit block follows.
Figure 16.2-1 Block diagram of 8/10-bit A/D converter
AVcc
AVRH
Avss
MPX
Input circuit
Comparator
F2MC-16LX bus
AN0
AN1
AN2
AN3
AN4
AN5
AN6
Sequential compare
register
D/A converter
AN7
Decoder
Sample &
hold circuit
A/D data register
ADCRH, L
A/D Control Status Register: High
A/D Control Status Register: Low
16-Bit Reload Timer 1
Timer start
P50/ADTG
Trigger start
ADCSH,L
Operation clock
Prescaler
336
16.2 Configuration of 8/10-Bit A/D Converter
❍ A/D control status register (ADCS)
Used to start by software, select the start trigger, conversion mode, and A/D conversion
channel, enable or disable interrupt requests, check the interrupt request state, and indicate
temporary stop and conversion modes.
❍ A/D data register (ADCR)
Used to store A/D conversion results and select the resolution for A/D conversion.
❍ Decoder
A circuit used to select an analog input pin to be used based on the settings of the ANE0 to
ANE2 and ANS0 to ANS2 bits of the A/D control status registers (ADCS).
❍ Analog channel selector
A circuit used to select the pins to use among eight analog input pins.
❍ Sample hold circuit
A circuit used to hold the input voltage selected by the analog channel selector. Holds a
sampling of input voltage soon after A/D conversion startups, then converts the input voltage of
A/D conversion mode (during compare operation) without variations in input voltage.
❍ D/A converter
Used to generate a reference value with which to compare the input voltage (held for sampling).
❍ Comparator
Compares a sample-holding input voltage with the D/A converter output voltage to determine
which is higher.
❍ Control circuit
Uses a comparison result signal from the comparator to determine the A/D conversion value.
When A/D conversion ends, conversion results are stored in the A/D data registers (ADCR) to
generate an interrupt request.
337
CHAPTER 16 8/10-BIT A/D CONVERTER
16.3 Pins of 8/10-Bit A/D Converter
This section describes the pins of the 8/10-bit A/D converter, and shows a block
diagram of these pins.
■ Pins of 8/10-bit A/D Converter
The pins of the A/D converter are shared with the general-purpose port. Table 16.3-1 "Pins of 8/
10-bit A/D converter" lists the pin functions, type of I/O mode, and settings for using the 8/10-bit
A/D converter.
Table 16.3-1 Pins of 8/10-bit A/D converter
Function
Pin name
Channel 0
P60/AN0
Channel 1
P61/AN1
Channel 2
P62/AN2
Channel 3
P63/AN3
Channel 4
P64/AN4
Channel 5
P65/AN5
Channel 6
P66/AN6
Channel 7
P67/AN7
338
Pin
function
Port 6 I/O
or analog
input
Type of I/O
CMOS output/
CMOS hysteresis
input, or analog
input
Pull-up
setting
None
Standby
control
None
Setting of I/O port
required for using
the pin
Set port 6 to "input"
(DDR6: bits 0 to
7=0). Set to analog
input (ADER: bits 0
to 7=1)
16.3 Pins of 8/10-Bit A/D Converter
■ Block Diagram of Pins of 8/10-Bit A/D Converter
Figure 16.3-1 "Block diagram of pins P60/AN0 to P67/AN7" shows a block diagram of the pins
of the A/D converter.
Figure 16.3-1 Block diagram of pins P60/AN0 to P67/AN7
ADER
Port data register (PDR)
Analog data
PDR read
Internal data bus
Output latch
PDR write
Pin
Port direction register (DDR)
Direction
latch
DDR write
DDR read
Standby control (SPL=1)
Notes:
•
For pins that are to be used as input ports, set the corresponding DDR6 register bit to "0"
and add a pull-up resistor to the external pin. Also, set the corresponding ADER register bit
to "0".
•
For pins that are to be used as analog input pins, set the corresponding ADER register bit to
"1". In this case, the value returned in read operations of the PDR6 register is "0".
339
CHAPTER 16 8/10-BIT A/D CONVERTER
16.4 Registers of 8/10-Bit A/D Converter
This section lists the 8/10-bit A/D converter registers.
■ List of 8/10-Bit A/D Converter Registers
Figure 16.4-1 "Registers of 8/10-bit A/D converter" lists the registers of the 8/10-bit A/D
converter.
Figure 16.4-1 Registers of 8/10-bit A/D converter
15 14 13 12 11 10
8
7
6
5
4
3
ADER
001Ah
340
9
0021h/0020h
ADCSH
ADCSL
0023h/0022h
ADCRH
ADCRL
2
1
0
16.4 Registers of 8/10-Bit A/D Converter
16.4.1 Upper Bits of A/D Control Status Register (ADCSH)
The upper bits of the control status register (ADCSH) can be used for starting by
software, selecting a start trigger, enabling or disabling interrupt requests, checking
the interrupt request state, and checking for temporary stop and conversion being
performed.
■ Upper Bits of A/D Control Status Register (ADCSH)
Figure 16.4-2 "Bit configuration of upper bits of A/D control status register (ADCSH)" shows the
bit configuration of the A/D Control Status Register: High (ADCSH); Table 16.4-1 "Description of
bit functions in the upper 8 bits of the A/D control status register (ADCSH)" lists the functions of
each bit.
Figure 16.4-2 Bit configuration of upper bits of A/D control status register (ADCSH)
Address
000021 H
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
BUSY
INT
INTE PAUS STS1 STS0 STRT RESV
R/W
R/W
R/W
R/W
R/W
R/W
W
bit0 Initial value
bit7
(ADCSL)
00000000 B
R/W
Reserved bit
RESV
Always set this bit to "0".
STRT
A/D conversion startup bit
(valid only for start by software )
0
1
A/D conversion function has not started
A/D conversion function has started
STS1STS0
0
0
1
0
0
1
1
1
PAUS
0
1
Selection bit for A/D start source
Start by software
Start by trigger or software
Start by timer or software
Start by trriger, timer or software
Flag bit for temporary stop
(valid only when using EI2OS)
No temporary stop occurs in A/D conversion.
Temporary stop occurs in A/D conversion.
INTE
Interrupt request bit
0 Output of interrupt requests prohibited
1 Output of interrupt requests allowed
INT
0
1
BUSY
0
R/W : Reading and writing permitted
W : Write only
: Initial value
1
Flag bit for interrupt requests
At reading
At writing
A/D conversion
(has not ended)
A/D conversion
(has ended)
Clear the bit.
Does not change and
has no effect
Conversion mode bit
At reading
At writing
Forced stop of A/D
conversion
Does not change and has
A/D conversion mode no effect
A/D conversion stop
mode
341
CHAPTER 16 8/10-BIT A/D CONVERTER
Table 16.4-1 Description of bit functions in the upper 8 bits of the A/D control status register (ADCSH)
Bit name
Function
bit15
BUSY:
Conversion mode bit
•
•
Indicates A/D conversion in progress.
When this bit is "0" during reading, A/D conversion has stopped.
When this bit is"1"during reading, A/D conversion is in progress.
• Clearing this bit by writing"0"will forcibly stop A/D conversion.
Setting this bit to "1" by writing has no effect.
Note:
Forced stop and software start (BUSY=0, STRT=1) must not be
performed at the same time.
bit14
INT:
Flag bit for interrupt
requests
•
"1" if the result of A/D conversion has been stored in the A/D
data register.
• When this bit and the interrupt request enable bit (ADCSH:
INTE) are both set to "1", an interrupt request is generated.
When EI2OS is enabled, EI2OS will start in this case.
• Writing"0" will clear this bit while writing "1" has no effect.
• This bit is cleared at EI2OS startup.
Note:
Clear this bit by writing "0" only when A/D conversion is stopped.
bit13
INTE:
Enable bit for interrupt
requests
•
•
•
342
Enables or disables issuing interrupts to the CPU.
When this bit and the flag bit for interrupt requests (ADCSH:
INT) are both set to "1", an interrupt request is generated.
Set this bit to "1" when using EI2OS.
bit12
PAUS:
Flag bit for temporary
stop
•
•
This bit is "1" if A/D conversion stops temporarily.
This A/D converter has only one A/D data register. If reading the
previous conversion results by the CPU is not completed in
continuous conversion mode, writing new conversion results will
result in a loss of the results from the previous conversion.
Therefore, when using continuous conversion mode, it is in
ordinary cases necessary to make the required settings so that
the conversion results are automatically transferred to memory
by EI2OS upon the completion of each conversion. With multiple
interrupts, however, transferring conversion data may not be
completed before the start of the next conversion. This bit
provides a function in consideration of such cases: this bit is set
to "1" for the time after conversion until EI2OS has transferred
the conversion result so as to stop A/D conversion and inhibiting
storing the next conversion result. After the data has been
transferred by EI2OS, A/D conversion will automatically be
started again.
Note:
This bit is only valid when using EI2OS.
bit11
bit10
STS1, STS0:
Selection bit for A/D
conversion start
source
•
•
Selects a start source for A/D conversion.
When there is more than one start source, only the first start
factor will start conversion.
Note:
The start source will change immediately at the time it is
rewritten. Therefore, rewrite the A/D conversion start source
only when the corresponding start source is currently not
applicable.
16.4 Registers of 8/10-Bit A/D Converter
Table 16.4-1 Description of bit functions in the upper 8 bits of the A/D control status register (ADCSH)
Bit name
Function
bit9
STRT:
A/D conversion startup
bit 14
• Starts A/D conversion by software.
• Set this bit to "1" to start A/D conversion.
• Setting this bit will not cause restart in stop conversion mode.
Note:
Do not use a forced stop and software start (BUSY=0, STRT=1)
at the same time.
bit8
RESV:
Reserved bit
Note:
Always set this bit to "0".
343
CHAPTER 16 8/10-BIT A/D CONVERTER
16.4.2 Lower bits of A/D Control Status Register (ADCSL)
The lower bits of the A/D control status register (ADCSL) are used to select the
conversion mode and A/D conversion channel.
■ Lower bits of the A/D control status register (ADCSL)
Figure 16.4-3 "Bit configuration of lower bits of A/D control status register (ADCSL)" shows the
bit configuration of the lower bits of the A/D control status register (ADCSL); Table 16.4-2
"Description of functions of lower bits of the A/D control status register (ADCSL)" lists the
functions of each bit.
Figure 16.4-3 Bit configuration of lower bits of A/D control status register (ADCSL)
bit15
Address
000020H
bit8 bit7
ADCSH
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 0 0 0 0 0 0 0 0 B
R/W R/W R/W R/W R/W R/W R/W R/W
ANE2 ANE1 ANE0 Channel selection bit for A/D conversion end
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
Channel selection bit for A/D conversion start
Reading
ANS2 ANS1 ANS0 Stop mode Reading
during temporary
during
conversion stop of conversion
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
MD1 MD0
R/W : Reading and writing permitted
: Initial value
344
AN0 pin
AN1 pin
AN2 pin
AN3 pin
AN4 pin
AN5 pin
AN6 pin
AN7 pin
Channel
number
during
conversion
Channel number
of conversion
performed
immediately before
Mode selection bit for A/D conversion
0
0
Single conversion mode 1 (restart during operation allowed)
0
1
Single conversion mode 2 (restart during operation prohibited)
1
0
Continuous conversion mode (restart during operation prohibited)
1
1
Stop convert mode (restart during operation prohibited)
16.4 Registers of 8/10-Bit A/D Converter
Table 16.4-2 Description of functions of lower bits of the A/D control status register (ADCSL)
Bit name
Function
bit7
bit6
MD1, MD0:
Mode selection bit for A/D
conversion
•
Selects the conversion mode when using the A/D
conversion function.
• Based on the 2-bit value of MD1 and MD0, either single
conversion mode 1, single conversion mode 2, continuous
conversion mode, or stop conversion mode is selected.
• The different modes work as follows:
Single Conversion Mode 1: A/D conversion is performed
continuously, but only once from setting channel ANS2 ANS0 to setting channel ANE2 - ANE0. Restart during
operation is allowed.
Single conversion mode 2: A/D conversion is performed
continuously, but only once from setting channel ANS2 ANS0 to setting channel ANE2 - ANE0. Restart during
operation is prohibited.
Continuous conversion mode: Repeats A/D conversion
continuously from setting channel ANS2 - ANS0 to setting
channel ANE2 - ANE0 until forcibly stopped by the BUSY bit.
Restart during operation is prohibited.
Stop conversion mode: Repeats A/D conversion from setting
channel ANS2 - ANS0 to setting channel ANE2 - ANE0 with
a temporary stop for each channel until a forced stop by the
BUSY bit is performed. Restart during operation is prohibited.
Restart in temporary stop mode is triggered by a source that
is selected by the STS1/0 bits.
Note:
Restart during single, continuous, or stop mode
conversion is performed in response to an external trigger
and by software.
bit5
bit4
bit3
ANS2, ANS1,ANS0:
Channel selection bit for
starting A/D conversion
•
•
•
bit2
bit1
bit0
ANE2, ANE1, ANE0:
Channel selection bit for A/D
conversion end
•
•
•
Used to specify the start channel for A/D conversion and
check the channel number during conversion.
Starts A/D conversion from the channel indicated by these
bits as soon as A/D conversion starts.
Can be used to identify the number of the channel being
converted during A/D conversion. In case of temporary
stop during stop conversion mode, the number of the
channel that was subject to conversion immediately
before can be identified by reading these bits.
Used to set the end channel for A/D conversion.
Starts and performs A/D conversion till the channel
specified in these bits has been reached.
By setting the same channels as in ANS2 to ANS0, only
those specific channels are converted. When either
continuous conversion mode or stop conversion mode is
set, conversion is performed until the channel specified by
these bits is reached; afterwards, conversion starts again
with the channels specified in ANS2 to ANS0. If the
channels are specified in such a way that "start channel >
end channel" applies, conversion is performed from the
start channel to AN7, then from AN0 to the end channel,
which concludes one phase of conversion.
345
CHAPTER 16 8/10-BIT A/D CONVERTER
16.4.3 A/D Data Registers (ADCRH/ADCRL)
The A/D Data Registers (ADCRH/ADCRL) are used to store A/D conversion results and
select the resolution for A/D conversion.
■ A/D Data Registers (ADCRH/ADCRL)
Figure 16.4-4 "Bit configuration of A/D data register (ADCRH/ADCRL)" shows the bit
configuration of the A/D Data Registers (ADCRH/ADCRL); Table 16.4-3 "Functions of lower bits
of A/D data register (ADCR)" lists the functions of the individual bits.
Figure 16.4-4 Bit configuration of A/D data register (ADCRH/ADCRL)
000023h/
000022h
Bit15
Bit14
S10
ST1
W
W
Bit10
Initial value
Bit13 Bit12
Bit11
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ST0
CT1
CT0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
00101XXXB
W
W
W
R
R
R
R
R
R
R
R
R
R
XXXXXXXX
B
AD data bit
D0 to D9
Conversion data
CT1 CT0
0
0
0
1
1
0
1
1
ST1 ST0
44 machine cycles (5.50
66 machine cycles (4.12
88 machine cycles (5.50
176 machine cycles (11.0
s@8MHz)
s@16MHz)
s@16MHz)
s@16MHz)
Setting bit for sampling time
0
0
0
1
1
0
20 machine cycles (2.5 s@8MHz)
32 machine cycles (2.0 s@16MHz)
48 machine cycles (3.0 s@16MHz)
1
1
128 machine cycles (8.0 s@16MHz)
S10
346
Compare time set bit
A/D data bit
0
10-bit resolution mode (D9 to D0) ( D9 to D0)
1
8-bit resolution mode (D7 to D0) ( D7 to D0)
16.4 Registers of 8/10-Bit A/D Converter
Table 16.4-3 Functions of lower bits of A/D data register (ADCR)
Bit name
Function
bit15
S10: Resolution selection bit
for A/D conversion
•
•
Used to select the resolution for A/D conversion.
Set this bit to "0" to select 10-bit resolution; set it to"1" to
select 8-bit resolution.
Note:
The resolution determines the data bits used.
bit14
bit13
ST1, ST0:
Setting bits for sampling time
•
•
bit12
bit11
CT1, CT0:
Compare time setting bits
•
•
bit10
Empty bit
−
bit9 to bit0
D9-D0
•
Used to select the sampling time for A/D conversion.
These bits allow analog input to obtain the sampling time
when A/D conversion starts.
Note:
When these bits are set to "00" (for 8 MHz) in 16-MHz
operation, it may not be possible to read in a correct
analog voltage.
Used to select the compare time for A/D conversion.
After the time specified in these bits (the sampling time)
has elapses after analog input has been started, it is
determined that the end result of conversion has been
obtained, and the result is stored in bits 9 - 0 of this
register.
Note:
When these bits are set to "00" (for 8 MHz) in 16-MHz
operation, it may not be possible to read in a correct
analog voltage.
Stores the result of A/D conversion. This area is
overwritten each time conversion has been completed.
• Stores in ordinary cases the final conversion result
The initial value of this register is undefined.
Note:
This device has a conversion data protect function (see
16.6 "Operation of 8/10-Bit A/D Converter")
Do not overwrite this bit while A/D conversion is in
progress.
Notes:
•
The S10-bits must be rewritten if A/D operation stops before conversion ends. Rewriting
after conversion may result in an undefined ADCR data.
•
To read ADCR with 10-bit mode specified, always use a word move instruction (e.g., MOVW
A, 0022H).
347
CHAPTER 16 8/10-BIT A/D CONVERTER
16.5 Interrupts of 8/10-Bit A/D Converter
The 8/10-bit A/D converter generates an interrupt request by setting data in the A/D
data register for A/D conversion. It also supports the extended intelligent I/O service
(EI2OS).
■ Interrupts of 8/10-Bit A/D Converter
Table 16.5-1 "Control bits and interrupt sources for 8/10-bit A/D converter" lists the control bits
and interrupt sources for the 8/10-bit A/D converter.
Table 16.5-1 Control bits and interrupt sources for 8/10-bit A/D converter
8/10-bit A/D converter
Flag bit for interrupt requests
INT bit of ADCSH
Enable bit for interrupt requests
INTE bit of ADCSH
Interrupt source
Writing A/D conversion results to A/D data register
If A/D conversion has started and A/D conversion results are stored in ADCR, the INT bit in the
upper bits of the A/D control status register (ADCSH) is set to "1". When interrupt requests are
enabled (ADCSH: INTE=1), an interrupt request is output to the interrupt controller in this case.
■ Interrupts of 8/10-Bit A/D Converter and EI2OS
Table 16.5-2 "Interrupts of 8/10-bit A/D converter and EI2OS" shows the correspondence
between 8/10-bit A/D converter interrupt, interrupt control registers that can use EI2OS and the
address of the vector table).
Table 16.5-2 Interrupts of 8/10-bit A/D converter and EI2OS
Interrupt control register
Interrupt
number
#32(20H)
Vector table address
Register
name
Address
Lower bits
Upper bits
Bank
ICR10
0000BAH
FFFF7CH
FFFF7DH
FFFF7EH
EI2OS
*
*: Available
■ EI2OS Function of 8/10-Bit Converter
The 8/10-bit A/D converter uses the EI2OS function to transfer A/D conversion results to
memory. In this case, until the conversion data protect function operates, A/D conversion data is
transferred to memory, and the INT bit is cleared, A/D conversion temporarily stops to prevent
data loss.
348
16.6 Operation of 8/10-Bit A/D Converter
16.6 Operation of 8/10-Bit A/D Converter
The 8/10-bit A/D converter has three modes: single conversion mode, continuous
conversion mode, and stop conversion mode. This section describes the operation of
each mode.
■ Operation of Single Conversion Mode
Single conversion mode sequentially converts the signals from analog input (specified by the
ANS and ANE bits). When conversion is completed up to the end channel specified by the ANE
bit, A/D conversion will stop. If the start channel and end channel are the same (ANS = ANE),
only one channel specified by the ANS bit is converted. To operate in single conversion mode,
the settings shown in Figure 16.6-1 "Settings in single conversion mode" are required.
Figure 16.6-1 Settings in single conversion mode
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
ADCS
ADCR
BUSY INT
INTE PAUS STS1 STS0 STRT
Bit8
Reserved
S10 ST1 ST0 CT1 CT0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
Stores conversion data
ADER
: Bit used
: The bit corresponding to the pin used is set to "1"
0 : Set to "0"
An example of the conversion order in single conversion mode is shown below.
When ANS=000B, ANE=011B: AN0 --> AN1 --> AN2 --> AN3 --> End
When ANS=110B", ANE=010B: AN6 --> AN7 --> AN0 --> AN1 --> AN2 --> End
When ANS=011B, ANE=011B: AN3 --> End
■ Operation of Continuous Conversion Mode
In continuous conversion mode, signals from analog input as specified by the ANS and ANE bits
is sequentially converted. When conversion ends with the end channel specified in the ANE bit,
A/D conversion starts again with the first analog input specified in the ANS bit. When the start
channel and end channel are the same (ANS = ANE), conversion is repeated for all channels
specified by ANS. To operate in continuous conversion mode, the settings shown in Figure
16.6-2 "Settings in continuous conversion mode" are required.
349
CHAPTER 16 8/10-BIT A/D CONVERTER
Figure 16.6-2 Settings in continuous conversion mode
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
ADCS BUSY INT INTE PAUS STS1 STS0 STRT
ADCR
Bit8 Bit7
Repeated
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
Conversion data is stored
S10 ST1 ST0 CT1 CT0
ADER
: Bit used
: The bit corresponding to the pin used is set to "1"
1 : Set to "1"
0 : Set to "0"
An example of the conversion order in continuous conversion mode is shown below.
When ANS=000B, ANE=011B: AN0 --> AN1 --> AN2 --> AN3 --> AN0 --> Reserved
When ANS=110B, ANE=010B: AN6 --> AN7 --> AN0 --> AN1 --> AN2 --> AN6 --> Reserved
When ANS=011B, ANE=011B: AN3 --> AN3 --> Reserved
■ Operation in Stop Conversion Mode
In stop conversion mode, signals from analog input as specified by the ANS and ANE bits is
converted for each channel using a temporary stop operation. When conversion ends at the end
channel specified by the ANE bit, A/D conversion will stop temporarily and then restart with the
first analog input specified by the ANS bit. When the start channel and end channel are the
same (ANS = ANE), conversion is repeated for all channels specified by the ANS bit. To restart
conversion after a temporary stop, the start source specified by the STS1/0 bits must be
generated. To operate in stop conversion mode, the settings shown in Figure 16.6-3 "Settings in
stop conversion mode" are required.
Figure 16.6-3 Settings in stop conversion mode
Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9
ADCS BUSY INT INTE PAUS STS1 STS0 STRT
ADCR
S10
ST1
ST0
CT1
CT0
Bit8 Bit7
Reserved
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0
Conversion data is stored
ADER
: Bit used
: The bit corresponding to the pin used is set to "1"
1 : Set to "1"
0 : Set to "0"
An example of the conversion order in stop conversion mode is shown below.
When ANS=000B, ANE=011B: AN0 --> temporary stop --> AN1 --> temporary stop --> AN2 -->
temporary stop --> AN0 --> repeated
When ANS=110B, ANE=001B: AN6 --> temporary stop --> AN7 --> temporary stop --> AN0 -->
temporary stop --> AN1 --> temporary stop --> AN6 --> repeated
When ANS=011B, ANE=011B: AN3 --> temporary stop --> AN3 --> temporary stop --> repeated
350
16.6 Operation of 8/10-Bit A/D Converter
16.6.1 Conversion Operation Using EI2OS
The 8/10-bit A/D converter uses EI2OS to transfer A/D conversion results to memory.
■ Conversion Operation using EI2OS
Figure 16.6-4 "Flowchart of operation using EI2OS" shows a flowchart of operation when using
EI2OS.
Figure 16.6-4 Flowchart of operation using EI2OS
Start of A/D conversion
Sample hold
EI2OS startup
Conversion
Data transfer
Conversion end
Specified
number of transfers
completed? *1
YES
Interrupt handling
NO
Interrupt generated
Interrupt cleared
*1: Determined with EI2OS.
Using EI2OS allows the using the conversion data protect function to transfer multiple items of
data to memory without data loss, even if multiple items of data are converted.
351
CHAPTER 16 8/10-BIT A/D CONVERTER
16.6.2 A/D Conversion Data Protect Function
The conversion data protect function operates when A/D conversion is executed in
interrupt enabled state.
■ A/D conversion data protect function
This A/D converter uses only one data register for storing conversion data. The data in this
register will be overwritten after A/D conversion ends. Therefore, some of the previous data may
be lost if transfer of conversion data to memory is delayed. To avoid this, the data protect
function can be used when interrupts are enabled (INTE=1). It works as described below.
❍ Data protect function without using EI2OS
When conversion data is stored in the A/D data register (ADCR), the INT bit of the upper bits of
the A/D control status register (ADCSH) is set to "1". While the INT bit is "1", A/D conversion is
temporarily stopped. After the contents of the A/D data register (ADCR) are transferred to
memory, the stop state will be released by clearing the INT bit from within the interrupt routine.
❍ Data protect function using EI2OS
By specifying continuous conversion with EI2OS, the PAUS bit of the upper bits in the A/D
control status register will be set to "1" at the end of conversion. This setting remains until
EI2OS completes the transfer of conversion data from the data register to memory. During this
time, A/D conversion stops an no new conversion data is stored. After data transfer to memory
has been completed, the PAUS bit is cleared to "0" and conversion operation starts again.
Figure 16.6-5 "Flowchart of data protect function operation using EI2OS" shows a flowchart of
data protect function operation using EI2OS.
352
16.6 Operation of 8/10-Bit A/D Converter
Figure 16.6-5 Flowchart of data protect function operation using EI2OS
Making EI2OS settings
Continuous A/D conversion
started
One-time conversion
completed
Storing result in data register
Start of EI2OS
Second conversion completed
Has EI2OS ended?
NO
Temporary stop of A/D
conversion
YES
Storing result in data register
Third conversion
EI2OS startup
Continued
All conversions completed
Continued
Storing result in data register
Start of EI2OS
Interrupt handling routine
A/D initialization or stop
End
Note: A flowchart for stopping A/D converter operation was omitted here.
Notes:
•
The conversion data protect function is only effective in the interrupt enabled (ADCSH:
INTE=1) state.
•
When A/D conversion temporarily stops during EI2OS operation and interrupts are disabled,
new data will be written before transferring the old data of A/D conversion. The previous data
will be lost after restart from temporary stop mode.
•
Wait data will be lost after restart from temporary stop mode.
353
CHAPTER 16 8/10-BIT A/D CONVERTER
16.7 Notes on Using the 8/10-Bit A/D Converter
This section provides notes on using the 8/10-bit A/D converter.
■ Notes on using 8/10-Bit A/D Converter
❍ Analog input pin
The A/D input pin is also used as I/O pin of port 6. Its use is switched using the port 6 direction
register (DDR6) and analog input enable register (ADER). For setting the port to "input", set the
bit in DDR6 that corresponds to the pin for analog input to "0", set ADER to "analog input mode
" (ADEx=1), and determine the input gate for the port. If a medium level signal is input in port
input mode (ADEx=0), input leakage current will flow to the gate.
❍ Notes on using the internal timer (16-bit reload timer 1)
When the A/D converter is started by the internal timer, according to the specification in the
STS1, STS0 bits among the upper bits in the A/D control status register (ADCSH), make sure
the input of the internal timer is set to the inactive side (in case of the internal timer, to "L").
When the input is set to the active side, operation may start when data is written to ADCSH.
❍ Order of supplying power and analog input to the A/D converter
Power (AVCC, AVRH) and analog input (AN0 to AN7) to the A/D converter must be supplied
either after turning on the digital power supply (VCC) or simultaneously with turning it on. For
powering off, first turn off A/D converter power and analog input, then the digital power supply
(VCC), or turn off everything simultaneously.
❍ Supply voltage of A/D converter
To avoid a latch-up, the voltage of the A/D converter power supply (AVCC) must not exceed the
voltage of the digital power supply (VCC).
354
16.8 Sample Program 1 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Single Mode)
16.8 Sample Program 1 for the 8/10-Bit A/D Converter (Example
of EI2OS Start in Single Mode)
The following shows a sample program for starting A/D conversion processing in
single conversion mode by EI2OS.
■ Sample Program for Start in Single Conversion Mode by EI2OS
❍ Specification of processing
Converts analog inputs AN1 to AN3, then ends.
Conversion data is transferred in order of addresses 200H to 205H.
Uses 10-bit resolution.
The start is triggered by software.
Figure 16.8-1 "Operational flow of starting conversion processing in single conversion mode by
EI2OS" shows the operational flow of the program in which conversion in single conversion
mode is started by EI2OS.
Figure 16.8-1 Operational flow of starting conversion processing in single conversion mode by EI2OS
Start
AN1
Interrupt
EI 2OS transfer
AN2
Interrupt
EI 2OS transfer
AN3
Interrupt
EI 2OS transfer
End
Interrupt sequence
Parallel
processing
355
CHAPTER 16 8/10-BIT A/D CONVERTER
[Coding example]
BAPL
EQU
000100H
; Buffer address pointer (lower bits)
BAPM
EQU
000101H
; Buffer address pointer (middle bits)
BAPH
EQU
000102H
; Buffer address pointer (upper bits)
ISCS
EQU
000103H
; EI2OS status register
IOAL
EQU
000104H
; Lower bits of I/O address register
IOAH
EQU
000105H
; Upper bits of I/O address register
DCTL
EQU
000106H
; Data counter (lower bits)
DCTH
EQU
000107H
; Data counter (upper bits)
DDR6
EQU
000016H
; Port 6 direction register
ADER
EQU
00001AH
; Analog input enable register
ICR10 EQU
0000BAH
; A/DC interrupt control register
ADCSL EQU
000020H
; A/D control status register
ADCSH EQU
000021H
;
ADCRL EQU
000022H
; A/D data register
ADCRH EQU
000023H
;
;----------Main program--------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
AND
CCR, #0BFH
; Disable interrupts
MOV
ICR10, #00H
; Interrupt level 0 (highest)
MOV
BAPL, #00H
; Specify the address to store conversion data
MOV
BAPM, #02H
; (Using 200H to 205H)
MOV
BAPH, #00H
;
MOV
ISCS, #18H
; Word data transfer, address after transfer+1,
; transfer I/O --> memory
MOV
IOAL, #22H
; Specify the address in the analog data
MOV
IOAH, #00H
; register by an address pointer to the
; transfer source
MOV
DCTL, #03H
; EI2OS transfer (three times), (same as
the conversion count)
MOV
DDR6, #11110001B
; Set input to P61 to P63
MOV
ADER, #00001110B
; Set analog input to P61/AN1 to P63/AN3
MOV
DCTH, #00H
;
MOV
ADCSL, #0BH
; Single start, convert AN1 to AN3 CH
MOV
ADCSH, #0A2H
; Software start, A/D conversion start,
; interrupt enabled
MOV
ILM, #07H
; Set ILM in PS to level 7
OR
CCR, #40H
; Enable interrupts
LOOP: MOV
A,#00H
; Infinite loop
MOV
A,#01H
BRA
LOOP
;----------Interrupt program---------------------------------------------------ED_INT1:
MOV
I:ADCSH, #00H
; A/D stop, clearing interrupt flag and
; disabling interrupts
RETI
; Return from interrupt
CODE
ENDS
;----------Vector settings-----------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FF7CH
; Set the vector to interrupt #32 (20H)
DSL
ED_INT1
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set to single-chip mode
VECT
ENDS
END
START
356
16.9 Sample Program 2 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Continuous Mode)
16.9 Sample Program 2 for the 8/10-Bit A/D Converter (Example
of EI2OS Start in Continuous Mode)
This section shows a sample program for A/D conversion processing by EI2OS start in
continuous conversion mode.
■ Sample Program for Start by EI2OS in Continuous Mode
❍ Specification of processing
Convert analog inputs AN3 to AN5 two times to obtain two data items for conversion per
channel.
Conversion data is transferred in order of addresses 600H to 60BH.
Uses 10-bit resolution.
Uses 16-Bit Reload Timer 1 to trigger the start of processing.
Figure 16.9-1 "Operational flow of program operation for start by EI2OS (in continuous mode)"
shows the operational flow of program operation for start by EI2OS (in continuous mode).
Figure 16.9-1 Operational flow of program operation for start by EI2OS (in continuous mode)
Start
AN3
Interrupt
EI 2OS
transfer
After 12 transfers
Stop
Interrupt sequence
External edge start
End
357
CHAPTER 16 8/10-BIT A/D CONVERTER
[Coding example]
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
DDR6
ADER
ICR10
; Buffer address pointer (lower bits)
; Buffer address pointer (middle bits)
; Buffer address pointer (Upper bits)
; EI2OS status register
; Lower bits of I/O address register
; Upper bits of I/O address register
; Data counter (lower bits)
; Data counter (upper bits)
; Port 6 direction register
; Analog input enable register
; Interrupt control register for A/D
; conversion (A/DC)
ADCSL
EQU
000020H
; Control status register for A/D conversion
ADCSH
EQU
000021H
;
ADCRL
EQU
000022H
; Data register for A/D conversion
ADCRH
EQU
000023H
;
TMCSR1L EQU
000054H
; Lower bits of timer control status register 1
TMCSR1H EQU
000055H
;
TMRLR1L EQU
000056H
; Reload register 1
TMRLR1H EQU
000057H
;
;----------Main program----------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
AND
CCR,#0BFH
; Disable interrupts
MOV
ICR10, #08H
; Interrupt level 0 (highest), interrupts
; enabled
MOV
BAPL, #00H
; Address setting for storing conversion data
MOV
BAPM, #06H
; (Using 600H to 60BH)
MOV
BAPH, #00H
;
MOV
ISCS, #18H
; Word transfer, address after transfer + 1,
; transfer I/O --> memory
MOV
IOAL, #22H
; Specify the transfer analog data
MOV
IOAH, #00H
; pointer address by a transfer source
; address register
MOV
DCTL, #06H
; 6 EI2OS transfers, transfers for 3ch x 2 times
MOV
DDR6, #00000000B ; Set P60 to P67 to input
MOV
ADER, #00111000B ; Set P63/AN3 to P65/AN5 to analog input
MOV
DCTH, #00H
;
MOV
ADCSL, #9DH
; Continuous mode, convert AN3 to AN5 CH
MOV
ADCSH, #0A8H
; 16-bit timer start, A/D conversion start,
interrupts enabled
MOVW TMRLR1L, #0320H
; Timer value set to 800 (320H), 100 µs
MOV
TMCSR1H, #00H
; Clock source set to 125 ns (with external
; trigger disabled)
MOV
TMCSR1L, #12H
; Timer output disabled, interrupts
; disabled, reload enabled
MOV
TMSCR1L, #13H
; 16 bit timer start
MOV
ILM, #07H
; Set ILM in PS to level 7
OR
CCR, #40H
; Interrupts enables
LOOP:
MOV
A,#00H
; Infinite loop
MOV
A,#01H
BRA
LOOP
358
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000016H
00001AH
0000BAH
16.9 Sample Program 2 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Continuous Mode)
;----------Interrupt program-----------------------------------------------------ED_INT1:
MOV
I:ADCSH, #80H
; A/D stopped, interrupt flag cleared and disabled
RETI
; Return from interrupt
CODE
ENDS
;----------Vector settings-------------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FF7CH
; Set the vector to interrupt #32 (20H)
DSL
ED_INT1
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set to single-chip mode
VECT
ENDS
END
START
359
CHAPTER 16 8/10-BIT A/D CONVERTER
16.10 Sample Program 3 for the 8/10-Bit A/D Converter (Example
of EI2OS Start in Stop Mode)
This section shows a sample program for A/D conversion processing by EI2OS startup
in stop mode.
■ Sample Program for EI2OS Startup in Stop Mode
❍ Specification of processing
Converts analog input AN3 12 times based on the specified interval.
Transfers conversion data in order of addresses 600H to 617H.
Uses 10-bit resolution.
Uses 16-Bit Reload Timer 1 to trigger startup.
Figure 16.10-1 "Flow of EI2OS startup program operation (in stop mode)" shows the operational
flow of EI2OS startup program operation (in stop mode).
Figure 16.10-1 Flow of EI2OS startup program operation (in stop mode)
Start
EI 2OS
transfer
Interrupt
AN3
After 12 transfers
Stop
Interrupt sequence
External edge start
End
[Coding example]
360
BAPL
BAPM
BAPH
ISCS
IOAL
IOAH
DCTL
DCTH
DDR6
ADER
ICR10
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
EQU
000100H
000101H
000102H
000103H
000104H
000105H
000106H
000107H
000016H
00001AH
0000B0H
ADCSL
ADCSH
ADCRL
ADCRH
EQU
EQU
EQU
EQU
000020H
000021H
000022H
000023H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Buffer address pointer (lower bits)
Buffer address pointer (middle bits)
Buffer address pointer (upper bits)
EI2OS status register
Lower bits of I/O address register
Upper bits of I/O address register
Data counter (lower bits)
Data counter (upper bits)
Port 6 direction register
Analog input enable register
Interrupt control register for A/D
conversion (A/DC)
Control status register for A/D conversion
Data register for A/D conversion
16.10 Sample Program 3 for the 8/10-Bit A/D Converter (Example of EI2OS Start in Stop Mode)
TMCSR1L EQU
000054H
; Lower bits of timer control status register 1
TMCSR1H EQU
000055H
;
TMRLR1L EQU
000056H
; Reload register 1
TMRLR1H EQU
000057H
;
;----------Main program------------------------------------------------------CODE
CSEG
START:
; Stack pointer (SP) already initialized
AND
CCR,#0BFH
; Interrupts disabled
MOV
ICR10, #08H
; Interrupt level 0 (highest)
MOV
BAPL, #00H
; Specify the address to store conversion data
MOV
BAPM, #06H
; (Using 600H to 617H)
MOV
BAPH, #00H
;
MOV
ISCS, #19H
; Word data transfer, address after
; transfer + 1, transfer I/O --> memory,
; end with resource request end
MOV
IOAL, #22H
; As transfer source address pointer, set
MOV
IOAH, #00H
; address of analog data register
MOV
DCTL, #0CH
; 12 EI2OS transfers, 3 ch only
MOV
DCTH, #00H
;
MOV
DDR6, #00000000B ; Set input to P60 to P67
MOV
ADER, #00001000B ; Set P63/AN3 to analog input
MOV
ADCSL, #0DBH
; Stop mode, conversion of AN3 CH
MOV
ADCSH, #0A8H
; 16-bit timer start, A/D conversion start,
; interrupts enabled
MOVW TMRLR1L, #0320H ; Set the timer value to 800 (320H), 100 µs
MOV
TMCSR1H, #00H
; Set clock source to 125 ns, external
; trigger disabled
MOV
TMCSR1L, #12H
; Timer output disabled, interrupt disabled,
; reload enabled
MOV
TMSCR1L, #13H
; Start of 16-bit timer
MOV
ILM, #07H
; Set ILM in PS to level 7
OR
CCR, #40H
; Interrupts enabled
LOOP:
MOV
A,#00H
; Infinite loop
MOV
A,#01H
BRA
LOOP
;----------Interrupt program-------------------------------------------------ED_INT1:
MOV
I:ADCSH, #80H
; A/D conversion not stopped, interrupt
; flag cleared/disabled
RETI
; Return from interrupt
CODE
ENDS
;----------Vector setting----------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FF7CH
; Set vector to interrupt #32 (20H)
DSL
ED_INT1
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set single-chip mode
VECT
ENDS
END
START
361
CHAPTER 16 8/10-BIT A/D CONVERTER
362
CHAPTER 17
UART
This chapter describes the functions and operations of UART.
17.1 "Overview of UART"
17.2 "Configuration of UART"
17.3 "Pins of UART"
17.4 "Registers of UART"
17.5 "Interrupts of UART"
17.6 "Baud Rates of UART"
17.7 "Operation of UART"
17.8 "Notes on Using UART"
17.9 "Sample Program for UART"
363
CHAPTER 17 UART
17.1 Overview of UART
UART is a general-purpose serial data communication interface that enables
synchronous communication or asynchronous communication (start/stop
synchronous) with an external unit. In addition to an ordinary bi-directional
communication function (normal mode), a master-slave type communication function
(in multiprocessor mode: only master) is also provided.
■ UART Functions
❍ UART functions
UART is a general-purpose serial data communication interface used to send data to and
receive data from another CPU or peripheral unit. Table 17.1-1 "UART functions" lists the
functions provided by UART.
Table 17.1-1 UART functions
Function
Data buffer
Full-duplex double buffer
Transfer mode
•
•
Clock synchronous (no start/stop bit)
Clock asynchronous (start/stop interval)
Baud rate
•
•
•
Dedicated baud rate generator (8 rates selectable)
External clock input enabled
Internal clock (supplied from 16-bit reload timer) available
Data length
•
•
7 bits (only in asynchronous normal mode)
8 bits
Signaling
NRZ (Non Return to Zero) method
Receive error detection
•
•
•
Framing error
Overrun error
Parity error (not enabled in the multiprocessor mode)
Interrupt request
•
Receive interrupt (receive complete, receive error
detection)
Send interrupt (send complete)
Extended intelligent I/O service (EI2OS) supported by
both send and receive interrupts
•
•
Master/slave type
communication function
(multiprocessor mode)
1 master to n slaves communication available (only
supported on the master unit)
Note:
UART transfers data for clock synchronous transfer without start/stop bits.
364
17.1 Overview of UART
■ Operation Modes of UART
Table 17.1-2 "Operation modes of UART" lists the operation modes of UART.
Table 17.1-2 Operation modes of UART
Data length
Operation mode
No parity
0
Normal mode
1
Multiprocessor mode
2
Normal mode
Parity used
7 or 8 bits
Synchronous
method
Stop bit length
Asynchronous
1 or 2 bits (*2)
8+1 (*1)
−
Asynchronous
8
−
Synchronous
None
−: Setting disabled
*1: "+1" indicates the address/data selection bit (A/D) used for communication control.
*2: Only a single stop bit can be detected for receive data
■ Interrupts for UART and EI2OS
Table 17.1-3 "Interrupts for UART and EI2OS" shows the relationship between the interrupts
and EI2OS for UART.
Table 17.1-3 Interrupts for UART and EI2OS
Interrupt source
Interrupt
number
Interrupt control
register
Register
name
Vector table address
EI2OS
Address
Lower
bits
Upper
bits
Bank
UART1 receive
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
*
UART1 send interrupt
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
**
UART0 receive
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*
UART0 send interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
**
*: EI2OS stop function based on UART receive error detection
**: Available only when not using interrupt sources that share ICR13, ICR14, or the interrupt vector.
365
CHAPTER 17 UART
17.2 Configuration of UART
UART consists of the following 11 circuit blocks:
• Clock selector
• Receive control circuit
• Send control circuit
• Receive state judge circuit
• Receive shift register
• Send shift register
• Mode registers (SMR0/1)
• Control registers (SCR0/1)
• Status registers (SSR0/1)
• Input data registers (SIDR0/1)
• Output data registers (SODR0/1)
• Communication prescaler control registers (CDCR0/1)
■ Block Diagram of UART
Figure 17.2-1 "UART block diagram" shows a block diagram of UART.
366
17.2 Configuration of UART
Figure 17.2-1 UART block diagram
Control bus
Dedicated baud rate generator
Communication prescaler
control registers
(CDCR0/1)
Send clock
16-bit reload timer
Clock
selector
Receive clock
Machine clock
Receive interrupt signal
#39 (27H) *1
*1
<#37 (25H) >
Send interrupt signal
#40 (28H) *1
<#38 (26H) >*1
Pin
P02/SCK0
<P05/SCK1>
Send control
circuit
Receive
control circuit
Start bit detection
circuit
Send start circuit
Receive bit counter
Send bit counter
Receive parity
counter
Send parity counter
Pin
P01/SOT0
<P04/SOT1
Receive shift
register
Pin
Send shift register
P00/SIN0
<P03/SIN1>
SIDR0/1
Receive
completed
SODR0/1
Send start
Receive state
judge circuit
EI2OS receive error
signal (to the CPU)
Internal data bus
SMR0/1
Resister
MD1
MD0
CS2
CS1
CS0
SCKE
SOE
SCR0/1
Resister
PEN
P
SBL
CL
A/D
REC
RXE
TXE
SSR0/1
Resister
PE
ORE
FRE
RDRF
TDRE
BDS
RIE
TIE
*1: interrupt number
❍ Clock selector
The clock selector is used to select send and receive clocks from the dedicated baud rate
generator, external input clock, and internal clock (supplied by the 16-bit reload timer).
❍ Receive control circuit
The receive control circuit consists of a receive bit counter, start bit detection circuit, and receive
parity counter. The receive bit counter counts the number of received data items and issues a
receive interrupt request as soon as one unit of data (as defined based on the data length) has
been received. The start bit detection circuit is used to detect start bits in the serial input signal,
then writes the data to SIDR while shifting based on transfer speed. The receive parity counter
will calculate the parity of the received data.
367
CHAPTER 17 UART
❍ Send control circuit
The send control circuit consists of a send bit counter, send start circuit, and send parity
counter. The send bit counter counts the number of sent data items and issues a send interrupt
request as soon as one unit of data (as defined based on the data length) has been sent. The
send start circuit starts send operation together with the SODR write operation. The send parity
counter generates a parity bit for the data sent if parity is used.
❍ Receive shift register
The shift register for receiving reads the receive data input from the SIN0 pin by shifting one bit
at a time, and transfers the receive data to SIDR when reception is completed.
❍ Send shift register
The send shift register transfers the data written to SODR to the send shift register and outputs
it via the SOT0 pin while shifting one bit at a time.
❍ Mode registers (SMR0/1)
The mode registers are used to select the operation mode and clock input source, set the
dedicated baud rate generator, select the clock rate (clock divide value) used by the dedicated
baud rate generator, and enable or disable serial data pin and clock pin output.
❍ Control registers (SCR0/1)
The control registers are used to set use or non-use of parity, as well as to select the parity,
stop bit length, data length, frame data format in mode 1. Moreover, they are used to clear flags
and enable or disable send and receive operations.
❍ Status registers (SSR0/1)
The status registers are used to confirm send and receive operations, indicate an error status,
and to allow or prohibit send/receive interrupt requests.
❍ Input data registers (SIDR0/1)
The input data registers store the received data. Serial input is stored in these registers after
conversion.
❍ Output data registers (SODR0/1)
The output data registers are used to store data to be sent. Data written to these registers is
output after serial conversion.
❍ Communication prescaler control registers (CDCR0/1)
The communication prescaler control registers (CDCR0/1) is a register setting the baud rate of
the Dedicated Baud Rate Generator.
The communication prescaler control registers (CDCR0/1) are used to control start/stop of the
communication prescaler, and the control divide ratio of the machine clock.
368
17.3 Pins of UART
17.3 Pins of UART
The following shows a block diagram of the pins of UART.
■ Pins of UART
The pins of UART are also used for general-purpose ports. Table 17.3-1 "UART pins" lists the
function of each pin, the type of I/O, and settings for using UART.
Table 17.3-1 UART pins
Pin name
Pin function
P00/SIN0/
INT4 (P03/
SIN1/INT7)
Port 0 I/O or
serial data input
P01/SOT0/
INT5 (P04/
SOT1)
Port 0 I/O or
serial data output
P02/SCK0/
INT6 (P05/
SCK1/TRG)
Port 0 I/O or
serial clock I/O
Type of I/O
Pull-up
selection
Standby
control
Setting for using pin
Set to input port
(DDR0: bit 0=0)
(DDR0: bit 3=0)
CMOS
output or
CMOS
(hysteresis)
(automotive
level (*))
Set to "output enabled"
(SMR:SOE=1)
Not used
Used
Set to input port at clock input
(DDR0: bit 2=0)
(DD0: bit 5=0)
Set to output enabled at clock
output
(SMR: SCKE=1)
*: "Automotive level" is a standard for input voltage.
For the standard values please refer to the data sheet ("3. DC Characteristics" in the topic title "ELECTRICAL
CHARACTERISTICS").
369
CHAPTER 17 UART
■ Block Diagram of Pins of UART
Figure 17.3-1 "Block diagram of pins of UART" shows a block diagram of the pins of UART.
Figure 17.3-1 Block diagram of pins of UART
Resource input*1
Resource output*1
PDR (Port data register)
Resource output enabled*1
Internal data bus
PDR read
Pch
Output latch
PDR write
Pin
DDR (Port direction register)
Nch
Direction latch
DDR write
DDR read
Standby control (SPL=1)
Standby control: stop, timebase timer modes, and SPL=1
*1: Resource I/O applies only to pins with peripheral functions
370
P00/SIN0
P01/SOT0
P02/SCK0
P03/SIN1
P04/SOT1
P05/SCK1
17.4 Registers of UART
17.4 Registers of UART
This section describes the registers of UART.
■ List of UART Registers
Figure 17.4-1 "Registers for UART" shows a list of the registers of UART.
Figure 17.4-1 Registers for UART
bit8 bit7
Address bit15
ch0 : 000035H, 34H
SCR( control register)
SMR(mode register )
ch1 : 000039H, 38H
ch0 : 000037H, 36H
SSR(status register )
SIDR/SODR( I/O data registers)
ch1 : 00003BH, 3AH
ch0 : 00003DH
Blank
CDCR(communication prescaler control register )
ch1 : 00003FH
bit0
371
CHAPTER 17 UART
17.4.1 Control Registers (SCR0/1)
The control registers (SCR0/1) are used to set parity, select the stop bit length and data
length, select the frame data format in mode 1, clear receive error flags, and enable or
disable send/receive operations.
■ Bit Configuration of Control Registers (SCR0/1)
Figure 17.4-2 "Bit configuration of control registers (SCR0/1)" shows the bit configuration of the
control registers (SCR0/1); Table 17.4-1 "Functions of bits of the control registers (SCR0/1)"
lists the function of each bit.
Figure 17.4-2 Bit configuration of control registers (SCR0/1)
Address
ch0: 000035H
ch1: 000039H
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PEN
P
SBL
CL
A/D REC RXE TXE
R/W R/W R/W R/W R/W
W
0
1
RXE
0
1
Send operation enable bit
Send operation disabled
Send operation enabled
Receive operation enable bit
Receive operation disabled
Receive operation enabled
Receive error flag clear bit
0
FRE, ORE, PE flags cleared
Does not change and has no effect
1
Address/data selection bit
Data frame
Address frame
CL
Data length selection bit
A/D
0
0
1
SBL
0
1
P
0
1
PEN
372
00000100B
REC
1
: Initial value
(SMR)
R/W R/W
TXE
R/W : Reading and writing permitted
: Write
W
bit0 Initial value
bit8 bit7
0
1
7 bits
8 bits
Stop bit length selection bit
1-bit length
2-bit length
Parity selection bit
Valid only when using parity (PEN=1)
Even-number parity
Odd-number parity
Parity enable bit
No parity
Parity used
17.4 Registers of UART
Table 17.4-1 Functions of bits of the control registers (SCR0/1)
Bit name
Function
bit15
PEN:
Parity enable bit
Selects whether a parity bit is added at serial data I/O processing
(when sending), and detected (when receiving).
Note:
Since operation modes 1, 2 use no parity, always set this bit to "0".
bit14
P:
Parity selection bit
bit13
SBL:
Stop bit length
selection bit
Selects the bit length of the stop bit (i.e., the end mark used for send
data in asynchronous transfer mode).
Note:
At reception, only the first stop bit is detected.
bit12
CL:
Data length
selection bit
Specifies the data length of send/receive data.
Note:
Selecting 7 bits is only enabled in operation mode 0
(asynchronous). Select 8 bits (CL=1) in mode 1 (multiprocessor
mode) or operation mode 2 (synchronous).
bit11
A/D:
Address/data
selection bit
•
bit10
REC:
Receive error flag
clear bit
•
bit9
RXE:
Receive operation
enable bit
•
•
bit8
TXE:
Send operation
enable bit
•
•
When using parity (PEN=1), odd or even parity is selected.
•
In multiprocessor mode (mode1), specifies the format of frame data
that is sent or received.
When this bit is "0", the frame data consists of normal data.
Otherwise, it consists of address data.
Used to clear the FRE, ORE and PE flags in the status register
(SSR).
• When this bit is "0", the FRE, ORE and PE flags are cleared; when
this bit is "1", no changes are made.
Note:
In receive interrupt enabled mode during UART operation, the REC
bit is cleared only when the FRE, DRE or PE flag is set to "1".
Controls UART receive operation.
When this bit is "0", receive operation is prohibited; when it is "1",
receive operation is allowed.
Note:
If receive operation becomes prohibited during reception, reception
is stooped after reception of the frame is completed and the data
has been stored in the buffer (SIDR1).
Controls UART send operation.
When this bit is "0", send operation is disabled; when it is "1", send
operation is enabled.
Note:
If send operation is disabled while sending, send operation will stop
when the send data buffer (SODR1) becomes empty.
373
CHAPTER 17 UART
17.4.2 Mode Registers (SMR0/1)
The mode registers (SMR0/1) are used to select the operation mode and baud rate
clock, and enable or disable pin output of the serial data clock.
■ Bit Configuration of Mode Registers (SMR0/1)
Figure 17.4-3 "Bit configuration of mode registers (SMR0/1)" shows the bit configuration of the
mode registers (SMR0/1); Table 17.4-2 "Functions of bits in the mode registers (SMR0/1)" lists
the function of each bit.
Figure 17.4-3 Bit configuration of mode registers (SMR0/1)
Address bit15
ch0:000034 H
ch1:000038 H
bit8 bit7
(SCR)
bit6
bit5
bit4
bit3
bit2
MD1 MD0 CS2 CS1 CS0
bit1
bit0
Initial value
SCKE SOE 0 0 0 0 0 - 0 0 B
R/W R/W R/W R/W R/W
R/W R/W
SOE Serial data output enable bit (P37/S0T0, P61/S0T1 pins)
0
General-purpose I/O port
1
UART0/1 serial data output
SCKE Serial clock output enable bit (P40/SCK0, P62/SCK1 pins)
0 General-purpose I/O port or UART0/1 clock input pin
1
UART0/1 clock output pin
CS2 to 0
"000B"to"101B"
"110B"
Baud rate by internal timer
(16-bit reload timer 0)
"111B"
Baud rate by external timer
Operation mode selection bit
Operation mode
MD1 MD0
R/W
374
: Reading and writing permitted
: Initial value
: Machine clock frequency
Clock selection bit
Baud rate by dedicated baud rate generator
0
0
0
0
1
1
1
0
2
1
1
Asynchronous (normal mode)
Asynchronous (multiprocessor mode)
Synchronous (normal mode)
Setting disabled
17.4 Registers of UART
Table 17.4-2 Functions of bits in the mode registers (SMR0/1)
Bit name
Function
bit7
bit6
MD1, MD0:
Operation mode selection
bit
• Used to select the operation mode.
Note:
Operation mode 1 (multiprocessor mode) can only be used
on the master unit in master-slave communication. UART
cannot be used as slave since it has no address/data
judgement function for reception.
bit5
bit4
bit3
CS2 to 0:
Clock selection bit
•
•
•
Used to select a clock source for the baud rate. When the
dedicated baud rate generator is selected, the baud rate is
determined at the same time.
When the dedicated baud rate generator is selected, one of
five baud rates can be selected in asynchronous transfer
mode, or one of eight rates can be selected in synchronous
transfer mode.
Clock input is selected from the external clock (SCK0 pin),
16-bit reload timer, and dedicated baud rate generator.
bit2
Empty bit
Reserved bit
bit1
SCKE:
Serial clock output enable
bit
•
•
bit0
SOE:
Serial data output enable
bit
•
•
Used to control serial clock I/O.
When this bit is "0", the P02/SCK0 pins function as a
general-purpose I/O port (P02) or serial clock input pin;
when this bit is "1", the pins function as a serial clock output
pin.
Notes:
• When the P02/SCK0 pins are used for serial clock input
(SCKE=0), set P02 as the input port. Use the clock
selection bit to select an external clock (SMR:CS2 to
CS0=111B).
• When used as serial clock output (SCKE=1), select a clock
other than the external clock (i.e., other than SMR:CS2 to
CS0=111B).
Reference:
When the SCK0 pin is used for serial clock output
(SCKE=1), it functions as a serial clock output pin
(regardless of general-purpose I-O port status).
Used to enable or disable serial data output.
When this bit is "0", the P01/SOT0 pins function as a
general-purpose I/O port (P01); when this bit is "1", the pins
function as a serial data output pin (SOT0).
Reference:
For serial data output (SOE=1), the pins function as SOTO
pins (regardless of the status of the general-purpose I/O
port (P01)).
375
CHAPTER 17 UART
17.4.3 Status Registers (SSR0/1)
The status registers (SSR0/1) are used to confirm send/receive operation, indicate an
error status, and allow or prohibit interrupts.
■ Bit configuration of Status Registers (SSR0/1)
Figure 17.4-4 "Bit configuration of status registers (SSR0/1)" shows the bit configuration of the
status registers (SSR0/1); Table 17.4-3 "Functions of bits in the status registers (SSR0/1)" lists
the function of each bit.
Figure 17.4-4 Bit configuration of status registers (SSR0/1)
Address
ch0:000037H
ch1:00003BH
bit15 bit14 bit13 bit12 bit11 bit10 bit9
PE
ORE FRE RDRF TDRE BDS RIE
R
R
R
R
R
bit8 bit7
TIE
bit0 Initial value
(SIDR/SODR)
00001000B
R/W R/W R/W
TIE Send interrupt request enable bit
0
1
Send interrupt request output disabled
Send interrupt request output enabled
Receive interrupt request enable bit
Receive interrupt request output disabled
1 Receive interrupt request output enabled
RIE
0
BDS
0
1
TDRE
0
1
RDRF
0
1
Transfer direction selection bit
LSB first (transfer starting with LSB)
MSB first (transfer starting with MSB)
Flag bit indicating no data
Send data present (writing send data disabled)
Send data not present (writing send data enabled)
Flag bit for receive data available
No receive data
Receive data exists
Flag bit for framing error
FRE
0 No framing error
1
ORE
0
1
PE
0
1
R/W : Reading and writing permitted
R : Read only
: Not used
X : Not specified
: Initial value
376
Framing error occurred
Flag bit for overrun error
No overrun error
Overrun error occurred
Flag bit for parity error
No parity error
Parity error occurred
17.4 Registers of UART
Table 17.4-3 Functions of bits in the status registers (SSR0/1)
Bit name
bit15
PE:
Flag bit for parity error
Function
•
•
•
bit14
ORE:
Flag bit for overrun error
•
•
•
bit13
FRE:
Flag bit for framing error
•
•
•
bit12
RDRF:
Flag bit for receive data
available
•
•
•
Set to "1" if parity error occurs at reception, or cleared by setting the
REC bit of the mode register (SMR) to "0" in a write operation.
When this bit and the RIE bit are set to "1", a receive interrupt request
is output.
When this flag is set, data in the input data register (SIDR) is invalid.
Set to "1" if an overrun occurs at reception, or cleared to "0" when the
REC bit in the mode register (SMR) is set to "0".
When this bit and the RIE bit are set to "1", a receive interrupt request
is output.
When this flag is set, data in the input data register (SIDR) is invalid.
Set to "1" if a framing error occurs at reception, or cleared to "0" when
the REC bit in the mode register (SMR) is set to "0".
When this bit and the RIE bit are set to "1", a receive interrupt request
is output.
When this flag is set, data in the input data register (SIDR) is invalid.
A flag to indicate the status of the input data register (SIDR).
When the SIDR contains receive data, this bit is set to "1". When SIDR
is read, this bit is cleared to "0".
When this bit and the RIE bit are set to "1", a receive interrupt request
is output.
bit11
TDRE:
Flag bit for no data
•
•
A flag to indicate the status of the output data register (SODR).
Cleared to "0" when send data is loaded into the SODR, or set to "1"
when data is loaded into the send shift register and sending starts.
• When this bit and the TIE bit are set to "1", a send interrupt request is
output.
Note:
In initial state, this bit is "1"(SODR empty).
bit10
BDS:
Transfer direction
selection bit 14.
•
bit9
RIE:
Receive interrupt
request enable bit
•
•
Used to enable or disable receive interrupt requests to the CPU.
When this bit and the receive data flag bit (RDRF) are "1", or this bit
and one or more error flag bits (PE, ORE, FRE) are "1", a receive
interrupt request is output.
bit8
TIE:
Send interrupt request
enable bit
•
•
Used to enable or disable send interrupt request output to the CPU.
When this bit and the TDRE bit are set to "1", a send interrupt request
is output.
Used to select whether serial data is transferred starting with LSB (LSB
first, BDS=0), or from MSB (MSB first, BDS=1).
Note:
Since the upper bits and lower bits of data are switched when reading
from or writing to the serial data register, the respective data will be
invalid if this bit is rewritten after data is written to SDR.
377
CHAPTER 17 UART
17.4.4 Input Data Registers (SIDR0/1) and Output Data Registers
(SODR0/1)
The input data registers (SIDR0/1) are used to receive serial data; the output data
registers (SODR0/1) are used to send serial data. SIDR0/1 and SODR0/1 are allocated
under the same address.
■ Bit Configuration of Input Data Registers (SIDR0/1)
Figure 17.4-5 "Bit configuration of input data registers (SIDR0/1)" shows the bit configuration of
the input data registers.
Figure 17.4-5 Bit configuration of input data registers (SIDR0/1)
Address
ch0: 000036H
ch1: 00003AH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
R
R
R
R
R
R
R
R
R: Read only
x: Not specified
The input data registers (SIDR0/1) are used to store the data received. A serial data signal sent
to the SIN0 pin is converted by the shift register, then stored in this register. When the data
length is 7 bits, the upper bit (D7) is invalid. If receive data is stored in this register, the flag bit
for receive data available (SSR: RDRF) is set to "1". If receive interrupt requests are enabled, a
receive interrupt will be generated in this case.
Read SIDR0/1 when the RDRF bit in the status registers (SSR0/1) is "1". The RDRF bit is
automatically cleared to "0" when SIDR0/1 is read. If a receive error occurs (with PE, ORE or
FRE in SSR set to "1"), the data in SIDR0/1 becomes invalid.
378
17.4 Registers of UART
■ Bit Configuration of Output Data Registers (SODR0/1)
Figure 17.4-6 "Bit configuration of output data registers (SODR0/1)" shows the bit configuration
of the output data registers.
Figure 17.4-6 Bit configuration of output data registers (SODR0/1)
Address
ch0: 000036H
ch1: 00003AH
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Initial value
D7
D6
D5
D4
D3
D2
D1
D0
XXXXXXXX B
W
W
W
W
W
W
W
W
W : Write only
X : Not specified
When data to be sent is written to these registers in sending enabled state, the data to be sent
is transferred to the send shift register, converted into serial data, then sent via the serial data
output pin (SOT0). For a data length of 7 bits, the upper bit (D7) becomes invalid.
When send data is written to these registers, the flag for empty send data (SSR: TDRE) is
cleared to "0". After data is transferred to the send shift register, the flag is set to "1". As soon as
the TDRE bit is set to "1", the next item of send data can be written. When send interrupt
requests are enabled in this case, a send interrupt is generated. Writing the next item of send
data is triggered by a send interrupt or the TDRE bit being set to "1".
Note:
SODR0/1 are write-only registers; SIDR0/1 are read-only registers. Both types are allocated
under the same address, but have different write and read values. Therefore, such readmodify-write (RMW) instructions as INC/DEC cannot be used.
379
CHAPTER 17 UART
17.4.5 Communication Prescaler Control Registers (CDCR0/1)
The communication prescaler control registers (CDCR0/1) are used to control the
division of the machine clock.
■ Bit Configuration of Communication Prescaler Control Registers (CDCR0/1)
The UART operation clock can be obtained by dividing the machine clock. This communication
prescaler is designed to obtain a constant baud rate for various machine cycles. Communication
prescaler output may be used for the operation clock in an extension I-O serial interface. Figure
17.4-7 "Bit configuration of communication prescaler control registers (CDCR0/1)" shows the bit
configuration of CDCR0/1.
Figure 17.4-7 Bit configuration of communication prescaler control registers (CDCR0/1)
Address
ch0: 00003DH
ch1: 00003FH
bit15 bit14 bit13 bit12 bit11 bit10 bit9
MD
-
-
-
R/W
bit8
DIV3 DIV2 DIV1 DIV0
Initial value
0---0000B
R/W R/W R/W R/W
R: Read only
x: Not specified
- : Undefined
[bit 15] MD (Machine clock divide mode select)
The MS bit is an operation enable bit for the communication prescaler.
0: Stop communication prescaler.
1: Operate communication prescaler.
[bit 14,13,12] undefined
Bit undefined.
Value at reading is not specified.
Writing does not affect operation.
380
17.4 Registers of UART
[bits 11,10,9,8] DIV3 to 0 (DIV 3 to 0)
Table 17.4-4 "Communication prescaler (divide ratio of machine clock)" shows how the
divide ratio of the machine clock is determined.
Table 17.4-4 Communication prescaler (divide ratio of machine clock)
MD
DIV3
DIV2
DIV1
DIV0
Div
0
−
−
−
−
Stop
1
0
0
0
0
1
1
0
0
0
1
2
1
0
0
1
0
3
1
0
0
1
1
4
1
0
1
0
0
5
1
0
1
0
1
6
1
0
1
1
0
7
1
0
1
1
1
8
Note:
After changing the divide ratio, enter two cycles of the interval clock to provide for
stabilization time before starting communication.
381
CHAPTER 17 UART
17.5 Interrupts of UART
UART uses send and receive interrupts to generate an interrupt request based on the
sources listed below.
• Loading receive data in an input data register (SIDR0/1) or occurrence of a receive
error
• Transferring send data from an output data register (SODR0/1) to the send shift
register
Both sources support the extended intelligent I/O service (EI2OS).
■ Interrupts of UART
Table 17.5-1 "Relationship between UART interrupt control bits and interrupt sources" shows
the relationship between UART interrupt control bits and interrupt sources.
Table 17.5-1 Relationship between UART interrupt control bits and interrupt sources
Send/
receive
Operation
mode
Flag bit for
interrupt
requests
0
1
2
RDRF
Y
Y
Y
Loading receive data
into the buffer (SIDR)
ORE
Y
Y
Y
Overrun error
FRE
Y
Y
N
Framing error
PE
Y
N
N
Parity error
Y
Y
Y
Send buffer (SODR)
empty
Receive
Send
TDRE
Interrupt source
Interrupt
source
enable bit
SSR0/1:
RIE
Interrupt request
flag cleared
Reading receive
data
Clearing the receive
error flag clear bit
(SCR0/1:REC) by
writing "0"
SSR0/1:
TIE
Writing send data
Y: Bit used
N: Bit not used
❍ Receive interrupt
In receive mode, the corresponding flag bit in the status register to "1" at data receive
completion (SSR0/1: RDRF), overrun error (SSR0/1: ORE), framing error (SSR0/1: FRE), or
parity error (SSR0/1: PE). If receive interrupts are enabled (SSR0/1: RIE=1) with either flag bit
set to "1", a receive interrupt request is output to the interrupt controller.
The flag for receive data available (SSR0/1…RDRF) is automatically cleared to "0" when an
input data register (SIDR0/1) is read. When all receive error flags (SSR0/1: PE, ORE, FRE) are
cleared to "0", the REC bit in the control registers (SCR0/1) is set to "0".
382
17.5 Interrupts of UART
❍ Send interrupt
When send data is transferred from an output data register (SODR0/1) to the transfer shift
register, the TDRE bit in the status registers (SSR0/1) is set to "1". When send interrupts are
enabled (SSR0/1: TIE=1) in this case, a send interrupt request is output to the interrupt
controller.
■ Interrupts of UART and EI2OS
Table 17.5-2 "Interrupts for UART and EI2OS" shows the relationship between the interrupts
and EI2OS for UART.
Table 17.5-2 Interrupts for UART and EI2OS
Interrupt source
Interrupt
number
Interrupt control
register
Vector table address
Register
name
Address
Lower
bits
Upper
bits
Bank
EI2OS
UART1 receive
interrupt
#37(25H)
ICR13
0000BDH
FFFF68H
FFFF69H
FFFF6AH
*
UART1 send
interrupt
#38(26H)
ICR13
0000BDH
FFFF64H
FFFF65H
FFFF66H
**
UART0 receive
interrupt
#39(27H)
ICR14
0000BEH
FFFF60H
FFFF61H
FFFF62H
*
UART0 send
interrupt
#40(28H)
ICR14
0000BEH
FFFF5CH
FFFF5DH
FFFF5EH
**
*: The EI2OS stop function is provided for UART receive error detection
**: Available when not using interrupt sources sharing ICR13, ICR14, and the interrupt vector.
■ EI2OS Function in UART
UART has a circuit for supporting EI2OS. Therefore, each interrupt generated by a receive/send
operation may separately start EI2OS.
❍ At receiving
EI2OS is used regardless of the status of other resources.
❍ At sending
Since UART shares the interrupt control registers (ICR13, ICR14) with UART receive interrupts,
it can start EI2OS only provided that the UART receive operation does not generate an interrupt.
383
CHAPTER 17 UART
17.5.1 Timing of Receive Interrupt Generation and Flag Setting
At reception, an interrupt is issued in case of receive completion (SSR0/1: RDRF) and
receive error (SSR0/1: PE, ORE, FRE).
■ Timing of Receive Interrupt Generation and Flag Setting
If the stop bit (in operation mode 0/1) or final data bit (D7) (in operation mode 2) is detected at
reception, receive data is stored in the input data registers (SIDR0/1). If a receive error occurs
in this case, an error flag (SSR0/1: PE, ORE, FRE) is set, then the flag for full receive data
(SSR0/1: RDRF) is set to "1". If any error flag is set to "1" in each mode, the SIDR0/1 value
becomes invalid.
❍ Operation mode 0 (asynchronous, normal mode)
If RDRF is set to "1" and a receive error occurs with the stop bit detected, an error flag (PE,
ORE, FRE) is set.
❍ Operation mode 1 (asynchronous, multiprocessor mode)
If RDRF is set to "1" and a receive error occurs with the stop bit detected, an error flag (ORE,
FRE) is set. Parity errors cannot be detected.
❍ Operation mode 2 (synchronous, normal mode)
If the final bit (D7) of the receive data is detected, RDRF is set, or a receive error occurs, an
error flag (ORE) is set. Neither a parity error nor a framing error can be detected. Figure 17.5-1
"Timing of receive operation and flag setting" shows the receive operation and timing of setting
flags.
Figure 17.5-1 Timing of receive operation and flag setting
Receive data
(Operation mode 0)
ST
D0
D1
D5
D6
D7
SP
Receive data
(Operation mode 1)
ST
D0
D1
D6
D7
A/D
SP
D0
D1
D4
D5
D6
D7
Receive data
(Operation mode 2)
PE, ORE, FRE*
RDRF
Receive interrupt generated
PE flag disabled in mode1
PE, PRE flag disabled in mode2
ST: Start bit
SP: Stop bit
A/D: Address/data selection bit for mode 2 (multiprocessor mode)
*:
❍ Timing of receive interrupt generation
When receive interrupts are enabled (SSR0/1: RIE=1), a receive interrupt request (#37, #39) is
generated immediately if the RDRF, PE, ORE or FRE flag is set to "1".
384
17.5 Interrupts of UART
17.5.2 Timing of Send Interrupt Generation and Flag Setting
A send interrupt is issued when the next item of data can be written to the output data
register (SODR0/1).
■ Timing of Send Interrupt Generation and Flag Setting
The flag bit for no data (SSR0/1: TDRE) is set to "1" when data written to an output data register
(SODR0/1) is transferred to the send shift register and the next item of data can be written.
When send data is written to SODR0/1, TDRE is cleared to "0". Figure 17.5-2 "Timing of send
operation and flag setting" shows the timing of the send operation and of setting flags.
Figure 17.5-2 Timing of send operation and flag setting
[Operation mode 0/1]
Send interrupt generated
Send interrupt generated
SODR write
TDRE
S0T0/1 output
[Operation mode 2]
ST
D0 D1 D2
Send interrupt generated
D3 D4
D5 D6
SP
D7 A/D SP
ST D0 D1
D2 D3
D3 D4 D5
D6 D7
Send interrupt generated
SODR write
TDRE
S0T0/1 output
:
ST
D0 to D7 :
:
SP
:
A/D
D0
D1 D2 D3
D4 D5
D6 D7
D0
D1 D2
Start bit
Data bit
Stop bit
Address/data selection bit
❍ Timing of send interrupt request
A send interrupt request (#38, #40) is generated immediately When sent interrupts are enabled
(SSR0/1: TIE=1) and the TDRE flag is set to "1".
Notes:
In the initial state immediately after the TDRE bit is set to "1" and send interrupts are enabled
(TIE=1), a send complete interrupt is generated. Since the TDRE bit is a read-only bit, it can
only be cleared by writing new data to the output data registers (SODR0/1). Therefore,
carefully consider the timing of enabling send interrupts.
When the send operation is disabled while data is being sent (this also applies to a receive
operation disabling RXE if SCR: TXE = 0 and the operation mode is 1), the send data empty
flag bit is set (SSR: TDRE=1), and the shifting operation of the shift register for sending data
is stopped. Then, UART communication is disabled. However, send data that had already
been written to the serial output data register (SODR) before the send operation was
stopped is sent.
385
CHAPTER 17 UART
17.6 Baud Rates of UART
One of the following UART send/receive clocks can be selected:
• Dedicated baud rate generator
• Internal clock (16-bit reload timer)
• External clock (SCK pin input clock)
■ UART Baud Rate Selection
One of the three baud rates listed below can be selected. Figure 17.6-1 "UART baud rate
selection circuit" shows the baud rate selection circuit.
❍ Baud rate selection by dedicated baud rate generator
UART has a built-in dedicated baud rate generator to select one of eight baud rates by using the
mode registers (SMR0/1). By using the machine clock frequency and the bit BCH and CS2 to
CS0 in the mode registers (SMR0/1), an asynchronous or a clock synchronous baud rate can
be selected.
❍ Baud rate selection by internal timer
The internal clock supplied by the 16-bit reload timer is used as is (for synchronous baud rate)
or by divide-by-16 (for asynchronous baud rate) to determine the baud rate. Setting a reload
value enables the selection of any baud rate.
❍ Baud rate selection by external clock
The clock supplied by the UART clock input pins (SCK0/P02, SCK1/P05) is used as is (for
synchronous baud rate) or by divide-by-16 (for asynchronous baud rate) to determine the baud
rate. Any baud rate can be set externally.
386
17.6 Baud Rates of UART
Figure 17.6-1 UART baud rate selection circuit
SMR0/1:CS2 to 0
(Clock selection bit)
[Dedicated baud rate generator]
4
Machine clock
divide ratio
Clock selector
For 000B to
101B
Dividing circuit
(Synchronous)
Select any divide ratio
from 1 to 32.
(asynchronous)
Select internal fixed
divide ratio.
[Internal timer]
TMCSR0/1:CSL1, CSL0
2
Clock selector
UF
Down
counter
For 110B
1/1 (Synchronous)
1/16 (Asynchronous)
Baud rate
/21 /23 /25
Prescaler
16-bit reload timer 0
[External clock]
SCK0,SCK1
Pin
For 111B
1/1 (Synchronous)
1/16 (Asynchronous)
SMR0/1:ND1
(Selecting clock synchronous/asynchronous baud rate)
: machine clock frequency
387
CHAPTER 17 UART
17.6.1 Baud Rate Selection by Dedicated Baud Rate Generator
When the output clock of the dedicated baud rate generator is selected as the UART
transfer clock, any of the baud rates listed below may be specified.
■ Baud Rate Selection by Dedicated Baud Rate Generator
To generate the transfer clock using the dedicated baud rate generator, the machine clock
prescaler divides the machine clock, which is then divided by the transfer clock divide ratio
selected by the clock selector. The machine clock divide ratio is the same for asynchronous/
synchronous operation, but the transfer clock divide ratio can be selected separately for
asynchronous or synchronous operation by internal setting values.
Therefore, the actual transfer rate is determined as follows.
Asynchronous baud rate = Φ x (prescaler divide ratio) x (asynchronous transfer clock
divide ratio)
Synchronous baud rate = Φ x (prescaler divide ratio) x (synchronous transfer clock
divide ratio)
Φ: Machine clock frequency
❍ Divide ratio specified by the prescaler (common for asynchronous/synchronous
operation)
The machine clock divide ratio is specified by the bits DIV3 to DIV0 in the CDCR0/1 registers as
listed in Table 17.6-1 "Selection of divide ratio by machine clock prescaler".
Table 17.6-1 Selection of divide ratio by machine clock prescaler
388
MD
DIV3
DIV2
DIV1
DIV0
Div
0
−
−
−
−
Stop
1
0
0
0
0
1
1
0
0
0
1
2
1
0
0
1
0
3
1
0
0
1
1
4
1
0
1
0
0
5
1
0
1
0
1
6
1
0
1
1
0
7
1
0
1
1
1
8
17.6 Baud Rates of UART
❍ Synchronous transfer clock divide ratio
The divide ratio of the synchronous baud rate is specified by the bits CS2-0 in the mode register
(SMR) as listed in Table 17.6-2 "Selection of synchronous baud rate and divide ratio".
Table 17.6-2 Selection of synchronous baud rate and divide ratio
CL2
CS1
CS0
CLK synchronization
Calculation
SCKI
0
0
0
16M
(φ/div)/1
(φ/div)/1
0
0
1
8M
(φ/div)/2
(φ/div)/2
0
1
0
4M
(φ/div)/4
(φ/div)/4
0
1
1
2M
(φdiv)/8
(φ/div)/8
1
0
0
1M
(φ/div)/16
(φ/div)/16
1
0
1
500K
(φ/div)/32
(φ/div)/32
φ is derived from the machine cycle, with φ = 16 MHz and div = 4.
❍ Asynchronous transfer clock divide ratio
The divide ratio of the asynchronous baud rate is specified by the bits CS2 to CS0 in the mode
registers (SMR0/1) as listed in Table 17.6-3 "Selection of asynchronous baud rate divide ratio".
Table 17.6-3 Selection of asynchronous baud rate divide ratio
CL2
CS1
CS0
CLK synchronization
Calculation
SCKI
0
0
0
76923
(φ/div)/(8×13×2)
(φ/div)/(13×1)
0
0
1
38461
(φ/div)/(8×13×4)
(φ/div)/(13×2)
0
1
0
19230
(φ/div)/(8×13×8)
(φ/div)/(13×4)
0
1
1
9615
(φ/div)/(8×13×16)
(φ/div)/(13×8)
1
0
0
500K
(φ/div)/(8×2×2)
(φ/div)/2
1
0
1
250K
(φ/div)/(8×2×4)
(φ/div)/4
φ is derived from the machine cycle, with φ =16 MHz and div=4.
❍ Internal timer
The formula for calculating the baud rate when CS2 to CS0 are set to 110B to select the internal
timer is shown below (example of using the reload timer).
asynchronous (start/stop synchronous) (φ
φ /N) / (16 x 2 x (n + 1))
CLK synchronous (φ
φ /N) / (2 x (n + 1))
N: timer count clock source
n: timer reload value
Note:
In mode 2 (CLK synchronous mode), SCK0 is delayed with respect to SCKI by up to three
clocks. A transfer rate of up to one-third the system clock frequency is theoretically possible.
In actual use, however, we recommend using not more than one-forth.
389
CHAPTER 17 UART
❍ External clock
When the external clock is selected with CS2 to CS0 set to 111B, the baud rate is selected as
follows (the frequency is indicated as f in the following formula).
In asynchronous operation (start/stop synchronous) f/16
In CLK synchronous operation f’
"f" can be no more than one-half the machine clock, while f’ can be no more than one-eighth the
machine clock.
390
17.6 Baud Rates of UART
17.6.2 Baud Rate Selection by Internal Timer (16-Bit Reload
Timer)
This section describes the settings and baud rate for the case when the internal clock
supplied from the 16-bit reload timer is selected as UART transfer clock.
■ Baud Rate Selection by Internal Timer (16-Bit Reload Timer)
Setting the CS2 to 0 bits in the mode registers (SMR0/1) to 110B will enable baud rate selection
by the internal timer. Any baud rate can be set by selecting a prescaler divide ratio and reload
value of the 16-bit reload timer. Figure 17.6-2 "Circuit for baud rate selection by internal timer
(16-bit reload timer)" shows the baud rate selection circuit used by the internal timer.
Figure 17.6-2 Circuit for baud rate selection by internal timer (16-bit reload timer)
SMR0/1: CS2 to CS0 = 110B
(Internal timer selection)
Clock selector
16-bit reload timer output
(specifying frequency based on
prescaler divide ratio and reload
value)
1/1 (synchronous)
1/16 (asynchronous)
Baud rate
SMR0/1:MD1
(Selecting clock synchronous/asynchronous operation)
❍ Formula for baud rate calculation
asynchronous baud rate =
X (n+1) 2 16
synchronous baud rate =
X (n+1) 2
X
n
bps
bps
: Machine clock frequency
: Divide ratio selected by prescaler of 16-bit reload timer (21, 23, 25)
: Reload value of 16-bit reload timer (0 to 65535)
391
CHAPTER 17 UART
❍ Example of setting the reload value (for 7.3728 MHz machine clock)
Table 17.6-4 "Baud rate and reload value" shows the relationship between the baud rate and
reload value.
Table 17.6-4 Baud rate and reload value
Reload value
Baud rate
Clock asynchronous (start/stop
synchronous)
X=21
(Divide-by-2 of
machine cycle)
X=23
(Divide-by-8 of
machine cycle)
X=21
(Divide-by-2 of
machine cycle)
X=23
(Divide-by-8 of
machine cycle)
38400
2
−
47
11
19200
5
−
95
23
9600
11
2
191
47
4800
23
5
383
95
2400
47
11
767
191
1200
95
23
1535
383
600
191
47
3071
767
300
383
95
6143
1535
X: Divide ratio for prescaler of 16-bit reload timer
−: Cannot be set
392
Clock synchronous
17.6 Baud Rates of UART
17.6.3 Baud Rate Selection by External Clock
This section describes the required settings and provides a formula to calculate the
baud rate for the case the external clock is selected as the UART transfer clock.
■ Baud Rate at Selection of External Clock
❍ Selecting the baud rate
To select a baud rate for using an external clock, the three settings listed below are required.
Set the bits CS2 to CS0 in the mode registers (SMR0/1) to 111B to select the baud rate based
on external clock input.
Set the SCK0/P02 and SCK1/P05 pins to input (DDR0: bit 2=0, bit 5=0).
Set the SCKE bit in the mode registers (SMR0/1) to "0" to define the pin as "external clock input
pin."
As shown in Figure 17.6-3 "Circuit for baud rate selection by external clock", the baud rate is
selected based on the external clock input from SCK0. Since the internal divide ratio is fixed, the
interval of the external input clock must be changed to change the baud rate.
Figure 17.6-3 Circuit for baud rate selection by external clock
SMR0/1:CS2 to 0="111B"
(External timer selection)
Clock selector
SCK0
SCK1
1/1 (synchronous)
1/16 (asynchronous)
Pin
Baud rate
SMR0/1:MD1
(Selecting clock synchronous/asynchronous operation)
❍ Baud rate calculation formula
Asynchronous baud rate = f/16
Synchronous baud rate = f
f: External clock frequency (f: up to 2 MHz)
393
CHAPTER 17 UART
17.7 Operation of UART
UART has a master-slave type connection communication function (operation mode 1),
in addition to an ordinary bi-directional serial communication function (operation
modes 0, 2).
■ Operation Modes of UART
❍ Operation modes of UART
UART has three operation modes: modes 0 to 2, which can be selected as shown in Table 17.71 "Operation modes of UART" based on the methods of connection and data transfer between
CPUs.
Table 17.7-1 Operation modes of UART
Data length
Operation mode
Synchronization type
No parity used
0
Normal
mode
Stop bit length
Parity used
7 or 8 bits
Asynchronous
1 or 2 bits*2
1
Multiproces
sor mode
8+1*1
−
Asynchronous
2
Normal
mode
8
−
Synchronous
None
−: Setting disabled
*1: "+1" is the address/data selection bit (A/D) used for communication control.
*2: At reception, only one stop bit is detected.
Note:
UART operation mode 1 can only be used by the master unit in a master-slave connection.
❍ Connection between CPUs
Either one-to-one connection (normal mode) or master-slave type connection (multiprocessor
mode) can be selected. Note that the use or nonuse of parity and the type of synchronization in
a selected connection mode must be the same for all CPUs as follows:
In one-to-one connection, two CPUs must use the same method from either operation mode 0
or 2. In asynchronous mode, select operation mode 0 for asynchronous operation or operation
mode 2 for synchronous operation.
In a master-slave connection, use operation mode 1 for the master and select no parity.
❍ Synchronous method
For the operation mode, asynchronous (start/stop synchronous) or clock synchronous mode can
be selected.
394
17.7 Operation of UART
❍ Signaling
UART only uses NRZ (Non Return to Zero) data.
❍ Operation enable
UART uses operation enable bits TXE (send) and RXE (receive) to control each send and
receive operation. If operation becomes disabled, the following actions are taken:
If reception is disabled in receive mode (with data input to the receive shift register), frame
reception ends and the data is stored in the input data registers (SIDR0/1), then operation
stops.
If sending is disabled in send mode (with data output from the send shift register), operation will
stop after no data remains in the output data registers (SODR0/1).
395
CHAPTER 17 UART
17.7.1 Asynchronous Mode Operation (Operation Modes 0, 1)
UART uses asynchronous transfer in operation mode 0 (normal mode) or operation
mode 1 (multiprocessor mode).
■ Asynchronous Mode Operation
❍ Transfer data format
Transfer data always begins with a start bit ("L" level). The specified number of bits are
transferred starting with the LSB, then transfer ends with the stop bit ("H" level).
In operation mode 1, the data length is fixed to 8 bits without parity. Instead of parity, an A/D bit
(address/data selection bit) is added.
Figure 17.7-1 "Transfer data format (operation modes 0, 1)" shows the data format in
asynchronous mode.
Figure 17.7-1 Transfer data format (operation modes 0, 1)
[Operation mode 0]
*
ST
D0
D1
D2
D3
D4
D5
D6
D7/P
SP
ST
D0
D1
D2
D3
D4
D5
D6
D7
A/D
[Operation mode 1]
SP
*: D7 (bit 7) ... No parity
P (parity) ... Parity used
ST: Start bit
SP: Stop bit
A/D: Address/data selection bit in operation mode 1 (multiprocessor mode)
❍ Send operation
When the flag bit for no send data (SSR0/1: TDRE) is "1", send data is written to the output data
register (SODR), provided that send operation is enabled (SCR0/1:TXE=1).
Send operation starts when send data is transferred to the send shift register. In this case, the
TDRE flag is again set to "1" to enable writing the next item of send data. When send interrupt
requests are enabled (SSR0/1: TIE=1), a send interrupt request is output to request loading
data into SODR0/1. The TDRE flag is cleared to "0" when send data is written to SODR0/1.
❍ Receive operation
When receive operation is enabled (SCR0/1: RXE=1), reception is always performed.
Whenever the start bit is detected, one frame is received based on the data format specified by
the control registers (SCR0/1). If an error occurs after one frame is received, an error flag is set,
then the flag bit for receive data available (SSR0/1: RDRF) is set to "1". When receive interrupt
requests are enabled (SSR0/1: RIE=1), a receive interrupt request is output. All flags of the
status registers (SSR0/1) are checked, and when reception had been normal, the input data
registers (SIDR0/1) are read. If an error occurs, error processing is performed. The RDRF flag is
cleared to "0" when receive data is read from SIDR0/1.
396
17.7 Operation of UART
❍ Detecting the start bit
Implement the following settings to detect the start bit:
•
Set the communication line level to H (attach the mark level) before the communication
period.
•
Specify reception permission (RXE = H) while the communication line level is H (mark level).
•
Do not specify reception permission (RXE = H) for periods other than the communication
period (without mark level). Otherwise, data is not received correctly.
•
After the stop bit is detected (the RDRF flag is set to 1), specify reception inhibition (RXE =
L) while the communication line level is H (mark level).
Figure 17.7-2 Normal operation
Communication period
Non-communication period
Mark level
Start bit
SIN
ST
Non-communication period
Stop bit
Data
D0
D1
D0
D1
D2
D3
D4
D5
D6
D7
SP
(Sending 01010101b)
RXE
Receive clock
Sampling clock
Receive clock (8 pulse)
Recognition by the microcontroller
ST
Generating sampling clocks by dividing the receive clock by 16
D2
D3
D4
D5
D6
D7
SP
(Receiving 01010101b)
Note that specifying reception permission at the timing shown below obstructs the correct
recognition of the input data (SIN) by the microcontroller.
•
Example of operation if reception permission (RXE = H) is specified while the communication
line level is L.
Figure 17.7-3 Abnormal operation
Communication period
Non-communication period
Mark level
SIN
(Sending 01010101b)
RXE
Start bit
ST
D0
Non-communication period
Stop bit
Data
D0
D1
D1
D2
D2
D3
D3
D4
D4
D5
D6
D7
D5
D6
D7
SP
SP
Receive clock
Sampling clock
Recognition by the microcontroller
ST recognition
(Receiving 10101010b)
PE,ORE,FRE
Occurrence of a reception error
❍ Stop bit
For sending, use of 1 or 2 stop bits can be selected. The receiving unit always checks only for
the first stop bit.
❍ Error detection
In mode 0, parity errors, overrun errors, and frame errors are detected.
In mode 1, overrun and frame errors are detected, but parity errors are not.
397
CHAPTER 17 UART
❍ Parity 0
Parity may be used only in operation mode 0 (asynchronous, normal mode). Set the PEN bit in
the control registers (SCR0/1) to specify whether parity is to be used, and set the P bit to specify
even parity or odd parity. In operation mode 1 (asynchronous, multiprocessor mode) and
operation mode 2 (synchronous, normal mode), parity cannot be used. Figure 17.7-4 "Send
data with parity enabled" shows the send and receive data when parity is enabled.
Figure 17.7-4 Send data with parity enabled
SIN0/1
ST
SP
Parity error occurred during
reception with even parity
(SCR0/1: P=0)
1 0 1 1 0 0 0 0
SOT0/1
ST
SP
Sending with even parity
(SCR0/1: P=0)
SP
Sending with odd parity
(SCR0/1: P=1)
1 0 1 1 0 0 0 1
SOT0/1
ST
1 0 1 1 0 0 0 0
Data
Parity
ST
: Start bit
SP
: Stop bit
(Note) : Parity cannot be used in operation modes 1 and 2.
398
17.7 Operation of UART
17.7.2 Synchronous Mode Operation (Operation Mode 2)
Transfer uses the clock sync method in UART operation mode 2 (normal mode).
■ Synchronous Mode Operation (Operation Mode 2)
❍ Transfer data format
In synchronous mode, 8-bit data is transferred starting with the LSB, without adding a start bit or
stop bit. Figure 17.7-5 "Transfer data format (in operation mode 2)" shows the data format in
clock synchronous mode.
Figure 17.7-5 Transfer data format (in operation mode 2)
Transferring data according to serial clock output
Mark level
SCK0 output
SOT0
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Send data
Writing send data
TXE
Receiving data according to serial clock input
Mark level
SCK0 input
SIN0
(LSB)
1
0
1
1
0
0
1
0
(MSB)
Receive data
RXE
Reading receive data
❍ Clock supply
In clock synchronous mode (Extended I/O serial), the number of clock pulses must match the
number of send/receive bits.
When an internal clock (dedicated baud rate generator or internal timer) is selected, the
synchronous clock for data reception is automatically generated when data is sent.
When an external clock is selected, any data remaining (SSR0/1: TDRE=0) in the UART output
data registers (SODR0/1) is first checked on the sending side, then a clock pulse for precisely
one byte is supplied externally. Always enter the mark level ("H") before and after a send
operation.
399
CHAPTER 17 UART
❍ Error detection
Only overrun errors are detected, and not parity and framing errors.
❍ Initialization
Each control register takes a setting as listed below in synchronous mode.
•
•
•
Mode registers (SMR0/1)
•
MD1,MD0:"10B"
•
CS2,CS1,CS0: specifies the clock input to the clock selector.
•
SCKE: "1" for the dedicated baud rate generator or internal timer, or "0" for clock output
or an external clock (clock input)
•
SOE: "1" for send, "0" only for receive
Control registers (SCR0/1)
•
PEN:"0"- P, SBL, A/D: These bits have no meaning.
•
CL: "1" (8-bit data)
•
REC: "0" (Clearing error flags for initialization)
•
RXE, TXE: One must be set to "1".
Status register (SSR0/1)
•
RIE: "1" to enable interrupt use; otherwise, "0"
•
TIE: "1" to enable interrupt use; otherwise, "0"
❍ Communication start
Writing to the output data registers (SODR0/1) starts communication. Note that to start
communication (even for reception), temporary data must be input to SODR.
❍ Communication end
When the sending or receiving of one frame of data is completed, the RDRF flag in the status
registers (SSR0/1) is set to "1". For receiving, check the flag bit for overrun errors (SSR0/1:
ORE) and confirm that communication is performed normally.
400
17.7 Operation of UART
17.7.3 Bidirectional Communication Function (Normal Mode)
Operation modes 0 and 2 enable ordinary serial bi-directional communication through
a one-to-one connection. Operation mode 0 uses asynchronous operation; operation
mode 2 uses synchronous operation.
■ Bidirectional Communication Function
To operate UART in normal mode (operation modes 0, 2), set UART1 to operation mode 0 as
shown in Figure 17.7-6 "Setting of UART1 operation mode 0".
Figure 17.7-6 Setting of UART1 operation mode 0
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
PEN P SBL CL AD REC RXE TXE MD1 MD0 CS2 CS1 CS0
SCR1, SMR1
- SCKE SOE
Mode 0
Mode 2
SSR1,
SIDR1/SODR1
Mode 0
Mode 2
PE ORE FRE RDRF TDRE BDS RIE TIE
Set conversion data (for reading)/hold
receive data (for writing)
DDR0
: Bit used
: Bit unused
: Set to "1"
: Set to "0"
: Set to "0" for pin input.
❍ Connection between CPUs
In bi-directional communication, two CPUs are connected as shown in Figure 17.7-7 "Example
of connection for UART1 bi-directional communication".
Figure 17.7-7 Example of connection for UART1 bi-directional communication
SOT1
SOT1
SIN1
SCK1
CPU-1
SIN1
Output
Input
SCK1
CPU-2
401
CHAPTER 17 UART
❍ Communication procedure
Communication can be started from the send side at any time when send data has been
prepared. When send data is received by the receive side, ANS is returned (in this example, for
each byte). Figure 17.7-8 "Example flowchart for bi-directional communication" shows an
example of the operational flow of bi-directional communication.
Figure 17.7-8 Example flowchart for bi-directional communication
(Receiving side)
(Sending side)
Start
Start
Set the operation
mode (0 or 2)
Set the operation mode
(matching with the sending side)
Sending data
Communication with
SODR set to one-byte data
NO
NO
Does
receive data exist?
YES
Does
receive data exist?
Reading and processing
receive data
YES
Reading and processing
receive data
402
Sending data
(ANS)
Send one-byte data
17.7 Operation of UART
17.7.4 Function for Master/Slave Communication
(Multiprocessor Mode)
UART enables communication with multiple CPUs through a master-slave connection
in operation mode 1. UART can only be used as the master, however.
■ Function for Master/Slave Communication
To operate UART in multiprocessor mode (operation mode 1), the settings shown in Figure
17.7-9 "Setting of UART operation mode 1" are required.
Figure 17.7-9 Setting of UART operation mode 1
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
SCR1, SMR1
PEN
P
SBL CL
0
SSR1,
SIDR1/SODR1
1
AD REC RXE TXE MD1 MD0 CS2 CS1 CS0
0
0
1
-
SCKE SOE
0
Set conversion data (for reading)/hold
PE ORE FRE RDRF TDRE BDS RIE TIE receive data (for writing)
DDR0
: Bit used
: Bit unused
: Set to "1"
: Set to "0"
: Set to "0" for pin input.
❍ Connection between CPUs
In the master-slave communication shown in Figure 17.7-10 "Example of connection in UART
master/slave communication", one master CPU and multiple slave CPUs are connected by two
common communication lines to form a communication system. UART1 can only be used as the
master CPU.
Figure 17.7-10 Example of connection in UART master/slave communication
SOT1
SIN1
Master CPU
SOT
SIN
Slave CPU#0
SOT
SIN
Slave CPU#1
403
CHAPTER 17 UART
❍ Function selection
In master-slave type communication, select the operation mode and data transfer method
according to Table 17.7-2 "Selection of master-slave type communication function".
Table 17.7-2 Selection of master-slave type communication function
Operation mode
Master
CPU
Address send/
receive
Mode 1
Data send/receive
404
Slave
CPU
−
Data
Parity
Sync method
Stop bit
None
Asynchronous
1 or 2 bits
A/D = "1" + 8bit address
A/D = "0" + 8bit address
17.7 Operation of UART
❍ Communication procedure
Communication starts when the master CPU sends the address data. Address data is data for
which the A/D bit is set to "1". This data is used to select the slave CPU to be the
communication destination. Each slave CPU runs a program to judge the address data, and, if
the data matches the assigned address, communication with the master CPU is performed (by
transmission of normal data).
Figure 17.7-11 "Flowchart of master/slave type communication" shows a flowchart of masterslave communication (in multiprocessor mode).
Figure 17.7-11 Flowchart of master/slave type communication
(Master CPU)
Start
Set operation mode to "1"
Set SIN pin to serial data input
Set one-byte data (address
data) in D0-D7 to select a slave
CPU, then send this information
(A/D=1)
Set A/D to "0"
Receive operation enabled
Communication with slave
CPU
Has
communication ended?
NO
YES
Communicate
with another slave
CPU?
NO
YES
Receive operation
disabled?
End
405
CHAPTER 17 UART
17.8 Notes on Using UART
This section provides notes on using UART.
■ Notes on Using UART
❍ Allowing operation
UART uses an operation enable bit for TXE (send) and RXE (receive) in the control registers
(SCR0/1) for send and receive operations separately. By default (as initial value), sending and
receiving is prohibited, and must be set to allowed before transfer. When required, transfer can
be prohibited so as to stop transfer.
❍ Setting the communication mode
The communication mode must be set while UART is stopped. When the mode is set during
sending or reception, the correctness of the data sent or received cannot be assured.
❍ Synchronous mode
UART clock synchronous mode (operation mode 2) uses the clock control (I-O extension serial)
method in which no start bit or stop bit is added to data.
❍ Timing of allowing send interrupts
The flag bit for no data (SSR0/1: TDRE) is set to "1"(no send data, send data write enabled) by
default (as initial value). As soon as send interrupt requests are enabled (SSR0/1: TIE=1), a
send interrupt request will be generated immediately. Set the TIE flag to "1" only after the send
data has been prepared.
❍ Receiving in multiprocessor mode
In UART multiprocessor mode, 9-bit format is not allowed for receive operations.
406
17.9 Sample Program for UART
17.9 Sample Program for UART
This section shows a sample program for UART.
■ Sample Program for UART
❍ Specification of processing
This section shows a sample program for which the following processing specification is
assumed:
•
The UART bi-directional communication function (normal mode) is used for a serial send/
receive operation.
•
Communication is performed based on the following conditions: operation mode 0,
asynchronous operation, transfer of 8-bit data, 2 stop bits, and no parity.
•
Communication uses the P00/SIN0 and P01/SOT0 pins.
•
The program uses the dedicated baud rate generator and a baud rate of about 9600 bps.
•
The character 13H is sent from the SOT0 pin and receive with an interrupt.
•
A machine clock frequency of 16 MHz is used.
407
CHAPTER 17 UART
[Coding example]
ICR14
EQU
0000BEH
; UART send/receive interrupt control register
DDR0
EQU
000010H
; Port 0 direction register
SMR
EQU
000034H
; Mode register
SCR
EQU
000035H
; Control register
SIDR
EQU
000036H
; Input data register
SODR
EQU
000036H
; Output data register
SSR
EQU
000037H
; Status register
REC
EQU
SCR:2
; Receive error flag clear bit
;----------Main program------------------------------------------------------CODE
CSEG ABS = 0FFH
START:
;
:
; Stack pointer (SP) assumed to be
; already initialized
AND
CCR,#0BFH
; Interrupt disable
MOV
I:ICR14, #00H
; Interrupt level 0 (highest)
MOV
I:DDR0, #00000000B ; Set SIN0 pin to "input"
MOV
I:SMR, #00010001B ; Operation mode 0 (asynchronous)
; Dedicated baud rate generator used
; (9615 bps selected)
; Clock output disabled, data output enabled
MOV
I:SCR, #00010011B ; No parity, 2 stop bits
; Send/receive operation enabled
; 8-bit data length, receive error flag clear
; Send/receive operation enabled
MOV
I:SSR, #00000010B ; Send interrupt disabled, receive
; interrupt enabled
MOV
I:SODR, #13H
; Writing send data
MOV
ILM, #07H
; ILM in PS set to level 7
OR
CCR, #40H
; Interrupts enabled
LOOP:
MOV
A,#00H
; Infinite loop
MOV
A,#01H
BRA
LOOP
;----------Interrupt program-------------------------------------------------WARI:
MOV
A, SIDR
; Read receive data
CLRB I:REC
; Clear receive interrupt request flag
;
:
;
User processing
;
:
RETI
; Return from interrupt
CODE
ENDS
;----------Vector setting----------------------------------------------------VECT
CSEG ABS=0FFH
ORG
0FF60H
; Set vector to interrupt #39 (27H)
DSL
WARI
ORG
0FFDCH
; Reset vector setting
DSL
START
DB
00H
; Set single-chip mode
VECT
ENDS
408
CHAPTER 18
CAN CONTROLLER
This chapter describes an overview of the CAN controller and its functions.
18.1 "CAN Controller Features"
18.2 "Block Diagram of CAN Controller"
18.3 "Types of CAN Controller Registers"
18.4 "Transmission Via CAN Controller"
18.5 "Reception Via CAN Controller"
18.6 "Notes on Using CAN Controller"
18.7 "Transmission via Message buffer (x)"
18.8 "Reception via Message buffer (x)"
18.9 "Specifying the Multi-Level Message Buffer Configuration"
18.10 "CAN WAKE UP Function"
18.11 "Sample Program for CAN Controller"
18.12 "Precautions when Using CAN Controller"
409
CHAPTER 18 CAN CONTROLLER
18.1 CAN Controller Features
The CAN controller is a module that is integrated into the 16-bit microcomputer F2MC16LX. Controller Area Network (CAN) is standard protocol used for serial
communications between controllers in automobiles and commonly applied in various
fields of the industry.
■ Features of CAN Controller
The CAN controller has the following features:
410
•
Conforms to CAN specifications version 2.0 (parts A and B). Supports send/receive
operations in standard frame and extended frame format.
•
Supports data frame transfer based on remote frame reception.
•
Provides 16 send and receive message buffers, 29-bit ID and 8-byte data, Multi-level
message buffer structure
•
Supports full-bit compare, full-bit mask, and partial-bit mask filtering. Standard frame or
extended frame format provides two mask registers for reception.
•
Transmission speed is 10 Kbps to 1 Mbps (A minimum 8 MHz machine clock is required if
1 Mbps is used).
•
CAN WAKE UP function
•
The CAN controller in the MB90420G series has two built-in channels and the CAN
controller in the MB90425G series has one built-in channel.
18.2 Block Diagram of CAN Controller
18.2 Block Diagram of CAN Controller
Figure 18.2-1 "Block diagram of CAN controller" shows a block diagram of the CAN
controller.
■ Block Diagram of CAN Controller
Figure 18.2-1 Block diagram of CAN controller
F2 MC-16LX bus
Clock
TQ (operation clock)
Prescaler frequency
division of 1 to 64
SYNC,TSELG1,TSEG2
Bit timing generation
PSC
PR
BTR
PH
PSJ
TOE
TS
RS
CSR
NIE
NT
Node status
change interrupt
generation
Node status
change interrupt
Error
control
NSL,0
RTEC
BVALR
TREQR
TBFx clear
Send buffer
judgment
TBFx
Send/receive
sequencer
Acceptance
Data
counter filter control
TDLC RDLC IDSEL
BITER,STFER,
CRCER,FRMER,
ACKER
TBFx
TCANR
TRTRR
TCR
TIER
RCR
RIER
RRTRR
ROVRR
Error frame
generation
Overload
frame
generation
Receive completed,
interrupt generation
RBFx, TBFx, set, clear
Transmit complete
interrupt
Receive complete
interrupt
TDLC
TX
Stuffing
CRC
ACK
generation generation
CRCER
RDLC CRC generation/error check
Receive shift
register
RBFx, set, IDSEL
Output
driver
ARBLOST
Send shift
register
RFWTR
TBFx, set, clear
Transmit complete
interrupt generation
RBFx, set
IDLE, SUSPEND,
send, receive,
ERR, OVRLD
Bus state
machine
HALT
STFER
Destuffing/stuffing error
check
AMSR
AMR0
AMR1
IDCR0 to 15,
DLCR0 to 15,
DTR0 to 15,
RAM
LEIR
0
1
Acceptance
filter
Receive buffer judgment
RBFx
ARBLOST
BITER
ACKER
RAM address
generation
RBFx,TBFx,RDLC,TDLC,IDSEL
FRMER
Arbitration
check
Bit error
check
Verify error
check
Format error
check
PH1
Input
latch
RX
411
CHAPTER 18 CAN CONTROLLER
18.3 Types of CAN Controller Registers
The CAN controller has the following four types of registers:
• General control registers
• Message buffer control registers
• Message buffers
• CAN WAKE UP control register
■ General control registers
The four types of general control registers are:
•
Control status register (CSR)
•
Last event indication register (LEIR)
•
Receive and transmit error counter (RTEC)
•
Bit timing register (BTR)
Table 18.3-1 "General control registers" lists the general control registers.
Table 18.3-1 General control registers
Address
Abbreviation
Access
Initial value
Control status register
CSR
(R/W, R)
00---000 0----0-1
Last event indication
register
LEIR
(R/W)
-------- 000-0000
Receive and transmit error
counter
RTEC
(R)
00000000 00000000
BTR
(R/W)
-1111111 11111111
Register
CAN0
CAN1
003C00H
003D00H
003C01H
003D01H
003C02H
003D02H
003C03H
003D03H
003C04H
003D04H
003C05H
003D05H
003C06H
003D06H
003C07H
003D07H
412
Bit timing register
18.3 Types of CAN Controller Registers
■ Message Buffer Control Registers
The 14 types of message buffer control registers are:
•
Message buffer valid register (BVALR)
•
IDE register (IDER)
•
Transmit request register (TREQR)
•
Transmit RTR register (TRTRR)
•
Remote frame transmission wait Register (RFWTR)
•
Transmission cancel register (TCANR)
•
Transmission complete register (TCR)
•
Transmission interrupt enable register (TIER)
•
Receive complete register (RCR)
•
Remote request transmission register (RRTRR)
•
Receive overrun register (ROVRR)
•
Receive interrupt enable register (RIER)
•
Acceptance mask selection register (AMSR)
•
Acceptance mask registers 0 and 1 (AMR0, AMR1)
Table 18.3-2 "Message buffer control registers" lists the message buffer control registers.
Table 18.3-2 Message buffer control registers
Address
Abbreviation
Access
Initial value
Message buffer valid
register
BVALR
(R/W)
00000000 00000000
Transmission request
register
TREQR
(R/W)
00000000 00000000
Transmission cancel
register
TCANR
(W)
00000000 00000000
Transmission complete
register
TCR
(R/W)
00000000 00000000
Receive complete
register
RCR
(R/W)
00000000 00000000
Remote request
receive register
RRTRR
(R/W)
00000000 00000000
Receive overrun
register
ROVRR
(R/W)
00000000 00000000
Register
CAN0
CAN1
000040H
000070H
000041H
000071H
000042H
000072H
000043H
000073H
000044H
000074H
000045H
000075H
000046H
000076H
000047H
000077H
000048H
000078H
000049H
000079H
00004AH
00007AH
00004BH
00007BH
00004CH
00007CH
00004DH
00007DH
413
CHAPTER 18 CAN CONTROLLER
Table 18.3-2 Message buffer control registers (Continued)
Address
Abbreviation
Access
Initial value
Receive interrupt
enable register
RIER
(R/W)
00000000 00000000
IDE register
IDER
(R/W)
XXXXXXXX XXXXXXXX
Transmission RTR
register
TRTRR
(R/W)
00000000 00000000
Remote frame
reception wait register
RFWTR
(R/W)
XXXXXXXX XXXXXXXX
Transmission interrupt
enable register
TIER
(R/W)
00000000 00000000
Register
CAN0
CAN1
00004EH
00007EH
00004FH
00007FH
003C08H
003D08H
003C09H
003D09H
003C0AH
003D0AH
003C0BH
003D0BH
003C0CH
003D0CH
003C0DH
003D0DH
003C0EH
003D0EH
003C0FH
003D0FH
003C10H
003D10H
003C11H
003D11H
003C12H
003D12H
003C13H
003D13H
003C14H
003D14H
003C15H
003D15H
003C16H
003D16H
003C17H
003D17H
003C18H
003D18H
003C19H
003D19H
003C1AH
003D1AH
003C1BH
003D1BH
414
XXXXXXXX XXXXXXXX
Acceptance mask
selection register
AMSR
(R/W)
XXXXXXXX XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask
register 0
AMR0
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
Acceptance mask
register 1
AMR1
(R/W)
XXXXX--- XXXXXXXX
18.3 Types of CAN Controller Registers
■ Message Buffers
The three types of message buffers are:
•
ID Register x (x = 0 to 15) (IDRx)
•
DLC Register x (x = 0 to 15) (DLCRx)
•
Data Register x (x = 0 to 15) (DTRx)
Table 18.3-3 "Message buffers (ID registers)" lists the ID register message buffers, Table 18.3-4
"Message buffers (DLC registers)" lists the DLC register message buffers, and Table 18.3-5
"Message buffers (DT registers)" lists the DT register message buffers.
Table 18.3-3 Message buffers (ID registers)
Address
Register
CAN0
CAN1
003A00H to
003A1FH
003B00H to
003B1FH
003A20H
003B20H
003A21H
003B21H
003A22H
003B22H
003A23H
003B23H
003A24H
003B24H
003A25H
003B25H
003A26H
003B26H
003A27H
003B27H
003A28H
003B28H
003A29H
003B29H
003A2AH
003B2AH
003A2BH
003B2BH
003A2CH
003B2CH
003A2DH
003B2DH
003A2EH
003B2EH
003A2FH
003B2FH
003A30H
003B30H
003A31H
003B31H
003A32H
003B32H
003A33H
003B33H
General-purpose RAM
Abbreviation
Access
Initial value
−
(R/W)
XXXXXXXX to XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 0
IDR0
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 1
IDR1
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 2
IDR2
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 3
IDR3
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 4
IDR4
(R/W)
XXXXX--- XXXXXXXX
415
CHAPTER 18 CAN CONTROLLER
Table 18.3-3 Message buffers (ID registers) (Continued)
Address
Register
CAN0
CAN1
003A34H
003B34H
003A35H
003B35H
003A36H
003B36H
003A37H
003B37H
003A38H
003B38H
003A39H
003B39H
003A3AH
003B3AH
003A3BH
003B3BH
003A3CH
003B3CH
003A3DH
003B3DH
003A3EH
003B3EH
003A3FH
003B3FH
003A40H
003B40H
003A41H
003B41H
003A42H
003B42H
003A44H
003B44H
003A45H
003B45H
003A46H
003B46H
003A47H
003B47H
003A48H
003B48H
003A49H
003B49H
003A4AH
003B4AH
003A4BH
003B4BH
003A4CH
003B4CH
003A4DH
003B4DH
003A4EH
003B4EH
003A4FH
003B4FH
003A50H
003B50H
003A51H
003B51H
003A52H
003B52H
003A53H
003B53H
416
Abbreviation
Access
Initial value
XXXXXXXX XXXXXXXX
ID register 5
IDR5
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 6
IDR6
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 7
IDR7
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 8
IDR8
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 9
IDR9
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 10
IDR10
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 11
IDR11
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 12
IDR12
(R/W)
XXXXX--- XXXXXXXX
18.3 Types of CAN Controller Registers
Table 18.3-3 Message buffers (ID registers) (Continued)
Address
Register
CAN0
CAN1
003A54H
003B54H
003A55H
003B55H
003A56H
003B56H
003A57H
003B57H
003A58H
003B58H
003A59H
003B59H
003A5AH
003B5AH
003A5BH
003B5BH
003A5CH
003B5CH
003A5DH
003B5DH
003A5EH
003B5EH
Abbreviation
Access
Initial value
XXXXXXXX XXXXXXXX
ID register 13
IDR13
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 14
IDR14
(R/W)
XXXXX--- XXXXXXXX
XXXXXXXX XXXXXXXX
ID register 15
IDR15
(R/W)
XXXXX--- XXXXXXXX
Table 18.3-4 Message buffers (DLC registers)
Address
CAN0
CAN1
003A60H
003B60H
003A61H
003B61H
003A62H
003B62H
003A63H
003B63H
003A64H
003B64H
003A65H
003B65H
003A66H
003B66H
003A67H
003B67H
003A68H
003B68H
003A69H
003B69H
003A6AH
003B6AH
003A6BH
003B6BH
003A6CH
003B6CH
003A6DH
003B6DH
Register
Abbreviation
Access
Initial value
DLC register 0
DLCR0
(R/W)
---- XXXX
DLC register 1
DLCR1
(R/W)
---- XXXX
DLC register 2
DLCR2
(R/W)
---- XXXX
DLC register 3
DLCR3
(R/W)
---- XXXX
DLC register 4
DLCR4
(R/W)
---- XXXX
DLC register 5
DLCR5
(R/W)
---- XXXX
DLC register 6
DLCR6
(R/W)
---- XXXX
417
CHAPTER 18 CAN CONTROLLER
Table 18.3-4 Message buffers (DLC registers) (Continued)
Address
CAN0
CAN1
003A6EH
003B6EH
003A6FH
003B6FH
003A70H
003B70H
003A71H
003B71H
003A72H
003B72H
003A73H
003B73H
003A74H
003B74H
003A75H
003B75H
003A76H
003B76H
003A77H
003B77H
003A78H
003B78H
003A79H
003B79H
003A7AH
003B7AH
003A7BH
003B7BH
003A7CH
003B7CH
003A7DH
003B7DH
003A7EH
003B7EH
003A7FH
003B7FH
Register
Abbreviation
Access
Initial value
DLC register 7
DLCR7
(R/W)
---- XXXX
DLC register 8
DLCR8
(R/W)
---- XXXX
DLC register 9
DLCR9
(R/W)
---- XXXX
DLC register 10
DLCR10
(R/W)
---- XXXX
DLC register 11
DLCR11
(R/W)
---- XXXX
DLC register 12
DLCR12
(R/W)
---- XXXX
DLC register 13
DLCR13
(R/W)
---- XXXX
DLC register 14
DLCR14
(R/W)
---- XXXX
DLC register 15
DLCR15
(R/W)
---- XXXX
Table 18.3-5 Message buffers (DT registers)
Address
Register
Abbreviation
Access
Initial value
CAN0
CAN1
003A80H
to
003A87H
003B80H
to
003B87H
Data register 0 (8 bytes)
DTR0
(R/W)
XXXXXXXX to XXXXXXXX
003A88H
to
003A8FH
003B88H
to
003B8FH
Data register 1 (8 bytes)
DTR1
(R/W)
XXXXXXXX to XXXXXXXX
003A90H
to
003A97H
003B90H
to
003B97H
Data register 2 (8 bytes)
DTR2
(R/W)
XXXXXXXX to XXXXXXXX
418
18.3 Types of CAN Controller Registers
Table 18.3-5 Message buffers (DT registers) (Continued)
Address
Register
Abbreviation
Access
Initial value
CAN0
CAN1
003A98H
to
003A9FH
003B98H
to
003B9FH
Data register 3 (8 bytes)
DTR3
(R/W)
XXXXXXXX to XXXXXXXX
003AA0H
to
003AA7H
003BA0H
to
003BA7H
Data register 4 (8 bytes)
DTR4
(R/W)
XXXXXXXX to XXXXXXXX
003AA8H
to
003AAFH
003BA8H
to
003BAFH
Data register 5 (8 bytes)
DTR5
(R/W)
XXXXXXXX to XXXXXXXX
003AB0H
to
003AB7H
003BB0H
to
003BB7H
Data register 6 (8 bytes)
DTR6
(R/W)
XXXXXXXX to XXXXXXXX
003AB8H
to
003ABFH
003BB8H
to
003BBFH
Data register 7 (8 bytes)
DTR7
(R/W)
XXXXXXXX to XXXXXXXX
003AC0H
to
003AC7H
003BC0H
to
003BC7H
Data register 8 (8 bytes)
DTR8
(R/W)
XXXXXXXX to XXXXXXXX
003AC8H
to
003ACFH
003BC8H
to
003BCFH
Data register 9 (8 bytes)
DTR9
(R/W)
XXXXXXXX to XXXXXXXX
003AD0H
to
003AD7H
003BD0H
to
003BD7H
Data register 10 (8 bytes)
DTR10
(R/W)
XXXXXXXX to XXXXXXXX
003AD8H
to
003ADFH
003BD8H
to
003BDFH
Data register 11 (8 bytes)
DTR11
(R/W)
XXXXXXXX to XXXXXXXX
003AE0H
to
003AE7H
003BE0H
to
003BE7H
Data register 12 (8 bytes)
DTR12
(R/W)
XXXXXXXX to XXXXXXXX
003AE8H
to
003AEFH
003BE8H
to
003BEFH
Data register 13 (8 bytes)
DTR13
(R/W)
XXXXXXXX to XXXXXXXX
003AF0H
to
003AF7H
003BF0H
to
003BF7H
Data register 14 (8 bytes)
DTR14
(R/W)
XXXXXXXX to XXXXXXXX
003AF8H
to
003AFFH
003BF8H
to
003BFFH
Data register 15 (8 bytes)
DTR15
(R/W)
XXXXXXXX to XXXXXXXX
419
CHAPTER 18 CAN CONTROLLER
■ CAN WAKE UP Control Register
There is one type of CAN WAKE UP control register:
•
CAN WAKE UP control register (CWUCR)
Table 18.3-6 "CAN WAKE UP control register" shows the specifications for the CWUCR.
Table 18.3-6 CAN WAKE UP control register
Address
Register
420
CAN0
CAN1
003EH
–
CAN WAKE UP control
register
Abbreviation
Access
Initial value
CWUCR
(R/W)
-------0
18.3 Types of CAN Controller Registers
18.3.1 Control Status Register (CSR)
Bit operation instructions (read - modify - write) cannot be used for the control status
register (CSR).
■ Bit Configuration of Control Status Register (CSR)
Figure 18.3-1 "Bit configuration of control status register (CSR)" shows the bit configuration of
the control status register (CSR).
Figure 18.3-1 Bit configuration of control status register (CSR)
Address : 003C01H (CAN0)
Address : 003D01H (CAN1)
Reading/writing
Initial value
Address: 003C00H (CAN0)
Address: 003D00H (CAN1)
Reading/writing
Initial value
15
TS
14
RS
13
-
12
-
11
-
10
NT
9
NS1
8
NS0
(R)
(0)
(R)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
(R)
(0)
(R)
(0)
7
TOE
6
-
5
-
4
-
3
-
2
NIE
1
-
0
HALT
(R/W)
(0)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(0)
(-)
(-)
(R/W)
(1)
[bit 15] TS: Transmission Status bit
This bit indicates whether a message is being sent.
- 0: No message being sent.
- 1: Message being sent.
This bit is "0" even if an "error frame" or "overload frame" is sent.
[bit 14] RS: receive status bit
This bit indicates whether a message is being received.
- 0: No message being received.
- 1: Message being received.
his bit is "1" while a message is transferred over the bus. Therefore, this bit is "1" whenever a
message is sent. This does not necessarily indicate whether a receive message is
transferred through an acceptance filter.
When this bit is "0", bus operation is halted (HALT = 0), the bus enters intermission/bus idle
mode, or an error/overload frame is transferred over the bus.
421
CHAPTER 18 CAN CONTROLLER
[bit 10] NT: node status transition flag
This bit is "1" if the node status changes to "increment" or from "bus-off" to "error active".
In other words, NT is set to "1" when the node status changes as follows. (The values in
parenthesis show the values of NS1 and NS0.)
- from error active ("00") to warning ("01")
- from warning ("01") to error passive ("10")
- from error passive ("10") to bus-off ("11")
- from bus-off ("11") to error active ("00")
When the node status transition interrupt enable bit (NIE) is set to "1", an interrupt is
generated.
By writing "0", NT is cleared to "0". Writing "1" is ignored. Read-modify-write instructions
return "1".
[bits 9 to 8] NS1,NS0: bits 1 and 0 of node status
NS1 and NS0 indicate the current node status.
Table 18.3-7 "Relationship between NS1/NS0 and node status" shows this relationship.
Table 18.3-7 Relationship between NS1/NS0 and node status
NS1
NS0
Node status
0
0
Error active
0
1
Warning (error active)
1
0
Error passive
1
1
Bus-off
Note:
Warning (error active) is included in the status "error active" described in CAN Specifications
2.0B for the node status, indicating that the transmit error counter or receive error counter
exceeds 96. Figure 18.3-2 "State transition diagram for node status" shows a transition
diagram for the states of the node status.
422
18.3 Types of CAN Controller Registers
Figure 18.3-2 State transition diagram for node status
Hardware reset
Error active
REC 96 or
TEC 96
Warning
REC: Receive Error Counter
TEC: Transmit error Counter
After the HALT bit in CSR is set to
"0", 11 consecutive bits of H level
(reset passive bits) are input 128
times to the receive input pin (RX).
REC<96 or
TEC<96
REC 128 or
TEC 128
REC<128 or
TEC<128
Error
passive
Bus-off
TEC>=256
[bit 7] TOE: Transmission output enable bit
When TOE is set to "1", the general-purpose port pin is used as a CAN controller send pin.
- 0: General-purpose port pin
- 1: CAN controller send pin
[bit 2] NIE: Node status transition interrupt enable bit
NIE enables or disables node status transition interrupts (NT = 1).
- 0: Disable node status transition interrupts.
- 1: Enable node status transition interrupts.
[bit 0] HALT: bus operation stop bit
HALT is used to set or release bus operation stop or indicate the bus status.
423
CHAPTER 18 CAN CONTROLLER
■ Bus operation stop bit (HALT = 1)
The bus operation stop bit is used to set or release bus operation stop, or indicate the bus
status.
❍ Condition to stop bus operation (HALT = 1)
The three conditions to stop bus operation (HALT = 1) are:
•
Hardware reset
•
Node status changes to bus-off
•
HALT was set to "1" by writing
Notes:
•
Bus operation must be stopped by setting HALT to "1" by writing before the F2MC-16LX
enters a low-power consumption mode (in stop mode, clock mode, hardware standby mode).
When HALT is set to "1" during transmission, bus operation will stop after transmission is
completed (HALT = 1). When HALT is set to "1" during reception, bus operation stops
immediately (HALT = 1). When a message received is being stored in Message Buffer (x),
bus operation will stop after the message is stored (HALT = 1).
•
Always confirm that bus operation stops after HALT is read.
❍ Condition to clear bus operation stop (HALT = 0)
Setting HALT to "0" releases bus operation stop.
Notes:
•
The bus operation stop state (caused by hardware reset or setting HALT to "1") is cleared
after HALT was cleared to "0", then 11 consecutive H-level (recessive) bits are input to the
receive input pin (RX).
•
The bus operation stop state caused when node status changes to bus-off is released after
HALT is set to "0", then 11 consecutive H level (recessive) bits are input 128 times to the
receive input pin (RX). Therefore, if both the transmission and receive error counters reach
"0", the node status changes to error active.
■ State between bus operation stops (HALT = 1)
States where bus operation stops are:
•
Bus is disabled from performing such operations as send and receive.
•
The transmission output pin (TX) outputs H level (recessive bit).
•
Other register and error counter values do not change.
Note:
The contents of the bit timing register (BTR) must be set during bus operation stops (HALT =
1).
424
18.3 Types of CAN Controller Registers
18.3.2 Last Event Indication Register (LEIR)
The last event indication register (LEIR) indicates the last event.
NTE, TCE and RCE are mutually exclusive. When the last event bit is set to "1", other
bits are set to "0".
■ Bit Configuration of Last Event Indication Register (LEIR)
Figure 18.3-3 "Bit configuration of last event indication register (LEIR)" shows the bit
configuration of the last event indication register (LEIR).
Figure 18.3-3 Bit configuration of last event indication register (LEIR)
Address : 003C02 H (CAN0)
Address : 003D02 (CAN1)
H
Reading/writing
Initial value
7
NTE
6
TCE
5
RCE
4
-
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(-)
(-)
3
MBP3
2
MBP2
1
MBP1
0
MBP0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
[bit 7] NTE: Node status transition event bit
When NTE is "1", the node status transition was the last event.
NTE is set to "1" at the same time when the NT bit in the control status register (CSR) is set.
NTE is set to "1" independently of the CSR node status transition interrupt enable bit (NIE).
When NTE is set to "0", then NIE is set to "0". Writing "1" is ignored.
Read-modify-write instructions return "1".
[bit 6] TCE: Transmission complete event bit
When TCE is "1", transmission completion was the last event.
TCE is set to "1" whenever any transmission complete register (TCR) bit is set. TCE is set to
"1" independently of the bits of the transmission interrupt enable register (TIER).
Setting TCE to "0" will in turn set TCR to "0". Writing "1" is ignored.
Read-modify-write instructions return "1".
When this bit is "1", bits MBP3 to MBP0 indicate the number of the message buffer for which
a send operation was completed.
[bit 5] RCE: Receive complete event bit
When RCE is "1", indicates that completion of reception was the last event.
RCE is set to "1" whenever any receive complete register (RCR) bit is set. RCE is set to "1"
independently of the bits of the reception interrupt enable register (RIER).
When RCE is set to "0", RCR is set to "0". Writing "1" is ignored.
Read-modify-write instructions return "1".
When RCE is "1", bits MBP3 to MBP0 indicate the number of the message buffer for which
reception was completed.
425
CHAPTER 18 CAN CONTROLLER
[bits 3 to 0] MBP3 to MBP0: Message buffer pointer bits
When TCE or RCE is "1", bits MBP3 to MBP0 indicate the number of the corresponding
message buffer (0 to 15).
When NTE is "1", bits MBP3 to MBP0 have no meaning.
MBP3 to MBP0 are cleared to "0" by write operations. Writing "1" is ignored.
Read-modify-write instructions return "1".
When LEIR is accessed from within the CAN interrupt handler, the event that causes an
interrupt is not necessarily the same as that indicated by LEIR: At the time an interrupt to
LEIR access is requested from within the interrupt handler, another CAN event may occur.
426
18.3 Types of CAN Controller Registers
18.3.3 Receive and Transmit error Counter (RTEC)
The receive and transmit error counter (RTEC) indicates the transmit error count and
receive error count defined by the CAN specifications. RTEC is a read-only register.
■ Bit Configuration of Receive Error Counter and Transmit Error Counter (RTEC)
Figure 18.3-4 "Bit configuration of receive error counter and transmit error counter (RTEC)"
shows the bit configuration of the receive error counter and transmit error Counter (RTEC).
Figure 18.3-4 Bit configuration of receive error counter and transmit error counter (RTEC)
Address : 003C05 H (CAN0)
Address: 003D05 H (CAN1)
Reading/writing
Initial value
15
TEC7
14
TEC6
13
TEC5
12
TEC4
11
TEC3
10
TEC2
9
TEC1
8
TEC0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
Address: 003C04 H (CAN0)
Address: 003D04 H (CAN1)
Reading/writing
Initial value
7
REC7
6
REC6
5
REC5
4
REC4
3
REC3
2
REC2
1
REC1
0
REC0
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
(R)
(0)
[bits 15 to 8] TEC7 to TEC0: Transmit error Counter
TEC7 to TEC0 act as transmit error counter.
TEC7 to TEC0 indicate 0 to 7 for a counter value greater than 256. Subsequent increments
of the counter value are not counted. In such case, the node status "error passive" is
indicated (CSR: NS1 and NS0 = 11).
[bits 7 to 0] REC7 to REC0: Receive error counter
REC7 to REC0 act as receive error counter.
REC7 to REC0 indicate 0 to 7 for a counter value greater than 256. Subsequent increments
of the counter value are added. In such case, the node status "bus-off" is indicated (CSR:
NS1 and NS0 = 10).
427
CHAPTER 18 CAN CONTROLLER
18.3.4 Bit Timing Register (BTR)
The Bit Timing Register (BTR) is used to specify the prescaler and bit timing.
■ Bit Configuration of Bit Timing Register (BTR)
Figure 18.3-5 "Bit configuration of bit timing register (BTR)" shows the bit configuration of the bit
timing register (BTR).
Figure 18.3-5 Bit configuration of bit timing register (BTR)
Address : 003C07 H (CAN0)
Address : 003D07 H (CAN1)
Reading/writing
Initial value
Address : 003C06 H (CAN0)
Address : 003D06 H (CAN1)
Reading/writing
Initial value
15
-
14
TS2.2
13
TS2.1
12
TS2.0
11
TS1.3
10
TS1.2
9
TS1.1
8
TS1.0
(-)
(-)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
7
RSJ1
6
RSJ0
5
PSC5
4
PSC4
3
PSC3
2
PSC2
1
PSC1
0
PSC0
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
(R/W)
(1)
Note:
BTR must be set in bus operation halt mode (HALT = 1).
[bits 14 to 12] TS2.2 to TS2.0: Time Segment 2 setting bits 2 to 0
Bits TS2.2 to TS2.0 specify time segment 2 (TSEG2) by dividing the unit time (TQ) by
[(TS2.2 to TS2.0)+1]. Time segment 2 is equal to phase buffer segment 2 (PHASE_SEG2) in
the CAN specifications.
[bits 11 to 8] TS1.3 to TS1.0: Time segment 1 setting bits 3 to 0
Bits TS1.3 to TS1.0 divide unit time (TQ) by [(TS1.3 to TS1.0)+1] to specify time segment 1
(TSEG1). Time segment 1 is equal to the propagation segment (PROP_SEG) + phase buffer
segment 1 (PHASE_SEG1) in the CAN specifications.
[bits 7 to 6] RSJ1 to RSJ0: Re-synchronous jump width setting bits 1 to 0
Bits RSJ1 to RSJ0 divide the unit time (TQ) by [(RSJ1 to RSJ0)+1] to specify a resynchronous jump width.
[bits 5 to 0] PSC5 to PSC0: Prescaler setting bits 5 to 0
Bits PSC5 to PSC0 divide the input clock by [(PSC5 to PSC0)+1] to specify the unit time of
the CAN controller.
Figure 18.3-6 "Bit time segments according to CAN specifications" and Figure 18.3-7 "Bit
time segments in the CAN controller" show each bit time segment for the CAN specifications
and the CAN controller.
428
18.3 Types of CAN Controller Registers
Figure 18.3-6 Bit time segments according to CAN specifications
Nominal bit time
SYNC_SEG
PROP_SEG
PHASE_SEG1 PHASE_SEG2
Sample point
Figure 18.3-7 Bit time segments in the CAN controller
Nominal bit time
SYNC_SEG
TSEG1
PHASE_SEG2
Sample point
The following shows the relationship between PSC=PSC5 to PSC0, TSI=TS1.3 to TS1.0,
TS2=TS2.2 to TS1.0, RSJ=RSJ1 and RSJ0 with respect to the frequency-division input clock
(CLK), unit time (TQ), bit time (BT), synchronous segment (SYNC_SEG), time segment 1/2
(TSEG1, TSEG2), and re-synchronous jump width [(RSJ1+RSJ0)+1].
TQ = (PSC+1) x CLK
BT = SYNC_SEG + TSEG1 + TSEG2
= (1 + (TS1+1) + (TS2+1)) ~TQ
= (3 + TS1+TS2) x TQ
RSJW = (RSJ + 1) x TQ
Normal operation must satisfy the following conditions:
BT
8TQ
TSEG2
RSJW
TSEG2
2TQ
When PSC = 0
TSEG1
When PSC
5TQ
1
TSEG1
2TQ
TSEG1
RSJW
The following shows sample BTR settings.
429
CHAPTER 18 CAN CONTROLLER
■ Sample BTR Settings
The following shows sample BTR settings.
❍ Applicable conditions
•
Communication speed (BT): 100 kbps (10 µs)
•
1TQ: 0.5 µs (1/20 of 1BT)
•
Re-synchronous jump width (RSJW): 4TQ
•
Delay time:50 ns
•
Internal operation frequency:16 MHz (0.0625 µs)
•
Sample setting
❍ Sample setting
The following procedure is used to specify the setting value of each bit.
TQ=(PSC+1)
CLK
0.5=(PSC+1)
0.0625
PSC=0.5/0.0625-1=7
Therefore, the setting value for PSC5 to PSC0 is as follows:
PSC5 to PSC0=000111B
RSJW=(RSJ+1)
4TQ=(RSJ+1)
TQ
TQ
RSJ=4-1=3
Therefore, the setting value for RSJ1 to RSJ0 is as follows:
RSJ1 to RSJ0=11B
TSEG2
(TS2+1)
RSJW
TS2
TQ
4-1
4TQ
3
Therefore, the setting value for TS2.2 to TS2.0 is as follows:
TS2.2 to TS2.0
TSEG1
(TS1+1)
TS1
011B
RSJW
TQ
4TQ
3
Therefore, the setting value for TS1.3 to TS1.0 is as follows:
TS1.3 to TS1.0 0100B
The requirement of a communication speed of 100 kbps, together with
allows the following combinations:
- TS1.3 to TS1.0=1010B
430
- TS1.3 to TS1.0=1011B
TS2.2 to TS2.0=111B
TS2.2 to TS2.0=110B
- TS1.3 to TS1.0=1100B
TS2.2 to TS2.0=101B
- TS1.3 to TS1.0=1101B
TS2.2 to TS2.0=100B
- TS1.3 to TS1.0=1110B
TS2.2 to TS2.0=011B
and
,
18.3 Types of CAN Controller Registers
18.3.5 Message Buffer Valid Register (BVALR)
The Message Buffer Valid Register (BVALR) is used to specify the validity of Message
Buffer (x) for indicating the buffer status.
■ Bit Configuration of Message Buffer Valid Register (BVALR)
Figure 18.3-8 "Bit configuration of message buffer valid register (BVALR)" shows the bit
configuration of the message buffer valid register (BVALR).
Figure 18.3-8 Bit configuration of message buffer valid register (BVALR)
15
14
13
12
11
10
9
Address : 000041 H (CAN0)
Address : 000071 H (CAN1) BVAL15 BVAL14 BVAL13 BVAL12 BVAL11 BVAL10 BVAL9
Reading/writing => (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W)
(0)
(0)
(0)
(0)
(0)
(0)
(0)
Initial value =>
Address : 000040 H (CAN0)
Address : 000070 H (CAN1)
Reading/writing =>
Initial value =>
8
BVAL8
(R/W)
(0)
7
6
5
4
3
2
1
0
BVAL7
BVAL6
BVAL5
BVAL4
BVAL3
BVAL2
BVAL1
BVAL0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
The message buffer valid register (BVALR) consists of 16 bits, each of which indicates whether
the contents of the corresponding message buffer is valid or invalid.
•
0: Message buffer (x) invalid
•
1: Message buffer (x) valid
When Message Buffer (x) is set to invalid ("0"), no messages are sent or received.
When the buffer is set to invalid ("0") during a send operation, the operation is completed, or the
buffer set to invalid (BVALx = 0) if the operation ends with an error.
When the buffer contents is set to invalid ("0") while a receive operation is in progress, the
buffer value becomes invalid immediately (BVALx = 0). However, if a received message is
currently being stored in Message Buffer (x), Message Buffer (x) becomes invalid after the
message has been stored.
Notes:
•
"x" indicates the message buffer number (x = 0 to 15).
•
When (BVALx) is set to "0" to invalidate Message Buffer (x), bit operation instructions are
disabled until the corresponding bit is set to "0".
•
To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller
is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section 18.12
"Precautions when Using CAN Controller".
431
CHAPTER 18 CAN CONTROLLER
18.3.6 IDE Register (IDER)
The IDE register (IDER) is used to specify the frame format used by Message Buffer (x)
in send and receive operations.
■ Bit Configuration of IDE Register (IDER)
Figure 18.3-9 "Bit configuration of IDE register (IDER)" shows the bit configuration of the IDE
register (IDER).
Figure 18.3-9 Bit configuration of IDE register (IDER)
Address: 003C09 H (CAN0)
Address: 003D09 H (CAN1)
Reading/writing
Initial value
15
IDE15
14
IDE14
13
IDE13
12
IDE12
11
IDE11
10
IDE10
9
IDE9
8
IDE8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
Address: 003C08 H (CAN0)
Address: 003D08 H (CAN1)
Reading/writing
Initial value
7
IDE7
6
IDE6
5
IDE5
4
IDE4
3
IDE3
2
IDE2
1
IDE1
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
0
IDE0
(R/W)
(X)
The IDE register (IDER) consists of 16 bits, each of which is used to specify the frame format of
the corresponding message buffer.
•
0: Standard frame format (ID11 bit) used by Message Buffer (x)
•
1: Extended frame format (ID29 bit) used by Message Buffer (x)
Notes:
432
•
The contents of this register must be set while Message Buffer (x) is invalid [i.e., with BVALx
(BVALR) = 0]. If this register is set when the buffer is valid (BVALx = 1), unnecessary receive
messages may be stored.
•
To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller
is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section 18.12
"Precautions when Using CAN Controller".
18.3 Types of CAN Controller Registers
18.3.7 Transmission Request Register (TREQR)
The transmission request register (TREQR) is used to set a transmission request to
Message Buffer (x) to indicate the buffer status.
■ Bit Configuration of Transmission Request Register (TREQR)
Figure 18.3-10 "Bit configuration of transmission request register (TREQR)" shows the bit
configuration of the transmission request register
Figure 18.3-10 Bit configuration of transmission request register (TREQR)
Address: 000043 H (CAN0)
Address: 000073 H (CAN1)
Reading/writing
Initial value
Address: 000042 H (CAN0)
Address: 000072 H (CAN1)
Reading/writing
Initial value
15
14
13
12
11
10
9
TREQ15 TREQ14 TREQ13 TREQ12 TREQ11 TREQ10 TREQ9
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
6
5
7
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
8
TREQ8
(R/W)
(0)
4
3
2
1
0
TREQ7
TREQ6 TREQ5
TREQ4
TREQ3
TREQ2
TREQ1
TREQ0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
With TREQx set to "1", transmission to Message Buffer (x) will start. When RFWTx in the
remote frame receive wait register (RFWTR) (*1) is set to "0", transmission starts immediately.
When RFWTx = 1, processing waits until a remote frame is received [i.e., the remote request
transmission register (RRTRR) (*1) is set to "1"], then transmission will start. If TREQx is set to
"1" when RRTRx is already set to "1", transmission starts immediately even if RFWTx = 1. (*2)
*1: See Sections 18.3.8 "Transmission RTR Register (TRTRR)" and Section 18.3.9 "Remote
Frame Receive Wait Register (RFWTR)" for details about TRTRR and RFWTR.
*2: See Sections 18.3.10 "Transmission Cancel Register (TCANR)" and Section 18.3.11
"Transmission Complete Register (TCR)" for how to clear transmission.
Setting TREQx to "0" is ignored.
Read-modify-write instructions return "0".
When clearing the register to "0" by completion of transmission and setting the register by
writing "1" occur at the same time, clearing has priority.
When one or more bits are set to "1", transmission begins starting with Message Buffer(x) with
the lowest number.
TREQx is set to "1" in transmission wait state, and set to "0" when transmission is completed or
cleared.
433
CHAPTER 18 CAN CONTROLLER
18.3.8 Transmission RTR Register (TRTRR)
The transmission RTR register (TRTRR) is used to set the remote transmission request
(RTR) bit in Message Buffer (x).
■ Bit Configuration of Transmission RTR Register (TRTRR)
Figure 18.3-11 "Bit configuration of transmission RTR register (TRTRR)" shows the bit
configuration of the transmission RTR register (TRTRR).
Figure 18.3-11 Bit configuration of transmission RTR register (TRTRR)
Address : 003C0B H (CAN0)
Address : 003D0B H (CAN1)
Reading/writing
Initial value
15
14
13
12
11
10
9
TRTR15 TRTR14 TRTR13 TRTR12 TRTR11 TRTR10 TRTR9
Address : 003C0A H (CAN0)
Address : 003D0A H (CAN1)
Reading/writing
Initial value
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
8
TRTR8
(R/W)
(0)
7
6
5
4
3
2
1
0
TRTR7
TRTR6
TRTR5
TRTR4
TRTR3
TRTR2
TRTR1
TRTR0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
The transmission RTR register (TRTRR) consists of 16 bits, each of which is used to specify a
remote transmission request for the corresponding message buffer.
434
•
0: Send data frame.
•
1: Send remote frame.
18.3 Types of CAN Controller Registers
18.3.9 Remote Frame Receive Wait Register (RFWTR)
The remote frame receive wait register (RFWTR) is used to specify the condition for
the start of transmission when a request for sending a data frame is specified (with
TREQx in TREQR set to "1" and TRTRx in the transmission RTR register (TRTRR) set
to "0").
■ Bit Configuration of Remote Frame Receive Wait Register (RFWTR)
Figure 18.3-12 "Bit configuration of remote frame receive wait register (RFWTR)" shows the bit
configuration of the remote frame receive wait register (RFWTR).
Figure 18.3-12 Bit configuration of remote frame receive wait register (RFWTR)
Address 003C0D H (CAN0)
Address 003D0D H (CAN1)
Reading/writing
Initial value
Address 003C0C H (CAN0)
Address 003D0C H (CAN1)
Reading/writing
Initial value
15
14
13
12
11
10
9
8
RFWT15
RFWT14
RFWT13
RFWT12
RFWT11
RFWT10
RFWT9
RFWT8
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
2
1
0
RFWT7
RFWT6
RFWT5
RFWT4
RFWT3
RFWT2
RFWT1
RFWT0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
The remote frame transmission wait register (RFWTR) consists of 16 bits, each of which is used
to specify the transmission start condition when a message buffer is specified for date frame
transmission.
•
0: Start transmission immediately.
•
1: Start transmission after waiting for remote frame reception (i.e., RRTRR set to "1").
Notes:
•
Transmission starts immediately when a transmission request is specified with RRTRx
already set to "1".
•
Do not set RFWTx to "1" for remote frame transmission.
435
CHAPTER 18 CAN CONTROLLER
18.3.10 Transmission Cancel Register (TCANR)
The transmission cancel register (TCANR) is used to clear a request in the wait state
for transmission via Message Buffer (x) when TCANx is set to "1".
TREQx in the transmission request register (TREQR) is set to "0" when clearing is
completed. Writing "0" for TCANx is ignored.
TCANR is a write-only register, and its read value is always "0".
■ Bit Configuration of Transmission Cancel Register (TCANR)
Figure 18.3-13 "Bit configuration of transmission cancel register (TCANR)" shows the bit
configuration of the transmission cancel register (TCANR).
Figure 18.3-13 Bit configuration of transmission cancel register (TCANR)
Address: 000045 H (CAN0)
Address: 000075 H (CAN1)
Reading/writing
Initial value
Address: 000044 H (CAN0)
Address: 000074 H (CAN1)
Reading/writing
Initial value
436
15
14
13
12
11
10
9
TCAN15 TCAN14 TCAN13 TCAN12 TCAN11 TCAN10 TCAN9
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
8
TCAN8
(W)
(0)
7
6
5
4
3
2
1
0
TCAN7
TCAN6
TCAN5
TCAN4
TCAN3
TCAN2
TCAN1
TCAN0
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
18.3 Types of CAN Controller Registers
18.3.11 Transmission Complete Register (TCR)
When transmission via Message Buffer (x) is completed, the corresponding TCx is set
to "1".
If TIEx in the transmission interrupt enable register (TIER) is set to "1", an interrupt is
generated.
■ Bit Configuration of Transmission Complete Register (TCR)
Figure 18.3-14 "Bit configuration of transmission complete register (TCR)" shows the bit
configuration of the transmission complete register (TCR).
Figure 18.3-14 Bit configuration of transmission complete register (TCR)
Address : 000047 H (CAN0)
Address : 000077 H (CAN1)
Reading/writing
Initial value
Address : 000046 H (CAN0)
Address : 000076 H (CAN1)
Reading/writing
Initial value
15
TC15
14
TC14
13
TC13
12
TC12
11
TC11
10
TC10
9
TC9
8
TC8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
TC7
6
TC6
5
TC5
4
TC4
3
TC3
2
TC2
1
TC1
0
TC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
TCx = 0 is set under the following conditions:
•
TCx is set to "0".
•
TREQx in the transmission request register (TREQR) is set to "1". When "0" is written to TCx
after transmission is completed, TCx is set to "0". Writing "1" is ignored. Read-modify-write
instructions return "1".
Note:
When this bit is set to "1" because a send operation is completed and clearing by writing "0"
is attempted at the same time, setting to "1" has priority.
437
CHAPTER 18 CAN CONTROLLER
18.3.12 Transmission Interrupt Enable Register (TIER)
The transmission interrupt enable register (TIER) allow or prohibit a transmission
interrupt via Message Buffer (x). A transmission interrupt is generated when
transmission is completed (i.e., when TCx in the transmission complete register (TCR)
is set to "1").
■ Bit Configuration of Transmission Interrupt Enable Register (TIER)
Figure 18.3-15 "Bit configuration of transmission interrupt enable register (TIER)" shows the bit
configuration of the transmission interrupt enable register (TIER).
Figure 18.3-15 Bit configuration of transmission interrupt enable register (TIER)
Address : 003C0FH (CAN0)
Address : 003D0FH (CAN1)
Reading/writing
Initial value
15
TIE15
14
TIE14
13
TIE13
12
TIE12
11
TIE11
10
TIE10
9
TIE9
8
TIE8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Address : 003C0EH (CAN0)
Address : 003D0EH (CAN1)
Reading/writing
Initial value
7
TIE7
6
TIE6
5
TIE5
4
TIE4
3
TIE3
2
TIE2
1
TIE1
0
TIE0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
The transmission interrupt enable register (TIER) consists of 16 bits, each of which is used to
allow or prohibit transmission interrupts to the corresponding message buffer.
438
•
0: Prohibits transmission interrupts.
•
1: Allows transmission interrupts.
18.3 Types of CAN Controller Registers
18.3.13 Receive Complete Register (RCR)
When storing a receive message in Message Buffer (x) is completed, RCx is set to "1".
When RIEx in the receive complete interrupt enable register is set to "1", an interrupt
is generated.
■ Bit Configuration of Receive Complete Register (RCR)
Figure 18.3-16 "Bit configuration of receive complete register (RCR)" shows the bit configuration
of the receive complete register (RCR).
Figure 18.3-16 Bit configuration of receive complete register (RCR)
Address : 000049 H (CAN0)
Address : 000079 H (CAN1)
Reading/writing
Initial value
Address : 000048 H (CAN0)
Address : 000078 H (CAN1)
Reading/writing
Initial value
15
RC15
14
RC14
13
RC13
12
RC12
11
RC11
10
RC10
9
RC9
8
RC8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
RC7
6
RC6
5
RC5
4
RC4
3
RC3
2
RC2
1
RC1
0
RC0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Conditions for setting RCx = 0 are:
•
Clearing RCx by writing "0".
•
After the receive message is processed, RCx is set to "0". Writing "1" is ignored. Readmodify-write instructions return "1".
Note:
If this bit is set to "1" because a receive operation is completed and there is an attempt to
clear this bit by writing "0" at the same time, setting "1" has priority.
439
CHAPTER 18 CAN CONTROLLER
18.3.14 Remote Request Transmission Register (RRTRR)
When a remote frame received is stored in Message Buffer (x), RRTRx is set to "1" at
the same time RCx is set to "1".
■ Bit Configuration of Remote Request Transmission Register (RRTRR)
Figure 18.3-17 "Bit configuration of remote request transmission register (RRTRR)" shows the
bit configuration of the remote request transmission register (RRTRR).
Figure 18.3-17 Bit configuration of remote request transmission register (RRTRR)
Address : 00004B H (CAN0)
Address : 00007B H (CAN1)
Reading/writing
Initial value
Address : 00004A H (CAN0)
Address : 00007A H (CAN1)
Reading/writing
Initial value
15
14
13
12
11
10
9
RRTR15 RRTR14 RRTR13 RRTR12 RRTR11 RRTR10 RRTR9
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
8
RRTR8
(R/W)
(0)
7
6
5
4
3
2
1
0
RRTR7
RRTR6
RRTR5
RRTR4
RRTR3
RRTR2
RRTR1
RRTR0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Conditions for setting RRTRx = 0 are:
•
Clearing RRTRx by writing "0"
•
After a received data frame has been stored in Message Buffer (x) (at the same time RCx
set is set to "1").
•
After transmission via Message Buffer (x) is completed (when TCx in the transmission
complete register (TCR) is "1"). Writing "1" to RRTRx is ignored. Read-modify-write
instructions always return "1".
Note:
If setting "1" and clearing to "0" by writing are attempted at the same time, setting "1" has
priority.
440
18.3 Types of CAN Controller Registers
18.3.15 Receive Overrun Register (ROVRR)
If the receive complete register (RCR) is already set to "1" at the time a received
message is about to be stored in Message Buffer (x), ROVRx is set to "1" indicating
that reception caused an overrun.
■ Bit Configuration of Receive Overrun Register (ROVRR)
Figure 18.3-18 "Bit configuration of receive overrun register (ROVRR)" shows the bit
configuration of the receive overrun register (ROVRR).
Figure 18.3-18 Bit configuration of receive overrun register (ROVRR)
Address: 00004D H (CAN0)
Address: 00007D H (CAN1)
Reading/writing
Initial value
Address: 00004C H (CAN0)
Address: 00007C H (CAN1)
Reading/writing
Initial value
15
14
13
12
11
10
9
ROVR15 ROVR14 ROVR13 ROVR12 ROVR11 ROVR10 ROVR9
(R/W)
(0)
(R/W)
(0)
7
6
ROVR7 ROVR6
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
5
4
ROVR5 ROVR4
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
3
2
(R/W)
(0)
8
ROVR8
(R/W)
(0)
1
0
ROVR3 ROVR2
ROVR1
ROVR0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
Writing "0" clears ROVRx to "0". Writing "1" is ignored. Writing "0" after checking whether
reception caused an overrun also clears ROVRx to "0".
Read-modify-write instructions always return"1".
Note:
If there is an attempt to set to "1" and clear by writing "0" at the same time, setting "1" has
priority.
441
CHAPTER 18 CAN CONTROLLER
18.3.16 Receive Interrupt Enable Register (RIER)
The receive interrupt enable register (RIER) allow or prohibit receive interrupts via
Message Buffer (x).
A receive interrupt is generated when reception is completed (i.e., RCx in RCR is set to
"1").
■ Bit Configuration of Receive Interrupt Enable Register (RIER)
Figure 18.3-19 "Bit configuration of receive interrupt enable register (RIER)" shows the bit
configuration of the receive interrupt enable register (RIER).
Figure 18.3-19 Bit configuration of receive interrupt enable register (RIER)
Address : 00004FH (CAN0)
Address : 00007FH (CAN1)
Reading/writing
Initial value
Address : 00004EH (CAN0)
Address : 00007EH (CAN1)
Reading/writing
Initial value
15
RIE15
14
RIE14
13
RIE13
12
RIE12
11
RIE11
10
RIE10
9
RIE9
8
RIE8
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
RIE7
6
RIE6
5
RIE5
4
RIE4
3
RIE3
2
RIE2
1
RIE1
0
RIE0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
The receive interrupt enable register (RIER) consists of 16 bits, each of which is used to allow
or prohibit receive interrupts of the corresponding message buffer.
442
•
0: Prohibit receive interrupts.
•
1: Allow receive interrupts.
18.3 Types of CAN Controller Registers
18.3.17 Acceptance Mask Selection Register (AMSR)
The acceptance mask selection register (AMSR) is used to select a mask (acceptance
mask) by comparing the receive message ID with the Message Buffer (x) ID.
■ Bit Configuration of Acceptance Mask Selection Register (AMSR)
Figure 18.3-20 "Bit configuration of acceptance mask selection register (AMSR)" shows the bit
configuration of the acceptance mask selection register (AMSR). As listed in Table 18.3-8
"Selection of the acceptance mask", a combination of 2 bits is used to select the acceptance
mask for the corresponding message buffer.
Figure 18.3-20 Bit configuration of acceptance mask selection register (AMSR)
Address : 003C10 H (CAN0)
Address : 003D10 H (CAN1)
Reading/writing
Initial value
Address : 003C11 H (CAN0)
Address : 003D11 H (CAN1)
Reading/writing
Initial value
Address : 003C12 H (CAN0)
Address : 003D12 H (CAN1)
Reading/writing
Initial value
Address : 003C13 H (CAN0)
Address : 003D13 H (CAN1)
Reading/writing
Initial value
7
6
5
4
3
2
1
0
AMS3.1
AMS3.0
AMS2.1
AMS2.0
AMS1.1
AMS1.0
AMS0.1
AMS0.0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
AMS7.1
AMS7.0
AMS6.1
AMS6.0
AMS5.1
AMS5.0
AMS4.1
AMS4.0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
6
5
4
3
AMS11.1 AMS11.0 AMS10.1 AMS10.0 AMS9.1
2
1
0
AMS9.0
AMS8.1
AMS8.0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
14
13
12
11
10
9
8
AMS15.1 AMS15.0 AMS14.1 AMS14.0 AMS13.1 AMS13.0 AMS12.1 AMS12.0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
443
CHAPTER 18 CAN CONTROLLER
Table 18.3-8 Selection of the acceptance mask
AMSx.1
AMSx.0
Acceptance mask
0
0
Full-bit compare
0
1
Full-bit mask
1
0
Acceptance Mask Register 0 (AMR0)
1
1
Acceptance Mask Register 1 (AMR1)
Notes:
444
•
AMSx.1 and AMSx.0 must be set while Message Buffer (x) is invalid (i.e., BVALx in the
buffer valid register (BVALR) is "0"). Setting these bits when the buffer contents is valid
(BVALx = 1) may result in unnecessary receive messages being stored.
•
To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller
is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section 18.12
"Precautions when Using CAN Controller".
18.3 Types of CAN Controller Registers
18.3.18 Acceptance mask Registers 0/1 (AMR0/AMR1)
AMR0 and AMR1 can both be used in standard frame format or extended frame format.
AM28 to AM18 (11 bits) are used for an acceptance mask in standard frame format;
AM28 to AM0 (29 bits) are used for an acceptance mask in extended format.
■ Bit Configuration of Acceptance mask Registers 0/1 (AMR0/AMR1)
Figure 18.3-21 "Bit configuration of acceptance mask registers 0/1 (AMR0/AMR1)" shows the bit
configuration of the Acceptance Mask Registers 0/1 (AMR0/AMR1).
Figure 18.3-21 Bit configuration of acceptance mask registers 0/1 (AMR0/AMR1)
AMRO BYTE0
Address : 003C14 H (CAN0)
Address : 003D14 H (CAN1)
Reading/writing =>
Initial value =>
AMRO BYTE1
Address : 003C15H (CAN0)
Address : 003D15H (CAN1)
Reading/writing =>
Initial value =>
AMRO BYTE2
Address : 003C16 H (CAN0)
Address : 003D16 H (CAN1)
Reading/writing =>
Initial value =>
AMRO BYTE3
Address: 003C17 H (CAN0)
Address: 003D17 H (CAN1)
Reading/writing =>
Initial value =>
AMR1 BYTE0
Address : 003C18H (CAN0)
Address : 003D18H (CAN1)
Reading/writing =>
Initial value =>
AMRO BYTE1
Address : 003C19H (CAN0)
Address : 003D19H (CAN1)
Reading/writing =>
Initial value =>
AMRO BYTE2
Address : 003C1AH (CAN0)
Address : 003D1AH (CAN1)
Reading/writing =>
Initial value =>
AMRO BYTE3
Address : 003C1BH (CAN0)
Address : 003D1BH (CAN1)
Reading/writing =>
Initial value =>
7
AM28
6
AM27
5
AM26
4
AM25
3
AM24
2
AM23
1
AM22
(R/W)
(X)
0
AM21
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
AM20
14
AM19
13
AM18
12
AM17
11
AM16
10
AM15
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
AM12
6
AM11
5
AM10
4
AM9
3
AM8
2
AM7
1
AM6
0
AM5
9
AM14
(R/W)
(X)
8
AM13
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
AM4
14
AM3
13
AM2
12
AM1
11
AM0
10
-
9
-
8
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(-)
(R/W)
(-)
(R/W)
(-)
7
AM28
6
AM27
5
AM26
4
AM25
3
AM24
2
AM23
1
AM22
(R/W)
(X)
0
AM21
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
AM20
14
AM19
13
AM18
12
AM17
11
AM16
10
AM15
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
AM12
6
AM11
5
AM10
4
AM9
3
AM8
2
AM7
1
AM6
0
AM5
9
AM14
(R/W)
(X)
8
AM13
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
AM4
14
AM3
13
AM2
12
AM1
11
AM0
10
-
9
-
8
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(-)
(R/W)
(-)
(R/W)
(-)
445
CHAPTER 18 CAN CONTROLLER
❍ 0: compare
The acceptance code corresponding to this bit (i.e., IDRx in the ID register) is compared with
the ID bit of the receive message. If these bits do not match, the message is not accepted.
❍ 1: mask
The acceptance code ID register (IDRx) corresponding to this bit is masked. The receive
message ID bit is not compared.
Notes:
446
•
AMR0 and AMR1 must be set while the contents of all message buffers (x) used to select
AMR0 and AMR1 are invalid (i.e., BVALx in the buffer valid register (BVALR) are set to "0").
Setting these registers when the contents of the message buffers are valid (BVALx = 1) may
result in unnecessary receive messages being stored.
•
To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller
is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section 18.12
"Precautions when Using CAN Controller".
18.3 Types of CAN Controller Registers
18.3.19 Message Buffers
This device has 16 message buffers. Message Buffer (x) (x = 0 to 15) consists of an ID
register (IDRx), DLC register (DLCRx), and data register (DTRx).
■ Message Buffers
Message buffer (x) is used for both send and receive operations.
Low-numbered message buffers have priority.
When a transmission request is issued to one or more message buffers, transmission starts with
the message buffer having the lowest number. (See Section 18.4 "Transmission Via CAN
Controller", for details.)
When the receive message ID of a message received passes through the acceptance filters of
one or more message buffers (i.e., the mechanism to compare the acceptance mask ID of a
received message with that for the message buffer), the receive message is stored in the
message buffer with the lowest number. (See Section 18.5 "Reception by CAN Controller", for
details.)
If the same acceptance filter is specified for multiple message buffers, the message buffers
concerned may be used as a multi-level message buffer. This creates a time reserve available
for reception-related processing. (See Section 18.8 "Reception via Message Buffer (x)", for
details.)
Notes:
•
Write operations to a message buffer and to general-purpose RAM area must be performed
using even-numbered addresses and in word units. Note that using byte units for write
operation may result in undefined data being written in the upper bytes when writing the
lower byte.
•
When the BVALx bit in the buffer valid register (BVALR) is set to "0" (invalid), the Message
Buffer (x) (IDRx, DLCRx, and DTRx) may be used as general-purpose RAM. When the CAN
controller is in send and receive operation mode, it uses a message buffer. Consequently,
CPU access may be delayed for up to 64 machine cycles. This problem may occur in the
general-purpose RAM area (CAN0: addresses 003A00H to 003A1FH and 003B00H to
003B1FH).
447
CHAPTER 18 CAN CONTROLLER
18.3.20 ID Register x (x = 0 to 15) (IDRx)
ID Register x (x = 0 to 15) (IDRx) is used for Message Buffer (x).
■ Bit Configuration of ID Register x (x = 0 to15) (IDRx)
Figure 18.3-22 "Bit configuration of ID register x (x = 0 to 15) (IDRx)" shows the bit configuration
of ID Register x (x = 0 to 15) (IDRx).
Figure 18.3-22 Bit configuration of ID register x (x = 0 to 15) (IDRx)
BYTE0
Address : 003A20 H +4x(CAN0)
Address : 003B20 H +4x(CAN1)
Reading/writing =>
Initial value =>
7
ID28
6
ID27
5
ID26
4
ID25
3
ID24
2
ID23
1
ID22
0
ID21
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
14
ID19
13
ID18
12
ID17
11
ID16
10
ID15
9
ID14
8
ID13
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
ID12
6
ID11
5
ID10
4
ID9
3
ID8
2
ID7
1
ID6
0
ID5
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
ID4
14
ID3
13
ID2
12
ID1
11
ID0
10
-
9
-
8
-
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(-)
(R/W)
(-)
(R/W)
(-)
BYTE1
15
Address : 003A21 H +4x(CAN0)
ID20
Address : 003B21 H +4x(CAN1)
Reading/writing => (R/W)
Initial value => (X)
BYTE2
Address : 003A22 H +4x(CAN0)
Address : 003B22 H +4x(CAN1)
Reading/writing =>
Initial value =>
BYTE3
Address : 003A23H +4x(CAN0)
Address : 003B23 +4x(CAN1)
H
Reading/writing =>
Initial value =>
When Message Buffer (x) is used in standard frame format (i.e., IDEx = 0 in the IDE register
(IDER)), use ID28 to ID18 (11 bits). When a buffer is used in extended frame format (IDEx = 1),
use ID28 to ID0 (29 bits).
ID28 to ID0 have the following functions:
448
•
Specifying an acceptance code (ID for comparing with receive message ID)
•
Specifying a send message ID: In standard frame format, the setting of all bits in ID28 to
ID22 to "1" is disabled.
•
Storing a receive message ID: Receive message IDs are also stored in bits masked by an
acceptance mask. In standard frame format, unspecified values (i.e., part of a message
previously received) are stored in ID17 to ID0.
18.3 Types of CAN Controller Registers
Notes:
•
Write operations to IDR must use word units. Using byte units for write operation may result
in undefined data being written in the upper byte when writing the lower byte. Attempts to
write the upper byte are ignored.
•
IDR must be set while the contents of the Message Buffer (x) is invalid (i.e., BVALx in the
buffer valid register (BVALR) is "0"). Setting IDR when the contents of the buffer is valid
(BVALx = 1) may result in unnecessary receive messages being stored.
•
To invalidate the message buffer (by setting the BVALR: BVAL bit to 0) while CAN Controller
is participating in CAN communication (the read value of the CSR: HALT bit is 0 and CAN
Controller is ready to receive or transmit messages), follow the cautions in Section 18.12
"Precautions when Using CAN Controller".
■ Example of Setting IDR
Table 18.3-9 "Example of setting IDR in standard frame format" and 18.3-10 show examples of
setting IDR in standard frame format and extended frame format.
Table 18.3-9 Example of setting IDR in standard frame format
ID (Dec)
ID (Hex)
BYTE0
BYTE1
1
1
00
20
2
2
00
40
3
3
00
60
4
4
00
80
5
5
00
A0
6
6
00
C0
7
7
00
E0
8
8
01
00
9
9
01
20
10
A
01
40
.
.
30
1E
03
C0
31
1F
03
C1
32
20
03
C2
100
064
0C
80
101
065
0C
A0
0C8
19
00
.
.
.
.
200
.
.
2043
7FB
FF
06
2044
7FC
FF
80
2045
7FD
FF
A0
2046
7FE
FF
C0
2047
7FF
FF
E0
449
CHAPTER 18 CAN CONTROLLER
Table 18.3-10 Example of setting IDR in extended frame format
ID (Dec)
ID (Hex)
BYTE0
BYTE1
BYTE0
BYTE1
1
1
00
00
00
08
2
2
00
00
00
10
3
3
00
00
00
18
4
4
00
00
00
20
5
5
00
00
00
28
6
6
00
00
00
30
7
7
00
00
00
38
8
8
00
00
00
40
9
9
00
00
00
48
10
A
00
00
00
50
.
.
.
.
30
1E
00
00
00
F0
31
1F
00
00
00
F8
20
00
00
01
00
03
20
03
28
06
40
32
.
.
100
101
.
.
064
00
00
065
00
00
.
.
200
.
.
0C8
00
00
.
.
.
.
2043
7FB
00
00
3F
D8
2044
7FC
00
00
3F
E0
2045
7FD
00
00
3F
E8
2046
7FE
00
00
3F
F0
2047
7FF
00
00
3F
F8
8190
1FFE
00
00
FF
F0
8191
1FFF
00
00
FF
F8
8192
2000
00
01
00
00
.
.
450
.
.
536870905
1FFFFFF9
FF
FF
FC
80
536870906
1FFFFFFA
FF
FF
FD
00
536870907
1FFFFFFB
FF
FF
FD
80
536870908
1FFFFFFC
FF
FF
FE
00
536870909
1FFFFFFD
FF
FF
FE
80
536870910
1FFFFFFE
FF
FF
FF
00
536870911
1FFFFFFF
FF
FF
FF
80
18.3 Types of CAN Controller Registers
18.3.21 DLC Register x (x = 0 to 15) (DLCRx)
DLC Register x (x = 0 to 15) (DLCRx) is used to store the DLC corresponding to
Message Buffer (x).
■ Bit Configuration of DLC Register x (x = 0 to 15) (DLCRx)
Figure 18.3-23 "Bit configuration of DLC register x (x = 0 to 15) (DLCRx)" shows the bit
configuration of DLC Register x (x = 0 to 15) (DLCRx).
Figure 18.3-23 Bit configuration of DLC register x (x = 0 to 15) (DLCRx)
Address : 003A60H+2x (CAN0)
Address : 003B60H+2x (CAN1)
Reading/writing =>
Initial value =>
7
-
6
-
5
-
4
-
3
DLC3
2
DLC2
1
DLC1
0
DLC0
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(-)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
❍ Transmission
•
When a data frame is sent (i.e., TRTRx in the transmission RTR register (TRTRR) is set to
"0"), the data length of the send message is stored (in units of bytes).
•
When a remote frame is sent (TRTRx = 1), the data length of the request message is stored
(in units of bytes).
Note:
Setting values other than 0000 to 1000 (0 to 8 bytes) is disabled.
❍ Receive
•
When a data frame is received (i.e., RRTRx in RRTRR is set to "0"), the data length of the
receive message is stored (in units of bytes).
•
When a remote frame is received (RRTRx = 1), the data length of the request message is
stored (in units of bytes).
Note:
Write operation to the DLC register must be performed in units of words. Write operations in
units of bytes may result in unspecified data being written in the upper byte when writing the
lower byte. Attempts to write the upper byte are ignored.
451
CHAPTER 18 CAN CONTROLLER
18.3.22 Data Register x (x = 0 to 15) (DTRx)
Data Register x (x = 0 to 15) (DTRx) is used for Message Buffer (x).
Data Register x (x = 0 to 15) (DTRx) is only used to send and receive data frames; it is
not used to send and receive remote frames.
■ Bit Configuration of Data Register x (x = 0 to 15) (DTRx)
Figure 18.3-24 "Bit configuration of data register x (x = 0 to 15) (DTRx) (to be continued)" shows
the bit configuration of Data Register x (x = 0 to 15) (DTRx).
Figure 18.3-24 Bit configuration of Data register x (x = 0 to 15) (DTRx) (to be continued)
BYTE0
Address : 003A80 H +8x(CAN0)
Address : 003B80 H +8x(CAN1)
Reading/writing =>
Initial value =>
BYTE1
Address : 003A81 H +8x(CAN0)
Address : 003B81 H +8x(CAN1)
Reading/writing =>
Initial value =>
BYTE2
Address : 003A82H +8x(CAN0)
Address : 003B82H +8x(CAN1)
Reading/writing =>
Initial value =>
BYTE3
Address : 003A83 H +8x(CAN0)
Address : 003B83 H +8x(CAN1)
Reading/writing =>
Initial value =>
BYTE4
Address : 003A84H +8x(CAN0)
Address : 003B84H +8x(CAN1)
Reading/writing =>
Initial value =>
BYTE5
Address : 003A85 H +8x(CAN0)
Address : 003B85 H +8x(CAN1)
Reading/writing =>
Initial value =>
BYTE6
Address : 003A86 H +8x(CAN0)
Address : 003B86 H +8x(CAN1)
Reading/writing =>
Initial value =>
BYTE7
Address : 003A87H +8x(CAN0)
Address : 003B87H +8x(CAN1)
Reading/writing =>
Initial value =>
452
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D7
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D7
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D7
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D7
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
18.3 Types of CAN Controller Registers
❍ Setting send message data (0 to 8 bytes)
Data transfer begins with the MSB, followed in the order of BYTE0, BYTE1, ...BYTE7.
❍ Receive message data
Storing data begins with the MSB, followed in the order of BYTE0, BYTE1, ...BYTE7.
Even if less than 8 bytes of receive message data have been received, the remaining bytes in
the data register (DTRx) used to store data will become undefined.
Note:
Write operations to the data register must be performed in units of words. Write operations in
units of bytes may result in undefined data being written in the upper byte when writing the
lower byte. Attempts to write the upper byte are ignored.
453
CHAPTER 18 CAN CONTROLLER
18.3.23 CAN WAKE UP Control Register (CWUCR)
The CAN WAKE UP Control Register (CWUCR) is used to control the internal
connection of the RX pin to the INT pin.
■ Bit Configuration of CAN WAKE UP Control Register (CWUCR)
Figure 18.3-25 "Bit configuration of CAN WAKE UP control register (CWUCR)" shows the bit
configuration of the CAN WAKE UP control register (CWUCR).
Figure 18.3-25 Bit configuration of CAN WAKE UP control register (CWUCR)
CWUCR
Address : 003E H
Reading/writing =>
Initial value =>
7
(R/W)
(-)
6
(R/W)
(-)
5
(R/W)
(-)
4
(R/W)
(-)
3
(R/W)
(-)
2
(R/W)
(-)
1
(R/W)
(-)
0
CWU
(R/W)
(0)
[bit 0]: CAN WAKE UP control bit
The CWU bit is used to control the internal connection of the RX pin to the INT pin.
454
•
0: The RX and INT pins are not internally connected. The INT pin functions as an ordinary
external interrupt pin.
•
1: The RX and INT pins are internally connected. The INT pin cannot be used by any
external interrupt function.
18.4 Transmission Via CAN Controller
18.4 Transmission Via CAN Controller
The CAN controller is used to start transmission via Message Buffer (x) when TREQx
in the transmission request register (TREQR) is set to "1". When TREQx is set to "1",
TCx in the transmission complete register (TCR) is set to "0".
■ Starting Transmission Via the CAN Controller
When RFWTx in the remote frame receive wait register (RFWTR) is set to "0", transmission
starts immediately. When RFWTx is set to "1", transmission will start after a remote frame is
received (i.e., RRTRx in the remote request receive register (RRTRR) set to "1").
When a transmission request is issued to multiple message buffers (i.e., more than one of the
TREQx bits is set to "1"), transmission starts from the message buffer with the lowest number.
Message transmission (via send output pin TX) to the CAN bus starts when the bus becomes
idle.
When TRTRx in the transmission RTR register (TRTRR) is "0", a data frame is sent. When
TRTRx is "1", a remote frame is sent.
If arbitration (for transmission) fails due to a message buffer conflict with another CAN controller
on the CAN bus or an error occurs during sending, the message buffer waits until the bus enters
idle mode to retransmit the message until sending was successful.
■ Clearing a CAN Controller Transmission Request
❍ Clearing via the transmission cancel register (TCANR)
A transmission request issued to Message Buffer (x) that does not result in transmission in send
wait state mode can be cleared by writing "1" to TCANx in TCANR. When clearing is completed,
TREQx is set to "0".
❍ Clearing by storing a receive message
Message buffer (x), for which (a requested) transmission failed will be used for reception
instead.
If a request for transmission of a data frame has been issued, but Message Buffer (x) fails to
perform the transmission (i.e., TRTRx = 0 or TREQx = 1), the transmission request is cleared
after a receive data frame that passed the acceptance filter is stored in the buffer instead (i.e.,
TREQx = 0). Storing a remote frame will not clear the transmission request (i.e., TREQx = 1
remains unchanged).
If a request to transmit a remote frame has been issued, but transmission with Message Buffer
(x) fails (i.e., TRTRx = 1 or TREQx = 1), the transmission request is cleared after a receive
remote frame that passed the acceptance filter is stored (TREQx = 0). Storing either a data
frame or remote frame will clear the transmission request.
455
CHAPTER 18 CAN CONTROLLER
■ Completed Transmission Via CAN Controller
RRTRx and TREQx are set to "0" to indicate successful transmission (with TCx in TCR set to
"1"). When transmission complete interrupts are enabled (i.e., TIEx in the transmission interrupt
enable register (TIER) is set to "1"), an interrupt is generated.
■ Flowchart of CAN Transmission Settings
Figure 18.4-1 "Flowchart of making CAN transmission settings" shows a flowchart of making the
CAN transmission settings.
Figure 18.4-1 Flowchart of making CAN transmission settings
START
Setting bit timing:
Setting frame format:
Setting ID:
Setting acceptance filter:
Bit Timing Register (BTR)
IDE Register (IDER)
ID Register (IDR)
Acceptance Mask Select Register (AMSR)
Acceptance Mask Registers (AMR0,1)
Select message buffer to be used:
Message Buffer Valid Register (BVALR)
Set transmission complete interrupt:
Transmission Interrupt Enable Register (TIER)
Data frame
Remote frame
Select frame type
Set frame type
Transmission RTR Register (TRTRR = 0)
Set frame type
Transmission RTR Register (TRTRR = 1)
Set send data length
DLC Register (DLCR)
Set request data length
DLC Register (DLCR)
Store send data in data register
Data Register (DTR)
Yes
Waiting to
receive remote frame?
No
Waiting to receive remote
frame RFWTR = 0
Waiting to receive remote
frame RFWTR = 1
Clear bus operation stop HALT = 1
Message
transmission
Set transmission request for data frame
Transmission request register (TREQR)
Waiting to receive remote
frame Communication error
N:0
Was
transmission
successful?
TCR
N
Cancel
transmission?
Y:1
Y
Cancel transmission request
Transmission Cancel Register (TCANR)
TREQR
1
0
1
TCR
0
Transmission completed
END
456
Cancel transmission
18.4 Transmission Via CAN Controller
■ Flowchart of Transmission Via CAN Controller
Figure 18.4-2 "Flowchart of transmission by CAN controller" shows a flowchart of transmission
via the CAN controller.
Figure 18.4-2 Flowchart of transmission by CAN controller
Transmission request
(TREQx = 1)
TCx = 0
0
TREQx?
1
0
RFWTx?
1
0
RRTRx?
1
If there are other message buffers that
satisfy the above condition, the buffer
with the lowest number is selected.
NO
No bus used?
YES
0
1
TRTRx?
Remote frame sent
Data frame sent
NO
Transmission
successful
YES
TCANx?
RRTRx = 0
TREQx = 0
TCx = 1
0
1
TREQx = 0
1
TIEx?
0
Transmission complete
interrupt generated.
End of transmission
457
CHAPTER 18 CAN CONTROLLER
18.5 Reception Via CAN Controller
Reception via the CAN controller starts when the start of a data frame or remote frame
(SOF) is detected on the CAN bus.
■ Acceptance Filtering
Receive messages in standard frame format are compared with Message Buffer (x) set to
standard frame format (i.e., IDEx in the IDE register (IDER) is set to "0"). Receive messages in
extended frame format are compared with Message Buffer (x) set to extended frame format
(i.e., IDEx is set to "1").
When all bits match the acceptance mask after the receive message ID and acceptance code
(i.e., IDRx in the ID register) are compared, the receive message passes the acceptance filter of
Message Buffer (x).
■ Storing a Receive Message
When receive operation is successful, the receive message (including the ID that passed the
acceptance filter) is stored in Message Buffer (x).
When a data frame is received, the receive message is stored in IDRx of the ID register, DLCRx
of the DLC register, and DTRx of the DTR register.
Even if the data length of a receive message is less than 8 bytes, the data is stored in DTRx
and the value of the remaining bytes is undefined.
When a remote frame is received, the receive message is only stored in IDRx and DLCRx (i.e.,
DTRx remains unchanged).
When there are more than one message buffers that have IDs that passed the acceptance filter,
the message buffer to store the receive message is specified by the following rule:
The priority of Message Buffer (x) (x = 0 to 15) becomes higher in descending order of buffer
numbers. In other words, message buffer 0 has the highest priority; message buffer 15 has the
lowest priority.
The message buffer for which the RCx bit in the receive complete register (RCR) is set to "0"
has priority for storing a receive message.
If the bits in the acceptance mask selection register (AMSR) are set in such a way that a
message buffer is selected for which all-bit compare is set to "00" (in bits AMSx.1 and AMSx.0),
the receive message is stored regardless of the value of the RCx bit in RCR.
When there are multiple buffers for which the RCx bit in the RCR is set to "0" and multiple
buffers for which the AMSR bit is set to all-bit compare, receive messages are stored in the
Message Buffer (x) with the lowest number (i.e., highest priority). If no such message buffer
exists, receive messages are stored in the buffer with the next lowest number after Message
Buffer (x).
Figure 18.5-1 "Flowchart for specifying Message Buffer (x) for storing receive message" shows
the flowchart of determining Message Buffer (x) for storing receive messages. Message buffers
should be sequentially set in order of buffer numbers, buffers for which each bit of AMSR is set
to all-bit compare, buffers that use AMR0 or AMR1, and buffers for which each bit of AMSR is
set to all-bit mask.
458
18.5 Reception Via CAN Controller
Figure 18.5-1 Flowchart for specifying Message Buffer (x) for storing receive message
Start
Are message buffers with RCx set to 0
or with AMSx.1 and AMSx.0 set to 00
found?
NO
YES
Select the lowest-numbered
message buffer (of applicable
message buffers with RCx set
to 0 or with AMSx.1 and
AMSx.0 set to 00).
Select the lowest-numbered
message buffer (of applicable
message buffers).
End
■ Receive Overrun
When RCx (corresponding to Message Buffer (x) that stores a receive message) is already set
to "1" in RCR when a receive message is about to be stored in Message Buffer (x), the ROVRx
bit in the receive overrun register (ROVRR) is set to "1" (to indicate receive overrun).
■ Processing for receiving data frame and remote frame
❍ Processing for receiving data frame
When a data frame is received, RRTRx in the transmission RTR register (RRTRR) is set to "0".
TREQx in TREQR is set to "0" immediately before a receive message is stored. Any
transmission request for Message Buffer (x) for which transmission fails is cleared, regardless of
whether this is a requests to transmit a data frame or a remote frame.
❍ Processing for receiving a remote frame
When a remote frame is received, RRTRx is set to "1".
When TRTRx in the TRTRR is set to "1", TREQx is set to "0". As a result, any transmission
request to the message buffer for which transmission failed will be cleared.
Notes:
•
Requests for transmission of data frames cannot be cleared.
•
See Section 18.4 "Transmission Via CAN Controller", for how to clear a transmission
request.
459
CHAPTER 18 CAN CONTROLLER
■ Receive Complete
RCx in the Receive Complete Register (RCR) is set to "1" after a received message has been
stored.
When receive interrupts are enabled (i.e., RIEx in the receive interrupt enable register (RIER) is
set to "1"), an interrupt is generated.
Note:
The CAN controller cannot receive messages that it transmitted itself.
■ Flowchart of Making CAN Receive Settings
Figure 18.5-2 "Flowchart of CAN receive settings" shows a flowchart of making the settings for
CAN reception.
Figure 18.5-2 Flowchart of CAN receive settings
START
Setting bit timing:
Setting frame format:
Setting ID:
Setting acceptance filter:
Bit Timing Register (BTR)
IDE Register (IDER)
ID Register (IDR)
Acceptance Mask Select Register (AMSR)
Acceptance Mask Registers (AMR0,1)
Select message buffer to be used:
Message buffer valid register (BVALR)
Set transmission complete interrupt:
Receive interrupt enable register (RIER)
Release bus operation halt: HALT = 1
N
Message received?
RCR = 1
Y
Message store processing
Processed e.g. by receive complete
interrupt
Read receive byte count
Clear receive overrun flag
ROVRR=0
Read receive message
Receive overrun?
ROVRR=0 ?
N
Y
Clear receive complete interrupt flag
RCR=0
END
460
18.5 Reception Via CAN Controller
■ Flowchart of Reception Via CAN Controller
Figure 18.5-3 "Flowchart of reception via CAN controller" shows a flowchart of reception via the
CAN controller.
Figure 18.5-3 Flowchart of reception via CAN controller
Detect start of data frame or
remote frame (SOF)
Is there a Message
Buffer(x) for message that passes acceptance filter
NO
YES
NO
Reception successful?
YES
Store received message
Specify Message Buffer(x)
Store received message in
Message Buffer(x)
1
RCx?
0
Data frame
ROVRx=1
Remote frame
Which type
of message was received?
RRTRx=0
RRTRx=1
1
TRTRx?
0
TREQx=0
RCx=1
RIEx?
0
1
Generate receive
interrupt
End of reception
461
CHAPTER 18 CAN CONTROLLER
18.6 Notes on Using CAN Controller
The CAN controller requires the following settings:
• Bit timing setting
• Frame format setting
• ID setting
• Acceptance filter setting
• Low-power consumption mode setting
■ Setting Bit Timing
The contents of the bit timing register (BTR) must be set while bus operation is halted (i.e.,
HALT in CSR is set to "1").
After the setting was completed, set HALT to "0" to release bus operation stop.
■ Setting Frame Format
Use Message Buffer (x) to set the frame format to be used. To use standard frame format, set
IDEx in the IDE register (IDER) to "0". To use extended frame format, set IDEx to "1".
This setting must be made while the contents of Message Buffer (x) is invalid (i.e., BVALx in the
message buffer enable register (BVALR) is set to"0"). Making the setting at a time when the
contents of the buffer is valid (BVALx = 1) may result in unnecessary receive messages being
stored.
■ Setting the ID
Set the ID of Message Buffer (x) in IDRx (ID28 to ID0) of the ID register. The ID of Message
Buffer (x) need not be set in ID17 to ID0 for standard frame format. The Message Buffer (x) ID is
used for messages to be sent and as acceptance code for receive operations.
This setting must be made while the contents of the Message Buffer (x) is invalid (i.e., while
BVALx in the message buffer enable register (BVALR) is set to"0"). Making the setting while the
contents of the buffer is valid (BVALx = 1) may result in unnecessary receive messages being
stored.
■ Setting the Acceptance Filter
The acceptance filter of Message Buffer (x) is specified via the acceptance code and
acceptance mask setting.
These settings must be made while the contents of message buffer (x) is invalid (i.e., BVALx in
the message buffer enable register (BVALR) set to"0"). Making the settings while the contents
of the buffer is valid (BVALx = 1) may result in unnecessary receive messages being stored.
Set the acceptance mask for each message buffer (x) in the acceptance mask selection register
(AMSR). Also specify the acceptance mask registers (AMR0 and AMR1) if used. (See Sections
18.3.17 "Acceptance Mask Selection Register" and Section 18.3.18 "Acceptance Mask
Registers 0/1", for details on these settings.
An acceptance mask must always be set (even if this results in storing unnecessary receive
messages) to avoid having to clear a transmission request. For example, to send messages
with the same ID, set "full-bit compare."
462
18.6 Notes on Using CAN Controller
■ Setting Low-Power Consumption Mode
To set the F2MC-16LX to "low-power consumption mode" (e.g., stop or clock), set HALT in the
control status register (CSR) to "1", then confirm that bus operation is stopped (HALT = 1).
463
CHAPTER 18 CAN CONTROLLER
18.7 Transmission Via Message Buffer (x)
After specifying the bit timing, frame format, ID, and acceptance filter, set BVALx to "1"
to validate the contents of message buffer (x).
■ Transmission via Message Buffer (x)
❍ Setting the send data length code
Set the send data length code (in units of bytes) in DLCRx (DLC3 to DLC0) of the DLC register.
For data frame transmission (with TRTRx in the transmission RTR register (TRTRR) set to "0"),
specify the data length of the send message.
For remote frame transmission (with TRTRx = 1), specify the data length of the request
message (in units of bytes).
Settings other than 0000 to 1000 (0 to 8 bytes) are prohibited.
❍ Making the send data settings (data frame transmission only)
For data frame transmission (with TRTRx in the transmission RTR register (TRTRR) set to "0"),
set the data for the send byte count in the data register (DTRx).
Send data must be rewritten after setting the TREQx bit in TREQR to "0".
The BVALx bit in the message buffer valid register (BVALR) need not be set to "0". Note that
setting the BVALx bit to "0" may result in a remote frame received being lost.
❍ Setting the transmission RTR register
For data frame transmission, set TRTRx in the transmission RTR register (TRTRR) to "0".
For remote frame transmission, set TRTRx to "1".
❍ Setting the send start conditions (only for data frame transmission)
To start transmission immediately after a data frame transmission request is issued, set RFWTx
in the remote frame receive wait register (RFWTR) to "0", TREQx in the transmission request
register TREQR to "1", and TRTRx in the transmission RTR register (TRTRR) to "0".
Set RFWTX to "1" to delay the start of transmission until a data frame transmission request is
issued (i.e., TREQx = 1 and TRTRx = 0) and a remote frame received (i.e., RRTRx in RRTRR
set to "1").
Setting RFWTx to "1" disables remote frame transmission.
❍ Setting a transmission complete interrupt
To generate a transmission complete interrupt, set TIEx in the transmission interrupt enable
register (TIER) to "1".
Otherwise, set TIEx to "0" (to not generate a transmission complete interrupt).
❍ Setting a transmission request
To issue a transmission request, set TREQx in the transmission request register (TREQR) to
"1".
464
18.7 Transmission Via Message Buffer (x)
❍ Clearing a transmission request
To clear a transmission request to message buffer (x), set TCANx in the transmission cancel
register (TCANR) to "1".
Check TREQx. TREQx = 0 indicates that transmission has been cleared or completed. Check
the TCx bit in TCR). TCx = 0 indicates that transmission is cleared; TCx = 1 indicates that
transmission is completed.
❍ Processing of transmission complete
When transmission is successfully completed, TCx in the transmission complete register (TCR)
is set to "1".
When transmission complete interrupts are enabled (i.e., TIEx in the transmission interrupt
enable register (TIER) is set to "1"), an interrupt is generated.
Check whether transmission is complete, then clear TCx to "0" by writing. Setting TCx to "0"
releases transmission complete interrupts.
In the following cases, a transmission request in wait state is cleared by receiving and storing a
message.
•
Receiving a data frame followed by requesting data frame transmission
•
Receiving a data frame followed by requesting remote frame transmission
•
Receiving a remote frame followed by requesting remote frame transmission
Receiving or storing a remote frame receive message does not clear a request for data frame
transmission. However, the values of ID and DLC will be replaced by the ID and DLC of the
received remote frame; in other words, it is necessary to consider that the ID and DLC values
for the data frame to be sent will become those of the remote frame received.
465
CHAPTER 18 CAN CONTROLLER
18.8 Reception Via Message Buffer (x)
The following settings are required after setting the bit timing, frame format, ID, and
acceptance filter for reception via message buffer (x).
■ Reception via Message Buffer (x)
❍ Making receive interrupt settings
To allow receive interrupts, set RIEx in the receive interrupt enable register (RIER) to "1".
To prohibit receive interrupts, set RIEx to "0".
❍ Starting reception via the message buffer
To start receive operation after making the necessary settings, set BVALx in the message buffer
enable register BVALR to "1" to validate the contents of message buffer (x).
❍ Processing for receive completion
When reception completes successfully after passing the acceptance filter, a receive message
is stored in message buffer (x), and RCx in RCR is set to "1". When a data frame is received,
RRTRx in the remote request transmission register (RRTRR) is set to "0". When a remote frame
is received, RRTRx is set to "1".
When a receive interrupt is enabled (i.e., RIEx in the remote interrupt enable register (RIER) set
to "1"), an interrupt is generated.
Check whether reception completed (RCx = 1), then process the receive message.
When receive message processing is completed, check the ROVRx bit in the receive overrun
register (ROVRR):.
ROVRx = 0 indicates that the received message processed is valid. Write "0" to CRx to set it to
"0" (and clear any receive complete interrupt). This completes the receive operation.
ROVRx = 1 indicates that a receive overrun may have occurred, and that the receive message
processed may have been overwritten by another received message. In such case, clear the
ROVRx bit to "0" by writing so that the receive message is processed again.
Figure 18.8-1 "Example of receive interrupt handling" shows an example of receive interrupt
handling.
466
18.8 Reception Via Message Buffer (x)
Figure 18.8-1 Example of receive interrupt handling
Interrupt by RCx = 1
Read receive message
A=ROVRx
ROVRx=0
A=0?
NO
YES
RCx=0
End
467
CHAPTER 18 CAN CONTROLLER
18.9 Specifying the Multi-Level Message Buffer Configuration
When receive operation is performed frequently or an unspecified number of
messages are received (in other words, when the time becomes insufficient to process
all messages), multiple message buffers may be combined to create a multi-level
message buffer for providing a time reserve for receive message processing by the
CPU.
■ Specifying the Multi-Level Message Buffer Configuration
To prepare a multi- level message buffer, specify the same acceptance filter for all of the
message buffers that are to be combined.
If each bit in the acceptance mask selection register (AMSR) is set to "all-bit compare"
[(AMSx.1, AMSx.0) = (0,0)], the message buffer is not allowed to accept multi-level messages.
This is because all-bit compare enables the storage of receive messages regardless of the
value of the RCx bit in RCR. As a result, even if "all-bit compare" or the same acceptance code
(i.e., IDRx in IDR) is specified for multiple message buffers, a receive message is always stored
in the message buffer with the lowest number (i.e., the one with the highest priority). Therefore,
do not specify "all-bit compare" and the same acceptance code for multiple message buffers.
Figure 18.9-1 "Example of multi-level message buffer operation" shows an example of multilevel message buffer operation.
468
18.9 Specifying the Multi-Level Message Buffer Configuration
Figure 18.9-1 Example of multi-level message buffer operation
Initialize
AMS15,AMS14,AMS13
AMR0 selection
10
10
10
AM2B to AM1B
AMSO
0000
1111
111
Message buffer 13
RC15,RC14,RC13
IDE
ID28 to ID18
0101
000
000
0
RCR
0
0
0
ROVRR
0
0
0
Message buffer 14
0101
000
000
0
Message buffer 15
0101
000
000
0
ROVR15,ROVR14,ROVR13
Mask
Message receive mode: Receive message is stored in message buffer 13.
IDE
ID28 to ID18
Message receive
mode
Message buffer 13
0101
1111
000
0
0101
1111
000
0
RCR
0
0
1
ROVRR
0
0
0
Message buffer 14
0101
0000
000
0
Message buffer 15
0101
0000
000
0
Message receive mode: Receive message is stored in message buffer 14.
0101
1111
001
0
Message buffer 13
0101
1111
000
0
Message buffer 14
0101
1111
001
0
Message buffer 15
0101
0000
000
0
Message receive
mode
RCR
0
1
1
ROVRR
0
0
0
Message receive mode: Receive message is stored in message buffer 15
0101
1111
010
0
Message buffer 13
0101
1111
000
0
Message buffer 14
0101
1111
001
0
Message buffer 15
0101
0000
010
0
Message receive
mode
RCR
1
1
1
ROVRR
0
0
0
Message receive mode: Receive message is stored in message buffer 13.
0101
1111
011
0
Message buffer 13
0101
1111
011
0
Message buffer 14
0101
1111
001
0
Message buffer 15
0101
0000
010
0
Message receive
mode
RCR
1
1
1
ROVRR
0
0
1
Note:
Four messages are received by message buffers 13, 14 and 15 (for which the same
acceptance filter is set).
469
CHAPTER 18 CAN CONTROLLER
18.10 CAN WAKE UP Function
CAN: The RX pin and an external interrupt pin are connected to enable a WAKE UP
function to be used in a CAN receive operation.
■ Pins Used for CAN WAKE UP Function
Connect the RX0 and INT0 pins internally to provide a WAKE UP function. In such case, the
external interrupt function of the INT pin is no longer available.
The RX1 and INT1 pins share a pin so that the WAKE UP function is made available without
having to switch pins.
Table 18.10-1 "CAN WAKE UP function and RX/INT pins" shows the relationship between the
CAN WAKE UP function, RX pin, and INT pin.
Table 18.10-1 CAN WAKE UP function and RX/INT pins
RX pin
Interrupt function
CAN0
RX0
INT0
CAN1
RX1
INT1
■ CAN WAKE UP Function
CAN receive data is used to return from sleep mode, timebase timer mode, watch mode, stop
mode, and each mode.
Notes:
When the WAKE UP function is used in CAN0ch, control the CAN WAKE UP Control
Register and external interrupts before shifting to sleep mode, timebase timer mode, watch
mode, stop mode, and each mode.
When the WAKE UP function is used in CAN1ch, control external interrupts before shifting to
sleep mode, timebase timer mode, watch mode, stop mode, and other modes. It is not
necessary to set a value in the CAN WAKE UP Control Register.
470
18.10 CAN WAKE UP Function
■ Block Diagram of CAN WAKE UP function pin change circuit
Figure 18.10-1 Block diagram of CAN WAKE UP function pin change circuit
P55/RX
1
PIN
Selector
P50/INT0/ADTG
INT0
PIN
003EH
-
0
-
-
-
-
-
-
CWU
CAN WAKE UP control register (CWUCR)
471
CHAPTER 18 CAN CONTROLLER
18.11 Sample Program for CAN Controller
This section shows a sample program for CAN the controller.
■ Sample Program for CAN Transmission/Reception
❍ Specification of processing
Buffer 5 in CAN0 is set up for data frame transmission; buffer 0 is set up for reception.
472
•
Set standard frame format.
•
ID setting: buffer 0 ID = 0, buffer 5 ID=5
•
Bit rate is 100 kbps (internal operation frequency: f = 16 MHz)
•
Acceptance mask (full-bit compare)
•
After entry to the bus (HALT = 0), the data item A0A0 H is sent.
•
Issue a transmission request (TREQx = 1) in the transmission complete interrupt routine to
transmit the same data. (Set TREQx to "transmission start" to clear the transmission
complete interrupt flag.)
•
In the receive interrupt routine, clear the receive interrupt flag.
18.11 Sample Program for CAN Controller
[Coding example]
:
:
:
//data format set (CAN initialize)
MOVW
IDER0,#0000H
; Frame format set (0: standard, 1: extension)
MOVW
BTR0,#05CC7H
; Bit rate set to 100 kbps (internal operation
; frequency f = 16 MHz)
MOVW
BVALR0,#21H
; Message buffer 5,0 valid
MOVW
IDR51,#0A000H
; Data frame 5ID set (ID = 0005)
MOVW
IDR01,#2000H
; Data frame 0ID set (ID = 0001)
MOVW
AMSR00,#0000H
; Acceptance mask selection register (full; bit compare)
//send setting
MOVW
DLCR5,#02H
MOVW
MOVW
RFWTR0,#0000H
TRTRR0,#0000H
MOVW
TIER0,#0020H
//receive setting
MOVW
RIER0,#0001H
//bus operation start
MOV
CSR00,#80H
sthlt
BBS
//send data setting
MOVW
DTR50,#0A0A0H
MOVW
TREQR0,#0020H
; Transfer data length setting (00H: 0-byte
length, 08H: 8-byte length)
; Remote frame receive wait register
; Remote transmission request (0: data sent,
1: remote frame sent)
; Transmission interrupt enable register
; Receive interrupt enable register
; Control status register (HALT = 0)
CSR00:0,sthlt
; HALT = 0 waiting
; Write AOAOH to data register in message
buffer 5
; Transmission request register
; (1: transmission start,
; 0: transmission stop)
:
:
:
//receive complete interrupt
CAN0RX MOVW RCR0,#0000H
; Receive complete register
RETI
//transmission complete interrupt
CAN0TX MOVW TREQR0,#0020H
; Transmission request register (1:
; transmission start, 0: transmission stop)
RETI
:
:
:
473
CHAPTER 18 CAN CONTROLLER
18.12 Precautions when Using CAN Controller
Use of the CAN Controller requires the following cautions.
■ Caution for Disabling Message Buffers by BVAL bits
The use of BVAL bits may affect malfunction of CAN Controller when messages buffers are set
disabled while CAN Controller is participating in CAN communication (read value of HALT bit is
0 and CAN Controller is ready to receive or transmit messages). This section shows the work
around of this malfunction.
❍ Condition
When following two conditions occur at the same time, CAN Controller will not perform to
receive or transmit messages normally.
•
CAN Controller is participating in the CAN communication. (i.e. The read value of HALT bit is
0 and CAN Controller is ready to receive or transmit messages)
•
Message buffers are read or written when the message buffers are disabled by BVAL bits.
❍ Work around
Operation for re-configuring receiving message buffers
While CAN Controller is participating in CAN communication (the read value of HALT bit is 0
and CAN Controller is ready to receive or transmit messages), it is necessary to following
one from the two operations described below to re-configure message buffers by ID, AMS
and AMR0/1 register-settings.
•
Use of HALT bit
Write 1 to HALT bit and read it back for checking the result is 1. Then change the settings for
ID/AMS/AMR0/1 registers.
•
No Use of Message Buffer 0
Don't use the message buffer 0. In other words, disable message buffer (BVAL0=0), prohibit
receive interrupt (RIE0=0) and do not request transmission (TREQ0=0).
Operation for processing received message
Don't use the receiving prohibition by BVAL bit to avoid over-written of next message. Use
the ROVR bit for checking if over-write has been performed. For details, refer to sections
18.3.15 "Receive Overrun Register (ROVRR)" and 18.8 "Reception Via Message Buffer (x)".
Operation for suppressing transmission request
Don't use BVAL bit for suppressing transmission request, use TCAN bit instead of it.
Operation for composing transmission message
For composing a transmission message, it is necessary to disable the message buffer by
BVAL bit to change contents of ID and IDE registers. In this case, BVAL bit should reset
(BVAL=0) after checking iff TREQ bit is 0 or after completion of the previous message
transmission (TC=1).
474
CHAPTER 19
LCD CONTROLLER/DRIVER
This chapter describes the functions and operations of the LCD controller/driver.
19.1 "Outline of LCD Controller/Driver"
19.2 "Configuration of LCD Controller/Driver"
19.3 "LCD Controller/Driver Pins"
19.4 "LCD Controller/Driver Register"
19.5 "LCD Controller/Driver Display RAM"
19.6 "Operation of LCD Controller/Driver"
475
CHAPTER 19 LCD CONTROLLER/DRIVER
19.1 Outline of LCD Controller/Driver
The LCD controller/driver has a built-in display data memory of 16 x 8 bits and controls
the LCD display with 4 common outputs and 24 segment outputs. Three types of duty
output can be selected to directly drive the LCD panel.
■ Function of LCD Controller/Driver
The LCD controller/driver has a built-in display data memory of 16 x 8 bits and controls the LCD
display with 4 common outputs and 24 segment outputs. Three types of duty output can be
selected to directly drive the LCD panel.
•
It has a built-in LCD drive voltage divide resistor. It also allows connection with an external
divide resistor.
•
Uses up to four common outputs (COM0 to COM3) and 24 segment outputs (SEG0 to
SEG23).
•
It has a built-in 16-byte display data memory (display RAM).
•
Selects a duty cycle of 1/2, 1/3, or 1/4 (controlled by setting a bias).
•
Directly drives the LCD.
Table 19.1-1 "Allowed combinations of bias duty" shows the allowed combinations of bias duty.
Table 19.1-1 Allowed combinations of bias duty
Bias
1/2 duty
1/3 duty
1/4 duty
1/2 bias
Y
N
N
1/3 bias
N
Y
Y
Y: Recommended mode
N: Use prohibited
Note:
Pins SEG12 to SEG23 are not used as segment outputs if the general-purpose port is
selected in the LCRH setting.
476
19.2 Configuration of LCD Controller/Driver
19.2 Configuration of LCD Controller/Driver
The LCD controller/driver consists of the blocks listed below. Functionally, it consists
of the controller section, which generates a segment signal and common signal based
on display RAM data, and the driver section, which drives the LCD.
• LCD control register (LCRL/LCRH)
• Display RAM
• Prescaler
• Timing controller
• AC circuit
• Common driver
• Segment driver
• Divide resistor
■ Block Diagram of LCD Controller/Driver
Figure 19.2-1 "Block diagram of LCD controller/driver" shows the block diagram of the LCD
controller/driver.
Figure 19.2-1 Block diagram of LCD controller/driver
V0 V1 V2 V3
Lower bits of LCD control register
(LCRL)
Divide resistor
4
Timebase
timer output
Timing
controller
Common
driver
AC circuit
Internal data bus
Prescale
24
Display RAM 16 x 8 bits
Segment
driver
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG2
SEG3
SEG4
to
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
Upper bits of LCD control register
(LCRH)
Controller
Driver
477
CHAPTER 19 LCD CONTROLLER/DRIVER
❍ Lower bits of LCD control register (LCRL)
Performs LCD drive power control, and is used for selection of display/display blanking, display
mode selection, and LCD clock interval selection.
❍ Upper bits of LCD control register (LCRH)
A register used to switch between segment output and the general-purpose port.
❍ Display RAM
16 x 8-bit RAM used to generate a segment output signal. RAM data is automatically read out in
synchronization with the selected timing of the common signal and output from the segment
output pin.
❍ Prescaler
Generates one of four frame frequencies depending on its setting.
❍ Timing controller
Controls the common signal and segment signal based on the setting of the frame frequency
and LCRL register.
❍ AC circuit
Generates the AC waveform used for driving the LCD from the timing controller signal.
❍ Common driver
A driver for the LCD common pin.
❍ Segment driver
A driver for the LCD Segment Pin.
❍ Divide resistor
A resistor for generating the LCD drive current after dividing. The divide resistor may be
external.
■ Power Supply Voltage of LCD Controller/Driver
The LCD driver’s power supply voltage is determined using a built-in divide resistor or by
connecting a divide resistor to pins V0 to V3.
478
19.2 Configuration of LCD Controller/Driver
19.2.1 LCD Controller/Driver’s Internal Divide Resistor
The LCD driver’s power supply voltage is supplied via an external divide resistor
connected to pins V0 to V3 or an internal divide resistor.
■ LCD Controller/Driver’s Internal Divide Resistor
The LCD controller/driver has a built-in internal divide resistor. The LCD drive power supply pins
(V0 to V3) can be connected to external divide resistors.
The internal divide resistor and external divide resistor are selected by the LCD control
register’s drive power supply control bit (LCRL: VSEL). Setting the VSEL bit to "1" allows the
internal divide resistor to enter the current-carrying state. Therefore, set it to "1" if the internal
divide resistor is to be used instead of the external divide register.
The LCD controller enable is inactive at LCD operation stop (LCRL: MS1, MS0=00B).
Figure 19.2-2 "Equivalent circuit of internal divide resistor" shows an equivalent circuit of the
internal divide resistor.
Figure 19.2-2 Equivalent circuit of internal divide resistor
Vcc
V3
V3
R
Pch
Nch
V2
V2
R
Pch
Nch
V1
V1
R
Pch
Nch
V0
LCD controller
permit
V0
Nch
VSEL
V0 to V3: Voltage at V0 to V3 pins
479
CHAPTER 19 LCD CONTROLLER/DRIVER
■ Using the Internal Divide Resistor
Even if the internal divide resistor is used, connect an external resistor between VCC and V3.
Figure 19.2-3 "Using the internal divide resistor" shows a diagram of using an internal divide
resistor.
For the 1/2 bias setting, short-circuit between the V2 and V1 pins.
Figure 19.2-3 Using the internal divide resistor
Vcc
Vcc
VR
V3
VR
V3
V3
V3
V2
R
V2
V2
R
V1
R
Short-circuited
V1
V1
R
V1
V0
R
V0
R
V0
LCD controller
permit
V0
LCD controller
permit
Q1
1/2 bias
V0 to V3: Voltage between V0 to V3
V2
Q1
1/3 bias
■ Brightness Adjustment When Using the Internal Divide Resistor
If an appropriate brightness cannot be obtained by using the internal divide resistor, place an
external variable resistor (VR) between VCC and V3 to adjust the V3 voltage as shown in Figure
19.2-4 "Brightness adjustment when using the internal divide resistor".
Figure 19.2-4 Brightness adjustment when using the internal divide resistor
Vcc
V3
V3
V2
R
V1
R
V1
V0
R
V0
LCD controller
permit
V2
Q1
Adjusting the brightness
V0 to V3: Voltage between V0 to V3
480
VR
19.2 Configuration of LCD Controller/Driver
19.2.2 LCD controller/driver’s external divide resistor
Uses an external divide resistor or internal divide resistor to generate the LCD drive
voltage.
The brightness can be controlled by connecting a variable register between the VCC
and V3 pins.
■ LCD Controller/Driver’s External Divide Resistor
Connect an external divide resistor between the LCD drive power supply pins (V0 to V3). The
connection of the external divide resistor and LCD drive voltage for the bias scheme are shown
in Figure 19.2-5 "Example connection of the external divide resistor" and Table 19.2-1 "Setting
the LCD drive voltage".
Figure 19.2-5 Example connection of the external divide resistor
Vcc
Vcc
VR
VR
V3
V3
R
R
V2
V2
V LCD
R
VLCD
V1
V1
R
R
V0
V0
V0 = Vss
V0 = Vss
1/3 bias
1/2 bias
Table 19.2-1 Setting the LCD drive voltage
V3
V2
V1
V0
1/2 bias
VLCD
1/2VLCD
1/2VLCD
VSS
1/3 bias
VLCD
2/3VLCD
1/3VLCD
VSS
V0 to V3: Voltage between V0 to V3 pins
VLCD: LCD drive voltage
481
CHAPTER 19 LCD CONTROLLER/DRIVER
■ Using the external divide resistor
If an external divide resistor is used, the current that flows into the resistor when the LCD
controller is stopped can be blocked by connecting the VSS side of the divide resistor to the V0
pin only, because the V0 pin is connected to VSS (GND) via an internal transistor.
Figure 19.2-6 "Situation when external divide resistor is used" shows the situation when an
external divide resistor is used.
Figure 19.2-6 Situation when external divide resistor is used
Vcc
V3
V3
V2
V1
V0
R
V2
R
V1
R
V0
VR
RX
RX
RX
V0 = Vss
LCD controller
enable
Q1
•
To connect an external resistor to inhibit the influence from the internal divide resistor, set
the LCD control register’s drive voltage control bit (LCRL: VSEL) to "0" to disconnect the
entire internal divide resistor.
•
By setting the LCD control register’s display mode selection bits (LCRL: MS1, CMS0) to 00B
when the internal divide resistor is disconnected, the LCDC enable transistor (Q1) is set to
"ON", and the current will pass through the external divide resistor.
•
Setting the display mode selection bits (MS1, MS0) to 00B turns the LCDC permit transistor
(Q1) to "OFF," and the current stops passing through the external divide resistor.
Note:
The RX value for the external resistor depends on the LCD used. Select an appropriate
value.
482
19.3 LCD Controller/Driver Pins
19.3 LCD Controller/Driver Pins
The pins related to the LCD controller/driver are explained below. Their block diagram
is provided as well.
■ LCD Controller/Driver Related Pins
The LCD controller/driver related pins consist of 4 common output pins (COM0 to COM3), C24
segment output pins (SEG0 to SEG23), and 4 LCD drive power supply pins (V0 to V3).
❍ COM0 - COM3 pins
The pins COM0 to COM3 are used as LCD common output pins.
❍ SEG00 to SEG11, P36/SEG12 to P37/SEG13, P40/SEG14 to P47/SEG21, and P90/SEG22 to
P91/SEG23 pins
SEG00 to SEG11 pins are used as LCD segment output pins.
Pins P36/SEG12 to P37/SEG13, P40/SEG14 to P47/SEG22, and P90/SEG22 to P91/SEG23
function both as general-purpose input/output ports (P36, P37, P40 to P47, P90 to P91) and as
LCD segment output pins (SEG12 to SEG13, SEG14 to SEG21,SEG22 to SEG23). The LCRH
register is used to switch between the use of these pins.
❍ V0 to V3 pins
The V0 to V3 pins are used as the LCD drive power supply pins (V0 to V3).
483
CHAPTER 19 LCD CONTROLLER/DRIVER
■ Block Diagram of LCD Controller/Driver Related Pins
Figure 19.3-1 "Block diagram of LCD controller/driver related pins" shows a block diagram of the
pins which also work as segment output pins.
Figure 19.3-1 Block diagram of LCD controller/driver related pins
Pins used also for segment output
Common segment control signal
Pch
Nch
LCD drive voltage (V3 or V2)
LCRH setting
Reset operation stop signal
Pch
Nch
LCD drive voltage (V1 or V0)
Common segment control signal
Stop mode (SPL=1)
or LCD enable
PDR (Port data register)
Internal data bus
PDR read
PDR read (bit operation instruction)
Output latch
Pch
PDR write
Pin
DDR
DDR write
Nch
(Port direction register)
Stop mode (SPL=1) or LCD enable
SPL: Standby control register (STBC): pin state specification bit
V0 to V3: Voltages of V0 to V3 pins
484
P36/SEG12 to P37/SEG13
P40/SEG14 to P47/SEG21
P90/SEG22 to P91/SEG23
19.4 LCD Controller/Driver Register
19.4 LCD Controller/Driver Register
This section describes the registers related to the LCD controller/driver.
■ Bit Configuration of Registers Related to LCD Controller/Driver
Figure 19.4-1 "Bit configuration of LCD controller/driver related registers" shows the bit
configuration of the registers related to the LCD controller/driver.
Figure 19.4-1 Bit configuration of LCD controller/driver related registers
LCRL (Lower bits of LCD control register)
Address
bit7
006CH
CSS LCEN VSEL
R/W
bit6
bit5
R/W R/W
bit4
bit3
bit2
bit1
bit0
Initial value
BK
MS1
MS0
FP1
FP0
00010000B
R/W
R/W
R/W
R/W
R/W
bit11 bit10
bit9
bit8
LCRH (Upper bits of LCD control register)
Address
006DH
bit15
bit14 bit13 bit12
RESV SEG5 SEG4 RESV SEG3 SEG2 SEG1 SEG0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
00000000B
R/W
R/W: Reading/writing permitted
485
CHAPTER 19 LCD CONTROLLER/DRIVER
19.4.1 Lower Bits of LCD Control Register (LCRL)
The lower bits of the LCD control register (LCRL) are used to for drive power control
and to select display blanking or the display mode.
■ Bit Configuration of the Lower Bits of the LCD Control Register (LCRL)
Figure 19.4-2 "Bit configuration of the lower bits of the LCD control register (LCRL)" shows the
bit configuration of the lower bits of the LCD control register (LCRL).
Figure 19.4-2 Bit configuration of the lower bits of the LCD control register (LCRL)
Address
bit7
006CH
CSS LCEN VSEL
R/W
bit6
R/W
bit5
R/W
bit4
bit3
bit2
bit1
bit0
Initial value
BK
MS1
MS0
FP1
FP0
00010000B
R/W
R/W
R/W
R/W
R/W
Frame interval selection bit
FP1 FP0
0
0
Fc/(211 x N)
0
1
Fc/(212 x N)
1
0
Fc/(213 x N)
1
1
Fc/(214 x N)
N: Time-division count
Fc: Oscillation
MS1 MS0
Display mode selection bit
0
0
LCD operation stop
0
1
1/2 duty output mode (time division count: N=2)
1
0
1/3 duty output mode (time division count: N=3)
1
1
1/4 duty output mode (time division count: N=4)
Display blanking selection bit
BK
0
1
Display
Display blanking
LCD drive power control bit
VSEL
External divide resistor used
0
1
LCEN
R/W: Reading/writing permitted
: Initial value
486
Internal divide resistor used
Watch mode operation enable bit
0
Watch mode operation stopped
1
Watch mode operation not stopped
CSS
Clock select bit
0
Main clock selected
1
Sub-clock selected
19.4 LCD Controller/Driver Register
Table 19.4-1 Functional description of each bit among the lower bits of the LCD control register (LCRL)
Bit name
Function
bit7
CSS:
Clock selection bit
Used to select the frame interval generation clock. If this bit is set to "0", the
main clock is selected.
If this bit is set to "1", the sub-clock is selected.
bit6
LCEN:
Watch mode operation
enable bit
Used to enable operation in watch mode.
If this bit is set to "0" in watch mode, operation stops. If this bit is set to "1",
operation is enabled.
bit5
VSEL:
LCD drive power
control bit
Used to select whether the internal divide resistor is supplied with current.
If this bit is set to "0", the internal divide resistor is disconnected. If this bit is
set to "1", the current is supplied. To connect an external divide resistor, set
this bit to "0".
bit4
BK:
Display blanking
selection bit
Used to select LCD display/nondisplay.
In the display section blanking mode (nondisplay, BK=1), the segment
output takes a non-select waveform (waveform outside the pre-defined
display conditions).
bit3
bit2
MS1, MS0:
Display mode
selection bit
Used to select one of three output waveform duties.
The common pin is specified for the duty output mode selected.
If these bits are set to "0", operation of the LCD controller/driver stops.
Note:
If the selected frame interval generation clock stops due to a transition
to the stop mode, stop the display operation in advance.
bit1
bit0
FP1, FP0:
Frame interval
selection bit
Used to select one of four LCD display frame intervals.
Note:
Calculate the optimal frame frequency for the LCD module to be used
and set the register to this value.
The frame frequency is affected by the oscillator frequency.
487
CHAPTER 19 LCD CONTROLLER/DRIVER
19.4.2 Upper Bits of LCD Control Register (LCRH)
The upper bits of the LCD control register (LCRH) are used to switch between segment
output and general-purpose port.
■ Bit Configuration of the Upper Bits of LCD Control Register (LCRH)
Figure 19.4-3 "Bit configuration of upper bits of LCD control register (LCRH)" shows the bit
configuration of the upper bits of the LCD control register (LCRH).
Figure 19.4-3 Bit configuration of upper bits of LCD control register (LCRH)
Address
006DH
bit15 bit14 bit13 bit12 bit11 bit10
bit9
bit8
RESV SEG5 SEG4 RESV SEG3 SEG2 SEG1 SEG0
R/W
R/W
R/W R/W
R/W
R/W R/W
Initial value
00000000B
R/W
Segment output
SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
General-purpose port
Segment output
0
0
0
0
0
0
SEG00 to SEG11
P36,P37,P40 to P47,P90,P91
0
0
0
0
0
1
SEG00 to SEG15
P42 to P47,P90,P91
0
0
0
0
1
1
SEG00 to SEG19
P46,P47,P90,P91
0
0
0
1
1
1
SEG00 to SEG20
P47,P90,P91
0
0
1
1
1
1
SEG00 to SEG21
P90,P91
0
1
1
1
1
1
SEG00 to SEG22
P91
1
1
1
1
1
1
SEG00 to SEG23
RESV
Always set this bit to "0".
R/W: Reading/writing permitted
: Initial value
488
Reserved bit
None
19.4 LCD Controller/Driver Register
Table 19.4-2 Functional description of each bit among the upper bits of the LCD control register
(LCRH)
Bit name
Function
bit15
Reserved
Reserved bit
Always set this bit to "0"
bit14
SEG5:
Segment pin switch bit
Used to set whether the P91/SEG23 pin is used as segment output or
general-purpose port.
bit13
SEG4:
Segment pin switch bit
Used to specify whether the P90/SEG22 pin is used as segment output
or general-purpose port.
bit12
Reserved
Reserved bit
Always set this bit to "0"
bit11
SEG3:
Segment pin switch bit
Used to specify whether the P47/SEG21 pin is used as a segment
output or general-purpose port.
bit10
SEG2:
Segment pin switch bit
Used to specify whether the P46/SEG20 pin is used as a segment
output or general-purpose port.
bit9
SEG1:
Segment pin switch bit
Used to specify whether the P42/SEG16 to P45/SEG19 pins are used
as a segment output or as a general-purpose port.
bit8
SEG0:
Segment pin switch bit
Used to specify whether the P36/SEG12 to P37/SEG13 and P40/SEG14
to P41/SEG15 pins are used as a segment output or as general-purpose
port.
489
CHAPTER 19 LCD CONTROLLER/DRIVER
19.5 Display RAM of the LCD Controller/Driver
The display RAM is a 16 x 8 bit display memory area used to generate a segment
output signal.
■ Display RAM and Output Pins
This RAM is automatically read in synchronization with the timing selected for the common
signal and output from the segment output pin.
If each bit is set to "1", the segment output signal is converted to the selected voltage (LCD
displayed). If each bit is set to "0", the segment output signal is converted to the nonselect
voltage (LCD not displayed) and then output.
The LCD display operates independently of the CPU, therefore reading and writing of the
display RAM can be performed with any timing.
Pins among Pin SEG00 to SEG23 that are not specified by the LCRH register as segment
output are used as general-purpose ports, and the corresponding RAM area is used as normal
RAM. (Table 19.5-1 "Relationship between segment output pins, display RAM, and sharing
pins")
Table 19.5-2 "Relationship between duty, common output, and bits used as display RAM"
shows the relationship between the duty value, common output, and display RAM.
Figure 19.5-1 "Relationship between display RAM, common output pins, and segment output
pins" shows the relationship between display RAM, common output pins, and segment output
pins.
Figure 19.5-1 Relationship between display RAM, common output pins, and segment output pins
Address
3960H
3961H
3962H
3963H
3964H
3965H
3966H
3967H
3968H
3969H
396AH
396BH
490
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
bit3
bit7
bit11
bit15
COM3
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
bit2
bit6
bit10
bit14
COM2
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
bit1
bit5
bit9
bit13
COM1
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
bit0
bit4
bit8
bit12
COM0
SEG00
SEG01
SEG02
SEG03
SEG04
SEG05
SEG06
SEG07
SEG08
SEG09
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
SEG18
SEG19
SEG20
SEG21
SEG22
SEG23
19.5 Display RAM of the LCD Controller/Driver
Table 19.5-1 Relationship between display RAM, common output pins, and segment output pins
Value of SEG5 to SEG0
bit in LCRH register
Segments used
RAM area used for
display
Pin used as generalpurpose port
00_0000B
SEG00 to SEG11 (12)
3960H to 3965H
P36, P37, P40 to P47,
P90, P91
00_0001B
SEG00 to SEG15 (16)
3960H to 3967H
P42 to P47, P90, P91
00_0011B
SEG00 to SEG19 (20)
3960H to 3969H
P46 to P47, P90, P91
00_0111B
SEG00 to SEG20 (21)
3960H to 396AH
P47, 90, P91
00_1111B
SEG00 to SEG21 (22)
3960H to 396AH
P90, P91
01_1111B
SEG00 to SEG22 (23)
3960H to 396BH
P91
11_1111B
SEG00 to SEG23 (24)
3960H to 396BH
None
Note:
RAM area not used for display may be used as normal RAM, allowing byte access only.
Table 19.5-2 Relationship between duty, common output, and bits used as display RAM
Bits used for display data
Duty setting
value
Common output
used
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
1/2
COM0, COM1 (2)
−
−
Y
Y
−
−
Y
Y
1/3
COM0 to COM2 (3)
−
Y
Y
Y
−
Y
Y
Y
1/4
COM0 to COM3 (4)
Y
Y
Y
Y
Y
Y
Y
Y
Y: Used
−: Not used
491
CHAPTER 19 LCD CONTROLLER/DRIVER
19.6 LCD Controller/Driver Operation
The LCD controller/driver performs control and drive operations as required for the
LCD display.
■ LCD Controller/Driver Operations
For the LCD display, the settings shown in Figure 19.6-1 "Settings of LCD controller/driver" are
required.
Figure 19.6-1 Settings of LCD controller/driver
bit7
LCRL
bit6
bit5
bit4
CSS LCEN VSEL BK
bit3
bit2
bit1
bit0
MS1 MS0 FP1 FP0
Other than 00B
bit15 bit14 bit13 bit12 bit11 bit10 bit 9
LCRH
Display RAM
3960H to 396BH
SEG5 SEG4
bit 8
SEG3 SEG2 SEG1 SEG0
Display data
: Bit used
0: Set to 0
The settings of the LCD controller/driver are shown below. When the selected frame interval
generation clock is oscillating, the LCD panel’s drive waveform is output to the common/
segment output pins (COM0 to COM3, SEG00 to SEG23) according to the display RAM.
The frame interval generation clock may be switched even during LCD display operation. Since,
however, the display may flicker in the event of switching, stop the display temporarily with
blanking (LCRL: BK=1) before switching the clock.
The display drive output is a two-frame AC waveform selected by the bias and duty settings.
COM2/COM3 pin output in case of a duty setting of 1/2 takes a non-select level waveform.
Usually, the COM3 pin output in case of a duty setting of 1/3 takes a nonselect level waveform.
If the LCD display operation stops (LCRL: MS1, MS0=00B), or during reset, both common/
segment output pins enter "L" level.
Note:
If, in LCD display operation mode, the frame interval generation clock selected stops, the AC
circuit stops, and then AC current is applied to the LCD element. In this case, LCD display
operation must be stopped in advance. The conditions under which the oscillator clock stops
depends on the standby mode selected.
■ Drive Waveform of the LCD
If the LCD is supplied with DC power, the LCD element undergoes a chemical change causing a
deterioration of the element. Therefore, the LCD controller/driver has a built-in AC circuit to drive
the LCD with a two-frame AC waveform. There are three types of output waveform:
492
•
1/2 bias, 1/2 duty output waveform
•
1/3 bias, 1/3 duty output waveform
•
1/3 bias, 1/4 duty output waveform
19.6 LCD Controller/Driver Operation
19.6.1 Output Waveform During LCD Controller/Driver Operation
(1/2 Duty)
The display drive output is a two-frame AC waveform of the multiplex drive method.
For display with a duty setting of 1/2, only COM0 and COM1 are used. COM2 and COM3
are not used.
■ Output Waveform with 1/2 Bias and 1/2 Duty
The LCD element is turned ON for which the potential difference between the LCD element
common output and segment output is greatest.
The output waveform when the contents of the display RAM is as shown in Table 19.6-1
"Example of display RAM contents" is shown in Figure 19.6-2 "Example of output waveform with
1/2 bias and 1/2 duty".
Table 19.6-1 Example of display RAM contents
Display RAM contents
Segment
COM3
COM2
COM1
COM0
SEGn
−
−
0
0
SEGn+1
−
−
0
1
−: Not used
493
CHAPTER 19 LCD CONTROLLER/DRIVER
Figure 19.6-2 Example of output waveform with 1/2 bias and 1/2 duty
COM0
V3
V2=V1
V0=Vss
COM1
V3
V2=V1
V0=Vss
COM2
V3
V2=V1
V0=Vss
COM3
V3
V2=V1
V0=Vss
SEGn
V3
V2=V1
V0=Vss
SEGn+1
V3
V2=V1
V0=Vss
Potential difference
between COM0
and SEGn
V3 (ON)
V2
Vss
-V2
-V3 (ON)
Potential difference
between COM1
and SEGn
V3 (ON)
V2
Vss
-V2
-V3 (ON)
V3 (ON)
V2
Vss
-V2
-V3 (ON)
Potential difference
between COM0
and SEGn+1
V3 (ON)
V2
Vss
-V2
-V3 (ON)
Potential difference
between COM1
and SEGn+1
1 frame
1 interval
V0 to V3 : Potential difference between the pins for V0 to V3
494
19.6 LCD Controller/Driver Operation
■ Example of LCD Panel Connection Display Data (1/2 Duty Drive Method)
Figure 19.6-3 Example of LCD panel display data
*0
*6
SEGn
SEGn+3
COM1
*1
SEGn+1
*5
*2
*3
n
H
n+1H
*4
SEGn+2
COM0
Address
Example) Displaying "5"
*7
COM3 COM2 COM1 COM0
bit3
bit2
bit1*1
bit0*0 SEGn
bit7
bit6
bit5*3
bit4*2 SEGn+1
bit3
bit2
bit1*5
bit0*4 SEGn+2
bit7
bit6
bit5*7
bit4*6 SEGn+3
[ LCD panel]
3961H
3965H
3964H
3963H
3962H
3961H
3960H
0
1
1
1
0
0
1
1
1
1
0
1
1
0
SEG1
1
0
SEG2
0
1
SEG3
0 : OFF
1 : ON
LCD
display
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
[Segment No.] COM3 COM2 COM1
[Display RAM]
[Address]
*0 to *7: Indicates the correspondence with the display RAM.
Bits 2, 3, 6, and 7 are not used.
Address COM3 COM2 COM1 COM0
SEG0
3960H
1
1
Example of data corresponding
to 0 to 9
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1 1
0
1
1 1
1
1
0 0
0
0
1 0
1
1
1 1
1
0
1 1
0
1
1 0
1
0
1 1
1
1
0 0
1
1
1 0
1
1
1 0
1
1
0 1
1
1
1 1
1
1
0 1
1
1
0 0
0
1
1 1
1
1
1 1
1
1
1 1
1
1
1 0
1
1
1 1
1
1
495
CHAPTER 19 LCD CONTROLLER/DRIVER
19.6.2 Output Waveform in LCD Controller/Driver Operation
(1/3 Duty)
COM0, COM1, and COM2 are used for display with 1/3 duty. COM3 is not used.
■ Output Waveform with 1/3 Bias and 1/3 Duty
The LCD element is turned ON for which the potential difference between the common output
and segment output is greatest.
The output waveform when the contents of the display RAM is as shown in Table 19.6-2
"Example of display RAM contents" is shown in Figure 19.6-2 "Example of output waveform with
1/3 bias and 1/3 duty".
Table 19.6-2 Example of display RAM contents
Display RAM contents
Segment
COM3
COM2
COM1
COM0
SEGn
−
1
0
0
SEGn+1
−
1
0
1
−: Not used
496
19.6 LCD Controller/Driver Operation
Figure 19.6-4 Example of output waveform with 1/3 bias and 1/3 duty
COM0
V3
V2
V1
V0=Vss
COM1
V3
V2
V1
V0=Vss
COM2
V3
V2
V1
V0=Vss
COM3
V3
V2
V1
V0=Vss
SEGn
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
SEGn+1
Potential difference
between COM0
and SEGn
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM1
and SEGn
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM2
and SEGn
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM0
and SEGn+1
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM1
and SEGn+1
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM2
and SEGn+1
1 frame
1 interval
V0 to V3 : Potential difference between the pins for V0 to V3
497
CHAPTER 19 LCD CONTROLLER/DRIVER
■ Example of LCD Panel Connection Display Data (1/3 Duty Drive Method)
Figure 19.6-5 Example of LCD panel display data
Example) Displaying "5"
*3
*0
*6
COM0
*4
SEGn
COM1
COM2
Address
n
H
n+1H
*7
*1
*5
SEGn+1
*8
Address COM3 COM2 COM1 COM0
SEGn+2
3960H
COM3 COM2 COM1 COM0
bit3
bit2*2 bit1*1
bit0*0 SEGn
bit7
bit6*5 bit5*4
bit4*3 SEGn+1
bit3
bit1*7
bit2*8
bit0*6
3961H
SEGn+2
3962H
[LCD display]
0
1
SEG0
1
1
1
SEG1 From bit 0
0
1
0
SEG2
0
0
1
SEG3
1
1
1
SEG4 From bit 4
0
1
0
SEG5
0: OFF
1: ON
0
1
0
1
1
0
1
1
1
0
0
1
0
1
1
SEG4
SEG5
SEG6
SEG7
SEG8
3964H
0
0
0
SEG3
3963H
1
1
1
SEG2
3962H
1
0
1
SEG1
3961H
1
1
0
3960H
LCD
panel
SEG0
[Segment No.] COM3 COM2 COM1 COM0
[Display RAM]
[Address]
*0 to *8: Indicates the correspondence with the display RAM.
Bits 3, 7, and *2 are not used.
0
Example of display data
for 0 to 9
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
1
1
0
1
1
1
1
1
0
1
0
1
1
1
0
1
1
1
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
: Data when starting from bit 4
: Data when starting from bit 0
As 2 digits are indicated by 3 bytes in
1/3 duty operation, two types of data
assignment are allowed: from bit 0/byte
1 and from bit 4/byte 2.
498
19.6 LCD Controller/Driver Operation
19.6.3 Output Waveform in LCD Controller/Driver Operation (1/4
Duty)
COM0, COM1, COM2, and COM3 are used for display with 1/4 duty.
■ Output Waveform with 1/3 Bias and 1/4 Duty
The LCD element is turned ON for which the potential difference between the common output
and segment output is greatest.
The output waveform when the contents of the display RAM is as shown in Table 19.6-3
"Example of display RAM" is illustrated in Figure 19.6-6 "Example of output waveform with 1/3
bias and 1/4 duty".
Table 19.6-3 Example of display RAM
Display RAM contents
Segment
COM3
COM2
COM1
COM0
SEGn
0
1
0
0
SEGn+1
0
1
0
1
499
CHAPTER 19 LCD CONTROLLER/DRIVER
Figure 19.6-6 Example of output waveform with 1/3 bias and 1/4 duty
COM0
V3
V2
V1
V0=Vss
COM1
V3
V2
V1
V0=Vss
COM2
V3
V2
V1
V0=Vss
COM3
V3
V2
V1
V0=Vss
SEGn
V3
V2
V1
V0=Vss
V3
V2
V1
V0=Vss
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
SEGn+1
Potential difference
between COM0
and SEGn
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM1
and SEGn
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM2
and SEGn
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM3
and SEGn
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM0
and SEGn+1
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM1
and SEGn+1
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM2
and SEGn+1
V3 (ON)
V2
V1
Vss
-V1
-V2
-V3 (ON)
Potential difference
between COM3
and SEGn+1
1 frame
1 interval
V0 to V3 : Potential difference between the pins for V0 to V3
500
19.6 LCD Controller/Driver Operation
■ Example of LCD Panel Connection Display Data (1/4 Duty Drive Method)
Figure 19.6-7 Example of LCD panel display data
Example) Displaying "5"
*0
COM3 SEGn
COM0
*4
*7
*5
COM1
*1
*3
*2
*6
COM2
SEGn+1
Address COM3 COM2 COM1 COM0
n
H
bit3*3
bit2*2
bit1*1
bit7*7
bit6*6 bit5*5
Address COM3 COM2 COM1 COM0
SEGn
bit0*0
3960H
bit4*4 SEGn+1
[LCD display]
1
SEG0
0
0
1
1
SEG1
Example of data correspondence
for 0 to 9
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
1
1 0
1 1 1
1
1
1
1 0
0 1 0
0
0
1
1 1
1 0 1
1
0
1
1 1
1 1 1
0
0
1
1 1
0 1 0
0
1
0
1 1
1 1 1
0
1
0
1 1
1 1 1
1
1
1
1 0
1 1 0
0
1
1
1 1
1 1 1
1
1
1
1 1
1 1 1
0
1
1
1
1
3963H
0
1
SEG7
0
0
1
1
SEG6
3962H
1
1
1
1
SEG5
0
1
1
0
SEG4
3961H
0
0
1
1
SEG3
0
0
0
1
SEG2
SEG1
1
1
0
1
3960H
1
1
1
1
1
0: OFF
1: ON
LCD
panel
SEG0
COM0
[Segment No.] COM3 COM2 COM1
[Display RAM]
[Address]
*0 to *7: Indicates the correspondence with the display RAM.
1
501
CHAPTER 19 LCD CONTROLLER/DRIVER
502
CHAPTER 20
LOW-VOLTAGE/CPU OPERATION
DETECTION RESET CIRCUIT
This chapter describes the functions and operations of the low-voltage/CPU operation
detection reset circuit.
20.1 "Outline of the Low-voltage/CPU Operation Detection Reset Circuit"
20.2 "Configuration of the Low-voltage/CPU Operation Detection Reset Circuit"
20.3 "Registers of the Low-voltage/CPU Operation Detection Reset Circuit"
20.4 "Operations of the Low-voltage/CPU Operation Detection Reset Circuit"
20.5 "Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit"
20.6 "Sample Program for the Low-voltage/CPU Operation Detection Reset
Circuit"
503
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.1 Outline of the Low-voltage/CPU Operation Detection Reset
Circuit
The low-voltage detection reset circuit has a function to monitor the power supply
voltage. If it detects a drop in the voltage, an internal reset is generated.
The CPU operation detection reset circuit is a 20-bit counter that uses the oscillator as
a count clock. If it is not cleared within a specific time after it has started, an internal
reset is generated.
■ Low-Voltage Detection Reset Circuit
Table 20.1-1 "Detection voltage of the low-voltage/CPU operation detection reset circuit" shows
the detection voltage.
Table 20.1-1 Detection voltage of the low-voltage/CPU operation detection reset circuit
Detection voltage
4.0V
0.3V
If a low-voltage is detected, the low-voltage detection flag (LVRC: LVRF) is set to "1" and an
internal reset is output.
Because operation continues even in STOP mode, if a low-voltage is detected, an internal reset
is generated with the STOP mode cleared.
In an internal RAM write operation, a low-voltage reset is generated only after the write
operation has been completed. During generation of an internal reset, reset output from this
circuit is suppressed.
■ CPU Operation Detection Reset Circuit
The CPU operation detection reset circuit is a counter to prevent the program from running out
of control. This circuit starts automatically after a power-on reset. After start, the counter of the
circuit must be cleared regularly within a specified time. If the program fails to clear the counter
within the specified time due to a problem, such as an infinite loop, an internal reset is
performed. The CPU operation detection circuit generates an internal reset with a length of 5
machine cycles.
Table 20.1-2 Interval time of the CPU operation detection reset circuit
Interval time
220/FC (about 262 ms)
Note:
Interval time apply for the case the oscillator clock operates at 4 MHz.
504
20.1 Outline of the Low-voltage/CPU Operation Detection Reset Circuit
In any mode in which the CPU stops, this circuit also stops.
The counter clearing conditions of this circuit are listed below.
•
Clearing the LVRC register’s CL bit to "0"
•
Internal reset
•
Stop of oscillator clock
•
Transition to sleep mode
•
Transition to timebase timer mode or watch mode
505
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.2 Configuration of the Low-Voltage/CPU Operation Detection
Reset Circuit
The low-voltage/CPU operation detection reset circuit consists of three blocks:
• CPU operation detection circuit
• Voltage compare circuit
• Low-voltage/CPU operation detection reset control register (LVRC)
■ Block Diagram of the Low-Voltage/CPU Operation Detection Reset Circuit
Figure 20.2-1 "Block diagram of the low-voltage/CPU operation detection reset circuit" shows a
block diagram of the low-voltage/CPU operation detection reset circuit.
Figure 20.2-1 Block diagram of the low-voltage/CPU operation detection reset circuit
Voltage compare
circuit
VCC
+
Constant voltage
source
VSS
CPU operation detection circuit
Oscillator
clock
F/F
Counter
Internal reset
Overflow
Clear
Noise canceller
RESV RESV RESV RESV
CL
LVRF RESV CPUF
Low-Voltage/CPU Operation detection reset control re
Internal data bus
506
20.2 Configuration of the Low-Voltage/CPU Operation Detection Reset Circuit
❍ CPU operation detection circuit
A counter used to prevent the program from running out of control. After its start, the counter
must be cleared regularly within the specified time.
❍ Voltage compare circuit
Compares the detection voltage with the power supply voltage, and if it detects a low-voltage,
outputs the "H" level.
After power-up, it operates continuously.
❍ Low-voltage/CPU operation detection reset control register (LVRC)
Contains flags for low-voltage/CPU operation detection reset and is used to clear the counter for
the CPU operation detection function.
❍ Reset sources for the low-voltage/CPU operation detection reset circuit
If the power supply voltage falls below the detection voltage, an internal reset occurs.
If the counter of the CPU operation detection circuit is not cleared within a certain time, an
internal reset occurs.
507
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.3 Registers of the Low-voltage/CPU Operation Detection
Reset Circuit
The low-voltage/CPU operation detection reset control register (LVRC) contains flags
for low-voltage/CPU operation detection reset and is used is used to clear the counter
for the CPU operation detection circuit.
■ Bit Configuration of the Low-voltage/CPU Operation Detection Reset Control Register (LVRC)
Figure 20.3-1 "Bit configuration of the low-voltage/CPU operation detection reset control register
(LVRC)" shows the bit configuration of the low-voltage/CPU operation detection reset control
register (LVRC).
Figure 20.3-1 Bit configuration of the low-voltage/CPU operation detection reset control register (LVRC)
Address
006EH
bit7
bit6
bit5
bit4
bit3
bit1
bit0
RESV RESV RESV RESV CL LVRF RESV CPUF
R/W R/W R/W R/W
W
CPUF
0
1
LVRF
0
1
CL
0
1
R/W R/W
Initial value
00111000B
R/W
CPU operation detection flag bit
Read
No overflow
Overflow
Write
Clears this bit
Does not change, and has no effect
Low-voltage detection flag bit
Write
Read
Low-voltage detected
Clears this bit
Does not change, and has no effect
No low-voltage detected
CPU operation detection circuit clear bit
Clears counter
Does not change, and has no effect
RESV
Always set this bit to "1"
Reserve bit
RESV
Always set this bit to "0"
Reserve bit
R/W: Reading/writing permitted
W: Writing only
X: Undefined
: Initial value
508
bit2
20.3 Registers of the Low-voltage/CPU Operation Detection Reset Circuit
Table 20.3-1 Functional description of each bit in the low-voltage/CPU operation detection reset control
register
Bit name
Function
bit7
bit6
RESV:
Reserved bit
Always set this bit to "0".
bit4
bit5
RESV:
Reserved bit
Always set this bit to "1".
bit3
CL:
CPU operation
detection clear bit
Used to clear the counter of the CPU operation detection circuit.
By clearing this bit to "0", the counter of the CPU operation detection circuit
will be cleared.
bit2
LVRF:
Low-voltage detection
flag bit
If a drop in power supply voltage is detected, this bit becomes "1".
This bit is cleared by writing "0". Writing "1" has no effect.
This bit is initialized by an external reset, but not by an internal reset.
bit1
RESV:
Reserved bit
Always set this bit to "0".
bit0
CPUF:
CPU operation
detection flag bit
If CPU operation detection function’s counter causes an overflow, this bit is
set to "1".
This bit is cleared by writing "0". Writing "1" has no effect.
This bit is initialized by an external reset, but not by an internal reset.
509
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.4 Operation of the Low-voltage/CPU Operation Detection
Reset Circuit
This circuit is used to monitor the power supply voltage. If the power supply voltage is
lower than the setting value, this circuit generates an internal reset. The CPU detection
function generates an internal reset if the counter is not cleared within a certain
period. It detects low-voltage or the CPU running out of control. If an internal reset
occurs, the register content cannot be assured. When a low-voltage reset is cleared
and the operation stabilization wait time has elapsed, a reset sequence is executed
and the program will restart from the address specified by the reset vector.
■ Operation of the Low-voltage Detection Reset Circuit
The low-voltage detection reset circuit starts low-voltage detection operation after a reset is
cleared. No operation stabilization wait time is required in this case.
■ Operation of the CPU Operation Detection Reset Circuit
The CPU operation detection reset circuit starts CPU detection after a reset is cleared. No
operation stabilization wait time applies in this case.
Note:
As the low-voltage reset circuit is always operating, current flows even in sleep and stop
mode.
510
20.5 Notes on Using the Low-voltage/CPU Operation Detection Reset Circuit
20.5 Notes on Using the Low-voltage/CPU Operation Detection
Reset Circuit
This section provides notes on using the low-voltage/CPU operation detection reset
circuit.
■ Notes on Using the Low-voltage Detection Reset Circuit
❍ Operation stop disabled in the program
The low-voltage detection reset circuit continuously operates when the operation stabilization
wait time has elapsed after power-up. Operations stops by software are not allowed.
❍ Operation in STOP mode
The low-voltage detection reset function operates even in STOP mode. If a low-voltage
condition is detected in STOP mode, a reset occurs and the STOP mode is released.
■ Notes on Using the CPU Operation Detection Reset Circuit
❍ No operation stop by program allowed
The CPU operation detection reset circuit continuously operates after the power-up. No
operation stop is allowed by software.
❍ Resets by CPU operation detection function suppressed
The CPU operation detection function must clear the counter in constant intervals. Clearing the
LVRC register’s CL bit by writing "0" clears the counter to suppress reset generation.
❍ Stopping and clearing the counter
In the modes where the CPU stops, the CPU operation detection function will clear the counter,
causing a stop of operation.
❍ Operation in sub-oscillation mode
The CPU operation detection function will stop operation in sub-oscillation mode. For this
reason, also use the watchdog reset function.
511
CHAPTER 20 LOW-VOLTAGE/CPU OPERATION DETECTION RESET CIRCUIT
20.6 Sample Program for the Low-voltage/CPU Operation
Detection Reset Circuit
This section provides a sample program for the low-voltage/CPU operation detection
reset circuit.
■ Sample Program for the Low-voltage/CPU Operation Detection Reset Circuit
❍ Specification of processing
The counter of the CPU operation detection function is cleared.
[Coding example]
LVRC
;Address of the low-voltage/CPU
;operation detection reset
;control register
;----------Main program-----------------------------------------------------CSEG
;[CODE SEGMENT]
:
MOV
LVRC, #00110101B
;Clears the counter of the CPU
;operation detection function
:
END
512
EQU
006EH
CHAPTER 21
STEPPING MOTOR CONTROLLER
This chapter describes the functions and operation of the stepping motor controller.
21.1 "Outline of the Stepping Motor Controller"
21.2 "Registers of the Stepping Motor Controller"
21.3 "Operation of the Stepping Motor Controller"
21.4 "Notes on Using the Stepping Motor Controller"
513
CHAPTER 21 STEPPING MOTOR CONTROLLER
21.1 Outline of the Stepping Motor Controller
The stepping motor controller consists of two PWM pulse generators, four motor
drivers, and the selector logic circuit.
The four motor drivers have a high output drive capacity and can be directly
connected at the four edges of the two motor coils. A combination of PWM pulse
generator and selector logic is used to control the motor rotation. The synchronization
mechanism assures synchronous operation of the of two PWMs.
■ Block Diagram of the Stepping Motor Controller
Figure 21.1-1 "Block diagram of the stepping motor controller" shows a block diagram of the
stepping motor controller.
Figure 21.1-1 Block diagram of the stepping motor controller
Machine clock
OE1
Prescaler
CK
PWM1Pn
PWM1 pulse generator
EN
P1
Output enable
Selector
PWM1Mn
PWM
P0
PWM1 selection register
PWM1 compare register
OE2
SC
CE
Output enable
PWM2Pn
CK
PWM2 pulse generator
EN
PWM
Selector
PWM2Mn
Load
PWM2 compare selector
514
BS
PWM2 selection register
n: 0 to 3
21.2 Registers of the Stepping Motor Controller
21.2 Registers of the Stepping Motor Controller
The stepping motor controller has five type of registers:
• PWM control register
• PWM1 compare register
• PWM2 compare register
• PWM1 selection register
• PWM2 selection register
■ Registers of the Stepping Motor Controller
Figure 21.2-1 "Registers of the stepping motor controller" shows the registers of the stepping
motor controller.
Figure 21.2-1 Registers of the stepping motor controller
PWM control register (PWC0, PWC1, PWC2, PWC3)
Address
7
6
5
4
0080H,0082H,
OE2
OE1
P1
P0
0084H,0086H
R/W
R/W
R/W
R/W
0
0
0
0
PWM1 compare register (PWC10, PWC11, PWC12, PWC13)
Address
7
6
5
4
D7
D6
D5
D4
3980H,3988H,
3990H,3998H
R/W
R/W
R/W
R/W
X
X
X
X
Address
3981H,3989H,
3991H,3999H
15
14
13
12
PWM2 compare register (PWC20, PWC21, PWC22, PWC23)
Address
7
6
5
4
D7
D6
D5
D4
3982H,398AH,
3992H,399AH
R/W
R/W
R/W
R/W
X
X
X
X
Address
3983H,398BH,
3993H,399BH
15
14
13
12
PWM1 select register (PWS10, PWS11, PWS12, PWS13)
Address
7
6
5
4
P2
P1
3984H,398CH,
3994H,399CH
R/W
R/W
0
0
PWM2 select register (PWS20, PWS21, PWS22, PWS23)
Address
15
14
13
12
BS
P2
P1
3985H,398DH,
3995H,399DH
R/W
R/W
R/W
0
0
0
3
CE
R/W
0
2
SC
R/W
0
1
-
0
TST
R/W
0
3
D3
R/W
X
2
D2
R/W
X
1
D1
R/W
X
0
D0
R/W
X
11
-
10
-
9
D9
R/W
X
8
D8
R/W
X
3
D3
R/W
X
2
D2
R/W
X
1
D1
R/W
X
0
D0
R/W
X
11
-
10
-
9
D9
R/W
X
8
D8
R/W
X
3
P0
R/W
0
2
M2
R/W
0
1
M1
R/W
0
0
M0
R/W
0
11
P0
R/W
0
10
M2
R/W
0
9
M1
R/W
0
8
M0
R/W
0
515
CHAPTER 21 STEPPING MOTOR CONTROLLER
21.2.1 PWM Control Register
The PWM control register is used to control the start/stop operations and interrupts of
the stepping motor controller. Moreover, it is used to specify the external output pins.
■ Bit configuration of the PWM Control Register
Figure 21.2-2 "Bit configuration of the PWM control register" shows the bit configuration of the
PWM control register.
Figure 21.2-2 Bit configuration of the PWM control register
7
OE2
6
OE1
5
P1
4
P0
3
CE
2
SC
1
-
0
TST
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
-
R/W
0
[bit 7] OE2: Output enable bit
If the OE2 bit is set to "1", external pins are used for PWM2P0, PWM2P1, PWM2P2,
PWM2P3 and PWM2M0, PWM2M1, PWM2M2, PWM2M3. If the bit is "0", these pins can be
used as general-purpose I/O ports.
[bit 6] OE1: Output enable bit
If the OE1 bit is set to "1", external pins are used for PWM1P0, PWM1P1, PWM1P2,
PWM1P3 and PWM1M0, PWM1M1, PWM1M2, PWM1M3. If the bit is "0", these pins can be
used as general-purpose I/O ports.
[bit 5 to 4] P1 to P0: Operation clock selection bit
The bits P1 to P0 are used to specify the clock input signal to the PWM pulse generator.
P1
P0
Clock input
0
0
Machine clock
0
1
1/2 machine clock
1
0
1/4 machine clock
1
1
1/8 machine clock
[bit 3] CE: Count enable bit
The CE bit is used to permit PWM pulse generator operation. The PWM pulse generator
start operation when the CE bit is set to "1". Note that the PWM2 pulse generator will start
one machine clock cycle after the PWM1 pulse generator, which is helpful for decreasing the
switching noise from the output driver.
By clearing the CE bit to "0", the PWM pulse generator is initialized and then stops.
[bit 2] SC: 8/10-bit switch bit
If the SC bit is set to "1", PWM operates with 10 bits. If set to "0", PWM operates with 8 bits.
[bit 0] TST: Test bit
The TST bit is used for device tests. The TST bit must always be cleared to "0" by the
application program of the user.
516
21.2 Registers of the Stepping Motor Controller
21.2.2 PWM1 and PWM2 Compare Registers
The contents of the two 8-bit or 10-bit compare registers, PWM1 and MWM2, specifies
the width of the PWM pulse. A value of 00H (000H) indicates that the PWM’s duty is 0%,
while FFH (3FFH) indicates that the duty is 99.6% (99.9%).
■ Bit Configuration of the PWM1 and PWM2 Compare Registers
The PWM1/PWM2 compare registers can be accessed at any time. Any change in values
changes the pulse width at the end of the current PWM cycle after the PWM2 selection
register’s BS bit has been set to "1".
This register requires access in units of words.
Figure 21.2-3 "Bit configuration of the PWM1/PWM2 compare registers" shows the bit
configuration of the PWM1 and PWM2 compare registers. Figure 21.2-4 "Setting the PWM
pulse width" shows the relationship between the PWM pulse width and the setting value.
Figure 21.2-3 Bit configuration of the PWM1/PWM2 compare registers
PWM1 compare register
PWM2 compare register
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
-
14
-
13
-
12
-
11
-
10
-
9
D9
8
D8
-
-
-
-
-
-
R/W
X
R/W
X
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
15
-
14
-
13
-
12
-
11
-
10
-
9
D9
8
D8
-
-
-
-
-
-
R/W
X
R/W
X
517
CHAPTER 21 STEPPING MOTOR CONTROLLER
Figure 21.2-4 Setting the PWM pulse width
One PWM cycle
256 (1024) input cycles
Register value
000h
80h (200h)
FFh (3FFh)
518
128 (512) input cycles
255 (1023) input cycles
21.2 Registers of the Stepping Motor Controller
21.2.3 PWM1/PWM2 Selection Registers
The PWM1/PWM2 selection registers are used to select whether the stepping motor
controller’s external pin output is "L", "H", a PWM pulse, or high-impedance.
■ Bit Configuration of PWM1/PWM2 Selection Registers
Figure 21.2-5 "Bit configuration of the PWM1/PWM2 selection registers" shows the bit
configuration of the PWM1/PWM2 selection registers.
Figure 21.2-5 Bit configuration of the PWM1/PWM2 selection registers
PWM1 selection register
PWM2 selection register
7
-
6
-
5
P2
4
P1
3
P0
2
M2
1
M1
0
M0
-
-
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
15
-
14
BS
13
P2
12
P1
11
P0
10
M2
9
M1
8
M0
-
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
[bit 14] BS: Rewrite bit
The BS bit is used for keeping in synchronization with respect to the settings for PWM
output. Any changes applied to the two compare registers and two select registers before the
BS bit is set will not be reflected to the output signal.
When the BS bit is set to "1", the PWM pulse generator and selector load the register content
at the end of the current PWM cycle. The BS bit is automatically reset to "0" at the start of
the following PWM cycle. If the BS bit is set to "1" by software at the same time as an
automatic reset, the BS bit will be set to "1" (i.e., remains unchanged), and the automatic
reset is cancelled.
[bit 13 to 11] P2 to P0: Output selection bits
The bits P2 to P0 are used to select the output signal at PWM2P0.
[bit 10 to 8] M2 to M0: Output selection bits
The bits M2 to M0 are used to select the output signal at PWM2M0.
[bit 5 to 3] P2 to P0: Output selection bit
The bits P2 to P0 are used to select the output signal at PWM1P0.
519
CHAPTER 21 STEPPING MOTOR CONTROLLER
[bit 2 to 0] M2 to M0: Output selection bit
The bits M2 to M0 are used to select the output signal at PWM1M0. The table below shows
the relationship between the output level and selection bits.
520
P2
P1
P0
PWMnP0
M2
M1
M0
PWMnM0
0
0
0
L
0
0
0
L
0
0
1
H
0
0
1
H
0
1
X
PWM pulse
0
1
X
PWM pulse
1
X
X
High-impedance
1
X
X
High-impedance
21.3 Operation of the Stepping Motor Controller
21.3 Operation of the Stepping Motor Controller
This section describes the operation of the stepping motor controller.
■ Settings for Stepping Motor Controller Operation
Operation of the stepping motor controller requires the settings listed in Figure 21.3-1 "Settings
of the stepping motor controller".
Figure 21.3-1 Settings of the stepping motor controller
bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
TST
OE2 OE1 P1 P0 CE SC
PWCn
1
0
PWC1n
Specifies the width of the "H" level (compare value) in PWM1
PWC2n
Specifies the width of the "H" level (compare value) in PWM2
P2
PWS1n
PWS2n
BS
P2
P1
P0
M2
M1 M0
P1
P0
M2
M1 M0
: Bit used
: Bit unused
1: Set to 1
0: Set to 0
n: Channel No.
❍ Operation of the PWM pulse generation circuit
As soon as the counter starts (PWCn: CE=1), counting starts from "00H" at the rising edge of
the clock signal selected. The PWM output waveform stays at the "H" level until the counter
value matches the value set in the PWM compare register and then stays at the "L" level until
an overflow of the counter value occurs (FFH -> 00H).
Figure 21.3-2 "Example of PWM1/PWM2 waveform outputs" shows the PWM waveform
generated by the PWM generation circuit.
521
CHAPTER 21 STEPPING MOTOR CONTROLLER
Figure 21.3-2 Example of PWM1/PWM2 waveform outputs
If the compare register value is "00H" respectively "000H" (duty ratio: 0 %)
3FFH000H
FFH00H
000H
Counter value 00H
H
PWM waveform
L
If the compare register value is "80H" respectively "200H" (duty ratio: 50 %)
200H
000H
3FFH000H
80H
Counter value 00H
FFH00H
PWM waveform
H
L
If the compare register value is "FFH" respectively "3FFH" (duty ratio: 99.6 % / 99.9 %)
000H
3FFH000H
Counter value 00H
FFH00H
PWM waveform
H
L
1 count
❍ Selection of motor drive signal
The stepping motor controller related pin outputs the motor drive signal, which can be set to one
of four types separately for each pin by setting the PWM selection register.
Table 21.3-1 "Selection of the motor drive signal and settings of the PWM selection registers 1
and 2" shows the selection of the motor drive signal and the settings of PWM Selection Register
1 and PWM Selection Register 2.
If the BS bit of PWM Selection Register 2 is set to "1" after the above settings have been made,
the new setting value will become effective at the end of the current PWM cycle. This BS bit is
automatically cleared at the start of the PWM cycle. If setting the BS bit and clearing the BS bit
both occur at the beginning of the PWM cycle, setting the BS bit has priority and clearing the BS
bit is cancelled.
Table 21.3-1 Selection of the motor drive signal and settings of the PWM selection
registers 1 and 2
522
P2, P1, P0 bits
PWM1P output
PWM2P output
M2, M1, M0 bits
PWM1M output
PWM2M output
000B
L
000B
L
001B
H
001B
H
01XB
PWM pulse
01XB
PWM pulse
1XXB
High- impedance
1XXB
High- impedance
21.4 Notes on Using the Stepping Motor Controller
21.4 Notes on Using the Stepping Motor Controller
This section provides notes on using the stepping motor controller.
■ Notes on Changing the PWM Setting Values
PWM Compare Register 1 (PWC1n), PWM Compare Register 2 (PWC2n), PWM Selection
Register 1 (PWS1n), and PWM Selection Register 2 (PWS2n) can always be accessed. To
change the setting of the PWM’s "H" width or PWM output, write the setting values to these
registers, then set the BS bit of PWM Selection Register 2 to "1" (or do this simultaneously).
If the BS bit is set to "1", the new setting value will become effective at the end of the current
PWM cycle, and the BS bit is automatically cleared.
If setting the BS bit to "1" and resetting the BS bit at the end of the PWM cycle both occur at the
same time, writing "1" has priority and resetting the BS bit will be cancelled.
523
CHAPTER 21 STEPPING MOTOR CONTROLLER
524
CHAPTER 22
SOUND GENERATOR
This chapter describes the functions and operation of the sound generator.
22.1 "Outline of the Sound Generator"
22.2 "Registers of the Sound Generator"
525
CHAPTER 22 SOUND GENERATOR
22.1 Outline of the Sound Generator
The sound generator consists of the sound control register, frequency data register,
amplitude data register, decrement grade register, tone count register, PWM pulse
generator, frequency counter, decrement counter, and tone pulse counter.
■ Block Diagram of the Sound Generator
Figure 22.1-1 "Block diagram of the sound generator" shows a block diagram of the sound
generator.
Figure 22.1-1 Block diagram of the sound generator
Clock input
Prescaler
S1
S0
8-bit PWM
pulse generator
CO
EN
PWM
CI
Toggle
flip-flop
Frequency
counter
Reload
Reload
Q
1/d
Frequency
data register
Amplitude
data register
DEC
DEC
Decrement
counter
D
EN
CO
EN
CI
CO
EN
SGA
OE1
Decrement
grade register
Tone pulse
counter
Tone count
register
Mixing
unit
TONE OE2
OE1
SGO
OE2
CI
CO
EN
INTE
INT
ST
IRQ #34
526
22.2 Registers of the Sound Generator
22.2 Registers of the Sound Generator
The sound generator has the following types of registers:
• Sound control register (SGCR)
• Frequency data register (SGFR)
• Amplitude data register (SGAR)
• Decrement grade register (SGDR)
• Tone count register (SGTR)
■ Registers of the Sound Generator
Figure 22.2-1 "Registers of the sound generator" shows the registers of the sound generator.
Figure 22.2-1 Registers of the sound generator
Upper bits of the sound
control register
Address: 00005BH
Reading/writing =>
Initial value =>
Lower bits of the sound
control register
Address: 00005AH
Reading/writing =>
Initial value =>
Amplitude data register
Address: 00005DH
Reading/writing =>
Initial value =>
Frequency data register
Address: 00005CH
Reading/writing =>
Initial value =>
Tone count register
Address: 00005FH
Reading/writing =>
Initial value =>
Decrement grade register
Address: 00005EH
Reading/writing =>
Initial value =>
15
TST
14
-
13
-
12
-
11
-
10
-
9
BUSY
(R/W)
(0)
-
-
-
-
-
(R)
(0)
(R/W)
(0)
7
S1
6
S0
(R/W)
(0)
(R/W)
(0)
15
D7
5
TONE
8
DEC
4
OE2
3
OE1
2
INTE
1
INT
0
ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
15
D7
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
<= Bit number
SGCRH
<= Bit number
SGCRL
<= Bit number
SGAR
<= Bit number
SGFR
<= Bit number
SGTR
<= Bit number
SGDR
527
CHAPTER 22 SOUND GENERATOR
22.2.1 Sound Control Register
The sound control register is used to set the interrupt control and external output pins
for the sound generator and control its operation.
■ Bit Configuration of the Sound Control Register
Figure 22.2-2 "Bit configuration of the sound control register" shows the bit configuration of the
sound control register.
Figure 22.2-2 Bit configuration of the sound control register
Upper bits of the sound
control register
15
Address: 00005BH
TST
Reading/writing => (R/W)
Initial value => (0)
Lower bits of the sound
control register
7
Address: 00005AH
S1
Reading/writing => (R/W)
Initial value => (0)
14
-
13
-
12
-
11
-
10
-
9
BUSY
8
DEC
-
-
-
-
-
(R)
(0)
(R/W)
(0)
6
S0
5
TONE
4
OE2
3
OE1
2
INTE
1
INT
0
ST
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
<= Bit number
SGCRH
<= Bit number
SGCRL
[bit 15] TST: Test bit
This bit is used for device tests. It must be cleared to "0" by the user’s application program.
[bit 9] BUSY: Busy bit
This bit indicates whether the sound generator is operating. It is set to "1" at the same time
the ST bit is set to "1". If the ST bit is set to "1", it will be reset to "0" when the operation is
completed at the end of one tone cycle. This bit cannot be changed by write operations.
[bit 8] DEC: Automatic decrement enable bit
The DEC bit is used together with the decrement grade register to automatically perform
sound degradation.
If this bit is set to "1", the tone pulse count in the toggle flip-flop specified by the decrement
grade register is decremented by the decrement counter’s count and the value stored in the
amplitude data register is decremented by 1.
[bit 7 to 6] S1 to S0: Operation clock selection bit
This bit group is used to specify the clock input signal for the sound generator.
528
S1
S0
Clock input
0
0
Machine clock
0
1
1/2 machine clock
1
0
1/4 machine clock
1
1
1/8 machine clock
22.2 Registers of the Sound Generator
[bit 5] TONE: Tone output bit
If this bit is set to "1", the SGO signal becomes a simple rectangular waveform (tone pulse
from the flip-flop). In other cases, the signal becomes a mixed (by AND logic) signal of the
tone pulse and PWM pulse.
[bit 4] OE2: Sound output enable bit
If this bit is set to "1", an external pin is assigned to be used for SGO output. In other cases,
the pin is a general-purpose pin.
[bit 3] OE1: Amplitude output enable bit
If this bit is set to "1", the external pin is assigned to be used for SGA output. In other cases,
the pin is a general-purpose pin.
The SGA signal is a PWM pulse from the PWM pulse generator indicating the sound
amplitude.
[bit 2] INTE: Interrupt enable bit
This bit is used to enable interrupt signals of the sound generator. If this bit is set to "1" and
the INT bit is set to "1", then the sound generator reports an interrupt with a signal.
[bit 1] INT: Interrupt bit
This bit is set to "1" if the tone pulse count specified by the tone count register and
decrement grade register is counted by the tone pulse counter.
This bit is reset by writing "0". Writing "1" has no effect, and read-modify-write instructions
always return "1".
[bit 0] ST: Start bit
This bit is used to start sound generator operation. As long as this bit is "1", the sound
generator is operating.
If this bit is reset to "0", the sound generator stops its operation at the end of the current tone
cycle. The BUSY bit indicates whether the sound generator completely stops its operation.
529
CHAPTER 22 SOUND GENERATOR
22.2.2 Frequency Data Register
The frequency data register is used to store the reload value for the frequency counter.
The value stored indicates a sound frequency (or tone signal from the toggle flip-flop).
The register value is reloaded to the counter each time a toggle signal progresses.
■ Frequency Data Register
Figure 22.2-3 "Bit configuration of frequency data register" shows the bit configuration of the
frequency data register. Figure 22.2-4 "Relationship between register value and tone signal"
shows the relationship between tone signals and register values.
Figure 22.2-3 Bit configuration of frequency data register
Frequency data register
Address: 00005CH
Reading/writing =>
Initial value =>
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
<= Bit number
SGFR
Figure 22.2-4 Relationship between register value and tone signal
One tone cycle
Tone signal
(register value + 1) x
1 PWM cycle
(register value + 1) x
1 PWM cycle
Note:
Changing the register value during operation may cause a deviation of a 50% duty cycle.
530
22.2 Registers of the Sound Generator
22.2.3 Amplitude Data Register
The amplitude data register is used to store a reload value of the PWM pulse
generator. The register value indicates the sound amplitude. It is reloaded to the PWM
pulse generator each time a tone cycle ends.
■ Amplitude Data Register
Figure 22.2-5 "Bit configuration of the amplitude data register" shows the bit configuration of the
amplitude data register.
Figure 22.2-5 Bit configuration of the amplitude data register
Amplitude data register
Address: 00005DH
Reading/writing =>
Initial value =>
15
D7
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
(R/W)
(0)
<= Bit number
SGAR
If the decrement counter reaches the reload value while the DEC bit is "1", the register value is
decremented by 1. If the register value reaches "00", no more decrement is made to the register
value, and the sound generator continues is operation until the ST bit is cleared.
Figure 22.2-6 "Relationship between register value and PWM pulse" shows the relationship
between register values and PWM pulses.
Figure 22.2-6 Relationship between register value and PWM pulse
One PWM cycle
256 input clock cycles
Register value
00h
One input clock cycle
80h
129 input clock cycles
FEh
255 input clock cycles
FFh
256 input clock cycles
When the register value is set to "FF", the PWM signal is always set to "1".
531
CHAPTER 22 SOUND GENERATOR
22.2.4 Decrement Grade Register
The decrement grade register loads a reload value into the decrement counter. It is
used to automatically decrement a value in the amplitude data register.
■ Decrement Grade Register
Figure 22.2-7 "Bit configuration of decrement grade register" shows the bit configuration of the
decrement grade register.
Figure 22.2-7 Bit configuration of decrement grade register
Decrement grade register
Address: 00005EH
Reading/writing =>
Initial value =>
7
D7
6
D6
5
D5
4
D4
3
D3
2
D2
1
D1
0
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
<= Bit number
SGDR
If, with DEC bit set to "1", the decrement counter counts a tone pulse up to the reload value, the
amplitude data register is decremented by 1 at the end of the tone cycle.
This operation performs automatic sound degradation while reducing the amount of required
CPU intervention.
Note that the tone pulse count specified by the register becomes "register value +1". With the
decrement grade register set to "00", the decrementing operation is performed every tone cycle.
532
22.2 Registers of the Sound Generator
22.2.5 Tone Count Register
The tone count register stores the reload value to the tone pulse counter. The tone
pulse counter stores a tone pulse count (or the count of a decrement operation), and if
it reaches the reload value, the INT bit is set. This is designed to decrease the
frequency of interrupts.
■ Tone Count Register
Figure 22.2-8 "Bit configuration of the tone count register" shows the bit configuration of the
tone count register.
Figure 22.2-8 Bit configuration of the tone count register
Tone count register
Address: 00005FH
Reading/writing =>
Initial value =>
15
D7
14
D6
13
D5
12
D4
11
D3
10
D2
9
D1
8
D0
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
(R/W)
(X)
<= Bit number
SGTR
The tone pulse counter’s count input is connected with the carry-out signal from the decrement
counter. If the tone count register is set to "00", the tone pulse counter sets the INT bit every
time a carry-out occurs at the decrement counter. Therefore, the tone pulse count stored is:
((decrement grade register)+1) x ((tone count register)+1)
In other words, if both registers are set to "00", the INT bit is set every tone cycle.
533
CHAPTER 22 SOUND GENERATOR
534
CHAPTER 23
ADDRESS MATCH DETECTION FUNCTION
This chapter describes functions and operations of the address matching detection.
23.1 "Outline of the Address Match Detection Function"
23.2 "Example Application of the Address MATCH DETECTION FUNCTION"
535
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
23.1 Outline of the Address Match Detection Function
If the address setting is the same as in the address detection register, the INT9
instruction is executed. The INT9 interrupt service routine is executed to provide an
address match detection function.
Two address detection registers, each of which has a compare enable bit, are
provided. If the address detection register and program counter match, and the
compare enable bit is set to "1", the CPU forces execution of an INT9 instruction.
■ Block Diagram of the Address Match Detection Function
Figure 23.1-1 "Block diagram of the address match detection function" shows a block diagram
of the address match detection function.
Address latch
Address detection register
Enable bit
Compare
Figure 23.1-1 Block diagram of the address match detection function
F2MC-16LX
CPU core
F2MC-16LX bus
536
23.1 Outline of the Address Match Detection Function
■ Register Configuration for the Address Match Detection Function
Figure 23.1-2 "Register configuration of the address match detection function" shows the
register configuration for the address match detection function.
Figure 23.1-2 Register configuration of the address match detection function
byte
Access
Initial value
PADR0 Address: 1FF2H/1FF1H/1FF0H
R/W
Unspecified
PADR1 Address: 1FF5H/1FF4H/1FF3H
R/W
Unspecified
7
Bit number
PACSR Address: 00009EH
6
byte
5
4
byte
3
2
1
0
Reserve Reserve Reserve Reserve AD1E Reserve AD0E Reserve
R/W
Initial value
----0-0-B
R/W
■ Program Address Detection Register (PADR0/PADR1)
The program address detection register is a register used to store an address for comparison
with the program counter. If the values match and the corresponding ADCSR compare enable
bit is set to "1", this module requests execution of the INT9 instruction by the CPU.
If the corresponding interrupt enable bit is set to "0", no actions are taken.
Figure 23.1-3 "Configuration of the program address detection register" shows the configuration
of the program address detection register.
Figure 23.1-3 Configuration of the program address detection register
Access
Initial value
PADR0 Address: 1FF2H/1FF1H/1FF0H
R/W
Unspecified
PADR1 Address: 1FF5H/1FF4H/1FF3H
R/W
Unspecified
byte
byte
byte
Correspondence with PACSR is shown below.
Program address detection register
Interrupt enable bit
PADR0
AD0E
PADR1
AD1E
537
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
■ Program Address Detection Control Register (PACSR)
The program address detection control register (PACSR) controls the operation of the address
detection function and indicates its state.
Figure 23.1-4 "Bit configuration of the program address detection control register (PACSR)"
shows the bit configuration of the program address detection control register (PACSR).
Figure 23.1-4 Bit configuration of the program address detection control register (PACSR)
7
PACSR Address: 00009EH
6
5
4
3
2
1
0
<= Bit number
Reserve Reserve Reserve Reserve AD1E Reserve AD0E Reserve
Reading/writing =>
(-)
(-)
(-)
(-)
Initial value =>
(-)
(-)
(-)
(-)
(R/W) ( - )
( 0)
(-)
(R/W) ( - )
( 0)
(-)
[bit 7 to 4]
Reserved bits, always keep this bits "0".
[bit 3] AD1E (Compare Enable 1)
A bit to permit the PADR1 operation.
If this bit is set to "1" and the values in a comparison of PADR1 register and the address
match, the INT9 instruction is issued to the CPU.
[bit 2]
A reserved bit, always keep this bit "0".
[bit 1] AD0E (Compare Enable 0)
Enable bit for PADR0 operation.
If this bit is set to "1", the PADR0 register and program counter are compared and, if the their
values match, the INT9 instruction is issued to the CPU.
[bit 0]
A reserved bit, always keep this bit "0".
■ Operation of the Address Match Detection Function
If the program counter has the same address as the program address detection register, the
INT9 instruction is executed. By processing the INT9 interrupt service routine, an address match
detection function is provided.
Two address detection registers, each of which has a compare enable bit, are provided. If the
address detection register and program counter match, and the compare enable bit is "1", the
CPU forces execution of the INT9 instruction.
Notes:
If the values of address detection register and program counter match, the contents of the
internal data bus are replaced with "01H" and the INT9 instruction is executed. Change the
contents in the address detection register after the compare enable bit is set to "0". Changing
it when the compare enable bit is set to "0" may cause an error.
The address match detection function is only effective for the address in the built-in ROM.
Even if an address in the external memory area is specified, no INT9 instruction is executed.
538
23.2 Example Application of Address Match Detection Function
23.2 Example Application of Address Match Detection Function
The address match detection function is realized by an external EEPROM storing
correction related information and patch programs. The CPU uses such information to
specify an address for which a correction must be applied to the address match
detection function, and transfers the patch program to RAM. Using the address match
detection function, the INT9 instruction is executed so that the patch program can
become subject to processing.
■ System Configuration
Figure 23.2-1 "Sample system configuration" shows a sample system configuration.
Figure 23.2-1 Sample system configuration
EEPROM
MCU
F2MC-16LX
Pull-up resistor
SIN
Connector (UART)
■ EEPROM Memory Map
The EEPROM memory map is shown in Table 23.2-1 "EEPROM memory map".
Table 23.2-1 EEPROM memory map
Address
Contents
0000H
Byte count of correction program No. 0 (No ROM correction for count = 0)
0001H
Bit 7 to 0 of program address No. 0
0002H
Bit 15 to 8 of program address No. 0
0003H
Bit 24 to 16 of program address No. 0
0004H
Correction program No. 1 byte count (No ROM corrected if count = 0)
0005H
Bit 7 to 0 of program address No. 1
0006H
Bit 15 to 8 of program address No. 1
0007H
Bit 24 to 16 of program address No. 1
00010H to
Main part of correction program No. 0/1
Note:
In the initial state, the contents of the EEPROM must be all zeros.
539
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
23.2.1 Example of Program Error Correction
The main part of the program and program addresses are transferred to MCU via the
connector (UART). MCU writes this information into EEPROM.
■ If a Program Error Occurs
Figure 23.2-2 "Example of address match detection function processing" shows an example of
address match detection function processing in which a program error occurs.
Figure 23.2-2 Example of address match detection function processing
MB90420G/425G series device
FFFFFFh
(3)
ROM
(1)
PC = error address
Program with error
External E 2PROM
Register setting for
address match
- Program byte count
- Interrupt generation address
- Corrected program
Data transfer using UART
(2)
RAM
000000h
540
Corrected program
23.2 Example Application of Address Match Detection Function
23.2.2 Example of Correction Processing
The MCU reads out the EEPROM value after resetting. Provided the byte count of the
patch program is not "0", the MCU reads the main part of the patch program and writes
it to RAM. It then sets PADR0 or PADR1 to the program address to enable the
operation. The start address of the program written to RAM is stored in RAM under the
address specified in the respective address detection register.
In this case, the INT9 service routine searches for the user defined address to jump to
the corrected program.
■ Flowchart of Address Match Detection Function Processing
Figure 23.2-3 "Flowchart of address match detection function processing" shows a flowchart of
the address match detection function processing.
Figure 23.2-3 Flowchart of address match detection function processing
Reset
INT9
Reads 00h of E2PROM
YES
0000h (E2PROM) =0
NO
Reads address
0001h to 0003h (E2PROM)
MOV
PADR0 (MCU)
Jumps to corrected program
JMP 000400h
Executes corrected program
000400h to 000480h
Reads corrected program
0010h to 0090h (E2PROM)
MOV
000400h to 000480h (MCU)
Ends corrected program
JMP FF0050h
Enables compare process
MOV PACSR, #02h
Executes normal program
NO
PC=PADR0
YES
INT9
541
CHAPTER 23 ADDRESS MATCH DETECTION FUNCTION
Figure 23.2-4 Diagram of address match detection function processing
FFFFFFh
MB90420G/425G series
FF0050h
Error program
ROM
FF0000h
E2PROM
FFFFh
0090h
FE0000h
Corrected program
0010h
001100h
Lower bytes of program address: 00
0003h
0002h
0001h
0000h
Middle bytes of program address: 00
Upper bytes of program address: 00
Byte count of corrected program: 80
Stack area
RAM area
000480h
Patch program
RAM
000400h
RAM/register area
000100h
I/O area
000000h
■ INT9 Interrupt
In the interrupt routine, the address that caused an interrupt is identified by the PC value which
was swapped out to the stack, and operation branches to the corresponding program.
Information loaded on the stack by an interrupt is discarded.
542
CHAPTER 24
ROM MIRROR FUNCTION SELECTION
MODULE
This chapter describes the ROM mirror function selection module.
24.1 "Outline of ROM Mirror Function Selection Module"
24.2 "ROM Mirror Function Selection Register (ROMM)"
543
CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE
24.1 Outline of the ROM Mirror Function Selection Module
The ROM mirror function selection module is used to select via register settings an FF
bank in ROM, whose contents can be viewed via bank 00.
■ Register of ROM mirror function selection module
Figure 24.1-1 "Bit configuration of ROM mirror function selection module register" shows the bit
configuration of the ROM mirror function selection module register.
Figure 24.1-1 Bit configuration of ROM mirror function selection module register
Address: 00006FH
Reading/writing =>
Initial value =>
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
MI
(W)
(1)
<= Bit number
ROMM
■ Block Diagram of the ROM mirror function selection module
Figure 24.1-2 "Block diagram of the ROM mirror function selection module" shows the block
diagram of the ROM mirror function selection module.
Figure 24.1-2 Block diagram of the ROM mirror function selection module
Internal data bus
ROM Mirror Function Selection Register
Address area
00 bank
FF bank
ROM
544
24.2 ROM Mirror Function Selection Register (ROMM)
24.2 ROM Mirror Function Selection Register (ROMM)
Accessing the ROM Mirror Function Selection Register (ROMM) is not allowed while
address 004000H to 00FFFFH are accessed.
■ ROM Mirror Function Selection Register (ROMM)
Figure 24.2-1 "Bit configuration of the ROM mirror function selection register (ROMM)" shows
the bit configuration of the ROM mirror function selection register (ROMM).
Figure 24.2-1 Bit configuration of the ROM mirror function selection register (ROMM)
Address: 00006FH
Reading/writing =>
Initial value =>
15
14
13
12
11
10
9
8
-
-
-
-
-
-
-
MI
(W)
(1)
<= Bit number
ROMM
[bit 8] MI
When this bit is "1", ROM data in the FF bank can be read from the 00 bank. When this bit is
"0", this function cannot be used. This bit is a write-only bit.
Note:
At the start of the ROM mirror function, addresses FF4000H to FFFFFFH are mirrored at the
addresses 004000H to 00FFFFH in Bank 00. ROM addresses of FF3FFFH or below are not
mirrored in Bank 00 even if the ROM mirror function is specified.
■ Memory space configuration
Figure 24.2-2 "Memory space configuration" shows the configuration of the memory space.
Figure 24.2-2 Memory space configuration
ROM area
ROM area
ROM area
RAM area
RAM area
I/O area
I/O area
Internal area
545
CHAPTER 24 ROM MIRROR FUNCTION SELECTION MODULE
546
CHAPTER 25
1M BIT FLASH MEMORY
This chapter describe functions and operation of the 1M bit flash memory.
There are three types of operations for writing/erasing flash memory data:
• Parallel programmer operations
• Serial-only programmer operation
• Writing/erasing by program execution
This chapter describes how to perform writing/erasing by program execution.
25.1 "Outline of 1M Bit Flash Memory"
25.2 "Block Diagram and Sector Configuration of Entire Flash Memory"
25.3 "Write/Erase Modes"
25.4 "Flash Memory Control Status Register (FMCS)"
25.5 "Starting the Flash Memory Automatic Algorithm"
25.6 "Verifying the Automatic Algorithm Execution State"
25.7 "Detailed Description of Writing/Erasing Flash Memory Data"
25.8 "Notes on Using the Flash Memory"
25.9 "Sample Program for the 1M Bit Flash Memory"
547
CHAPTER 25 1M BIT FLASH MEMORY
25.1 Outline of 1M Bit Flash Memory
The 1M bit flash memory is allocated within the FE-FF bank on the CPU memory map.
As with the mask ROM, read access from the CPU and program access can be
performed via the functions of the flash memory interface circuit. Writing/erasing flash
memory data can be performed via the flash memory interface circuit using
instructions executed by the CPU. Therefore, rewriting data may be performed under
control of the built-in CPU in implementation mode, which improves the usage
efficiency of programs and data.
Selector operations such as enable sector protect cannot be used.
■ Features of 1M bit flash memory
•
128K words x 8 bits or 64K words x 16 bits (16 KB + 8 KB + 8 KB + 32 KB + 64 KB) sector
configuration
•
Automatic program algorithm (same as Embedded AlgorithmTM: MBM29F400TA)
•
Erasure suspend/erasure resume function is installed
•
Write/erase complete detection by data polling and toggle bit
•
Detection of write/erase completion by CPU interrupt
•
Write/erase count (minimum): 10,000
•
Compatible with JEDEC standard type commands
•
Erase available per sector (in any combination of sectors)
•
Sector protect function
•
Temporary sector protect clear function
•
Automatic sleep mode function
•
Installation of flash memory interface circuit enables writing/erasing the contents of flash
memory from external pins (when using the programmer) or from the internal bus (when
using the CPU).
Embedded AlgorithmTM is a trademark of Advanced Micro Devices, Inc.
■ Procedure of Flash Memory Write/Erase
In Flash memory, write/erase and read cannot be performed at the same time. In other words,
flash memory data write/erase operations must be performed by copying the program in flash
memory first into RAM and executing it, which only allows writing without program access from
the flash memory.
548
25.1 Outline of 1M Bit Flash Memory
■ Register of the Flash Memory
Figure 25.1-1 "Bit configuration of the flash control register (FMCS)" shows the bit configuration
of the flash control register (FMCS).
Figure 25.1-1 Bit configuration of the flash control register (FMCS)
Address: 0000AEH
Reading/writing =>
Initial value =>
7
INTE
6
RDYINT
(R/W)
(0)
(R/W)
(0)
5
WE
(R/W)
(0)
4
RDY
(R)
(1)
3
Reserve
2
LPM1
1
Reserve
(W)
(0)
(W)
(0)
(W)
(0)
0
<= Bit number
LPM0
(R/W)
(0)
549
CHAPTER 25 1M BIT FLASH MEMORY
25.2 Overall Block Diagram of the Flash Memory and Its Sector
Configuration
This section provides an overall block diagram of the flash memory and its interface
circuit, and explains the sector configuration of the flash memory.
■ Overall Block Diagram of the Flash Memory
Figure 25.2-1 "Overall block diagram of the flash memory" shows the overall block diagram of
the flash memory.
Figure 25.2-1 Overall block diagram of the flash memory
Flash memory
interface circuit
Port 0
Port 3
Port 4
---------------
BYTE
--------
COM2 to COM3
SEG0 to SEG11
CE
-------
---------------
BYTE
--------
CE
-------
OE
OE
---------
---------
WE
F2MC-16LX
bus
1M bit flash memory
WE
AQ0 to AQ18
AQ0 to AQ17
AQ-1
DQ0 to AQ15
DQ0 to DQ15
INT
--------
RY/ BY
--------
RY/ BY
RESET
Write enable interrupt
signal (to CPU)
External reset signal
550
-------
RY/BY write
enable signal
25.2 Overall Block Diagram of the Flash Memory and Its Sector Configuration
■ Sector Configuration of 1M Bit Flash Memory
Figure 25.2-2 "Configuration of 1M bit flash memory sector" shows the sector configuration of
the 1M bit flash memory. The addresses in the diagram indicate the upper address and lower
address in each sector.
For an access from the CPU, the SA0 is allocated in the FE bank register, and SA1 to SA6 are
allocated in the FF bank register.
Figure 25.2-2 Configuration of 1M bit flash memory sector
Flash memory
CPU address
Programmer address
FFFFFFH
7FFFFH
FFC000H
7C000H
FFBFFFH
7BFFFH
FFA000H
7A000H
FF9FFFH
79FFFH
FF8000H
78000H
FF7FFFH
77FFFH
FF0000H
70000H
FEFFFFH
6FFFFH
FE0000H
60000H
SA4 (16 KB)
SA3 ( 8K KB)
SA2 ( 8K KB)
SA1 (32K KB)
SA0 (64K KB)
*: Write address refers to the address corresponding to the
CPU address when writing data to the flash memory using
the parallel programmer. Write/erase operations with a
general-purpose programmer must use this address.
551
CHAPTER 25 1M BIT FLASH MEMORY
25.3 Write/Erase Mode
The flash memory can be accessed in flash memory mode and two other ways. In flash
memory mode, direct write/erase operations from an external pin are allowed. In the
other modes, writing/erasing from the CPU can be performed via the internal bus. The
mode is selected via the external mode pin.
■ Flash Memory Mode
If, when a reset signal is generated, the mode pins are set to "111", the CPU will stop. As the
flash memory interface circuit is connected with the direct ports 0, 2, 3, and 4, direct control can
be performed via an external pin. In this mode, the MCU performs the same operation as for the
standard flash memory connected to an external pin, in other words, write/erase can be
performed using the flash memory programmer.
In flash memory mode, all operations supported by the flash memory automatic algorithm are
available.
■ Other Modes
Flash memory is allocated in the FE and FF banks of the CPU memory space. Read accesses
from the CPU and program access via the flash memory interface circuit are available in the
same way as for an ordinary mask ROM.
Flash memory data can be written or erased through instructions from the CPU via the flash
memory interface circuit. Therefore, data can be rewritten in this mode even if MCU is
connected to the board by soldering.
In these modes, sector protect operations cannot be executed.
552
25.3 Write/Erase Mode
■ Control Signals for the Flash Memory
Table 25.3-1 "Flash control signals" shows the flash memory control signals in flash memory
mode.
Flash memory control signals and the external pins of the MBM29F400TA have almost a oneto-one correspondence to one another. The VID (12V) pins required for the sector protect
operation are MD0, MD1, and MD2 in place of A9, RESET and OE in the MBM29F400TA.
As the memory capacity of MB90F428G/MB90F423G is a fourth that of MBM29F400TA, the
AQ18 and AQ17 pins corresponding to address signals A17 and A16 in MBM29F400TA are
redundant. These are therefore always set to "1".
In flash memory mode, the external data bus width is limited to eight bits and only permit
accesses of one byte. DQ15 to DQ8 are not supported. The BYTE pin is always "0".
Table 25.3-1 Flash control signals
MB90F428G/MB90F423G
Normal function
In flash memory
mode
MBM29F400TA
Pin number
1 to 8
COM2, COM3,
SEG0 to SEG5
AQ0 to AQ7
A-1, A0 to A6
9
SEG6
AQ16
A15
10
SEG7
CE
CE
12
SEG8
OE
OE
13
SEG9
WE
WE
14 to 15
SEG10 to SEG11
AQ17 to AQ18
A16 to A17
16
P36
BYTE
BYTE
17
P37
RY/BY
RY/BY
18 to 22
P40 to P44
AQ8 to AQ12
A7 to A11
24 to 26
P45 to P47
AQ13 to AQ15
A12 to A14
49
MD0
MD0
A9 (VID)
50
MD1
MD1
RESET (VID)
51
MD2
MD2
OE (VID)
85 to 92
P00 to P07
DQ0 to DQ7
DQ0 to DQ7
77
RST
RESET
RESET
Unsupported
DQ8 to DQ15
553
CHAPTER 25 1M BIT FLASH MEMORY
25.4 Flash Memory Control Status Register (FMCS)
The control status register (FMCS) is located in the flash memory interface circuit and
is used to write/erase the contents of flash memory.
■ Control Status Register (FMCS)
Figure 25.4-1 "Bit configuration of the control status register (FMCS)" shows the bit
configuration of the control status register (FMCS).
Figure 25.4-1 Bit configuration of the control status register (FMCS)
Address: 0000AEH
Reading/writing =>
Initial value =>
7
6
5
4
3
2
1
0
INTE
RDYINT
WE
RDY
Reserve
LPM1
Reserve
LPM0
(R/W)
(0)
(R/W)
(0)
(W)
(0)
(W)
(0)
(W)
(0)
(R/W)
(0)
(R)
(1)
<= Bit number
(R/W)
(0)
[bit 7] INTE (INTerrupt Enable)
This bit is used to generate an interrupt at the end of a flash memory write/erase operation.
If the INTE bit is set to "1" and the RDYINT bit is "1", a CPU interrupt is generated. If the
INTE bit is set to "0", no interrupt is generated.
- 0: Interrupts at the end of write/erase prohibited
- 1: Interrupts at the end of write/erase allowed
[bit 6] RDYINT (ReaDY INTerrupt)
This bit is used to indicate the state of flash memory operation.
This bit becomes "1" when the flash memory ends a write/erase operation. At the time this bit
is "0" after a flash memory write/erase operation has ended, no new flash memory write/
erase operation is allowed. The next flash memory write/erase operation can be performed
only after this bit is set to "1".
Writing "0" clears this bit, but writing "1" is ignored. When the flash memory automatic
algorithm (refer to Section 25.5 "Starting the Flash Memory Automatic Algorithm") is
completed, this bit is set to "1". Read-modify-write (RMW) instructions always return "1".
- 0: Write/erase operation being executed
- 1: Write/erase operation end (interrupt request generation)
[bit 5] WE (Write Enable)
A write enable bit for the flash memory area.
If this bit is "1", attempts to write after a command sequence to banks FE to FF has been
issued (refer to Section 25.5 "Starting the Flash Memory Automatic Algorithm") are executed
in the flash memory area. If this bit is "0", no write/erase signals are generated. Set this bit
for executing a flash memory write/erase command.
We recommend to keep this bit always "0" when no write/erase operation is to be executed,
so as to avoid accidentally writing data to the flash memory.
- 0: Flash memory write/erase prohibited
- 1: Flash memory write/erase allowed
554
25.4 Flash Memory Control Status Register (FMCS)
[bit 4] RDY (ReadDY)
This bit is used to enable flash memory write/erase operations.
If this bit is "0", no flash memory write/erase operations are not allowed. However, read/reset
commands and suspend commands, such as sector erasure suspend, are accepted in this
state.
- 0: Write/erase operation being executed
- 1: Write/erase operation end (enable next data write/erase operation)
[bit 3, 1] Reserved bit
This bit is reserved for testing. Set this bit to "0" for normal use.
[bit 2, 0] LPM1, LPM0 (Low-Power Mode)
This bit is used to control the current consumption during flash memory accesses. Because
the access time from the CPU to the flash memory depends on the setting, select the setting
value based on the CPU’s operation frequency.
01: Low-power consumption mode (operated at internal operation frequency of 4 MHz or
less)
10: Low-power consumption (operated at internal operation frequency of 8 MHz or less)
11: Low-power consumption (operated at internal operation frequency of 10 MHz or less)
00: Normal power consumption mode (operated at internal operation frequency of 16 MHz or
less)
Note:
RDYINT bit and RDY bit cannot change at the same a time. Write the program in such a way
that either bit is used for detection.
■ Timing of Automatic Algorithm End
Figure 25.4-2 "Relationship between the timing for automatic algorithm end, RDYINT bit and
RDY bit" shows the relationship between the timing for automatic algorithm end, the RDYINT
bit, and the RDY bit.
Figure 25.4-2 Relationship between the timing for automatic algorithm end, RDYINT bit and RDY bit
Timing of automatic
algorithm end
RDYINT bit
RDY bit
One machine cycle
555
CHAPTER 25 1M BIT FLASH MEMORY
25.5 Starting the Flash Memory Automatic Algorithm
There are four commands to start the automatic algorithm for flash memory: read/
reset, write, and chip erase. For sector erasure, control of suspension and resuming
the operation is available.
■ Command Sequence Table
Table 25.5-1 "Command sequence table" shows a list of the commands used for flash memory
write/erase operations. Although data is written to the command register in units of bytes, use a
unit of words in write accesses. In this case, the data in the upper byte will be ignored.
Table 25.5-1 Command sequence table
Command
sequence
Bus
write
access
1st bus write
cycle
2nd bus write
cycle
3rd bus write
cycle
4th bus write cycle
5th bus write
cycle
6th bus write
cycle
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Address
Data
Read/reset
(*1)
1
FxXXXX
XXF0
-
-
-
-
-
-
-
-
-
-
Read/reset
(*1)
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXF0
RA
RD
-
-
-
-
Write
program
4
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XXA0
RA
(even)
RD
(word)
-
-
-
-
Chip erase
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX10
Sector
erasure
6
FxAAAA
XXAA
Fx5554
XX55
FxAAAA
XX80
FxAAAA
XXAA
Fx5554
XX55
SA
(even)
XX30
Sector erasure
Sector erasure resume
By inputting address "FxXXXX" data (xxB0H), sector erasure is temporarily suspended.
By inputting address "FxXXXX" data (xx30H), temporarily suspended sector erasure is resumed.
Note:
• The address Fx in the table stands for FF or FE. Use the relevant bank to be accessed in each operation.
• The address in the table represents a value on the CPU memory map. Address and data are represented in
hexadecimal format. "X" means an arbitrary value.
• RA: read address
• PA: write address must be an even address only.
• SA: sector address; refer to "Sector Configuration in 1M Bit Flash Memory" within Section 25.2 "Block
Diagram and Sector Configuration of Entire Flash Memory".
• RD: Read data
• PD: Write data: only word data can be specified
*1: Both types of read/reset commands can be used to reset the flash memory to read mode.
556
25.6 Confirming the Execution State of the Automatic Algorithm
25.6 Confirming the Execution State of the Automatic Algorithm
The flash memory contains hardware to report the operation state and operation end
in the operational flow for writing/erasing with the automatic algorithm. The automatic
algorithm uses the hardware sequence shown below to confirm the built-in flash
memory’s operation state.
■ Hardware Sequence Flags
The hardware sequence flags consists of a four-bit output, DQ7, DQ6, DQ5, and DQ3. They
have the following functions: Data polling flag (DQ7), toggle bit flag (DQ6), timing limit excess
flag (DQ5), and sector erasure timer flag (DQ3). Use of these flags allows to confirm whether
write/chip sector erasure has ended and erase code writing is enabled.
To reference the hardware sequence flag, read the sector address in the internal flash memory
after setting the command sequence (refer to Table 25.5-1 "Command sequence table"). Table
25.6-1 "Bit configuration of hardware sequence flags" shows the bit configuration of the
hardware sequence flags.
Table 25.6-1 Bit configuration of hardware sequence flags
Bit No.
7
6
5
4
3
2
1
0
Hardware sequence flag
DQ7
DQ6
DQ5
-
DQ3
-
-
-
Whether an automatic write/chip sector erasure operation is being executed or not can be
identified by checking the hardware sequence flags or the RDY bit in the flash memory control
register (FMCS). (The RDY bit in the flash memory control register indicates whether the write
operation has ended: If a write/erase operation has ended, it returns to the read/reset state.)
When creating a program, use either of these flags to determine whether the next processing
step can be performed (such as for confirming that an automatic write/erase operation has
ended before reading data). The hardware sequence flags can also be used to confirm whether
writing the second and subsequent sector erasure codes is effective. The hardware sequence
flags are described below. Table 25.6-2 "List of hardware sequence flag functions" shows the
functions of the hardware sequence flags.
557
CHAPTER 25 1M BIT FLASH MEMORY
Table 25.6-2 List of hardware sequence flag functions
State
Write operation --> Write complete
(Write address specified)
State change
during normal
operation
Error operation
558
DQ7
DQ7 -->
DATA:7
Chip sector erasure operation -->
Erase complete
0 --> 1
Sector erasure wait --> Erase start
0
Erase operation --> Sector
erasure suspend
(Sector being erased)
DQ6
Toggle -->
DATA:6
Toggle -->
Stop
DQ5
DQ3
0 -->
DATA:5
0 -->
DATA:3
0 --> 1
1
Toggle
0
0 --> 1
0 --> 1
Toggle --> 1
0
1 --> 0
Sector erasure suspended -->
Erasure resumed
(Sector being erased)
1 --> 0
1 --> Toggle
0
0 --> 1
Sector erasure suspended
(Sector not being erased)
DATA:7
DATA:6
DATA:5
DATA:3
DQ7
Toggle
1
0
0
Toggle
1
1
Write operation
Chip sector erasure operation
25.6 Confirming the Execution State of the Automatic Algorithm
25.6.1 Data Polling Flag (DQ7)
The data polling flag (DQ7) is used to indicate via the data polling function whether an
automatic algorithm is being executed or has completed.
■ Data Polling Flag (DQ7)
Table 25.6-3 "State transitions of data polling flag (state transitions in normal operation)" and
Table 25.6-4 "State transitions of data polling flag (state transitions during operation error)"
show the state transitions of the data polling flag.
Table 25.6-3 State transitions of data polling flag (state transitions in normal operation)
Write
operation -->
Complete
Operation
state
DQ7 -->
DATA:7
DQ7
Chip sector
erasure -->
Complete
0 --> 1
Sector
erasure
wait -->
Start
0
Sector erasure
--> Erasure
suspended
(Sector being
erased)
0 --> 1
Sector erasure
suspended -->
Erasure
resumed
(Sector being
erased)
1 --> 0
Sector
erasure
suspended
(Sector not
being
erased)
DATA:7
Table 25.6-4 State transitions of data polling flag (state transitions during operation error)
Operation
state
Write
operation
Chip sector
erasure
operation
DQ7
DQ7
0
❍ During write operations
If read access is performed when the automatic write algorithm is being executed, the flash
memory outputs the inverse of bit 7 from the last data item written irrespective of the address
specified. If read access is performed after the automatic write algorithm has completed, the
flash memory outputs bit 7 of the read value at the specified address.
❍ During chip/sector erasure
Flash memory returns "0" in read operations during execution of the chip erase/sector erasure
algorithm, either for the currently erased sector, or irrespective of the address specified for chip
erasure. Similarly, it returns "1" at the end of the algorithm.
559
CHAPTER 25 1M BIT FLASH MEMORY
❍ During sector erasure suspension
If read access is performed during sector erasure suspension, the flash memory returns "1" in
read operations if the specified address refers to a erased sector or bit 7 (DATA: 7) of the value
at the address specified. Referencing this bit along with the toggle bit flag (DQ6) enables to
identify whether the operation for the sector is currently suspended and which sector is currently
being erased.
Note:
When the automatic algorithm starts, read accesses to the specified address are ignored. As
soon as data polling flag (DQ7) indicates the end of data polling, other bits can be read out.
Therefore, for reading data after the end of the automatic algorithm, wait for confirmation on
the end of data polling.
560
25.6 Confirming the Execution State of the Automatic Algorithm
25.6.2 Toggle Bit Flag (DQ6)
Similarly to the data polling flag (DQ7), the toggle bit flag (DQ6) is a flag used to notify
via a toggle bit function whether execution of the automatic algorithm is in progress or
has completed.
■ Toggle Bit Flag (DQ6)
Table 25.6-5 "State transitions of toggle bit flag (state transitions in normal operation)" and
Table 25.6-6 "State transitions of the toggle bit flag (state transitions during operation error)"
show the state transitions of the toggle bit flag.
Table 25.6-5 State transitions of toggle bit flag (state transitions in normal operation)
Operation
state
DQ6
Write
operation -->
Complete
Chip sector
erasure -->
Complete
Toggle -->
DATA:6
Toggle -->
Stop
Sector
erasure
wait -->
Start
Toggle
Sector erasure
--> Erasure
suspended
(Sector being
erased)
Toggle --> 1
Sector erasure
suspended -->
Erasure
resumed
(Sector being
erased)
Sector
erasure
suspended
(Sector not
being
erased)
1 --> Toggle
DATA:6
Table 25.6-6 State transitions of the toggle bit flag (state transitions during operation error)
Operation
state
Write
operation
Chip sector
erasure
operation
DQ6
Toggle
Toggle
❍ Operation during write/chip sector erasure
In repeated read accesses during operation of the automatic write algorithm or chip sector
erasure algorithm, "1" and "0" are output alternately irrespective of the specified flash memory
address. In repeated read accesses after the automatic write algorithm or chip/sector erasure
algorithm has ended, the flash memory stops toggling bit 6 and outputs bit 6 (DATA: 6) of the
read value at the address specified.
561
CHAPTER 25 1M BIT FLASH MEMORY
❍ Operation during sector erasure suspension
For read accesses during sector erasure suspension, the flash memory outputs "1" if the
address specified indicates a erased sector or bit 6 (DATA:6) of the read value at the address
specified.
Reference:
If, in a write operation, the sector to be written is protected against overwriting, the toggle
operation ends after only about 2 µs of toggle operation without overwriting.
If, during erasure, all sectors selected are protected against overwriting, the toggle bit is
toggled for about 100 µs and the operations returns to read/reset mode without overwriting
data.
562
25.6 Confirming the Execution State of the Automatic Algorithm
25.6.3 Timing Limit Excess Flag (DQ5)
The timing limit excess flag (DQ5) is used to indicate that the automatic algorithm
execution exceeds the time (internal pulse count) internally specified by the flash
memory.
■ Timing Limit Excess Flag (DQ5)
Table 25.6-7 "State transition of timing limit excess flag (during normal operation)" and Table
25.6-8 "State transitions of timing limit excess flag (during operation error)" show the state
transitions of the timing limit excess flag.
Table 25.6-7 State transition of timing limit excess flag (during normal operation)
Operation
state
Write
operation -->
Complete
DQ5
0 --> DATA:5
Chip sector
erasure -->
Complete
0 --> 1
Sector
erasure
wait -->
Start
Sector erasure
--> Erasure
suspended
(Sector being
erased)
0
0
Sector erasure
suspended -->
Erasure
resumed
(Sector being
erased)
0
Sector
erasure
suspended
(Sector not
being
erased)
DATA:5
Table 25.6-8 State transitions of timing limit excess flag (during operation error)
Operation
state
Write
operation
Chip sector
erasure
operation
DQ5
1
1
❍ Operation during write/chip sector erasure
During read accesses after a write operation, or when the chip sector erasure automatic
algorithm is working, the flash memory outputs "0" if the specified time (time required for write/
erase) has not passed or "1" if it has passed. This happens irrespective of whether the
automatic algorithm is in progress or has ended, and allows to identify whether the write/erase
has been succeeded or failed: If "1" is returned with a data polling function or toggle bit function
for this flag at a time when the automatic algorithm is still in progress, this indicates that the
write operation has failed.
For example, when there is an attempt to write "1" to a location in flash memory for which "0"
was already written, a failure occurs. In this case, the flash memory becomes locked and the
automatic algorithm will not end. Therefore, the data polling flag (DQ7) will not have a valid
output. The toggle bit flag (DQ6) will not interrupt the toggle operation after the time limit has
expired, and the timing limit excess flag (DQ5) will at that time return "1". This indicates not a
failure of flash memory, bit that the flash memory is incorrectly used. In case of such event,
execute the reset command.
563
CHAPTER 25 1M BIT FLASH MEMORY
25.6.4 Sector Erasure Timer Flag (DQ3)
The sector erasure timer flag is used to notify whether the flash memory is in sector
erasure wait state after the sector erasure command has started.
■ Sector erasure Timer Flag (DQ3)
Table 25.6-9 "State transitions of sector erasure timer flag (during normal operation)" and Table
25.6-10 "State transition of sector erasure timer flag (during operation error)" show the state
transitions of sector erasure timer flag.
Table 25.6-9 State transitions of sector erasure timer flag (during normal operation)
Operation
state
Write
operation -->
Complete
DQ3
0 --> DATA:3
Chip sector
erasure -->
Complete
1
Sector
erasure
wait -->
Start
0 --> 1
Sector erasure
--> Erasure
suspended
(Sector being
erased)
1 --> 0
Sector erasure
suspended -->
Erasure
resumed
(Sector being
erased)
0 --> 1
Sector
erasure
suspended
(Sector not
being
erased)
DATA:3
Table 25.6-10 State transition of sector erasure timer flag (during operation error)
Operation
state
Write
operation
Chip sector
erasure
operation
DQ3
0
1
❍ Operation during sector erasure
In read accesses after the sector erasure command starts, the flash memory returns case "0" if
the sector erasure wait time has not passed or "1" if it has passed, irrespective of the address
specified for the sector in the command.
If this flag is "1" while the data polling function or toggle bit function indicates that the erasure
algorithm is in progress, the internally controlled erasure operation has started. Subsequent
write commands with sector erasure code or commands other than erasure suspend are
ignored until the erasure ends.
If this flag is "0", the flash memory accepts writing of subsequent sector erasure codes. To
confirm this, it is recommended to check the state of this flag before subsequent writing of
sector erasure codes. If the second state check returns "1", the additional sector erase code
might not be accepted.
❍ Operation during sector erasure suspension
During read accesses in sector erasure suspension, the flash memory outputs "1" if the address
specified refers to a erased sector or bit 3 (DATA: 3) of the read value at the address specified.
564
25.7 Detailed Description of Writing/Erasing Flash Memory Data
25.7 Detailed Description of Writing/Erasing Flash Memory Data
This section describes the detailed procedures for issuing a command to start the
automatic algorithm and perform such operations as flash memory read /reset, write,
chip erase, sector erasure, sector erasure suspend, and sector erasure resume.
■ Detailed Explanation of Flash Memory Write/Erase
Such operations as read/reset, write, chip erase, sector erasure, sector erasure suspend, and
sector erasure resume can be performed by the automatic algorithm by inserting the
corresponding instructions to the command sequence bus (see Table 25.5-1 "Command
sequence table") at a write cycle. The write cycles for each bus must be performed
consecutively. The automatic algorithm can detect the end of the respective operation via the
data polling function. After normal end, operation returns to the read/reset state.
The related operations are described below in the following order.
•
Setting the read/reset state
•
Writing data
•
Erasing all data (all chip erase)
•
Erasing any data (sector erasure)
•
Suspending sector erasure
•
Resuming sector erasure
565
CHAPTER 25 1M BIT FLASH MEMORY
25.7.1 Setting the Flash Memory to Read/Reset State
This section describes the procedures to issue read/reset commands and set the flash
memory to read/reset state.
■ Setting the Flash Memory to Read/Reset State
To put the flash memory into the read/reset state, issue the read/reset commands from the
command sequence table (see Table 25.5-1 "Command sequence table") to the relevant sector
in the flash memory to have them executed.
There are two types of command sequences for read/reset commands, performing one or three
bus operations.
The read/reset state is the initial state of the flash memory. The flash memory always stays in
this state after the commands at power-on have been completed normally. During read/reset
state, the device waits for other commands.
In read/reset state, data can be read out in normal read accesses. Program access from the
CPU can be performed in the same way as for mask ROM. This command is not required to
read data in a normal read operation. This command is mainly needed for initializing the
automatic algorithm in case a command did not end normally.
566
25.7 Detailed Description of Writing/Erasing Flash Memory Data
25.7.2 Writing Data to the Flash Memory
This section describes the procedures to issue a write command for writing data to
flash memory.
■ Writing Data to the Flash Memory
To start the automatic algorithm for writing data to flash memory, issue a write command form
the command sequence table (see Table 25.5-1 "Command sequence table") to the relevant
sector in the flash memory to have it executed. The automatic algorithm will start at the fourth
cycle after the data write operation to the intended address has ended, starting with automatic
writing.
❍ Address specification
Only even addresses can be specified as write address in the write data cycle. If an odd
address is specified, the write operation will not be performed correctly. Writing must be
performed to even addresses in word units.
Any address sequence is allowed for writing, and the sector boundaries can be exceeded, but in
a single write operation, only one word of data can be written.
❍ Notes on writing data
Write operations cannot change a data item "0" to a data item "1". When overwriting data item
"0" by data item "1", neither the data polling algorithm (whose state is indicated by DQ7) or
toggle operation (whose state is indicated by DQ6) will end and a failure will be indicated for the
respective flash memory element. As a result, the timing limit excess flag (DQ5) will indicate an
error because the specified write time is exceed, or it will merely appear as if data item "1" had
been written. However, subsequent read operations in the read/reset state will still return data
item "0". Only after a erase operation can a data item "0" be changed to data item "1".
During automatic writing, all commands are ignored. Note that if a hardware reset occurs during
writing, the correctness of data at the respective address is not assured.
■ Writing to Flash Memory
Figure 25.7-1 "Example of flash memory write procedure" shows a sample procedure for writing
to flash memory. The operational state of the automatic algorithm in flash memory can be
identified by the hardware sequence flag (refer to Section 25.6 "Confirming the Execution State
of the Automatic Algorithm"). For this case, the end of writing can be confirmed via the data
polling flag (DQ7).
Data for the flag check is read out starting from the address where the last write operation
occurred.
Recheck the data polling flag (DQ7) since it will change at the same time the timing limit excess
flag (DQ5). Even if the timing limit excess flag (DQ5) is set to "1", check again the data polling
flag bit (DQ7).
Check again the toggle bit flag (DQ6), since the toggle operation stops also when the timing
limit excess flag bit (DQ5) changes to "1".
567
CHAPTER 25 1M BIT FLASH MEMORY
Figure 25.7-1 Example of flash memory write procedure
Start of writing
FMCS:WE(bit5)
Allow flash memory write
Write command sequence
(1)FxAAAA
XXAA
XX55
(2)Fx5554
(3)FxAAAA
XXA0
(4) Write address
write data
Internal address read
Data polling (DQ7)
Next address
Data
Data
0
Timing limit (DQ5)
1
Internal address read
Data
Data polling (DQ7)
Data
Write error
Last address
FMCS:WE(bit5)
Prohibit Flash memory write
Write end
568
Confirmation by hardware
sequence flag
25.7 Detailed Description of Writing/Erasing Flash Memory Data
25.7.3 Erasing All Data in the Flash Memory (Chip Erase)
This section describes procedures to issue the chip erase command for erasing all
data from the flash memory.
■ Erasing Data From the Flash Memory (Chip Erase)
To erase all data from the flash memory, issue the chip erase command from the command
sequence table (see Table 25.5-1 "Command sequence table") to the appropriate sector in the
flash memory to have it executed.
The chip erase command is executed in six bus operations. When the 6th cycle write is
completed, the chip erasure operation will start. To execute the chip erase operation, the user
does not need to write to flash memory in advance. During execution of the automatic erase
algorithm, the algorithm writes "0" to all cells in advance before erasure and verifies this.
569
CHAPTER 25 1M BIT FLASH MEMORY
25.7.4 Erasing Data From the Flash Memory (Sector erasure)
This section explains the procedures to issue the sector erasure command for erasing
data from the flash memory (sector erasure). This allows erasure separately by sector.
Moreover, multiple sectors can be specified for erasure as well.
■ Erasing Data From the Flash Memory (Sector erasure)
To erase a sector from the flash memory, issue consecutively the sector erasure commands
from the command sequence table (see Table 25.5-1 "Command sequence table") to the
appropriate sectors in the flash memory to have them executed.
❍ Sector specification
The sector erasure command is executed in six bus operations. A sector erasure wait period of
50 µs will start by writing the sector erasure code (30H) to an arbitrary accessible, even address
at the sixth cycle. For executing multiple sector erasure, write the erase code (30H) to the
address in the sector where the erasure is to be performed after the above processing.
❍ Notes on specifying multiple sectors
Erasure will start when the sector erasure wait time of 50 µs has passed after the last sector
erasure code was written. In other words, to erase multiple sectors at a time, the address and
erase code of the subsequent erase sector (6th cycle of command sequence) must be entered
within 50 µs. Any later entry may be rejected. Whether subsequent writing of the sector erasure
code is effective is checked by the sector erasure timer (with the hardware sequence flag DQ3).
The address read by the sector erasure timer must specify the sector to be erased.
■ Procedure to Erase Sectors From the Flash Memory
Using the hardware sequence flag (see Section 25.6 "Confirming the Execution State of the
Automatic Algorithm"), the status of the automatic algorithm with respect to the internal flash
memory can be identified. Figure 25.7-2 "Sample procedure for erasing a sector from flash
memory" shows a sample procedure for erasing a flash memory sector. This example uses the
toggle bit flag (DQ6) to check for the end of erasure.
Note that the data for the flag check is read from the sector to be erased.
The toggle bit flag (DQ6) will stop a toggle operation when the timing limit excess flag (DQ5)
changes to "1". Therefore, check the toggle bit flag (DQ6) again even if the timing limit excess
flag (DQ5) is set to "1".
In ordinary cases, recheck the data polling flag (DQ7), since it may change at the same time the
timing limit excess flag (DQ5).
570
25.7 Detailed Description of Writing/Erasing Flash Memory Data
Figure 25.7-2 Sample procedure for erasing a sector from flash memory
Start deletion
FMCS:WE(bit5)
Allow flash memory delete
Command sequence for deletion
(1)FxAAAA
XXAA
XX55
(2)Fx5554
XX80
(3)FxAAAA
(4)FxAAAA
XXAA
XX55
(5)Fx5554
1
Sector deletion timer
(DQ3)
Internal address read
0
(6)Enter the code (30H) to the
sector to be deleted
Y
Any other sector to
be deleted?
N
Internal address read 1
Internal address read 2
Toggle bit (DQ6)
Data 1 (DQ6) = data 2
(DQ6)
N
0
Next sector
Y
Timing limit (DQ5)
1
Internal address read 1
Internal address read 2
N
Delete error
Toggle bit (DQ6)
Data 1 (DQ6) = Data 2
(DQ6)
Y
Last sector
N
Y
FMCS:WE(bit5)
Flash memory delete prohibited
Deletion completed
Confirmation by hardware
sequence flag
571
CHAPTER 25 1M BIT FLASH MEMORY
25.7.5 Suspending Flash Memory Sector Erasure
This section describes the procedure used to issue the sector erasure suspend
command and suspend flash memory sector erasure, allowing to read the data of
sectors that are not being erased.
■ Suspending Flash Memory Sector Erasure
To suspend flash memory sector erasure, issue the sector erasure suspend command from the
command sequence table (see Table 25.5-1 "Command sequence table") to the flash memory
to have it executed.
The sector erasure suspend command will suspend sector erasure, allowing data to be read
from sectors that are not being erased. In this state, only reading is allowed, writing is
prohibited. This command is only valid during sector erasure, including the erasure wait period,
and ignored during chip erasure or during write operations.
Sector erasure can be suspended by writing the erasure suspend code (B0H), where any
address in the flash memory may be specified. Repeated erasure suspend commands are
ignored during erasure suspension.
Entering the sector erasure suspend command during the sector erasure wait period will
immediately end the sector erasure wait, interrupt the erasure operation, and put the device into
erase stop state. If the erasure suspend command is entered during the sector erasure
operation after the sector erasure wait time has passed, the flash memory enters the erasure
suspend state after 15 µs or earlier.
572
25.7 Detailed Description of Writing/Erasing Flash Memory Data
25.7.6 Restarting Flash Memory Sector Erasure
This section describes the procedure used to issue the sector erasure resume
command and resume a suspended sector erasure of flash memory.
■ Resuming the Sector Erasure of Flash Memory
To resume sector erasure, issue consecutively the sector erasure resume commands from the
command sequence table (see Table 25.5-1 "Command sequence table") to the flash memory
to have them executed.
The sector erasure resume command resumes sector erasure from suspension caused by the
sector erasure suspend command. This command is executed by writing the erase restart code
(30H), where any address in the flash memory area may be specified.
Sector erasure resume commands issued during sector erasure are ignored.
573
CHAPTER 25 1M BIT FLASH MEMORY
25.8 Notes on Using Flash Memory
This section provides notes on using the flash memory.
■ Notes on Using the Flash Memory
❍ Entering a hardware reset (RST)
To enter a hardware reset during reading when the automatic algorithm has not started, use an
L level width of at least 500 ns. In this case, it takes at least 500 ns before data is read from the
flash memory after the hardware reset is activated. To enter a hardware reset during reading/
erasing when the automatic algorithm starts, use in ordinary cases an L level width of at least 50
ns. In this case, to initialize the flash memory, wait at least 20 µs before data is read out after
the operation in progress is stopped.
When a hardware reset is performed in write mode, the stored data will become undefined.
When the hardware reset is performed in erase mode, the erased sectors may become
unavailable.
❍ Canceling software reset, watchdog timer reset, and hardware standby
The CPU may run out of control if the conditions for a reset apply during a CPU access for a
flash memory write/erase operation when the automatic algorithm is active.
This can occur because the flash memory unit will not be initialized when the reset conditions
apply. The automatic algorithm will in this case continue operation, and during the next CPU
sequence, the flash memory may not correctly enter reading status after the reset has been
canceled. For this reason, reset sources must be disabled in flash memory write/erase mode.
❍ Program access to the flash memory
During operation of the automatic algorithm, any read access to the flash memory is prohibited.
If the CPU’s memory access mode is set to built-in ROM mode, the write/erase operation must
start after the program area has been switched to another area such to RAM. If, in this case, a
sector (SA6) including interrupt vectors is erased, a failure occurs during write/erase interrupt
handling.
For the same reasons, all interrupt sources other than for flash memory interrupts are disabled
while the automatic algorithm runs.
❍ Hold function
If the CPU accepts a hold request, write signals to the flash memory unit WE maybe corrupted
and an illegal write may cause an illegal write/erase operation. If accepting a hold request is
permitted (EPCR: HDE bit set to "1"), the WE bit of the control status register (FMCS) must be
set to "0".
❍ Extended intelligent I/O service (EI2OS)
Write/erase interrupts issued from the flash memory interface circuit to the CPU cannot be
accepted by EI2OS, and can therefore not be used.
574
25.8 Notes on Using Flash Memory
❍ Using VID
Applying the VID required for the sector protect operation must be started (and subsequently
stopped) when the supply voltage is turned ON.
575
CHAPTER 25 1M BIT FLASH MEMORY
25.9 Sample Program for the 1M Bit Flash Memory
A program example for the 1M bit flash memory is listed below.
■ Sample Program for 1M Bit Flash Memory
NAME
FLASHWE
TITLE
FLASHWE
;---------------------------------------------------------------------------;1Mbit-FLASH
Sample program for 1M bit-FLASH
;
;1: Program in FLASH (address: FFBC00H, sector SA3)
;
is transferred to RAM (address: 000700H)
;2: The program is executed in RAM
;3: The value in PDR1 is written to FLASH (address: FE0000H, sector:
;
SA0)
;4: The value written (address: FE0000H, sector: SA0)is output to
;
read PDR2
;5: The written sector (SA0) is erased
;6: Condition for output of data erasure check
;
- RAM transfer byte count : 100H (256B)
;
- Judgement of end of write or erase operation
;
Judgement based on DQ5 (timing limit excess flag)
;
Judgement based on DQ6 (toggle bit flag)
;
Judgment based on RDY (FMCS)
;
- Processing in case of error
;
Reset command issued to output Hi to P00 to P07
;---------------------------------------------------------------------------;
RESOUS IOSEG
ABS=00
;Definition of "RESOUS"I/O segment
ORG
0000H
PDR0
RB
1
PDR1
RB
1
PDR2
RB
1
PDR3
RB
1
ORG
0010H
DDR0
RB
1
DDR1
RB
1
DDR2
RB
1
DDR3
RB
1
ORG
00A1H
CKSCR
RB
1
ORG
00AEH
FMCS
RB
1
ORG
006FH
ROMM
RB
1
RESOUS ENDS
;
SSTA
SSEG
RW
0127H
STA_T
RW
1
SSTA
ENDS
;
576
25.9 Sample Program for the 1M Bit Flash Memory
DATA
DSEG
ABS=0FFH
FLASH command address
ORG
5554H
COMADR2 RW
1
ORG
0AAAAH
COMADR1 RW
1
DATA
ENDS
;////////////////////////////////////////////////////////////////////////////
; Main program (FFA000H)
;////////////////////////////////////////////////////////////////////////////
CODE
CSEG
START:
;////////////////////////////////////////////////////////////////////
; Initialize
;////////////////////////////////////////////////////////////////////
MOV
CKSCR, #0BAH
;Set to multiplication-by-3
MOV
RP, #0
MOV
A, #!STA_T
MOV
SSB, A
MOVW
A, #STA_T
MOVW
SP, A
MOV
ROMM, #00H
;Mirror OFF
MOV
PDR0, #00H
;For error confirmation
MOV
DDR0, #0FFH
MOV
PDR1, #00H
;Data input port
MOV
DDR1, #00H
MOV
PDR2, #00H
;Data output port
MOV
DDR2, #0FFH
;////////////////////////////////////////////////////////////////////
;"FLASH write erasure program (FFBCOOH)" is transferred to
; RAM (to address 700H)
;////////////////////////////////////////////////////////////////////
MOVW
A, #0700H
;Transfer destination RAM area
MOVW
A, #0BC00H
;Transfer source address (location
of the program)
MOVW
RW0, #100H
;Transferred byte count
MOVS
ADB, PCB
;Transferring 100H from FFBC00H to
000700H
CALLP
000700H
;Jump to address where program
transferred is located
;////////////////////////////////////////////////////////////////////
; Data output
;////////////////////////////////////////////////////////////////////
OUT
MOV
A, #0FEH
MOV
ADB, A
MOVW
RW2, #0000H
MOVW
A, @RW2+00
MOV
PDR2, A
END
JMP
*
CODE
ENDS
577
CHAPTER 25 1M BIT FLASH MEMORY
;////////////////////////////////////////////////////////////////////////////
; FLASH write erase program (SA3)
;////////////////////////////////////////////////////////////////////////////
RAMPRG CSEG
ABS=0FFH
ORG
0BC00H
;
/////////////////////////////////////////////////////////////////////
;
Initialize
;
/////////////////////////////////////////////////////////////////////
MOVW
RW0, #0500H
;RW0: RAM area allocated for input
data 00: 0500 and later
MOVW
RW2, #0000H
;RW2: flash memory write address
FD: 0000 and later
MOV
A, #00H
;DTB changed
MOV
DTB, A
;@RW0 bank specify
MOV
A, #0FEH
;ADB change #1
MOV
ADB, A
;Specify bank for write mode
specified address
MOV
PDR3, #00H
;Switch initialization
MOV
DDR3, #00H
;
WAIT1
BBC
PDR3:0, WAIT1
;PDR3: 0 Hi for starting to
write
;
;////////////////////////////////////////////////////////////////////////////
; Write (SA0)
;////////////////////////////////////////////////////////////////////////////
MOV
A, PDR1
MOVW
@RW0+00, A
;PDR1 data stored in RAM
MOV
FMCS, #20H
;Write mode setting
MOVW
ADB:COMADR1, #00AAH
;Flash write command 1
MOVW
ADB:COMADR2, #0055H
;Flash write command 2
MOVW
ADB:COMADR1, #00A0H
;Flash write command 3
;
MOVW
A, @RW0+00
;Input data (RW0) stored in
;
flash memory (RW2)
MOVW
@RW2+00, A
WRITE
;Waiting time check
;
/////////////////////////////////////////////////////////////////////
;
Time limit excess check - ERROR if flag is set to toggle
;
operation mode
;
/////////////////////////////////////////////////////////////////////
MOVW
A, @RW2+00
AND
A, #20H
;DQ5 time limit check
BZ
NTOW
;Time limit over
MOVW
A, @RW2+00
;AH
MOVW
A, @RW2+00
;AL
XORW
A
;XOR for AH AL (1 if value
differs)
AND
A, #40H
;DQ6 toggle bit is wrong?
BNZ
ERROR
;ERROR if it differs
578
25.9 Sample Program for the 1M Bit Flash Memory
;
;
;
NTOW
;
WAIT2
/////////////////////////////////////////////////////////////////////
Check for write end (FMCS-RDY)
/////////////////////////////////////////////////////////////////////
MOVW
A, FMCS
AND
A, #10H
;Fetching FMCS RDY bits
(4-bits)
BZ
WRITE
;Write endAH
MOV
FMCS, #00H
;Write mode released
;////////////////////////////////////////////////////////////////////
; Write data output
;////////////////////////////////////////////////////////////////////
MOVW
RW2, #0000H
;Write data output
MOVW
A, @RW2+00
MOV
PDR2, A
BBC
PDR3:1, WAIT2
;Sector erasure starts by
PDR3: 1 Hi
;
;////////////////////////////////////////////////////////////////////////////
; Sector erasure (SA0)
;////////////////////////////////////////////////////////////////////////////
MOV
@RW2+00, #0000H
;Address initialize
MOV
FMCS, #20H
;erase mode set
MOVW
ADB:COMADR1, #00AAH
;Flash erase command 1
MOVW
ADB:COMADR2, #0055H
;Flash erase command 2
MOVW
ADB:COMADR1, #0080H
;Flash erase command 3
MOVW
ADB:COMADR1, #00AAH
;Flash erase command 4
MOVW
ADB:COMADR2, #0055H
;Flash erase command 5
MOV
@RW2+00, #0030H
;erase command 6 issued to
sector to be erased
ELS
; Waiting time check
;
/////////////////////////////////////////////////////////////////////
;
Time limit excess check - ERROR if flag is set to toggle
;
operation mode
;
/////////////////////////////////////////////////////////////////////
MOVW
A, @RW2+00
AND
A, #20H
;DQ5 time limit check
BZ
NTOE
;Time limit over
MOVW
A, @RW2+00
;AH
In write operation,
from DQ6
MOVW
A, @RW2+00
;AL
Hi/ Low is alternately
output at every write
operation
XORW
A
;ASOR for AH and AL(1 if DQ6
value is wrong during
;
write operation)
AND
A, #40H
;DQ6 toggle bit is Hi ?
BNZ
ERROR
;ERROR if Hi
;
/////////////////////////////////////////////////////////////////////
;
erase end check (FMCS-RDY)
;
/////////////////////////////////////////////////////////////////////
NTOE
MOVW
A, FMCS
;
AND
A, #10H
;FMCS RDY bit (4 bits)
extracted
BZ
ELS
;End sector erasureAH
MOV
FMCS, #00H
;FLASH erase mode released
RETP
;Return to main program
579
CHAPTER 25 1M BIT FLASH MEMORY
;////////////////////////////////////////////////////////////////////////////
; Error
;////////////////////////////////////////////////////////////////////////////
ERROR
MOV
FMCS, #00H
;FLASH mode released
MOV
PDR0, #0FFH
;Error processing confirmed
MOV
ADB:COMADR1, #0F0H
;Reset command (allowing
reading)
RETP
;Return to main program
RAMPRG ENDS
;////////////////////////////////////////////////////////////////////////////
VECT
CSEG
ABS=0FFH
ORG
0FFDCH
DSL
START
DB
00H
VECT
ENDS
;
END
START
580
CHAPTER 26
EXAMPLE OF SERIAL PROGRAMMING
CONNECTION
This chapter shows an example of a serial programming connection using the AF220/
AF210/AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital
Computer Corporation.
26.1 "Basic Configuration"
26.2 "Oscillator Clock Frequency and Serial Clock Input Frequency"
26.3 "Flash Micro-Computer Programmer and System Configuration"
26.4 "Example of Serial Programming Connection"
581
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
26.1 Basic Configuration
The MB90F428G/MB90F423G supports serial onboard writing (Fujitsu standard) of the
flash ROM. This section provides the related specifications.
■ Basic Configuration
Figure 26.1-1 "Basic configuration of example serial programming connection" shows the basic
configuration for the example serial programming connection.
Fujitsu standard serial onboard writing uses the Yokogawa Digital Computer Corporation flash
microcomputer programmer.
Figure 26.1-1 Basic configuration of example serial programming connection
Host interface cable (AZ221)
General-purpose common cable (AZ210)
RS232C
Flash
microcomputer
programmer
and
memory card
CLK synchronous
serial
MB90F428G
/MB90F423G
User system
Operable in stand-alone mode
For information on the functions of and operational procedures related to the flash
microcomputer programmer (AF220/AF210/AF120/AF110), the general-purpose common cable
(AZ210) for connection, and the connector, contact Yokogawa Digital Computer Corporation.
582
26.1 Basic Configuration
■ Pins Used for Fujitsu Standard Serial Onboard Writing
Table 26.1-1 "Function of pins" shows the functions of the related pins.
Table 26.1-1 Function of pins
Pin
Function
Description
Mode pin
Setting MD2=1, MD1=1, and MD0=0 to enter the serial
programming mode.
X0, X1
Oscillation pin
As, in the serial programming mode, CPU internal operation
clock is the PLL clock multiplied by 1, the internal operation
clock frequency is equal to the oscillator clock frequency.
Consequently, the frequencies that can be input to the highspeed oscillation input pin for serial writing are from 1 to 16
MHz.
P00, P01
Programming program
start pin
Set P00 to an input of "L" level and P01 to an input of "H" level.
RST
Reset pin
SIN1
Serial data input pin
SOT1
Serial data output pin
SCK1
Serial clock input pin
VCC
Power voltage supply pin
If the programming voltage (VCC=5.0V 10%) is supplied from
the user system, connection with the flash microcomputer
programmer is not required.
VSS
GND pin
Must be shared with GND of the flash microcomputer
programmer.
MD2, MD1,
MD0
-
Use UART1 for CLK sync mode.
Figure 26.1-2 Pin control circuit
AF220/AF210/AF120/AF110
Write control pin
MB90F428G/MB90F423G
Write control pin
10K
AF220/AF210/AF120/AF110
/TICS pin
User
Notes:
To use the P00, SIN1, SOT1, and SCK1 pins within the user system as well, the control
circuit shown in the Figure 26.1-2 "Pin control circuit" is required.
Using the flash microcomputer programmer’s/TICS signal, the user circuit can be
disconnected in serial programming mode. Refer to the connection example.
583
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
26.2 Oscillator Clock Frequency and Serial Clock Input
Frequency
The serial clock frequency of the MB90F428G/MB90F423G that can be input can be
derived by the formula shown below. Based on the oscillator clock frequency used,
modify the serial clock input frequency via the settings of the flash microcomputer
programmer as required.
■ Serial Clock Frequency that Can Be Input
Calculate the serial clock frequency that can be input as follows:
Table 26.2-1 "Example of serial clock frequency calculation" shows a calculation example.
Serial clock frequency to be input=0.125 x oscillator clock frequency
Table 26.2-1 Example of serial clock frequency calculation
Oscillator
clock
frequency
Maximum serial clock
frequency that can be
input to microcomputer
Maximum serial clock
frequency that can be set for
AF220/AF210/AF120/AF110
Maximum serial clock
frequency that can be
set for AF200
4 MHz
500 kHz
500 kHz
500 kHz
584
26.3 System Configuration of Flash Microcomputer Programmer
26.3 System Configuration of Flash Microcomputer Programmer
This section describes the system configuration of Yokogawa Digital Computer
Corporation flash microcomputer programmer.
■ System Configuration of the Flash Microcomputer Programmer
Table 26.3-1 "System configuration of the flash microcomputer programmer" shows the system
configuration of the flash microcomputer programmer.
Table 26.3-1 System configuration of the flash microcomputer programmer
Type
Function
AF220/AC4P
Main
body
Model with built-in Ethernet interface /100V to 220V power adapter
AF210/AC4P
Standard model /100V to 220V power adapter
AF120/AC4P
Model with built-in single key Ethernet interface /100V to 220V power adapter
AF110/AC4P
Single key model /100V to 220V power adapter
AZ221
Programmer dedicated RS232C cable for PC/AT
AZ210
Standard target probe (a) length: 1m
FF201
Fujitsu F2MC-16LX flash microcomputer control module
AZ290
Remote controller
/P2
2MB PC Card (Option) FLASH memory capacity up to 128 KB supported
/P4
4MB PC Card (Option) FLASH memory capacity of up to 512 KB supported
Inquiries: Yokogawa Digital Computer Corporation
Telephone number: (81)-42-333-6224
Note:
The AF200 flash microcomputer programmer is a discontinued product; however, the control
module FF201 is compatible with it. Serial programming connection is also supported, in the
sense shown in the example in the next section.
585
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
26.4 Examples of Serial Programming Connection
This section shows examples of serial programming connections in various modes.
■ Examples of Serial Programming Connections
Examples for the following four types of connections are shown below.
586
•
Example of connection in single-chip mode (using power from the user system)
•
Example of connection in single-chip mode (power supplied from the flash microcomputer
programmer)
•
Example minimum connection with flash microcomputer programmer (using power from the
user system)
•
Example of minimum connection with flash microcomputer programmer (power supplied from
the flash microcomputer programmer)
26.4 Examples of Serial Programming Connection
■ Example of Connection in Single-Chip Mode (Using Power from User System)
In the user system, mode pins MD2 and MD0, which are set to single-chip mode, are supplied
with the inputs MD2=1 and MD0=0 by TAUX3 and TMODE of AF220/AF210/AF120/AF110, and
the system is set to serial programming mode (serial programming mode: MD2, MD1,
MD0="110").
Figure 26.4-1 Example of serial programming connection in single chip mode for MB90F428G/
MB90F423G (power supplied from the user system)
AF220/AF210/AF120/AF110
Flash microcomputer
programmer
TAUX3
User system
Connector
DX10-28S
MB90F428G/MB90F423G
(19)
MD2
10k
10k
MD1
10K
TMODE
MD0
X0
(12)
4MHz
X1
TAUX
(23)
/TICS
(10)
P00
10K
User
10k
10k
/TRES
(5)
RST
User
TTXD
TRXD
TCK
(13)
(27)
(6)
TVcc
(2)
GND
(7,8,
14,15,
21,22,
1,28)
10k
SIN1
SOT1
SCK1
User power
supply
Pin 14
Pins 3, 4, 9, 11, 16, 17,
18, 20, 24, 25 and 26
are open
DX10-28S: write angle type
P01
Vcc
Vss
Pin 1
DX10-28S
Pin 28
Pin 15
Pin assignment of connector (Hirose Electric)
587
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
Figure 26.4-2 Pin control circuit
AF220/AF210/AF120/AF110
Write control pin
MB90F428G/MB90F423G
Write control pin
10K
AF220/AF210/AF120/AF110
/TICS pin
User
Notes:
588
•
Similarly to P00, using the SIN1, SOT1, and SCK1 pins in the user system requires a control
circuit as shown in Figure 26.4-2 "Pin control circuit" (the user circuit is disconnected in serial
programming mode by the flash microcomputer programmer’s "/TICS" signal).
•
Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off.
26.4 Examples of Serial Programming Connection
■ Example of Connection in Single-Chip Mode (Power Supply from the Flash Microcomputer
Programmer)
In the user system, mode pins MD2 and MD0, which are set to single-chip mode, are supplied
with the inputs MD2=1 and MD0=0 by TAUX3 and TMODE of AF220/AF210/AF120/AF110, and
the system is set to serial programming mode (serial programming mode: MD2, MD1,
MD0="110").
Figure 26.4-3 Example of serial programming connection in single-chip mode of MB90F428G/
MB90F423G (power supply from the flash microcomputer programmer)
AF220/AF210/AF120/AF110
Flash microcomputer
programmer
TAUX3
User system
Connector
DX10-28S
(19)
MB90F428G/MB90F423G
MD2
10k
10k
MD1
10k
MD0
X0
(12)
TMODE
4MHz
X1
TAUX
(23)
/TICS
(10)
P00
10K
User
10k
10k
RST
(5)
/TRES
User
TTXD
TRXD
TCK
TVcc
Vcc
TVPP1
GND
10k
SIN1
SOT1
SCK1
(13)
(27)
(6)
(2)
(3)
(16)
(7,8,
14,15,
21,22,
1,28)
User power
supply
Vcc
Vss
Pin 14
Pins 4, 9, 11, 17, 18,
20, 24, 25 and 26
are open
Pin 1
DX10-28S
Pin 28
DX10-28S: write angle type
P01
Pin 15
Pin assignment of connector (Hirose Electric)
589
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
Figure 26.4-4 Pin control circuit
AF220/AF210/AF120/AF110
Write control pin
MB90F428G/MB90F423G
Write control pin
10K
AF220/AF210/AF120/AF110
/TICS pin
User
Notes:
590
•
Similarly to P00, using the SIN1, SOT1, and SCK1 pins in the user system requires a control
circuit as shown in Figure 26.4-4 "Pin control circuit" (the user circuit is disconnected in serial
programming mode by the flash microcomputer programmer’s "/TICS" signal).
•
Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off.
•
When supplying the programming power from the AF220/AF210/AF120/AF110, do not shortcircuit it with the power supply of the user system.
26.4 Examples of Serial Programming Connection
■ Example of Minimum Connection with Flash Microcomputer Programmer (Using Power from the User
System)
If, in serial programming mode, pins (MD2, MD0 and P00) are set as shown below, MD2, MD0,
and P00 do not need to be connected with the flash microcomputer programmer.
Figure 26.4-5 Example of minimum connection with flash micro-computer programmer of MB90F428G/
MB90F423G (using power from the user system)
AF220/AF210/AF120/AF110
Flash microcomputer
programmer
MB90F428G/MB90F423G
User system
10k
Serial rewrite mode 1
Serial rewrite
mode 1
MD2
10k
10k
MD1
10k
10k
MD0
10k
Serial rewrite mode 0
X0
4MHz
X1
P00
Serial rewrite
mode 0
User circuit
10k
10k
Serial rewrite mode 1
User circuit
Connector
DX10-28S
10k
/TRES
(5)
TTXD
(13)
RST
SIN1
TRXD
(27)
SOT1
TCK
TVcc
(6)
SCK1
GND
(2)
Vcc
User power
supply
(7,8,
14,15,
21,22,
1,28)
Pin 14
Pins 3, 4, 9, 10, 11, 12,
16, 17,18,19,20,23,24,25
and 26 are open
DX10-28S
Pin 28
DX10-28S: write angle type
Pin 1
Pin 15
Pin assignment of connector (Hirose Electric)
591
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
Figure 26.4-6 Pin control circuit
AF220/AF210/AF120/AF110
Write control pin
MB90F428G/MB90F423G
Write control pin
10K
AF220/AF210/AF120/AF110
/TICS pin
User
Notes:
592
•
Using the pins SIN1, SOT1, and SCK1 in the user system requires a control circuit as shown
in Figure 26.4-6 "Pin control circuit" (the user circuit is disconnected in serial programming
mode by the flash microcomputer programmer’s "/TICS" signal).
•
Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off.
26.4 Examples of Serial Programming Connection
■ Example of Minimum Connection with Flash Microcomputer Programmer (with Power Supply From
Flash Microcomputer Programmer)
If, in serial programming mode, pins MD2, MD0, and P00 are set as shown below, the pins
MD2, MD0, and P00 do not need to be connected with the flash microcomputer programmer.
Figure 26.4-7 Example of minimum connection with flash microcomputer programmer on MB90F428G/
MB90F423G (with power supply from flash micro-computer programmer)
AF220/AF210/A F120/AF110
Flash microcomputer
User system
programmer
Serial rewrite mode 1
10k
MB90F428G/MB90F423G
MD2
10k
10k
Serial rewrite
mode 1
MD1
10k
10k
MD0
Serial rewrite mode 0
10k
X0
4MHz
X1
P00
10k
Serial
rewrite
mode 0
User circuit
P01
Serial rewrite mode 1
User circuit
Connector
DX10-28S
/TRES
TTXD
TRXD
TCK
Vcc
TVPP1
GND
10k
(5)
(13)
(27)
(6)
(2)
RST
SIN1
SOT1
SCK1
Vcc
(16)
User power
supply
(7,8,
14,15,
21,22,
1,28)
Pin 14
Pins 4, 9, 10, 11, 12, 17,
18, 19, 20, 23, 24, 25
and 26 are open
Pin 1
DX10-28S
Pin 28
DX10-28S: write angle type
Vss
Pin 15
Pin assignment of connector (Hirose Electric)
593
CHAPTER 26 EXAMPLE OF SERIAL PROGRAMMING CONNECTION
Figure 26.4-8 Pin control circuit
AF220/AF210/AF120/AF110
Write control pin
MB90F428G/MB90F423G
Write control pin
10K
AF220/AF210/AF120/AF110
/TICS pin
User
Notes:
594
•
Using the SIN1, SOT1, and SCK1 pins in the user system requires a control circuit as shown
in Figure 26.4-8 "Pin control circuit" (the user circuit is disconnected in serial programming
mode by the flash microcomputer programmer’s "/TICS" signal).
•
Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off.
•
When supplying the programming power from the AF220/AF210/AF120/AF110, do not shortcircuit it with the power supply of the user system.
APPENDIX
The Appendix provides the I/O map and describes the instructions of the F2MC-16LX.
APPENDIX A "I/O Map"
APPENDIX B "Instructions"
595
APPENDIX A I/O Map
APPENDIX A I/O Map
The addresses under which the registers for each peripheral are allocated are listed
below.
■ I/O Map
Table A-1 "I/O map" shows the addresses under which the registers for each peripheral function
are allocated.
Table A-1 I/O map (1)
Address
Register
Abbr.
Access
Peripheral
Initial value
00H
Port 0 data register
PDR0
R/W
Port 0
XXXXXXXX
01H
Port 1 data register
PDR1
R/W
Port 1
--XXXXXX
02H
Use prohibited
03H
Port 3 data register
PDR3
R/W
Port 3
XX------
04H
Port 4 data register
PDR4
R/W
Port 4
XXXXXXXX
05H
Port 5 data register
PDR5
R/W
Port 5
XXXXXXXX
06H
Port 6 data register
PDR6
R/W
Port 6
XXXXXXXX
07H
Port 7 data register
PDR7
R/W
Port 7
XXXXXXXX
08H
Port 8 data register
PDR8
R/W
Port 8
XXXXXXXX
09H
Port 9 data register
PDR9
R/W
Port 9
------XX
0A to 0FH
Use prohibited
10H
Port 0 direction register
DDR0
R/W
Port 0
00000000
11H
Port 1 direction register
DDR1
R/W
Port 1
--000000
12H
Use prohibited
13H
Port 3 direction register
DDR3
R/W
Port 3
00------
14H
Port 4 direction register
DDR4
R/W
Port 4
00000000
15H
Port 5 direction register
DDR5
R/W
Port 5
00000000
16H
Port 6 direction register
DDR6
R/W
Port 6
00000000
17H
Port 7 direction register
DDR7
R/W
Port 7
00000000
18H
Port 8 direction register
DDR8
R/W
Port 8
00000000
19H
Port 9 direction register
DDR9
R/W
Port 9
------00
1AH
Analog input permit
ADER
R/W
Port 6, CA/D
11111111
1B to 1FH
Use prohibited
596
APPENDIX A I/O Map
Table A-1 I/O map (1) (Continued)
Address
Register
Abbr.
Access
Peripheral
20H
Lower bits of the A/D control status
register
ADCSL
R/W
21H
Upper bits of A/D control status
register
ADCSH
R/W
00000000
22H
Lower bits of A/D data register
ADCRL
R
XXXXXXXX
23H
Upper bits of A/D data register
ADCRH
R/W
00101XXX
24H
Compare clear register
CPCLR
R/W
25H
26H
Timer data register
TCDT
A/D converter
Initial value
16-bit free-run
timer
R/W
00000000
XXXXXXXX
XXXXXXXX
00000000
00000000
27H
28H
Upper bits of timer control status
register
TCCSL
R/W
00000000
29H
Lower bits of timer control status
register
TCCSH
R/W
0--00000
2AH
Lower bits of PPG0 control status
register
PCNTL0
R/W
2BH
Upper bits of PPG0 control status
register
PCNTH0
R/W
2CH
Lower bits of PPG1 control status
register
PCNTL1
R/W
2DH
Upper bits of PPG1 control status
register
PCNTH1
R/W
2EH
Lower bits of PPG2 control status
register
PCNTL2
R/W
2FH
Upper bits of PPG2 control status
register
PCNTH2
R/W
30H
External interrupt enable
ENIR
R/W
31H
External interrupt request
EIRR
R/W
00000000
32H
Lower bits of external interrupt level
ELVRL
R/W
00000000
33H
Upper bits of external interrupt level
ELVRH
R/W
00000000
34H
Serial mode register 0
SMR0
R/W
35H
Serial control register 0
SCR0
R/W
00000100
36H
Input data register 0/
Output data register 0
SIDR0/
SODR0
R/W
XXXXXXXX
37H
Serial status register 0
SSR0
R/W
00001000
16bit PPG0
00000000
0000000-
16bit PPG1
00000000
0000000-
16bit PPG2
00000000
0000000-
External interrupt
UART0
00000000
00000-00
597
APPENDIX A I/O Map
Table A-1 I/O map (1) (Continued)
Address
Register
Abbr.
Access
Peripheral
38H
Serial mode register 1
SMR1
R/W
39H
Serial control register 1
SCR1
R/W
00000100
3AH
Input data register 1/
Output data register 1
SIDR1/
SODR1
R/W
XXXXXXXX
3BH
Serial status register 1
SSR1
R/W
00001000
3CH
Use prohibited
3DH
Clock divide control register 0
CDCR0
R/W
Prescaler
0---0000
3EH
CAN wake-up control register
CWUCR
R/W
CAN
-------0
3FH
Clock divide control register 1
CDCR1
R/W
Prescaler
0---0000
40 to 4FH
Reserved for CAN interface 0. Refer to the "CAN controller hardware manual".
50H
Timer control status
Lower bits of Register 0
TMCSR0L
R/W
51H
Timer control status
Upper bits of Register 0
TMCSR0H
R/W
----0000
52H
Timer register 0/ reload register 0
TMR0/
TMRLR0
R/W
XXXXXXXX
53H
UART1
Initial value
16-bit reload timer
0
00000-00
00000000
XXXXXXXX
54H
Timer control status
Lower bits of register 0
TMCSR1L
R/W
55H
Timer control status
Upper bits of Register 0
TMCSR1H
R/W
----0000
56H
Timer register 1/ reload register 1
TMR1/
TMRLR1
R/W
XXXXXXXX
57H
16-bit reload timer
1
00000000
XXXXXXXX
58H
Lower bits of watch timer control
register
WTCRL
R/W
59H
Upper bits of watch timer control
register
WTCRH
R/W
5AH
Lower bits of sound control register
SGCRL
R/W
5BH
Upper bits of sound control register
SGCRH
R/W
0-----00
5CH
Frequency data register
SGFR
R/W
XXXXXXXX
5DH
Amplitude data register
SGAR
R/W
00000000
5EH
Decrement capture register
SGDR
R/W
XXXXXXXX
5FH
Tone count register
SGTR
R/W
XXXXXXXX
60H
Input capture register 0
IPCP0
R
61H
62H
63H
598
Input capture register 1
IPCP1
R
Watch timer
(main clock)
000--000
00000000
Sound generator
Input Capture
0/1
00000000
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
APPENDIX A I/O Map
Table A-1 I/O map (1) (Continued)
Address
64H
Register
Input capture register 2
Abbr.
IPCP2
Access
R
65H
66H
Input capture register 3
IPCP3
Peripheral
Input Capture
2/3
R
Initial value
XXXXXXXX
XXXXXXXX
XXXXXXXX
XXXXXXXX
67H
68H
Input capture control
Status 0/1
ICS01
R/W
Input capture
0/1
00000000
69H
Use prohibited
6AH
Input capture control
Status 2/3
ICS23
R/W
Input capture
2/3
00000000
6BH
Use prohibited
6CH
Lower bits of LCD control register
LCRL
R/W
00100000
6DH
Upper bits of LCD control register
LCRH
R/W
LCD controller /
driver
6EH
Low-voltage/CPU operation detection
reset control register
LVRC
R/W
Low-voltage/CPU
operation
detection reset
00111000
6FH
ROM mirror
ROMM
W
ROM mirror
-------1
70 to 7FH
Reserved for CAN interface 1. Refer to the "CAN controller hardware manual".
80H
PWM control register 0
81H
Use prohibited
82H
PWM control register 1
83H
Use prohibited
84H
PWM control register 2
85H
Use prohibited
86H
PWM control register 3
87 to 9DH
Use prohibited
9EH
X00X0000
PWC0
R/W
Stepping motor
controller 0
000000-0
PWC1
R/W
Stepping motor
controller 1
000000-0
PWC2
R/W
Stepping motor
controller 2
000000-0
PWC3
R/W
Stepping motor
controller 3
000000-0
Program address detection control
register
PACSR
R/W
Address match
detect function
----0-0-
9FH
Delay interrupt/release
DIRR
R/W
Delay interrupt
-------0
A0H
Low-power consumption mode
LPMCR
R/W
00011000
A1H
Clock select
CKSCR
R/W
Low-power
consumption
control circuit
A2 to A7H
Use prohibited
A8H
Watchdog control
WDTC
R/W
Watchdog timer
X-XX111
A9H
Timebase timer control register
TBTC
R/W
Timebase timer
1--00100
11111100
599
APPENDIX A I/O Map
Table A-1 I/O map (1) (Continued)
Address
Register
AAH
Watch timer control register
AB to ADH
Use prohibited
AEH
Flash control register
AFH
Use prohibited
B0H
Abbr.
Access
Peripheral
Initial value
WTC
R/W
Watch timer
(subclock)
1001000
FMCS
R/W
Flash I/F
00010000
Interrupt control register 00
ICR00
R/W
Interrupt controller
00000111
B1H
Interrupt control register 01
ICR01
R/W
00000111
B2H
Interrupt control register 02
ICR02
R/W
00000111
B3H
Interrupt control register 03
ICR03
R/W
00000111
B4H
Interrupt control register 04
ICR04
R/W
00000111
B5H
Interrupt control register 05
ICR05
R/W
00000111
B6H
Interrupt control register 06
ICR06
R/W
00000111
B7H
Interrupt control register 07
ICR07
R/W
00000111
B8H
Interrupt control register 08
ICR08
R/W
00000111
B9H
Interrupt control register 09
ICR09
R/W
00000111
BAH
Interrupt control register 10
ICR10
R/W
00000111
BBH
Interrupt control register 11
ICR11
R/W
00000111
BCH
Interrupt control register 12
ICR12
R/W
00000111
BDH
Interrupt control register 13
ICR13
R/W
00000111
BEH
Interrupt control register 14
ICR14
R/W
00000111
BFH
Interrupt control register 15
ICR15
R/W
00000111
C0 to FFH
Use prohibited
•
•
600
An initial value of "?" indicates an unused bit, while "X" indicates that no value is defined.
The addresses in the range of 0000H to 00FFH, which not listed in the table, are reserved for major MCU functions.
Read access to these addresses returns an undefined value, and write accesses to these addresses is prohibited.
APPENDIX A I/O Map
Table A-2 I/O map (2)
Address
Register
Abbr.
Access
Peripheral
Initial value
1FF0H
Program address detect register 0
PADR0
R/W
1FF1H
Program address detect register 1
PADR0
R/W
1FF2H
Program address detect register 2
PADR0
R/W
XXXXXXXX
1FF3H
Program address detect register 3
PADR1
R/W
XXXXXXXX
1FF4H
Program address detect register 4
PADR1
R/W
XXXXXXXX
1FF5H
Program address detect register 5
PADR1
R/W
XXXXXXXX
•
Address match
detect function
XXXXXXXX
XXXXXXXX
An initial value of "?" indicates an unused bit, while "X" indicates that no value is defined.
Table A-3 I/O map (3)
Address
Register
3900 to
391FH
Use prohibited
3920H
PPG0 down-counter register
Abbr.
PDCR0
Access
R
Peripheral
16bit PPG0
PPG0 interval set register
PCSR0
W
XXXXXXXX
3923H
3924H
XXXXXXXX
PPG0 duty set register
PDUT0
W
XXXXXXXX
XXXXXXXX
3925H
3926 to
3927H
Use prohibited
3928H
PPG1 down-counter register
PDCR1
R
PPG1 interval set register
PCSR1
W
392BH
392CH
11111111
XXXXXXXX
XXXXXXXX
PPG1 duty set register
392DH
392E to
392FH
16bit PPG1
11111111
3929H
392AH
11111111
11111111
3921H
3922H
Initial value
PDUT1
W
XXXXXXXX
XXXXXXXX
Use prohibited
601
APPENDIX A I/O Map
Table A-3 I/O map (3) (Continued)
Address
3930H
Register
PPG2 down-counter register
Abbr.
PDCR2
Access
R
Peripheral
16bit PPG2
PPG2 interval set register
PCSR2
W
XXXXXXXX
XXXXXXXX
3933H
3934H
11111111
11111111
3931H
3932H
Initial value
PPG2 duty set register
PDUT2
W
XXXXXXXX
XXXXXXXX
3935H
3936 to
3959H
Use prohibited
395AH
Sub-second data register
WTBR
R/W
395BH
Watch timer (Main
clock)
395CH
XXXXXXXX
XXXXXXXX
---XXXXX
395DH
Second data register
WTSR
R/W
--XXXXXX
395EH
Minute data register
WTMR
R/W
--XXXXXX
395FH
Hour data register
WTHR
R/W
---XXXXX
3960 to
396BH
RAM for LCD display
VRAM
R/W
LCD controller/
driver
XXXXXXXX
396C to
397FH
Use prohibited
3980H
PWM1 compare register 0
PWC10
R/W
Stepping motor
controller 0
XXXXXXXX
3981H
3982H
PWM2 compare register 0
PWC20
R/W
------XX
XXXXXXXX
------XX
3983H
3984H
PWM1 select register 0
PWS10
R/W
--000000
3985H
PWM2 select register 0
PWS20
R/W
-0000000
3986 to
3987H
Use prohibited
3988H
PWM1 compare register 1
PWC11
R/W
3989H
398AH
PWM2 compare register 1
PWC21
R/W
Stepping motor
controller 1
XXXXXXXX
------XX
XXXXXXXX
------XX
398BH
398CH
PWM1 select register 1
PWS11
R/W
--000000
398DH
PWM2 select register 1
PWS21
R/W
-0000000
398E to
398FH
Use prohibited
602
APPENDIX A I/O Map
Table A-3 I/O map (3) (Continued)
Address
3990H
Register
PWM1 compare register 2
Abbr.
PWC12
Access
R/W
3991H
3992H
PWM2 compare register 2
PWC22
Peripheral
Stepping motor
controller 2
R/W
Initial value
XXXXXXXX
------XX
XXXXXXXX
------XX
3993H
3994H
PWM1 select register 2
PWS12
R/W
--000000
3995H
PWM2 select register 2
PWS22
R/W
-0000000
3996 to
3997H
Use prohibited
3998H
PWM1 compare register 3
PWC13
R/W
3999H
399AH
PWM2 compare register 3
PWC23
Stepping motor
controller 3
R/W
XXXXXXXX
------XX
XXXXXXXX
------XX
399BH
399CH
PWM1 select register 3
PWS13
R/W
--000000
399DH
PWM2 select register 3
PWS23
R/W
-0000000
399E to
39FFH
Use prohibited
3A00 to
3AFFH
Reserved for CAN interface 0. Refer to the "CAN controller hardware manual."
3B00 to
3BFFH
Reserved for CAN interface 1. Refer to the "CAN controller hardware manual."
3C00 to
3CFFH
Reserved for CAN interface 0. Refer to the "CAN controller hardware manual."
3D00 to
3DFFH
Reserved for CAN interface 1. Refer to the "CAN controller hardware manual."
3E00 to
3EFFH
Use prohibited
•
An initial value of "..." indicates an undefined bit, while "X" indicates that no value is defined.
❍ Description of write/read operations
R/W: Reading/writing permitted
R: Read-only
W: Write-only
❍ Description of initial values
0: This bit has the initial value "0".
1: This bit has the initial value "1".
X: The initial value for this bit is not specified.
-: This bit is undefined. The initial value for this bit is not specified.
603
APPENDIX B Instructions
APPENDIX B Instructions
Appendix B describes the instructions used by the F2MC-16LX.
B.1 "Instruction Types"
B.2 "Addressing"
B.3 "Direct Addressing"
B.4 "Indirect Addressing"
B.5 "Execution Cycle Count"
B.6 "Effective Address Field"
B.7 "How to Read the Instruction List"
B.8 "F2MC-16LX Instruction List"
B.9 "Instruction Map"
604
APPENDIX B Instructions
B.1
Instruction Types
The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an
effective address field of each instruction or using the instruction code itself.
■ Instruction Types
The F2MC-16LX supports the following 351 types of instructions:
•
41 transfer instructions (byte)
•
38 transfer instructions (word or long word)
•
42 addition/subtraction instructions (byte, word, or long word)
•
12 increment/decrement instructions (byte, word, or long word)
•
11 comparison instructions (byte, word, or long word)
•
11 unsigned multiplication/division instructions (word or long word)
•
11 signed multiplication/division instructions (word or long word)
•
39 logic instructions (byte or word)
•
6 logic instructions (long word)
•
6 sign inversion instructions (byte or word)
•
1 normalization instruction (long word)
•
18 shift instructions (byte, word, or long word)
•
50 branch instructions
•
6 accumulator operation instructions (byte or word)
•
28 other control instructions (byte, word, or long word)
•
21 bit operation instructions
•
10 string instructions
605
APPENDIX B Instructions
B.2
Addressing
With the F2MC-16LX, the address format is determined by the instruction effective
address field or the instruction code itself (implied). When the address format is
determined by the instruction code itself, specify an address in accordance with the
instruction code used. Some instructions permit the user to select several types of
addressing.
■ Addressing
The F2MC-16LX supports the following 23 types of addressing:
606
•
Immediate (#imm)
•
Register direct
•
Direct branch address (addr16)
•
Physical direct branch address (addr24)
•
I/O direct (io)
•
Abbreviated direct address (dir)
•
Direct address (addr16)
•
I/O direct bit address (io:bp)
•
Abbreviated direct bit address (dir:bp)
•
Direct bit address (addr16:bp)
•
Vector address (#vct)
•
Register indirect (@RWj j = 0 to 3)
•
Register indirect with post increment (@RWj+ j = 0 to 3)
•
Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
•
Long register indirect with displacement (@RLi + disp8 i = 0 to 3)
•
Program counter indirect with displacement (@PC + disp16)
•
Register indirect with base index (@RW0 + RW7, @RW1 + RW7)
•
Program counter relative branch address (rel)
•
Register list (rlst)
•
Accumulator indirect (@A)
•
Accumulator indirect branch address (@A)
•
Indirectly-specified branch address (@ear)
•
Indirectly-specified branch address (@eam)
APPENDIX B Instructions
■ Effective Address Field
Table B.2-1 "Effective address field" lists the address formats specified by the effective address
field.
Table B.2-1 Effective address field
Code
Representation
00
R0
RW0
RL0
01
R1
RW1
(RL0)
02
R2
RW2
RL1
03
R3
RW3
(RL1)
04
R4
RW4
RL2
05
R5
RW5
(RL2)
06
R6
RW6
RL3
07
R7
RW7
(RL3)
08
@RW0
09
@RW1
Address format
Default bank
Register direct: Individual parts correspond
to the byte, word, and long word types in
order from the left.
None
DTB
DTB
Register indirect
0A
@RW2
ADB
0B
@RW3
SPB
0C
@RW0+
DTB
0D
@RW1+
DTB
Register indirect with post increment
0E
@RW2+
ADB
0F
@RW3+
SPB
10
@RW0+disp8
DTB
11
@RW1+disp8
DTB
Register indirect with 8-bit displacement
12
@RW2+disp8
ADB
13
@RW3+disp8
SPB
14
@RW4+disp8
DTB
15
@RW5+disp8
DTB
Register indirect with 8-bit displacement
16
@RW6+disp8
ADB
17
@RW7+disp8
SPB
18
@RW0+disp16
DTB
19
@RW1+disp16
DTB
Register indirect with 16-bit displacement
1A
@RW2+disp16
ADB
1B
@RW3+disp16
SPB
1C
@RW0+RW7
1D
@RW1+RW7
1E
@PC+disp16
1F
addr16
DTB
Register indirect with index
Register indirect with index
PC indirect with 16-bit displacement
Direct address
DTB
PCB
DTB
607
APPENDIX B Instructions
B.3
Direct Addressing
An operand value, register, or address is specified explicitly in direct addressing
mode.
■ Direct Addressing
❍ Immediate addressing (#imm)
Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32).
Figure B.3-1 Example of immediate addressing (#imm)
MOVW A, #01212H (This instruction stores the operand value in A.)
Before execution
A
2233 4455
After execution
A
4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.)
❍ Register direct addressing
Specify a register explicitly as an operand. Table B.3-1 "Direct addressing registers" lists the
registers that can be specified. Figure B.3-2 "Example of register direct addressing" shows an
example of register direct addressing.
Table B.3-1 Direct addressing registers
General-purpose
register
Special-purpose
register
Byte
R0, R1, R2, R3, R4, R5, R6, R7
Word
RW0, RW1, RW2, RW3, RW4, R5W,
RW6, RW7
Long word
RL0, RL1, RL2, RL3
Accumulator
A, AL
Pointer
SP *1
Bank
PCB, DTB, USB, SSB, ADB
Page
DPR
Control
PS, CCR, RP, ILM
*1: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used
depending on the value of the S flag bit in the condition code register (CCR). For branch
instructions, the program counter (PC) is not specified in an instruction operand but is
specified implicitly.
608
APPENDIX B Instructions
Figure B.3-2 Example of register direct addressing
MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose
register R0.)
Before execution
A
0716 2534
After execution
A
0716 2564
Memory space
R0
??
Memory space
R0
34
❍ Direct branch addressing (addr16)
Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits,
which indicates the branch destination in the logical address space. Direct branch addressing is
used for an unconditional branch, subroutine call, or software interrupt instruction. Bits 23 to 16
of the address are specified by the program bank register (PCB).
Figure B.3-3 Example of direct branch addressing (addr16)
JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing
in a bank.)
Before execution
After execution
PC 3 C 2 0
PCB 4 F
PC 3 B 2 0
Memory space
4F3C22H
4F3C21H
4F3C20H
3B
20
62
4F3B20H
Next instruction
JMP 3B20H
PCB 4 F
❍ Physical direct branch addressing (addr24)
Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits.
Physical direct branch addressing is used for unconditional branch, subroutine call, or software
interrupt instruction.
Figure B.3-4 Example of direct branch addressing (addr24)
JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit
addressing.)
Before execution
After execution
PC 3 C 2 0
PC 3 B 2 0
PCB 4 F
Memory space
4F3C23H
4F3C22H
4F3C21H
4F3C20H
33
3B
20
63
333B20H
Next instruction
JMPP 333B20H
PCB 3 3
609
APPENDIX B Instructions
❍ I/O direct addressing (io)
Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space
in the physical address space from 000000H to 0000FFH is accessed regardless of the data
bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is
invalid if specified before an instruction using I/O direct addressing.
Figure B.3-5 Example of I/O direct addressing (io)
MOVW A, i:0C0H (This instruction reads data by I/O direct addressing and stores it in A.)
Before execution
A
0716 2534
Memory space
0000C1H
0000C0H
After execution
A
FF
EE
2534 FFEE
❍ Abbreviated direct addressing (dir)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to
15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the
data bank register (DTB).
Figure B.3-6 Example of abbreviated direct addressing (dir)
MOVW S;20H, A
(This instruction writes the contents of the eight low-order bits of A in abbreviated
direct addressing mode.)
Before execution
4455
A
66
After execution
A
DTB 7 7
4455
66
Memory space
1212
776620H
1212
DTB 7 7
??
Memory space
776620H
12
❍ Direct addressing (addr16)
Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to
23 are specified by the data bank register (DTB). A prefix instruction for access space
addressing is invalid for this mode of addressing.
Figure B.3-7 Example of direct addressing (addr16)
BRA 3B20H (This instruction causes an unconditional relative branch.)
Before execution PC
3C20
PCB 4 F
Memory space
4F3C22H
4F3C21H
4F3C20H
After execution
PC
3B20
PCB 4 F
4F3B20H
610
FF
FE
60
BRA 3B20H
APPENDIX B Instructions
❍ I/O direct bit addressing (io:bp)
Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by
":bp", where the larger number indicates the most significant bit (MSB) and the lower number
indicates the least significant bit (LSB).
Figure B.3-8 Example of I/O direct bit addressing (io:bp)
SETB I:0C1H: (This instruction sets bits by I/O direct bit addressing.)
Memory space
Before execution
0000C1H
00
After execution
0000C1H
01
❍ Abbreviated direct bit addressing (dir:bp)
Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to
15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the
data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates
the most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-9 Example of abbreviated direct bit addressing (dir:bp)
SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.)
Memory space
Before execution DTB 5 5
DPR 6 6
556610H
00
Memory space
After execution
DTB 5 5
DPR 6 6
556610H
01
❍ Direct bit addressing (addr16:bp)
Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data
bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the
most significant bit (MSB) and the lower number indicates the least significant bit (LSB).
Figure B.3-10 Example of direct bit addressing (addr16:bp)
SETB 2222H:0 (This instruction sets bits by direct bit addressing.)
Memory space
Before execution DTB 5 5
552222H
00
Memory space
After execution
DTB 5 5
552222H
01
611
APPENDIX B Instructions
❍ Vector Addressing (#vct)
Specify vector data in an operand to indicate the branch destination address. There are two
sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or
software interrupt instruction.
Figure B.3-11 Example of vector addressing (#vct)
CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector
specified in an operand.)
Before execution
PC
0000
PCB F F
After execution
PC
Memory space
FFFFE1H
FFFFE0H
D0
00
FFC000H
EF
D000
PCB F F
CALLV #15
Table B.3-2 CALLV vector list
Instruction
Vector address L
Vector address H
CALLV #0
XXFFFEH
XXFFFFH
CALLV #1
XXFFFCH
XXFFFDH
CALLV #2
XXFFFAH
XXFFFBH
CALLV #3
XXFFF8H
XXFFF9H
CALLV #4
XXFFF6H
XXFFF7H
CALLV #5
XXFFF4H
XXFFF5H
CALLV #6
XXFFF2H
XXFFF3H
CALLV #7
XXFFF0H
XXFFF1H
CALLV #8
XXFFEEH
XXFFEFH
CALLV #9
XXFFECH
XXFFEDH
CALLV #10
XXFFEAH
XXFFEBH
CALLV #11
XXFFE8H
XXFFE9H
CALLV #12
XXFFE6H
XXFFE7H
CALLV #13
XXFFE4H
XXFFE5H
CALLV #14
XXFFE2H
XXFFE3H
CALLV #15
XXFFE0H
XXFFE1H
Note: A PCB register value is set in XX.
Note:
When the program bank register (PCB) is FFH, the vector area overlaps the vector area of IN
#vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2 "CALLV vector list").
612
APPENDIX B Instructions
B.4
Indirect Addressing
In indirect addressing mode, an address is specified indirectly by the address data of
an operand.
■ Indirect Addressing
❍ Register indirect addressing (@RWj j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address.
Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used,
system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or
additional data bank register (ADB) when RW2 is used.
Figure B.4-1 Example of register indirect addressing (@RWj j = 0 to 3)
MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.)
Before execution
A
0716
2534
RW1 D 3 0 F DTB 7 8
After execution
A
Memory space
78D310H
78D30FH
FF
EE
2534 FFEE
RW1 D 3 0 F DTB 7 8
❍ Register indirect addressing with post increment (@RWj+ j = 0 to 3)
Memory is accessed using the contents of general-purpose register RWj as an address. After
operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a
long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or
RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is
used, or additional data bank register (ADB) when RW2 is used.
If the post increment results in the address of the register that specifies the increment, the
incremented value is referenced after that. In this case, if the next instruction is a write
instruction, priority is given to writing by an instruction and, therefore, the register that would be
incremented becomes write data.
613
APPENDIX B Instructions
Figure B.4-2 Example of register indirect addressing with post increment
(@RWj+ j = 0 to 3)
MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post
increment and stores it in A.)
Before execution
A
0716
2534
Memory space
RW1 D 3 0 F DTB 7 8
After execution
A
78D310H
78D30FH
FF
EE
2534 FFEE
RW1 D 3 1 1 DTB 7 8
❍ Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to
3)
Memory is accessed using the address obtained by adding an offset to the contents of generalpurpose register RWj. Two types of offset, byte and word offsets, are used. They are added as
signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB)
when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank
register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or
RW6 is used.
Figure B.4-3 Example of register indirect addressing with offset
(@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3)
MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an
offset and stores it in A.)
Before execution
A
0716
2534
Memory space
RW1 D 3 0 F DTB 7 8
78D320H
78D31FH
FF
EE
(+10H)
After execution
A
2534 FFEE
RW1 D 3 0 F DTB 7 8
❍ Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3)
Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset
to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a
signed numeric value.
Figure B.4-4 Example of long register indirect addressing with offset
(@RLi + disp8 i = 0 to 3)
MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an
offset and stores it in A.)
Before execution A
RL2
0716
2534
F382 4B02
Memory space
824B28H
824B27H
(+25H)
After execution
614
A
2534 FFEE
RL2
F382 4B02
FF
EE
APPENDIX B Instructions
❍ Program counter indirect addressing with offset (@PC + disp16)
Memory is accessed using the address indicated by (instruction address + 4 + disp16). The
offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB).
Note that the operand address of each of the following instructions is not deemed to be (next
instruction address + disp16):
•
DBNZ eam, rel
•
DWBNZ eam, rel
•
CBNE eam, #imm8, rel
•
CWBNE eam, #imm16, rel
•
MOV eam, #imm8
•
MOVW eam, #imm16
Figure B.4-5 Example of program counter indirect addressing with offset (@PC + disp16)
MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a
offset and stores it in A.)
Before execution
A
0716
2534
PCB C 5 PC 4 5 5 6
After execution
A
2534 FFEE
PCB C 5 PC 4 5 5 A
Memory space
C5457BH
C5457AH
FF
EE
C5455AH
+20H C54559H
+4
C54558H
C54557H
C54556H
00
20
9E
73
MOVW
A, @PC+20H
❍ Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7)
Memory is accessed using the address determined by adding RW0 or RW1 to the contents of
general-purpose register RW7. Address bits 16 to 23 are indicated by the data bank register
(DTB).
Figure B.4-6 Example of register indirect addressing with base index
(@RW0 + RW7, @RW1 + RW7)
MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a
base index and stores it in A.)
Before execution
A
0716
RW1 D 3 0 F
2534
DTB 7 8
+
Memory space
78D411H
78D410H
FF
EE
RW7 0 1 0 1
After execution
A
2534 FFEE
RW1 D 3 0 F
DTB 7 8
RW7 0 1 0 1
615
APPENDIX B Instructions
❍ Program counter relative branch addressing (rel)
The address of the branch destination is a value determined by adding an 8-bit offset to the
program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing
or decrementing is not performed and the excess part is ignored, and therefore the address is
contained within a 64-kilobyte bank. This addressing is used for both conditional and
unconditional branch instructions. Address bits 16 to 23 are indicated by the program bank
register (PCB).
Figure B.4-7 Example of program counter relative branch addressing (rel)
BRA 3B20H (This instruction causes an unconditional relative branch.)
Before execution PC
3C20
PCB 4 F
Memory space
4F3C22H
4F3C21H
4F3C20H
After execution
PC
3B20
FF
FE
60
BRA 3B20H
PCB 4 F
4F3B20H
Next instruction
❍ Register list (rlst)
Specify a register to be pushed onto or popped from a stack.
Figure B.4-8 Configuration of the register list
MSB
LSB
RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0
A register is selected when the corresponding bit is 1 and deselected when the bit is 0.
616
APPENDIX B Instructions
Figure B.4-9 Example of register list (rlist)
POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple
word registers indicated by the register list.)
SP
34FA
SP
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
RW0
RW1
RW2
RW3
RW4
RW5
RW6
RW7
SP
02 01
04 03
Memory space
Memory space
SP
34FEH
34FDH
34FCH
34FBH
34FAH
04
03
02
01
34FE
04
03
02
01
34FEH
34FDH
34FCH
34FBH
34FAH
After execution
Before execution
❍ Accumulator indirect addressing (@A)
Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits)
of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank
register (DTB).
Figure B.4-10 Example of accumulator indirect addressing (@A)
MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.)
Before execution
A
0716
2534
DTB B B
After execution
A
Memory space
BB2535H
BB2534H
FF
EE
0716 FFEE
DTB B B
617
APPENDIX B Instructions
❍ Accumulator indirect branch addressing (@A)
The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the
accumulator. It indicates the branch destination in the bank address space. Address bits 16 to
23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction,
however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is
used for unconditional branch instructions.
Figure B.4-11 Example of accumulator indirect branch addressing (@A)
JMP @A (This instruction causes an unconditional branch by accumulator indirect branch
addressing.)
Before execution PC
3C20
PCB 4 F
A
6677
3B20
PC
3B20
PCB 4 F
Memory space
4F3C20H
4F3B20H
After execution
A
61
JMP @A
Next instruction
6677 3B20
❍ Indirect specification branch addressing (@ear)
The address of the branch destination is the word data at the address indicated by ear.
Figure B.4-12 Example of indirect specification branch addressing (@ear)
JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.)
Before execution
3C20
PCB 4 F
PW0 7 F 4 8
DTB 2 1
PC
Memory space
4F3C21H
4F3C20H
4F3B20H
After execution
3B20
PCB 4 F
PW0 7 F 4 8
DTB 2 1
PC
217F49H
217F48H
08
73
JMP @@RW0
Next instruction
3B
20
❍ Indirect specification branch addressing (@eam)
The address of the branch destination is the word data at the address indicated by eam.
Figure B.4-13 Example of indirect specification branch addressing (@eam)
JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.)
Before execution PC
3C20
PCB 4 F
4F3C21H
4F3C20H
PW0 3 B 2 0
After execution
PC
3B20
PW0 3 B 2 0
618
Memory space
PCB 4 F
4F3B20H
00
73
JMP @RW0
Next instruction
APPENDIX B Instructions
B.5
Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is
obtained by adding the number of cycles required for each instruction, "correction
value" determined by the condition, and the number of cycles for instruction fetch.
■ Execution Cycle Count
The number of cycles required for instruction execution (execution cycle count) is obtained by
adding the number of cycles required for each instruction, "correction value" determined by the
condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction
from memory such as internal ROM connected to a 16-bit bus, the program fetches the
instruction being executed in word increments. Therefore, intervening in data access increases
the execution cycle count.
Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus,
the program fetches every byte of an instruction being executed. Therefore, intervening in data
access increases the execution cycle count. In CPU intermittent operation mode, access to a
general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes
the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low
power consumption mode control register. Therefore, for the cycle count required for instruction
execution in CPU intermittent operation mode, add the "access count x cycle count for the halt"
as a correction value to the normal execution count.
619
APPENDIX B Instructions
■ Calculating the Execution Cycle Count
Table B.5-1 "Execution cycle counts in each addressing mode" lists execution cycle counts and
Table B.5-2 "Cycle count correction values for counting execution cycles" and Table B.5-3
"Cycle count correction values for counting instruction fetch cycles" summarize correction value
data.
Table B.5-1 Execution cycle counts in each addressing mode
(a) (*1)
Code
Operand
00
|
07
Ri
Rwi
RLi
08
|
0B
Register access count in
each addressing mode
See the instruction list.
See the instruction list.
@RWj
2
1
0C
|
0F
@RWj+
4
2
10
|
17
@RWi+disp8
2
1
18
|
1B
@RWi+disp16
2
1
1C
1D
1E
1F
@RW0+RW7
@RW1+RW7
@PC+disp16
addr16
4
4
2
1
2
2
0
0
*1: (a) is used for
List".
620
Execution cycle count in
each addressing mode
(cycle count) and B (correction value) in B.8 "F2MC-16LX Instruction
APPENDIX B Instructions
Table B.5-2 Cycle count correction values for counting execution cycles
(b) byte (*1)
Operand
(c) word (*1)
(d) long (*1)
Cycle
count
Access
count
Cycle
count
Access
count
Cycle
count
Access
count
Internal register
+0
1
+0
1
+0
2
Internal memory
Even address
+0
1
+0
1
+0
2
Internal memory
Odd address
+0
1
+2
2
+4
4
External data bus
16-bit even address
+1
1
+1
1
+2
2
External data bus
16-bit odd address
+1
1
+4
2
+8
4
External data bus
8-bits
+1
1
+4
2
+8
4
*1: (b), (c), and (d) are used for
Instruction List".
(cycle count) and B (correction value) in B.8 "F2MC-16LX
Note:
When an external data bus is used, the cycle counts during which an instruction is made to
wait by ready input or automatic ready must also be added.
Table B.5-3 Cycle count correction values for counting instruction fetch cycles
Byte boundary
Word
boundary
Internal memory
-
+2
External data bus 16-bits
-
+3
External data bus 8-bits
+3
-
Instruction
Note:
•
When an external data bus is used, the cycle counts during which an instruction is made to
wait by ready input or automatic ready must also be added.
•
Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the
correction values to calculate the worst case.
621
APPENDIX B Instructions
B.6
Effective Address Field
Table B.6-1 "Effective address field" shows the effective address field.
■ Effective Address Field
Table B.6-1 Effective address field
Code
Representation
00
01
R0
R1
RW0
RW1
RL0
(RL0)
02
03
R2
R3
RW2
RW3
RL1
(RL1)
04
05
R4
R5
RW4
RW5
RL2
(RL2)
06
07
R6
R7
RW6
RW7
RL3
(RL3)
08
09
@RW0
@RW1
0A
0B
@RW2
@RW3
0C
0D
@RW0+
@RW1+
0E
0F
@RW2+
@RW3+
10
11
@RW0+disp8
@RW1+disp8
12
13
@RW2+disp8
@RW3+disp8
14
15
@RW4+disp8
@RW5+disp8
16
17
@RW6+disp8
@RW7+disp8
18
19
@RW0+disp16
@RW1+disp16
1A
1B
@RW2+disp16
@RW3+disp16
1C
1D
1E
1F
Address format
Byte count of
extended
address part (*1)
Register direct: Individual parts
correspond to the byte, word, and long
word types in order from the left.
-
Register indirect
0
Register indirect with post increment
0
Register indirect with 8-bit displacement
1
Register indirect with 16-bit displacement
2
@RW0+RW7
@RW1+RW7
Register indirect with index
Register indirect with index
0
0
@PC+disp16
addr16
PC indirect with 16-bit displacement
Direct address
2
2
*1: Each byte count of the extended address part applies to + in the # (byte count) column in B.8
"F2MC-16LX Instruction List".
622
APPENDIX B Instructions
B.7
How to Read the Instruction List
Table B.7-1 "Description of items in the instruction list" describes the items used in
the F2MC-16LX Instruction List, and Table B.7-2 "Explanation on symbols in the
instruction list" describes the symbols used in the same list.
■ Description of instruction presentation items and symbols
Table B.7-1 Description of items in the instruction list
Item
Mnemonic
#
Description
Uppercase, symbol: Represented as is in the assembler.
Lowercase: Rewritten in the assembler.
Number of following lowercase: Indicates bit length in the instruction.
Indicates the number of bytes.
Indicates the number of cycles.
See Table B.2-1 "Effective address field" for the alphabetical letters in
items.
RG
B
Operation
Indicates the number of times a register access is performed during
instruction execution.
The number is used to calculate the correction value for CPU intermittent
operation.
Indicates the correction value used to calculate the actual number of
cycles during instruction execution.
The actual number of cycles during instruction execution can be
determined by adding the value in the
column to this value.
Indicates the instruction operation.
LH
Indicates the special operation for bits 15 to 08 of the accumulator.
Z: Transfers 0.
X: Transfers after sign extension.
-: No transfer
AH
Indicates the special operation for the 16 high-order bits of the
accumulator.
*: Transfers from AL to AH.
-: No transfer
Z: Transfers 00 to AH.
X: Transfers 00H or FFH to AH after AL sign extension.
623
APPENDIX B Instructions
Table B.7-1 Description of items in the instruction list (Continued)
Item
I
S
T
N
Description
Each indicates the state of each flag: I (interrupt enable), S (stack), T
(sticky bit), N (negative), Z (zero), V (overflow), C (carry).
*: Changes upon instruction execution.
-: No change
Z: Set upon instruction execution.
X: Reset upon instruction execution.
Z
V
C
RMW
Indicates whether the instruction is a Read Modify Write instruction
(reading data from memory by the I instruction and writing the result to
memory).
*: Read Modify Write instruction
-: Not Read Modify Write instruction
Note:
Cannot be used for an address that has different meanings between
read and write operations.
Table B.7-2 Explanation on symbols in the instruction list
Symbol
A
624
Explanation
The bit length used varies depending on the 32-bit accumulator
instruction.
Byte: Low-order 8 bits of byte AL
Word: 16 bits of word AL
Long word: 32 bits of AL and AH
AH
16 high-order bits of A
AL
16 low-order bits of A
SP
Stack pointer (USP or SSP)
PC
Program counter
PCB
Program bank register
DTB
Data bank register
ADB
Additional data bank register
SSB
System stack bank register
USB
User stack bank register
SPB
Current stack bank register (SSB or USB)
DPR
Direct page register
brg1
DTB, ADB, SSB, USB, DPR, PCB, SPB
brg2
DTB, ADB, SSB, USB, DPR, SPB
APPENDIX B Instructions
Table B.7-2 Explanation on symbols in the instruction list (Continued)
Symbol
Ri
Explanation
R0, R1, R2, R3, R4, R5, R6, R7
RWi
RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7
RWj
RW0, RW1, RW2, RW3
RLi
RL0, RL1, RL2, RL3
dir
Abbreviated direct addressing
addr16
Direct addressing
addr24
Physical direct addressing
ad24 0-15
Bits 0 to 15 of addr24
ad24 16-23
Bits 16 to 23 of addr24
io
I/O area (000000H to 0000FFH)
#imm4
4-bit immediate data
#imm8
8-bit immediate data
#imm16
16-bit immediate data
#imm32
32-bit immediate data
ext (imm8)
16-bit data obtained by sign extension of 8-bit immediate data
disp8
8-bit displacement
disp16
16-bit displacement
bp
Bit offset
vct4
Vector number (0 to 15)
vct8
Vector number (0 to 255)
( )b
Bit address
rel
PC relative branch
ear
Effective addressing (code 00 to 07)
eam
Effective addressing (code 08 to 1F)
rlst
Register list
625
APPENDIX B Instructions
B.8
F2MC-16LX Instruction List
Table B.8-1 "41 Transfer instructions (byte)" to Table B.9-19 "MOVW ea, Rwi instruction
(first byte = 7DH)" list the instructions used by the F2MC-16LX.
■ F2MC-16LX Instruction List
Table B.8-1 41 Transfer instructions (byte)
Mnemonic
#
MOV A,dir
MOV A,addr16
MOV A,Ri
MOV A,ear
MOV A,eam
MOV A,io
MOV A,#imm8
MOV A,@A
MOV A,@RLi+disp8
MOVN A,#imm4
MOVX A,dir
MOVX A,addr16
MOVX A,Ri
MOVX A,ear
MOVX A,eam
MOVX A,io
MOVX A,#imm8
MOVX A,@A
MOVX A,@RWi+disp8
MOVX A,@RLi+disp8
MOV dir,A
MOV addr16,A
MOV Ri,A
MOV ear,A
MOV eam,A
MOV io,A
MOV @RLi+disp8,A
MOV Ri,ear
MOV Ri,eam
MOV ear,Ri
MOV eam,Ri
MOV Ri,#imm8
MOV io,#imm8
MOV dir,#imm8
MOV ear,#imm8
MOV eam,#imm8
MOV @AL,AH / MOV @A,T
XCH A,ear
XCH A,eam
XCH Ri,ear
XCH Ri,eam
2
3
1
2
2+
2
2
2
3
1
2
3
2
2
2+
2
2
2
2
3
2
3
1
2
2+
2
3
2
2+
2
2+
2
3
3
3
3+
2
2
2+
2
2+
RG
3
4
2
2
3 + (a)
3
2
3
10
1
3
4
2
2
3 + (a)
3
2
3
5
10
3
4
2
2
3 + (a)
3
10
3
4 + (a)
4
5 + (a)
2
5
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
0
0
1
1
0
0
0
0
2
0
0
0
1
1
0
0
0
0
1
2
0
0
1
1
0
0
2
2
1
2
1
1
0
0
1
0
0
2
0
4
2
B
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
0
(b)
(b)
0
0
(b)
(b)
0
(b)
(b)
(b)
(b)
(b)
0
0
(b)
(b)
(b)
0
(b)
0
(b)
0
(b)
(b)
0
(b)
(b)
0
2 x (b)
0
2 x (b)
Operation
byte (A) <-- (dir)
byte (A) <-- (addr16)
byte (A) <-- (Ri)
byte (A) <-- (ear)
byte (A) <-- (eam)
byte (A) <-- (io)
byte (A) <-- imm8
byte (A) <-- ((A))
byte (A) <-- ((RLi)+disp8)
byte (A) <-- imm4
byte (A) <-- (dir)
byte (A) <-- (addr16)
byte (A) <-- (Ri)
byte (A) <-- (ear)
byte (A) <-- (eam)
byte (A) <-- (io)
byte (A) <-- imm8
byte (A) <-- ((A))
byte (A) <-- ((RWi)+disp8)
byte (A) <-- ((RLi)+disp8
byte (dir) <-- (A)
byte (addr16) <-- (A)
byte (Ri) <-- (A)
byte (ear) <-- (A)
byte (eam) <-- (A)
byte (io) <-- (A)
byte ((RLi)+disp8) <-- (A)
byte (Ri) <-- (ear)
byte (Ri) <-- (eam)
byte (ear) <-- (Ri)
byte (eam) <-- (Ri)
byte (Ri) <-- imm8
byte (io) <-- imm8
byte (dir) <-- imm8
byte (ear) <-- imm8
byte (eam) <-- imm8
byte ((A)) <-- (AH)
byte (A) <--> (ear)
byte (A) <--> (eam)
byte (Ri) <--> (ear)
byte (Ri) <--> (eam)
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
X
X
X
X
X
X
X
X
X
X
Z
Z
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
*
*
*
*
*
*
*
*
*
R
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
626
APPENDIX B Instructions
Table B.8-2 38 Transfer instructions (byte)
Mnemonic
#
MOVW A,dir
MOVW A,addr16
MOVW A,SP
MOVW A,RWi
MOVW A,ear
MOVW A,eam
MOVW A,io
MOVW A,@A
MOVW A,#imm16
MOVW A,@RWi+disp8
MOVW A,@RLi+disp8
MOVW dir,A
MOVW addr16,A
MOVW SP,A
MOVW RWi,A
MOVW ear,A
MOVW eam,A
MOVW io,A
MOVW @RWi+disp8,A
MOVW @RLi+disp8,A
MOVW RWi,ear
MOVW
MOVW ear,Rwi
MOVW eam,Rwi
MOVW RWi,#imm16
MOVW io,#imm16
MOVW ear,#imm16
MOVW eam,#imm16
MOVW @AL,AH / MOVW @A,T
XCHW A,ear
XCHW A,eam
XCHW RWi, ear
XCHW RWi, eam
MOVL A,ear
MOVL A,eam
MOVL A,#imm32
MOVL ear,A
MOVL eam,A
2
3
3
1
2
2+
2
2
3
2
3
2
3
1
1
2
2+
2
2
3
2
2+
2
2+
3
4
4
4+
2
2
2+
2
2+
2
2+
5
2
2+
RG
3
4
1
2
2
3 + (a)
3
3
2
5
10
3
4
1
2
2
3 + (a)
3
5
10
3
4 + (a)
4
5 + (a)
2
5
2
4 + (a)
3
4
5 + (a)
7
9 + (a)
4
5 + (a)
3
4
5 + (a)
0
0
0
1
1
0
0
0
2
1
2
0
0
0
1
1
0
0
1
2
2
1
2
1
1
0
1
0
0
2
0
4
2
2
0
0
2
0
B
(c)
(c)
0
0
0
(c)
(c)
(c)
0
(c)
(c)
(c)
(c)
0
0
0
(c)
(c)
(c)
(c)
0
(c)
0
(c)
0
(c)
0
(c)
(c)
0
2 x (c)
0
2 x (c)
0
(d)
0
0
(d)
Operation
word (A) <-- (dir)
word (A) <-- (addr16)
word (A) <-- (SP)
word (A) <-- (RWi)
word (A) <-- (ear)
word (A) <-- (eam)
word (A) <-- (io)
word (A) <-- ((A))
word (A) <-- imm16
word (A) <-- ((RWi)+disp8)
word (A) <-- ((RLi)+disp8)
word (dir) <-- (A)
word (addr16) <-- (A)
word (SP) <-- (A)
word (RWi) <-- (A)
word (ear) <-- (A)
word (eam) <-- (A)
word (io) <-- (A)
word ((RWi)+disp8) <-- (A)
word ((RLi)+disp8) <-- (A)
word (RWi) <-- (ear)
word (RWi) <-- (eam)
word (ear) <-- (RWi)
word (eam) <-- (RWi)
word (RWi) <-- imm16
word (io) <-- imm16
word (ear) <-- imm16
word (eam) <-- imm16
word ((A)) <-- (AH)
word (A) <--> (ear)
word (A) <-- >(eam)
word (RWi) <--> (ear)
word (RWi) <--> (eam)
long (A) <-- (ear)
long (A) <-- (eam)
long (A) <-- imm32
long (ear1) <-- (A)
long(eam1) <-- (A)
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
-
*
*
*
*
*
*
*
*
*
*
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
627
APPENDIX B Instructions
Table B.8-3 42 Addition/subtraction instructions (byte, word, long word)
Mnemonic
#
RG
B
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 x (b)
0
0
(b)
0
SUB
SUB
SUB
SUB
SUB
SUB
SUBC
SUBC
SUBC
SUBDC
A,#imm8
A,dir
A,ear
A,eam
ear,A
eam,A
A
A,ear
A,eam
A
2
2
2
2+
2
2+
1
2
2+
1
2
5
3
4 + (a)
3
5 + (a)
2
3
4 + (a)
3
0
0
1
0
2
0
0
1
0
0
0
(b)
0
(b)
0
2 x (b)
0
0
(b)
0
ADDW
ADDW
ADDW
ADDW
ADDW
ADDW
ADDCW
ADDCW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBW
SUBCW
SUBCW
ADDL
ADDL
ADDL
SUBL
SUBL
SUBL
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A
A,ear
A,eam
A,#imm16
ear,A
eam,A
A,ear
A,eam
A,ear
A,eam
A,#imm32
A,ear
A,eam
A,#imm32
1
2
2+
3
2
2+
2
2+
1
2
2+
3
2
2+
2
2+
2
2+
5
2
2+
5
2
3
4+(a)
2
3
5+(a)
3
4+(a)
2
3
4+(a)
2
3
5+(a)
3
4+(a)
6
7+(a)
4
6
7+(a)
4
0
1
0
0
2
0
1
0
0
1
0
0
2
0
1
0
2
0
0
2
0
0
0
0
(c)
0
0
2 x (c)
0
(c)
0
0
(c)
0
0
2 x (c)
0
(c)
0
(d)
0
0
(d)
0
Operation
byte (A) <-- (A) + imm8
byte (A) <-- (A) + (dir)
byte (A) <-- (A) + (ear)
byte (A) <-- (A) + (eam)
byte (ear) <-- (ear) + (A)
byte (eam) <-- (eam) + (A)
byte (A) <-- (AH) + (AL) + (C)
byte (A) <-- (A) + (ear)+ (C)
byte (A) <-- (A) + (eam)+ (C)
byte (A) <-- (AH) + (AL) + (C)
(decimal)
byte (A) <-- (A) - imm8
byte (A) <-- (A) - (dir)
byte (A) <-- (A) - (ear)
byte (A) <-- (A) - (eam)
byte (ear) <-- (ear) - (A)
byte (eam) <-- (eam) - (A)
byte (A) <-- (AH) - (AL) - (C)
byte (A) <-- (A) - (ear) - (C)
byte (A) <-- (A) - (eam) - (C)
byte (A) <-- (AH) - (AL) - (C)
(decimal)
word (A) <-- (AH) + (AL)
word (A) <-- (A) + (ear)
word (A) <-- (A) + (eam)
word (A) <-- (A) + imm16
word (ear) <-- (ear) + (A)
word (eam) <-- (eam) + (A)
word (A) <-- (A) + (ear) + (C)
word (A) <-- (A) + (eam) + (C)
word (A) <-- (AH) - (AL)
word (A) <-- (A) - (ear)
word (A) <-- (A) - (eam)
word (A) <-- (A) - imm16
word (ear) <-- (ear) - (A)
word (eam) <-- (eam) - (A)
word (A) <-- (A) - (ear) - (C)
word (A) <-- (A) - (eam) - (C)
long (A) <-- (A) + (ear)
long (A) <-- (A) + (eam)
long (A) <-- (A) + imm32
long (A) <-- (A) - (ear)
long (A) <-- (A) - (eam)
long (A) <-- (A) - imm32
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
Z
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Z
Z
Z
Z
Z
Z
Z
Z
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
-
-
-
-
-
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
-
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
628
APPENDIX B Instructions
Table B.8-4 12 Increment/decrement instructions (byte, word, long word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
INC
ear
2
3
2
0
byte (ear) <-- (ear) + 1
-
-
-
-
-
*
*
*
-
-
INC
eam
2+
5+(a)
0
2 x (b)
byte (eam) <-- (eam) + 1
-
-
-
-
-
*
*
*
-
*
DEC
ear
2
3
2
0
byte (ear) <-- (ear) - 1
-
-
-
-
-
*
*
*
-
-
DEC
eam
2+
5+(a)
0
2 x (b)
byte (eam) <-- (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCW
ear
2
3
2
0
word (ear) <-- (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCW
eam
2+
5+(a)
0
2 x (c)
word (eam) <-- (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECW
ear
2
3
2
0
word (ear) <-- (ear) - 1
-
-
-
-
-
*
*
*
-
-
DECW
eam
2+
5+(a)
0
2 x (c)
word (eam) <-- (eam) - 1
-
-
-
-
-
*
*
*
-
*
INCL
ear
2
7
4
0
long (ear) <-- (ear) + 1
-
-
-
-
-
*
*
*
-
-
INCL
eam
2+
9+(a)
0
2 x (d)
long (eam) <-- (eam) + 1
-
-
-
-
-
*
*
*
-
*
DECL
ear
2
7
4
0
long (ear) <-- (ear) - 1
-
-
-
-
-
*
*
*
-
-
DECL
eam
2+
9+(a)
0
2 x (d)
long (eam) <-- (eam) - 1
-
-
-
-
-
*
*
*
-
*
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
Table B.8-5 11 Compare instructions (byte, word, long word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
CMP
A
1
1
0
0
byte (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMP
A,ear
2
2
1
0
byte (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMP
A,eam
2+
3+(a)
0
(b)
byte (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMP
A,#imm8
2
2
0
0
byte (A) - imm8
-
-
-
-
-
*
*
*
*
-
CMPW
A
1
1
0
0
word (AH) - (AL)
-
-
-
-
-
*
*
*
*
-
CMPW
A,ear
2
2
1
0
word (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPW
A,eam
2+
3+(a)
0
(c)
word (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPW
A,#imm16
3
2
0
0
word (A) - imm16
-
-
-
-
-
*
*
*
*
-
CMPL
A,ear
2
6
2
0
long (A) - (ear)
-
-
-
-
-
*
*
*
*
-
CMPL
A,eam
2+
7+(a)
0
(d)
long (A) - (eam)
-
-
-
-
-
*
*
*
*
-
CMPL
A,#imm32
5
3
0
0
long (A) - imm32
-
-
-
-
-
*
*
*
*
-
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
629
APPENDIX B Instructions
Table B.8-6 11 Unsigned multiplication/division instructions (word, long word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
DIVU
A
1
*1
0
0
word (AH) / byte (AL)
quotient --> byte (AL) remainder --> byte (AH)
-
-
-
-
-
-
-
*
*
-
DIVU
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient --> byte (A) remainder --> byte (ear)
-
-
-
-
-
-
-
*
*
-
DIVU
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient --> byte (A) remainder --> byte (eam)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient --> word (A) remainder --> word (ear)
-
-
-
-
-
-
-
*
*
-
DIVUW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient --> word (A) remainder --> word (eam)
-
-
-
-
-
-
-
*
*
-
MULU
A
1
*8
0
0
byte (AH) * byte (AL) --> word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,ear
2
*9
1
0
byte (A) * byte (ear) --> word (A)
-
-
-
-
-
-
-
-
-
-
MULU
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) --> word (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A
1
*11
0
0
word (AH) * word (AL) --> Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,ear
2
*12
1
0
word (A) * word (ear) --> Long (A)
-
-
-
-
-
-
-
-
-
-
MULUW
A,eam
2+
*13
0
(c)
word (A) * word (eam) --> Long (A)
-
-
-
-
-
-
-
-
-
-
*1: 3: Division by 0 7: Overflow 15: Normal
*2: 4: Division by 0 8: Overflow 16: Normal
*3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal
*4: 4: Division by 0 7: Overflow 22: Normal
*5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal
*6: (b): Division by 0 or overflow 2 x (b): Normal
*7: (c): Division by 0 or overflow 2 x (c): Normal
*8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0.
*9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0.
*10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0.
*11: 3: Word (AH) is 0. 11: Word (AH) is not 0.
*12: 4: Word (ear) is 0. 12: Word (ear) is not 0.
*13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0.
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
630
APPENDIX B Instructions
Table B.8-7 11 Signed multiplication/division instructions (word, long word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
DIV
A
2
*1
0
0
word (AH) / byte (AL)
quotient --> byte (AL) remainder --> byte (AH)
Z
-
-
-
-
-
-
*
*
-
DIV
A,ear
2
*2
1
0
word (A) / byte (ear)
quotient --> byte (A) remainder --> byte (ear)
Z
-
-
-
-
-
-
*
*
-
DIV
A,eam
2+
*3
0
*6
word (A) / byte (eam)
quotient --> byte (A) remainder --> byte (eam)
Z
-
-
-
-
-
-
*
*
-
DIVW
A,ear
2
*4
1
0
long (A) / word (ear)
quotient --> word (A) remainder --> word (ear)
-
-
-
-
-
-
-
*
*
-
DIVW
A,eam
2+
*5
0
*7
long (A) / word (eam)
quotient --> word (A) remainder --> word (eam)
-
-
-
-
-
-
-
*
*
-
MUL
A
2
*8
0
0
byte (AH) * byte (AL) --> word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,ear
2
*9
1
0
byte (A) * byte (ear) --> word (A)
-
-
-
-
-
-
-
-
-
-
MUL
A,eam
2+
*10
0
(b)
byte (A) * byte (eam) --> word (A)
-
-
-
-
-
-
-
-
-
-
MULW
A
2
*11
0
0
word (AH) * word (AL) --> Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,ear
2
*12
1
0
word (A) * word (ear) --> Long (A)
-
-
-
-
-
-
-
-
-
-
MULW
A,eam
2+
*13
0
(c)
word (A) * word (eam) --> Long (A)
-
-
-
-
-
-
-
-
-
-
*1:
*2:
*3:
*4:
3: Division by 0, 8 or 18: Overflow, 18: Normal
4: Division by 0, 11 or 22: Overflow, 23: Normal
5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal
When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal
When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal
*5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal
When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal
*6: (b): Division by 0 or overflow, 2 x (b): Normal
*7: (c): Division by 0 or overflow, 2 x (c): Normal
*8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative
*9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative
*10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative
*11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative
*12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative
*13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative
Notes:
•
The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may
be a pre-operation count or a post-operation count depending on the detection timing.
•
When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed.
•
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
631
APPENDIX B Instructions
Table B.8-8 39 Logic 1 instructions (byte, word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
AND
A,#imm8
2
2
0
0
byte (A) <-- (A) and imm8
-
-
-
-
-
*
*
R
-
-
AND
A,ear
2
3
1
0
byte (A) <-- (A) and (ear)
-
-
-
-
-
*
*
R
-
-
AND
A,eam
2+
4+(a)
0
(b)
byte (A) <-- (A) and (eam)
-
-
-
-
-
*
*
R
-
-
AND
ear,A
2
3
2
0
byte (ear) <-- (ear) and (A)
-
-
-
-
-
*
*
R
-
-
AND
eam,A
2+
5+(a)
0
2 x (b)
byte (eam) <-- (eam) and (A)
-
-
-
-
-
*
*
R
-
*
OR
A,#imm8
2
2
0
0
byte (A) <-- (A) or imm8
-
-
-
-
-
*
*
R
-
-
OR
A,ear
2
3
1
0
byte (A) <-- (A) or (ear)
-
-
-
-
-
*
*
R
-
-
OR
A,eam
2+
4+(a)
0
(b)
byte (A) <-- (A) or (eam)
-
-
-
-
-
*
*
R
-
-
OR
ear,A
2
3
2
0
byte (ear) <-- (ear) or (A)
-
-
-
-
-
*
*
R
-
-
OR
eam,A
2+
5+(a)
0
2 x (b)
byte (eam) <-- (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XOR
A,#imm8
2
2
0
0
byte (A) <-- (A) xor imm8
-
-
-
-
-
*
*
R
-
-
XOR
A,ear
2
3
1
0
byte (A) <-- (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XOR
A,eam
2+
4+(a)
0
(b)
byte (A) <-- (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XOR
ear,A
2
3
2
0
byte (ear) <-- (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XOR
eam,A
2+
5+(a)
0
2 x (b)
byte (eam) <-- (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOT
A
1
2
0
0
byte (A) <-- not (A)
-
-
-
-
-
*
*
R
-
-
NOT
ear
2
3
2
0
byte (ear) <-- not (ear)
-
-
-
-
-
*
*
R
-
-
NOT
eam
2+
5+(a)
0
2 x (b)
byte (eam) <-- not (eam)
-
-
-
-
-
*
*
R
-
*
ANDW
A
1
2
0
0
word (A) <-- (AH) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
A,#imm16
3
2
0
0
word (A) <-- (A) and imm16
-
-
-
-
-
*
*
R
-
-
ANDW
A,ear
2
3
1
0
word (A) <-- (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDW
A,eam
2+
4+(a)
0
(c)
word (A) <-- (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ANDW
ear,A
2
3
2
0
word (ear) <-- (ear) and (A)
-
-
-
-
-
*
*
R
-
-
ANDW
eam,A
2+
5+(a)
0
2 x (c)
word (eam) <-- (eam) and (A)
-
-
-
-
-
*
*
R
-
*
ORW
A
1
2
0
0
word (A) <-- (AH) or (A)
-
-
-
-
-
*
*
R
-
-
ORW
A,#imm16
3
2
0
0
word (A) <-- (A) or imm16
-
-
-
-
-
*
*
R
-
-
ORW
A,ear
2
3
1
0
word (A) <-- (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORW
A,eam
2+
4+(a)
0
(c)
word (A) <-- (A) or (eam)
-
-
-
-
-
*
*
R
-
-
ORW
ear,A
2
3
2
0
word (ear) <-- (ear) or (A)
-
-
-
-
-
*
*
R
-
-
ORW
eam,A
2+
5+(a)
0
2 x (c)
word (eam) <-- (eam) or (A)
-
-
-
-
-
*
*
R
-
*
XORW
A
1
2
0
0
word (A) <-- (AH) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
A,#imm16
3
2
0
0
word (A) <-- (A) xor imm16
-
-
-
-
-
*
*
R
-
-
XORW
A,ear
2
3
1
0
word (A) <-- (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORW
A,eam
2+
4+(a)
0
(c)
word (A) <-- (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
XORW
ear,A
2
3
2
0
word (ear) <-- (ear) xor (A)
-
-
-
-
-
*
*
R
-
-
XORW
eam,A
2+
5+(a)
0
2 x (c)
word (eam) <-- (eam) xor (A)
-
-
-
-
-
*
*
R
-
*
NOTW
A
1
2
0
0
word (A) <-- not (A)
-
-
-
-
-
*
*
R
-
-
NOTW
ear
2
3
2
0
word (ear) <-- not (ear)
-
-
-
-
-
*
*
R
-
-
NOTW
eam
2+
5+(a)
0
2 x (c)
word (eam) <-- not (eam)
-
-
-
-
-
*
*
R
-
*
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
632
APPENDIX B Instructions
Table B.8-9 6 Logic 2 instructions (long word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
ANDL
A,ear
2
6
2
0
long (A) <-- (A) and (ear)
-
-
-
-
-
*
*
R
-
-
ANDL
A,eam
2+
7+(a)
0
(d)
long (A) <-- (A) and (eam)
-
-
-
-
-
*
*
R
-
-
ORL
A,ear
2
6
2
0
long (A) <-- (A) or (ear)
-
-
-
-
-
*
*
R
-
-
ORL
A,eam
2+
7+(a)
0
(d)
long (A) <-- (A) or (eam)
-
-
-
-
-
*
*
R
-
-
XORL
A,ear
2
6
2
0
long (A) <-- (A) xor (ear)
-
-
-
-
-
*
*
R
-
-
XORL
A,eam
2+
7+(a)
0
(d)
long (A) <-- (A) xor (eam)
-
-
-
-
-
*
*
R
-
-
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
Table B.8-10 6 Sign inversion instructions (byte, word)
Mnemonic
NEG
A
NEG
NEG
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
1
2
0
0
byte (A) <-- 0 - (A)
X
-
-
-
-
*
*
*
*
-
ear
2
3
2
0
byte (ear) <-- 0 - (ear)
-
-
-
-
-
*
*
*
*
-
eam
2+
5+(a)
0
2 x (b)
byte (eam) <-- 0 - (eam)
-
-
-
-
-
*
*
*
*
*
NEGW
A
1
2
0
0
word (A) <-- 0 - (A)
-
-
-
-
-
*
*
*
*
-
NEGW
ear
2
3
2
0
word (ear) <-- 0 - (ear)
-
-
-
-
-
*
*
*
*
-
NEGW
eam
2+
5+(a)
0
2 x (c)
word (eam) <-- 0 - (eam)
-
-
-
-
-
*
*
*
*
*
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
Table B.8-11 1 Normalization instruction (long word)
NRML
Mnemonic
#
A,R0
2
*1
RG
B
1
0
Operation
long (A) <-- Shifts to the position where '1' is
set for the first time.
byte (RD) <-- Shift count at that time
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
-
-
-
-
-
-
*
-
-
-
*1: 4 when all accumulators have a value of 0; otherwise, 6+(R0)
633
APPENDIX B Instructions
Table B.8-12 18 Shift instructions (byte, word, long word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
RORC
A
2
2
0
0
byte (A) <-- With right rotation carry
-
-
-
-
-
*
*
-
*
-
ROLC
A
2
2
0
0
byte (A) <-- With left rotation carry
-
-
-
-
-
*
*
-
*
-
RORC
ear
2
3
2
0
byte (ear) <-- With right rotation carry
-
-
-
-
-
*
*
-
*
-
RORC
eam
2+
5+(a)
0
2 x (b)
byte (eam) <-- With right rotation carry
-
-
-
-
-
*
*
-
*
*
ROLC
ear
2
3
2
0
byte (ear) <-- With left rotation carry
-
-
-
-
-
*
*
-
*
-
ROLC
eam
2+
5+(a)
0
2 x (b)
byte (eam) <-- With left rotation carry
-
-
-
-
-
*
*
-
*
*
ASR
A,R0
2
*1
1
0
byte (A) <-- Arithmetic right shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
LSR
A,R0
2
*1
1
0
byte (A) <-- Logical right barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
LSL
A,R0
2
*1
1
0
byte (A) <-- Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRW
A
1
2
0
0
word (A) <-- Arithmetic right shift (A, 1 bit)
-
-
-
-
*
*
*
-
*
-
LSRW
A/SHRW A
1
2
0
0
word (A) <-- Logical right shift (A, 1 bit)
-
-
-
-
*
R
*
-
*
-
LSLW
A/SHLW A
1
2
0
0
word (A) <-- Logical left shift (A, 1 bit)
-
-
-
-
-
*
*
-
*
-
ASRW
A,R0
2
*1
1
0
word (A) <-- Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRW
A,R0
2
*1
1
0
word (A) <-- Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLW
A,R0
2
*1
1
0
word (A) <-- Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
ASRL
A,R0
2
*2
1
0
long (A) <-- Arithmetic right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSRL
A,R0
2
*2
1
0
long (A) <-- Logical right barrel shift (A, R0)
-
-
-
-
*
*
*
-
*
-
LSLL
A,R0
2
*2
1
0
long (A) <-- Logical left barrel shift (A, R0)
-
-
-
-
-
*
*
-
*
-
*1: 6 when R0 is 0; otherwise, 5 + (R0)
*2: 6 when R0 is 0; otherwise, 6 + (R0)
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
634
APPENDIX B Instructions
Table B.8-13 31 Branch 1 instructions
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
BZ/BEQ
rel
2
*1
0
0
Branch on (Z) = 1
-
-
-
-
-
-
-
-
-
-
BNZ/BNE
rel
2
*1
0
0
Branch on (Z) = 0
-
-
-
-
-
-
-
-
-
-
BC/BLO
rel
2
*1
0
0
Branch on (C) = 1
-
-
-
-
-
-
-
-
-
-
BNC/BHS
rel
2
*1
0
0
Branch on (C) = 0
-
-
-
-
-
-
-
-
-
-
BN
rel
2
*1
0
0
Branch on (N) = 1
-
-
-
-
-
-
-
-
-
-
BP
rel
2
*1
0
0
Branch on (N) = 0
-
-
-
-
-
-
-
-
-
-
BV
rel
2
*1
0
0
Branch on (V) = 1
-
-
-
-
-
-
-
-
-
-
BNV
rel
2
*1
0
0
Branch on (V) = 0
-
-
-
-
-
-
-
-
-
-
BT
rel
2
*1
0
0
Branch on (T) = 1
-
-
-
-
-
-
-
-
-
-
BNT
rel
2
*1
0
0
Branch on (T) = 0
-
-
-
-
-
-
-
-
-
-
BLT
rel
2
*1
0
0
Branch on (V) nor (N) = 1
-
-
-
-
-
-
-
-
-
-
BGE
rel
2
*1
0
0
Branch on (V) nor (N) = 0
-
-
-
-
-
-
-
-
-
-
BLE
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BGT
rel
2
*1
0
0
Branch on ((V) xor (N)) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BLS
rel
2
*1
0
0
Branch on (C) or (Z) = 1
-
-
-
-
-
-
-
-
-
-
BHI
rel
2
*1
0
0
Branch on (C) or (Z) = 0
-
-
-
-
-
-
-
-
-
-
BRA
rel
2
*1
0
0
Unconditional branch
-
-
-
-
-
-
-
-
-
-
JMP
@A
1
2
0
0
word (PC) <-- (A)
-
-
-
-
-
-
-
-
-
-
JMP
addr16
3
3
0
0
word (PC) <-- addr16
-
-
-
-
-
-
-
-
-
-
JMP
@ear
2
3
1
0
word (PC) <-- (ear)
-
-
-
-
-
-
-
-
-
-
JMP
@eam
2+
4+(a)
0
(c)
word (PC) <-- (eam)
-
-
-
-
-
-
-
-
-
-
JMPP
@ear *3
2
5
2
0
word (PC) <-- (ear), (PCB) <-- (ear+2)
-
-
-
-
-
-
-
-
-
-
JMPP
@eam *3
2+
6+(a)
0
(d)
word (PC) <-- (eam), (PCB) <-- (eam+2)
-
-
-
-
-
-
-
-
-
-
JMPP
addr24
4
4
0
0
word (PC) <-- ad24 0-15, (PCB) <-- ad24 16-23
-
-
-
-
-
-
-
-
-
-
CALL
@ear *4
2
6
1
(c)
word (PC) <-- (ear)
CALL
addr16 *5
2+
7+(a)
0
2 x (c) word (PC) <-- (eam)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CALL
@eam *4
3
6
0
(c)
word (PC) <-- addr16
-
-
-
-
-
-
-
-
-
-
CALLV
#vct4 *5
1
7
0
2 x (c) Vector call instruction
-
-
-
-
-
-
-
-
-
-
CALLP
@ear *6
2
10
2
2 x (c) word (PC) <-- (ear)0-15, (PCB) <-- (ear)16-23
-
-
-
-
-
-
-
-
-
-
CALLP
@eam *6
2+
11+(a)
0
*2
-
-
-
-
-
-
-
-
-
-
CALLP
addr24 *7
4
10
0
2 x (c) word (PC) <-- addr0-15, (PCB) <-- addr16-23
word (PC) <-- (eam)0-15, (PCB) <-- (eam)16-23
-
-
-
-
-
-
-
-
-
-
*1: 4 when a branch is made; otherwise, 3
*2: 3 x (c) + (b)
*3: Read (word) of branch destination address
*4: W: Save to stack (word) R: Read (word) of branch destination address
*5: Save to stack (word)
*6: W: Save to stack (long word), R: Read (long word) of branch destination address
*7: Save to stack (long word)
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
635
APPENDIX B Instructions
Table B.8-14 19 Branch 2 instructions
Mnemonic
#
RG
B
Operation
L A
H H
I
S T N Z V C R
M
W
CBNE
A,#imm8,rel
3
*1
0
0
Branch on byte (A) not equal to imm8
-
-
-
-
-
*
*
*
*
CWBNE
A,#imm16,rel
4
*1
0
0
Branch on word (A) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CBNE
ear,#imm8,rel
4
*2
1
0
Branch on byte (ear) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CBNE
eam,#imm8,rel *9
4+
*3
0
(b)
Branch on byte (eam) not equal to imm8
-
-
-
-
-
*
*
*
*
-
CWBNE
ear,#imm16,rel
5
*4
1
0
Branch on word (ear) not equal to imm16
-
-
-
-
-
*
*
*
*
-
CWBNE
eam,#imm16,rel*9
5+
*3
0
(c)
Branch on word (eam) not equal to imm16
-
-
-
-
-
*
*
*
*
-
DBNZ
ear,rel
3
*5
2
0
Branch on byte (ear) = (ear) - 1, (ear) not equal to 0
-
-
-
-
-
*
*
*
-
-
DBNZ
eam,rel
3+
*6
2
2 x (b) Branch on byte (eam) = (eam) - 1, (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
DWBNZ
ear,rel
3
*5
2
0
-
-
-
-
-
*
*
*
-
-
DWBNZ
eam,rel
3+
*6
2
2 x (c) Branch on word (eam) = (eam) - 1, (eam) not equal to 0
-
-
-
-
-
*
*
*
-
*
INT
#vct8
2
20
0
8 x (c) Software interrupt
-
-
R S
-
-
-
-
-
-
INT
addr16
3
16
0
6 x (c) Software interrupt
-
-
R S
-
-
-
-
-
-
INTP
addr24
4
17
0
6 x (c) Software interrupt
-
-
R S
-
-
-
-
-
-
INT9
1
20
0
8 x (c) Software interrupt
-
-
R S
-
-
-
-
-
-
RETI
1
*8
0
*7
Return from interrupt
-
-
*
*
*
*
*
*
*
-
2
6
0
(c)
Saves the old frame pointer in the stack upon entering the
function, then sets the new frame pointer and reserves the
local pointer area.
-
-
-
-
-
-
-
-
-
-
1
5
0
(c)
Recovers the old frame pointer from the stack upon exiting the
function.
-
-
-
-
-
-
-
-
-
-
LINK
#imm8
UNLINK
Branch on word (ear) = (ear) - 1, (ear) not equal to 0
-
RET
*10
1
4
0
(c)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
RETP
*11
1
6
0
(d)
Return from subroutine
-
-
-
-
-
-
-
-
-
-
*1: 5 when a branch is made; otherwise, 4
*2: 13 when a branch is made; otherwise, 12
*3: 7+(a) when a branch is made; otherwise, 6+(a)
*4: 8 when a branch is made; otherwise, 7
*5: 7 when a branch is made; otherwise, 6
*6: 8+(a) when a branch is made; otherwise, 7+(a)
*7: 3 x (b) + 2 x (c) when jumping to the next interruption request; 6 x (c) when returning from the current interruption
*8: 15 when jumping to the next interruption request; 17 when returning from the current interruption
*9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction.
*10: Return from stack (word)
*11: Return from stack (long word)
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
636
APPENDIX B Instructions
Table B.8-15 28 Other control instructions (byte, word, long word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
PUSHW
A
1
4
0
(c)
word (SP) <-- (SP) - 2, ((SP)) <-- (A)
-
-
-
-
-
-
-
-
-
-
PUSHW
AH
1
4
0
(c)
word (SP) <-- (SP) - 2, ((SP)) <-- (AH)
-
-
-
-
-
-
-
-
-
-
PUSHW
PS
1
4
0
(c)
word (SP) <-- (SP) - 2, ((SP)) <-- (PS)
-
-
-
-
-
-
-
-
-
-
PUSHW
rlst
2
*3
*5
*4
(SP) <-- (SP) - 2n, ((SP)) <-- (rlst)
-
-
-
-
-
-
-
-
-
-
POPW
A
1
3
0
(c)
word (A) <-- ((SP)), (SP) <-- (SP) + 2
-
*
-
-
-
-
-
-
-
-
POPW
AH
1
3
0
(c)
word (AH) <-- ((SP)), (SP) <-- (SP) + 2
-
-
-
-
-
-
-
-
-
-
POPW
PS
1
4
0
(c)
word (PS) <-- ((SP)), (SP) <-- (SP) + 2
-
-
*
*
*
*
*
*
*
-
POPW
rlst
2
*2
*5
*4
(rlst) <-- ((SP)), (SP) <-- (SP)
-
-
-
-
-
-
-
-
-
-
JCTX
@A
1
14
0
6 x (c)
Context switch instruction
-
-
*
*
*
*
*
*
*
-
AND
CCR,#imm8
2
3
0
0
byte (CCR) <-- (CCR) and imm8
-
-
*
*
*
*
*
*
*
-
OR
CCR,#imm8
2
3
0
0
byte (CCR) <-- (CCR) or imm8
-
-
*
*
*
*
*
*
*
-
MOV
RP,#imm8
2
2
0
0
byte (RP) <-- imm8
-
-
-
-
-
-
-
-
-
-
MOV
ILM,#imm8
2
2
0
0
byte (ILM) <-- imm8
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,ear
2
3
1
0
word (RWi) <-- ear
-
-
-
-
-
-
-
-
-
-
MOVEA
RWi,eam
2+
2+(a)
1
0
word (RWi) <-- eam
-
-
-
-
-
-
-
-
-
-
MOVEA
A,ear
2
1
0
0
word (A) <-- ear
-
*
-
-
-
-
-
-
-
-
MOVEA
A,eam
2+
1+(a)
0
0
word (A) <-- eam
-
*
-
-
-
-
-
-
-
-
ADDSP
#imm8
2
3
0
0
word (SP) <-- ext(imm8)
-
-
-
-
-
-
-
-
-
-
ADDSP
#imm16
3
3
0
0
word (SP) <-- imm16
-
-
-
-
-
-
-
-
-
-
MOV
A,brg1
2
*1
0
0
byte (A) <-- (brg1)
Z
*
-
-
-
*
*
-
-
-
MOV
brg2,A
2
1
0
0
byte (brg2) <-- (A)
-
-
-
-
-
*
*
-
-
-
NOP
1
1
0
0
No operation
-
-
-
-
-
-
-
-
-
-
ADB
1
1
0
0
Prefix code for AD space access
-
-
-
-
-
-
-
-
-
-
DTB
1
1
0
0
Prefix code for DT space access
-
-
-
-
-
-
-
-
-
-
PCB
1
1
0
0
Prefix code for PC space access
-
-
-
-
-
-
-
-
-
-
SPB
1
1
0
0
Prefix code for SP space access
-
-
-
-
-
-
-
-
-
-
NCC
1
1
0
0
Prefix code for flag no-change
-
-
-
-
-
-
-
-
-
-
CMR
1
1
0
0
Prefix code for common register bank
-
-
-
-
-
-
-
-
-
-
*1: PCB, ADB, SSB, USB, SPB: 1
DTB, DPR: 2
*2: 7 + 3 x (POP count) + 2 x (POP last register number), 7 when RLST = 0 (no transfer register)
*3: 29 + 3 x (PUSH count) - 3 x (PUSH last register number), 8 when RLST = 0 (no transfer register)
*4: (POP count) x (c) or (PUSH count) x (c)
*5: (POP count) or (PUSH count)
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
637
APPENDIX B Instructions
Table B.8-16 21 Bit operand instructions
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
MOVB
A,dir:bp
3
5
0
(b)
byte (A) <-- (dir:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,addr16:bp
4
5
0
(b)
byte (A) <-- (addr16:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
A,io:bp
3
4
0
(b)
byte (A) <-- (io:bp)b
Z
*
-
-
-
*
*
-
-
-
MOVB
dir:bp,A
3
7
0
2 x (b)
bit (dir:bp)b <-- (A)
-
-
-
-
-
*
*
-
-
*
MOVB
addr16:bp,A
4
7
0
2 x (b)
bit (addr16:bp)b <-- (A)
-
-
-
-
-
*
*
-
-
*
MOVB
io:bp,A
3
6
0
2 x (b)
bit (io:bp)b <-- (A)
-
-
-
-
-
*
*
-
-
*
SETB
dir:bp
3
7
0
2 x (b)
bit (dir:bp)b <-- 1
-
-
-
-
-
-
-
-
-
*
SETB
addr16:bp
4
7
0
2 x (b)
bit (addr16:bp)b <-- 1
-
-
-
-
-
-
-
-
-
*
SETB
io:bp
3
7
0
2 x (b)
bit (io:bp)b <-- 1
-
-
-
-
-
-
-
-
-
*
CLRB
dir:bp
3
7
0
2 x (b)
bit (dir:bp)b <-- 0
-
-
-
-
-
-
-
-
-
*
CLRB
addr16:bp
4
7
0
2 x (b)
bit (addr16:bp)b <-- 0
-
-
-
-
-
-
-
-
-
*
CLRB
io:bp
3
7
0
2 x (b)
bit (io:bp)b <-- 0
-
-
-
-
-
-
-
-
-
*
BBC
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBC
io:bp,rel
4
*2
0
(b)
Branch on (io:bp) b = 0
-
-
-
-
-
-
*
-
-
-
BBS
dir:bp,rel
4
*1
0
(b)
Branch on (dir:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
addr16:bp,rel
5
*1
0
(b)
Branch on (addr16:bp) b = 1
-
-
-
-
-
-
*
-
-
-
BBS
io:bp,rel
4
*1
0
(b)
Branch on (io:bp) b = 1
-
-
-
-
-
-
*
-
-
-
SBBS
addr16:bp,rel
5
*3
0
2 x (b)
Branch on (addr16:bp) b = 1, bit = 1
-
-
-
-
-
-
*
-
-
*
WBTS
io:bp
3
*4
0
*5
Waits until (io:bp) b = 1
-
-
-
-
-
-
-
-
-
-
WBTC
io:bp
3
*4
0
*5
Waits until (io:bp) b = 0
-
-
-
-
-
-
-
-
-
-
*1: 8 when a branch is made; otherwise, 7
*2: 7 when a branch is made; otherwise, 6
*3: 10 when the condition is met; otherwise, 9
*4: Undefined count
*5: Until the condition is met
Note:
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
Table B.8-17 6 Accumulator operation instructions (byte, word)
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
SWAP
1
3
0
0
byte (A)0-7 <--> (A)8-15
-
-
-
-
-
-
-
-
-
-
SWAPW / XCHW A,T
1
2
0
0
word (AH) <--> (AL)
-
*
-
-
-
-
-
-
-
-
EXT
1
1
0
0
Byte sign extension
X
-
-
-
-
*
*
-
-
-
EXTW
1
2
0
0
Word sign extension
-
X
-
-
-
*
*
-
-
-
ZEXT
1
1
0
0
Byte zero extension
Z
-
-
-
-
R
*
-
-
-
ZEXTW
1
1
0
0
Word zero extension
-
z
-
-
-
R
*
-
-
-
638
APPENDIX B Instructions
Table B.8-18 10 String instructions
Mnemonic
#
RG
B
Operation
L
H
A
H
I
S
T
N
Z
V
C
R
M
W
MOVS / MOVSI
2
*2
*5
*3
byte transfer @AH+ <-- @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSD
2
*2
*5
*3
byte transfer @AH- <-- @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCEQ / SCEQI
2
*1
*5
*4
byte search @AH+ <-- AL, counter RW0
-
-
-
-
-
*
*
*
*
-
SCEQD
2
*1
*5
*4
byte search @AH- <-- AL, counter RW0
-
-
-
-
-
*
*
*
*
-
FILS / FILSI
2
6m+6
*5
*3
byte fill @AH+ <-- AL, counter RW0
-
-
-
-
-
*
*
-
-
-
MOVSW / MOVSWI
2
*2
*5
*6
word transfer @AH+ <-- @AL+, counter = RW0
-
-
-
-
-
-
-
-
-
-
MOVSWD
2
*2
*5
*6
word transfer @AH- <-- @AL-, counter = RW0
-
-
-
-
-
-
-
-
-
-
SCWEQ / SCWEQI
2
*1
*5
*7
word search @AH+ - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
SCWEQD
2
*1
*5
*7
word search @AH- - AL, counter = RW0
-
-
-
-
-
*
*
*
*
-
FILSW / FILSWI
2
6m+6
*5
*6
word fill @AH+ <-- AL, counter = RW0
-
-
-
-
-
*
*
-
-
-
*1: 5 when RW0 is 0, 4 + 7 x (RW0) when the counter expires, or 7n + 5 when a match occurs
*2: 5 when RW0 is 0; otherwise, 4 + 8 x (RW0)
*3: (b) x (RW0) + (b) x (RW0) When the source and destination access different areas, calculate the (b) item individually.
*4: (b) x n
*5: 2 x (RW0)
*6: (c) x (RW0) + (c) x (RW0) When the source and destination access different areas, calculate the (c) item individually.
*7: (c) x n
Note:
m: RW0 value (counter value), n: Loop count
See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle
count correction values for counting execution cycles" for information on (a) to (d) in the
table.
639
APPENDIX B Instructions
B.9
Instruction Map
Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction
map consists of multiple pages. Table B.9-2 "Basic page map" to Table B.9-21 "XCHW
RWi, ea instruction (first byte = 7FH)" summarize the F2MC-16LX instruction map.
■ Structure of Instruction Map
Figure B.9-1 Structure of instruction map
Basic page map
: Byte 1
Bit operation
instructions
Character string
operation instructions
2-byte instructions
ea instructions x 9
: Byte 2
An instruction such as the NOP instruction that ends in one byte is completed within the basic
page. An instruction such as the MOVS instruction that requires two bytes recognizes the
existence of byte 2 when it references byte 1, and can check the following one byte by
referencing the map for byte 2. Figure B.9-2 "Correspondence between actual instruction code
and instruction map" shows the correspondence between an actual instruction code and
instruction map.
640
APPENDIX B Instructions
Figure B.9-2 Correspondence between actual instruction code and instruction map
Some instructions do
not contain byte 2.
Length varies depending
on the instruction.
Instruction code
Byte 1
Byte 2
Operand
Operand
...
[Basic page map]
XY
+Z
[Extended page map] (*1)
UV
+W
*1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte
instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions.
An example of an instruction code is shown in Table B.9-1 "Example of an instruction code".
Table B.9-1 Example of an instruction code
Byte 1
(from basic page map)
Byte 2
(from extended page
map)
NOP
00 +0=00
-
AND A, #8
30 +4=34
-
MOV A, ADB
60 +F=6F
00 +0=00
@RW2+d8, #8rel
70 +0=70
F0 +2=F2
Instruction
641
642
2-byte
instruction
Character
string operation instruction
Bit operation
instruction
Ri,ea
ea instruction 9
ea instruction 8
ea instruction 7
ea instruction 6
ea instruction 5
ea instruction 4
ea instruction 3
ea instruction 2
ea instruction 1
APPENDIX B Instructions
Table B.9-2 Basic page map
APPENDIX B Instructions
Table B.9-3 Bit operation instruction map (first byte = 6CH)
643
APPENDIX B Instructions
Table B.9-4 Character string operation instruction map (first byte = 6EH)
644
APPENDIX B Instructions
A
A
DIVU
MULW
MUL
A
Table B.9-5 2-byte instruction map (first byte = 6FH)
645
646
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
Use
prohibited
APPENDIX B Instructions
Table B.9-6 ea instruction 1 (first byte = 70H)
APPENDIX B Instructions
Table B.9-7 ea instruction 2 (first byte = 71H)
647
APPENDIX B Instructions
Table B.9-8 ea instruction 3 (first byte = 72H)
648
APPENDIX B Instructions
Table B.9-9 ea instruction 4 (first byte = 73H)
649
APPENDIX B Instructions
Table B.9-10 ea instruction 5 (first byte = 74H)
650
APPENDIX B Instructions
Table B.9-11 ea instruction 6 (first byte = 75H)
651
APPENDIX B Instructions
Table B.9-12 ea instruction 7 (first byte = 76H)
652
APPENDIX B Instructions
Table B.9-13 ea instruction 8 (first byte = 77H)
653
APPENDIX B Instructions
Table B.9-14 ea instruction 9 (first byte = 78H)
654
APPENDIX B Instructions
Table B.9-15 MOVEA RWi, ea instruction (first byte = 79H)
655
APPENDIX B Instructions
Table B.9-16 MOV Ri, ea instruction (first byte = 7AH)
656
APPENDIX B Instructions
Table B.9-17 MOVW RWi, ea instruction (first byte = 7BH)
657
APPENDIX B Instructions
Table B.9-18 MOV ea, Ri instruction (first byte = 7CH)
658
APPENDIX B Instructions
Table B.9-19 MOVW ea, Rwi instruction (first byte = 7DH)
659
APPENDIX B Instructions
Table B.9-20 XCH Ri, ea instruction (first byte = 7EH)
660
APPENDIX B Instructions
Table B.9-21 XCHW RWi, ea instruction (first byte = 7FH)
661
APPENDIX B Instructions
662
INDEX
INDEX
The index follows on the next page.
This is listed in alphabetic order.
663
INDEX
Index
Numerics
1/2 bias and 1/2 duty, output waveform ............... 493
1/3 bias and 1/3 duty , output waveform .............. 496
1/3 bias and 1/4 duty, output waveform ............... 499
16-bit free-run timer operation, explanation of ..... 248
16-bit free-run timer section register .................... 236
16-bit free-run timer, clear timing for .................... 249
16-bit free-run timer, count timing for ...................249
16-bit input capture, input timing for ..................... 247
16-bit input capture, operation of .........................246
16-bit reload register (TMRLR0/1L, TMRLR0/1H)
................................................................... 265
16-bit reload timer ................................................ 391
16-bit reload timer pin, block diagram of .............. 258
16-bit reload timer setting..................................... 267
16-bit reload timer, block diagram of.................... 255
16-bit reload timer, EI2OS function of .................. 266
16-bit reload timer, interrupt and use of EI2OS from
................................................................... 254
16-bit reload timer, interrupt generated by ........... 266
16-bit reload timer, interrupt of ............................. 266
16-bit reload timer, list of register of..................... 259
16-bit reload timer, note on using.........................275
16-bit reload timer, operation mode of ................. 252
16-bit reload timer, pin of ..................................... 257
16-bit timer register (TMR0/1) .............................. 264
1M bit flash memory, feature of............................ 548
1M bit flash memory, sample program for............576
1M bit flash memory, sector configuration of........ 551
24-bit operand, specification with ........................... 28
32-bit register, indirect specification with................ 28
8/10-Bit A/D converter register, list of...................340
8/10-bit A/D converter, block diagram of.............. 336
8/10-bit A/D converter, block diagram of pin of .... 339
8/10-Bit A/D converter, Feature of ....................... 334
8/10-bit A/D converter, interrupt of ............... 335, 348
8/10-Bit A/D converter, note on using .................. 354
8/10-bit A/D converter, pin of ............................... 338
8/10-bit converter, EI2OS function of ...................348
A
A/D conversion data protect function ...................352
A/D converter power supply pin, processing related to
..................................................................... 19
664
A/D data register (ADCRH/ADCRL)..................... 346
acceptance filter, setting ...................................... 462
acceptance filtering .............................................. 458
acceptance mask register 0/1 (AMR0/AMR1), bit
configuration of .......................................... 445
acceptance mask selection register (AMSR), bit
configuration of .......................................... 443
access space ......................................................... 29
accumulator (A)...................................................... 36
ADB.................................................................. 47, 50
ADCRH/ADCRL ................................................... 346
ADCSH ................................................................ 341
ADCSL ................................................................. 344
address field, effective ................................. 607, 622
address match detection function processing,
flowchart of ................................................ 541
address match detection function, block diagram of
................................................................... 536
address match detection function, operation of ... 538
address match detection function, register
configuration for ......................................... 537
addressing ........................................................... 606
addressing, direct................................................. 608
addressing, indirect.............................................. 613
all "H", example of PWM output for...................... 302
all "L" or all "H", example of PWM output for ....... 302
amplitude data register ........................................ 531
AMR0/AMR1 ........................................................ 445
AMSR................................................................... 443
analog input of A/D converter, power-on sequence for
..................................................................... 20
asynchronous mode operation............................. 396
automatic algorithm end, timing of ....................... 555
B
bank addressing..................................................... 27
bank addressing and default space ....................... 30
bank register (PCB, DTB, USB, SSB, ADB) .......... 47
bank register and access space ............................ 29
bank select prefix (PCB, DTB, ADB, SPB) ............ 50
basic configuration ............................................... 582
baud rate selection by dedicated baud rate generator
................................................................... 388
baud rate selection by internal timer (16-bit reload
timer).......................................................... 391
INDEX
bidirectional communication function ................... 401
bit timing register (BTR), bit configuration of........ 428
bit timing, setting .................................................. 462
block diagram................................................... 6, 235
block diagram of CAN WAKE UP function pin change
circuit ......................................................... 471
block diagram of LCD controller/driver relat pin... 484
brightness adjustment when using internal divide
resistor ....................................................... 480
BTR...................................................................... 428
buffer address pointer (BAP) ................................. 89
bus mode ............................................................. 156
bus mode setting bit............................................. 158
bus operation stop bit (HALT = 1) ........................ 424
BVAL bit, caution for disabling message buffers by
................................................................... 474
BVALR ................................................................. 431
C
calculating execution cycle count......................... 620
CAN controller transmission request, clearing..... 455
CAN controller, block diagram of ......................... 411
CAN controller, completed transmission via ........ 456
CAN controller, flowchart of reception via............ 461
CAN controller, flowchart of transmission via ...... 457
CAN controller, starting transmission via ............. 455
CAN controller,features of.................................... 410
CAN transmission setting, flowchart of ................ 456
CAN transmission/reception, sample program for
................................................................... 472
CAN WAKE UP control register ........................... 420
CAN WAKE UP control register (CWUCR), bit
configuration of .......................................... 454
CAN WAKE UP function ...................................... 470
CAN WAKE UP function pin change circuit, block
diagram of.................................................. 471
CAN WAKE UP function, pin used for ................. 470
CDCR0/1.............................................................. 380
CKSCR ................................................................ 123
clock generation section, block diagram of .......... 121
clock mode........................................................... 133
clock mode, switching .......................................... 154
clock mode, transition of ...................................... 126
clock selection register (CKSCR), configuration of
................................................................... 123
clock supply map ................................................. 119
clock unit, outline of ............................................. 118
CMR....................................................................... 52
command sequence table.................................... 556
common register bank prefix (CMR) ...................... 52
communication prescaler control register (CDCR0/1),
bit configuration of ......................................380
compare clear register (CPCLR) ..........................241
condition code register ...........................................42
configuration .........................................................234
continuous conversion mode, operation of...........349
continuous mode, sample program for start by EI2OS
in.................................................................357
control register (SCR0/1), bit configuration of ......372
control status register (CSR), bit configuration of
...................................................................421
control status register (FMCS)..............................554
conversion operation using EI2OS .......................351
corresponding function ...........................................58
counter operation..................................................253
counter operation, states of ..................................268
CPCLR .................................................................241
CPU feature............................................................22
CPU intermittent operation mode .................133, 140
CPU operation detection reset circuit ...................504
CPU operation detection reset circuit, note on using
...................................................................511
CPU operation detection reset circuit, operation of
...................................................................510
CPU operation mode and current consumption ...132
CR00 to ICR15 .......................................................65
current consumption .............................................132
CWUCR................................................................454
cycle count, execution ..........................................619
D
data counter (DCT).................................................87
data polling flag (DQ7)..........................................559
data register (TCDT).............................................240
data register x (x = 0 to 15) (DTRx), bit configuration
of ................................................................452
decrement grade register .....................................532
dedicated register and general-purpose register....33
dedicated register, configuration of ........................34
default space ..........................................................30
delay interrupt generation module, block diagram of
...................................................................304
delay interrupt generation module, list of register of
...................................................................304
delay interrupt generation module, note on using
...................................................................306
delay interrupt generation module, operation of ...306
delayi nterrupt generation module, interrupt for....305
direct addressing ..................................................608
direct page register (DPR)......................................46
665
INDEX
display RAM and output pin ................................. 490
DLC register x (x = 0 to 15) (DLCRx), bit configuration
of ................................................................451
DLCRx.................................................................. 451
DPR........................................................................ 46
DTB ..................................................................47, 50
DTP function, operation of ................................... 324
DTP function, sample program for ....................... 330
DTP/external interrupt circuit, block diagram of ... 310
DTP/external interrupt circuit, block diagram of pin of
................................................................... 313
DTP/external interrupt circuit, interrupt of............. 309
DTP/external interrupt circuit, Note on using........ 326
DTP/external interrupt circuit, pin of..................... 312
DTP/external interrupt circuit, register of.............. 314
DTP/external interrupt circuit, setting of ............... 320
DTP/external interrupt function ............................ 308
DTP/external interrupt operation .......................... 321
DTP/interrupt enable register (ENIR) ...................316
DTP/interrupt source register (EIRR) ...................315
DTRx .................................................................... 452
E
EEPROM memory map........................................ 539
effective address field .................................. 607, 622
EI2OS.. 227, 228, 245, 266, 291, 305, 309, 335, 348,
365, 383
EIRR..................................................................... 315
ELVR.................................................................... 318
ENIR..................................................................... 316
event count mode................................................. 273
event count mode (external clock mode) ............. 253
event count mode, sample program for................ 278
exception interrupt because of undefined instruction
..................................................................... 95
execution cycle count ........................................... 619
execution cycle count, calculating ........................ 620
Expanded intelligent I/O service (EI2OS) channel
selection bit (ICS3 to ICS0).......................... 68
expanded intelligent i/o service (EI2OS) enable bit
(ISE) ............................................................. 68
expanded intelligent I/O service (EI2OS),
specification of processing for sample program
of ................................................................100
extended intelligent I/O service (EI2OS) ................ 83
extended intelligent I/O service (EI2OS) (time
consumed per transfer), processing time for
..................................................................... 92
extended intelligent i/o service (EI2OS) descriptor
666
(ISD), configuration of.................................. 85
extended intelligent I/O service (EI2OS) status
register (ISCS) ............................................. 88
extended intelligent I/O service (EI2OS), operation of
..................................................................... 84
extended intelligent I/O service (EI2OS), procedure
for using ....................................................... 91
extended intelligent I/O service (EI2OS), processing
sequence for ................................................ 90
external clock ....................................................... 130
external clock mode ............................................. 253
external clock, baud rate at selection of............... 393
external clock, using .............................................. 19
external divide resistor, using .............................. 482
external interrupt function .................................... 323
external interrupt function, sample program for ... 328
external reset pin, block diagram of ..................... 109
F
F2MC-16LX instruction list................................... 626
feature...................................................................... 4
flag change suppression prefix (NCC) ................... 53
flash memory (chip erase), erasing data from ..... 569
flash memory (sector erasure), erasing data from
................................................................... 570
flash memory mode ............................................. 552
flash memory to read/reset state, setting............. 566
flash memory write/erase, detail explanation of... 565
flash memory write/erase, procedure of............... 548
flash memory, control signal for ........................... 553
flash memory, note on using................................ 574
flash memory, overall block diagram of ............... 550
flash memory, procedure to erase sector from .... 570
flash memory, register of ..................................... 549
flash memory, resuming sector erasure of........... 573
flash memory, writing data to ............................... 567
flash memory, writing to ....................................... 567
flash microcomputer programmer (using power from
user system), example of minimum connection
................................................................... 591
flash microcomputer programmer (with power supply
from flash microcomputer programmer),
example of minimum connection ............... 593
flash microcomputer programmer, system
configuration of .......................................... 585
frame format, setting ............................................ 462
frequency data register ........................................ 530
fujitsu standard serial onboard writing, pin use for
................................................................... 583
INDEX
G
general control register ........................................ 412
general-purpose register........................................ 33
general-purpose register area and register bank
pointer.......................................................... 43
general-purpose register, configuration of ............. 48
H
hardware interrupt operation.................................. 74
hardware interrupt processing, starting of.............. 73
hardware interrupt suppressing ............................. 71
hardware interrupt, Configuration for ..................... 71
hardware interrupt, function of ............................... 70
hardware interrupt, operation flow for .................... 75
hardware interrupt, procedure for using................. 76
hardware interrupt, return from .............................. 73
hardware interrupt, time for handling ..................... 79
hardware sequence flag....................................... 557
I
I/O map ................................................................ 596
I/O port function ................................................... 162
I/O port register .................................................... 164
I/O port, example program for.............................. 211
I/O register address pointer (IOA).......................... 87
ICR......................................................................... 67
ICS01 ................................................................... 238
ICS23 ................................................................... 238
ICS3 to ICS0 .......................................................... 68
ID register x (x = 0 to15) (IDRx), bit configuration of
................................................................... 448
ID, setting............................................................. 462
IDE register (IDER), bit configuration of............... 432
IDRx ..................................................................... 448
indirect addressing............................................... 613
input capture control status register (ICS01, ICS23)
................................................................... 238
input capture data register (IPCP0-3) .................. 238
input capture interrupt and EI2OS ....................... 245
input capture section register............................... 237
input data register (SIDR0/1), bit configuration of
................................................................... 378
input port, operation as ........................................ 194
input/output circuit, type of ..................................... 16
instruction map, structure of................................. 640
instruction presentation item and symbol, description
of................................................................ 623
instruction type..................................................... 605
INT9 interrupt ....................................................... 542
internal clock mode...............................................252
internal clock mode (one-shot mode), operation of
...................................................................271
internal clock mode (reload mode), operation in ..269
internal clock mode, sample program for .............276
internal divide resistor, using ................................480
interrupt ................................................................153
interrupt control register..........................................61
interrupt control register (ICR) configuration ..........67
interrupt control register (ICR00 to ICR15).............65
interrupt control register list ....................................63
interrupt control register, function of .................64, 68
interrupt handling, example program for.................98
interrupt level mask register ...................................44
interrupt operation ..................................................59
interrupt source.......................................................61
interrupt source, timing of .....................................302
interrupt type...........................................................58
interrupt vector..................................................60, 61
interval interrupt function ......................................226
IPCP0-3 ................................................................238
ISE..........................................................................68
L
last event indication register (LEIR), bit configuration
of ................................................................425
LCD control register (LCRH), bit configuration of
upper bit of .................................................488
LCD control register (LCRL), bit configuration of lower
bit of............................................................486
LCD controller/driver external divide resistor........481
LCD controller/driver operation.............................492
LCD controller/driver relat pin...............................483
LCD controller/driver, block diagram of ................477
LCD controller/driver, function of ..........................476
LCD controller/driver, power supply voltage of.....478
LCD controller/driver’s internal divide resistor ......479
LCD panel connection display data (1/2 duty drive
method), example of...................................495
LCD panel connection display data (1/3 duty drive
method), example of...................................498
LCD panel connection display data (1/4 duty drive
method), example of...................................501
LCD, drive waveform of ........................................492
linear addressing and bank addressing..................27
lower bit of A/D control status register (ADCSL) ..344
lower bit of timer control status register (TMCSR0/1L)
...................................................................262
low-power consumption control circuit, block diagram
of ................................................................135
667
INDEX
low-power consumption mode control register
(LPMCR) .................................................... 137
low-power consumption mode control register,
accessing ...................................................139
low-power consumption mode, operation states of
................................................................... 151
low-power consumption mode, setting ................. 463
low-voltage detection reset circuit ........................ 504
low-voltage detection reset circuit, note on using
................................................................... 511
low-voltage detection reset circuit, operation of ... 510
low-voltage/CPU operation detection reset circuit,
register of ...................................................508
low-voltage/CPU operation detection reset circuit,
sample program for .................................... 512
LPMCR................................................................. 137
LQFP100............................................................ 9, 11
M
machine clock ...................................................... 127
main clock mode, pll clock mode, and sub-clock mode
................................................................... 126
making CAN receive setting, flowchart of............. 460
master/slave communication, function for ............403
maximum voltage rating strictly observing, for latchup prevention ............................................... 18
MD2 to MD0 .........................................................157
memory map .......................................................... 25
memory space........................................................ 23
memory space configuration ................................ 545
message buffer ............................................ 415, 447
message buffer (x), reception via .........................466
message buffer control register............................ 413
message buffer valid register (BVALR), bit
configuration of .......................................... 431
message buffer(x), transmission via..................... 464
mode data ............................................................ 158
mode fetch ........................................................... 111
mode pin .............................................................. 110
mode pin (MD2 to MD0) ....................................... 157
mode pin and mode data, relationship between .. 159
mode register (SMR0/1), bit configuration of........ 374
mode setting.........................................................156
multi-level message buffer configuration, specifying
................................................................... 468
multiple byte length operand, allocation of ............. 31
multiple interrupt, example of ................................. 78
multiple interrupt, operation for .............................. 77
multiple-byte data in ram, allocating....................... 31
multiple-byte data on stack, allocation of ............... 32
668
multiple-byte data, accessing................................. 32
N
NCC ....................................................................... 53
O
one-shot operation ............................................... 301
operation .............................................................. 223
operation mode .................................................... 156
operation mode 2 ................................................. 399
operation, description of....................................... 245
oscillation stabilization wait reset state ................ 108
oscillation stabilization wait time .......... 107, 129, 154
oscillation stabilization wait time, timer function for
................................................................... 227
other mode........................................................... 552
output data register (SODR0/1), bit configuration of
................................................................... 379
overview............................................................... 290
ow-voltage/CPU operation detection reset circuit,
block diagram of ........................................ 506
P
package dimension (LQFP100) ............................... 9
package dimension (QFP100) ................................. 8
PC .......................................................................... 45
PCB.................................................................. 47, 50
PCNT ................................................................... 294
PCSR ................................................................... 298
PDCR................................................................... 297
PDUT ................................................................... 298
pin after reading mode data, state of ................... 116
pin assignment (LQFP100) .................................... 11
pin assignment (QFP100) ...................................... 10
pin function, description of ..................................... 12
pin in reset mode, state of.................................... 116
pll clock mode ...................................................... 126
PLL clock mode, note on during operation of ........ 20
PLL clock multiplication ratio, selecting ............... 127
port 0 pin .............................................................. 165
port 0 register, function of .................................... 167
port 0, configuration of ......................................... 165
port 0, operation of............................................... 168
port 0, pin block diagram for ................................ 166
port 0, register for................................................. 166
port 1 configuration .............................................. 170
port 1 pin .............................................................. 170
port 1 register, function of .................................... 172
port 1, operation of............................................... 173
INDEX
port 1, pin block diagram for ................................ 171
port 1, register for................................................. 171
port 3 configuration .............................................. 175
port 3 pin .............................................................. 175
port 3 register, function of .................................... 177
port 3, operation of............................................... 178
port 3, pin block diagram for ................................ 176
port 3, register for................................................. 176
port 4 configuration .............................................. 180
port 4 pin .............................................................. 180
port 4 register, function of .................................... 182
port 4, operation of............................................... 183
port 4, pin block diagram for ................................ 181
port 4, register for................................................. 181
port 5 configuration .............................................. 185
port 5 pin .............................................................. 185
port 5 register, function of .................................... 187
port 5, operation of............................................... 188
port 5, pin block diagram for ................................ 186
port 5, register for................................................. 186
port 6 configuration .............................................. 190
port 6 pin .............................................................. 190
port 6 register, function of .................................... 192
port 6, operation of............................................... 194
port 6, pin block diagram for ................................ 191
port 6, register for................................................. 191
port 7 configuration .............................................. 196
port 7 pin .............................................................. 196
port 7 register, function of .................................... 198
port 7, operation of............................................... 199
port 7, pin block diagram for ................................ 197
port 7, register for................................................. 197
port 8 configuration .............................................. 201
port 8 pin .............................................................. 201
port 8 register, function of .................................... 203
port 8, operation of............................................... 204
port 8, pin block diagram for ................................ 202
port 8, register for................................................. 202
port 9 configuration .............................................. 206
port 9 pin .............................................................. 206
port 9 register, function of .................................... 208
port 9, operation of............................................... 209
port 9, pin block diagram for ................................ 207
port 9, register for................................................. 207
power pin ............................................................... 19
power supply to high current output buffer pin (DVcc
and DVss), handling .................................... 20
power-on ................................................................ 18
PPG control status register (PCNT) ..................... 294
PPG down counter register (PDCR).....................297
PPG duty setting register (PDUT) ........................298
PPG interval setting register (PCSR) ...................298
PPG timer interrupt and EI2OS ............................291
PPG timer register, list of......................................293
PPG timer, block diagram of.................................292
prefix code ..............................................................50
prefix code, restriction on .......................................54
processor status register (PS), bit configuration of.41
product outline ..........................................................2
program address detection control register (PACSR)
...................................................................538
program address detection register (PADR0/PADR1)
...................................................................537
program counter (PC).............................................45
program error occur, if ..........................................540
PS...........................................................................41
pull-up/pull-down resistor........................................20
PWM control register, bit configuration of.............516
PWM operation.....................................................299
PWM setting value, note on changing ..................523
PWM1 and PWM2 compare register, bit configuration
of ................................................................517
PWM1/PWM2 selection register, bit configuration of
...................................................................519
Q
QFP100 ..............................................................8, 10
R
RCR......................................................................439
real-time watch timer, block diagram of................282
real-time watch timer, list of registe of ..................283
receive complete ..................................................460
receive complete register (RCR), bit configuration of
...................................................................439
receive error counter and transmit error counter
(RTEC), bit configuration of........................427
receive interrupt enable register (RIER), bit
configuration of...........................................442
receive interrupt generation and flag setting, timing of
...................................................................384
receive message, storing......................................458
receive overrun.....................................................459
receive overrun register (ROVRR), bit configuration of
...................................................................441
receiving data frame and remote frame, processing
for ...............................................................459
register bank...........................................................49
register bank pointer...............................................43
669
INDEX
register relat to LCD controller/driver, bit configuration
of ................................................................485
reload mode .........................................................269
remote frame ........................................................ 459
remote frame receive wait register (RFWTR), bit
configuration of .......................................... 435
remote request transmission register (RRTRR), bit
configuration of .......................................... 440
request level setting register (ELVR).................... 318
reset operation, outline of..................................... 110
reset source .........................................................104
reset source and oscillation stabilization wait time
................................................................... 107
reset source bit..................................................... 112
reset source bit and reset source, correspondence
between .................................................... 113
reset source bit, note on....................................... 115
reset source bits, state of ..................................... 114
reset source, confirming....................................... 224
resonator and external clock, connection of......... 130
RFWTR ................................................................435
RIER..................................................................... 442
ROM area............................................................... 24
ROM mirror function selection module, block diagram
of ................................................................544
ROM mirror function selection module, register of
................................................................... 544
ROM mirror function selection register (ROMM) .. 545
ROVRR ................................................................441
RRTRR................................................................. 440
RTEC ................................................................... 427
run mode .............................................................. 156
S
sample BTR setting.............................................. 430
second/minute/hour data register, bit configuration of
................................................................... 287
sector erasure timer flag (DQ3)............................ 564
send interrupt generation and flag setting, timing of
................................................................... 385
serial programming connection, example of......... 586
setting IDR, example of........................................ 449
single conversion mode by EI2OS, sample program
for start in ...................................................355
single conversion mode, operation of .................. 349
single-chip mode (power supply from flash
microcomputer programmer), example of
connection in .............................................. 589
single-chip mode (using power from user system),
example of connection in ........................... 587
670
single-chip mode, pin state in .............................. 152
sleep mode, canceling ......................................... 142
sleep mode, transition to...................................... 142
SMR0/1 ................................................................ 374
SODR0/1.............................................................. 379
software interrupt processing, operation for........... 82
software interrupt processing, start of.................... 81
software interrupt, precaution for ........................... 82
software interrupt, return from................................ 81
sound control register, bit configuration of ........... 528
sound generator, block diagram of ...................... 526
sound generator, register of................................. 527
SPB........................................................................ 50
SSB........................................................................ 47
SSP........................................................................ 40
SSR0/1................................................................. 376
stable supply voltage, providing............................. 18
stack area .............................................................. 97
stack operation after return from interrupt handling
..................................................................... 96
stack operation when interrupt handling start ........ 96
stack selection ....................................................... 39
standby mode ...................................................... 134
standby mode by interrupt, canceling .................. 154
standby mode, transition to.................................. 153
starting watchdog timer, method of...................... 224
state between bus operation stop (HALT = 1) ..... 424
state transition diagram........................................ 150
status register (SSR0/1), bit configuration of ....... 376
stepping motor controller operation, settings for.. 521
stepping motor controller, block diagram of ......... 514
stepping motor controller, register of ................... 515
stop conversion mode, operation in ..................... 350
stop mode, canceling ................................... 149, 154
stop mode, sample program for EI2OS startup in
................................................................... 360
stop mode, transition to........................................ 148
structure of instruction map.................................. 640
sub-clock mode.................................................... 126
sub-second data register, bit configuration of ...... 286
suspending flash memory sector erasure ............ 572
synchronous mode operation (operation mode 2)
................................................................... 399
system configuration ............................................ 539
system stack pointer (SSP).................................... 40
T
TBTC.................................................................... 219
TCANR................................................................. 436
INDEX
TCCSH................................................................. 242
TCCSL ................................................................. 242
TCDT ................................................................... 240
TCR...................................................................... 437
TIER..................................................................... 438
timebase timer ............................................. 215, 216
timebase timer control register (TBTC), bit
configuration of .......................................... 219
timebase timer interrupt ....................................... 226
timebase timer interrupt and EI2OS..................... 227
timebase timer mode, canceling .......................... 145
timebase timer mode, transition to....................... 144
timebase timer operation ..................................... 226
timebase timer, example program of ................... 232
timebase timer, function of................................... 214
timebase timer, note on using.............................. 229
timebase timer, operation of ................................ 230
timer control register, bit configuration of............. 284
timer control status register (TCCSH, TCCSL) .... 242
timing limit excess flag (DQ5) .............................. 563
TMCSR0/1H......................................................... 260
TMCSR0/1L ......................................................... 262
TMR0/1 ................................................................ 264
TMRLR0/1H ......................................................... 265
TMRLR0/1L.......................................................... 265
toggle bit flag (DQ6)............................................. 561
tone count register ............................................... 533
transition to standby mode, notes on ................... 153
transmission cancel register (TCANR), bit
configuration of .......................................... 436
transmission complete register (TCR), bit
configuration of .......................................... 437
transmission interrupt enable register (TIER), bit
configuration of .......................................... 438
transmission request register (TREQR), bit
configuration of .......................................... 433
transmission RTR register (TRTRR), bit configuration
of................................................................ 434
TREQR ................................................................ 433
type of instruction................................................. 605
U
UART baud rate selection.................................... 386
UART function...................................................... 364
UART register, list of ............................................371
UART, block diagram of .......................................366
UART, block diagram of pin of..............................370
UART, EI2OS function in......................................383
UART, interrupt for ...............................................365
UART, interrupt of.........................................382, 383
UART, note on using ............................................406
UART, operation mode of.............................365, 394
UART, pin of .........................................................369
UART, sample program for...................................407
unused pin, handling ..............................................19
upper bit and bit 7 of timer control status register
(TMCSR0/1H).............................................260
upper bit of A/D control status register (ADCSH)
...................................................................341
USB ........................................................................47
user stack pointer (USP) ........................................40
USP ........................................................................40
W
watch mode, canceling .........................................147
watch mode, transition to......................................146
watch timer ...................................................215, 216
watch timer control register (WTC).......................221
watch timer function..............................................214
watch timer interrupt and EI2OS ..........................228
watch timer operation ...........................................228
watch timer, interval interrupt function of..............228
watchdog stop ......................................................224
watchdog timer control register (WDTC), bit
configuration for..........................................217
watchdog timer reset, inhibiting ............................224
watchdog timer, clearing.......................................224
watchdog timer, example program for ..................231
watchdog timer, functions of.................................214
watchdog timer, note on using..............................229
watchdog timer/timebase timer/clock timer, block
diagram of ..................................................215
watchdog timer/timebase timer/clock timer, list of
register for ..................................................216
watchdog timer’s interval time ..............................225
WDTC...................................................................217
when sub-clock mode is not used ..........................20
WTC .....................................................................221
671
INDEX
672
CM44-10113-1E
FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL
F2MC-16LX
16-BIT MICROCONTROLLER
MB90420G/425G Series
HARDWARE MANUAL
April 2002 the first edition
Published
FUJITSU LIMITED
Edited
Technical Information Dept.
Electronic Devices