FUJITSU SEMICONDUCTOR CM44-10115-3E CONTROLLER MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90470 Series HARDWARE MANUAL 2 F MC-16LX 16-BIT MICROCONTROLLER MB90470 Series HARDWARE MANUAL FUJITSU LIMITED PREFACE ■ Purpose of This Manual and Intended Readers Thank you very much for purchasing FUJITSU products. MB90470 is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. MB90470 functions are suitable for controlling PHS, cellular phones, CD-ROMs, and VCRs. This manual, intended for engineers developing products using the MB90470, explains the MB90470 functions and operations. Read this manual first, before using the product. For details on the instructions, refer to the "Instruction Manual". ■ Trademark F2MC is a trademark of FUJITSU Flexible Microcontroller. Embedded Algorithm is a registered trademark of Advanced Micro Devices, Inc. ■ License Purchase of FUJITSU I2C components conveys a license under the Philips I2C Patent Rights to use these components in the I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. i ■ Composition of This Manual This Manual consists of the following 27 Chapters and an Appendix. CHAPTER 1 "OVERVIEW OF MB90470" This chapter gives an overview of MB90470, including its basic characteristics, block diagram, and its functions. CHAPTER 2 "CPU" This chapter explains CPU specifications, memory, and the functions of registers to provide readers with a better understanding of the MB90470 functions. CHAPTER 3 "INTERRUPT" This chapter explains interrupts and direct access (DMA). CHAPTER 4 "RESET" This chapter explains reset for the MB90470 series. CHAPTER 5 "CLOCKS" This chapter describes the clocks of the MB90470 series. CHAPTER 6 "LOW-POWER CONSUMPTION MODE" This chapter explains the low-power consumption mode of the MB90470 series. CHAPTER 7 "MODE SETTING" This chapter explains mode setting and external memory access. CHAPTER 8 "I/O PORT" This chapter shows the configuration and explains the functions of the registers used for the I/O port. CHAPTER 9 "TIMEBASE TIMER" This chapter explains the function and operation of the timebase timer. CHAPTER 10 "WATCHDOG TIMER" This chapter describes the operation and function of the watchdog timer. CHAPTER 11 "WATCH TIMER" This chapter has an overview of the watch timer, describes the configuration and functions of the register, and explains the operation of the watch timer. CHAPTER 12 "16-BIT INPUT/OUTPUT TIMER" This chapter has an overview of the 16-bit input/output timer, describes the configuration and function of its register, and explains the operation of the timer. CHAPTER 13 "8/16-BIT UP-DOWN COUNTER/TIMER" This chapter has an overview of the 8/16-bit up/down counter/timer, describes the configuration and functions of its registers, and explains the operation of the 8/16-bit up/ down counter/timer. CHAPTER 14 "PWC TIMER" This chapter provides an overview of the PWC timer, provides notes on its use, and explains the configuration and functions of its registers. CHAPTER 15 "µ µPG TIMER" This chapter provides a block diagram of the µPG timer and explains the configuration and functions of its registers. ii CHAPTER 16 "16-BIT RELOAD TIMER" This chapter provides an overview of the 16-bit reload timer and its operation, and explains the configuration and functions of its registers. CHAPTER 17 "8/16-BIT PPG TIMER" This chapter provides an overview of the 8/16-bit PPG timer and its operation, and explains the configuration and functions of its registers. CHAPTER 18 "DTP/EXTERNAL INTERRUPT UNIT" This chapter provides an overview of the DTP/external interrupt unit, its operation, and explains the configuration and functions of its registers. CHAPTER 19 "8/10-BIT A/D CONVERTER" This chapter provides an overview of the 8/10-bit A/D converter and its operation, and explains the configuration and functions of its registers. CHAPTER 20 "EXPANDED I/O SERIAL INTERFACE" This chapter provides an overview of the expanded I/O serial interface and its operation, and explains the configuration and functions of its registers. CHAPTER 21 "UART" This chapter provides an overview of the UART, its operation, and explains the configuration and functions of its registers. CHAPTER 22 "I2C INTERFACE" This chapter provides an overview of the I2C interface and its operation, and explains the configuration and functions of its registers. CHAPTER 23 "CHIP SELECTION FACILITY" This chapter provides an overview of the chip selection facility and its operation, and explains the configuration and functions of its registers. CHAPTER 24 "ADDRESS MATCH DETECTION FUNCTION" This chapter describes the address match detection function and its operation CHAPTER 25 "ROM MIRROR FUNCTION SELECTION MODULE" This chapter describes the functions of the ROM mirror function selection module. CHAPTER 26 "2M BIT FLASH MEMORY" This chapter describes the functions and operations of the 2M bit flash memory. CHAPTER 27 "EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION" This chapter shows an example of a serial programming connection using the AF220/AF210/ AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation. "APPENDIX" The appendix provides the memory map and lists the instructions used in the F2MC-16LX. iii • • • • • • The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of Fujitsu semiconductor device; Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of Fujitsu or any third party or does Fujitsu warrant non-infringement of any third-party' s intellectual property right or other right by using such information. Fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan. ©2003 FUJITSU LIMITED Printed in Japan iv CONTENTS CHAPTER 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 OVERVIEW OF MB90470 ............................................................................. 1 Overview ................................................................................................................................................ 2 Block Diagram of MB90470 ................................................................................................................... 5 Package Dimensions ............................................................................................................................. 6 Pin Assignment ...................................................................................................................................... 8 Pin Functions ....................................................................................................................................... 10 I/O Circuit Type .................................................................................................................................... 16 Handling the Device ............................................................................................................................. 19 CHAPTER 2 CPU ............................................................................................................. 21 2.1 Overview of CPU Specifications .......................................................................................................... 22 2.2 Memory Space ..................................................................................................................................... 23 2.3 CPU Registers ..................................................................................................................................... 27 2.3.1 Accumulator (A) .............................................................................................................................. 29 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) .......................................................... 30 2.3.3 Processor Status (PS) .................................................................................................................... 31 2.3.4 Program Counter (PC) .................................................................................................................... 34 2.3.5 Program Count Bank Register (PCB) ............................................................................................. 35 2.3.6 Direct Page Register (DPR) ........................................................................................................... 36 2.3.7 General-Purpose Register (Register Bank) .................................................................................... 37 2.4 Prefix Codes ........................................................................................................................................ 38 CHAPTER 3 INTERRUPT ................................................................................................ 41 3.1 Overview .............................................................................................................................................. 42 3.2 Interrupt Factor and Interrupt Vector ................................................................................................... 44 3.3 Interrupt Control Register and Peripheral Function ............................................................................. 47 3.3.1 Interrupt Control Register (ICR00 to ICR15) .................................................................................. 49 3.3.2 Interrupt Control Register Functions ............................................................................................... 52 3.4 Hardware Interrupt ............................................................................................................................... 55 3.4.1 Hardware Interrupt Operation ......................................................................................................... 58 3.4.2 Flow of Hardware Interrupt Operation ............................................................................................ 60 3.4.3 Procedure for Using Hardwar Interrupt ........................................................................................... 61 3.4.4 Multiple Interrupts ........................................................................................................................... 63 3.4.5 Hardware Interrupt Processing Time .............................................................................................. 65 3.5 Software Interrupt ................................................................................................................................ 67 3.6 Interrupt by µDMA ............................................................................................................................... 69 3.6.1 DMA Descriptor .............................................................................................................................. 73 3.6.2 Individual Registers of DMA Descriptor .......................................................................................... 75 3.6.3 DMA Processing Procedure ........................................................................................................... 78 3.6.4 µDMA Processing Time .................................................................................................................. 79 3.7 Interrupt of Extended Intelligent I/O Service (EI2OS) .......................................................................... 81 3.7.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) ............................................................. 83 3.7.2 Description of Extended Intelligent I/O service (EI2OS) descriptor (ISD) ....................................... 85 3.7.3 Operation of Extended Intelligent I/O Service (EI2OS) .................................................................. 88 v 3.7.4 Setting procedure of Extended Intelligent I/O Service (EI2OS) ..................................................... 89 3.7.5 Processing Time for Extended Intelligent I/O Service (EI2OS) ..................................................... 90 3.8 Exception Processing Interrupt by Executing Undefined Instruction .................................................. 93 3.9 Stack Operation of Interrupt Processing ............................................................................................. 94 3.10 Sample Program of Interrupt Processing ............................................................................................ 96 3.11 Delay Interrupt Event Module ............................................................................................................. 99 3.11.1 Operation of Delay Interrupt Event Module ................................................................................. 100 CHAPTER 4 4.1 4.2 4.3 4.4 4.5 4.6 CHAPTER 5 5.1 5.2 5.3 5.4 5.5 5.6 RESET ...................................................................................................... 101 Overview of Reset ............................................................................................................................. Reset Factors and Oscillation Stabilization Wait Time ..................................................................... External-Reset Pin ............................................................................................................................ Resetting ........................................................................................................................................... Reset-Factor Bits .............................................................................................................................. Condition of Pins as Result of Reset ................................................................................................ CLOCKS ................................................................................................... 113 Overview ........................................................................................................................................... Block Diagram of Clock Generator ................................................................................................... Clock Selection Register (CKSCR) ................................................................................................... Clock Modes ..................................................................................................................................... Oscillation Stabilization Wait Time .................................................................................................... Connecting Oscillator to External Clock ............................................................................................ CHAPTER 6 128 131 133 136 137 138 140 142 144 146 148 153 MODE SETTING ....................................................................................... 157 7.1 Mode Setting ..................................................................................................................................... 7.2 Mode Pins (MD2 to MD0) ................................................................................................................. 7.3 Mode Data ........................................................................................................................................ 7.4 External Memory Access .................................................................................................................. 7.4.1 Automatic ready function selection register (ARSR) .................................................................... 7.4.2 External address output control register (HACR) ......................................................................... 7.4.3 Bus control signal selection register (EPCR) ............................................................................... 7.5 Operation of Each Mode for Mode Setting ........................................................................................ 7.5.1 External memory access control signals ...................................................................................... vi 114 116 118 121 125 126 LOW-POWER CONSUMPTION MODE .................................................... 127 6.1 Overview of Low-Power Consumption Mode .................................................................................... 6.2 Block Diagram of Low-power Control Circuit .................................................................................... 6.3 Low-Power Consumption Mode Control Register (LPMCR) ............................................................. 6.4 CPU Intermittent Operation Mode ..................................................................................................... 6.5 Standby Mode ................................................................................................................................... 6.5.1 Sleep Mode .................................................................................................................................. 6.5.2 Timebase Timer Mode ................................................................................................................. 6.5.3 Watch Mode ................................................................................................................................. 6.5.4 Stop Mode ................................................................................................................................... 6.6 State Transition Diagram .................................................................................................................. 6.7 Pin State in Standby Mode, Hold, and Reset .................................................................................... 6.8 Caution on Using Low-Power Consumption Mode ........................................................................... CHAPTER 7 102 104 106 107 109 111 158 159 160 164 166 168 169 171 172 7.5.2 7.5.3 Ready function .............................................................................................................................. 175 Hold function ................................................................................................................................. 178 CHAPTER 8 I/O PORT ................................................................................................... 181 8.1 Functions of I/O Port .......................................................................................................................... 182 8.2 Registers for I/O Port ......................................................................................................................... 183 8.2.1 Port registers (PDR0 to PDRA) .................................................................................................... 184 8.2.2 Port direction registers (DRR0 to DRRA) ..................................................................................... 185 8.2.3 Other registers .............................................................................................................................. 187 CHAPTER 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 TIMEBASE TIMER .................................................................................... 189 Overview ............................................................................................................................................ 190 Timebase Timer Configuration .......................................................................................................... 192 Timebase Timer Control Register (TBTC) ......................................................................................... 194 Timebase Timer Interrupt .................................................................................................................. 196 Timebase Timer Operation ................................................................................................................ 197 Notes on Using Timebase Timer ....................................................................................................... 199 Sample Programs .............................................................................................................................. 201 CHAPTER 10 WATCHDOG TIMER ................................................................................. 203 10.1 10.2 10.3 10.4 10.5 10.6 Overview ............................................................................................................................................ 204 Watchdog Timer Control Register (WDTC) ....................................................................................... 206 Watchdog Timer Configuration .......................................................................................................... 208 Watchdog Timer Operation ................................................................................................................ 210 Notes on Using Watchdog Timer ....................................................................................................... 212 Sample Programs .............................................................................................................................. 213 CHAPTER 11 WATCH TIMER ......................................................................................... 215 11.1 11.2 11.3 11.4 Overview ............................................................................................................................................ 216 Watch Timer Configuration ................................................................................................................ 217 Watch Timer Control Register (WTC) ................................................................................................ 218 Watch Timer Operation ...................................................................................................................... 220 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ................................................................ 223 12.1 Overview ............................................................................................................................................ 224 12.2 16-bit Input/Output Timer Register .................................................................................................... 226 12.2.1 16-bit free-running timer ............................................................................................................... 227 12.2.2 Output compare ............................................................................................................................ 232 12.2.3 Input capture ................................................................................................................................. 236 12.3 16-bit Input/Output Timer Operation .................................................................................................. 239 12.3.1 Operation of 16-bit free-running timer .......................................................................................... 240 12.3.2 Operation of 16-bit output compare .............................................................................................. 242 12.3.3 Operation of 16-bit input capture .................................................................................................. 244 12.3.4 16-bit free-running timer timing ..................................................................................................... 245 12.3.5 Output compare timing ................................................................................................................. 246 12.3.6 Timing of input capture ................................................................................................................. 247 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ................................................... 249 vii 13.1 Overview ........................................................................................................................................... 13.2 Registers for 8/16-bit Up/Down Counter/Timer ................................................................................. 13.2.1 Counter control register H0 (CCRH0) .......................................................................................... 13.2.2 Counter control register H1 (CCRH1) .......................................................................................... 13.2.3 Counter control register L0/1 (CCRL0/1) ..................................................................................... 13.2.4 Counter status register 0/1 (CSR0/1) ........................................................................................... 13.2.5 Up/down count register 0/1 (UDCR0/1) ....................................................................................... 13.2.6 Reload/compare register 0/1 (RCR0/1) ....................................................................................... 13.3 8/16-bit Up/Down Counter/Timer Operation ..................................................................................... 13.3.1 Reload/compare function ............................................................................................................. 13.3.2 Writing data to up/down count register (UDCR) ........................................................................... 250 253 254 256 258 260 262 263 264 267 270 CHAPTER 14 PWC TIMER .............................................................................................. 273 14.1 Overview of PWC Timer ................................................................................................................... 14.2 PWC Timer Registers ....................................................................................................................... 14.2.1 PWC Control/Status Register (PWCSR0 to PWCSR2) ............................................................... 14.2.2 PWC Data Buffer Register (PWCR0 to PWCR2) ......................................................................... 14.2.3 Divide Ratio Control Register (DIVR0 to DIVR2) ......................................................................... 14.3 Operations of PWC Timer ................................................................................................................. 14.3.1 Operations of the Timer Function ................................................................................................ 14.3.2 Operations of the Pulse Width Measurement Function ............................................................... 14.3.3 Selection of Count Clock and Operation Mode ............................................................................ 14.3.4 Start and Stop of Timer/Pulse Width Measurement ..................................................................... 14.3.5 Timer Mode Operation ................................................................................................................. 14.3.6 Operation in Pulse Width Measurement Mode ............................................................................ 14.4 Notes on PWC Timer Usage ............................................................................................................. 274 276 277 282 283 284 285 286 288 290 292 295 301 CHAPTER 15 µPG TIMER ............................................................................................... 303 15.1 Overview of µPG Timer ..................................................................................................................... 304 15.2 µPG Timer Registers ........................................................................................................................ 305 15.3 Timing Chart of µPG Timer ............................................................................................................... 307 CHAPTER 16 16-BIT RELOAD TIMER ........................................................................... 309 16.1 Overview of 16-Bit Reload Timer ...................................................................................................... 16.1.1 Functions of the 16-Bit Reload Timer .......................................................................................... 16.1.2 Block Diagram of the 16-Bit Reload Timer ................................................................................... 16.2 16-Bit Reload Timer Registers .......................................................................................................... 16.2.1 Timer Control Status Register (TMCSR) ..................................................................................... 16.2.2 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) ................................................... 16.3 Operations of the 16-Bit Reload Timer ............................................................................................. 16.3.1 State Transitions During Counter Operation ................................................................................ 16.3.2 Operations of Internal Clock Mode (Reload Mode) ...................................................................... 16.3.3 Internal Clock Mode (One-Shot Mode) ........................................................................................ 16.3.4 Event Count Mode ....................................................................................................................... 310 311 313 314 315 319 321 322 323 325 327 CHAPTER 17 8/16-BIT PPG TIMER ................................................................................ 329 17.1 Overview of 8/16-bit PPG Timer ....................................................................................................... 330 17.1.1 Block Diagram of the 8/16-Bit PPG Timer ................................................................................... 331 viii 17.2 8/16-bit PPG Timer Registers ............................................................................................................ 333 17.2.1 PPG0/2/4 Operation Mode Control Register (PPGC0) ................................................................. 334 17.2.2 PPG1/3/5 Operation Mode Control Register (PPGC1) ................................................................. 336 17.2.3 PPG0 to PPG5 Output Control Registers (PPG0/1, PPG2/3, PPG4/5) ........................................ 339 17.2.4 Reload Registers (PPLL0 to PPLL5, PPLH0 to PPLH5) .............................................................. 341 17.3 Operations of 8/16-Bit PPG Timer ..................................................................................................... 342 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT ........................................................ 347 18.1 18.2 18.3 18.4 Overview of DTP/External Interrupt Unit ............................................................................................ 348 DTP/External Interrupt Unit Registers ............................................................................................... 349 Operations of DTP/External Interrupt Unit ......................................................................................... 351 Notes on DTP/External Interrupt Unit Usage ..................................................................................... 353 CHAPTER 19 8/10-BIT A/D CONVERTER ...................................................................... 355 19.1 Overview of 8/10-bit A/D Converter ................................................................................................... 356 19.2 8/10-bit A/D Converter Registers ....................................................................................................... 358 19.2.1 Control Status Register 1 (ADCS1) .............................................................................................. 359 19.2.2 Control Status Register 2 (ADCS2) .............................................................................................. 362 19.2.3 Data Registers (ADCR2 and ADCR1) .......................................................................................... 365 19.3 Operations of 8/10-bit A/D Converter ................................................................................................ 366 19.3.1 Example of µDMA Start in Single Mode ....................................................................................... 368 19.3.2 Example of µDMA Start in Continuous Mode ............................................................................... 370 19.3.3 Example of µDMA Start in Stop Mode .......................................................................................... 372 19.4 Conversion Data Protection Function ................................................................................................ 374 19.5 Precautions When Using the 8/10-bit A/D Converter ........................................................................ 376 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE ..................................................... 377 20.1 Overview of Expanded I/O Serial Interface ........................................................................................ 378 20.2 Registers of Expanded I/O Serial Interface ....................................................................................... 379 20.2.1 Serial Mode Control Status Register (SMCS) .............................................................................. 380 20.2.2 Serial Shift Data Register (SDR) .................................................................................................. 384 20.2.3 Dedicated Prescaler Control Register (SDCR) ............................................................................. 385 20.3 Operation of Expanded I/O Serial Interface ....................................................................................... 386 20.3.1 Shift Clock Modes ......................................................................................................................... 387 20.3.2 Operational States of Serial I/O Units ........................................................................................... 388 20.3.3 Start/Stop Timing and Input/Output Timing of Shift Operation ..................................................... 390 20.3.4 Interrupt Function ......................................................................................................................... 392 CHAPTER 21 UART ......................................................................................................... 393 21.1 Overview of the UART ....................................................................................................................... 394 21.2 UART Registers ................................................................................................................................. 396 21.2.1 Serial Mode Register (SMR) ......................................................................................................... 397 21.2.2 Serial Control Register (SCR) ...................................................................................................... 399 21.2.3 Serial Input/Output Register (SIDR/SODR) .................................................................................. 401 21.2.4 Serial Status Register (SSR) ........................................................................................................ 402 21.2.5 Communication Prescaler Control Register (CDCR) .................................................................... 404 21.3 UART Operations .............................................................................................................................. 406 21.3.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) .................................................... 410 ix 21.3.2 Operation in Synchronous Mode (Operation Mode 2) ................................................................. 21.3.3 Two-Way Communication Function (Normal Mode) .................................................................... 21.3.4 Master/Slave Communication Function (Multiprocessor Mode) .................................................. 21.4 Precautions on Using the UART ....................................................................................................... 21.5 UART Program Example .................................................................................................................. 413 415 417 420 421 CHAPTER 22 I2C INTERFACE ........................................................................................ 423 22.1 Overview of I2C Interface .................................................................................................................. 22.2 I2C Interface Registers ...................................................................................................................... 22.2.1 Bus Status Register (IBSR) ......................................................................................................... 22.2.2 Bus Control Register (IBCR) ........................................................................................................ 22.2.3 Clock Control Register (ICCR) ..................................................................................................... 22.2.4 Address Register (IADR) ............................................................................................................. 22.2.5 Data Register (IDAR) ................................................................................................................... 22.3 I2C Interface Operation ..................................................................................................................... 424 426 427 429 432 434 435 436 CHAPTER 23 CHIP SELECTION FACILITY ................................................................... 439 23.1 Overview of Chip Selection Facility ................................................................................................... 23.2 Registers of Chip Selection Facility .................................................................................................. 23.2.1 Chip Select Area MASK Register (CMRx) ................................................................................... 23.2.2 Chip Selection Area Register (CARx) .......................................................................................... 23.2.3 Chip Selection Control Register (CSCR) ..................................................................................... 23.2.4 Chip Selector Active Level Register (CALR) ................................................................................ 23.3 Operation of the Chip Selection Facility ............................................................................................ 440 441 442 443 444 445 446 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION .......................................... 449 24.1 Overview of Address Match Detection Function ............................................................................... 24.2 Block Diagram of Address Match Detection Function ....................................................................... 24.3 Configuration of Address Match Detection Function ......................................................................... 24.3.1 Address Detection Control Register (PACSR) ............................................................................. 24.3.2 Detect Address Setting Registers (PADR0H and PADR1) ......................................................... 24.4 Explanation of Operation of Address Match Detection Function ...................................................... 24.4.1 Example of using Address Match Detection Function ................................................................. 24.5 Program Example of Address Match Detection Function ................................................................. 450 451 452 453 455 457 458 463 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE ................................. 465 25.1 Overview of ROM Mirror Function Select Module ............................................................................. 466 25.2 ROM Mirror Function Select Register (ROMM) ................................................................................ 467 CHAPTER 26 2M BIT FLASH MEMORY ......................................................................... 469 26.1 Overview of 2M Bit Flash Memory .................................................................................................... 26.2 Sector Configuration of 2M Bit Flash Memory .................................................................................. 26.3 Control Status Register (FMCS) ....................................................................................................... 26.4 Method for Starting the Flash Memory's Automatic Algorithm .......................................................... 26.5 Verifying the Execution State of the Automatic Algorithm ................................................................. 26.5.1 Data Polling Flag (DQ7) ............................................................................................................... 26.5.2 Toggle Bit Flag (DQ6) .................................................................................................................. 26.5.3 Timing Limit Excess Flag (DQ5) .................................................................................................. x 470 471 472 475 476 478 480 481 26.5.4 Sector Erase Timer Flag (DQ3) .................................................................................................... 482 26.6 Flash Memory Write/Erase Operations .............................................................................................. 483 26.6.1 Setting the Flash Memory to Read/Reset State ........................................................................... 484 26.6.2 Writing Data to Flash Memory ...................................................................................................... 485 26.6.3 Erasing All Data in the Flash Memory (Chip Erase) ..................................................................... 487 26.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) .............................................................. 488 26.6.5 Suspending Sector Erasure for the Flash Memory ....................................................................... 490 26.6.6 Resuming the Sector Erasure of Flash Memory ........................................................................... 491 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION ........................................................................................... 493 27.1 Basic Configuration ............................................................................................................................ 494 27.2 Oscillation Clock Frequency and Serial Clock Input Frequency ........................................................ 496 27.3 System Configuration of Flash Microcomputer Programmer ............................................................. 497 27.4 Examples of Serial Programming Connection ................................................................................... 498 27.4.1 Example of Connection in Single-Chip Mode (Using Power from User System) ......................... 499 27.4.2 Example of Minimum Connection with Flash Microcomputer Programmer (Using Power from the User System) ........................................................................................................................................ 501 APPENDIX .......................................................................................................................... 503 APPENDIX A Memory Map ......................................................................................................................... 504 APPENDIX B Instructions ............................................................................................................................ 515 B.1 Instruction Types ............................................................................................................................. 516 B.2 Addressing ...................................................................................................................................... 517 B.3 Direct Addressing ............................................................................................................................ 519 B.4 Indirect Addressing ......................................................................................................................... 524 B.5 Execution Cycle Count .................................................................................................................... 530 B.6 Effective Address Field ................................................................................................................... 533 B.7 How to Read the Instruction List ..................................................................................................... 534 B.8 F2MC-16LX Instruction List ............................................................................................................. 537 B.9 Instruction Map ................................................................................................................................ 551 INDEX .................................................................................................................................. 573 xi xii CHAPTER 1 OVERVIEW OF MB90470 This chapter gives an overview of MB90470, including its basic characteristics, block diagram, and its functions. 1.1 "Overview" 1.2 "Block Diagram of MB90470" 1.3 "Package Dimensions" 1.4 "Pin Assignment" 1.5 "Pin Functions" 1.6 "I/O Circuit Type" 1.7 "Handling of the Devices" 1 CHAPTER 1 OVERVIEW OF MB90470 1.1 Overview MB90470 is a 16-bit microcontroller designed for applications such as consumer devices requiring high-speed real-time processing. MB90470 functions are suitable for controlling PHS, cellular phones, CD-ROMs, and VCRs. ■ MB90470 features The MB90470 has the following features: • • 50.0 ns/5 MHz oscillation multiplied by 4 (20 MHz/3.3 0.3 V for internal operation) • 62.5 ns/4 MHz oscillation multiplied by 4 (16 MHz/3.0 0.3 V for internal operation) • PLL clock multiply system • Maximum memory space: 16 MB • Instruction system optimized for control applications • 2 Minimum instruction execution time • Available data types: bit, byte, word, long word • Standard addressing modes: 23 types • Improved high-precision operation using a 32-bit accumulator • Signed multiply and divide operations, extensive RETI instruction Instruction system supporting multitasking in high-level languages (such as C) • Use of a system stack pointer • Symmetry of instruction sets and barrel shift instructions • Multi-bus and non-multi-bus support • Program patch function (for two address pointers) • Improved execution speed: 4-byte queue • Improved interrupt function (priority is a programmable setting of up to 8 levels): 8 external interrupts • Data transfer function (µDMAC): maximum of 16 channels • Built-in ROM (FLASH version: 256 KB; MASKROM version: 128 KB/256 KB) • Built-in RAM: 10 KB/16 KB • General-purpose ports: maximum of 84 ports (input pull-up resistor settings available for 16 ports, output open drain settings available for 14 ports, and output open drain for 2 ports) • A/D converter (RC step-by-step compare type): 8 channels (resolution: 10 bits; conversion time: 4.65 µs (20 MHz operation)) • I2C interface: 1 channel • µPG: 1 channel • UART: 1 channel • I/O extensive serial interface (SIO): 2 channels CHAPTER 1 OVERVIEW OF MB90470 • 16-bit PPG: 3 channels (8 bits x 6 channels; mode switching function of 16 bits x 3 channels) • 8/16-bit U/D timer: 1 channel • 16-bit PWC: 3 channels (function that compares input by two of the three channels is installed) • 16-bit reload timer: 1 channel(8 bits x 2 channels; mode switching function of 16 bits x 1 channel) • 16-bit input/output timer (input capture x 2 channels; output compare x 6 channels; free-run timer x 1 channel) • Built-in dual-system clock generator • Power-saving mode (e.g., stop, sleep, CPU intermittent operation mode, watch mode) • Package: QFP100/LQFP100 • CMOS technology • Available for 3-V single power supply (some pins supply 3/5 V of power from a dual power supply to support 5-V I/F) 3 CHAPTER 1 OVERVIEW OF MB90470 ■ Product configuration Table 1.1-1 "MB90470-series product configuration" is an outline of the MB90470-series product configuration. Table 1.1-1 MB90470-series product configuration MB90V470B MB90F474L MB90F474H ROM capacity - FLASH 256KB FLASH 256KB RAM capacity 16KB 16KB 16KB EVA function 3-V/5-V version of user pin*1 Description Emulator-dedicated power supply*2 FLASH product Low-voltage version (VCC=2.4 V; f=10 MHz or less) Provided FLASH product High-speed version (f=20 MHz) - - MB90473 MB90474 MB90477 MB90478 ROM capacity MASKROM 128KB MASKROM 256KB MASKROM 256KB MASKROM 256KB RAM capacity 10KB 16KB 8KB 8KB MASK product MASK product MASK product I2C interface not installed Provided - - Description MASK product Emulator-dedicated power supply*2 Provided *1: User pins: P20 to P27, P30 to P37, P40 to P47, P70 to P77 *2: The setting of dip switch S2 is applicable during use of emulation pod MB2145-507. For more information, refer to the MB2145-507 hardware manual (Section 2.7, "Emulator-specific Power Supply"). Note: Writing FLASH requires VCC = 3 V or more. 4 CHAPTER 1 OVERVIEW OF MB90470 1.2 Block Diagram of MB90470 This section has a block diagram of the MB90470. ■ Block diagram of MB90470 Figure 1.2-1 "Block diagram of MB90470" is a block diagram of the MB90470. Figure 1.2-1 Block diagram of MB90470 X0,X1,RST 8 X0A,X1A MD2,MD1,MD0 Clock control circuit CPU FMC16LX-series core Interrupt controller RAM ROM PPG0,1 PPG2,3 PPG4,5 8/16-bit PPG µDMA SIN0 SOT0 SCK0 Internal data bus Communication prescaler 2 UART SIN1,2 SOT1,2 SCK1,2 8/16-bit U/D counter AIN0,1 BIN0,1 ZIN0,1 µPG EXTC MT00 MT01 Chip select CS0,1,2,3 I/O extensive serial interface × 2 channels Input/output timer AVCC AVRH AVSS ADTG AN0-7 A/D converter (10 bits) 16-bit input capture × 2 16-bit output compare × 6 16-bit free-running timer PWC0 PWC1 PWC2 16-bit PWC × 3 channels IN0,1 OUT0,1,2,3,4,5 16-bit reload timer TIN0 TOT0 IIC interface SCL SDA External interrupt 8 IRQ0-7 I/O port 8 8 8 8 8 8 8 8 8 8 4 P00 P10 P20 P30 P40 P50 P60 P70 P80 P90 PA0 P07 P17 P27 P37 P47 P57 P67 P77 P87 P97 PA3 P00 to P07(×8) P10 to P17(×8) P40 to P47(×8) P70 to P75(×6) P76, 77(×2) : : : : : With register for input pull-up resistor settings With register for input pull-up resistor settings With register for open drain settings Open drain with register Open drain Note: In the Figure 1.2-1 "Block diagram of MB90470", the I/O port shares a pin with each built-in function block. The pin cannot be used as an I/O port if it is used as a built-in module pin. 5 CHAPTER 1 OVERVIEW OF MB90470 1.3 Package Dimensions MB90470 has two types of packages. ■ Package dimensions (LQFP-100) Figure 1.3-1 "Package dimensions of LQFP-100 type" is a diagram of the package dimensions of the LQFP-100 type. Figure 1.3-1 Package dimensions of LQFP-100 type 6 CHAPTER 1 OVERVIEW OF MB90470 ■ Package dimensions (QFP-100) Figure 1.3-2 "Package dimensions of QFP-100 type" is a diagram of the package dimensions of the QFP-100 type. Figure 1.3-2 Package dimensions of QFP-100 type 7 CHAPTER 1 OVERVIEW OF MB90470 1.4 Pin Assignment This section shows the MB90470 pin assignments for two types of packages. ■ Pin assignment diagram (QFP-100) Figure 1.4-1 "Pin assignment diagram of MB90470 (QFP-100)" is a pin assignment diagram for the QFP-100 type. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 QFP-100 (TOP VIEW) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P74/TOT0 P75/PWC2 P76/SCL P77/SDA AVcc AVRH AVss P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 Vss P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1 P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00 P44/A12/MT01 Vcc5 P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 P71/SOT0 P72/SCK0 P73/TIN0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 Vcc3 X1 X0 Vss Figure 1.4-1 Pin assignment diagram of MB90470 (QFP-100) 8 X0A X1A P57/CLK RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 P82/IRQ2 MD2 CHAPTER 1 OVERVIEW OF MB90470 ■ Pin assignment diagram (LQFP-100) Figure 1.4-2 "Pin assignment diagram of MB90470 (LQFP-100)" is a pin assignment diagram for the LQFP-100 type. LQFP-100 (TOP VIEW) 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 RST P56/RDY P55/HAK P54/HRQ P53/WRH P52/WRL P51/RD P50/ALE PA3/OUT3 PA2/OUT2 PA1/OUT1 PA0/OUT0 P97/IN1 P96/IN0 P95/PPG5 P94/PPG4 P93/FRCK/ADTG/CS3 P92/SCK1/CS2 P91/SOT1/CS1 P90/SIN1/CS0 P87/IRQ7 P86/IRQ6 P85/IRQ5 P84/IRQ4 P83/IRQ3 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 P71/SOT0 P72/SCK0 P73/TIN0 P74/TOT0 P75/PWC2 P76/SCL P77/SDA AVcc AVRH AVss P60/AN0 P61/AN1 P62/AN2 P63/AN3 Vss P64/AN4 P65/AN5 P66/AN6 P67/AN7 P80/IRQ0 P81/IRQ1 MD0 MD1 MD2 P82/IRQ2 P22/A18 P23/A19 P24/A20/PPG0 P25/A21/PPG1 P26/A22/PPG2 P27/A23/PPG3 P30/A00/AIN0 P31/A01/BIN0 Vss P32/A02/ZIN0 P33/A03/AIN1 P34/A04/BIN1 P35/A05/ZIN1 P36/A06/PWC0 P37/A07/PWC1 P40/A08/SIN2 P41/A09/SOT2 P42/A10/SCK2 P43/A11/MT00 P44/A12/MT01 Vcc5 P45/A13/EXTC P46/A14/OUT4 P47/A15/OUT5 P70/SIN0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 P21/A17 P20/A16 P17/AD15/D15 P16/AD14/D14 P15/AD13/D13 P14/AD12/D12 P13/AD11/D11 P12/AD10/D10 P11/AD09/D09 P10/AD08/D08 P07/AD07/D07 P06/AD06/D06 P05/AD05/D05 P04/AD04/D04 P03/AD03/D03 P02/AD02/D02 P01/AD01/D01 P00/AD00/D00 Vcc3 X1 X0 Vss X0A X1A P57/CLK Figure 1.4-2 Pin assignment diagram of MB90470 (LQFP-100) 9 CHAPTER 1 OVERVIEW OF MB90470 1.5 Pin Functions This section explains the MB90470 pin functions. ■ Pin functions Table 1.5-1 "Pin functions" explains MB90470 pin function. Table 1.5-1 Pin functions LQFP QFP Pin name Circuit 80 82 X0 A Oscillation pin 81 83 X1 A Oscillation pin 78 80 X0A A 32-kHz oscillation pin 77 79 X1A A 32-kHz oscillation pin 75 77 RST B Reset input pin P00 to P07 83 | 90 91 | 98 99 100 1 2 85 | 92 93 | 100 1 | 4 AD00 to AD07 General-purpose input/output port. With a register for pull-up resistor settings (RDR0), a pull-up resistor can be set to the enabled state (RD00-07="1") (disabled for the output setting). Functions as the lower input/output pin of an external address and data bus in the multiplex mode. D00 to D07 Functions as the lower output pin of an external data bus in the nonmultiplex mode. P10 to P17 General-purpose input/output port. With a register for pull-up resistor settings (RDR1), a pull-up resistor is set to the enabled state (RD10-17="1") (disabled for the output setting). AD08 to AD15 C (CMOS) Functions as the upper input/output pin of an external address and data bus in the multiplex mode. D08 to D15 Functions as the upper output pin of an external data bus in the nonmultiplex mode. P20 to P23 General-purpose input/output port. Functions as the general-purpose input/output port in the external bus mode if the bit corresponding to external address output control register (HACR) is set to "1". A16 to A19 A16 to A19 10 C (CMOS) Function E (CMOS/H) Functions as the upper output pin of an address (A16 to A19) in the multiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". Functions as the upper output pin of an address (A16 to A19) in the non-multiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP 3 | 6 QFP 5 | 8 Pin name Circuit P24 to P27 General-purpose input/output port. Functions as the general-purpose input/output port in the external bus mode if the bit corresponding to external address output control register (HACR) is set to "1". A20 to A23 Functions as the upper output pin of an address (A20 to A23) in the multiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". E (CMOS/H) Functions as the upper output pin of an address (A20 to A23) in the non-multiplex mode if the bit corresponding to external address output control register (HACR) is set to "0". A20 to A23 PPG0 to PPG3 Functions as the PPG-timer output pin. P30 7 9 A00 General-purpose input/output port. E (CMOS/H) AIN0 10 A01 General-purpose input/output port E (CMOS/H) BIN0 11 12 12 13 14 A02 General-purpose input/output port E (CMOS/H) 8/16-bit up-down timer input pin (channel 0) P33 General-purpose input/output port A03 E (CMOS/H) 8/16-bit up-down timer input pin (channel 1) P34 General-purpose input/output port A04 E (CMOS/H) A05 General-purpose input/output port E (CMOS/H) A06, A07 PWCO, PWC1 General-purpose input/output port E (CMOS/H) P40 16 18 A08 SIN2 Functions as an external address pin in the non-multi-bus mode. 8/16-bit up-down timer input pin (channel 1) P36,37 16 17 Functions as an external address pin in the non-multi-bus mode. 8/16-bit up-down timer input pin (channel 1) ZIN1 14 15 Functions as an external address pin in the non-multi-bus mode. AIN1 P35 15 Functions as an external address pin in the non-multi-bus mode. ZIN0 BIN1 13 Functions as an external address pin in the non-multi-bus mode. 8/16-bit up-down timer input pin (channel 0) P32 10 Functions as an external address pin in the non-multi-bus mode. 8/16-bit up-down timer input pin (channel 0) P31 8 Function Functions as an external address pin in the non-multi-bus mode. Functions as the PWC input pin. General-purpose input/output port G (CMOS/H) Functions as an external address pin in the non-multi-bus mode. Simple serial I/O input pin 11 CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP QFP Pin name Circuit P41 17 19 A09 General-purpose input/output port F (CMOS) SOT2 20 A10 General-purpose input/output port G (CMOS/H) SCK2 21 22 A11, A12 General-purpose input/output port F (CMOS) P45 24 A13 General-purpose input/output port G (CMOS/H) P46, P47 25 26 A14, A15 General-purpose input/output port F (CMOS) OUT4/OUT5 D (CMOS) 70 ALE P51 69 70 71 72 D (CMOS) 71 General-purpose input/output port. It functions as the ALE pin in the external bus mode. Functions as the address read permission signal (ALE) pin in the external bus mode. General-purpose input/output port. It functions as the RD pin in the external bus mode. RD Functions as the read strobe output (RD) pin in the external bus mode. P52 General-purpose input/output port. It functions as the WRL pin in the external bus mode if the WRE bit of the EPCR register is set to "1". D (CMOS) 72 WRL In the external bus mode, functions as the write strobe output (WRL) pin of data on the lower side. This pin functions as a general-purpose input/output port if the WRE bit of the EPCR register is set to "0". P53 General-purpose input/output port. It functions as the WRH pin in the external bus mode of a 16-bit bus width if the WRE bit of the EPCR register is set to "1". D (CMOS) 73 WRH Functions as the write strobe output (WRH) pin of data from the upper side in the external bus mode of a 16-bit bus width, and functions as a general-purpose input/output port if the WRE bit of the EPCR register is set to "0". P54 General-purpose input/output port. It functions as the HRQ pin in the external bus mode if the HDE bit of the EPCR register is set to "1". D (CMOS) 74 HRQ 12 Functions as an external address pin in the non-multi-bus mode. Functions as the output pin for output compare events. P50 68 Functions as an external address pin in the non-multi-bus mode. µPG input pin EXTC 23 24 Functions as an external address pin in the non-multi-bus mode. µPG output pin MT00, MT01 22 Functions as an external address pin in the non-multi-bus mode. Simple serial I/O clock input/output pin P43, P44 19 20 Functions as an external address pin in the non-multi-bus mode. Simple serial I/O output pin P42 18 Function Functions as the hold request input (HRQ) pin in the external bus mode, and functions as a general-purpose input/output port if the HDE bit of the EPCR register is set to "0". CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP QFP Pin name Circuit General-purpose input/output port. It functions as the HAK pin in the external bus mode if the HDE bit of the EPCR register is set to "1". P55 73 74 76 D (CMOS) 75 HAK Functions as the hold acknowledge output (HAK) pin in the external bus mode, and functions as a general-purpose input/output port if the HDE bit of the EPCR register is set to "0". P56 General-purpose input/output port. It functions as the RDY pin in the external bus mode if the RYE bit of the PCR register is set to "1". D (CMOS) 76 RDY Functions as the external ready input (RDY) pin in the external bus mode, and functions as a general-purpose input/output port if the RYE bit of the EPCR register is set to "0". P57 General-purpose input/output port. It functions as the CLK pin in the external bus mode if the CKE bit of the EPCR register is set to "1". D (CMOS) 78 CLK 36 | 39 38 | 41 41 | 44 43 | 46 25 27 P60 to P63 AN0 to AN3 P64 to P67 AN4 to AN7 P70 SIN0 P71 26 28 SOT0 P72 27 29 SCK0 P73 28 30 TIN0 P74 29 31 TOT0 P75 30 32 PWC2 H (CMOS) H (CMOS) 33 SCL 34 SDA General-purpose input/output port Functions as an analog input pin. General-purpose input/output port Functions as an analog input pin. General-purpose input/output port F (CMOS) General-purpose input/output port G (CMOS) General-purpose input/output port G (CMOS/H) General-purpose input/output port F (CMOS) General-purpose input/output port F (CMOS) General-purpose input/output port Functions as the UART data input pin. Functions as the UART data output pin. Functions as the UART clock input/output pin. Functions as the event input pin of a 16-bit reload timer. Functions as the output pin of a 16-bit reload timer. Functions as the PWC input pin. General-purpose input/output port I (NMOS/H) P77 32 Functions as the machine cycle clock output (CLK) pin in the external bus mode, and functions as a general-purpose input/output port if the CKE bit of the EPCR register is set to "0". G (CMOS/H) P76 31 Function Functions as the input/output pin of I2C interface clock. Set the port output to Hi-Z in I2C interface operation. General-purpose input/output port I (NMOS/H) Functions as the input/output pin of the I2C interface data. Set the port output to Hi-Z in I2C interface operation. 13 CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP QFP Pin name Circuit 45 46 47 48 P80, P81 E (CMOS/H) 50 | 55 52 | 57 IRQ0, IRQ1 P82 to P87 IRQ2 to IRQ7 E (CMOS/H) P90 56 57 58 59 SIN1 E (CMOS/H) SOT1 SCK1 D (CMOS) Chip select 1 General-purpose input/output port E (CMOS/H) P93 General-purpose input/output port E (CMOS/H) 61 62 P95 63 PPG5 P96 64 IN0 P97 65 IN1 14 Functions as the input/output pin of a simple serial IO clock. Chip select 2 PPG4 63 Functions as the output pin of simple serial IO data. CS2 P94 62 Functions as the input pin of simple serial IO data. General-purpose input/output port CS3 61 Functions as the external interrupt input pin. P91 ADTG 60 General-purpose input/output port Chip select 0 FRCK 59 Functions as the external interrupt input pin. CS0 P92 60 General-purpose input/output port General-purpose input/output port CS1 58 Function Functions as the external clock input pin when a free-running timer is used. Functions as the external trigger input pin when an A/D converter is used. Chip select 3 D (CMOS) General-purpose input/output port D (CMOS) General-purpose input/output port. E (CMOS/H) General-purpose input/output port E (CMOS/H) General-purpose input/output port Functions as the output pin of the PPG timer. Functions as the output pin of the PPG timer. Captured as trigger input of input capture channel 0. Captured as trigger input of input capture channel 1. 64 | 67 66 | 69 PA0 to PA3 33 35 AVCC - Power supply pin of A/D converter 34 36 AVRH - External reference power supply pin of A/D converter 35 37 AVSS - Power supply pin of A/D converter 47 | 49 49 | 51 MD0 to MD2 J (CMOS/H) OUT0 to OUT3 General-purpose input/output port D (CMOS) Functions as the output pin of output compare events. Input pin name to specify the operation mode. CHAPTER 1 OVERVIEW OF MB90470 Table 1.5-1 Pin functions (Continued) LQFP QFP Pin name Circuit Function 82 84 VCC3 - Power supply pin of 3.3 21 23 VCC5 - Shared power supply pin of 3.3 9 40 79 11 42 81 VSS - Power supply input (GND) 0.3 V (VCC3) 0.3 V or 5.0 0.5 V (VCC5) Note: 1. If only a power supply of 3.3 V is used, apply the same voltage to both VCC3 and VCC5. 2. If using two power supplies, apply voltage to each of VCC3 and VCC5. For two power supplies, 32 pins (P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/A07/PWC1, P40/A08/SIN2 to P47/ A15/OUT5, and P70/SIN0 to P77/SDA) in total are used with a 5-V interface at all operation mode. Note that all other pins use a 3-V interface. If two power supplies are used, neither of the following cases is allowed: only a 5 V power supply is turned on; or only a 3-V power supply is turned on. Turn on both power supplies. (Fujitsu recommends that the 3-V power supply is turned on first.) 15 CHAPTER 1 OVERVIEW OF MB90470 1.6 I/O Circuit Type This section explains the I/O circuit type of MB90470 pins. ■ I/O circuit type Table 1.6-1 "I/O circuit type" summarizes the I/O circuit type of MB90470 pins. Table 1.6-1 I/O circuit type Class Circuit Description • • Oscillation feedback resistor: • X1, X0: about 1 MΩ • X1A, X0A: 10 MΩ Use of standby control • • • Hysteresis input with pull-up Resistor: about 50 KΩ Use of standby control • • • Use of input pull-up resistor control CMOS level input/output Resistor: about 50 KΩ X1,X1A X0,X0A A Standby control signal B Hysteresis input Control C CMOS 16 CHAPTER 1 OVERVIEW OF MB90470 Table 1.6-1 I/O circuit type (Continued) Class Circuit Description CMOS level input/output D CMOS • • Hysteresis input CMOS level output • • CMOS level input/output Use of open-drain control • • • CMOS level output Hysteresis input Use of open-drain control E CMOS Open-drain control signal F CMOS Open-drain control signal G Hysteresis input 17 CHAPTER 1 OVERVIEW OF MB90470 Table 1.6-1 I/O circuit type (Continued) Class Circuit Description • • CMOS level input/output Analog input • • Hysteresis input N-channel open-drain output H CMOS Analog input Digital output I Hysteresis input (FLASH product) • CMOS level input • High-voltage control provided for FLASH test (FLASH product) Control signal J Mode input Dispersion resistor (Mask product) • Hysteresis input port (Mask product) Hysteresis input 18 CHAPTER 1 OVERVIEW OF MB90470 1.7 Handling the Device This section gives notes on handling the MB90470. ■ Notes on handling the device ❍ Latch-up prevision and power-on sequence Some CMOS ICs may cause latch-up symptoms as described below: • If voltages higher than VCC or lower than VSS are applied to the input and output pins. • If the applied voltage ranging between VCC and VSS is higher than the rated voltage. • If voltage VCC is applied following the AVCC power supply Analog voltage must be supplied at the same time as VCC, or it must be applied after the digital power supply is turned on. (Turn off the analog power supply before or at the same time as the power supply is turned off.) Once a latch-up occurs, the power supply current increases rapidly, possibly causing heat damage in the element. Be sure to prevent such damage during use. ❍ Processing unused input pins Keeping an unused input pin open may cause an error in operation. Apply pull-up or pull-down to such pins as necessary. For an unused A/D converter, connect it so that AVCC = AVRH = VCC, and AVSS = VSS. ❍ Handling a power supply pin (VCC/VSS) If multiple VCC and/or VSS are used, all power supply pins must be connected with a power supply and ground externally in consideration of device design in order to decrease latch-up and unnecessary radiation. Be sure to connect all power supply pins to the power supply or ground so that the total output current specification is not exceeded. As much as possible, the power supply source must be connected with VCC/VSS of this device at the lowest impedance. Fujitsu recommends placing a bypass condenser of 0.1 µF between VCC and VSS. ❍ Crystal oscillation circuit Noise around the X0/X1 or X0A/X1A pins, if generated, may cause an error during operation on this device. X0/X1, X0A/X1A and a crystal oscillator (or ceramic oscillator), or a bypass condenser to ground must be arranged as close to each other as possible to prevent crossover between them. Printed board artwork is strongly recommended since it is expected to provide stable operation. ❍ Notes on using external clock Use of the external clock requires a connection with an external pin, as shown in Figure 1.7-1 "Use of external clock". Figure 1.7-1 "Use of external clock" shows a connection with the external clock (f=20 MHz or below) 19 CHAPTER 1 OVERVIEW OF MB90470 Figure 1.7-1 Use of external clock X0 OPEN X1 ❍ Note on operations during PLL clock mode If the PLL clock mode is selected, the microcontroller attempt to be working with the selfoscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed. ■ Notes on handling the power supply ❍ Stabilizing the power supply Even in the range of VCC power supply voltage, a rapid change in the power supply may cause a misoperation. Fujitsu recommends that, as a reference for stabilization, the VCC ripple variation (P-P value) in the commercial frequency (50/60 MHz) must be 10% of the standard VCC value or lower, or the transient variation must be 0.1 V/ms in instantaneous variation including power supply switching. ❍ Notes on using two power supplies The MB90470 series usually uses the 3-V power supply as the main power source. With VCC3 = 3 V and VCC5 = 5 V, however, it can interface with P20/A16 to P27/A23/PPG3, P30/A00/AIN0 to P37/A07/PWC1, P40/A08/SIN2 to P47/A15/OUT5, and P70/SIN0 to P77/SDA for the 5-V power supply separately from the 3-V power supply at all operation mode. Note, however, that the analog power supply of the A/D converter (e.g., AVCC and AVSS) can be used only as 3-V power supplies. ❍ Crystal oscillation circuit using low voltage At voltages below 2.0 V, some external crystal oscillators may not work when the power supply is turned on. Thus, Fujitsu recommends using the external clock. ❍ To use this product, which is two system products, as a single system, use it under the conditions of X0A = VSS and X1A = OPEN. ❍ For serial writing to flash memory, always make sure that the operating voltage VCC is between 3.13 V and 3.6 V. For normal writing to flash memory, always make sure that the operating voltage VCC is between 3 V and 3.6 V. 20 CHAPTER 2 CPU This chapter explains CPU specifications, memory, and the functions of registers to provide readers with a better understanding of the MB90470 functions. 2.1 "Overview of CPU Specifications" 2.2 "Memory Space" 2.3 "CPU Registers" 2.4 "Prefix Codes" 21 CHAPTER 2 CPU 2.1 Overview of CPU Specifications This section gives an overview of the CPU specifications. ■ Overview of CPU specifications The F2MC-16LX CPU core is a 16-bit CPU designed for devices that requires high-speed realtime processing. The F2MC-16LX instruction set is designed for controller applications, providing high-speed and high-efficiency control processes. In addition to 16-bit data processing, the F2MC-16LX CPU core can provide 32-bit data processing with an installed internal 32-bit accumulator (some instructions perform 32-bit data processing). Memory spaces are a maximum of 16 MB (expandable) and can be accessed by using a linear pointer or bank. Based on the F2MC8 AT architecture, its instruction system is improved because of increasing the instructions supporting high-level languages, expanding addressing modes, improving multiply and divide operation instructions, and enhancing bit processing. The F2MC-16LX CPU has the following features: ❍ Minimum instruction execution time • 50.0 ns/5 MHz oscillation multiplied by 4 (20 MHz/3.3 ± 0.3 V for internal operation) • 62.5 ns/4 MHz oscillation multiplied by 4 (16 MHz/3.0 ± 0.3 V for internal operation) • PLL clock multiply scheme ❍ Maximum memory space: 16 MB, accessing by using a linear pointer or bank ❍ Instruction system optimized for control applications • Data types available: bit, byte, word, long word • Standard addressing mode: Use of 23-type, 32-bit accumulator for enhancing high-precision operation • Signed multiply and divide operations, expanded RETI instruction ❍ Enhanced interrupt function: 8 priority levels (programmable) ❍ CPU independent automatic transfer function: µDMA up to 16 channels ❍ Multitasking-compatible instruction system in high-level language (C) Use of system stack pointers, symmetrical instruction set, and barrel shift instruction ❍ Improved execution speed: 4-byte queue 22 CHAPTER 2 CPU 2.2 Memory Space The F2MC-16LX CPU has a 16-MB memory space, to which all input to and output from the F2MC-16LX CPU controlled data program is allocated. CPU has a 24-bit address bus to access each resource. ■ Memory map Figure 2.2-1 "Example showing correspondence between F2MC-16LX system and memory map" shows the F2MC-16LX system and the associated memory map. Figure 2.2-1 Example showing correspondence between F2MC-16LX system and memory map F2MC-16LX CPU Program FFFFFFH FF8000H Data 810000H Interrupt 800000H Program area Data area [Device] Peripheral circuit Generalpurpose port 0000C0H 0000B0H 000020H 000000H Interrupt controller Peripheral circuit General-purpose port ■ Address generation type The F2MC-16LX CPU has two types of address generation. One is linear addressing that specifies all 24-bit addresses with instructions. The other is bank addressing that specifies upper 8-bit addresses with appropriate bank registers and lower 16-bit addresses with instructions. Linear addressing has two types: one uses operands to directly specify 24-bit addresses; the other refers to contents of the lower 24 bits in a 32-bit general-purpose register as addresses. ❍ Linear addressing (specified with 24-bit operand) Figure 2.2-2 "Linear addressing (specified with 24-bit operand)" shows an example of linear addressing scheme specified with 24-bit operands. 23 CHAPTER 2 CPU Figure 2.2-2 Linear addressing (specified with 24-bit operand) JMPP 123456H Previous program counter 17 17452DH 452D 123456H New program counter 12 JMPP 123456H Next instruction 3456 ❍ Linear addressing (indirectly specified using 32-bit register) Figure 2.2-3 "Linear addressing (indirectly specified using 32-bit register)" shows an example of linear addressing scheme indirectly specified using a 32-bit register. Figure 2.2-3 Linear addressing (indirectly specified using 32-bit register) MOV A, @RL1+7 Old AL 090700H XXXX 3A +7 RL1 (Upper 8 bits are ignored) New AL 240906F9 003A ■ Addressing type by bank Bank addressing divides a 16-MB space into 256 banks of 64 KB each, using five bank registers to specify banks for each space. • Program bank register (PCB) • Data bank register (DTB) • User stack bank register (USB) • System stack bank register (SSB) • Additional bank register (ADB) A 64-KB bank specified with PCB is called the program (PC) space. The PC space includes such information as instruction codes, vector tables, and immediate data. A 64-KB bank specified with DTB is called the data (DT) space. The DT space includes writable data, and internal and external resource control/data registers. A 64-KB bank specified with USP or SSP is called the stack (SP) space. The SP space is accessed if a stack access occurs by storing the push/pop instruction or interrupt register. The stack space to be accessed is determined by the S-flag in the condition code register. 24 CHAPTER 2 CPU A 64-KB bank specified with ADB is called the additional (AD) space. The AD space includes, for example, data that cannot be included in the DT space. As shown in Table 2.2-1 "Default Space", each addressing mode uses a default space defined in advance to improve the efficiency of coding instructions. If an addressing mode uses a space other than the default space, a prefix code corresponding to the bank must be specified prior to the instruction code, enabling access to any bank space corresponding to the prefix code. After resetting, DTB, USB, SSB and ADB are initialized to 00H, and PCB is initialized to the value specified by a reset vector. After resetting, each space for DT, SP and AD is allocated to bank 00H (000000H to 00FFFFH), and each PC space is allocated to the bank specified by the reset vector. Table 2.2-1 Default Space Default space Addressing mode Program space PC indirect, program access, branch instruction Data space Addressing mode using @RW0,@RW1, @RW4, and @RW5; @A; addr16; dir Stack space Addressing mode using PUCHW, POPW, @RW3, and @RW7 Additional space Addressing mode using @RW2 and @RW6 Figure 2.2-4 "Physical address in each space" shows an example of a memory space divided for a register bank. Figure 2.2-4 Physical address in each space FFFFFFH FF0000H Program space FEH : PCB (Program bank register) B3H : ADB (Additional bank register) 92H : USB (User stack bank register) 68H : DTB (Data bank register) 4BH : SSB (System stack bank register) Physical address B3FFFFH B30000H 92FFFFH 920000H Additional space User stack space 68FFFFH 680000H Data space 4BFFFFH 4B0000H System stack space 000000H 25 CHAPTER 2 CPU ■ Allocation of data of multi-byte length in memory space Figure 2.2-5 "Example of allocating data of multi-byte length in memory" shows the configuration of data of a multi-byte length in memory. The lower 8 bits of a data item are stored at address n, then address n+1, address n+2, address n+3, etc. Figure 2.2-5 Example of allocating data of multi-byte length in memory MSB 01010101 H 1100110 11111111 LSB 00000000 01010101 11001100 11111111 Address n 00000000 L Data is written in memory in sequence starting from the lower addresses. Thus, the lower 16 bits of a 32-bit data item is transferred first, followed by the upper 16 bits. If a reset signal is input immediately after writing the lower bit, writing the upper bit may fail. ■ Access to data of multi-byte length Figure 2.2-6 "Example of accessing data of multi-byte length" shows an example of accessing data of a multi-byte length. In this example, MOVW A, 030FFFFH is executed. Figure 2.2-6 Example of accessing data of multi-byte length H 80FFFFH AL before execution ?? ?? AL after execution 23H 01H 01H · · · 800000H 23H L 26 CHAPTER 2 CPU 2.3 CPU Registers The F2MC-16LX registers are divided into special registers inside CPU and generalpurpose registers on memory. The former is dedicated hardware inside the CPU, and its use is limited because of the CPU architecture. The latter shares CPU address spaces with RAM. A general-purpose register can be accessed without specifying an address, and a user can specify the use of a general-purpose register, which is the same as for memory spaces. ■ Dedicated registers The F2MC-16LX has the following 11 types of dedicated registers: • Accumulator (A = AH: AL): Two 16-bit accumulators (used as single 32-bit accumulator) • User stack pointer (USP): 16-bit pointer pointing to user stack area • System stack pointer (SSP): 16-bit pointer pointing to system stack area • Processor status (PS): 16-bit register indicating system status • Program counter: 16-bit register containing a program address • Program bank register: 8-bit register indicating a PC space • Data bank register: 8-bit register indicating a DT space • User stack bank register (USB): 8-bit register indicating a user stack space • System stack bank register (SSB): 8-bit register indicating a system stack space • Additional bank register (ADB): 8-bit register indicating an AD space • Direct page register (DPR): 8-bit register indicating a direct page Figure 2.3-1 "Configuration of dedicated registers" shows the configuration of the dedicated registers. Figure 2.3-1 Configuration of dedicated registers AH AL Accumulator USP User stack pointer SSP System stack pointer PS Processor status PC Program counter DPR Direct page register PCB Program bank register DTB Data bank register USB User stack bank register SSB System stack bank register ADB Additional data bank register 8 bits 32 bits 16 bits 27 CHAPTER 2 CPU ■ General-purpose register The F2MC-16LX general-purpose register resides on the main memory addresses: 000180H to 00037FH (maximum configuration). It uses a register bank register (RP) to indicate which part of addresses are currently used for register banks. Each bank has the three types of registers listed below. They are dependent on one another, as shown in Figure 2.3-2 "Configuration of general-purpose register". • R0 to R7: 8-bit general-purpose register • RW0 to RW7: 16-bit general-purpose register • RL0 to RL3: 32-bit general-purpose register Figure 2.3-2 "Configuration of general-purpose register" shows the configuration of a generalpurpose register. Figure 2.3-2 Configuration of general-purpose register MSB LSB 16 bits 000180H RP × 10H RW0 RL0 RW1 RW2 RL1 RW3 RW4 R1 R3 R2 RW5 R5 R4 RW6 R7 R6 RW7 RL2 The relationship between upper and lower bytes in a byte register and word register is represented with the following formula: RW(i + 4) = RW(i x 2 + 1) x 256 + R(i x 2) [i = 0 to 3]. The relationship of upper and lower bytes in Rli is represented with the following formula: RW(i) = RW(i x 2 + 1) x 65536 + RW(i x 2) [i = 0 to 3]. 28 CHAPTER 2 CPU 2.3.1 Accumulator (A) This section explains the accumulator (A) functions. ■ Accumulator (A) An accumulator (A) consists of two 16-bit arithmetic operation registers (AH/AL) that are used to store operation results and temporarily store data transfer results. For 32-bit data processing, AH is connected with AL. For word processing in the 16-bit data processing mode and for byte processing in the 8-bit data processing mode, only AL is used. Data stored in an accumulator (A) is used together with that in memory and registers (Ri, Rwi, Rli); and similar to F2MC-8L operations, the data item with a smaller word length is transferred to AL. This enables data items in AL before the transfer to be automatically transferred to AH (data hold function). The data hold function and operation between AL-AH support improvements in processing efficiency. During a transfer of a data item with a lower byte length to AL, a sign extension or zero extension is added to the data, and the data is saved in AL as a 16-bit data item. Also, data in AL is handled in either word lengths or byte lengths. If an arithmetic operation instruction of byte processing is executed in AL, the upper 8 bits in AL before the operation is ignored, and the upper 8 bits of operation results are reset to zero. Resetting an accumulator (A) does not initialized it, and it has an undefined value after the reset. Figure 2.3-3 "32-bit data transfer" shows 32-bit data transfer processing, and Figure 2.3-4 "ALAH transfer" shows AL-AH transfer processing. Figure 2.3-3 32-bit data transfer MOVL A,@RW1+6 A before execution XXXXH MSB XXXXH DTB A after execution 8F74H A6H LSB A61540H 8FH 74H A6153EH 2BH 52H 15H 38H +6 RW1 2B52H Figure 2.3-4 AL-AH transfer MOVW A,@RW1+6 A before execution XXXXH 1234H DTB A after execution 1234H MSB A6H 2B52H LSB A61540H 8FH 74H A6153EH 2BH 52H 15H 38H +6 RW1 29 CHAPTER 2 CPU 2.3.2 User Stack Pointer (USP) and System Stack Pointer (SSP) This section explains the functions of the user stack pointer (USP) and system stack pointer (SSP). ■ User stack pointer (USP) and system stack pointer (SSP) The user stack pointer (USP) and system stack pointer (SSP) are 16-bit registers indicating the push/pop instruction or the memory address to which data is saved or restored at subroutine execution. The USP register and SSP register are used in stack-type instructions. If the S-flag in the processor status register is set to "0", the USP register is enabled. If the S-flag is set to "1", SSP register is enabled (see Figure 2.3-1 "Configuration of dedicated registers"). If an interrupt is accepted, the S-flag is set and then the register value is saved in the memory area indicated by SSP in interrupt processing. SSP is used to execute stack processing of interrupt routines, and USP is used to execute stack processing other than interrupt routines. Only SSP is used if stack space is not divided. In stack processing, the address of upper 8 bits is indicated with SSP -> SSB and USP -> USB. Resetting USP and SSP does not initialize them, but each then has an undefined value. Figure 2.3-5 "Relationship between stack operation instructions and stack pointer" shows the relationship between stack operation instructions and the stack pointer where the S-flag is set to "0" and "1". Figure 2.3-5 Relationship between stack operation instructions and stack pointer Example 1: PUCHW A where S-flag is set to "0" MSB Before execution AL S-flag Before execution AL S-flag LSB A624H USB C6H USP F328H 0 SSB 56H SSP 1234H A624H USB C6H USP F328H 0 SSB 56H SSP 1234H C6F326H A6H 24H 561232H XX XX 561232H A6H 24H C6F326H XX XX Use of user stack because S-flag is set to "0" Example 2: PUCHW A where S-flag is set to "1" Before execution Before execution AL A624H USB C6H USP F328H S-flag 1 SSB 56H SSP 1234H AL A624H USB C6H USP F328H S-flag 1 SSB 56H SSP 1232H Use of system stack because S-flag is set to "1" Note: Use an even-numbered address for a stack pointer, in principle. 30 CHAPTER 2 CPU 2.3.3 Processor Status (PS) This section explains the processor status (PS) functions. ■ Processor status (PS) Processor status (PS) consists of bits used to execute CPU operations and bits indicating the CPU state. As shown in Figure 2.3-6, the upper byte in the PS register consists of a register bank pointer (RP) and interrupt level mask register (ILM). RP indicates the header address of a register bank. The lower byte of PS register is the condition code register (CCR) that includes a flag that is set and reset depending on execution results or interrupt events. Figure 2.3-6 "Configuration of processor status (PS)" shows the configuration of processor status (PS). Figure 2.3-6 Configuration of processor status (PS) 15 PS 13 12 0 8 7 ILM RP CCR ■ Condition code register (CCR) Figure 2.3-7 "Configuration of condition code register" shows the configuration of the condition code register. Figure 2.3-7 Configuration of condition code register Initial value 7 6 5 4 3 2 1 0 - I S T N Z V C - 0 1 * * * * * * Not defined ❍ I: Interrupt permission flag An interrupt other than software interrupt is permitted if the I-flag is set to "1" and masked if set to "0". The I-flag is cleared if reset. ❍ S: Stack flag If the S-flag is set to "0", USP is enabled as the stack operation pointer, and if it is set to "1", SSP is enabled. The S-flag is set if an interrupt or reset occurs. ❍ T: Sticky bit flag If the logic right shift instruction or arithmetic right shift instruction is executed, there is one or more "1" in the data shifted out by a carry operation, then the T-flag is set to either "1". Otherwise, it is set to "0". (if the shift amount is zero, it is set to "0".) ❍ N: Negative flag If MSB in operation results indicates "1", the N-flag is set. Otherwise, it is cleared. 31 CHAPTER 2 CPU ❍ Z: Zero flag If all operation results indicate zero, the Z-flag is set. Otherwise, it is cleared. ❍ V: Overflow flag If an overflow with a signed figure occurs as an operation execution result, the V-flag is set. Otherwise, it is cleared. ❍ C: Carry flag If a shift-in/shift-out operation occurs from MSB as operation execution results, the C-flag is set. Otherwise, it is cleared. ■ Register bank pointer (RP) The register bank pointer (RP) shows the relationship between the F2MC-16LX general-purpose register and internal RAM addresses. RP indicates the header memory address in the currently used register bank with the conversion formula [00180H + RP x 10H]. RP consists of 5 bits, with an address ranging from 00H to 1FH. A register bank can be allocated to a memory address in a range of 000180H to 00037FH. Even in this range, however, a register bank cannot be used as a general-purpose register if a register bank is not in internal RAM. An instruction transfers an immediate value of 8 bits to RP, but only the lower 5 bits are actually used. Figure 2.3-8 Configuration of register bank pointer (RP) Initial value 32 B4 B3 B2 B1 B0 0 0 0 0 0 CHAPTER 2 CPU ■ Interrupt level mask register (ILM) The interrupt level mask register (ILM) consists of 3 bits indicating the level of the CPU interrupt mask. Only an interrupt level higher than that represented with the 3 bits is accepted. The highest level is indicated with 0, the lowest level is indicated with 7 (see Table 2.3-1 ). Thus, to accept an interrupt, its level must be lower than the current ILM value. If an interrupt is accepted, its interrupt level value is set to ILM, and then any interrupts with the same or lower level of the interrupt priority are not accepted. ILM is initialized to zero by a reset. An instruction can transfer an 8-bit immediate value to the ILM register, but only the lower 3 bits are actually used. Figure 2.3-9 "Configuration of interrupt level mask register" shows the configuration of the interrupt level mask register. Table 2.3-1 has explanations of the level indicated in the interrupt level mask register (ILM). Figure 2.3-9 Configuration of interrupt level mask register ILM2 Initial value 0 ILM1 ILM0 0 0 Table 2.3-1 Level indicated by interrupt level mask register (ILM) ILM2 ILM1 ILM0 Level value Permitted interrupt level 0 0 0 0 Interrupt prohibited 0 0 1 1 0 only 0 1 0 2 Level value less than 1 0 1 1 3 Level value less than 2 1 0 0 4 Level value less than 3 1 0 1 5 Level value less than 4 1 1 0 6 Level value less than 5 1 1 1 7 Level value less than 6 33 CHAPTER 2 CPU 2.3.4 Program Counter (PC) This section explains the program counter (PC) functions. ■ Program counter (PC) PC is a 16-bit counter indicating the lower 16 bits in the memory address of an instruction code to be executed by CPU. An upper 8-bit address is indicated with the program count bank register (PCB). PC contents are updated by condition branch instructions, sub-routine call instructions, interrupts, or resets. It also may be used as a base pointer for operand access. Figure 2.3-10 "Program counter (PC) functions" explains the program counter (PC) functions. Figure 2.3-10 Program counter (PC) functions PCB FEH PC ABCDH Next instruction executed FEABCDH 34 CHAPTER 2 CPU 2.3.5 Program Count Bank Register (PCB) This section explains the program count bank register (PCB) functions. ■ Program count bank register (PCB) [Initial value: value in reset vector] The program count bank register (PCB) consists of the following registers: • Data bank register (DTB) < Initial value: 00H > • User stack bank register (USB) < Initial value: 00H > • System stack bank register (SSB) < Initial value: 00H > • Additional data bank register (ADB) < Initial value: 00H > Each bank register indicates memory banks to which PC, DT, SP (user), SP (system), and AD space are allocated. All bank registers has a length of 1 byte. They are initialized to 00H by a reset. Bank registers other than PCB can be read. PCB can be read, but writing to PCB is not permitted. PCB is updated either when the JMPP, CALLP, RETP, RETI, or RETF instruction that branches is executed, and it may then branch to an entire 16-MB space. PCB is also updated when an interrupt occurs. For information on the operation of each register, see Section 2.2 "Memory Space". 35 CHAPTER 2 CPU 2.3.6 Direct Page Register (DPR) This section explains the direct page register (DPR) functions. ■ Direct page register (DPR) [Initial value: 01H] The direct page register (DPR) specifies, as shown in Figure 2.3-11 "Generating a physical address in direct addressing mode", addresses 8 to 15 of an instruction operand in the direct addressing mode. DPR has a length of 8 bits, and is initialized to 01H by a reset. It also allows reading and writing by instructions. Figure 2.3-11 "Generating a physical address in direct addressing mode" illustrates the generation of a physical address in the direct addressing mode. Figure 2.3-11 Generating a physical address in direct addressing mode DTB register MSB 24-bit physical address 36 DPR register Direct address in instruction LSB CHAPTER 2 CPU 2.3.7 General-Purpose Register (Register Bank) This section explains the general-purpose register (register bank) functions. ■ General-purpose register (register bank) A register bank consists of 8 words and is used as a general-purpose register for arithmetic operation in the byte register (R0 - R7), word register (RW0 to RW7) and long-word register (RL0 to RL3). A register bank is also used as an instruction pointer. Table 2.3-2 "Register functions" lists the register functions and Figure 2.3-12 "Relationship among registers" shows the relationship between registers. Register bank values are not initialized by a reset, the same as for RAM spaces, but the state before resetting is kept. At power-on, however, the values are undefined. Table 2.3-2 Register functions R0 to R7 Used as operand in different instructions Note: R0 is used as the barrel shift counter or normalization instruction counter. RW0 to RW7 Used as a pointer or operand in different instructions Note: RW0 is used as a string instruction counter RL0 to RL3 Used as a long pointer or operand in different instructions Figure 2.3-12 Relationship among registers RW0 RW1 RW2 RW3 R0 R1 R2 R3 RL0 R4 RL1 R5 RL2 R6 RW6 RL3 RW7 R7 37 CHAPTER 2 CPU 2.4 Prefix Codes By inserting a prefix code before an instruction, part of an instruction operation may change. Three types of prefix code are provided: bulk select prefixes, common register bank prefixes, and flag change suppress prefixes. ■ Bank select prefix Memory space used in data access is determined according to the addressing mode. By inserting a bank select prefix before an instruction, the instruction may select the memory address used for data access regardless of the addressing mode in use. Table 2.4-1 "Bank select prefix" shows the relationship between the bank select prefix and a selected space. Table 2.4-1 Bank select prefix Bank select prefix Selected space PCC PC space DTB Data space ADB AD space SPB Either SSP or USP space is used depending on the stack flag value. Be careful when you are using the following instructions: ❍ String instruction (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) This uses bank registers specified with an operand regardless of a prefix. ❍ Stack operation instruction (PUCHW, POPW) SSV or USB is used depending on the S-flag, regardless of a prefix. ❍ I/O access instruction MOVA A, io/MOV io, A/MOVX A, io/MOVW A, io/MOVW io, A MOV io, #imm8/MOVW io, #imm8/MOBV A, io: bp/MOVB io: bp, A SETB io: bp/CLRB io: bp/BBC io:bp, rel/BBS io:bp, rel WBTC WBTS The I/O space of a bank is used regardless of whether a prefix is in an instruction. ❍ Flag change instruction (AND CCR,#imm8,OR CCR,#imm8) An instruction operation is normal, but a prefix affects the next instruction. ❍ POPW PS Regardless of prefix, SSB or USB is used depending on the S-flag. A prefix affects the next instruction. 38 CHAPTER 2 CPU ❍ MOV ILM, #imm8 If an instruction operation is normal as is, a prefix affects the next instruction. ❍ RETI SSB is used regardless of prefix. ■ Common register bank prefix (CMR) To facilitate data exchange between multiple tasks, the same register bank needs to be easily accessed regardless of each register bank pointer (RP) value. If CMR is inserted before an instruction that accesses a register bank, the instruction accesses the common bank with addresses ranging from 000180H to 00018FH (register bank selected if RP = 0) regardless of the current RP value. However, be careful when you are using the following instructions: ❍ String instruction (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request is issued while a string instruction with a prefix code is executed, the prefix code is disabled when the string instruction is returned after the interrupt is processed. Thus, with interrupt processing, the string instruction causes an error. Do not add a CMR prefix to such a string instruction. ❍ Flag change instruction (AND CCR, #imm8, OR CCR, #imm8) An instruction operation is normal, but a prefix affects the next instruction. ❍ MOV ILM, #imm8 An instruction operation is normal, but a prefix affects the next instruction. ■ Flag change suppress prefix To suppress a flag change, specify the flag change suppress prefix code (NCC). By inserting NCC before an instruction, the flag change caused by an instruction is suppressed. However, be careful if you use instructions listed below. ❍ String instruction (MOVS, MOVSW, SCEQ, SCWEQ, FILS, FILSW) If an interrupt request occurs when a string instruction with prefix code is executed, the prefix code is disabled when the string instruction is returned after the interrupt is processed. Thus, with interrupt processing, the string instruction causes an error. Do not add a CMR prefix to the above string instruction. ❍ Flag change instruction (AND CCR, #imm8, OR CCR, #imm8) An instruction operation is normal, but a prefix affects the next instruction. ❍ Interrupt instruction (INT #vct8, INT9, INT addr16, INTO addr24, POPW PS) CCR changes according to the instruction specification regardless of the prefix. ❍ JCTX@A CCR change according to the instruction specification regardless of the prefix. ❍ MOV ILM, #imm8 An instruction operation is normal, but a prefix affects the next instruction. 39 CHAPTER 2 CPU ■ Interrupt suppress instruction No interrupt requests are sampled on ten types of instruction. MOV ILM, #imm8/PCB/SPB/OR CCR, #imm8/NCC AND CCR, #imm8/ADB/CMR/POPW PS/DTB If an effective interrupt request is issued when any of above instructions is executed, an interrupt may be processed only if instructions other than the above are executed. For more information, see Figure 2.4-1 "Interrupt suppress instruction" Figure 2.4-1 Interrupt suppress instruction Interrupt suppress instruction (a) (a) Normal instruction Interrupt request Interrupt accept ■ Restrictions on interrupt suppress instruction and prefix instruction If a prefix code is inserted before an interrupt is suppressed, the prefix code affects up to the first instruction that appears after any code other than interrupt suppress instructions, as shown in Figure 2.4-2 "Interrupt suppress instruction and prefix code". Figure 2.4-2 Interrupt suppress instruction and prefix code Interrupt suppress instruction MOV A, FFH NCC ADD A,01H MOV ILM,#imm8 CCR:XXX10XX No CCR changes are caused by NCC. ■ Continuous prefix codes If continuous prefix codes conflict, the latest ones are valid, as shown in Figure 2.4-3 "Continuous prefix codes". Such conflicting prefix codes mean PCB, ADB, DTB, and SPB, as shown in Figure 2.4-3 "Continuous prefix codes". Figure 2.4-3 Continuous prefix codes Prefix code ADB DTB PCB ADD A,01H PCB is valid as a prefix code. 40 CHAPTER 3 INTERRUPT This chapter explains interrupts and direct access (DMA)/Extended intelligent I/O service (EI2OS) . 3.1 "Overview" 3.2 "Interrupt Factor and Interrupt Vector" 3.3 "Interrupt Control Register and Peripheral Function" 3.4 "Hardware Interrupt" 3.5 "Software Interrupt" 3.6 "Interrupt by µDMA" 3.7 "Interrupt of Extended Intelligent I/O Service (EI2OS)" 3.8 "Exception Processing Interrupt by Executing Undefined Instruction" 3.9 "Stack Operation of Interrupt Processing" 3.10 "Sample Program of Interrupt Processing" 3.11 "Delay Interrupt Event Module" 41 CHAPTER 3 INTERRUPT 3.1 Overview This chapter explains interrupts and direct access (DMA). • Hardware interrupt • Software interrupt • Interrupt by µDMA/Extended intelligent I/O service (EI2OS) • Exception processing ■ Types and functions of interrupts ❍ Hardware interrupt Control is moved to the user-defined interrupt processing program in response to an interrupt request from a peripheral function. ❍ Software interrupt Control is moved to the user-defined interrupt processing program by execution of a dedicated instruction for software interrupts (e.g., INT instruction). ❍ Interrupt by µDMA/Extended intelligent I/O service (EI2OS) µDMA/Extended intelligent I/O service (EI2OS) is a function used to automatically transfer data between peripheral functions and memory. Previous data transfers by an interrupt processing program is provided in the same way as the direct memory access (DMA). When a transfer of data of a specified count is completed, an interrupt processing program is automatically executed. Interrupt by µDMA/Extended intelligent I/O service (EI2OS) is a type of hardware interrupts. ❍ Exception processing Exception processing is basically the same with interrupts. Exceptions are handled by interrupting normal processing at the instruction boundary if exception event (execution of undefined instruction) generation is detected. Exception processing is equivalent to software interrupt instruction "INT10". 42 CHAPTER 3 INTERRUPT ■ Interrupt operation Four types of interrupt functions provide start and return processing, as shown in Figure 3.1-1 "Overall flow of interrupt operation". Figure 3.1-1 Overall flow of interrupt operation START Main program Valid hardware interrupt request String-type instruction being NO executed*1 YES Interrupt start and return processing YES µDMA/EI2OS? µDMA/EI2OS Fetching and decoding of next instruction NO INT instruction? YES Storing dedicated registers in the system stack NO µDMA/EI2OS processing Software interrupt and exception processing Hardware interrupt acceptance prohibited (I = 0) Hardware interrupt YES Specified count completed? End of request from peripheral function? Storing dedicated registers in the system stack NO Updating CPU interrupt processing level (ILM) RETI instruction? YES NO Execution of normal instruction NO Execution of interrupt return A dedicated register is returned from the system stack to the routine that exists before the interrupt routine is called. Reading of interrupt vector to update PC and PCB, and then branching to interrupt routine Completed reiteration of string-type instruction*1 YES Pointer moved to next instruction if PC updated *1 When a string-type instruction is being executed, the interrupt condition is checked in each step. 43 CHAPTER 3 INTERRUPT 3.2 Interrupt Factor and Interrupt Vector The F2MC-16LX has functions corresponding to 256 types of interrupt factors, and 256 interrupt vector tables are assigned to the highest address. The interrupt vector is shared by all interrupts. A software interrupt may use all of the above interrupts (INT0 to INT256), although parts of interrupt vectors are shared by hardware interrupt and exception processing interrupt. A hardware interrupt has a specific interrupt vector and interrupt control register (ICR) for each peripheral function. ■ Interrupt vector Interrupt vector tables referenced during interrupt processing are assigned to the memory area of the highest address ("FFFC00H" to "FFFFFFH"). The interrupt vectors for µDMA, exception processing, hardware interrupt, and software interrupt share the same area. Table 3.2-1 "Interrupt vectors" lists the assignment of interrupt numbers to interrupt vectors. Table 3.2-1 Interrupt vectors Software interrupt instruction Vector address L Vector address M Vector address H Mode data Interrupt No. Hardware interrupt INT0 FFFFFCH FFFFFDH FFFFFEH Unused #0 None : : : : : : : INT7 FFFFE0H FFFFE1H FFFFE2H Unused #7 None INT8 FFFFDCH FFFFDDH FFFFDEH FFFFDFH #8 (RESET vector) INT9 FFFFD8H FFFFD9H FFFFDAH Unused #9 None INT10 FFFFD4H FFFFD5H FFFFD6H Unused #10 < Exception processing > INT11 FFFFD0H FFFFD1H FFFFD2H Unused #11 Hardware interrupt #0 INT12 FFFFCCH FFFFCDH FFFFCEH Unused #12 Hardware interrupt #1 INT13 FFFFC8H FFFFC9H FFFFCAH Unused #13 Hardware interrupt #2 INT14 FFFFC4H FFFFC5H FFFFC6H Unused #14 Hardware interrupt #3 : : : : : : : INT254 FFFC04H FFFC05H FFFC06H Unused #254 None INT255 FFFC00H FFFC01H FFFC02H Unused #255 None Reference: For interrupt vectors that are not used, Fujitsu recommends specifying such vectors for the address for exception processing. 44 CHAPTER 3 INTERRUPT ■ Interrupt factors and interrupt vector and interrupt control register Table 3.2-2 "Interrupt factors, interrupt vectors, and interrupt control registers" shows the relationship among interrupt factors excluding software interrupts, interrupt vectors, and interrupt control registers. Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers Interrupt factor EI2OS support µDMA channel number Interrupt vector Interrupt control register Number Address Number Address Reset #08 FFFFDCH - - INT9 instruction #09 FFFFD8H - - Exception #10 FFFFD4H - - #11 FFFFD0H ICR00 0000B0H INT1 #12 FFFFCCH INT2 #13 FFFFC8H ICR01 0000B1H INT3 #14 FFFFC4H INT4 #15 FFFFC0H ICR02 0000B2H INT5 #16 FFFFBCH INT6 #17 FFFFB8H ICR03 0000B3H INT7 #18 FFFFB4H PWC1 #19 FFFFB0H ICR04 0000B4H PWC2 #20 FFFFACH ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH INT0 0 PWC0 1 #21 FFFFA8H PPG0/PPG1 counter borrow 2 #22 FFFFA4H PPG2/PPG3 counter borrow 3 #23 FFFFA0H PPG4/PPG5 counter borrow 4 #24 FFFF9CH #25 FFFF98H 8/16-bit U/D counter timer compare/underflow/overflow/ampdown reverse (channel 0,1) Input capture (channel 0) read 5 #26 FFFF94H Input capture (channel 1) read 6 #27 FFFF90H Output compare (channel 0) match 8 #28 FFFF8CH Output compare (channel 1) match 9 #29 FFFF88H Output compare (channel 2) match 10 #30 FFFF84H #31 FFFF80H Output compare (channel 3) match 45 CHAPTER 3 INTERRUPT Table 3.2-2 Interrupt factors, interrupt vectors, and interrupt control registers (Continued) Interrupt factor EI2OS support µDMA channel number Interrupt vector Number Address Output compare (channel 4) match #32 FFFF7CH Output compare (channel 5) match #33 FFFF78H UART transmit completed 11 #34 FFFF74H 16-bit free-running timer/16 reload timer overflow 12 #35 FFFF70H UART receive completed 7 #36 FFFF6CH SI01 13 #37 FFFF68H SI02 14 #38 FFFF64H #39 FFFF60H #40 FFFF5CH FLASH write/delete, timebase timer, interval interrupt (watch timer) #41 FFFF58H Delay interrupt generation module #42 FFFF54H I2C interface A/D 15 Interrupt control register Number Address ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH : Interrupt request flag cleared by the interrupt clear signal. The stop request is available. : Interrupt request flag cleared by the interrupt clear signal. : Interrupt request flag not cleared by the interrupt clear signal. If the same interrupt number has two interrupt factors, both of their interrupt request flags are cleared by the EI2OS/DMAC interrupt clear signal for a resource. If one of the two factors then uses the EI2OS/µDMA function, the other interrupt function is not allowed to use it. Set the interrupt request permit bit of the relevant resource to "0" so that software polling processing can handle it. 46 CHAPTER 3 INTERRUPT 3.3 Interrupt Control Register and Peripheral Function Interrupt control registers (ICR00 to ICR15) are located in the interrupt controller, and they correspond to every peripheral function that has an interrupt function. This register controls interrupts. ■ List of interrupt control registers Table 3.3-1 "Interrupt control registers" lists interrupt control registers and the corresponding peripheral functions. Table 3.3-1 Interrupt control registers Address Register Abbreviation Corresponding peripheral functions 0000B0H Interrupt control register 00 ICR00 INT0, 1 0000B1H Interrupt control register 01 ICR01 INT2, 3 0000B2H Interrupt control register 02 ICR02 INT4, 5 0000B3H Interrupt control register 03 ICR03 INT6, 7 0000B4H Interrupt control register 04 ICR04 PWC1, 2 0000B5H Interrupt control register 05 ICR05 PWC0, 8/16-bit PPG timer 0, 1 0000B6H Interrupt control register 06 ICR06 8/16-bit PPG timer 2, 3, 4, 5 0000B7H Interrupt control register 07 ICR07 8/16UD counter 0, 1, input capture 0 0000B8H Interrupt control register 08 ICR08 Input capture 1, output compare 0 0000B9H Interrupt control register 09 ICR09 Output compare 1, 2 0000BAH Interrupt control register 10 ICR10 Output compare 3, 4 0000BBH Interrupt control register 11 ICR11 Output compare 5, UART transmit 0000BCH Interrupt control register 12 ICR12 UART receive, 16-bit free-running timer, reload timer 0000BDH Interrupt control register 13 ICR13 SI00, 1 0000BEH Interrupt control register 14 ICR14 IIC, A/D 0000BFH Interrupt control register 15 ICR15 FLASH write, timebase timer, watch timer, delay interrupt generation module 47 CHAPTER 3 INTERRUPT ■ Interrupt control register function The interrupt control register (ICR) has the following one function: • Specifies the interrupt levels for respective peripheral function The interrupt control register (ICR) has partially different functions between write and read operations, as shown in the next section in Figure 3.3-1 "Interrupt Control Registers (ICR00 to ICR15) during Writing" and Figure 3.3-2 "Interrupt Control Registers (ICR00 to ICR15) during Reading". Note: Avoid accessing the interrupt control register (ICR) with read, modify, and write instructions since they may cause incorrect operation. 48 CHAPTER 3 INTERRUPT 3.3.1 Interrupt Control Register (ICR00 to ICR15) The interrupt control register (ICR00 to ICR15) corresponds to every peripheral function that has interrupt functions for controlling processing during interrupt request generation. This register has different functions between write and read operations. ■ Interrupt control register (ICR00 to ICR15) function The interrupt control register (ICR00 to ICR15) consists of bit having the following one function: • Interrupt level setting bit (IL2 to IL0) ■ Configuration of interrupt control register (ICR00 to ICR15) When µDMA is used, the function used at a write and that used at a read are the same. When EI2OS is used, however, the function is different between at a write and at a read. Figure 3.3-1 "Interrupt Control Registers (ICR00 to ICR15) during Writing" and Figure 3.3-2 "Interrupt Control Registers (ICR00 to ICR15) during Reading" shows the bit configuration of the interrupt control register (ICR00 to ICR15). 49 CHAPTER 3 INTERRUPT • At a write Figure 3.3-1 Interrupt Control Registers (ICR00 to ICR15) during Writing Address 0000B0 H to 0000BFH Bit 7 6 5 4 3 ICS3 ICS2 ICS1 ICS0 ISE 2 1 0 Initial value IL2 IL1 IL0 00000111B IL2 IL1 IL0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level setting bit Interrupt level 0 (highest) Interrupt level 7 (no interrupt) EI2OS activate bit ISE 0 Activates the interrupt sequence when an interrupt occurs (when µDMA is used) 1 Activates EI2OS when an interrupt occurs ICS3 ICS2 ICS1 ICS0 : Initial value 50 EI2OS channel setting bit Channel Descriptor address 0 0 0 0 0 100h 0 0 0 1 1 108h 0 0 1 0 2 110h 0 0 1 1 3 118h 0 1 0 0 4 120h 0 1 0 1 5 128h 0 1 1 0 6 130h 0 1 1 1 7 138h 1 0 0 0 8 140h 1 0 0 1 9 148h 1 0 1 0 10 150h 1 0 1 1 11 158h 1 1 0 0 12 160h 1 1 0 1 13 168h 1 1 1 0 14 170h 1 1 1 1 15 178h CHAPTER 3 INTERRUPT • At a read Figure 3.3-2 Interrupt Control Registers (ICR00 to ICR15) during Reading Address Bit 0000B0 H to 0000BFH 7 : Initial value 6 5 4 3 2 1 0 Initial value S1 S0 ISE IL2 IL1 IL0 XX000111B IL2 IL1 IL0 Interrupt level setting bit 0 0 0 Interrupt level 0 (highest) 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level 7 (no interrupt) ISE EI2OS activate bit 0 Activates the interrupt sequence when an interrupt occurs (when µDMA is used) 1 Activates EI2OS when an interrupt occurs S1 S0 0 0 EI2OS operation in progress or EI2OS not activated 0 1 Stopped status due to count termination 1 0 Reserved 1 1 Stopped status due to a request from the peripheral function EI2OS status 51 CHAPTER 3 INTERRUPT 3.3.2 Interrupt Control Register Functions The interrupt control register (ICR00 to ICR15) consists of bit having the following four functions: • Interrupt level setting bit (IL2 to IL0) • Extended intelligent I/O service (EI2OS) enable bit (ISE) • Extended intelligent I/O service (EI2OS) channel setting bits (ICS3 to ICS0) • Extended intelligent I/O service (EI2OS) status (S1 and S0) ■ Configuration of Interrupt Control Registers (ICR) Figure 3.3-3 Bit configuration of Interrupt Control Registers (ICR) Address 0000B0 H to 0000BFH Bit Address 0000B0 H to 0000BFH Bit 7 6 5 4 3 ICS3 ICS2 ICS1 ICS0 ISE 7 6 2 1 0 Initial value IL2 IL1 IL0 00000111B 5 4 3 2 1 0 Initial value S1 S0 ISE IL2 IL1 IL0 XX000111B Reference: ICS3 to ICS0 bits are valid only when Extended intelligent I/O (EI2OS) is activated. Set "1" in ISE bit to activate EI2OS, and set "0" in ISE bit not to activate it. When EI2OS is not to be activated, any value can be set in ICS3 to ICS0. ICS1 and ICS0 are valid for write only. S1 and S0 are valid for read only. 52 CHAPTER 3 INTERRUPT ■ Function of each bit in interrupt control register (ICR00 to ICR15) ❍ Interrupt level setting bits (IL2 to IL0) This specifies the corresponding interrupt level in the peripheral function. A reset initializes the bit to level 7 (no interrupts). Table 3.3-2 "Relationship between interrupt level setting bits and interrupt levels" lists the relationship between interrupt level setting bits and every interrupt level. Table 3.3-2 Relationship between interrupt level setting bits and interrupt levels IL2 IL1 IL0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Interrupt level 0 (Highest interrupt) 6 (Lowest interrupt) 7 (No interrupt) ❍ Extended intelligent I/O (EI2OS) enable bit (ISE) When an interrupt request is output with the EI2OS enable bit (ISE) set to "1" or to "0", EI2OS or the interrupt sequence is activated, respectively. When the EI2OS process is completed, the EI2OS enable bit (ISE) is cleared to "0". When no peripheral resource has the EI2OS feature, set the EI2OS enable bit (ISE) to "0" by means of software.The EI2OS enable bit (ISE) is cleared to "0" at a reset. ❍ Setting the Extended Intelligent I/O service (EI2OS) descriptor address The EI2OS descriptor addressing bits (ICS3 to ICS0) are enabled for a write. Used to set the EI2OS descriptor address. The EI2OS descriptor is addressed by setting the EI2OS descriptor addressing bits (ICS3 to ICS0) to the address value. The EI2OS descriptor addressing bits (ICS3 to ICS0) are initialized to "0000B" at a reset. Initialized to level 7 (no interrupt) at a reset. Table 3.3-3 "Interrupt control registers (ICR00 to ICR15) bit configuration" shows the relationships between interrupt level setting bits and individual interrupt levels. 53 CHAPTER 3 INTERRUPT Table 3.3-3 Interrupt control registers (ICR00 to ICR15) bit configuration ICS3 54 ICS2 ICS1 ICS0 EI2OS channel setting bits Channel Descriptor address 0 0 0 0 0 100h 0 0 0 1 1 108h 0 0 1 0 2 110h 0 0 1 1 3 118h 0 1 0 0 4 120h 0 1 0 1 5 128h 0 1 1 0 6 130h 0 1 1 1 7 138h 1 0 0 0 8 140h 1 0 0 1 9 148h 1 0 1 0 10 150h 1 0 1 1 11 158h 1 1 0 0 12 160h 1 1 0 1 13 168h 1 1 1 0 14 170h 1 1 1 1 15 178h CHAPTER 3 INTERRUPT 3.4 Hardware Interrupt Hardware interrupt is a function to temporarily stop the execution of program being executed by the CPU in response to an interrupt request signal from the peripheral function. It then moves control to the interrupt processing program defined by a user. Also, µDMA/Eextended intelligent I/O service (EI2OS) external interrupt may be executed as a kind of hardware interrupt. ■ Hardware interrupt function ❍ Hardware interrupt function A hardware interrupt compares the interrupt level of an interrupt request signal that is output by the peripheral function and interrupt level mask register (ILM) in the CPU processor status (PS). It then refers to the I-flag in the processor status (PS) to determine whether or not the interrupt is acceptable. If the hardware interrupt is accepted, registered contents in the CPU are automatically stored to the system stack, and the interrupt level currently requested is saved in the interrupt level mask register (ILM). In this event, control then branches to the corresponding interrupt vector. ❍ Multiple interrupts Multiple hardware interrupts can start at one time. ❍ µDMA/Extended intelligent I/O service (EI2OS) µDMA/Extended intelligent I/O service (EI2OS) is an automatic transfer function between memory and I/O, and if the transfer is completed, a hardware interrupt starts. µDMA/Extended intelligent I/O service (EI2OS) does not start in a multiplex manner, and if some µDMA process is executed, other interrupt requests and all µDMA/Extended intelligent I/O service (EI2OS) requests wait temporarily. ❍ External interrupt An external interrupt (including wake-up interrupt) is accepted as a hardware interrupt via the peripheral function (interrupt request detect circuit). ❍ Interrupt vector Interrupt processing refers to the interrupt vector table assigned in memory addresses ranging from "FFFC00H" to "FFFFFFH" and shared with software interrupts. For the assignment of interrupt number and interrupt vector, see Section 3.2 "Interrupt Factor and Interrupt Vector". 55 CHAPTER 3 INTERRUPT ■ Configuration of hardware interrupt The hardware-interrupt mechanism is divided into four parts, as shown in Table 3.4-1 "Hardware-interrupt mechanism". To use hardware interrupts, a program must contain settings for the four locations. Table 3.4-1 Hardware-interrupt mechanism Hardware-interrupt mechanism Function Peripheral function Interrupt enable bit, interrupt request bit Control of interrupt request by peripheral function Interrupt controller Interrupt control register (ICR) Setting for interrupt level and controlling µDMA/Extended intelligent I/O service (EI2OS) Interrupt enable flag (I) Identifying interrupt enable state Interrupt level mask register (ILM) Comparing request interrupt level and current interrupt level Micro-code Executing interrupt processing routine Interrupt vector table Storing branch address for interrupt processing CPU "FFFC00H" to "FFFFFFH" in memory ■ Suppressing hardware interrupt Accepting a hardware interrupt request is suppressed under the following conditions: ❍ Suppressing hardware interrupts during writing to peripheral function control register area During writing to the peripheral function control register area, no hardware interrupt requests are accepted. This prevents incorrect interrupt-related operations by the CPU during its rewriting of the interrupt control registers with each peripheral function. Peripheral function control register area refers not to a range of "000000H" to "0000FFH" for the I/O addressing area, but to the areas assigned to the control register within peripheral function control registers and data register. Figure 3.4-1 "Hardware interrupt requests during writing to peripheral function control register area" shows hardware interrupt operations during writing to the peripheral function control register area. Figure 3.4-1 Hardware interrupt requests during writing to peripheral function control register area Write instruction to peripheral function control register area MOV A,#08 MOV io,A Interrupt request is issued at this point 56 MOV A,2000H Not branched to interrupt Interrupt processing Branched to interrupt CHAPTER 3 INTERRUPT ❍ Suppressing hardware interrupts in the interrupt suppress instruction Of the ten types of hardware interrupt suppress instruction listed in Table 3.4-2 "Hardware interrupt suppress instruction", none can detect whether or not hardware interrupt requests are present, and none can ignore an interrupt request. If a valid hardware interrupt request is generated during execution of these instructions, the interrupt request is not executed until execution of a subsequent instruction is completed. In this case, the subsequent instruction is other than the instructions mentioned above. Table 3.4-2 Hardware interrupt suppress instruction Instruction that rejects interrupt and hold requests Prefix code Interrupt and hold suppress instruction (instruction to delay the effect of prefix code) PCB DTB ADB SPB CMR NCC MOV ILM, #imm8 OR CCR, #imm8 AND CCR, #imm8 POPW PS ❍ A hardware interrupt is suppressed during execution of software interrupt When a software interrupt starts, other interrupt requests are not accepted so that the I-flag is cleared to "0". 57 CHAPTER 3 INTERRUPT 3.4.1 Hardware Interrupt Operation This section explains an operation starting from hardware interrupt request generation until completion of interrupt processing. ■ Starting hardware interrupt ❍ Operation of peripheral function (generating an interrupt request) The peripheral functions including hardware interrupt request functions have the "interrupt request flag" to indicate whether or not to generate an interrupt request and "interrupt enable flag" that selects whether to enable or disable an interrupt request to the CPU. The interrupt request flag is set when a peripheral function specific event is generated, and it issues an interrupt request to the interrupt controller if the interrupt enable flag is set to "enable". ❍ Operation of interrupt controller (control of interrupt request) The interrupt controller compares interrupt levels (IL) in interrupt requests that are received at one time, and selects the request of the highest level (the lowest value of IL) and notifies the CPU of it. If multiple requests have the same level, the one with the lower interrupt number has a priority. ❍ CPU operation (acceptance of interrupt requests and interrupt processing) CPU compares the levels (ICR: IL2 to IL0) of received interrupts with the interrupt level mask register (ILM). If IL < ILM and the interrupt is permitted (I = 1, in PC: CCR), the interrupt processing microcode starts and interrupt processing is executed,after the instruction currently being executed is completed. Interrupt processing first saves the contents of a dedicated register (12 bytes of A, DPR, ADB, DTB, PCB, PC and PS) in the system stack (system stack space indicated by SSB and SSP). Then, it loads the interrupt vector to the program counter (PCB, PC), updates ILM, and sets the stuffing (S) flag (i.e., sets the CCR S-flag to "1" and enables the system stack). ■ Return from hardware interrupt In the interrupt processing program, if the RETI instruction is executed and the interrupt request flag of a peripheral function that is an interrupt factor is cleared, 12 bytes of the data stored in the system stack is returned to the dedicated register to restart the processing in progress before the interrupt branch. By clearing the interrupt request flag, the interrupt request that the peripheral function output to the interrupt controller is automatically removed. 58 CHAPTER 3 INTERRUPT ■ Hardware interrupt operation Figure 3.4-2 "Hardware interrupt operation" shows the operation from the generation of hardware interrupt until the completion of interrupt processing. Figure 3.4-2 Hardware interrupt operation Internal data bus PS,PC (7) Microcode PS II LM IR Check (6) 2 F MC-16LX CPU Comparator (5) (4) Other peripheral function (3) Peripheral function generating an interrupt request Level comparator Enable FF Interrupt level IL AND Factor FF (8) (2) (1) Interrupt controller RAM IL PS I ILM IR FF : : : : : : Interrupt level setting bit for interrupt control register (ICR) Processor status Interrupt enable flag Interrupt level mask register Instruction register Flip-flop 1. An interrupt factor is generated in the peripheral function. 2. If an interrupt is permitted after referring to the interrupt enable bit of the peripheral function, the interrupt request is issued from the peripheral to the interrupt controller. 3. The interrupt controller that receives the interrupt request also checks the priority of a requested interrupt, and it then transfers the interrupt level (IL) corresponding to the interrupt request to the CPU. 4. The CPU compares the interrupt level (IL) requested from the interrupt controller with the interrupt level mask register (ILM). 5. If the compare results have a priority higher than the current interrupt processing level, the Iflag of the condition code register (CCR) is checked. 6. As a result of the check in step 5, if the I-flag indicates an interrupt enable (I = 1), the interrupt operation waits until the instruction currently being executed is completed and then sets ILM to the requested level (IL). 7. The contents of the resisters are stored and branched to the interrupt processing routine. 8. Software in the user's interrupt processing routine clears the interrupt factor generated in step 1 for executing the RETI instruction, and then interrupt processing is completed. 59 CHAPTER 3 INTERRUPT 3.4.2 Flow of Hardware Interrupt Operation If an interrupt request is generated by a peripheral function, the interrupt controller transfers its interrupt level to the CPU. If the CPU accepts the interrupt request, the instruction currently being executed is temporarily suspended to execute the interrupt processing routine or to start µ DMA/Extended intelligent I/O service (EI2OS). If a software interrupt is generated by the INT instruction, the interrupt processing routine is executed regardless of the CPU state. Moreover, if a software interrupt is generated by the INT instruction, the hardware interrupt is prohibited. ■ Hardware interrupt operation flow Figure 3.4-3 "Flow of hardware interrupt operation" shows the hardware interrupt operation flow. Figure 3.4-3 Flow of hardware interrupt operation START Main program I&IF&IE=1 AND ILM>IL String-type instruction being executed*1 Interrupt start and return processing YES NO ENx=1? Reading and decoding of next instruction INT instruction? YES NO Software interrupt and exception processing Storing dedicated registers in the system stack NO I 0 Hardware interrupt prohibited YES µDMA/EI2OS µDMA/EI2OS processing Has the specified number of times been completed? Or did a peripheral function issue a complete request? Storing dedicated registers in the system stack Hardware interrupt YES NO ILM IL (If an interrupt request is accepted, its interrupt level is transferred to ILM.) YES RETI instruction? Execution of interrupt return NO Execution of normal instruction (Including interrupt processing) Return of dedicated registers from system stack and then its return to routine that existed before calling of interrupt routine Completed NO reiteration of string-type instruction*1 S 1 (Enabling system stack) PCB, PC Interrupt vector (Branching to interrupt processing routine) YES Moving of pointer to next instruction if PC updated *1 : When a string-type instruction is being executed, the interrupt condition is checked in each step. I : Interrupt permission flag of condition code register (CCR) IF : Interrupt request flag of peripheral function IE : Interrupt permission flag of peripheral function ILM : Interrupt level mask register (in PS) 60 ENx : Request flag executing DMA of DMA enable register (DER) IL : Interrupt level setting bit in interrupt control register (ICR) S : Stack flag in condition code register (CCR) PCB : Program bank register PC : Program counter CHAPTER 3 INTERRUPT 3.4.3 Procedure for Using Hardwar Interrupt To use hardware interrupts, necessary setup including the system stack area, peripheral functions, and interrupt control registers (ICR) must be performed. ■ Procedure for using hardware interrupt Figure 3.4-4 "Procedure for using hardware interrupt" shows an example of a procedure for using hardware interrupts. Figure 3.4-4 Procedure for using hardware interrupt Start (1) Setup of the system stack area (2) Initial setup of peripheral functions (3) Setup of ICR in the interrupt controller (4) Start of the operation of peripheral functions The interrupt enable bit is set to "permit" (5) Setup of ILM and I in PS Interrupt processing program Stack processing Branching to stack processing interrupt vector (8) (7) Processing by hardware Execution of interrupt in a peripheral function (execution of an interrupt processing routine) (9) Clearing of interrupt factor (10) Interrupt return instruction (RETI) Main program (6) Generation of an interrupt request Main program 1. The system stack area is set up. 2. The initial setup of peripheral functions for which interrupt requests can be generated is performed. 3. The interrupt control register (ICR) is set up in the interrupt controller. 4. The peripheral function is set to the operation start state, and the interrupt enable bit is set to "permit". 61 CHAPTER 3 INTERRUPT 5. The interrupt level mask register (ILM) and interrupt enable flag (I) are set to "interrupt acceptable". 6. A hardware interrupt request is generated by generation of a peripheral function interrupt. 7. Interrupt processing hardware saves registers to branch to the interrupt processing program. 8. The interrupt processing program processes peripheral functions because of interrupt generation. 9. The interrupt request from peripheral function is canceled. 10.The interrupt return instruction is executed, and the program is restored to what it was before branching. 62 CHAPTER 3 INTERRUPT 3.4.4 Multiple Interrupts For hardware interrupts, multiple interrupts from peripheral functions are simultaneously executed by specifying a different interrupt level for each interrupt level setting bit (IL0 to IL2) in the interrupt control register (ICR), thereby enabling to execute multiple interrupt requests. µDMAs cannot be started in duplicate, however. ■ Multiple interrupt operations While an interrupt processing routine is executed, if an interrupt request with a higher level is generated, the interrupt processing is interrupted and then the higher interrupt request is accepted. In this case, after execution of the interrupt with the higher level is completed, the interrupt processing being stopped is restarted. The interrupt level can be set in a range of 0 to 7, but a CPU does not accept the level 7. While an interrupt is executed, if another interrupt request with the same or lower level occurs, that interrupt request waits until the current interrupt is completed, unless ILM is changed by the I-flag. In the interrupt processing routine, if the I-flag in the condition code register (CCR) is set to "interrupt prohibited" (I in CCR set to "0") or the interrupt level mask register (ILM) is set to "interrupt prohibited" (ILM set to "000"), the starting of multiple interrupts within the interrupt can be temporarily prohibited. Note: µDMA/EI2OS cannot be started in duplicate. All other interrupt requests and µDMA/EI2OS requests have to wait during execution of µDMA/EI2OS. ■ Example of multiple interrupts Suppose a timer interrupt has priority over the A/D converter. In this case, the interrupt level of the A/D converter is 2 whereas that of timer interrupt is 1. If a timer interrupt is generated while an A/D converter interrupt is executed, the processing shown in the Figure 3.4-5 "Example of multiple interrupts" is performed. Figure 3.4-5 Example of multiple interrupts Main program A/D interrupt processing Interrupt level 2 Peripheral (1) (ILM = 010) initialized Timer interrupt processing Interrupt level 1 (ILM = 001) (3) Timer interrupt generated A/D interrupt (2) generated (4) Timer interrupt processing Interrupt Restart Main process (8) restart (6) A/D interrupt processing (5) Timer interrupt return (7) A/D interrupt return 63 CHAPTER 3 INTERRUPT ❍ A/D interrupt generation When the A/D converter interrupt processing starts, the interrupt level mask register (ILM) is automatically set to the same interrupt level (IL2 to IL0 in ICR) as that for the A/D converter (i.e., 2 in this example). In this example, if an interrupt request of level 1 or 0 is generated, the interrupt with higher priority is executed first. ❍ End of interrupt processing If interrupt processing is completed and a return instruction (RETI) is then executed, the values of the dedicated registers (A, DPR, ADB, DTB, PCB, PC, PS) stored in the stack are returned and the values of the interrupt level mask register (ILM) are specified to those defined before the interrupt. 64 CHAPTER 3 INTERRUPT 3.4.5 Hardware Interrupt Processing Time The time period starting from generation of a hardware interrupt request until the interrupt handling routine starts execution requires the time until the instruction currently being executed is completed plus the interrupt processing time. ■ Hardware interrupt processing time The time period starting from generation of a hardware interrupt request until the interrupt handling routine starts execution requires the interrupt request sample waiting time and interrupt handling time (time required for preparing interrupt processing). Figure 3.4-6 "Interrupt processing time" illustrates the interrupt processing time. Figure 3.4-6 Interrupt processing time Normal instruction execution CPU operation Interrupt waiting time Interrupt request sample waiting time Interrupt handling Interrupt processing routine Interrupt handling time ( θ machine cycle)* Interrupt request generated : Last cycle of the instruction. The interrupt request is sampled in this part. * : One machine cycle corresponds with one clock interval of the machine clock interval (φ). ❍ Interrupt request sample waiting time Refers to a time period starting after an interrupt request is generated until the instruction currently being executed is completed. Sampling is performed in the last cycle of each instruction to determine whether an interrupt request is generated or not. Thus, during execution of each instruction, the CPU is unable to recognize an interrupt request, resulting in a waiting time. The interrupt request sample waiting time reaches the maximum value if an interrupt request occurs immediately after the start of POPW RW0...RW7 instructions (45 machine cycles), which have the longest execution cycle. 65 CHAPTER 3 INTERRUPT ❍ Interrupt processing time (θ θ machine cycles) After the CPU accepts an interrupt request, the CPU stores the dedicated registers in the system stack and fetches the interrupt vector. The interrupt processing time is thus derived from the following formula: • At interrupt start: θ = 24 + 6 x Z machine cycles • At interrupt return: θ = 11 + 6 x Z machine cycles (RETI instruction) The interrupt processing time differs depending on the address indicated by the stack pointer. Table 3.4-3 "Correction values (Z) for interrupt processing times" lists correction values (Z) for interrupt processing times. One machine cycle corresponds to a clock interval of machine clocks (φ). Table 3.4-3 Correction values (Z) for interrupt processing times Address pointed by stack pointer 66 Correction value (Z) External 8 bits +4 External even address +1 External odd address +4 Internal even address 0 Internal odd address +2 CHAPTER 3 INTERRUPT 3.5 Software Interrupt Software interrupt is a function used to move control to the user-defined program for interrupt processing from a program that the CPU is being executed if a software interrupt instruction (INT instruction) is executed. A hardware interrupt is stopped while a software interrupt is executed. ■ Start of software interrupt ❍ Software interrupt start To start a software interrupt, execute the INT instruction. A software interrupt request has neither the interrupt request flag nor enable flag. It always generates an interrupt request if the INT instruction is executed. ❍ Hardware interrupt suppressed Because the INT instruction has no interrupt levels, the interrupt level mask register (ILM) is not updated. During INT instruction execution, the I-flag in the condition code register (CCR) is set to "0" to mask hardware interrupts. To permit a hardware interrupt during software interrupt processing, set the I-flag to "1" in the software interrupt processing routine. ❍ Software interrupt operation If the CPU obtains the INT instruction and execute it, a microcode for software interrupt processing starts. This microcode is used to store the registers inside the CPU in the system stack and to mask hardware interrupts (set the I-flag in CCR to "0"), leading to branching to the corresponding interrupt vector. For the assignment of interrupt numbers to interrupt vectors, see Section 1.2, "Interrupt Factor and Interrupt Vector". ■ Return from software interrupt If an interrupt return instruction (RETI instruction) is executed in the interrupt processing program, the 12-byte data stored in the system stack is restored to the dedicated registers, returning control to the processing that was executed before the interrupt processing. 67 CHAPTER 3 INTERRUPT ■ Software interrupt operation Figure 3.5-1 "Software interrupt operation" shows the operation starting from software interrupt generation until interrupt processing completion. Figure 3.5-1 Software interrupt operation Internal data bus PS,PC (2) Microcode (1) PS I S IR Queue Fetch RAM PS I S IR : : : : Processor status Interrupt enable flag Stack flag Instruction register 1. Run a software interrupt instruction. 2. Based on the microcode corresponding to the software interrupt instruction, the necessary processes are performed, such as storage of the dedicated registers. The branch processing is then executed. 3. The RETI instruction is executed in user's interrupt processing routine to end interrupt processing. ■ Notes on software interrupts If the program bank register (PCB) is set to "FFH", the CALLV instruction vector area is duplicated with the table for INT #vct8 instructions. When creating software, make sure that the CALLV instruction and INT #vct8 instruction have no address duplication. 68 CHAPTER 3 INTERRUPT 3.6 Interrupt by µ DMA The µDMA controller is a simplified DMA that has the same function as EI2OS. DMA transfers are set up using the EI2OS descriptor. ■ µDMA functions µDMA has the functions listed below. • Provides an automatic data transfer between a peripheral resource (I/O) and memory. • CPU program execution stops during the DMA start sequence. • A DMA transfer channel has 16 channels (a smaller channel number is assigned a higher DMA transfer priority) • Allow selection of whether or not to increment the transfer source, transfer destination addresses. • A DMA transfer starts with an interrupt factor of the peripheral resource (I/O). • DMA transfers are controlled with a (a) DMA enable register, (b) DMA stop status register, (c) DMA status register and (e) descriptor (assigned to a range of 000100H to 00017FH in RAM). • STOP requests are issued as a means to stop DMA transfers from a resource. • After the end of a DMA transfer, a flag is set to the bit corresponding to the transfer end channel of the DMA status register, and an end interrupt is then output to the interrupt controller. 69 CHAPTER 3 INTERRUPT ■ List of µDMA registers ❍ DMA enable register (DER) DMA enable register (DER) has the bit configuration shown in the diagram below. Bit 14 13 12 11 10 9 8 0000AD EN15 EN14 EN13 EN12 EN11 EN10 EN9 EN8 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 R/W R/W R/W R/W R/W R/W R/W R/W 0000AC 15 DERH Initial value 00000000B DERL Initial value 00000000B DMA enable register (DER) has the bit functions listed below. . ENx bit Function 0 (Initial value) Outputs an interrupt request from a resource to the interrupt controller. (An interrupt request from a resource is not used as a DMA start request). An interrupt request output from a resource is used as a DMA start request. Cleared to "0" when the DMA transfer byte count reaches 0. 1 ❍ DMA stop status register (DSSR) The bit configuration of the DMA stop status register (DSSR) is shown below. Bit 7 6 5 4 3 2 1 0 0000A4H STP7 STP6 STP5 STP4 STP3 STP2 STP1 STP0 R/W R/W R/W R/W R/W R/W R/W R/W DSSR Initial value 00000000B The function of each bit in the DMA stop status register (DSSR) is shown below. STPx bit 0 (Initial value) 1 70 Function No STOP request is accepted in a DMA transfer. STOP request is accepted in a DMA transfer to stop DMA operation. STOP request is accepted only the UART receive (channels 7). The bits other than the bit 7 are not valid. Writing "1" by running software is not valid. CHAPTER 3 INTERRUPT ❍ DMA status register (DSR) The bit configuration of the DMA status register (DSR) is shown below. 15 14 13 12 11 10 9 8 DE15 DE14 DE13 DE12 DE11 DE10 DE9 DE8 R/W R/W R/W R/W R/W R/W R/W R/W Bit 00009DH Bit 00009CH 7 6 5 4 3 2 1 0 DE7 DE6 DE5 DE4 DE3 DE2 DE1 DE0 R/W R/W R/W R/W R/W R/W R/W R/W DSRH Initial value 00000000B DSRL Initial value 00000000B The functions of each bit in the DMA status register (DSR) is shown in the table below. DEx bit 0 (Initial value) 1 Function No DMA transfer has ended. If a DMA transfer ends, an interrupt request is output to the interrupt controller. Note: If "1" is written, DMA transfer does not end. An interrupt is output to the interrupt controller. 71 CHAPTER 3 INTERRUPT ■ µDMA operations Figure 3.6-1 "µDMA operations" shows µDMA operations. performed as described below. Data transfer using DMA is 1. A peripheral resource (I/O) requests a DMA transfer. 2. The DMA controller reads a descriptor. 3. The transfer source, transfer destination, and transfer data count are read from the descriptor. 4. A DMA transfer between I/O and memory starts. 5. For no transfer end: The interrupt request of a resource is cleared. For transfer end: After the DMA transfer ends, the DMA status register is set to the transfer end flag, thereby causing output of an interrupt request to the interrupt controller. Figure 3.6-1 µDMA operations Memory space by IOA I/O register I/O register Peripheral function (I/O) (1) (3) DMA descriptor (3) DER DMA controller (2) by BAP Buffer (4) by DCT CPU IOA BAP DER DCT 72 : : : : I/O address buffer Buffer address pointer DMA enable register (also selects ENx) Data counter Interrupt controller CHAPTER 3 INTERRUPT 3.6.1 DMA Descriptor The DMA descriptor is located in internal RAM within a range from "000100H" to "00017FH" consisting of 8 bytes x 16 channels. ■ DMA descriptor configuration A DMA descriptor consists of 8 bytes x 16 channels. Each DMA descriptor has the configuration shown in the Figure 3.6-2 "Configuration of µDMA descriptor". Table 3.6-1 "Relationship between channel number and descriptor address" lists the relationship between channel number and DMA descriptor address. Figure 3.6-2 Configuration of µDMA descriptor MSB LSB Upper 8 bits of data counter (DCTH) H Lower 8 bits of data counter (DCTL) Upper 8 bits of I/O register address pointer (IOAH) Lower 8 bits of I/O register address pointer (IOAL) DMA control register (DMACS) Upper 8 bits of buffer address pointer (BAPH) Middle 8 bits of buffer address pointer (BAPM) Descriptor header address Lower 8 bits of buffer address pointer (BAPL) L Table 3.6-1 Relationship between channel number and descriptor address DMA enable register Channel Descriptor address EN0 0 000100H INT0 EN1 1 000108H PWC0 EN2 2 000110H PPG0/PPG1 counter borrow EN3 3 000118H PPG2/PPG3 counter borrow EN4 4 000120H PPG4/PPG5 counter borrow EN5 5 000128H Input capture (channel 0) read EN6 6 000130H Input capture (channel 1) read EN7 7 000138H UART receive completed EN8 8 000140H Output compare (channel 0) match EN9 9 000148H Output compare (channel 1) match Resource interrupt request 73 CHAPTER 3 INTERRUPT Table 3.6-1 Relationship between channel number and descriptor address (Continued) 74 DMA enable register Channel Descriptor address EN10 10 000150H Output compare (channel 2) match EN11 11 000158H UART transmit completed EN12 12 000160H 16-bit FRT/16-bit reload timer overflow EN13 13 000168H SI01 EN14 14 000170H SI02 EN15 15 000178H A/D Resource interrupt request CHAPTER 3 INTERRUPT 3.6.2 Individual Registers of DMA Descriptor Each DMA descriptor consists of the following registers: • Data counter (DCT) • I/O register address pointer (IOA) • DMA control register (DMACS) • Buffer address pointer (BAP) The registers must be initialized because their initial values become undefined when they are reset. ■ Data counter (DCT) The data counter (DCT) is a register with a length of 16 bits and corresponds to the transfer data count. After each item of data is transferred, the counter decrements by one. If this counter reaches zero, DMA ends. Figure 3.6-3 "Configuration of data counter (DCT)" shows the configuration of the data counter (DCT). If the data counter (DCT) is set to "0", the maximum data transfer count (i.e., 65536) is defined. Figure 3.6-3 Configuration of data counter (DCT) DCTH Bit DCT 15 14 13 12 B15 B14 B13 B12 11 10 09 B11 B10 B09 DCTL 05 08 07 06 B08 B07 B06 B05 04 03 B04 B03 02 01 B02 B01 00 Initial value B00 XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/write allowed x : Undefined ■ I/O register address pointer (IOA) The I/O register address pointer (IOA) is a register with a length of 16 bits, and it indicates the lower address (A15 to A0) of the I/O register providing a buffer for data transfers. All of the upper addresses (A23 to A16) are set to "0". Any I/O in a range of "000000H" to "00FFFFH" can be specified with the address. Figure 3.6-4 "Configuration of I/O register address pointer (IOA)" shows the configuration of the I/O register address pointer (IOA). Figure 3.6-4 Configuration of I/O register address pointer (IOA) IOAH Bit IOA 15 14 13 12 A15 A14 A13 A12 11 10 09 A11 A10 A09 IOAL 05 08 07 06 A08 A07 A06 A05 04 03 A04 A03 02 01 A02 A01 00 Initial value A00 XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/write allowed x : Undefined 75 CHAPTER 3 INTERRUPT ■ DMA control status register (DMACS) The DMA control status register (DMACS) has a length of 8 bits that indicate the update or fixed state, transfer data format (byte/word), and transfer directions for the buffer address pointer (BAP) and I/O register address pointer (IOA). Figure 3.6-5 "Configuration of DMA control status register (DMACS)" shows the configuration of the DMA control status register (DMACS). Figure 3.6-5 Configuration of DMA control status register (DMACS) Bit 07 06 05 RESV RESV RESV 04 03 02 01 00 IF BW BF DIR SE Initial value XXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W DMA end control bit SE 0 1 Operation is not ended by a request from a peripheral function. Operation is ended by a request from a peripheral function. DIR 0 1 Data transfer direction specify bit I/O register address pointer -> buffer address pointer Buffer address pointer → I/O register address pointer BAP update/fixed selection bit BF 0 1 The buffer address pointer is updated after a data transfer.*1 The buffer address pointer is not updated after a data transfer. BW 0 1 IF 0 1 Transfer data length setting bit Byte Word IOA update/fixed selection bit The I/O register pointer is updated after a data transfer. The I/O register pointer is not updated after a data transfer. RESV Reserve bit Always set these bits to 0. R/W x *1 *2 76 : Read/write allowed : Undefined : The buffer address pointer changes at the lower 16 bits, and it can only be incremented. : I/O register address pointer can only be incremented. CHAPTER 3 INTERRUPT ■ Buffer address pointer (BAP) The buffer address pointer (BAP) has a length of 24 bits, containing the address used in the next DMA transfer. BAP is independent from each DMA channel, so each DMA channel can transfer data between any of 16MB addresses and I/O. If the BF bit (BAP update/fixed selection bit) in the DMA control status register (DMACS) is set to "update provided", BAP changes at the lower 16 bits (BAPM, BAPL), but the upper 8 bits (BAPH) do not change. Figure 3.6-6 "Configuration of buffer address pointer (BAP)" shows the configuration of BAP. Figure 3.6-6 Configuration of buffer address pointer (BAP) 23 BAP 16 15 BAPH (R/W) 8 7 BAPM (R/W) 0 BAPL Initial value XXXXXXB (R/W) R/W : Read/write allowed X : Undefined Notes: • The I/O register address pointer (IOA) can be used to specify an area ranging from "000000H" to "00FFFFH". • The buffer address pointer (BAP) can be used to specify an area ranging from "000000H" to "FFFFFFH". 77 CHAPTER 3 INTERRUPT 3.6.3 DMA Processing Procedure If an interrupt request is generated by a peripheral resource (I/O) and the corresponding DMA enable register (DER) has a setting of DMA start, then a DMA transfer is performed. If a data transfer ends at the specified count, an interrupt request is output to the interrupt controller. ■ DMA processing procedure Figure 3.6-7 "DMA processing procedure" shows a simple DMA processing procedure Figure 3.6-7 DMA processing procedure Software processing Hardware processing Start Initial setup Setting up of system stack area Definition of DMA descriptor Initial definition of peripheral function Definition of interrupt control register (ICR) Initial definition of DMA controller Setting up of ILM and I in PS Clearing of peripheral interrupt (Interrupt request) and (DER: ENx = 1) Execution of user program DMA data transfer Evaluation of end request from countout event or resource DMA transfer end Clearing of peripheral interrupt Clearing of DSR register by software RETI DERx: DMA enable register DSRx: DMA status register 78 YES DSRx="1" NO CHAPTER 3 INTERRUPT 3.6.4 µDMA Processing Time Time consumed in µDMA processing varies with the following factors: • Settings of µDMA control status register (DMACS) • Address (area) indicated by the I/O register address pointer (IOA) • Address (area) indicated by the buffer address pointer (BAP) • External data bus width for external access • Data length of transfer data When a µDMA data transfer ends, a hardware interrupt starts, and then the interrupt processing time is added. ■ µDMA processing time (time per one-time transfer) ❍ If data transfer continues The µDMA processing time during a continuation of a data transfer depends on the setting of µDMA control status register (DMACS), as shown in Table 3.6-2 "µDMA execution time". Table 3.6-2 µDMA execution time Setting of IOA update/fixed selection bit (IF) BAP address update/fixed Setting of selection bit (BF) Fixed Update Fixed 17 19 Update 19 21 Note: In units of machine cycles. One machine cycle corresponds to one clock interval of the machine clock (φ). Correction is required depending on the condition at µDMA execution, as shown in Table 3.6-3 "Correction values of data transfer for µDMA execution time". Table 3.6-3 Correction values of data transfer for µDMA execution time Internal access External access I/O register address pointer B/even Odd B/even 8/odd B/even 0 +2 +1 +4 Odd +2 +4 +3 +6 B/even +1 +3 +2 +5 8/odd +4 +6 +5 +8 Internal access Buffer address pointer External access Note: B indicates a byte data transfer, 8 indicates a word transfer with an external bus width of 8 bits, even indicates word transfer of an even-numbered address, and odd indicates a word transfer of an odd-numbered address. 79 CHAPTER 3 INTERRUPT ❍ Transfer performance Minimum transfer speed 1.7 µs/10 MHz (machine clock) 1.07 µs/16 MHz (machine clock) • Built-in I/O -> built-in RAM; or built-in RAM -> built-in I/O without address increment • Even-numbered address -> even-numbered address or 8-bit access Maximum transfer speed 2.8 µs/10 MHz (machine clock) 1.75 µs/16 MHz (machine clock) Table 3.6-4 "Correction values (Z) for interrupt handling time" indicates the correction values for interrupt handling time. Table 3.6-4 Correction values (Z) for interrupt handling time Address indicated by stack pointer Correction value (Z) External 8 bit +4 External even-numbered address +1 External odd-numbered address +4 Internal even-numbered address 0 Internal odd-numbered address +2 ❍ If a transfer is ended with an end request from a peripheral function (I/O) If a µDMA data transfer ends partway (DEx = 1) because of an end request by a peripheral function (I/O), the data transfer fails and a hardware interrupt starts. The µDMA processing time in this case is calculated with the following formula. Z in the formula indicates a correction value for interrupt processing time (see Table 3.6-3 "Correction values of data transfer for µDMA execution time"). The µDMA processing time if a transfer ends partway is: 36 + 6 x Z machine cycle where one machine cycle corresponds to one clock interval of the machine clock (φ). 80 CHAPTER 3 INTERRUPT 3.7 Interrupt of Extended Intelligent I/O Service (EI2OS) Extended Intelligent I/O service (EI2OS) is the function to transfer data between peripheral resources and memory. EI2OS causes a hardware interrupt upon completion of data transfer. ■ Extended Intelligent I/O Service (EI2OS) The Extended Intelligent I/O service is a type of hardware interrupt, serving as the function for data transfer between a peripheral resource and memory. The user can create programs to activate and terminate EI2OS without the need for providing a data transfer program. ❍ Advantages of Extended Intelligent I/O service (EI2OS) The data transfer by EI2OS has the following advantages over the data transfer executed by an interrupt handler: • No need to code a transfer program, resulting in smaller program size. • Capable of triggering a transfer by a peripheral resource interrupt source, eliminating the need for polling a data transfer source. • Capable of setting the incrementing of the transfer address. • Capable of the incrementing and no updating of the I/O register address. ❍ Interrupt upon completion of Extended Intelligent I/O service (EI2OS) EI2OS causes a branch to an interrupt handler upon completion of data transfer. The interrupt handler can identify the EI2OS termination source by checking the EI2OS status bits (S1, S0) in the interrupt control register (ICR). Reference: Interrupt numbers and interrupt vectors are fixed for individual resources. For details, see Section 3.2 "Interrupt Sources and Interrupt Vectors". ❍ Interrupt control register (ICR) The ICR can set the activation of EI2OS and its channel. It can also be used to display the EI2OS status upon termination of EI2OS. 81 CHAPTER 3 INTERRUPT ❍ Extended Intelligent I/O service (EI2OS) descriptor (ISD) The EI2OS descriptor is located from "000100H" to "00017FH" in RAM, serving as a register containing 8 bytes x 16 channels to set the transfer mode, peripheral resource address, the number of bytes to transfer, and the transfer destination address. Channels are set by the interrupt control register (ICR). Note: CPU programs are not executed during the execution of the Extended Intelligent I/O service (EI2OS). ■ Operation of the Extended Intelligent I/O Service (EI2OS) Figure 3.7-1 Extended Intelligent I/O Service (EI2OS) Operation Memory space Peripheral function (resource) by I/OA Resource register Resource register (5) CPU Interrupt request (3) ISD by ICS (2) (3) (1) Interrupt control register (ICR) Interrupt controller by BAP (4) Buffer by DCT ISD : EI2OS OS descriptor I/OA : I/O address pointer BAP : Buffer address pointer ICS : EI2OS channel setting bit in the interrupt control register (ICR) DCT: Data counter 1. A peripheral resource outputs an interrupt request. 2. The interrupt controller sets the EI2OS descriptor according to the settings in the interrupt control registers (ICRs). 3. The transfer source and destination are read from the EI2OS descriptor. 4. Data is transferred between the peripherals resource and memory. 5. Upon completion of data transfer, the interrupt request flag bit of the peripheral resource is cleared to "0". 82 CHAPTER 3 INTERRUPT 3.7.1 Extended Intelligent I/O Service (EI2OS) Descriptor (ISD) The Extended Intelligent I/O service (EI2OS) descriptor (ISD) is 8 bytes x 16 channels long, ranging from "000100H" to "00017FH". ■ Configuration of the Extended Intelligent I/O Service (EI2OS) descriptor (ISD) The ISD consists of 8 bytes x 16 channels. Figure 3.7-2 Configuration of El2OS descriptor (ISD) MSB LSB Data counter upper 8 bits (DCTH) H Data counter lower 8 bits (DCTL) I/O register address pointer upper 8 b its (I/OAH) I/O register address pointer lower 8 b its (I/OAL) EI2OS status register (ISCS) Buffer address pointer upper 8 bits (BAPH) Buffer address pointer middle 8 bits (BAPM) First ISD address (000100H + 8 x ICS) Buffer address pointer lower 8 bits (BAPL) L MSB : Most significant bit LSB : Least significant bit 83 CHAPTER 3 INTERRUPT Table 3.7-1 Channel numbers and descriptor addresses Channel Descriptor address * 0 000100H 1 000108H 2 000110H 3 000118H 4 000120H 5 000128H 6 000130H 7 000138H 8 000140H 9 000148H 10 000150H 11 000158H 12 000160H 13 000168H 14 000170H 15 000178H *: ISD addresses are start addresses in eight bytes. 84 CHAPTER 3 INTERRUPT Description of Extended Intelligent I/O service (EI2OS) descriptor (ISD) 3.7.2 The Extended Intelligent I/O service (EI2OS) descriptor (ISD) consists of the following four types of eight-bit registers: • Data count register (DCT: 2 bytes) • I/O register address pointer register (I/OA: 2 bytes) • EI2OS status register (ISCS: 1 byte) • Buffer address pointer register (BAP: 3 bytes) The initial value of each register is undefined. ■ Data count register (DCT) The data count register (DCT) is a 16-bit register to hold the number of bytes in the data to be transferred. The DCT register is decremented by 1 whenever each byte of data is transferred. EI2OS terminates when the DCT register value becomes "0000H". Figure 3.7-3 Configuration of Data count register (DCT) DCTH Bit 15 14 13 12 11 DCTL 10 9 8 7 6 5 4 3 2 1 0 DCT B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B00 Initial value XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: Read-write X : Undefined ■ I/O register address pointer register (I/OA) The I/O register address pointer register (I/OA) is a 16-bit register that contains the I/O register lower address (A15 to A0) for data transfer. As the upper address (A23 to A16) is "00H", the I/OA register can set I/O addresses from "0000H" to "FFFFH". Figure 3.7-4 Configuration of I/O register address pointer register (I/OA) I/OAH Bit IOA 15 14 13 12 11 I/OAL 10 9 8 7 6 5 4 3 2 1 0 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00 Initial value XXXXXXXXXXXXXXXXB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W: Read-write X : Undefined 85 CHAPTER 3 INTERRUPT ■ Extended Intelligent I/O Service (EI2OS) Status Register (ISCS) The Extended Intelligent I/O service (EI2OS) status register (ISCS) is an eight-bit register to update/fix the buffer address pointer and I/O register address pointer and to set the transfer data format (in bytes or words) and transfer direction. Figure 3.7-5 Configuration of EI2OS status register (ISCS) Bit 7 6 5 RESV RESV RESV R/W R/W R/W 4 3 2 1 0 Initial value IF BW BF DIR SE XXXXXXXX B R/W R/W R/W R/W R/W SE EI2OS termination control bit 0 Not terminated by a request from the peripheral function. Terminated by a request from the peripheral function 1 Data transfer direction specification bit DIR 0 1 I/O register address pointer -> buffer address pointer. Buffer address pointer -> I/O register address pointer BAP update/fixed selection bit BF 0 After data transfer, the buffer address pointer is updated. (*1) 1 After data transfer, the buffer address pointer is not updated. BW Transfer data length specification bit 0 Byte 1 Word IF IOA update/fixed selection bit 0 After data transfer, the I/O register address pointer is updated. (*2) 1 After data transfer, the buffer address pointer is not updated. RESV Reserved bits 0 must be written to these bits. R/W : Read-write X : Undefined *1 : Only the lower 16 bits of the buffer address pointer change. The buffer address pointer can only be incremented. *2 : The address pointer can only be incremented. 86 CHAPTER 3 INTERRUPT ■ Buffer Address Pointer register (BAP) The buffer address pointer register (BAP) is a 24-bit register that contains the memory address of the data transfer source during EI2OS operation. Since the BAP register exists for each EI2OS channel, data can be transferred between 16-megabyte memory addresses and peripheral resource addresses. When the BAP update/fix bit (BF) in the EI2OS status register (ISCS) is set to "0", the lower 16 bits (BAPM, BAPL) are incremented while the upper eight bits (BAPH) are not incremented. Figure 3.7-6 Configuration of buffer address pointer register (BAP) bit23 BAP to bit16 bit15 to bit8 bit7 to BAPH BAPM BAPL (R/W) (R/W) (R/W) bit0 Initial value XXXXXXB R/W : Read-write X : Undefined Reference: • The maximum number of transfers that can be set by the data count register (DCT) is 65,536 (64 kilobytes). • The area that can be set by the I/O address pointer register (I/OA) is from "000000H" to "00FFFFH". • The area that can be set by the buffer address pointer register (BAP) is from "000000H" to "FFFFFFH". 87 CHAPTER 3 INTERRUPT 3.7.3 Operation of Extended Intelligent I/O Service (EI2OS) When a peripheral resource outputs an interrupt request with the interrupt control register (ICR) set in advance to activate EI2OS, the CPU transfers data using EI2OS. A hardware interrupt is caused upon completion of the EI2OS process. ■ Processing procedure of the Extended Intelligent I/O Service (EI2OS) Figure 3.7-7 Operation flow of Extended Intelligent I/O Service (El2OS) Interrupt request generated by peripheral function ISE="1" NO YES Interrupt sequence Read ISD/ISCS Termination request from peripheral function YES NO DIR="1" YES SE="1" NO YES NO Data indicated by BAP (data transfer) memory indicated by I/OA Data indicated by I/OA (data transfer) memory indicated by BAP IF="0" YES NO Update value by BW Update I/OA Update value by BW Update BAP YES BF="0" NO Decrement DCT DCT="00B" NO (-1) YES Set S1 and S0 to "00B" EI2OS termination processing Set S1 and S0 to "01B" Clear interrupt request from the peripheral function Clear ISE to "0" Return to CPU operation ISD : EI2OS descriptor ISCS : EI2OS status register IF : I/OA update/fixed selection bit in the EI2OS status register (ISCS) BW : Transfer data length specification bit in the EI2OS status register (ISCS) BF : BAP update/fixed selection bit in the EI2OS status register (ISCS) 88 Set S1 and S0 to "11B" Interrupt sequence DIR : Data transfer direction specification bit in the EI2OS status register (ISCS) SE : EI2OS termination control bit in the EI2OS status register (ISCS) DCT : Data counter I/OA : I/O register address pointer BAP : Buffer address pointer ISE : EI2OS enable bit in the interrupt control register (ICR) S1, S0: EI2OS status in the interrupt control register (ICR) CHAPTER 3 INTERRUPT 3.7.4 Setting procedure of Extended Intelligent I/O Service (EI2OS) The Extended Intelligent I/O service (EI2OS) is set by the system stack area, Extended Intelligent I/O service (EI2OS) descriptor, peripheral resource, and interrupt control register (ICR). ■ Setting procedure of Extended Intelligent I/O Service (EI2OS) Figure 3.7-8 Setting procedure of Extended Intelligent I/O Service (EI2OS) Software processing Hardware processing Start Initialization Set the system stack area Set the EI2OS descriptor Initialize the peripheral function Set the interrupt control register (ICR) Set the built-in resource to start operation. Set the interrupt enable bit Set the ILM and I in the PS Execute the user program (Interrupt request) and (ISE = "1") S1, S0 = "00B" Transfer data Decide whether to end counting or to branch to an interrupt requested by the resource (Branch to interrupt vector) YES S1, S0 = "01B" or S1, S0 = "11B" Set the extended intelligent NO I/O service again (switch channels) Process data in the buffer RETI ISE : EI2OS enable bit in the interrupt control register (ICR) S1, S0 : EI2OS status of the interrupt control register (ICR) 89 CHAPTER 3 INTERRUPT 3.7.5 Processing Time for Extended Intelligent I/O Service (EI2OS) The time required for the processing of the Extended Intelligent I/O service (EI2OS) depends on the settings in the Extended Intelligent I/O service descriptor (ISD). Setting of the EI2OS status register (ISCS) Address set by the I/O register address pointer register (I/OA) Address set by the buffer address pointer register (BAP) External data bus width for external access Transfer data length • • • • • As a hardware interrupt is activated upon completion of data transfer by EI2OS, the time for handling the interrupt is added. ■ Processing time for Extended Intelligent I/O service (EI2OS) (Time for each transfer) ❍ To continue data transfer The EI2OS processing time taken when EI2OS continues data transfer depends on the EI2OS status register (ISCS) setting as shown in Table 3.7-2 "Execution time for Extended Intelligent I/O service". Table 3.7-2 Execution time for Extended Intelligent I/O service Setting in EI2OS termination control bit (SE) Setting in I/OA update/fix bit (IF) Setting in BAP address update/fix selection bit (BF) Terminates due to termination request from the peripheralI Ignores termination request from the peripheral Fix Update Fix Update Fix 32 34 33 35 Update 34 36 35 37 Unit: Machine cycle (One machine cycle corresponds to one clock cycle of the machine clock (φ).) The EI2OS processing time taken when EI2OS continues data transfer must be corrected according to the EI2OS execution conditions as shown in Table 3.7-3 "Correction values for EI2OS execution time for data transfer". 90 CHAPTER 3 INTERRUPT Table 3.7-3 Correction values for EI2OS execution time for data transfer I/O register address pointer Buffer address pointer Internal access External access B/Even Odd B/Even 8/Odd 0 +2 +1 +4 Internal access B/Even Odd +2 +4 +3 +6 External access B/Even +1 +3 +2 +5 8/Odd +4 +6 +5 +8 B: Byte data transfer 8: Word transfer with external bus width of 8 bits Even: Even-address word transfer Odd: Odd-address word transfer ❍ When the data counter (DCT) is exhausted (upon completion of the last data transfer) As a hardware interrupt is activated upon completion of data transfer by EI2OS, the time for handling the interrupt is added. The EI2OS processing time when the count is exhausted is calculated from the following equation. "Z" in the equation represents the correction value for interrupt handling time. EI2OS processing time at count end = EI2OS processing time for data is transfer + (21 + 6 x Z) machine cycles Interrupt handling time The interrupt handling time depends on the address held in the stack pointer. Table 3.7-4 Correction value (Z) for interrupt handling time Address contained in the stack pointer Interpolation value (Z) When the external interrupt is for 8-bit transfer +4 When the external interrupt is for even-address transfer +1 When the external interrupt is for odd-address transfer +4 When the internal interrupt is for even-address transfer 0 When the internal interrupt is for odd-address transfer +2 91 CHAPTER 3 INTERRUPT ❍ When data transfer is ended by the terminate request by the peripheral resource If data transfer by EI2OS is terminated prematurely in response to the terminate request by the peripheral resource (ICRÅFS1,S0="11B"), a hardware interrupt occurs without executing the data transfer. The EI2OS processing time is calculated from the following equation. "Z" in the equation represents the correction value for interrupt handling time. (See Table 3.7-4 "Correction value (Z) for interrupt handling time ".) EI2OS processing time on halt = (36 + 6 x Z) machine cycles Reference: One machine cycle corresponds to one clock cycle of the machine clock (φ). 92 CHAPTER 3 INTERRUPT 3.8 Exception Processing Interrupt by Executing Undefined Instruction The F2MC-16LX performs exception processing by executing an undefined instruction. Exception processing is basically the same with an interrupt (i.e., interrupts normal processing and starts exception processing if exceptional event generation is detected when processing moves to the next instruction). Generally, exception processing is generated when an unexpected operation is done. Therefore, use of exception processing is recommended only for debugging or if recovery software has been started for emergency use. ■ Exception processing interrupt by executing undefined instruction ❍ Exception processing operation The F2MC-16LX treats all codes not defined on an instruction map as an undefined instruction. If undefined instructions are executed, the same processing as that for a software interrupt instruction such as "INT #10" is performed. Exception processing performs the following processing before branching to the interrupt routine. • Stores the A, DPR, ADB, DTB, PCB, PC, PS registers in the system stack. • Clears the I-flag of the condition code register (CCR) to "0", masking the hardware interrupt. • Sets the S-flag of the condition code register (CCR) to "1", enabling operation of the system stack. A program counter (PC) value stored in the stack represents an address where an undefined instruction is stored. An instruction code of two bytes or more is the address where a code identified as "undefined" is stored. In the exception processing routine, if the type of exception factor must be identified, use this PC value. ❍ Return from exception processing During a return from exception processing with the RETI instruction, another exception processing starts since PC points to an undefined instruction. Take appropriate action, such as a software reset. 93 CHAPTER 3 INTERRUPT 3.9 Stack Operation of Interrupt Processing If an interrupt is accepted, contents of the dedicated registers are automatically stored in the system stack before branching to interrupt processing. Return from the stack is also automatically performed when interrupt processing is completed. ■ Stack operation when interrupt processing starts With an accepted interrupt, CPU automatically stores the contents of the current dedicated registers in the system stack in the following sequence: 1. Accumulator (A) 2. Direct page register (DPR) 3. Additional data bank register (ADB) 4. Data bank register (DTB) 5. Program bank register (PCB) 6. Program counter (PC) 7. Processor status (PS) Figure 3.9-1 "Stack operation at start of interrupt processing" shows the stack operation when interrupt processing starts. Figure 3.9-1 Stack operation at start of interrupt processing Immediately before interrupt SSB SSP A Address 08FFH 08FEH 00H 08FEH 0000H 08FEH AH AL DPR 01H ADB 00H DTB 00H PCB FFH PC 803FH PS 20E0H 08F2H SSB Address 08FFH 08FEH 00H SP XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH XXH Byte 94 Immediately after interrupt Memory H SSP A 08F2H 0000H 08FEH AH L Memory AL DPR 01H ADB 00H DTB 00H PCB FFH PC 803FH PS 20E0H 08F2H SP 00H 00H 08H FEH 01H 00H 00H FFH 80H 3FH 20H E0H Byte AH AL DPR ADP DTB PCB PC PS SP after updating CHAPTER 3 INTERRUPT ■ Stack operation during return from interrupt processing At the end of interrupt processing, if the interrupt return instruction (RETI) is executed, PS, PC, PCB, DTB, ADB, DPR, and A values are returned from the stack in the reverse order of the interrupt processing. The dedicated registers are then restored to their previous state (i.e., immediately before the interrupt started). ■ Stack area ❍ Assigning the stack area The stack area is used for storage and return of the program counter (PCD) required for executing interrupt processing, subroutine call instruction (CALL) and vector call instruction (CALLV), as well as temporary storage and return of registers executed by using the PUSHW and POPW instructions. The stack area is assigned in RAM in addition to the data area. Figure 3.9-2 "Stack area" shows the stack area. Figure 3.9-2 Stack area Vector table FFFFFFH (Reset/interrupt vector call instructions) FFFC00H ROM area FF0000H*1 000D00H*2 Built-in RAM area Stack area 000380H General-purpose register bank area 000180H 000100H 0000D0H 000000H Built-in I/O area *1 Built-in ROM capacity differs depending on the product type. *2 Built-in RAM capacity differs depending on the product type. Note: • If specifying addresses of the stack pointers (SSP, USP), specify them with even numbers. • Assign the system stack area, user stack area, and data area while avoiding duplication with one another. ❍ System stack and user stack Interrupt processing uses the system stack area. Even if the user stack area is being used when an interrupt occurs, it is forcibly switched to the system stack. Thus, the system that uses primarily the user stack area must also correctly prepare the system stack area. Use only the system stack unless the stack space must be separated. 95 CHAPTER 3 INTERRUPT 3.10 Sample Program of Interrupt Processing A sample program for interrupt processing is shown below. ■ Sample program for interrupt processing ❍ Processing specification An example of an interrupt program using external interrupt 0 (INT0) is shown. Sample coding from the program is shown below. [Coding example] DDR1 ENIR EIRR ELVR ICR00 STACK EQU 000011H ;Port 1 direction register EQU 028H ;Interrupt/DTP enable register EQU 029H ;Interrupt/DTP flag EQU 02AH ;Request level set register EQU 0B0H ;Interrupt control register SSEG ;Stack RW 100 STACK_T RW 1 STACK ENDS ;-----------Main program---------------------------------------------------------CODE CSEG START: MOV RP,#0 ;General-purpose register use of ;header bank MOV ILM,#07H ;PS:ILM is set to level 7 MOV A,#!STACK_T ;Definition of system stack MOV SSB,A MOVW A,#STACK_T ;Setting of stack pointer, where MOVW SP,A ;it is set to SSPS since S-flag = 1 MOV DDR1,#00000000B ;P10/INT0 pin is set to input OR CCR,#40H ;I-flag in PS:CCR is set for interrupt enable MOV I:ICR00,#00H ;Interrupt set to level 0 (highest) MOV I:ELVR,#00000001B ;INT0 is set to H-level request MOV I:EIRR,#00H ;INT0 interrupt factor cleared MOV I:ENIR,#01H ;INT0 input enable : LOOP: NOP ;Dummy loop NOP NOP NOP BRA LOOP ;Unconditional jump ;-----------Interrupt handling routine-------------------------------------------ED_INT1: MOV I:EIRR,#00H ;Prohibition of acceptance of new ;INT0 NOP NOP NOP NOP NOP NOP RETI ;Return from interrupt CODE ENDS ;-----------Vector setting-------------------------------------------------------VECT CSEG ABS=OFFH ORG OFFDOH ;Vector is set to interrupt #11(0BH) DSL ED_INT1 ORG OFFDCH ;Reset vector setting DSL START DB 00H ;Set to single chip mode VECT ENDS END START 96 CHAPTER 3 INTERRUPT ■ Processing Specifications of Sample Program for Extended Intelligent I/O Service (EI2OS) ❍ Processing Specifications • This program detects the "H" level signal input to the INT0 pin and activates the extended intelligent I/O service (EI2OS). • When the "H" level is input to the INT0 pin, El2OS is activated. Data is transferred from port 0 to the memory at the "3000H" address. • The number of transfer data bytes is 100 bytes. After 100 bytes are transferred, an interrupt is generated because EI2OS transfer has terminated. ❍ Sample coding DDR1 ENIR EIRR ELVR ICR00 BAPL BAPM BAPH ISCS I/OAL I/OAH DCTL DCTH ER0 STACK EQU 000011H ;Port 1-direction register EQU 000030H ;DTP/interrupt permission register EQU 000031H ;DTP/interrupt cause register EQU 000032H ;Request level setting register EQU 0000B0H ;Interrupt control register 00 EQU 000100H ;Lower buffer address pointer EQU 000101H ;Middle buffer address pointer EQU 000102H ;Upper buffer address pointer EQU 000103H ;EI2OS status EQU 000104H ;Lower I/O address pointer EQU 000105H ;Upper I/O address pointer EQU 000106H ;Low-order data counter EQU 000107H ;High-order data counter EQU EIRR:0 ;Definition of external interrupt request flag bit SSEG ;Stack RW 100 STACK_T RW 1 STACK ENDS ;-------------------Main program------------------------------------------------CODE CSEG START: AND CCR, #0BFH ;Clears the I flag of the CCR in the PS and ;prohibits interrupts. MOV RP, #00 ;Sets the register bank pointer. MOV A, #!STACK_T ;Sets the system stack. MOV SSB, A MOVW A, #STACK_T ;Sets the stack pointer, then MOVW SP, A ;Sets SSP because the S flag = 1. MOV I:DDR1, #00000000B ;Sets the P10/INT0 pin to input. MOV BAPL, #00H ;Sets the buffer address (003000H). MOV BAPM, #30H MOV BAPH, #00H MOV ISCS, #00010001B ;No I/O address update, byte transfer, buffer ;address updated, I/O -> buffer transfer, ;terminated by the peripheral function(resource). MOV IOAL, #00H ;Sets the transfer source address ;(port 0:000000H). MOV IOAH, #00H MOV DCTL, #64H ;Sets the number of transfer bytes (100 bytes). MOV DCTH, #00H 97 CHAPTER 3 INTERRUPT MOV MOV MOV MOV MOV OR I:ICR00,#00001000B ;EI2OS channel 0, EI2OS enable, interrupt level 0 ;(highest priority) I:ELVR, #00000001B ;Requests that INT0 be made H level. I:EIRR, #00H ;Clears the INT0 interrupt cause. I:ENIR, #01H ;Enables INT0 interrupts. ILM, #07H ;Sets the ILM in the PS to level 7. CCR, #040H ;Sets the I flag of the CCR in the PS and ;enables interrupts. : LOOP BRA LOOP ;Infinite loop ;---------------Interrupt program-----------------------------------------------WARI CLRB ER0 ;Clears interrupt/DTP request flag. : User processing ;Checks EI2OS termination factor, : ;processes data in buffer, sets EI2OS again. RETI CODE ENDS ;---------------Vector processing-----------------------------------------------VECT CSEG ABS=0FFH ORG 0FFD0H ;Sets vector for interrupt #11 (0BH). DSL WARI ORG 0FFDCH ;Sets reset vector. DSL START DB 00H ;Sets single-chip mode. VECT ENDS END START 98 CHAPTER 3 INTERRUPT 3.11 Delay Interrupt Event Module The delay interrupt event module is a module that generates an interrupt for task switching. Using this module allows generation and clearing of an interrupt request to the F2MC-16LX CPU by software. ■ Block diagram of delay interrupt event module Figure 3.11-1 "Block diagram of delay interrupt event module" is a block diagram of the delay interrupt event module. Figure 3.11-1 Block diagram of delay interrupt event module F2MC-16LX bus Delay interrupt request generate/clear decoder Factor latch ■ List of registers in delay interrupt event module The delay interrupt event module, delay interrupt factor originate/clear register (DIRR: delayed interrupt request register), has the register configuration shown below. Bit 15 14 00009FH 13 12 11 10 9 8 Initial value R0 -------0B R/W R/W: Read/write enabled The delay interrupt factor originate/clear register (DIRR) is a register used to generate/clear the delay interrupt factor. Writing "1" to the register results in a request to delay an interrupt, and writing "0" clears the delay interrupt request. Resetting causes the factor clear state. Either "0" or "1" can be written to the reserve bit area. For future expansion, however, Fujitsu recommends using the set bit or clear bit instructions to access this register. 99 CHAPTER 3 INTERRUPT 3.11.1 Operation of Delay Interrupt Event Module If CPU software writes "1" to the relevant DIRR bit with software, the request latch in the delay interrupt event module is set to generate an interrupt request to the interrupt controller. ■ Operation of delay interrupt event module If CPU software writes "1" to the relevant DIRR bit, the request latch in the delay interrupt event module is set to generate an interrupt request to the interrupt controller. If other interrupt requests have a priority lower than this interrupt or there are no other interrupt requests, the interrupt controller generates an interrupt to the F2MC-16LX CPU. The F2MC-16LX CPU compares the interrupt request with the ILM bit in the internal CCR register, and if the request level is higher than that of the ILM bit, the hardware interrupt processing micro-program starts immediately after the instruction currently being executed is completed. As a result, the interrupt routine for this interrupt is executed. By writing "0" to the relevant DDIR bit within the interrupt processing routine, this interrupt factor is cleared and the task is switched. The above operation flow is illustrated in the Figure 3.11-2 "Operation of delay interrupt event module". Figure 3.11-2 Operation of delay interrupt event module Delay interrupt originate module Interrupt controller F2MC-16LX CPU Other request ICRXX ICRYY DDIR CMP ICRXX CMP ICRXX NTA ■ Notes on using delay interrupt event module (delay interrupt request latch) This latch is set by writing "1" to the relevant DIRR bit, and cleared by writing "0" to the same bit. Be sure to create software so that a factor is cleared in the interrupt processing routine. Otherwise, interrupt processing starts soon after the system returns from interrupt factor processing. 100 CHAPTER 4 RESET This chapter explains reset for the MB90470 series. 4.1 "Overview of Reset" 4.2 "Reset Factors and Oscillation Stabilization Wait Time" 4.3 "External-Reset Pin" 4.4 "Resetting" 4.5 "Reset-Factor Bits" 4.6 "Condition of Pins as Result of Reset" 101 CHAPTER 4 RESET 4.1 Overview of Reset If a reset factor occurs, the CPU immediately stops the processing currently in progress and stands by for cancellation of the reset. After the reset is canceled, processing starts at the address specified by the reset vector. A reset is triggered by the following four factors: • Power-on reset • Watchdog timer overflow • External reset request from RST pin • Software reset request ■ Reset factors Table 4.1-1 "Reset factors" summarizes the reset factors. Table 4.1-1 Reset factors Reset Reset factor Machine clock Watchdog timer Waits until oscillation is stabilized? Power on When power is turned on Main clock (MCLK) Stopped Yes Watchdog timer Watchdog timer overflow Main clock (MCLK) Stopped No External pin "L"-level input to pin RST Main clock (MCLK) Stopped No Software "0" is written in internal reset signal bit (RST) of low-power consumption mode control register (LPMCR) Main clock (MCLK) Stopped No Main clock: clock of oscillation clock divided by two ❍ Power-on reset A power-on reset occurs when the power is turned on. The oscillation stabilization wait time for evaluation devices and FLASH devices is 218/HCLK (about 65.54 ms where the oscillation clock is 4 MHz). The oscillation stabilization wait time for mask devices is fixed at 217/HCLK (about 32.77 ms where the oscillation clock is 4 MHz). A reset is performed after the end of the oscillation stabilization wait time. ❍ Watchdog reset A watchdog reset is triggered by a watchdog timer overflow if "0" is not written in the watchdog control bit (WTE) of the watchdog timer control register (WDTC) within a preset time after the watchdog timer is activated. The oscillation stabilization wait time can be specified in the clock selection register (CKSCR). 102 CHAPTER 4 RESET ❍ External reset An external reset is triggered by input of the "L" level to the external-reset pin (pin RST). More than 16 machine cycles (16/φ) is required for the "L"-level input time to pin RST. An external reset (pin RST input reset) does not require the oscillation stabilization wait time. Reference: After an instruction processing ends, the reset cancellation waiting state is set only when a reset request is issued via pin RST because of the event where a reset factor is triggered during writing (such as the MOV instruction while a transfer instruction is being executed). Writing thus ends normally even if a reset is input during writing. However, string instructions (such as the MOVS instruction) accept a reset before a transfer completes at the specified count, so the transfer of all data cannot be assured. Reset requests are also accepted when a bus cycle extension with pin RDY continues for more than 16 machine cycles during external bus access. ❍ Software reset In a software reset, an internal reset is triggered by writing "0" in the internal reset signal bit (RST) of the low-power consumption mode control register (LPMCR). A software reset does not require the oscillation stabilization wait time. Reference: Definition of clock HCLK: Oscillation clock (clock supplied via high-speed oscillation pin) MCLK: Main clock (clock of HCLK divided by two) SCLK: Sub-clock (clock divided by four, supplied via low-speed oscillation pin) φ: Machine clock (CPU operation clock) 1/φ: Machine cycle (CPU operation clock period) Refer to Section 5.1 "Overview of clocks", for a detailed information on machine clocks. Note: The oscillation stabilization wait time of 217/HCLK (about 32.77 ms where the oscillation clock is 4 MHz) is required if a reset is triggered in the stop mode or the sub-clock mode. Refer to Section 5.4 "Clock Modes", for a detailed information on clock modes. 103 CHAPTER 4 RESET 4.2 Reset Factors and Oscillation Stabilization Wait Time The four types of reset factors can occur in the MB90470-series devices. The oscillation stabilization wait time during a reset varies depending on the reset factor. ■ Reset factors and oscillation stabilization wait time Table 4.2-1 "Reset factors and oscillation stabilization wait time" summarizes the reset factors and the oscillation stabilization wait time. Table 4.2-1 Reset factors and oscillation stabilization wait time Reset factors Oscillation stabilization wait time The value in parentheses ( ) is a period when oscillation clock is 4 MHz Power-on reset Evaluation devices/FLASH devices: 218/HCLK (about 65.54 ms). Mask devices: 217/HCLK (about 32.77 ms) Watchdog timer None: Bits WS1 and WS0 are initialized to "11". External reset via pin RST None: Bits WS1 and WS0 are initialized to "11". Software reset None: Bits WS1 and WS0 are initialized to "11". HCLK: Oscillation clock WS1, WS0: Bits for selecting oscillation stabilization wait time of clock selection register (CKSCR) Figure 4.2-1 "Waiting times to stable oscillation for evaluation devices/FLASH devices and mask devices during power-on reset" shows the oscillation stabilization wait time for evaluation devices, FLASH devices, and mask devices during a power-on reset. 104 CHAPTER 4 RESET Figure 4.2-1 Waiting times to stable oscillation for evaluation devices/FLASH devices and mask devices during power-on reset Evaluation device/FLASH device Vcc 217/HCLK 217/HCLK CLK CPU operation Stabilization wait time of regulator oscillation stabilization wait time Mask device Vcc 217/HCLK CLK CPU operation oscillation stabilization wait time HCLK: Oscillation clock Note: Ceramic and crystal oscillators generally require a waiting time ranging from several milliseconds to several ten milliseconds after the start of oscillation until oscillation stabilizes at a specific frequency. Therefore, specify a oscillation stabilization wait time suitable for the oscillator used. Refer to Section 5.5 "Oscillation Stabilization Wait Time", for more information. ■ Reset state waiting for stable oscillation A reset during the power-on sequence and a reset in response to a reset request in the stop and sub-clock modes is performed after the end of the oscillation stabilization wait time created by the timebase timer. In this event, a reset is performed after an external reset is canceled unless external reset input is cleared. 105 CHAPTER 4 RESET 4.3 External-Reset Pin The external-reset pin (pin RST) is a pin dedicated for the input of resets, and it triggers an internal reset by input of the "L" level. The MB90470 series devices have resets synchronized to the CPU operation clock. However, only external pins (e.g., ports) change asynchronously to a reset state. ■ Block diagram of external-reset pin Figure 4.3-1 "Block diagram of internal reset" shows the block diagram of internal reset. Figure 4.3-1 Block diagram of internal reset CPU operation clock (PLL multiplier circuit, clock of HCLK divided by two) RST CPU Pch Synchronization circuit Pin Nch Input buffer Peripheral function I/O ports, etc. HCLK: Oscillation clock Note: To prevent damage to the memory contents by a reset during writing, input to pin RST is accepted in a cycle that precludes damage to memory contents. A clock is required to initialize internal circuits. Input of a clock is required during input of a reset when an external clock is used for operation. 106 CHAPTER 4 RESET 4.4 Resetting Cancellation of a reset, a read from operation of mode data, and the reset vector can be selected by setting the mode pin to perform mode fetching. Mode fetching determines the CPU operation mode and the start address of execution after the end of a reset. When the power is turned on or when the system is returned from the stopmode by a reset, perform mode fetching after the end of the oscillation stabilization wait time. ■ Overview of resetting Figure 4.4-1 "Flow of resetting" shows the flow of resetting. Figure 4.4-1 Flow of resetting Power-on reset Stop mode Sub clock mode Reset in progress Mode fetching (reset) External reset Software reset Watchdog timer reset Reset state to wait for stable oscillation Fetch of mode data Pin state and function changes related to external bus mode Fetch of reset vector Normal operation (run state) Fetch of instruction code from addresses indicated by a reset vector, and execution of instruction ■ Mode pins Mode pins (MD2 to MD0) specify a method to fetch reset vectors and mode data. A reset vector and mode data are fetched in a sequence for resetting. Refer to Section 7.2 "Mode Pins (MD2 to MD0)", for details of the mode pins. 107 CHAPTER 4 RESET ■ Mode fetch After a reset is canceled, the CPU transfers the reset vectors and mode data to the applicable registers in the CPU core. The reset vectors and mode data are allocated to four bytes, namely FFFFDCH to FFFFDFH. Upon a reset cancellation, the CPU immediately outputs these addresses to a bus and fetches reset vectors and mode data. During mode fetching, the CPU starts processing beginning from the address specified by the reset vector. Figure 4.4-2 "Transfer of reset vectors and mode data" shows transfer of reset vectors and mode data. Figure 4.4-2 Transfer of reset vectors and mode data F2MC-16LX CPU Core Memory space FFFFDFH Mode data FFFFDEH Reset vector bits 23 to 16 FFFFDDH Reset vector bits 15 to 8 FFFFDCH Reset vector bits 7 to 0 Mode register Micro ROM Sequence for resetting PCB PC Reference: Use a mode pin, from which reset vectors and mode data are read, to specify either internal ROAM or external memory. If the external vector mode is specified with a mode pin, however, external memory and not internal ROM is accessed to read reset vectors and mode data. Fujitsu recommends specifying the internal vector mode with a mode pin when the single-chip mode and internal ROM external bus mode are used. ❍ Mode data (Address: FFFFDFH) The data in the mode register can be modified only by a reset, and the mode register settings become effective after a reset. Refer to Section 7.3 "Mode Data", for details on mode data. ❍ Reset vector (Address: FFFFDCH to FFFFDEH) Write the execution start address after the end of a reset. Execution starts from this address. 108 CHAPTER 4 RESET 4.5 Reset-Factor Bits Reset factors can be determined by reading the watchdog timer control register (WDTC). ■ Reset-factor bits As shown in the Figure 4.5-1 "Block diagram of reset-factor bits", each reset factor has a corresponding flip-flop assigned to it. This information can be obtained by reading the watchdog timer control register (WDTC). If a reset factor must be determined after a reset cancellation, run software to process the read value of the WDTC register, and branch to an appropriate program. Figure 4.5-1 Block diagram of reset-factor bits Pin RST Power on RST=L Power-on detection circuit External reset request detection circuit Watchdog timer control register (WDTC) S F/F Q R No periodic clearing S R S F/F Watchdog timer reset detection circuit R LPMCR and RST bit writing detection circuit S F/F Q Q RST bit set F/F R Delay circuit Q Reading of watchdog timer control register (WDTC) F2MC-16LX Internal bus S: Set; R: Reset; Q: Output; F/F: Flip-flop 109 CHAPTER 4 RESET ■ Correspondence between reset-factor bits and reset factors Figure 4.5-2 "Configuration of reset-factor bits (watchdog timer control register)" shows the configuration of the reset-factor bits of the watchdog timer control register (WDTC). Table 4.5-1 "Correspondence between reset-factor bits and reset factors" shows the correspondence between reset-factor bits and reset factors. For details, refer to Section 10.2 "Watchdog Timer Control Register (WDTC)". Figure 4.5-2 Configuration of reset-factor bits (watchdog timer control register) Bit 0000A8H 15 - 8 (TBTC) 7 6 5 4 PONR Reserved WRST ERST X R X R X R 3 SRST 2 WTE 1 WT1 0 WT0 X R 1 W 1 W 1 W X R Initial value R/W R: Read only; W: Write only; W: Not fixed Table 4.5-1 Correspondence between reset-factor bits and reset factors Reset factor PONR WRST ERST SRST Power-on reset 1 X X X Watchdog timer overflow * 1 * * External reset request via pin RST * * 1 * Software reset request * * * 1 Note 1: An asterisk (*) indicates an undefined bit. ■ Cautions about reset-factor bits ❍ If more than one reset factor occurs If more than one reset factor occurs, the individual reset-factor bits of the WDTC register are set to "1". For example, if an external reset via pin RST is requested at the same time as a watchdog timer overflow occurs, bits ERST and WRST of the reset-factor bits are set to "1". ❍ Power-on reset During a power-on reset, bit PONR of the reset-factor bits is set to "1". However, the resetfactor bits other than bit PONR are undefined. Therefore, if bit PONR is "1", create software so that reset-factor bits other than bit PONR are ignored. ❍ Clearing reset-factor bits The reset-factor bits is cleared only if the data in the WDTC register is read. Bits corresponding to reset factors that have occurred once are not cleared even if a reset is triggered (remains "1"). Note: The values of the WDTC register may be incorrect if the power is turned on under a condition that precludes a power-on reset. 110 CHAPTER 4 RESET 4.6 Condition of Pins as Result of Reset This section explains the states of pins after a reset. ■ Pin states during a reset States of the pins during a reset are determined by the settings of mode pins MD2 to MD0. ❍ If the internal vector mode is set (MD2 to MD0 = "011B") All I/O pins (resource pins) become set at the high-impedance state, and mode data is read from internal ROM. Refer to Section 6.7 "Pin States in Standby Mode, Hold, and Reset", for the states of pins during a reset. ■ Pin states after mode data Is read The states of the pins after mode data is read are determined by mode data (M1, M0). ❍ If the single-chip mode is set (M1, M0 = "00B") All I/O pins (resource pins) become set at the high-impedance state, and mode data is read from the internal ROM. Note: Take care with the pins that have the high-impedance state during a reset so that equipment connected to the pins do not malfunction. 111 CHAPTER 4 RESET 112 CHAPTER 5 CLOCKS This chapter describes the clocks of the MB90470 series. 5.1 "Overview" 5.2 "Block Diagram of Clock Generator" 5.3 "Clock Selection Register (CKSCR)" 5.4 "Clock Modes" 5.5 "Oscillation Stabilization Wait Time" 5.6 "Connecting Oscillator to External Clock" 113 CHAPTER 5 CLOCKS 5.1 Overview The clock generator controls the operations of internal clocks, which are the operation clocks of the CPU and peripheral functions. In this document, the clocks are called as follows according to clock type: • Machine clock: Defined as an internal clock. • Machine cycle: Defined as one period of a machine clock. • Oscillation clock: Defined as a clock supplied via a high-speed oscillation pin. • PLL clock: Defined as a clock using internal PLL oscillation. • Sub-clock: Clock divided by four, provided from a low-speed oscillation pin. ■ Overview of clocks The clock generator contains an oscillation circuit and generates an oscillation clock and subclock by using an external connection to an oscillator. The generator generates an oscillation clock by inputting a clock generated externally. The generator contains a PLL clock multiplier circuit and generates four multiplication clocks of an oscillation clock. The clock generator controls the oscillation stabilization wait time, PLL clock multiplication, and operations of internal clocks by changing the clock of the clock selector. ❍ Oscillation clock (HCLK) This clock is generated by connecting an oscillator to the high-speed oscillation pin or by inputting an external clock. ❍ Sub-clock (SCLK) This clock operates the watch timer. It can also be used as a low-speed machine clock. This clock is divided by four and created by connecting an oscillator to the low-speed oscillation pin or by inputting an external clock. ❍ Main clock (MCLK) This is clock of the oscillation clock divided by two, and is used as an input clock to the timebase timer and clock selector. ❍ PLL clock (PCLK) This clock is a clock obtained by multiplying with the built-in PLL clock multiplier circuit (PLL oscillation circuit). Four types of the clocks can be selected. ❍ Machine clock (φ φ) This clock is an operation clock of the CPU and peripheral functions. One period of this clock is used as a machine cycle (1/φ). One clock can be selected from among the main clock (clock of oscillation clock divided by two), sub-clock, and four types of multiplication clocks. Note: Oscillation clocks have an oscillation frequency ranging from 3 to 20 MHz. The maximum operating frequency of the CPU and peripheral functions is 20 MHz. If a multiplication rate is specified and the specified value exceeds the maximum operating frequency, the device does not operate correctly. For example, if the source oscillation is 20 MHz, only clock 114 CHAPTER 5 CLOCKS multiplied by one can be specified. PLL oscillation can be between 3 and 20 MHz. This oscillation range varies depending on operating voltage and the multiplication rate. ■ Clock supply map Machine clocks generated by the clock generator are supplied as operation clocks of the CPU and peripheral functions. Therefore, operations of the CPU and peripheral functions are affected by changes between the main clock and PLL clock (clock mode) and by changes in the PLL clock multiplication rate. The clock-divided outputs of the timebase timer are supplied to some peripheral functions, and the peripheral functions can select their own operation clocks. Figure 5.1-1 "Clock supply map" shows a clock supply map. Figure 5.1-1 Clock supply map Peripheral functions 4 Watchdog timer 4 8/16-bit PPG timer 0 8/16-bit PPG timer 1 Watch timer X0A Pin X1A Pin 8/16-bit PPG timer 2 Timebase timer Sub clock generator circuit 1 2 3 4 16-bit reload timer 0 PLL multiplier circuit X0 Pin X1 Pin Clock divided by four SCLK PCLK System Clock divided clock Clock selector by two generator MCLK circuit HCLK φ UART I/O extensive serial interface 2 channels CPU, PPG2, 3 Pin PPG4, 5 Pin TIN0 Pin TOT0 Pin SCK0, SIN0 Pin SOT0 Pin SCK1, 2 SIN1, 2 Pin SOT1, 2 Pin DMA 8/16-bit U/D counter Chip selection 16-bit output compare HCLK : MCLK : SCLK : PCLK : φ : PPG0, 1 Pin Oscillation clock Main clock Sub clock PLL clock Machine clock CS0, 1, 2,3 Pin OUT0, 1, 2, 3, 4, 5 Pin 16-bit freerunning timer FRCK Pin 16-bit input capture IN0, 1 Pin 10-bit A/D converter External interrupt PG I2 C interface 16-bit PWC 3 channels 3 AIN0, 1 BIN0, 1 ZIN0, 1 Pin AN0 to AN7, ADTG Pin IRQ0 to IRQ7 Pin EXTC Pin NIT00, NIT01 Pin SCL, SDA Pin PWC1, 2, 3 Pin Control of oscillation stabilization wait 115 CHAPTER 5 CLOCKS 5.2 Block Diagram of Clock Generator The clock generator consists of the following five blocks: • System clock generator circuit • PLL multiplier circuit • Clock selector • Clock selection register (CKSCR) • Selector for oscillation stabilization wait time ■ Block diagram of clock generator Figure 5.2-1 "Block diagram of clock generator" is a block diagram of the clock generator. Figure 5.2-1 "Block diagram of clock generator" also includes the standby control circuits and timebase timer circuit. Figure 5.2-1 Block diagram of clock generator Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin highimpedance control circuit RST Internal reset generator circuit Pin CPU intermittent operation selector Interrupt reset Internal reset Intermittent cycle selection CPU-clock control circuit 2 Pin high-impedance control CPU clock Stop and sleep signal Standby control circuit Stop signal Peripheral Machine clock Peripheral clock clock control Cancel waiting time circuit to stable oscillation Clock generator Selector for waiting time to stable oscillation Clock selector Clock SCLK divided by four 2 2 Sub clock generator circuit PLL multiplier circuit System clock generator circuit X0A Pin X1A Pin X0 Pin X1 Pin 116 SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) Clock Clock HCLK divided MCLK divided by 1024 by two Clock divided by two Clock divided by four Clock divided by four Clock divided by four Timebase timer HCLK : Oscillation clock MCLK : Main clock SCLK : Sub clock To watchdog timer Clock divided by two CHAPTER 5 CLOCKS ❍ System clock generator circuit This circuit generates an oscillation clock (HCLK) by using an oscillator connected to the highspeed oscillation pin. Also, an external clock can be input to it. ❍ Sub-clock generator circuit This circuit generates a sub-clock (SCLK) by using an oscillator connected to the low-speed oscillation pin. Also, an external clock can be input to it. ❍ PLL multiplier circuit This circuit multiplies an oscillation circuit by using PLL oscillation and supplies it to the CPU clock selector. ❍ Clock selector This circuit selects clocks from among the main clock, sub-clock, and four PLL clocks supplied to the CPU clock control circuit and peripheral clock control circuit. ❍ Clock selection register (CKSCR) This register changes between the oscillation clock and PLL clocks, selects the oscillation stabilization wait time, and selects the multiplication rate of the PLL clocks. ❍ Selector for the oscillation stabilization wait time This circuit selects the oscillation stabilization wait time of the oscillation clock when the stop mode is reset and during watchdog reset. Four types of the timebase timer output are selected. 117 CHAPTER 5 CLOCKS 5.3 Clock Selection Register (CKSCR) The clock selection register (CKSCR) switches among the main clock, sub-clock, and PLL clock, and it selects the oscillation stabilization wait time and PLL clock multiplication rate. ■ Configuration of clock selection register (CKSCR) Figure 5.3-1 "Configuration of clock selection register (CKSCR)" shows the configuration of the clock selection register (CKSCR). Table 5.3-1 "Functions of bits in clock selection register (CKSCR)" has explanations of the functions of bits in the clock selection register. Figure 5.3-1 Configuration of clock selection register (CKSCR) Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 0000A1H SCM MCM WS1 WS0 SCS MCS CS1 CS0 R R (LPMCR) bit0 Initial value 11111100B R/W R/W R/W R/W R/W R/W 0 0 Multiplication rate selection bit Values in ( ) are for 4 MHz oscillation clock 1 × HCLK ( 4 MHz) 0 1 1 0 2 × HCLK ( 8 MHz) 3 × HCLK (12 MHz) 1 1 4 × HCLK (16 MHz) CS1 CS0 PLL clock selection bit MCS 0 1 PLL clock selection Main clock selection Sub clock selection bit SCS 0 Sub clock selection 1 Main clock selection Oscillation stabilization wait time selection bits WS1 WS0 Values in ( ) are for 4 MHz oscillation clock 0 0 210/HCLK (about 256 µs) 213/HCLK (about 2.05 ms) 0 1 215/HCLK (about 8.19 ms) 1 0 1 1 217/HCLK (about 32.77 ms) * During a power-on reset, evaluation devices and FLASH devices become 218/HCLK (about 65.54 ms), and mask devices become 217/HCLK (about 32.77 ms). PLL clock display bit MCM 0 In use by PLL clock 1 In use by main clock or sub clock HCLK : Oscillation clock R/W : Read/write enabled R : Read only 0 : Not used : Initial value Sub clock display bit SCM 0 In use by sub clock 1 In use by main clock or PLL clock Note When reset, the machine clock selection (MCS) bit is initialized to the main clock selection. 118 CHAPTER 5 CLOCKS Table 5.3-1 Functions of bits in clock selection register (CKSCR) Bit name Function • Bit 15 SCM: Sub-clock display bit • • • Bit 14 MCM: PLL clock display bit • • This bit displays whether the main clock or sub-clock is selected as a machine clock. If the bit is "0", the sub-clock is selected. If "1", the main clock or PLL clock is selected. If SCS = 1 and SCM = 0, the mode is the waiting time for stable oscillation of the main clock. This bit displays whether the main clock or PLL clock is selected as a machine clock. If this bit is "0", the PLL clock is selected. If "1", the main clock or subclock is selected. If PLL clock selection bit (MCS) = 0 and MCM = 1, the mode is the waiting time for stable oscillation of the PLL clock. • Bit 13 Bit 12 WS1, WS0: Oscillation stabilization wait time selection bits Selects the waiting time for stable oscillation of oscillation clock in a change from the sub-clock mode to the main clock mode or from the sub-clock mode to the PLL clock mode if the stop mode is canceled. • Initialized to "11B" by all reset factors. Note: The specified value for the waiting time for stable oscillation must be suitable for the oscillator used. Refer to Section 4.2 "Reset Factors and Waiting time to Stable Oscillation", for more information. Specify "00B" only if the mode is the main clock mode. When the main clock is switched to PLL clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK. When sub-clock mode is switched to PLL clock mode or when PLL stop mode is returned to PLL clock mode, the oscillation stabilization wait time uses the specified values in the WS1 and WS0 bits. For PLL oscillation stabilization, at least 214 /HCLK is required. Accordingly, when subclock mode is switched to PLL clock mode, or when PLL clock mode is switched to PLL stop mode, set WS1 and WS0 bits to "10B" or "11B". • • • Bit 11 SCS: Sub-clock selection bit • • • • This bit specifies selection of the main clock or sub-clock as a machine clock. If this bit is "0", the sub-clock is selected. If "1", the main clock is selected. When this bit is rewritten from "1" to "0", the mode is switched to the sub-clock mode synchronizing the sub-clock (approx. 130µs.) Writing "1" when this bit is "0" generates a standby period for stable oscillation of the main clock. The timebase timer is automatically cleared. Use the sub-clock as an operation clock when the sub-clock is selected. (The machine clock changes to a frequency of 8 kHz during low-speed oscillation at 32 kHz) If both SCS and MCS are "0", SCS is assigned with priority, and the sub-clock is selected. Initialized to "1" by all reset factors. 119 CHAPTER 5 CLOCKS Table 5.3-1 Functions of bits in clock selection register (CKSCR) (Continued) Bit name Function • Bit 10 Bit 9 Bit 8 MCS: PLL clock selection bit This bit specifies selection of the main clock or PLL clock as a machine clock. • If this bit is "0", the PLL clock is selected. If "1", the main clock is selected. • Writing "0" when this bit is "1" generates a waiting time for stable oscillation of the PLL clock. The timebase timer is automatically cleared. The interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) is also cleared. • When the main clock is switched to PLL clock mode, the oscillation stabilization wait time is fixed at 214/HCLK. (The oscillation stabilization wait time is about 4.1 ms if the oscillation clock has a frequency of 4 MHz.) When sub-clock mode is switched to PLL clock, the oscillation stabilization wait time uses the specified values in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0). • When the main clock is selected, the operation clock is the oscillation clock divided by 2. (The operation clock is 2 MHz if the oscillation clock is 4 MHz.) • Initialized to "1" by all reset factors. Note: When writing "0" when the MCS bit is "1", write while the timebase timer interrupt is masked by using the interrupt request enable bit (TBIE) of the TBTC register or the interrupt level register (ILM). CS1, CS0: Multiplication rate selection bit • This bit selects the multiplication rate of the PLL clocks. • Selection is from four multiplication rates. • All reset factors initialize it to "00B". Note: Writing is disabled if the MCS bit or MCM bit is "0". Rewrite the CS1 and CS0 bits after setting the MCS bit to "1" (main clock mode). HCLK: Oscillation clock 120 CHAPTER 5 CLOCKS 5.4 Clock Modes The clock modes are the main clock, PLL clock, and sub-clock modes. ■ Main clock mode, PLL clock mode, and sub-clock mode ❍ Main clock mode The main clock mode uses a clock obtained by dividing the oscillation clock by two as the operation clock of the CPU and peripheral resources. This mode stops the PLL clock. ❍ PLL clock mode The PLL clock mode uses the PLL clock obtained as the operation clock of the CPU and peripheral functions. The multiplication rate of the PLL clock can be selected with the clock selection register (CKSCR). ❍ Sub-clock mode The main clock mode uses a sub-clock as the operation clock of the CPU and peripheral resources. This mode stops the main and PLL clocks. ■ Change of clock mode The clock mode changes to the main clock, PLL clock, or sub-clock mode according to the writing of the PLL clock selection bit (MCS) and sub-clock selection bit (SCS) in the CKSCR register. ❍ Change from the main clock mode to the PLL clock mode Changing the MCS bit in the CKSCR register from "1" to "0" in the main clock mode changes the main clock to the PLL clock after the end of the oscillation stabilization wait time of the PLL clock (214/HCLK). ❍ Change from the PLL clock mode to the main clock mode Changing the MCS bit in the CKSCR register from "0" to "1" in the PLL clock mode changes the PLL clock to the main clock adjusted to the timing where the edges of the PLL clock and main clock match (after 1 to 8 PLL clocks). ❍ Change from the main clock mode to the sub-clock mode Changing the SCS bit in the CKSCR register from "1" to "0" in the main clock mode changes the main clock to the sub-clock synchronizing the sub-clock (approx. 130µs.). ❍ Change from the sub-clock mode to the main clock mode Changing the SCS bit in the CKSCR register from "0" to "1" in the sub-clock mode changes the sub-clock to the main clock after end of the oscillation stabilization wait time of the main clock. Select the oscillation stabilization wait time by using selection bits (WS1, WS0) for the oscillation stabilization wait time of the CKSCR register. 121 CHAPTER 5 CLOCKS ❍ Change from the PLL clock mode to the sub-clock mode Changing the sub-clock selection bit (SCS) of the clock selection register (CKSCR) from "1" to "0" in the PLL clock mode changes the PLL clock to the sub-clock. ❍ Change from the sub-clock mode to the PLL clock mode Changing the SCS bit in the CKSCR register from "0" to "1" in the sub-clock mode changes the sub-clock to the PLL clock after the end of the oscillation stabilization wait time of the main clock. Select the oscillation stabilization wait time by using selection bits (WS1, WS0) for the oscillation stabilization wait time of the CKSCR register. Note: Changing the PLL clock selection bit (MCS) or SCS bit in the CKSCR register does not change the machine clock immediately. When operating a resource that depends on a machine clock, make sure that the intended machine clock change has completed by checking the PLL clock display bit (MCM) and sub-clock display bit (SCM) in the CKSCR register. Then operate the resource. If both of the SCS and MCS bits are "0", SCS is assigned with priority, and the sub-clock mode is set. When the clock mode is switched, do not switch to low power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched. ■ Selection of PLL clock multiplication rate If "00B" to "11B" are written to the CS1 and CS0 bits of the CKSCR register, four types of PLL multiplication rates (multiplication by 1 to 4) can be selected. ■ Machine clock The PLL clock, main clock, and sub-clock output by the PLL multiplier circuit are machine clocks, which are supplied to the CPU and peripheral functions. The main clock, PLL clock, and sub-clock can be selected by writing in the SCS or MCS bit of the CKSCR register. Figure 5.4-1 "State transition diagram of machine clock selection" is a state transition diagram of machine clock selection. 122 CHAPTER 5 CLOCKS Figure 5.4-1 State transition diagram of machine clock selection (8) Main MCS=1 MCM=1 (1) SCS=1 SCM=1 CS1,CS0=xx (10) Main→Sub MCS=1 MCM=1 (9) SCS=0 SCM=1 CS1,CS0=xx (16) (10) Sub→Main (11) (8) MCS=1 MCM=1 SCS=1 (8) (6) SCM=0 Main→PLLx (2) CS1,CS0=xx (12) Sub→PLL MCS=0 (3) (13) MCS=0 MCM=1 (14) MCM=1 (4) SCS=1 (15) SCS=1 (5) SCM=0 SCM=1 CS1,CS0=xx CS1,CS0=xx (7) (7) (7) (7) Sub MCS=1 MCM=1 SCS=0 SCM=0 CS1,CS0=xx PLL1→Main MCS=1 MCM=0 SCS=1 SCM=1 CS1,CS0=00 PLL multiplied by one MCS=0 MCM=0 (6) SCS=1 (8) SCM=1 CS1,CS0=00 PLL1→Sub MCS=1 MCM=0 SCS=0 SCM=1 CS1,CS=00 PLL2→Main MCS=1 MCM=0 SCS=1 SCM=1 CS1,CS0=01 PLL multiplied by two MCS=0 MCM=0 (6) SCS=1 (8) SCM=1 CS1,CS0=01 PLL2→Sub MCS=1 MCM=0 (17) SCS=0 SCM=1 CS1,CS0=01 PLL3→Main MCS=1 MCM=0 SCS=1 SCM=1 CS1,CS0=10 PLL multiplied by three MCS=0 MCM=0 (8) (6) SCS=1 SCM=1 CS1,CS0=10 PLL3→Sub MCS=1 (17) MCM=0 SCS=0 SCM=1 CS1,CS0=10 PLL4→Main MCS=1 MCM=0 SCS=1 SCM=1 CS1,CS0=11 PLL multiplied by four MCS=0 MCM=0 (8) (6) SCS=1 SCM=1 CS1,CS0=11 PLL4→Sub MCS=1 (17) MCM=0 SCS=0 SCM=1 CS1,CS0=11 (17) (1) MCS bit "0" write (2) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 00 (3) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 01 (4) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 10 123 CHAPTER 5 CLOCKS (5) Waiting for PLL clock oscillation stability is complete. &CS1, CS0 = 11 (6) MCS bit "1" write (includes watchdog reset) (7) Synchronization timing of PLL and main clocks (8) SCS bit "0" write (9) End of waiting time for sub-clock oscillation stability (maximum 214/SCLK) (10) SCS bit "1" write (11) Waiting for main clock oscillation stability is complete. (12) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 00 (13) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 01 (14) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 10 (15) Waiting for main clock oscillation stability is complete. &CS1, CS0 = 11 (16) SCS bit "1" write, MCS bit "0" write (17) Synchronization timing of PLL and sub-clocks MCS: PLL clock selection bit of clock selection register (CKSCR) MCM: PLL clock display bit of clock selection register (CKSCR) SCS: Sub-clock selection bit of clock selection register (CKSCR) SCM: Sub-clock display bit of clock selection register (CKSCR) CS1, CS0: Multiplication rate selection bit of clock selection register (CKSCR) Note: The initial value of the machine clocks is the main clock (MCS = 1, SCS = 1). If both of the SCS and MCS bits are "0", SCS is assigned with priority and the sub-clock is set. When sub-clock mode is switched to PLL clock, set "10B" or "11B" in the oscillation stabilization wait time selection bits (WS1, WS0) of the CKSCR register. 124 CHAPTER 5 CLOCKS 5.5 Oscillation Stabilization Wait Time When the power is turned on, when stop mode is released, or switching from the subclock to the main clock or from sub-clock to the PLL clock occurs, an oscillation stabilization wait time is required after oscillation begins because the oscillation clock is stopped. When switching from the main clock to the PLL clock or from the main clock to the sub-clock occurs, an oscillation stabilization wait time is required. ■ Oscillation stabilization wait time Ceramic and crystal oscillators generally require a waiting time ranging from several milliseconds to several ten milliseconds after the start of oscillation until oscillation stabilizes to a natural frequency (oscillation frequency). Therefore, disable CPU operation immediately after the start of oscillation, and supply a clock to the CPU when oscillation completely stabilizes following the elapse of the oscillation stabilization wait time. Specify a oscillation stabilization wait time suitable for the oscillator used because the time required for oscillation to stabilize varies depending on the type of oscillator (crystal, ceramic, or other material). The oscillation stabilization wait time can be selected by defining the clock selection register (CKSCR). When clock mode is switched from main clock to PLL clock, main clock to subclock, subclock to main clock, or subclock to PLL clock, the CPU runs in the clock mode set before switching for the oscillation stabilization wait time. After the oscillation stabilization wait time has elapsed, the CPU changes to the specified clock mode. Figure 5.5-1 "Operation immediately after start of oscillation" illustrates operation immediately after the start of oscillation. Figure 5.5-1 Operation immediately after start of oscillation Oscillator oscillation time oscillation stabilization wait time Switching to operation start or changing from PLL clock/sub clock X1 Start of Oscillation Stable Oscillation 125 CHAPTER 5 CLOCKS 5.6 Connecting Oscillator to External Clock Devices in the MB90470 series contain a system clock generator circuit and generate clocks using an externally connected oscillator. Also, an external clock can be input to it. ■ Connection of oscillator and external clock ❍ Example of connecting crystal or ceramic oscillator Connect a crystal oscillator or a ceramic oscillator as shown in the example in Figure 5.6-1 "Example of connecting crystal or ceramic oscillator". Figure 5.6-1 Example of connecting crystal or ceramic oscillator MB90470 series X0(X0A) X1(X1A) ❍ Example of connecting external clock Connect an external clock to pin X0 and set up pin X1 to be open as shown in the example in the Figure 5.6-2 "Example of connecting external clock". Figure 5.6-2 Example of connecting external clock MB90470 series X0(X0A) X1(X1A) Open 126 CHAPTER 6 LOW-POWER CONSUMPTION MODE This chapter explains the low-power consumption mode of the MB90470 series. 6.1 "Overview of Low-Power Consumption Mode" 6.2 "Block Diagram of Low-Power Control Circuit" 6.3 "Low-Power Consumption Mode Control Register (LPMCR)" 6.4 "CPU Intermittent Operation Mode" 6.5 "Standby Mode" 6.6 "State Transition Diagram" 6.7 "Pin State in Standby Mode, Hold, and Reset" 6.8 "Caution on Using Low-Power Consumption Mode" 127 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.1 Overview of Low-Power Consumption Mode The following CPU operation modes are available on the MB90470-series devices by selecting a suitable operation clock and by controlling clock operation. • Clock modes (PLL clock mode, main clock mode, and sub-clock mode) • CPU intermittent operation modes (PLL clock intermittent operation mode, main clock intermittent operation mode, and sub-clock intermittent operation mode) • Standby modes (sleep mode, timebase timer mode, stop mode, and watch mode) ■ CPU operation mode and current consumption Figure 6.1-1 "CPU operation mode and current consumption" illustrates the relationship between CPU operation mode and current consumption. Figure 6.1-1 CPU operation mode and current consumption Current consumption Several dozen mA CPU operation mode PLL clock mode Clock multiplied by four Clock multiplied by three Clock multiplied by two Clock multiplied by one Clock multiplied by four PLL clock intermittent operation mode Clock multiplied by three Clock multiplied by two Clock multiplied by one Main clock mode (1/2 clock mode) Main clock intermittent operation mode Several mA Sub clock mode Sub clock intermittent operation mode Standby mode Sleep mode Several mA Timebase timer mode Watch mode Stop mode Low-power consumption mode Note: This diagram is just an example, so its values may differ from actual current consumption. 128 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Clock modes ❍ PLL clock mode This mode operates the CPU and peripheral functions by using the PLL multiplication clock of the oscillation clock (HCLK). ❍ Main clock mode This mode operates the CPU and peripheral functions by using the clock of the oscillation clock (HCLK) divided by two. The PLL multiplier circuit stops its operation in the main clock mode. ❍ Sub-clock mode This mode operates the CPU and peripheral functions by using the sub-clock (SCLK). The main clock and the PLL multiplier circuit stop their operation in the sub-clock mode. Reference: Refer to Section 5.4 "Clock Modes", for more information on clock modes. ■ CPU intermittent operation mode The CPU intermittent operation mode operates the CPU intermittently while supplying a highspeed clock to the peripheral functions, thereby reducing power consumption. This mode inputs an intermittent clock only to the CPU while the CPU accesses registers, built-in memory, peripheral functions, and external devices. ■ Standby mode The standby mode reduces current consumption by stopping supply of a clock to the CPU by using the low-power control circuit (sleep mode), stopping supply of a clock to the CPU and peripheral functions (timebase timer mode), and stopping oscillation clocks (stop mode). ❍ PLL sleep mode The PLL sleep mode stops the CPU operation clock in the PLL clock mode. Devices other than the CPU are operated by the PLL clock. ❍ Main sleep mode The main sleep mode stops the CPU operation clock in the main clock mode. Devices other than the CPU are operated by the main clock. ❍ Sub sleep mode The sub sleep mode stops the CPU operation clock in the sub-clock mode. Devices other than the CPU are operated by the sub-clock. ❍ Timebase timer mode The timebase timer mode stops clocks and operations other than the oscillation clock, timebase timer, and watch timer. Functions other than the timebase timer and watch timer are stopped. ❍ Watch mode The watch mode operates only the watch timer. In this mode, only the sub-clock operates. The main clock and PLL multiplier circuit are stopped. 129 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ Stop mode The stop mode stops source oscillation, and all functions are stopped. Note: In the stop mode, the oscillation clock stops and data can be retained with the lowest consumption of power. When the clock mode is switched, do not switch to low power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched. 130 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.2 Block Diagram of Low-power Control Circuit The low-power control circuit is composed of the following seven blocks: • CPU intermittent operation selector • Standby control circuit • CPU-clock control circuit • Peripheral clock control circuit • Pin high-impedance control circuit • Internal reset generator circuit • Low-power consumption mode control register (LPMCR) ■ Block diagram of low-power control circuit Figure 6.2-1 "Block diagram of low-power control circuit" shows the low-power control circuit. Figure 6.2-1 Block diagram of low-power control circuit Low-power mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 Reserved Pin highimpedance control circuit RST Internal reset generator circuit Pin CPU intermittent operation selector Interrupt reset Stop signal Peripheral Peripheral clock clock control circuit Selector for waiting time to stable oscillation Clock selector Clock SCLK divided by four CPU clock Stop and sleep signal Standby control circuit Machine clock Cancel waiting time to stable oscillation Clock generator Internal reset Intermittent cycle selection CPU-clock control circuit 2 Pin high-impedance control 2 2 Sub clock generator circuit PLL multiplier circuit System clock generator circuit X0A Pin X1A Pin X0 Pin X1 Pin SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock selection register (CKSCR) Clock Clock HCLK divided MCLK divided by 1024 by two Clock divided by two Clock divided by four Clock divided by four Clock divided by four Clock divided by two Timebase timer HCLK : Oscillation clock MCLK : Main clock SCLK : Sub clock To watchdog timer 131 CHAPTER 6 LOW-POWER CONSUMPTION MODE ❍ CPU intermittent operation selector The CPU intermittent operation selector selects the number of pause clocks in the CPU intermittent operation mode. ❍ Standby control circuit The standby control circuit controls the CPU-clock control circuit and peripheral clock control circuit for resetting and changing to the low-power consumption mode. ❍ CPU-clock control circuit The CPU-clock control circuit controls clocks supplied to the CPU. ❍ Peripheral clock control circuit The peripheral clock control circuit controls clocks supplied to peripheral functions. ❍ Pin high-impedance control circuit The pin high-impedance control circuit changes the states of external pins to high impedance in the timebase timer mode and stop mode. In the stop mode, the circuit isolates pull-up resistance with pins for which the pull-up option is selected. ❍ Internal reset generator circuit The internal reset generator circuit generates an internal reset signal. ❍ Low-power consumption mode control register (LPMCR) The low-power consumption mode control register (LPMCR) performs functions, such as resetting and changing to the standby mode and defining the CPU intermittent operation function. 132 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.3 Low-Power Consumption Mode Control Register (LPMCR) The low-power consumption mode control register (LPMCR) performs functions including changing the current mode to the low-power consumption mode, canceling from the low-power consumption mode, and specifying the number of CPU-clock pause cycles in the CPU intermittent operation mode. ■ Low-power consumption mode control register (LPMCR) Figure 6.3-1 "Configuration of low-power consumption mode control register (LPMCR)" shows the configuration of the low-power consumption mode control register (LPMCR). Figure 6.3-1 Configuration of low-power consumption mode control register (LPMCR) Address 0000A0H bit15 bit8 bit7 bit6 bit5 STP SLP SPL RST TMD CG1 CG0 Reserved W W (CKSCR) R/W bit4 W bit3 bit2 R/W R/W bit1 bit0 00011000B R/W R/W Reserved Initial value Reserved bit Reading and writing has no effect on operation CG1 CG2 Bit for number of CPU-clock pause cycles 0 0 0 cycle (CPU clock = Resource clock) 0 1 8 cycles (CPU clock: Resource clock = 1: About 3 to 4) 1 0 16 cycles (CPU clock: Resource clock = 1: About 5 to 6) 1 1 32 cycles (CPU clock: Resource clock = 1: About 9 to 10) Clock mode or timebase timer mode bit TMD 0 Change to timebase timer mode 1 RST No change, no effect on others Internal reset signal generator bit 0 Generates an internal reset signal of 3 machine cycles 1 No change, no effect on others SPL 0 1 Pin state specification bit (in watch and timebase timer stop modes) Hold High impedance Sleep mode bit SLP 0 No change, no effect on others 1 R/W : Read/write enabled W : Write only : Initial value STP Change to sleep mode Stop mode bit 0 No change, no effect on others 1 Change to stop mode 133 CHAPTER 6 LOW-POWER CONSUMPTION MODE Table 6.3-1 Functions of bits in low-power consumption mode control register (LPMCR) Bit name Function STP: Stop mode bit • • • • • This bit instructs a change to the stop mode. Write "1" in this bit to change the mode to the stop mode. Writing "0" in this bit does not affect operation. Cleared to "0" by a reset or if an interrupt request is generated. "0" is always read when this bit is read. Bit 6 SLP: Sleep mode bit • • • • • This bit instructs a change to the sleep mode. Write "1" in this bit to change the mode to the sleep mode. Writing "0" in this bit does not affect operation. Cleared to "0" by a reset or if an interrupt request is generated. "0" is always read when this bit is read. Bit 5 SPL: Pin state specification bit (in watch, timebase timer, and stop modes) • • • This bit is effective only in the watch, timebase timer, and stop modes. If level of this bit is "0", the levels of external devices are retained. If level of this bit is "1", the levels of external devices are changed to high impedance. Initialized to "0" when reset. Bit 7 Bit 4 RST: Internal reset signal generator bit • • • • • • Bit 3 TMD: watch, timebase timer mode bit • • • • Bit 2 Bit 1 Bit 0 134 CG1, CG0: Bit for selecting number of CPU-clock pause cycles Reserved: Reserved bit • • • Write "0" in this bit to generate an internal reset signal of 3 machine cycles. Writing "1" in this bit does not affect operation. "1" is always read when this bit is read. This bit instructs a change to the watch or timebase timer mode. Write "0" in this bit in the main clock or PLL clock mode to change the mode to the timebase timer mode. Write "0" in this bit in the sub-clock mode to change the mode to the watch mode. Initialized to "1" by a reset or if an interrupt request is generated. "1" is always read when this bit is read. This bit specifies the number of pause cycles of the CPU clock in the CPU intermittent operation function. Stops supply of CPU clocks for the specified number of cycles for each instruction. Can be selected from four clock numbers. Initialized to "00B" by a reset. Reading and writing has no effect on operation. CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Accessing low-power consumption mode control register Writing in the low-power consumption mode control register executes a change to the lowpower consumption mode (stop, sleep, timebase timer and watch modes). Use the instructions listed in Table 6.3-2 "Instructions used for change to low-power consumption mode". The low-power consumption mode transition instruction in Table 6.3-2 "Instructions used for change to low-power consumption mode" must always be followed by an array of instructions highlighted by a line below. MOV LPMCR,#H'XX ; the low-power consumption mode transition instruction in table 6.3-2 NOP NOP JMP $+3 MOV A,#H'10 ; jump to next instruction ; any instruction The devices does not guarantee its operation after returning from the low-power consumption mode if you place an array of instructions other than the one enclosed in the dotted line.To access the low-power consumption mode control register (LPMCR) with C language, refer to "Å° Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Enter the Standby Mode" in the section 6.8 "Notes on Using the Low-Power Consumption Mode".When writing to the low-power consumption mode control register with a length of words, use even addresses only. Performing transition by using an odd address for writing may result in operation errors. Any instruction may be used to control functions not listed in Table 6.3-1 "Functions of bits in low-power consumption mode control register (LPMCR)". Table 6.3-2 Instructions used for change to low-power consumption mode MOV io,#imm8 MOV dir,#imm8 MOV eam,#imm8 MOV eam,Ri MOV io,A MOV dir,A MOV addr16,A MOV eam,A MOVW dir,#imm16 MOVW eam,#imm16 MOVW eam,RWi MOVW addr16,A MOVW eam,A MOV @RLi+disp8,A MOVW io,#imm16 MOVW io,A MOVW @RLi+disp8,A MOVPW addr24,A SETB io:bp SETB dir:bp SETB addr16,A CLRB io:bp CLRB dir:bp CLRB addr16,A ■ Priority of STP, SLP, and TMD bits Requests are processed with the following order of priority in the event that stop mode, sleep mode, and timebase timer mode requests are issued simultaneously. Stop-mode request > Timebase timer mode request > Sleep mode request 135 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.4 CPU Intermittent Operation Mode The CPU intermittent operation mode reduces power consumption by intermittently operating the CPU while operating external buses and peripheral functions at high speeds. ■ CPU intermittent operation mode To delay activation of the internal bus cycle, the CPU intermittent operation mode stops clocks supplied to the CPU for a preset period for each instruction during access to registers, embedded memory (ROM or RAM), I/O, peripheral functions, and external buses. Low-power processing is possible by lowering the CPU execution speed while high-speed peripheral clocks are supplied to peripheral functions. • Select the number of clock pause cycles supplied to the CPU using a bit for selecting the number of CPU-clock pause cycles (CG1 or CG0) of the low-power consumption mode control register (LPMCR). • Use the same clock as that for the peripheral functions when operating external buses. • The instruction execution time when the CPU intermittent operation mode is set can be calculated by dividing the number of instruction executions for accessing registers, embedded memory, embedded peripheral functions, and external buses by the number of pauses. The correction value thus obtained is added to the usual execution time. Figure 6.41 "Clocks in CPU intermittent operation mode" illustrates operation clocks in the CPU intermittent operation mode. Figure 6.4-1 Clocks in CPU intermittent operation mode Peripheral clock CPU clock Pause cycle One instruction execution cycle Internal bus activation 136 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5 Standby Mode The standby mode is divided into three modes, namely, the sleep (PLL sleep, main sleep, and sub sleep), clock, and stop modes. ■ Operational states in standby mode Table 6.5-1 "Operational states in standby mode" lists operational states in the standby mode. Table 6.5-1 Operational states in standby mode Standby mode Change Main clock condition PLL sleep mode SCS = 1 MCS = 0 SLP = 1 Main sleep mode SCS = 1 MCS = 1 SLP = 1 Sub sleep mode SCS = 0 SLP = 1 Timebase timer mode (SPL = 0) SCS = 1 TMD = 0 Sub-clock Machine clock CPU Peripheral Pin In operation In operation Cancellation method In operation Sleep mode Timebase timer mode In operation Stopped In operation Hold In operation Timebase timer mode (SPL = 1) SCS = 1 TMD = 0 Watch mode (SPL = 0) SCS = 0 TMD = 0 Watch mode (SPL = 1) SCS = 0 TMD = 0 Stop mode (SPL = 0) STP = 1 Stop mode (SPL = 1) STP = 1 Stopped Reset or interrupt Stopped (*1) Hi-Z Hold Stopped Watch mode Stopped (*2) Hi-Z Stopped Hold Stopped Stop mode Stopped Hi-Z *1: The timebase timer and watch timer are operating. *2: The watch timer is operating SPL: Pin-state specification bit of low-power consumption mode control register (LPMCR) SLP: Sleep mode bit of low-power consumption mode control register (LPMCR) STP: Stop mode bit of low-power consumption mode control register (LPMCR) TMD: Clock/timebase timer mode bit of low-power consumption mode control register (LPMCR) MCS: Machine clock selection bit of the clock selection register (CKSCR) SCS: Machine clock selection bit (Sub) of the clock selection register (CKSCR) Hi-Z: High impedance RST: External-reset pin 137 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.1 Sleep Mode The sleep mode stops CPU operation clocks, allowing devices other than the CPU to continue operation. When a change to the sleep mode is instructed by the low-power consumption mode control register (LPMCR), the PLL sleep mode is set if the PLL clock mode is set. The main sleep mode sets if the main clock mode is set. The sub sleep mode is set if the sub-clock mode is set. ■ Change to sleep mode Writing "1" in the sleep mode bit (SLP), "1" in the clock/timebase timer mode bit (TMD), and "0" in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR) changes the mode to the sleep mode. At this time, the PLL sleep mode is set if 0 is selected for the PLL clock selection bit (MCS) and 1 is selected for sub-clock selection bit (SCS) of the clock selection register (CKSCR); the main sleep mode is set if 1 is selected for MCS and SCS; and the sub sleep mode is set if 0 is selected for SCS. Note: If "1" is simultaneously written in the SLP and STP bits of the LPMCR register, the STP bit has the priority and the device is changed to the stop mode. If writing "1" in the SLP bit and writing "0" in the TMD bit of the low-power consumption mode control register are performed at the same time, the TMD bit has the priority and the device is changed to the timebase timer mode or watch mode. ❍ Data hold function This function in the sleep mode holds data of the internal RAM and dedicated registers such as an accumulator. ❍ Hold function The external bus hold function operates in the sleep mode. A hold state is set if a hold request is issued. ❍ Operation during interrupt request The sleep mode is not set if an interrupt request is issued while "1" is written in the SLP bit of the LPMCR register. The CPU executes a next instruction if an interrupt request is not accepted. If the CPU can accept an interrupt request, the request is branched immediately to an interrupt processing routine. ❍ Pin state In the sleep mode, the previous states are maintained except for pins used for bus input and output or for bus control. 138 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Canceling the sleep mode The low-power control circuit cancels the sleep mode by input of a reset or by an interrupt. ❍ Reset by a reset Reset initializes to the main clock mode. ❍ Reset by interrupt The sleep mode is canceled if an interrupt request whose interrupt level is higher than 7 is generated in a peripheral circuit, etc., in the sleep mode. After the sleep mode is canceled, the interrupt is processed with the same method as for ordinary interrupt processing. If interrupts are accepted by setting the I-flag of the condition code register (CCR), interrupt level mask register (ILM), or the interrupt control register (ICR), then the CPU executes the interrupts. If the interrupts cannot be accepted, the CPU continues processing beginning from an instruction next to the instruction specifying the sleep mode. Figure 6.5-1 "Canceling of sleep mode by interrupt" illustrates the canceling of the sleep mode by an interrupt. Figure 6.5-1 Canceling of sleep mode by interrupt Setting interrupt enable flag Interrupt from peripheral functions INT generates (IL<7) NO Sleep not canceled Sleep not canceled YES I=0 YES Next instruction Sleep canceled NO YES ILM < IL Executes next instruction NO Interrupt executed Note: When executing an interrupt, an instruction next to the instruction that specified the sleep mode is normally executed first before an interrupt request is processed. If a change to the sleep mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed. 139 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.2 Timebase Timer Mode The timebase timer mode stops operations except for source oscillation, timebase timer and watch timer. All functions except the timebase timer and watch timer are stopped. ■ Change to timebase timer mode To change the mode to the timebase timer mode, write "0" in clock/timebase timer mode bit (TMD) of the low-power consumption mode control register (LPMCR) in the PLL clock mode or the main clock mode (sub-clock display bit (SCM) = 1) of the clock selection register (CKSCR). ❍ Data hold function This function in the timebase timer mode holds data of the internal RAM and dedicated registers such as an accumulator. ❍ Hold function In the timebase timer mode, the external bus hold function is stopped and hold requests cannot be accepted even if they are input. If a hold request is input during a change to the timebase timer mode, the level of the HAK signal may not change to "L" while the bus is set to the highimpedance state. ❍ Operation during interrupt request The timebase timer mode is not set if an interrupt request is issued while "0" is written to the TMD bit of the low-power consumption mode control register (LPMCR). ❍ Pin state Pin state specification bit (SPL) of the LPMCR register can control whether to maintain the state of an external pin in the timebase timer mode in the previous state or in the high-impedance state. ■ Canceling the timebase timer mode The low-power control circuit cancels the timebase timer mode by input of a reset or by an interrupt. ❍ Reset by external reset External reset initializes to the main clock mode. ❍ Reset by interrupt The timebase timer mode is canceled by the low-power control circuit if an interrupt request whose interrupt level is higher than 7 (other than IL2, IL1, and IL0-"111B" of the interrupt control register (ICR)) is generated in a peripheral circuit, etc., in the timebase timer mode. After the timebase timer mode is canceled, interrupts are processed with the same method as for ordinary interrupt processing. If interrupts are accepted by setting the I-flag of the condition code register (CCR), interrupt level mask register (ILM), or the interrupt control register (ICR), then the CPU executes the interrupts. If an interrupt cannot be accepted, the CPU continues processing beginning from an instruction that was processed before the timebase timer mode was set. 140 CHAPTER 6 LOW-POWER CONSUMPTION MODE Note: When executing an interrupt, an instruction next to the instruction specifying the timebase timer mode is normally executed first before an interrupt request is processed. If a change to the timebase timer mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed. 141 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.3 Watch Mode The watch mode stops operations other than those of the sub-clock and watch timer. Almost all functions on the chip are stopped. ■ Change to watch mode To change the mode to the watch mode, write "0" in watch/timebase timer mode bit (TMD) of the low-power consumption mode control register (LPMCR) in the sub-clock mode (sub-clock display bit (SCS) = 0) of the clock selection register (CKSCR). ❍ Data hold function This function in the watch mode holds data of the internal RAM and dedicated registers such as an accumulator. ❍ Hold function In the watch mode, the external bus hold function is stopped and hold requests cannot be accepted even if they are input. If a hold request is input during a change to the watch mode, the level of the HAK signal may not change to "L" while the bus is set to the high-impedance state. ❍ Operation during interrupt request The watch mode is not set if an interrupt request is issued while "0" is set in the TMD bit of the LPMCR register. ❍ Pin state setting Pin state specification bit (SPL) of the LPMCR register can control whether to maintain the state of an external pin in the watch mode in the previous state or in the high-impedance state. ■ Canceling the watch mode The low-power control circuit cancels the watch mode by input of a reset or by an interrupt. ❍ Reset by a reset When the watch mode is canceled by a reset factor, the watch mode is canceled first, and a reset state for standing by for stable oscillation is set. The sequence for resetting is executed after the end of the oscillation stabilization wait time. ❍ Reset by interrupt The watch mode is canceled by the low-power control circuit if an interrupt request whose interrupt level is higher than 7 (other than IL2, IL1, and IL0-"111B" of the interrupt control register (ICR)) is generated in a peripheral circuit, etc., in the watch mode. The mode immediately changes to the sub-clock mode. After the change to the sub-clock mode, interrupts are processed with the same method as for ordinary interrupt processing. If interrupts are accepted by setting the I-flag of the condition code register (CCR), interrupt level mask register (ILM), or the interrupt control register (ICR), then the CPU executes the interrupts. If an interrupt cannot be accepted, the CPU continues processing beginning from an instruction next to the instruction that was processed before the watch mode was set. 142 CHAPTER 6 LOW-POWER CONSUMPTION MODE Note: When executing an interrupt, an instruction next to the instruction specifying the watch mode is normally executed first before an interrupt request is processed. If a change to the watch mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed. Figure 6.5-2 "Cancel operation of watch mode (external reset)" illustrates the cancel operation of the watch mode. Figure 6.5-2 Cancel operation of watch mode (external reset) RST pin Watch mode Oscillation stabilization wait PLL clock Sub clock Not operating Oscillation Main clock During oscillation Not operating Oscillating CPU clock Not operating CPU operation Not operating Main clock Processing Sequence for resetting Reset cancel Watch mode cancel 143 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.5.4 Stop Mode The stop mode stops source oscillation and stops all functions, thereby enabling retention of data with the lowest consumption of power. ■ Change to stop mode Write "1" in the stop mode bit (STP) of the low-power consumption mode control register (LPMCR) to change the mode to the stop mode. ❍ Data hold function This function in the stop mode holds data of the internal RAM and dedicated registers such as an accumulator. ❍ Hold function In the stop mode, the external bus hold function is stopped and hold requests cannot be accepted even if they are input. If a hold request is input during a change to the stop mode, the level of the HAK signal may not change to "L" while the bus is set to the high-impedance state. ❍ Operation during interrupt request The stop mode is not set if an interrupt request is issued while "1" is set in the STP bit of the LPMCR register. ❍ Pin state setting Pin state specification bit (SPL) of the LPMCR register can specify whether to maintain the state of an external pin in the stop mode in the previous state or in the high-impedance state. ■ Canceling the stop mode The low-power consumption control circuit releases the stop mode when a reset is input or an interrupt occurs. Because the oscillation clock (HCLK) and sub-clock (SCLK) are halted, the stop mode is released after the oscillation stabilization wait interval of the main clock or subclock. ❍ Reset by a reset When the stop mode is canceled by a reset factor, the stop mode is canceled first and the reset state standing by for stable oscillation is set. The sequence for resetting is executed after the end of the oscillation stabilization wait time. ❍ Reset by interrupt The stop mode is canceled by the low-power control circuit if an interrupt request whose interrupt level is higher than 7 (other than IL2, IL1, and IL0-"111B" of the interrupt control register (ICR)) is generated in a peripheral circuit, etc., in the stop mode. After the stop mode is canceled, interrupts are processed with the same method as for ordinary interrupt processing, following the elapse of the oscillation stabilization wait time of the main clock specified by the selection bits (WS1, WS0) for the oscillation stabilization wait time of the clock selection register (CKSCR). If the interrupts are accepted by setting the I-flag of the condition code register (CCR), interrupt level mask register (ILM) or the interrupt control register (ICR), the CPU executes interrupts. If an interrupt cannot be accepted, the CPU continues processing beginning 144 CHAPTER 6 LOW-POWER CONSUMPTION MODE from an instruction next to the instruction that was processed before the stop mode was set. Note: • When executing an interrupt, an instruction next to the instruction that specified the Stop mode is normally executed first before an interrupt request is processed. If a change to the stop mode occurs at the same time as an external bus hold request is received, an interrupt may be executed first before the next instruction is executed. • In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". Figure 6.5-3 "Cancel operation of stop mode (external reset)" shows the cancel operation of the stop mode. Figure 6.5-3 Cancel operation of stop mode (external reset) RST pin Stop mode Oscillation stabilization wait PLL clock CPU clock CPU operation Oscillation Main clock During oscillation Not operating Main clock Not operating Processing Sequence for resetting Reset cancel Stop-mode cancel 145 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.6 State Transition Diagram This section explains the transition of operational states for the MB90470 series and describes the transition conditions. ■ State transition diagram Figure 6.6-1 "State transition and transition conditions" illustrates the transition of operational states for the MB90470 series and the transition conditions. Figure 6.6-1 State transition and transition conditions External reset, watchdog timer reset, software reset Power on Reset Power-on reset SCS=0 End of oscillation stabilization wait SCS=1 Main clock mode SLP=1 MCS=0 PLL clock mode MCS=1 SLP=1 Interrupt Main sleep mode TMD=0 Interrupt TMD=0 Interrupt STP=1 End of oscillation stabilization wait Oscillation stabilization wait of main clock 146 Interrupt Sub-clock mode SLP=1 TMD=0 Interrupt Watch mode STP=1 PLL stop mode Interrupt Interrupt Sub sleep mode Timebase timer mode Main stop mode TMD=0 SCS=1 Interrupt PLL sleep mode Timebase timer mode STP=1 SCS=0 Sub stop mode End of oscillation Interrupt stabilization wait Oscillation stabilization wait of main clock End of oscillation stabilization wait Oscillation stabilization wait of sub-clock CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Operational state in low-power consumption mode Table 6.6-1 "Operational states in low-power consumption mode" lists operational states in the low-power consumption mode. Table 6.6-1 Operational states in low-power consumption mode Operational state Main clock Sub-clock PLL clock PLL CPU Peripheral Clock Timebase timer Operating Operating Not operating Not operating Operating Operating Operating Operating Not operating Not operating Operating Operating Clock source Operating Operating PLL sleep Operating Operating Operating PLL stop Not operating Not operating Not operating Standby for stable oscillation of PLL clock Operating Operating Operating Timebase timer (*1) Not operating Main Not operating Operating PLL clock Operating Operating Main sleep Operating Operating Not operating Not operating Operating Operating Timebase timer (*2) Main stop Standby for stable oscillation of main clock Not operating Sub-clock Not operating Not operating Main clock Operating Operating Operating Sub sleep Operating Clock Sub-clock stop Not operating Standby for stable oscillation of sub-clock Power-on reset Not operating Not operating Not operating Not operating Reset Operating Sub-clock Operating Main clock Not operating Operating Operating Not operating Operating Not operating Not operating Not operating Operating Operating *1: In PLL clock mode *2: In main clock mode 147 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.7 Pin State in Standby Mode, Hold, and Reset The states of the pins in the standby mode and in the hold and reset states are described for each memory access mode. ■ Pin state in single chip mode Table 6.7-1 "Pin states in single chip mode" lists the pin states in the single-chip mode. Table 6.7-1 Pin states in single chip mode When stopped Pin name In sleep state In hold state SPL = 0 SPL = 1 Input cutoff/ Maintains the previous state (*2, *3) Input cutoff/ Maintains the previous state (*3) When reset P07 to P00 P17 to P10 P27 to P20 P37 to P30 P47 to P40 P57 to P50 Maintains the previous state (*2) P67 to P60 This state does not exist Input disabled/ Output Hi-Z P77 to P70 P97 to P90 PA3 to PA0 P87 to P80 Input enabled (*1) Input enabled (*1) Input disabled *1: Same as in other ports when used in the output state. "Input enabled" means that input functions are ready and require pull up/pull down or external input. *2: The state output immediately before this mode was set is output as is. If it is input, input is disabled. "Input disabled" means that operations of input gates located very close to the pins are enabled, but pin states cannot be accepted in internal operations because internal circuits are not operating. *3: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. 148 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode Table 6.7-2 "Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode" summarizes pin states in the external bus 16-bit data bus mode and multiplex 16-bit external bus mode. Table 6.7-2 Pin states in external bus 16-bit data bus mode and multiplex 16-bit external bus mode When stopped Pin name In sleep state SPL = 0 P07 to P00 (AD07 to AD00) In hold state When reset SPL = 1 Internal ROM access immediately after reset cancellation Internal ROM access after external ROM access Output Hi-Z/Input Output Hi-Z/Input enabled enabled Input disabled/ Output Hi-Z Input cutoff/ Output Hi-Z Input disabled/ Output Hi-Z Input disabled/ Output Hi-Z P27 to P20 (A23 to A16) Output state (*1, *4) Output state (*1, *4) Input disabled/ Output Hi-Z (*4) Output state (*1) Output state (*1) P57 (CLK) Input disabled/ Output enabled (*2, *4) Input disabled/ Output state (*1, *4) Input disabled/ Output enabled (*2, *4) Input disabled/ Output enabled (*2) CLK output CLK output Maintains the previous state (*5) Input cutoff/ Maintains the previous state (*5, *6) Input disabled/ Output Hi-Z Output Hi-Z/Input Output Hi-Z/Input enabled enabled "H" output "H" output "H" output Output enabled (*2) "L" output "L" output Output Hi-Z/Input Output Hi-Z/Input enabled enabled P17 to P10 (AD15 to AD08) P56 (RDY) P55 (HAK) Maintains the previous address Input disabled (*4) "L" output P54 (HRQ) "I" input P53 (WRH) "H" output (*4) "H" output (*4) Input cutoff/ Output Hi-Z (*6) P52 (WRL) P51 (RD) "H" output "H" output P50 (ALE) "L" output "L" output Maintains the previous state (*5) Input cutoff/ Maintains the previous state (*5) Input disabled/ Output Hi-Z (*4) Input disabled/ Output Hi-Z P37 to P30 P47 to P40 P67 to P60 P77 to P70 P97 to P91 Input disabled/ Output Hi-Z Maintains the previous state (*5) PA3 to PA0 P90 (CS0) P87 to P80 "H" output Input enabled (*3) Input enabled (*3) Input enabled (*3) Input disabled *1: "Output state" means that the pin-drive transistors are set in a drive-enabled state, but internal circuits are stopped so that a fixed value, "H" or "L", is output. When internal peripheral circuits are in operation and output functions are used, output varies except when reset. Output does not vary during a reset. *2: "Output enabled" means that the pin-drive transistors are set in a drive state and that internal circuit operations are enabled. Operational states therefore are conveyed on the pins. *3: Same as in other ports when used in the output state. "Input enabled" means that input functions are ready and require pull up/pull down or external input. *4: The previous values are retained if used as an output port. *5: The state output immediately before this mode was set is output as is. If it is input, input is disabled. "Input disabled" means that operations of input gates located very close to the pins are enabled, but pin states cannot be accepted in internal operations because internal circuits are not operating. *6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. 149 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode Table 6.7-3 "Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode" lists pin states in the external bus 8-bit data bus mode and multiplex 6-bit external bus mode. Table 6.7-3 Pin states in external bus 8-bit data bus mode and multiplex 8-bit external bus mode When stopped Pin name In sleep state In hold state SPL = 0 Input disabled/ Output Hi-Z Input cutoff/ Output Hi-Z P17 to P10 (AD15 to AD08) Output state (*1) Output state (*1) P27 to P20 (A23 to A16) Output state (*1, *4) Output state (*1, *4) Input disabled/ Output Hi-Z (*4) P57 (CLK) Input disabled/ Output enabled (*2, *4) Input disabled/ Output state (*1, *4) Input disabled/ Output enabled (*2, *4) Input disabled/ Output Hi-Z Internal ROM access after external ROM access Input disabled/ Output Hi-Z Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled Output state (*1) Output state (*1) Maintains the previous address Input disabled/ Output enabled (*2) CLK output CLK output Input disabled/ Output Hi-Z Output Hi-Z/ Input enabled Output Hi-Z/ Input enable "H" output "H" output "H" output "L" output "L" output "L" output Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled Input disabled (*4) P56 (RDY) P54 (HRQ) Internal ROM access immediately after reset cancellation SPL = 1 P07 to P00 (AD07 to AD00) P55 (HAK) When reset Maintains the previous state (*5) "L" output Input cutoff/ Maintains the previous state (*5) "I" input Input cutoff/ Output Hi-Z (*6) P53 (WRH) P52 (WRL) "H" output (*5) "H" output (*5) P51 (RD) "H" output "H" output P50 (ALE) "L" output "L" output Maintains the previous state (*5) Input cutoff/ Maintains the previous state (*5) Maintains the previous state (*5) Input disabled/ Output Hi-Z (*4) Input disabled/ Output Hi-Z P37 to P30 P47 to P40 P67 to P60 P77 to P70 P97 to P91 Input disabled/ Output Hi-Z Maintains the previous state (*5) PA3 to PA0 P90 (CS0) P87 to P80 "H" output Input enabled (*3) Input enabled (*3) Input enabled (*3) Input disabled *1: "Output state" means that the pin-drive transistors are set in a drive-enabled state, but internal circuits are stopped so that a fixed value, "H" or "L", is output. When internal peripheral circuits are in operation and output functions are used, output varies except when reset. Output does not vary during a reset. *2: "Output enabled" means that the pin-drive transistors are set in a drive state and that internal circuit operations are enabled. Operational states therefore are conveyed on the pins. *3: Same as in other ports when used in the output state. "Input enabled" means that input functions are ready and require pull up/pull down or external input. *4: The previous values are retained if used as an output port. *5: The state output immediately before this mode was set is output as is. If it is input, input is disabled. "Input disabled" means that operations of input gates located very close to the pins are enabled, but pin states cannot be accepted in internal operations because internal circuits are not operating. *6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. 150 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode Table 6.7-4 "Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode" lists pin states in the external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode. Table 6.7-4 Pin states in external bus 16-bit data bus mode and non-multiplex 16-bit external bus mode When stopped Pin name In sleep state In hold state SPL = 0 P07 to P00 (D07 to D00) P17 to P10 (D15 to D08) P37 to P30 (A07 to A00) P47 to P40 (A15 to A08) Input disabled/ Output Hi-Z Internal ROM access immediately after reset cancellation Internal ROM access after external ROM access Input disabled/ Output Hi-Z Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled Output state (*1) Output state (*1) Maintains the previous address Input disabled/ Output enabled (*2) CLK output CLK output Input disabled/ Output Hi-Z Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled "H" output "H" output "H" output Output enabled (*2) "L" output "L" output Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled SPL = 1 Input cutoff/ Output Hi-Z Input disabled/ Output Hi-Z Output state (*1) Output state (*1) P27 to P20 (A23 to A16) Output state (*1, *4) Output state (*1, *4) Input disabled/ Output Hi-Z (*4) P57 (CLK) Input disabled/ Output enabled (*2, *4) Input disabled/ Output enabled (*1, *4) Input disabled/ Output enabled (*2, *4) Maintains the previous state (*5) Input cutoff/ Maintains the previous state (*5) P56 (RDY) P55 (HAK) When reset Input disabled (*4) Input cutoff/ Output Hi-Z (*6) P54 (HRQ) "L" output "I" input P53 (WRH) "H" output (*5) Input disabled/ Output Hi-Z (*4) "H" output (*5) P52 (WRL) P51 (RD) "H" output "H" output P50 (ALE) "L" output "L" output Maintains the previous state (*5) Input cutoff/ Maintains the previous state (*5) Input disabled/ Output Hi-Z P67 to P60 P77 to P70 P97 to P91 PA3 to PA0 Input disabled/ Output Hi-Z Maintains the previous state (*5) P90 (CS0) P87 to P80 "H" output Input enabled (*3) Input enabled (*3) Input enabled (*3) Input disabled *1: "Output state" means that the pin-drive transistors are set in a drive-enabled state, but internal circuits are stopped so that a fixed value, "H" or "L", is output. When internal peripheral circuits are in operation and output functions are used, output varies except when reset. Output does not vary during a reset. *2: "Output enabled" means that the pin-drive transistors are set in a drive state and that internal circuit operations are enabled. Operational states therefore are conveyed on the pins. *3: Same as in other ports when used in the output state. "Input enabled" means that input functions are ready and require pull up/pull down or external input. *4: The previous values are retained if used as an output port. *5: The state output immediately before this mode was set is output as is. If it is input, input is disabled. "Input disabled" means that operations of input gates located very close to the pins are enabled, but pin states cannot be accepted in internal operations because internal circuits are not operating. *6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. 151 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode Table 6.7-5 "Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode" summarizes pin states in the external bus 8-bit data bus mode and non-multiplex 6-bit external bus mode. Table 6.7-5 Pin states in external bus 8-bit data bus mode and non-multiplex 8-bit external bus mode When stopped Pin name In sleep state In hold state SPL = 0 P07 to P00 (D07 to D00) P37 to P30 (A07 to A00) P47 to P40 (A15 to A08) Input disabled/ Output Hi-Z Input cutoff/ Output Hi-Z Output state (*1) Output state (*1) Output state (*1, *4) Input disabled/ Output Hi-Z (*4) P57 (CLK) Input disabled/ Output enabled (*2, *4) Input disabled/ Output enabled (*1, *4) Input disabled/ Output enabled (*2, *4) Input disabled/ Output Hi-Z Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled Output state (*1) Output state (*1) Maintains the previous address Input disabled/ Output enabled (*2) CLK output CLK output Input disabled/ Output Hi-Z Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled "H" output "H" output "H" output Output enabled (*2) "L" output "L" output Output Hi-Z/ Input enabled Output Hi-Z/ Input enabled Input disabled (*4) P56 (RDY) Maintains the previous state (*5) Input cutoff/ Maintains the previous state (*5) P53 (WRH) P52 (WRL) "H" output (*4) "H" output (*4) P51 (RD) "H" output "H" output P50 (ALE) Internal ROM access after external ROM access Input disabled/ Output Hi-Z Output state (*1, *4) P54 (HRQ) Internal ROM access immediately after reset cancellation SPL = 1 P27 to P20 (A23 to A16) P55 (HAK) When reset "L" output "L" output Maintains the previous state (*5) Input cutoff/ Maintains the previous state (*5) "L" output Input cutoff/ Output Hi-Z (*6) "I" input Maintains the previous state (*5) Input disabled/ Output Hi-Z (*4) Input disabled/ Output Hi-Z P17 to P10 P67 to P60 P77 to P70 P97 to P91 Input disabled/ Output Hi-Z Maintains the previous state (*5) PA3 to PA0 P90 (CS0) P87 to P80 "H" output Input enabled (*3) Input enabled (*3) Input enabled (*3) Input disabled *1: "Output state" means that the pin-drive transistors are set in a drive-enabled state, but internal circuits are stopped so that a fixed value, "H" or "L", is output. When internal peripheral circuits are in operation and output functions are used, output varies except when reset. Output does not vary during a reset. *2: "Output enabled" means that the pin-drive transistors are set in a drive state and that internal circuit operations are enabled. Operational states therefore are conveyed on the pins. *3: Same as in other ports when used in the output state. "Input enabled" means that input functions are ready and require pull up/pull down or external input. *4: The previous values are retained if used as an output port. *5: The state output immediately before this mode was set is output as is. If it is input, input is disabled. "Input disabled" means that operations of input gates located very close to the pins are enabled, but pin states cannot be accepted in internal operations because internal circuits are not operating. *6: "Input cutoff" means that operations of input gates located very close to the pins are disabled. "Output Hi-Z" means that the pin-drive transistors are disabled and the pins are set to the high-impedance state. 152 CHAPTER 6 LOW-POWER CONSUMPTION MODE 6.8 Caution on Using Low-Power Consumption Mode When operating in the low-power consumption mode, exercise reasonable care concerning the following: • Change to the standby mode and interrupts • Cancellation of standby mode by interrupt • Oscillation stabilization wait time • Switching the clock mode • Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Enter the Standby Mode ■ Change to standby mode and interrupts When a peripheral function issues an interrupt request to the CPU, the setting of "1" to the stop mode bit (STP) and sleep mode bit (SLP) in the low-power consumption mode control register (LPMCR) and "0" to the clock/timebase timer mode bit (TMD) is ignored. A change to the appropriate standby mode is not executed. (Neither is a change to the standby mode executed after interrupt processing.) In this event, the acceptance of interrupt requests by the CPU if the interrupt level is higher than 7 is irrelevant. Even when the CPU is processing an interrupt, the interrupt request flag bit is cleared, and a change to the standby mode is possible unless there is another interrupt request. ■ Cancellation of standby mode by interrupt The standby mode is canceled if a peripheral function or other device issues an interrupt request whose interrupt level is higher than 7 in the sleep, timebase timer, or stop mode. This is irrelevant to whether or not the CPU accepts an interrupt. After the standby mode is canceled by an interrupt, branching to an interrupt processing routine is performed as in a normal interrupt operation if the priority of interrupt level setting bit (bits IL2, IL1, and IL0 of the ICR register) corresponding to an interrupt request is higher than the interrupt level mask register (ILM) and if interrupts are enabled (I = "1") by the I-flag of the condition code register (CCR). If an interrupt is not accepted, the standby mode is specified and operation is resumed beginning from an instruction next to the instruction specifying the standby mode. In the execution of interrupt processing, interrupt processing is normally started after execution of an instruction next to the instruction specifying the standby mode. However, depending on the conditions under which the mode is changed to the standby mode, interrupt processing may be started before the next instruction is executed. Note: Disabling of interrupts or other actions are required before setting the standby mode if branching to an interrupt processing routine is not performed immediately after a reset. 153 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Oscillation stabilization wait time ❍ Oscillation stabilization wait time of oscillation clock The oscillator for source oscillation is stopped in the stop mode, and a oscillation stabilization wait time must be provided. Specify the oscillation stabilization wait time selected with the selection bits (WS1 and WS0) for the oscillation stabilization wait time of the clock selection register (CKSCR). Note: Set "00B" in the selection bits (WS1 and WS0) for the oscillation stabilization wait time of the clock selection register (CKSCR) only in the main clock mode. ❍ Oscillation stabilization wait time of PLL clock In main clock mode, the PLL multiplication circuit stops. When changing to PLL clock mode, it is necessary to reserve the PLL clock oscillation stabilization wait time. The CPU runs in main clock mode till the PLL clock oscillation stabilization wait time has elapsed. When the main clock mode is switched to PLL clock mode, the PLL clock oscillation stabilization wait time is fixed at 214/HCLK (HCLK: oscillation clock). In sub-clock mode, the main clock and PLL multiplication circuit stop. When changing to PLL clock mode, it is necessary to reserve the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of the main clock and PLL clock oscillation stabilization wait times. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". In PLL stop mode, the main clock and PLL multiplication circuit stop. During recovery from PLL stop mode, it is necessary to allot the main clock oscillation stabilization wait time and PLL clock oscillation stabilization wait time. The oscillation stabilization wait times for the main clock and PLL clock are counted simultaneously according to the value specified in the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register. The oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register must be selected accordingly to account for the longer of main clock and PLL clock oscillation stabilization wait time. The PLL clock oscillation stabilization wait time, however, requires 214/HCLK or more. Set the oscillation stabilization wait time selection bits (CKSCR: WS1, WS0) in the clock selection register to "10B" or "11B". ■ Switching the clock mode When the clock mode is switched, do not switch to low power consumption mode and other clock mode before this switching is completed. Confirm the completion of clock mode switching by referring to the MCM and SCM bits of the clock selection register (CKSCR). If the mode is switched to another clock mode or low-power-consumption mode before completion of switching, the mode may not be switched. 154 CHAPTER 6 LOW-POWER CONSUMPTION MODE ■ Notes on Accessing the Low-Power Consumption Made Control Register (LPMCR) to Enter the Standby Mode ❍ To access the low-power consumption mode control register (LPMCR) with assembler language • To set the low-power consumption mode control register (LPMCR) to enter the standby mode, use the instruction listed in Table 6.3-2 "Instructions used for change to low-power consumption mode". • The low-power consumption mode transition instruction in Table 6.3-2 "Instructions used for change to low-power consumption mode" must always be followed by an array of instructions highlighted by a line below. MOV LPMCR,#H'XX ; the low-power consumption mode transition instruction in table 6.3-2 NOP NOP JMP $+3 ; jump to next instruction MOV A,#H'10 ; any instruction The devices does not guarantee its operation after returning from the low-power consumption mode if you place an array of instructions other than the one enclosed in the line. ❍ To access the low-power consumption mode (LPMCR) with C language To enter the standby mode using the low-power consumption mode control register (LPMCR), use one of the following methods (1) to (3) to access the register: (1) Specify the standby mode transition instruction as a function and insert two _wait_nop() built-in functions after that instruction. If any interrupt other than the interrupt to return from the standby mode can occur within the function, optimize the function during compilation to suppress the LINK and UNLINK instructions from occurring. Example: Watch mode or timebase timer mode transition function Void enter_watch(){ IO_LPMCR_byte = 0x10 /* Set LPMCR TMD bit to 0 */ _wait_nop(); _wait_nop(); } (2) Define the standby mode transition instruction using _asm statements and insert two NOP and JMP instructions after that instruction. Example: Transition to sleep mode _asm(" MOV I: _IO_LPMCR,#H'58); /* Set LPMCR SLP bit to 1 */ _asm(" NOP"); _asm(" NOP"); _asm(" JMP $+3"); /* Jump to next instruction */ 155 CHAPTER 6 LOW-POWER CONSUMPTION MODE (3) Define the standby mode transition instruction between #pragma asm and #pragma endasm and insert two NOP and JMP instructions after that instruction. Example: Transition to stop mode #pragma asm MOV I: _IO_LPMCR,#H'98 /* Set LPMCR STP bit to 1 */ NOP NOP JMP $+3 #pragma endasm 156 /* Jump to next instruction */ CHAPTER 7 MODE SETTING This chapter explains mode setting and external memory access. 7.1 "Mode Setting" 7.2 "Mode Pins (MD2 to MD0)" 7.3 "Mode Data " 7.4 "External Memory Access" 7.5 "Operation of Each Mode for Mode Setting" 157 CHAPTER 7 MODE SETTING 7.1 Mode Setting The F2MC-16LX has different modes in each access system and access area. Each mode is set according to a mode pin at the reset state and according to mode data obtained by mode-fetch. ■ Mode setting The F2MC-16LX has different modes in each access system and access area. In this module, they are categorized as shown in Figure 7.1-1 "Categories of modes". Figure 7.1-1 Categories of modes Operation modes RUN operation FLASH write mode Bus modes Single-chip mode Internal ROM external bus mode External ROM external bus mode Access modes External bus data length 8/15 bit Address data bus Non-multiplex bus mode Multiplex mode ■ Operation modes Operation modes are used to control the operating conditions of devices, and they are set by mode setting pins (MDx) and with the contents of the Mx bits in mode data. By selecting an operation mode, normal operation activation or flash serial programming can be performed. ■ Bus modes Bus modes are used to control the operation of internal ROMs and of external access functions, and they are specified by mode setting pins (MDx) and with the contents of the Mx bits in mode data. Mode setting pins (MDx) specify the reset vector as well as set the bus mode for reading mode data. The Mx bits in mode data specify the bus mode during normal operation. ■ Access modes Access modes are used to control the external data bus width, and they are set by mode setting pins (MDx) and with the contents of the Mx bits in mode data. Selection of an access mode specifies either an 8-bit length or 16-bit length for the external data bus. It also specifies either the non-multiplex mode or multiplex mode for the address data bus. 158 CHAPTER 7 MODE SETTING 7.2 Mode Pins (MD2 to MD0) Mode pins are three external pins (MD2 to MD0) that specify the reset vector and mode data fetching method. ■ Settings of mode pins (MD2 to MD0) Mode pins (MD2 to MD0) are used to select the source, either the external or internal data bus when reset vectors are read and stored, and to select the bus width when the external data bus is used. For a device with built-in FLASH ROM, the mode pins are also used to set the FLASH ROM write mode for writing built-in ROM program. Table 7.2-1 "Contents of mode pin settings" lists the contents of mode pin settings. Table 7.2-1 Contents of mode pin settings P81 P80 MD1 MD1 MD0 Mode name Reset vector access area External data bus width Remarks - - 0 0 0 External vector mode 0 External Multiplex mode Reset vector 8-bit bus width access - - 0 0 1 External vector mode 1 External - - 0 1 0 External vector mode 2 External Internal vector mode - - 0 1 1 - - 1 0 0 - - 1 0 1 1 0 1 1 0 - - 1 1 1 Internal Reset vector 16-bit bus width access Nonmultiplex mode Mode data Reset vector 8-bit bus width access Operation after reset sequence is controlled with mode data Setting is prohibited FLASH serial writing FLASH writer write mode - - - Note: MD2 to MD0: Specify 0=VSS or 1=VCC. For external vector mode 2, the data bus width also has a default value of 8 bits. To specify 16 bits as the data bus width, specify mode data for the non-multiplex external data bus 16-bit mode, and then the IOBS and LMBS areas are set up for 16-bit size access. To set up the HMBS area for 16-bit size access, change the HMBS setting. 159 CHAPTER 7 MODE SETTING 7.3 Mode Data Mode data stored at address "FFFFDFH" in memory specifies the operation immediately after the reset sequence. Mode data is read and stored in the CPU automatically by mode fetching. ■ Mode data During the reset sequence, mode data at address "FFFFDFH" is sent to the mode register in the CPU core. The CPU uses this mode data to set the memory access mode. The contents of the mode register can be changed only by the reset sequence. Furthermore, mode data settings become valid only after the reset sequence. The configuration of mode data is shown in the figure below. Mode data 7 6 5 4 3 2 1 0 M1 M0 0 S1 S0 0 0 0 Bus mode setting bits Setting bits of different modes Function expansion bits (reserved area) ■ Setting bits of different modes (S1, S0) Bits S1 and S0 specify the bus mode and access mode that is set after completion of the reset sequence. Table 7.3-1 "Contents of bit S1 and S0 settings" lists the contents of the settings of bits S1 and S0. Table 7.3-1 Contents of bit S1 and S0 settings S1 S2 Functions 0 0 External data bus 8-bit mode 0 1 External data bus 16-bit mode 1 0 External data bus 8-bit mode 1 1 External data bus 16-bit mode Address data bus multiplex Address data bus non-multiplex 160 CHAPTER 7 MODE SETTING ■ Bus mode setting bits (M1, M0) Bits M1 and M0 specify the operation mode that is set after completion of the reset sequence. Table 7.3-2 "Contents of bit M1 and M0 settings" lists the contents of the settings of bits M1 and M0. Table 7.3-2 Contents of bit M1 and M0 settings M1 M0 Functions 0 0 Single-chip mode 0 1 Internal ROM and external bus mode 1 0 External ROM and external bus mode 1 1 (Setting is prohibited) Figure 7.3-1 "Relationship between access areas and physical addresses" shows the correspondence between access areas and physical addresses. Figure 7.3-1 Relationship between access areas and physical addresses Single chip Internal ROM external bus ROM area ROM area External ROM external bus FFFFFFH Address #1 FC0000H 010000H ROM area, image of FF bank ROM area, image of FF bank RAM Register RAM Register Address #2 Address #3 RAM Register 000100H 0000D0H Peripheral Peripheral Peripheral 000000H Internal access External access No access Note: "Address #X" is determined based on individual models. See Appendix A "Memory Map", for details. 161 CHAPTER 7 MODE SETTING ■ Relationship between mode pins and mode data (an example showing recommended relationship) Table 7.3-3 "Relationship between mode pins and mode data" shows the relationship between mode pins and mode data. Table 7.3-3 Relationship between mode pins and mode data Mode MD2 MD1 MD0 M1 M0 S1 S0 Single chip 0 1 1 0 0 X X Internal ROM external bus mode, 8-bit (address data multiplex) 0 1 1 0 1 0 0 Internal ROM external bus mode, 16-bit (address data multiplex) 0 1 1 0 1 0 1 Internal ROM external bus mode, 8-bit (address data non-multiplex) 0 1 1 0 1 1 0 Internal ROM external bus mode, 16-bit (address data non-multiplex) 0 1 1 0 1 1 1 External ROM external bus mode, 16-bit, bus vector with 16-bit width (address data multiplex) 0 0 1 1 0 0 1 External ROM external bus mode, 8-bit (address data multiplex) 0 0 0 1 0 0 0 External ROM external bus mode, 8-bit (address data non-multiplex) 0 1 0 1 0 1 0 Note: If the output of high-order addresses of A23 to A16 is suppressed, the maximum capacity of accessible memory is 64 KB. 162 CHAPTER 7 MODE SETTING ■ Operation of external pins in each mode Table 7.3-4 "Operation of external pins in each mode" shows the operation of each external pin in the non-multiplex mode and multiplex mode. Table 7.3-4 Operation of external pins in each mode Functions Non-multiplex mode Multiplex mode External address control External address control Permitted (address) Prohibited (port) External bus extension External bus extension 8-bit 16-bit P07 to P00 /D07 to D00 /AD07 to AD00 P17 to P10 /D15 to D08 /AD15 to AD08 8-bit 16-bit Permitted (address) Prohibited (port) External bus extension External bus extension 8-bit 16-bit D07 to D00 Port D15 to D08 8-bit 16-bit AD07 to AD00 Port D15 to D08 A15 to A08 AD15 to AD08 A15 to A08 AD15 to AD08 P27 to P20 A23 to A16 Port A23 to A16 P37 to P30 A07 to A00 A07 to A00 P47 to P40 A15 to A08 A15 to A08 Port Port ALE ALE ALE RD RD RD P52/WRL WRL WRL P53/WRH • • • • Port WRH Port WRH Port WRH Port P54/HRQ HRQ HRQ P55/HAK HAK HAK P56/RDY RDY RDY P57/CLK CLK CLK WRH In the single-chip mode, all addresses can be used as ports. High-order addresses, WRL, WRH, HAK, HRQ, RDY, and CLK can be used as ports depending on the selected function. In the multiplex mode, high-order addresses ranging from A23 to A20 can be used as ports or as the range of PPG3 to PPG0. In the non-multiplex mode, the up/down-counter, SCI2, and µPG cannot be used. They function as addresses. 163 CHAPTER 7 MODE SETTING 7.4 External Memory Access This section contains block diagrams about external memory access, the configuration and functions of registers, and operation of external memory access. ■ I/O signal pins for external memory access For accessing external memory and peripheral devices, the F2MC-16LX supplies the following address, data, and control signals: • CLK (P57): Outputs the machine cycle clock (KBP) • RDY (P56): External ready input pin • HAK (P55): Hold acknowledge output pin • WRH (P53): Write signal for the high-order 8 bits on the data bus • WRL (P52): Write signal for the low-order 8 bits on the data bus • RD (P51): Read signal • ALE (P50): Address latch enable signal (effective in the multiplex mode) ■ Block diagram Figure 7.4-1 "Block diagram of external bus pin control circuit" is a block diagram of the external bus pin control circuit. Figure 7.4-1 Block diagram of external bus pin control circuit P0 Internal address bus P1 P2 P0 data P0 direction Internal data bus Data control Address control Access control 164 Access control P3 P4 P5 P5 P0 CHAPTER 7 MODE SETTING ■ List of registers Figure 7.4-2 "Registers in external bus pin control circuit" shows a list of registers in the external bus pin control circuit. Figure 7.4-2 Registers in external bus pin control circuit 15 14 13 12 Bit 0000A5H IOR1 IOR0 HMR1 HMR0 (W) (W) (W) (W) (0) (0) (1) (1) Bit 7 0000A6H E23 15 0000A7H CKE 10 9 8 Automatic ready function LNR1 LMR0 selection register (ARSR) (-) (-) (-) (-) (W) (W) (0) (0) 6 5 4 3 2 1 0 E22 E21 E20 E19 E18 E17 E16 (W) (W) (W) (W) (0) (0) (0) (0) Bit 11 14 RYE 13 12 (W) (W) (W) (W) (0) (0) (0) (0) 11 10 9 8 HDE IOBS HMBS WRE LMBS (W) (W) (W) (W) (0) (0) (0) (0) (W) (W) (W) ( ) (1) (0) (-) (-) Read/write Initial value External address output control (HACR) Read/write Initial value Bus control signal selection register (EPCR) Read/write Initial value 165 CHAPTER 7 MODE SETTING 7.4.1 Automatic ready function selection register (ARSR) This section shows the configuration and explains the function of the automatic ready function selection register (ARSR) ■ Automatic ready function selection register (ARSR) The bit configuration of the automatic ready function selection register (ARSR) is shown in the figure below. 15 14 13 12 11 10 Automatic ready function LNR1 LMR0 selection register (-) (-) (-) (-) (W) (W) (0) (0) 0000A5H IOR1 IOR0 HMR1 HMR0 (W) (W) (W) (W) (0) (0) (1) (1) 9 8 Read/write Initial value Functions of each bit in the automatic ready function selection register are described below. [Bits 15, 14] IOR1, IOR0 These bits are used to select the automatic wait function for external access to areas in a range of 0000D0H to 0000FFH. Contents of settings are listed below. IOR1 IOR0 Setting 0 0 Automatic wait prohibited [Initial value] 0 1 Automatic wait in 1 machine cycle during external access 1 0 Automatic wait in 2 machine cycle during external access 1 1 Automatic wait in 3 machine cycle during external access [Bits 13, 12] HMR1, HMR0 These bits are used to select the automatic wait function for external access to areas in a range of 800000H to FFFFFFH. Contents of settings are listed below. 166 HMR1 HMR0 Setting 0 0 Automatic wait prohibited 0 1 Automatic wait in 1 machine cycle during external access 1 0 Automatic wait in 2 machine cycle during external access 1 1 Automatic wait in 3 machine cycle during external access [Initial value] CHAPTER 7 MODE SETTING [Bits 9, 8] LMR1, LMR0 These bits are used to select the automatic wait function for external access to areas in a range of 002000H to 7FFFFFH. Contents of settings are listed below. LMR1 LMR0 Setting 0 0 Automatic wait prohibited [Initial value] 0 1 Automatic wait in 1 machine cycle during external access 1 0 Automatic wait in 2 machine cycle during external access 1 1 Automatic wait in 3 machine cycle during external access 167 CHAPTER 7 MODE SETTING 7.4.2 External address output control register (HACR) This section shows the configuration and explains the function of the external address output control register. ■ External address output control register (HACR) The bit configuration of the external address output control register is shown in the figure below. 7 0000A6H E23 6 5 4 3 2 1 0 E22 E21 E20 E19 E18 E17 E16 (W) (W) (W) (W) (0) (0) (0) (0) (W) (W) (W) (W) (0) (0) (0) (0) External address output control Read/write Initial value The external address output control register controls external output of addresses (A23 to A16). One bit corresponds to each of addresses A23 to A16 and controls each address output pin as follows. 0 The corresponding pin is for address output (AXX). [Initial value] 1 The corresponding pin is as an I/O port (PXX). This register cannot be accessed while the device is set to the single-chip mode. In this event, all ports function as I/O ports regardless of the values in this register. All bits of this register are dedicated for writing, and the readout value is "1". Furthermore, if addresses are expected to be output with address output selected, specify the value of DDR to "0". Note: When using PPG, set it to "1" (setting for an I/O port). Be careful when using it as an I/O port in the internal ROM external bus mode because the address function (A23 to A16) is assumed to be in effect after mode data is read, and address output remain in effect until it is set to an I/O port by HACR. 168 CHAPTER 7 MODE SETTING 7.4.3 Bus control signal selection register (EPCR) This section shows the configuration and explains the function of the bus control signal selection register. ■ Bus control signal selection register (EPCR) The bit configuration of the bus control signal selection register is shown in the figure below. 15 0000A7H CKE 14 RYE 13 12 11 10 9 8 HDE IOBS HMBS WRE LMBS (W) (W) (W) (W) (0) (0) (0) (0) (W) (W) (W) ( ) (1) (0) (-) (-) Bus control signal selection register Read/write Initial value This register cannot be accessed while the device is set to the single-chip mode. In the singlechip mode, all ports function as I/O ports regardless of the values in this register. All bits of this register are dedicated for writing, and the readout value is "1". Functions of each bit in the bus control signal selection register are described below. [Bit 15] CKE This bit controls the external clock (CLK) output. 0 I/O port (P57) operation (clock prohibited) 1 Clock signal (CLK) output permitted [Initial value] [Bit 14] RYE This bit controls the external ready (RDY) input. 0 I/O port (P56) operation (external RDY input prohibited) [Initial value] 1 External ready (RDY) input permitted [Bit 13] HDE This bit specifies I/O enable for hold-related pins. Hold request input (HRQ) and hold acknowledge output (HAK) are controlled with this bit setting. 0 I/O port (P55, 54) operation (hold function I/O prohibited) [Initial value] 1 Hold request (HRQ)/hold acknowledge (HAK) output permitted 169 CHAPTER 7 MODE SETTING [Bit 12] IOBS This bit specifies the bus width for accessing external buses corresponding to areas in a range of 0000D0H to 0000FFH, in the external data bus 16-bit mode. 0 16-bit bus width access [Initial value] 1 8-bit bus width access [Bit 11] HMBS This bit specifies the bus width for accessing external buses corresponding to areas in a range of 800000H to FFFFFFH, in the external data bus 16-bit mode. 0 16-bit bus width access [Default value in external vector mode 1] 1 8-bit bus width access [Default value in external vector modes 0 and 2] [Bit 10] WRE This bit controls the output of external write signals (both the WRH and WRL pins in the external data bus 16-bit mode or the WRL pin in the external data bus 8-bit mode). 0 I/O port (P53, P52) operation (write signal output prohibited) 1 Write strobe signal (WRH and WRL, or only WRL) output permitted [Initial value] [Bit 9] LMBS This bit specifies the bus width for accessing external buses corresponding to areas in a range of 002000H to 7FFFFFH, in the external data bus 16-bit mode. 0 16-bit bus width access [Initial value] 1 8-bit bus width access Note: To permit use of the WRH or WRL function by using the WRE bit in the external data bus 16bit mode, set P53 and P52 to the input mode (set bits 3 and 2 of DDR5 to "0"). Furthermore, even when RDY and HRQ input is permitted by RYE and HDE bits, the I/O port function of a port is enabled. Therefore, be sure to set "0" (input mode) to the bit in DDR5 corresponding to that port. 170 CHAPTER 7 MODE SETTING 7.5 Operation of Each Mode for Mode Setting This section has a timing chart showing the operation of each mode for mode setting. ■ Types of mode Operation with the following items is categorized by function as follows: • • • External memory access control signals • External data bus 8-bit mode (non-multiplex mode) • External data bus 8-bit mode (multiplex mode) • External data bus 16-bit mode (non-multiplex mode) • External data bus 16-bit mode (multiplex mode) Ready function • Non-multiplex mode • Multiplex mode Hold function • Non-multiplex mode • Multiplex mode 171 CHAPTER 7 MODE SETTING 7.5.1 External memory access control signals Access to external memory is performed in 3 cycles when the ready function is not used. ■ External memory access control signal Timing charts for external access in each mode are shown in Figure 7.5-1 "Access timing chart of external data bus 8-bit mode (non-multiplex mode)" to Figure 7.5-4 "Access timing chart of external data bus 16-bit mode (multiplex mode)". Access with an 8-bit bus width in the 16-bit external bus mode is a function for reading from and writing to peripheral chips of an 8-bit width when a mixture of peripheral chips of an 8-bit width and 16-bit width are connected to the external bus. Because access with an 8-bit bus width is performed using the low-order 8 bits of the data bus, connect the peripheral chips of an 8-bit bus width to the low-order 8 bits of data. Access with either a 16-bit bus width or an 8-bit bus width in the external data bus 16-bit mode is determined by the specification of the HMBS, LMBS, and/or IOBS bit of ECPR. Incidentally, there is a case where bus operation is not actually done by only outputting addresses and ALE assert results in the multiplex mode without assert for RD, WRL, and WRH. Note: Be sure to not perform access to peripheral chips with only ALE signals. 172 CHAPTER 7 MODE SETTING ❍ External data bus 8-bit mode (non-multiplex mode) Figure 7.5-1 Access timing chart of external data bus 8-bit mode (non-multiplex mode) Read Write Read P57/CLK P53/WRH (Port data) P52/WRL P51/RD P50/ALE A23 16 Read address Write address Read address A15 08 Read address Write address Read address A07 00 Read address Write address Read address D15 AD15 08/ 08 D07 AD07 00/ 00 (Port data) Read data Write data ❍ External data bus 8-bit mode (multiplex mode) Figure 7.5-2 Access timing chart of external data bus 8-bit mode (multiplex mode) Read Write Read P57/CLK P53/WRH (Port data) P52/WRL P51/RD P50/ALE A23 to 16 Read address A15 to 08 (Port data) A07 to 00 (Port data) D15 to 08/ AD15 to 08 D07 to 00/ AD07 to 00 Read address Read address Write address Read address Write address Read address Read address Write address Read data Write data 173 CHAPTER 7 MODE SETTING ❍ External data bus 16-bit mode (non-multiplex mode) Figure 7.5-3 Access timing chart of external data bus 16-bit mode (non-multiplex mode) Even-numbered address word read Even-numbered address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address Read address A15 to 08 Read address Write address Read address A07 to 00 Read address Write address Read address D15 to 08/ AD15 to 08 D07 to 00/ AD07 to 00 Read data Write data ❍ External data bus 16-bit mode (multiplex mode) Figure 7.5-4 Access timing chart of external data bus 16-bit mode (multiplex mode) Read Write Read Read address Write address P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 174 A15 to 08 (Port data) A07 to 00 (Port data) Read address D15 to 08/ AD15 to 08 Read address Write address Read address D07 to 00/ AD07 to 00 Read address Write address Read address Read data Write data CHAPTER 7 MODE SETTING 7.5.2 Ready function By setting the P56/RDY pin or defining the automatic ready function selection register (ARSR), access to low-speed memory and peripheral circuits is enabled. If the RYE bit in the bus control signal selection register (EPCR) is set to "1", wait cycles are generated during the period where the "L" level is input to the P56/RDY pin while access to the external area is in progress. Thus, the access cycle can be extended. ■ Ready function The F2MC-16LX has two types of built-in auto-ready functions for external memory. The autoready functions enable the access cycle to be extended by inserting 1 to 3 wait cycles automatically without an external cycle when access occurs to the external area within the following address ranges: a low-order address allocated between 002000H and 7FFFFFH, and a high-order address allocated between 800000H and FFFFFFH. These functions are evoked by setting the LMR1 and LMR0 bits of ARSR (external area of a low-order address) and the HMR1 and HMR9 bits of ARSR (external area of a high-order address). Furthermore, the F2MC-16LX has a built-in auto-ready function for external I/O that is independent of those for external memory. This function enables the access cycle to be extended by inserting 1 to 3 wait cycles automatically without an external cycle when access occurs to the external area between addresses 0000D0H and 0000FFH. This function is evoked by setting the IOR1 and IOR0 bits in ARSR. With the auto-ready functions for either external memory or external I/O, if the RYE bit of EPCR is set to "1" when the "L" level is input to the P56/RDY pin upon completion of the wait cycle generated by auto-ready, the wait cycle continues as is. The timing charts of the ready function in the non-multiplex mode and multiplex mode are shown below. In both modes, the top figure shows the case where the ready function is not set and the bottom figure shows the case where the ready function is set. Note: If the AC rating is not satisfied for input from the RDY pin, be careful because this device may enter the runaway state. 175 CHAPTER 7 MODE SETTING ❍ Non-multiplex mode Figure 7.5-5 Timing chart of ready function (non-multiplex mode) Even-numbered address word read Even-numbered address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address A15 to 08 Read address Write address A07 to 00 Read address Write address D15 to 08/ AD15 to 08 D07 to 00/ AD07 to 00 P56/RDY Capturing the RDY pin signal Read data Even-numbered address word read Write data Even-numbered address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address A15 to 08 Read address Write address A07 to 00 Read address Write address D15 to 08/ AD15 to 08 D07 to 00/ AD07 to 00 Write data 176 Cycles extended by auto-ready CHAPTER 7 MODE SETTING ❍ Multiplex mode Figure 7.5-6 Timing chart of ready function (multiplex mode) Even-numbered address word read Even-numbered address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address A15 to 08 (Port data) A07 to 00 (Port data) Write address D15 to 08/ AD15 to 08 Read address Write address D07 to 00/ AD07 to 00 Read address Write address P56/RDY Introduction of RDY pin Read data Even-numbered address word read Write data Even-numbered address word write P57/CLK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 Read address Write address A15 to 08 (Port data) A07 to 00 (Port data) D15 to 08/ AD15 to 08 Write address Read address D07 to 00/ AD07 to 00 Write address Read address Write data Cycles extended by auto-ready 177 CHAPTER 7 MODE SETTING 7.5.3 Hold function This section uses timing charts to describe the operation of the hold function. ■ Operation of hold function When the HDE bit of EPCR is set to "1", the external bus hold function specified by both the P54/HRQ and P55/HAK pins become effective. When the "H" level is input to the P54/HRQ pin, the hold state is set upon completion of a command by the CPU (after data of 1 element is processed in the case of the string command), and the "L" level is output from P55/HAK to set the following pins to a high-impedance state: ❍ Non-multiplex mode • Address output: A23 to A00 • Data input/output: D15/AD15 to D00/AD00 • Bus control signal: P51/RD, P52/WRL, P53/WRH ❍ Multiplex mode • Address output: A23 to A16 • Data input/output: D15/AD15 to D00/AD00 • Bus control signal: P51/RD, P52/WRL, P53/WRH This operation enables use of the external bus via the device external circuit. When the "L" level is input to the P54/HRQ pin, the P55/HAK pin outputs the "H" level to restore the external pin state, and the CPU restarts operation. In the STOP state, requests for hold are rejected. 178 CHAPTER 7 MODE SETTING ■ Non-multiplex mode Figure 7.5-7 "Timing chart of hold function (non-multiplex mode)" shows a timing chart of the non-multiplex-mode hold function in the external data bus 16-bit mode. Figure 7.5-7 Timing chart of hold function (non-multiplex mode) Read cycle Hold cycle Write cycle P57/CLK P54/HRQ P55/HAK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 (Address) (Address) /A15 to 08 (Address) (Address) A07 to 00 (Address) (Address) D15 to 08/ AD15 to 08 D07 to 00/ AD07 to 00 Read data Write data ■ Multiplex mode Figure 7.5-8 "Timing chart of hold function (multiplex mode)" shows a timing chart of the multiplex-mode hold function in the external data bus 16-bit mode. Figure 7.5-8 Timing chart of hold function (multiplex mode) Read cycle Hold cycle Write cycle P57/CLK P54/HRQ P55/HAK P53/WRH P52/WRL P51/RD P50/ALE A23 to 16 (Address) /A15 to 08 (Port data) A07 to 00 (Port data) D15 to 08/ AD15 to 08 D07 to 00/ AD07 to 00 (Address) (Address) (Address) Read data Write data 179 CHAPTER 7 MODE SETTING 180 CHAPTER 8 I/O PORT This chapter shows the configuration and explains the functions of the registers used for the I/O port. 8.1 "Functions of I/O Port" 8.2 "Registers for I/O Port" 181 CHAPTER 8 I/O PORT 8.1 Functions of I/O Port This section outlines the functions of the I/O port. ■ Functions of I/O port The I/O port has functions to output data from the CPU to I/O pins and introduce the signals input to I/O pins to the CPU by using the port register (PDR). Furthermore, the I/O port enables input to and output from I/O pins to be set in any direction in units of bits by using the port direction register (DDR). The MB90470 has 82 input/output ports and two open-drain output pins. Ports 0 to A are output ports, and P76 and P77 are open-drain pins. 182 CHAPTER 8 I/O PORT 8.2 Registers for I/O Port This section shows the configuration and explains the functions of the registers used for the I/O port. ■ Registers for I/O port The registers for the I/O port are listed below: • Port registers (PDR0 to PDRA) • Port direction registers (DDR0 to DDRA) • Input resistor registers (RDR0, RDR1) • Output pin registers (ODR7, ODR4) • Analog input enable registers (ADER) • Up/down timer input enable registers (UDER) 183 CHAPTER 8 I/O PORT 8.2.1 Port registers (PDR0 to PDRA) This section shows the configuration and explains the functions of port registers (PDR0 to PDRA) ■ Port registers (PDR0 to PDRA) Figure 8.2-1 "Port registers (PDR0 to PDRA)" shows a list of port registers (PDR0 to PDRA). Figure 8.2-1 Port registers (PDR0 to PDRA) PDR0 Address:000000H PDR1 Address:000001H PDR2 Address:000002H PDR3 Address:000003H PDR4 Address:000004H PDR5 Address:000005H PDR6 Address:000006H PDR7 Address:000007H PDR8 Address:000008H PDR9 Address:000009H PDRA Address:00000AH 7 P07 7 P17 7 P27 7 P37 7 P47 7 P57 7 P67 7 P77 7 P87 7 P97 7 - 6 P06 6 P16 6 P26 6 P36 6 P46 6 P56 6 P66 6 P76 6 P86 6 P96 6 - 5 P05 5 P15 5 P25 5 P35 5 P45 5 P55 5 P65 5 P75 5 P85 5 P95 5 - 4 P04 4 P14 4 P24 4 P34 4 P44 4 P54 4 P64 4 P74 4 P84 4 P94 4 - 3 P03 3 P13 3 P23 3 P33 3 P43 3 P53 3 P63 3 P73 3 P83 3 P93 3 PA3 2 P02 2 P12 2 P22 2 P32 2 P42 2 P52 2 P62 2 P72 2 P82 2 P92 2 PA2 1 P01 1 P11 1 P21 1 P31 1 P41 1 P51 1 P61 1 P71 1 P81 1 P91 1 PA1 0 Initial value P00 Undefined 0 P10 Undefined 0 P20 Undefined 0 P30 Undefined 0 P40 Undefined 0 P50 Undefined 0 P60 Undefined 0 P70 11XXXXXX 0 P80 Undefined 0 P90 Undefined 0 PA0 Undefined Access R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W (Note) R/W access to I/O ports differs slightly in operation from R/W access to memory. Be careful about such R/W access because it operates as follows: • • 184 Input mode • During reading: The level of the relevant pins is read and output. • During writing: Writing is performed on the latch for output. Output mode • During reading: The value of the data register latch is read and output. • During writing: Output is to the relevant pins. CHAPTER 8 I/O PORT 8.2.2 Port direction registers (DRR0 to DRRA) This section shows the configuration and explains the functions of port direction registers (DRR0 to DRRA.) ■ Port direction registers (DRR0 to DRRA) Figure 8.2-2 "Port direction registers (DRR0 to DRRA)" shows a list of port direction registers (DRR0 to DRRA). Figure 8.2-2 Port direction registers (DRR0 to DRRA) DDR0 Address:000010H DDR1 Address:000011H DDR2 Address:000012H DDR3 Address:000013H DDR4 Address:000014H DDR5 Address:000015H DDR6 Address:000016H DDR7 Address:000017H DDR8 Address:000018H DDR9 Address:000019H DDRA Address:00001AH 7 D07 7 D17 7 D27 7 D37 7 D47 7 D57 7 D67 7 7 D87 7 D97 7 - 6 D06 6 D16 6 D26 6 D36 6 D46 6 D56 6 D66 6 6 D86 6 D96 6 - 5 D05 5 D15 5 D25 5 D35 5 D45 5 D55 5 D65 5 D75 5 D85 5 D95 5 - 4 D04 4 D14 4 D24 4 D34 4 D44 4 D54 4 D64 4 D74 4 D84 4 D94 4 - 3 2 1 D03 D02 D01 3 2 1 D13 D12 D11 3 2 1 D23 D22 D21 3 2 1 D33 D32 D31 3 2 1 D43 D42 D41 3 2 1 D53 D52 D51 3 2 1 D63 D62 D61 3 2 1 D73 D72 D71 3 2 1 D83 D82 D81 3 2 1 D93 D92 D91 3 2 1 DA3 DA2 DA1 0 Initial value D00 00000000 0 D10 00000000 0 D20 00000000 0 D30 00000000 0 D40 00000000 0 D50 00000000 0 D60 00000000 0 D70 --000000 0 D80 00000000 0 D90 00000000 0 DA0 ----0000 Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W ❍ When each pin functions as a port When each pin functions as a port, it controls the corresponding pin as follows: • 0: Input mode • 1: Output mode, which can be set to "0" by a reset. 185 CHAPTER 8 I/O PORT ❍ Handling of ports 76 and 77 These ports have no DDR. Since they always function as ports in which data is to be effective, specify the value of PDR to "1" when using P76 and P77 as pins for I2C. (Incidentally, when using them as P76 and P77, stop I2C.) Furthermore, these ports are open-drain output ports, so to turn off the transistor when they are used as input ports, specify the output data register to have a value of "1" and attach a pull-up resistor to the external pin. Note: If this register is accessed with a command of the read-modify-write type (such as the bit-set command), the contents of the output registers corresponding to the other bits specified for input are replaced with the input value of the pin at the time of access even if the bit specified by the command is set to the required value. Therefore, when a pin for input is switched to a pin for output, be sure to define DDR after writing the desired value to PDR, and then switch it to a pin for input. 186 CHAPTER 8 I/O PORT 8.2.3 Other registers This section shows the configuration and explains the functions of registers other than port registers (PDR0 to PDRA) or port direction registers (DDR0 to DDRA). ■ Input resistor registers (RDR0, ROR1) The bit configuration of input resistor registers (RDR0, ROR1) is shown in the figure below. RDR0 7 6 5 4 3 2 1 0 Address:00001CH RD07 RD06 RD05 RD04 RD03 RD02 RD01 RD00 RDR1 7 6 5 4 3 2 1 0 Address:00001DH RD17 RD16 RD15 RD14 RD13 RD12 RD11 RD10 Initial value Access 00000000 R/W 00000000 R/W Input resistor registers (RDR0, ROR1) specify whether or not there is pull-up resistor in the input mode. • 0: Pull-up resistor in the input mode • 1: No pull-up resistor in the input mode These registers have no function in the output mode (no pull-up resistor). The input or output mode is determined by the setting on the direction register (DDR). During a stoppage (SPL = 1), the lack of pull-up resistor is specified (high impedance). This function is prohibited if an external bus is used. Do not write it to this register. ■ Output pin registers (ODR7, ODR4) The bit configuration of output pin registers (ODR7, ODR4) is shown in the figure below. ODR7 7 6 5 4 3 2 1 0 - OD75 OD74 OD73 OD72 OD71 OD70 Address:00001EH ODR4 7 6 5 4 3 2 1 0 Address:00001BH OD47 OD46 OD45 OD44 OD43 OD42 OD41 OD40 Initial value Access --000000 R/W 00000000 R/W Output pin registers (ODR7, ODR4) perform open drain control in the output mode. • 0: Sets a standard output port to the output mode • 1: Sets an open-drain output port to the output mode Output pin registers have no function in the input mode (Output Hi-Z). The input or output mode is determined by the setting of the direction register (DDR). This function is prohibited when an external bus is used. Do not write it to this register. 187 CHAPTER 8 I/O PORT ■ Analog input enable register (ADER) The bit configuration of the analog input enable register (ADER) is shown in the figure below. ADER 7 6 5 4 3 2 1 0 Address:00001FH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 Initial value Access 11111111 R/W The analog input enable register (ADER) controls the pins of port 6 as follows: • 0: Sets the port I/O mode • 1: Set the analog I/O mode. "1" is restored by a reset. ■ Up/down timer input enable register (UDER) The bit configuration of the up/down timer input enable register (UDER) is shown in the figure below. UDER Address:00000BH 7 - 6 - 5 4 3 2 1 0 Initial value Access UDE5 UDE4 UDE3 UDE2 UDE1 UDE0 XX000000 R/W The up/down timer input enable register (UDER) controls the pins of port 6 as follows: • 0: Sets the port I/O mode • 1: Sets the up/down timer input mode. "1" is restored by a reset. In the MB90470 series, each bit is set as follows: 188 • UDE0: P30/AIN0 • UDE1: P31/BIN0 • UDE2: P32/ZIN0 • UDE3: P33/AIN1 • UDE4: P34/BIN1 • UDE5: P35/ZIN1 CHAPTER 9 TIMEBASE TIMER This chapter explains the function and operation of the timebase timer. 9.1 "Overview" 9.2 "Timebase Timer Configuration" 9.3 "Timebase Timer Control Register (TBTC)" 9.4 "Timebase Timer Interrupt " 9.5 "Timebase Timer Operation" 9.6 "Notes on Using Timebase Timer" 9.7 "Sample Programs" 189 CHAPTER 9 TIMEBASE TIMER 9.1 Overview The timebase timer, which is an 18-bit free-running counter (timebase timer counter) that counts in synchronization with the internal count clock (the source clock frequency divided by 2), has the interval timer function to enable selection of four types of interval times. Furthermore, it also has functions to supply operation clocks including timer output for the oscillation stabilization wait time as well as the watchdog timer. ■ Interval timer function The interval timer function generates repetitive interval interrupt requests. • An interrupt request is generated when the bit for the interval timer in the timebase counter overflows. • The bit for the interval timer (interval time) can be selected out of four types. Table 9.1-1 "Interval time of timebase timer" shows the interval time of the timebase timer. Table 9.1-1 Interval time of timebase timer Internal count clock cycle Interval cycle 212 / HCLK (approximately 1.0 ms) 2 / HCLK (0.5 µs) 214 / HCLK (approximately 4.1 ms) 216 / HCLK (approximately 16.4 ms) 219 / HCLK (approximately 131.1 ms) HCLK: Oscillation clock The value during operation of the oscillation clock at 4 MHz is shown in ( ). 190 CHAPTER 9 TIMEBASE TIMER ■ Clock supplying function The clock supplying function is the function supplying the timer for the oscillation stabilization wait time and the operation clocks to some peripheral functions. Table 9.1-2 "Clock cycles supplied by timebase timer" lists the cycles of the clocks supplied by the timebase timer to individual peripheral functions. Table 9.1-2 Clock cycles supplied by timebase timer Function to which clock is supplied Clock cycle 213 / HCLK (approximately 2.0 ms) Oscillation stabilization wait time 215 / HCLK (approximately 8.2 ms) 2 17 / HCLK (approximately 32.8 ms) Remarks Oscillation stabilization wait time for ceramic resonator Oscillation stabilization wait time for crystal resonator 212 / HCLK (approximately 1.0 ms) 214 / HCLK (approximately 4.1 ms) Watchdog timer 216 / HCLK (approximately 16.4 ms) Up-count clock for watchdog timers 219 / HCLK (approximately 131.1 ms) HCLK: Oscillation clock The value during operation of the oscillation clock at 4 MHz is shown in ( ). Reference: Because the oscillation cycle immediately after the start of oscillation is unstable, the oscillation stabilization wait time is merely a guideline. 191 CHAPTER 9 TIMEBASE TIMER 9.2 Timebase Timer Configuration The timebase timer is composed of the following four blocks: • Timebase timer counter • Counter clear circuit • Interval timer selector • Timebase timer control register (TBTC) ■ Block diagram of timebase timer Figure 9.2-1 "Block diagram of timebase time" is a block diagram of the timebase timer. Figure 9.2-1 Block diagram of timebase timer To watchdog timer To PPG timer Timebase timer counter HCLK frequency divided by 2 × 21 × 22 × 23 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 OF OF Power-on reset Stop mode start CKSCR : MCS = 1→ 0 (*1) CKSCR : SCS = 0 → 1 (*2) OF OF To selector of oscillation stabilization wait time in clock control section Counter clear circuit Interval timer selector TBOF set TBOF clear Timebase timer control register (TBTC) RESV TBIE TBOF TBR TBC1 TBC0 Timebase timer interrupt signal OF HCLK *1 *2 : Not used : Overflow : Oscillation clock : Switching the machine clock from the main clock or the sub-clock to the PLL clock : Switching the machine clock from the sub-clock to the main clock ❍ Timebase timer counter This is an 18-bit up-counter that uses the oscillation clock (HCLK) frequency divided by 2 as the count clock. ❍ Counter clear circuit This circuit clears the counter at the time of writing of "0" to the timebase timer initializing bit (TBR) in the timebase timer control register (TBTC), a power-on reset, a transition to the main stop mode, a transition to the PLL stop mode, switching from the main clock mode to the PLL clock mode, switching from sub-clock mode to the PLL clock mode, and switching from the subclock mode to main clock mode. 192 CHAPTER 9 TIMEBASE TIMER ❍ Interval timer selector Selects one of the four types of timebase timer counter output. Overflow of the selected bit causes an interrupt. ❍ Timebase timer control register (TBTC) Selects the interval time, clears the counter, controls interrupt requests, and checks the current state. 193 CHAPTER 9 TIMEBASE TIMER 9.3 Timebase Timer Control Register (TBTC) This register selects the interval time, clears the counter, controls interrupt requests, and checks the state. ■ Timebase timer control register (TBTC) Figure 9.3-1 Timebase timer control register (TBTC) bit15 bit14 0000A9H RESV R/W bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0 TBIE TBOF TBR TBC1 TBC0 R/W R/W W R/W (TBTC) Initial value 1XX00100B R/W TBC1 TBC0 Interval time selection bit 0 0 212/HCLK (approximately 1.0 ms) 0 1 214/HCLK (approximately 4.1 ms) 1 0 216/HCLK (approximately 16.4 ms) 1 1 219/HCLK (approximately 131 ms) The value during operation of the oscillation clock at 4 MHz is shown in ( ). TBR Timebase timer initializing bit During reading During writing Clears TBOF bit of timebase timer counter 0 1 TBOF 194 Interrupt request flag bit During reading During writing No overflow of specified bit Clears this bit. 1 Overflow of specified bit No change, no effect on other functions Interrupt request permit bit 0 Prohibits interrupt request output 1 Permits interrupt request output RESV : Read and write enabled : Write only : Not used : Undefined : Oscillation clock : Initial value No change, no effect on other functions 0 TBIE R/W W x HCLK "1" is always read and output Reserved bit Always write "1" to this bit CHAPTER 9 TIMEBASE TIMER Table 9.3-1 Functions of bits in timebase timer control register (TBTC) Bit name Function Bit 15 RESV: Reserved bit <Note> Always write "1" to this bit. Bit 14 Bit 13 Unused bits • • Undefined value in reading No effect on write operation Bit 12 TBIE: Interrupt request permit bit • • This bit permits or prohibits output of interrupt requests to the CPU. An interrupt request is output if this bit and the interrupt request flag bit (TBOF) are set to "1". • Bit 11 TBOF: Interrupt request flag bit Bit 10 TBR: Timebase timer initializing bit Bit 9 Bit 8 TBC1, TBC: Interval time selection bit This bit is set to "1" when the bit specified by the timebase timer counter overflows. • An interrupt request is output if this bit and the interrupt request permit bit (TBIF) are set to "1". • This bit is cleared by writing "0" but is not changed by writing "1" so that this operation does not affect other functions. • Reading by read-modify-write type instructions always returns "1". <Notes> • Clearing of the interrupt request flag bit (TBOF) in the timebase timer control register (TBTC) must be implemented in the state where the timebase timer interrupt is prohibited by the interrupt request permit bit (TBIE) or by the interrupt level mask register (ILM) setting of the processor status (PS). • This bit is cleared to "0" by writing "0", a transition to the main stop mode, a transition to the PLL stop mode, a transition from the subclock mode to the main clock mode, a transition from the sub-clock mode to the PLL clock mode, a transition from the main clock mode to the PLL clock mode, or writing "0" to the timebase timer initializing bit (TBR) or a reset. • • This bit clears the timebase timer counter. When "0" is written to this bit, the counter is cleared and the TBOF bit is cleared. This bit is not changed by writing "1" so that this operation does not affect other functions. [Reference] The readout value is always "1". • • • This bit specifies the cycle of the interval timer. The bit for the interval timer in the timebase timer counter is specified. The interval time can be selected out of four types. 195 CHAPTER 9 TIMEBASE TIMER 9.4 Timebase Timer Interrupt The timebase timer can generate the interrupt request caused by an overflow of the specified bit in the timebase timer counter (interval timer function). ■ Timebase timer interrupt When the timebase timer counter counts up using the internal count clock and the bit for the selected interval timer overflows, the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) is set to "1". In this event, if an interrupt request is permitted because the interrupt request permit bit (TBIE) is set to "1", an interrupt request is generated in the CPU. Clear this interrupt request by writing "0" to the TBOF bit using the interrupt processing routine. Incidentally, TBOF is set when the specified bit overflows regardless of the value of the interrupt request permit bit (TBIE). Note: Clearing of the interrupt request flag bit (TBOF) in the timebase timer control register (TBTC) must be implemented in the state where the timebase timer interrupt is prohibited by the interrupt request permit bit (TBIE) or by the interrupt level mask register (ILM) setting of the professor status (PS). Reference: • If the TBOF bit is set to "1", an interrupt request is generated immediately when the TBIE bit is switched from prohibit (0) to permit (1). • µDMA cannot be used in the timebase timer. ■ Timebase timer interrupt and µDMA Table 9.4-1 "Timebase timer interrupt and µDMA (This table shall be shown for each model.)" lists timebase timer interrupts and µDMA. Table 9.4-1 Timebase timer interrupt and µ DMA (This table shall be shown for each model.) Interrupt level setting register Address of the vector table Interrupt No. #41 Register name Address Low-order High-order Bank ICR15 0000BFH FFFF58H FFFF59H FFFF5AH µDMA x x: Not used Note: This note shall be provided for each model. ICR15 is commonly used by the timebase timer interrupt, the watch timer interrupt, and FLASH write. Although interrupt can be used for these three purposes, the interrupt level is the same. 196 CHAPTER 9 TIMEBASE TIMER 9.5 Timebase Timer Operation The timebase timer has the interval timer function as well as the clock supplying function for some peripheral functions. ■ Operation of interval timer function (timebase timer) The interval timer function generates interrupt requests at any defined interval times. For its operation as an interval timer, the settings shown in Figure 9.5-1 "Timebase timer settings" are required. Figure 9.5-1 Timebase timer settings Address bit15 bit14 bit13 bit12 bit11 bit10 bit9 0000A9H TBTC RESV 1 bit8 bit7 TBIE TBOF TBR TBC1 TBC0 0 bit15 (WDTC) 0 : Bits in use - : Unused bits 0 : 0 is set 1 : 1 is set • The timebase timer counter continues counting up in synchronization with the internal count clock (the source clock frequency divided by 2) as long as the clock is oscillating. • When the counter has been cleared, the up-count starts from "0", and an overflow of the bit used for the interval timer sets the interrupt request flag bit (TBOF) to "1". In this event, if the interrupt request output is permitted (TBIE = 1), interrupts are generated at the selected interval times with the clearing time used as a reference time point. • The interval time may become longer than the specified time, e, when the timebase timer was cleared. ■ Timer function for Oscillation Stabilization Wait Time The timebase timer can also be used as the main clock as well as the timer for the oscillation stabilization wait time of the PLL clock. The oscillation stabilization wait time is the time in which counting starts when the counter is set to "0" (clearing of counter) and continues until an overflow occurs in the bit for the oscillation stabilization wait time. However, during return from the timebase timer mode to the PLL clock mode or main clock mode, the waiting time differs because the timebase timer counter is not cleared and the time count does not start from zero. Table 9.5-1 "Timebase timer clear operation and oscillation stabilization wait time" explains the timebase timer clear operation and oscillation stabilization wait time. 197 CHAPTER 9 TIMEBASE TIMER Table 9.5-1 Timebase timer clear operation and oscillation stabilization wait time. Operation Counter clear TOBF clear Oscillation stabilization wait time Writing "0" to initializing bit (TBR) for timebase timer control register (TBTC) - Power-on reset Watchdog reset Oscillation stabilization wait time of main clock x Release of the main stop mode Oscillation stabilization wait time of main clock Release of the PLL stop mode Release of the sub stop mode x x Switching from main clock mode to PLL clock mode (MCS: transition from 1 to 0) Oscillation stabilization wait time of sub-clock Oscillation stabilization wait time of PLL clock Transition from sub-clock mode to main clock mode (SCS: transition from 0 to 1) x x Oscillation stabilization wait time of main clock Release of timebase timer mode x x Not provided Release of sleep mode x x Not provided : Cleared x: Not cleared ■ Clock supplying function The timebase timer supplies a clock to the watchdog timer. Clearing of the timebase timer counter affects the operation of the watchdog timer. 198 CHAPTER 9 TIMEBASE TIMER 9.6 Notes on Using Timebase Timer This section explains notes on using the timebase timer, including the effects of clearing an interrupt request or clearing the timebase timer on peripheral functions. ■ Notes on using timebase timer ❍ Clearing an interrupt request Clearing the interrupt request flag bit (TBOF) of the timebase timer control register (TBTC) must be implemented in the state where the timebase timer interrupt is masked by the interrupt request permit bit (TBIE) or by the interrupt level mask register (ILM) setting of the processor status (PS). ❍ Effect of clearing the timebase timer Clearing the timebase timer counter affects the following: • Operations where the interval timer function (interval interrupt) is used by the timebase timer • Operations using the watchdog timer ❍ Use of the timer for the oscillation stabilization wait time When power is turned on, the oscillation clock is stopped in the main stop mode. In such a case, after the oscillator starts operating, the oscillation stabilization wait time of the clock must be provided by using as a timing reference the operation clock supplied by the timebase timer. An appropriate oscillation stabilization wait time must be selected depending on the type of oscillator (resonator) connected to the high-speed oscillation pin. See Section 5.5 "Oscillation Stabilization Wait Time", for details. ❍ Caution on using peripheral functions whose operation clock is supplied from the timebase timer In a mode where the main clock stops, the counter is cleared and the timebase timer stops operating. Furthermore, because the clock supplied by the timebase timer is reset to the initial state and is supplied again when the timebase timer counter is cleared, the period of "H" level may become shorter or the period of "L" level may become longer by a maximum of a 1/2 cycle. Although the clock for the watchdog timer is also supplied from the initial state, the watchdog timer operates at normal cycles because the watchdog time counter is cleared at the same time. 199 CHAPTER 9 TIMEBASE TIMER ■ Operation of timebase timer Operations in the following states are shown in Figure 9.6-1 "Operation of timebase time": • Where the power-on sequence has occurred • Where transition to the sleep mode has occurred during processing for the interval time function • Where transition to the stop mode has occurred • Where clearing of the counter is requested Transition to the stop mode clears the timebase timer to stop operation. After restoration from the stop mode, the timebase timer counter starts an up-count of the oscillation stabilization wait time. Figure 9.6-1 Operation of timebase timer Counter value 3FFFFH Clearing by transition to stop mode Overflow during oscillation stabilization wait time 00000H Start of CPU operation Power-on reset (option) Interval cycle (TBTC : TBC1, TBC0 = 11B) Clearing of counter (TBTC : TBR = 0) Clearing by the interrupt processing routine TBOF bit TBIE bit Sleep SLP bit (LPMCR register) Release of interval interrupt sleep Stoppage STP bit (LPMCR register) Release of stoppage by external interrupt "11B" is set to the interval time selection bit (TBTC, TBC1, TBC0) in the timebase timer control register (219/HCLK). : Oscillation stabilization wait time HCLK : Oscillation clock 200 CHAPTER 9 TIMEBASE TIMER 9.7 Sample Programs Sample programs for the timebase timer are shown below. ■ Sample programs of timebase timer ❍ Specifications for processing Repetitive generation of an interval interrupt of 212/HCLK (oscillation clock). The interval time in this case is approximately 1.0 ms (when operating at 4 MHz). ❍ Sample coding ICR12 EQU 0000BCH ; Interrupt control register for timebase timer TBTC EQU 0000A9H ; timebase timer control register TBOF EQU TBTC:3 ; Interrupt request flag bit ;---------- Main program ------------------------------------------CODE CSEG START: ; : ; Assumption that stack pointer ; (SP), etc., have been initialized AND CCR, #0BFH ; Disabling interrupts MOV I:ICR12, #00H ; Interrupt level 0 (highest) MOV I:TBTC, #10010000B ; Three high-order bits must be fixed ; Permitting interrupts, clearing of TBOF ; Clearing the counter ; Selection of interval time of 212/HCLK MOV ILM, #07H ; Setting ILM in PS to level 7 OR CCR, #40H ; Enabling interrupts LOOP: MOV A,#00H ; Infinite loop MOV A,#01H BRA LOOP ;---------- Interrupt program -------------------------------------WARI: CLR bit BOF ; Clearing the interrupt request flag ; : ; User processing ; : RETI ; Restoration from interrupt CODE ENDS ;---------- Specifying vectors ------------------------------------VECT CSEG ABS=0FFH ORG 0FF6CH ; Specifying the interrupt vector DSL WARI ORG 0FFDCH ; Specifying the reset vector DSL START DB 00H ; Setting to the single-chip mode VECT ENDS END START 201 CHAPTER 9 TIMEBASE TIMER 202 CHAPTER 10 WATCHDOG TIMER This chapter describes the operation and function of the watchdog timer. 10.1 "Overview" 10.2 "Watchdog Timer Control Register (WDTC)" 10.3 "Watchdog Timer Configuration" 10.4 "Watchdog Timer Operation" 10.5 "Notes on Using Watchdog Timer" 10.6 "Sample Programs" 203 CHAPTER 10 WATCHDOG TIMER 10.1 Overview The watchdog timer is a 2-bit counter that uses the output of the timebase timer or the watch timer as the count clock, and if it is not cleared within a certain period of time after startup, this timer resets the CPU. ■ Functions of watchdog timer The watchdog timer is a counter used to prevent runaway programs. Once it is started, this timer must be cleared periodically within a certain period of time. If it is not cleared within a certain period of time because a program is running in an infinite loop, it generates a watchdog reset to the CPU. The interval time of the watchdog timer can be specified on the WT1 and WT0 bits in the watchdog timer control register (WDTC), as shown in Table 10.1-1 "Interval time for watchdog timer". If the watchdog timer is not cleared, a watchdog reset is generated after the minimum time and before the maximum time. Be sure to clear the timer within the minimum time. Table 10.1-1 Interval time for watchdog timer WT1 WT0 WDCS & SCM 0 0 1 Approximately 3.58 ms Approximately 4.61 ms 214 ± 211 HLCK cycles 0 1 1 Approximately 14.33 ms Approximately 18.43 ms 216 ± 213 HLCK cycles 1 0 1 Approximately 57.23 ms Approximately 73.73 ms 218 ± 215 HLCK cycles 1 1 1 Approximately 458.75 ms Approximately 589.82 ms 221 ± 218 HLCK cycles 0 0 0 Approximately 0.457 s Approximately 0.576 s 212 ± 29 SLCK cycles 0 1 0 Approximately 3.584 s Approximately 4.608 s 215 ± 212 SLCK cycles 1 0 0 Approximately 7.168 s Approximately 9.216 s 216 ± 213 SLCK cycles 1 1 0 Approximately 14.336 s Approximately 18.432 s 217 ± 214 SLCK cycles Interval time Minimum (*1) Maximum (*1) Number of clock cycles *1: Values during operation of the oscillation clock (HCLK) at 4 MHz and the sub-clock (SCLK) at 32 kHz frequency divided by 4 (= 8 kHz) The maximum and minimum watchdog timer interval times and the number of the oscillation clock cycles depend on the time of the clear operation. The interval time is 3.5 to 4.5 times as large as the cycle of the count clock (clock supplied by the timebase timer). For the watchdog timer interval times, see Section 10.4 "Watchdog Timer Operation". Note: The watchdog counter is composed of a 2-bit counter to count the carry signals of the timebase timer. Therefore, if the timebase timer counter has been cleared, the time until the occurrence of watchdog reset may become longer than the specified time. 204 CHAPTER 10 WATCHDOG TIMER Reference: When the watchdog timer is started, it can be initialized by a power-on reset or watchdog reset so that it stops. In addition, the watchdog timer is still active even though the watchdog counter is cleared at reset by the external pin, reset by software, writing to the watchdog control bit (WTE) of the watchdog timer control register, transition to the sleep mode, transition to the stop mode, and transition to the watch mode. 205 CHAPTER 10 WATCHDOG TIMER 10.2 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) is used for the start and clearing of the watchdog timer and the display of reset causes. ■ Watchdog timer control register (WDTC) Figure 10.2-1 "Watchdog timer control register (WDTC)" shows the configuration of the watchdog timer control register (WDTC), and Table 10.2-1 "Function of bits in watchdog timer control register (WDTC)" explains the function of each bit in the WDTC register. Figure 10.2-1 Watchdog timer control register (WDTC) Address 0000A8H bit15 bit8 (TBTC) bit7 bit6 bit5 bit4 bit3 bit2 bit1 PONR Reserved WRST ERST SRST WTE WT1 R R R R W bit0 Initial value WT0 XXXXX111B W W Interval time selection bit (at HCLK: 4 MHz; SCLK: 32 kHz) Interval time Number of oscillation & SCM clock cycles Minimum Maximum WT1 WT0 WDCS 0 0 0 1 Approximately 3.58 ms Approximately 4.61 ms 214 ± 211 HCLK cycles 1 Approximately 14.33 ms Approximately 18.3 ms 216 ± 213 HCLK cycles 218 ± 215 HCLK cycles 1 1 1 Approximately 57.23 ms Approximately 73.73 ms 1 1 1 Approximately 458.75 ms Approximately 589.82 ms 221 ± 218 HCLK cycles 0 0 1 0 0 Approximately 0.457 s Approximately 0.576 s 0 Approximately 3.584 s Approximately 4.608 s 215 ± 212 SCLK cycles 1 0 0 Approximately 7.168 s Approximately 9.216 s 217 ± 213 SCLK cycles 1 1 0 Approximately 14.336 s Approximately 18.432 s 217 ± 214 SCLK cycles 212 ± 29 SCLK cycles HCLK: Oscillation clock SCLK: Sub-clock Watchdog control bit WTE 0 Starts the watchdog timer (at first write event after reset) Clears the watchdog timer (at second write event after reset) 1 No operation Reserved bit Reading and writing has no effect on operation Reset cause bits Reset cause PONR WRST ERST SRST R W x * : Read only : Write only : Undefined : Not used : The previous state is held. : Default value 1 X X X Power on * * 1 * * Watchdog timer * 1 * * External pin (RST = "L" input) * * 1 RST bit (software reset) The interval time is 3.5 to 4.5 times as large as the count clock (output of the timebase timer) cycle. See Section 10.4 "Watchdog Timer Operation", for details. 206 CHAPTER 10 WATCHDOG TIMER Table 10.2-1 Function of bits in watchdog timer control register (WDTC) Bit name Function • These are read-only bits that indicate reset causes. Each of these bits is set to "1" when the corresponding reset cause has occurred. All of these bits are cleared to "0" after reading of the WDTC register. When power is turned on, the contents of bits other than the PONR bit are not assured. Therefore, if the POBR bit is set to "1", ignore the contents of other bits. Bit 7 Bit 5 Bit 4 Bit 3 PONR WRST ERST SRST Reset cause bits • • Bit 6 Reserved Reserved bit Reading and writing to this bit has no effect on operation. • Bit 2 WTE Watchdog control bit • • • Bit 1 Bit 0 WT1 WT0 Interval time selection bits • • When "0" is written to this bit, the watchdog timer is started (at the first write event after a reset) or the 2-bit counter is cleared (at the second and succeeding write events after a reset). Writing "1" does not affect operation. These are the bits for selecting the interval time of the watchdog timer. The interval time varies, as shown in Figure 10.2-1 "Watchdog timer control register (WDTC)", between the case where the sub-clock mode is selected as the clock mode (the sub-clock display bit (SCM) of the clock selection register (CKSCR) is "0") or the clock source of the watchdog timer is set to the watch timer by the watch timer control register (WTC) (the watchdog timer clock source selection bit (WDCS) is set to "0") and the case where the main clock mode or PLL clock mode is selected as the clock mode while the WDCS bit of WTC is set to "1". Only data that has been defined before the start of the watchdog timer are effective. Any data that is written after the start of the watchdog timer is ignored. These bits are write-only. 207 CHAPTER 10 WATCHDOG TIMER 10.3 Watchdog Timer Configuration The watchdog timer is composed of the following five blocks: • Count clock selector • Watchdog counter (2-bit counter) • Watchdog reset generation circuit • Counter clear control circuit • Watchdog timer control register (WDTC) ■ Block diagram of watchdog timer Figure 10.3-1 "Block diagram of watchdog time" is a block diagram of the watchdog timer. Figure 10.3-1 Block diagram of watchdog timer Watchdog timer control register (WDTC) PONR Reserved WRST ERST SRST WTE WT1 WT0 WDCS bit in watch timer control register (WTC) SCM bit in clock selection register (CKSCR) Watch mode start Timebase timer mode start Sleep mode start Hold state start Watchdog timer Stop mode start 2 CLR and start Counter clear control circuit Count clock selector 2-bit counter Overflow CLR Watchdog reset generation circuit To internal reset generation circuit CLR 4 Clear 4 (Timebase timer counter) HCLK frequency divided by 2 × 21 × 2 2 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 SCLK × 21 × 2 2 × 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218 HCLK: Oscillation clock SCLK: Sub-clock ❍ Count clock selector This circuit selects the count clock of the watchdog time from among four types of timebase timer output and four types of watch timer output. This selection determines the time for generating a watchdog reset. ❍ Watchdog counter (2-bit counter) This is a 2-bit up-counter that uses timebase timer output as the count clock. ❍ Watchdog reset generation circuit This circuit generates a reset signal for an overflow of the watchdog counter. ❍ Counter clear circuit This circuit controls the clearing of the watchdog counter and the start and stop of the counter. 208 CHAPTER 10 WATCHDOG TIMER ❍ Watchdog timer control register (WDTC) This register is used for the start and clearing of the watchdog timer, and holding of the reset cause. 209 CHAPTER 10 WATCHDOG TIMER 10.4 Watchdog Timer Operation The watchdog timer generates a watchdog reset for an overflow of the watchdog counter. ■ Operation of watchdog timer Figure 10.4-1 "Watchdog timer settings" shows the settings required for operation of the watchdog timer. Figure 10.4-1 Watchdog timer settings Address bit15 0000A8H WDTC bit8 (TBTC) bit7 bit6 bit5 bit4 bit3 bit2 PONR Reserved WRST ERST SRST WTE bit1 bit0 WT1 WT0 0 : Bits being used 0 : Set to 0 ❍ Starting the watchdog timer • After a reset, the watchdog timer starts operation when the first "0" is written to the watchdog control bit (WTE) in the watchdog timer control register (WDTC). The interval time is then specified at the same time on the interval time selection bits (WT1, WT0) in the WDTC register. • Once the watchdog timer has started operating, it cannot be stopped unless the power-on sequence is used or a watchdog reset occurs. ❍ Clearing of the watchdog timer • The 2-bit counter of the watchdog timer is cleared when the second or subsequent "0" is written to the WTE bit. If the counter is not cleared within the interval time, the counter overflows to generate a watchdog reset. • The watchdog counter is cleared when a reset occurs and by a transition to the sleep mode, stop mode, or timebase timer mode. • When a transition to the timebase timer mode or watch mode occurs, the watchdog counter is cleared once, but be careful because the watchdog counter does not stop after being cleared. • When the device is used in the watch mode (sub-clock), do not use the watchdog timer. ❍ Interval time of the watchdog timer Figure 10.4-2 "Clearing times and interval time of watchdog time" shows the relationship between the timing and interval time of the watchdog timer. The interval time varies depending on the timing when the watchdog timer is cleared, which takes 3.5 to 4.5 times as much time as the count clock cycle. ❍ Check of reset causes After a reset, the reset cause can be found by checking the reset cause bits [PONR, WRST, ERST, SRST] in the WDTC register. 210 CHAPTER 10 WATCHDOG TIMER Figure 10.4-2 Clearing times and interval time of watchdog timer [Block diagram of watchdog timer] 2-bit counter Clock selector a WTE bit frequency divide-by-2 circuit Count permit output circuit b frequency divide-by-2 circuit c d Reset circuit Reset signal Count permit and clear [Minimum interval time] The WTE bit is cleared immediately before the count clock starts. Start of count Counter clearing Count clock a frequency divide-by-2 value b frequency divide-by-2 value c Count permit Reset signal d 7 × (count-clock-cycles/2) WTE bit clearing Occurrence of watchdog reset [Maximum interval time] The WTE bit is cleared immediately after the count clock starts. Start of count Counter clearing Count clock a frequency divide-by-2 value b frequency divide-by-2 value c Count permit Reset signal d 9 × (count-clock-cycles/2) WTE bit clearing Occurrence of watchdog reset 211 CHAPTER 10 WATCHDOG TIMER 10.5 Notes on Using Watchdog Timer This section explains notes on using the watchdog timer. ■ Notes on using watchdog timer ❍ Stopping the watchdog timer Once the watchdog timer has started operating, it cannot be stopped unless the power-on sequence is used or an external reset of watchdog occurs. ❍ Interval time Because the interval time uses the carry signals of the timebase timer as the count clock, the interval time of the watchdog timer may become longer than the specified time when the timebase timer is cleared. The timebase timer is also cleared by writing "0" to the TBR bit in the timebase timer control register (TBTC), transition from main clock mode to PLL clock mode, transition from sub-clock mode to main clock mode and transition from sub-clock mode to PLL clock mode. ❍ Selection of the interval time The interval time can be specified when the watchdog timer is started. Any data written after the start of the watchdog timer is ignored. ❍ Caution on preparing programs When preparing a program that clears the watchdog timer repetitively in the main loop, the main loop processing time, including interrupt processing, must be less than the minimum interval time of the watchdog timer. 212 CHAPTER 10 WATCHDOG TIMER 10.6 Sample Programs Sample programs for the watchdog timer are shown below. ■ Sample programs for watchdog timer ❍ Specifications for processing • Clears the watchdog timer once per loop of the main program. • The main loop must complete a circuit within the minimum interval time of the watchdog timer. ❍ Sample coding WDTC EQU 0000A8H ; Watchdog timer control register WTE EQU WDTC:2 ; Watchdog control bit ;---------- Main program -----------------------------------------------------CODE CSEG START: ; : ; Assumption that the stack pointer (SP), ; etc., have been initialized. WDG_START: MOV WDTC, #00000011B ; Start of watchdog timer Selection of ;interval time of 221 ± 218 cycles ;---------- Main loop --------------------------------------------------------MAIN: CLRB I:WTE ; Clearing of watchdog timer ; : ; Periodic 2-bit clearing ; User processing ; : JMP MAIN ; Loop time shorter than interval ; time of watchdog timer CODE ENDS ;---------- Specifying vectors -----------------------------------------------VECT CSEG ABS=0FFH ORG 0FFDCH ; Specifying the reset vector DSL START DB 00H ; Setting to the single-chip mode VECT ENDS END START 213 CHAPTER 10 WATCHDOG TIMER 214 CHAPTER 11 WATCH TIMER This chapter has an overview of the watch timer, describes the configuration and functions of the register, and explains the operation of the watch timer. 11.1 "Overview" 11.2 "Watch Timer Configuration" 11.3 "Watch Timer Control Register (WTC)" 11.4 "Watch Timer Operation" 215 CHAPTER 11 WATCH TIMER 11.1 Overview The watch timer is a 15-bit timer using the sub-clock. This timer can generate interval interrupts. Furthermore, depending on the setting, this timer can be used as the clock source for the watchdog timer. ■ Functions of watch timer The watch timer is composed of a 15-bit timer and a circuit to control interval interrupts. The watch timer uses the sub-clock regardless of the PLL clock selection bit (MCS) or the subclock selection bit (SCS) in the clock selection register (CKSCR). Table 11.1-1 "Interval times of watch timer" lists the interval times of the watch timer. Table 11.1-1 Interval times of watch timer WTC2 WTC1 WTC0 Interval time (*1) 0 0 0 31.25 ms 0 0 1 62.5 ms 0 1 0 125 ms 0 1 1 250 ms 1 0 0 500 ms 1 0 1 1.000 s 1 1 0 2.000 s 1 1 1 Setting is prohibited *1: Sub-clock: 32 kHz frequency divided by 4 (= 8 KHz) 216 CHAPTER 11 WATCH TIMER 11.2 Watch Timer Configuration The watch timer is composed of three blocks that include the following: • Interval selector • Watch counter • watch timer interrupt generating circuit • watch timer control register (WTC) ■ Block diagram of watch timer Figure 11.2-1 "Block diagram of watch timer" is a block diagram of the watch timer. Figure 11.2-1 Block diagram of watch timer Watch timer control register (WTC) WDCS Sub-clock SCE WTIE WTOF WTR Watch counter 212 213 214 WTC2 WTC1 WTC0 Clear 28 29 210 211 212 213 214 215 Interval selector Interrupt generating circuit Interrupt of watch timer To watchdog timer ❍ Watch counter This is a 15-bit up-counter that uses the sub-clock as the clock source. ❍ Interval selector This selector selects one of seven types of watch timer interrupt intervals. ❍ Interrupt generating circuit This circuit generates the interval interrupts of the watch timer. ❍ Watch timer control register (WTC) This register controls operation of the watch timer and watch timer interrupt, and it specifies the clock source for the watchdog timer. 217 CHAPTER 11 WATCH TIMER 11.3 Watch Timer Control Register (WTC) The watch timer control register (WTC) controls operation of the watch timer. This register also controls the time of interval interrupts. ■ Configuration of watch timer control register (WTC) Figure 11.3-1 "Configuration of watch timer control register (WTC)" shows the configuration of the watch timer control register (WTC), and Table 11.3-1 "Functions of bits in watch timer control register (WTC)" lists the functions of bits in the watch timer control register (WTC). Figure 11.3-1 Configuration of watch timer control register (WTC) Address bit15 0000AAH bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0 R/W R R/W R/W R/W R/W R/W WTC2 WTC1 WTC0 Initial value 10001000B R/W Watch timer interval selection bit Interval time (sub-block 32 KHz) 0 0 0 0 0 1 31.25 ms 62.5 ms 0 1 0 125 ms 0 1 1 0 1 0 250 ms 500 ms 1 0 1 1 1 0 1.000 s 2.000 s 1 1 1 Setting is prohibited WTR 0 1 WTOF 0 1 Watch counter clear bit All bits of the watch timer counter are cleared to "0." Nothing happens. This bit is always displayed during reading. Watch timer interrupt request flag bit No interrupt request is generated. An interrupt request is generated. Watch timer interval interrupt permit bit WTIE 0 Interrupt prohibited. 1 Interrupt permitted. SCE 0 1 R/W : Read/write enabled R : Read only : Default value 218 Bit indicating end of waiting time to stable oscillation of sub-clock The waiting time to stable oscillation is ongoing. The waiting time to stable oscillation has ended. Watchdog timer clock source selection bit WDCS 0 Select the clock for the watch timer 1 Select the clock for the timebase timer. CHAPTER 11 WATCH TIMER Table 11.3-1 Functions of bits in watch timer control register (WTC) Bit name Bit 7 WDCS: Watchdog timer clock source selection bit Function • • • • Bit 6 SCE: Bit indicating end of oscillation stabilization wait time of sub-clock • • • Bit 5 WTIE: Watch timer interval interrupt permit bit • • • • This bit is for selecting the clock source for the watchdog timer. If set to "0", this bit specifies clock for the watch timer; if set to "1", it specifies clock for the timebase timer. If the mode transits to the subclock mode with setting to "1", the watchdog timer stops. This bit is initialized to "1" by a reset. This bit indicates that the oscillation stabilization wait time of the subclock has ended. If set to "0", this bit indicates that the oscillation stabilization wait time of the sub-clock is ongoing. The oscillation stabilization wait time of the sub-clock is fixed at 214 cycles of the sub-clock. This bit is initialized to "0" by a power-on reset or stoppage. This bit is for permitting interval interrupts by the watch timer. If set to "1", this bit permits interrupts; if set to "0", it prohibits interrupts. This bit is initialized to "0" by a power-on reset • This bit indicates that an interrupt request by the watch timer has been issued. If this bit is set to "1" and the WTIE bit is set to "1", an interrupt request has been issued. This bit is set to "1" at each interval time specified by the WTC2-0 bits. This bit is cleared to "0" by writing "0", a transition to the stop mode, and a reset. Writing "1" to this bit has no effect. Bit 3 WTR: Watch counter clear bit • • • • This bit is for clearing all bits in the watch timer counter. Writing "0" to this bit clears the watch timer counter to "0". Writing "1" to this bit has no effect. During reading, "1" is always read and output. Bit 2 Bit 1 Bit 0 WTC2, WTC1, WTC0: Watch timer interval selection bits • • • These bits specify the interval of the watch timer. These bits are initialized to "000B" by a reset. When changing the bit settings, clear the WTOF bit at the same time. Bit 4 WTOF: Watch timer interrupt request flag bit • • • 219 CHAPTER 11 WATCH TIMER 11.4 Watch Timer Operation The watch timer functions as a clock source for the watchdog timer, timer for the oscillation stabilization wait time of the sub-clock, and interval timer to generate interrupts at fixed intervals. ■ Watch counter The watch counter is composed of a 15-bit counter to count the sub-clock, and it always continues counting as long as the sub-clock is input. ❍ Clearing the watch counter The operation of clearing the watch counter is affected by a power-on reset, a transition to the stop mode, and writing "0" to the watch counter clear bit (WTR) in the watch timer control register (WTC). Note: Clearing the clock counter affects the watchdog counter and interval interrupts that use clock timer output. To clear the clock timer by writing "0" to the WTR bit in the clock timer control register (WTC), set the WTIE bit to "0" and set the clock timer to interrupt inhibited state. Before permitting an interrupt, clear the interrupt request issued by writing "0" to the WTOF flag. ■ Interval interrupt function of watch timer This function generates interrupts at fixed intervals by using the carry signals of the watch counter. ❍ Specification of the interval time The interval time can be specified with the WTC2, WTC1, and WTC0 bits in the WTC register. ❍ Generation of watch timer interrupts The watch timer interrupt request flag bit (WTOF) is set to "1" at each interval time specified by the WTC2-0 bits. Consequently, when interrupts are permitted by setting the watch timer interval interrupt permit bit (WTIE) to "1", a watch timer interrupt occurs. The timing, when the WTOF bit is set, depends on the timing as a time reference when the watch timer was cleared for the last time. Because the watch timer is used as the timer for the oscillation stabilization wait time of the subclock after a transition to the stop mode, the WTOF bit is cleared immediately after the transition to this mode. ■ Clock source for watchdog timer specifying function The clock source for the watchdog timer can be specified with the watchdog timer clock source selection bit (WDCS) of the WTC register. If the sub-clock is used as the machine clock, set the WDCS bit to "0" and select the output of the watch timer. If the mode transits to the sub-clock mode with the WDCS bit setting to "1", the watchdog timer stops. 220 CHAPTER 11 WATCH TIMER ■ Sub-clock stable oscillation wait function For a power-on reset or restoration from the stop mode, the watch timer functions as the timer for the oscillation stabilization wait time of the sub-clock. The oscillation stabilization wait time of the sub-clock is fixed at 214 cycles of the sub-clock. 221 CHAPTER 11 WATCH TIMER 222 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER This chapter has an overview of the 16-bit input/output timer, describes the configuration and function of its register, and explains the operation of the timer. 12.1 "Overview" 12.2 "16-bit Input/Output Timer Register " 12.3 "16-bit Input/Output Timer Operation" 223 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.1 Overview The 16-bit input/output timer consists of one module of a 16-bit free-running timer, six modules of output compare and two modules of input capture. This function provides an output of six independent waveforms based on the 16-bit free-running time, enabling measurement of input pulse widths and external clock intervals. ■ Configuration and function of 16-bit input/output timer The 16-bit input/output timer consists of a 16-bit free-running timer, output compare and input capture, whose functions are explained below. ❍ 16-bit free-running timer (x 1) 16-bit free-running timer consists of 16-bit up-counter, control register and prescaler. The output of this timer counter is used as a base time (timebase timer) of input capture and output compare. The clock used for counter operation is selected from 8 types. (φ: machine clock) • Internal clock: 8 types (φ, φ/2, φ/4, φ/8, φ/16, φ/32, φ/64, φ/128) • The basic machine clock is selected from either an internal clock or external clock (FRCK). An interrupt is generated in the event of a counter overflow or a compare match between the output and the compare clear register (the compare match requires mode setting). The count value can be initialized to "0000H" in the event of a reset, clearing by software, or compare match with compare clear register 0. ❍ Output compare (x 6) Output compare consists of three 16-bit compare registers, a compare output latch, and a control register. If a 16-bit free-running timer and compare register have matching values, the output level is reversed with a generation of an interrupt. • Six compare registers operate independently. Each compare register has a corresponding output pin and interrupt flag. • Two compare registers are used as a pair to control the output pin. • Sets the output pin to its initial value. • An interrupt is generated by a compare match. ❍ Input capture (x 2) Input capture consists of two independent external input pins and corresponding capture registers and control registers. If an edge of a signal input from the external input pin is detected, the 16-bit free-running timer value is specified in the capture register and, at the same time, an interrupt is generated. • The edge of an external input signal can be selected from its rising edge and falling edge. • The two input capture operate independently. Interrupts occur at the valid edge of external input signals. Input capture can start DMAC by the interrupt. 224 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Block diagram Figure 12.1-1 "Block diagram of 16-bit input/output timer" is a block diagram of the 16-bit input/ output timer. Figure 12.1-1 Block diagram of 16-bit input/output timer To each block Control logic Interrupt 16-bit free-running timer 16-bit timer Clear Output compare 0 Compare register 0 TQ OUT0 TQ OUT1 TQ OUT2 TQ OUT3 TQ OUT4 TQ OUT5 Bus Output compare 1 Compare register 1 Output compare 2 Compare register 2 Output compare 3 Compare register 3 Output compare 4 Compare register 4 Output compare 5 Compare register 5 Input capture 0 Capture register 0 Edge selection IN0 Capture register 0 Edge selection IN1 225 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2 16-bit Input/Output Timer Register The 16-bit input/output timer registers are classified as follows: • 16-bit free-running timer • 16-bit output compare • 16-bit input capture This section shows the configuration and explains the functions of these registers. ■ Configuration of 16-bit input/output timer register The 16-bit input/output timer has the register configuration listed below. ❍ 16-bit free-running timer Figure 12.2-1 Configuration of 16-bit free-running timer 15 0 000066/67H CPCLR 000062/63H TCDT Timer data register 000064/65H TCCS Control status register Compare clear register ❍ 16-bit output compare Figure 12.2-2 Configuration of 16-bit output compare 00004A,4C,4E,50,52,54H 00004B,4D,4F,51,53,55H 15 000056,58,5AH 000057,59,5BH 0 OCCP0 OCS1/3/5 5 Compare register OCS0/2/4 Control status register ❍ 16-bit input capture Figure 12.2-3 Configuration of 16-bit input capture 00005C,5EH 00005D,5FH 000060H 226 15 0 IPCP0 1 Compare register ICS Control status register CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2.1 16-bit free-running timer The 16-bit free-running timer consists of a 16-bit up/down counter and control status register. The value of this timer counter is used as the base time (timebase timer) of input capture and output compare. • The clock used for counter operation can be selected out of 8 types. • A counter overflow interrupt may be generated. • By setting the mode, the counter is initialized if the output compare and the compare clear register have matching values. ■ List of 16-bit free-running timer registers Figure 12.2-4 "16-bit free-running timer registers" shows a list of the 16-bit free-running timer registers. Figure 12.2-4 16-bit free-running timer registers 000067H 000066H 000063H 000062H 000065H 000064H 15 CL15 (R/W) 7 CL07 (R/W) 15 T15 (R/W) 7 T07 (R/W) 15 ECKE (R/W) 7 IVF (R/W) 14 CL14 (R/W) 6 CL06 (R/W) 14 T14 (R/W) 6 T06 (R/W) 14 (R/W) 6 IVFE (R/W) 13 12 11 CL13 CL12 CL11 (R/W) (R/W) (R/W) 5 4 3 CL05 CL04 CL03 (R/W) (R/W) (R/W) 13 12 11 T13 T12 T11 (R/W) (R/W) (R/W) 5 4 3 T05 T04 T03 (R/W) (R/W) (R/W) 13 12 11 MSI2 MSI1 (R/W) (R/W) (R/W) 5 4 3 STOPMODE SCLR (R/W) (R/W) (R/W) 10 CL10 (R/W) 2 CL02 (R/W) 10 T10 (R/W) 2 T02 (R/W) 10 MSI0 (R/W) 2 CLK2 (R/W) 9 CL09 (R/W) 1 CL01 (R/W) 9 T09 (R/W) 1 T01 (R/W) 9 ICLR (R/W) 1 CLK1 (R/W) 8 CL08 (R/W) 0 CL00 (R/W) 8 T08 (R/W) 0 T00 (R/W) 8 ICRE (R/W) 0 CLK0 (R/W) CPCLR Compare clear register Initial value XXXXXXXXB CPCLR Compare clear register Initial value XXXXXXXXB TCDT Timer counter data register Initial value 00000000B TCDT Timer counter data register Initial value 00000000B TCCS Timer counter control/status register Initial value 0 - - 00000B TCCS Timer counter control/status register Initial value 00000000B 227 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Block diagram of 16-bit free-running timer Figure 12.2-5 "Block diagram of 16-bit free-running timer" is a block diagram of the 16-bit freerunning timer. Figure 12.2-5 Block diagram of 16-bit free-running timer φ Interrupt request Divider IVF STOP MODE SCLR CLK2 CLK1 IVF CLK0 Bus Clock 16-bit free-running timer 16-bit compare clear register Compare circuit Counter value output T15 to T00 ICLR MSI2 to 0 ICRE Interrupt request ■ Compare clear register (CPCLR) Figure 12.2-6 "Bit configuration of the compare clear register (CPCLR)" shows the bit configuration of the compare clear register (CPCLR). Figure 12.2-6 Bit configuration of the compare clear register (CPCLR) 15 000067H CL15 (R/W) 7 000066H CL07 (R/W) 14 CL14 (R/W) 6 CL06 (R/W) 13 12 CL13 CL12 (R/W) (R/W) 5 4 CL05 CL04 (R/W) (R/W) 11 CL11 (R/W) 3 CL03 (R/W) 10 CL10 (R/W) 2 CL02 (R/W) 9 CL09 (R/W) 1 CL01 (R/W) 8 CL08 (R/W) 0 CL00 (R/W) CPCLR Compare clear register Initial value XXXXXXXXB CPCLR Compare clear register Initial value XXXXXXXXB The compare clear register is a 16-bit compare register used to make a comparison with the 16bit free-run timer. An initial value of a register value is undefined. Therefore, set the initial value, then allow the activation. This register requires word access. When this register value matches the value of the 16-bit free-run timer, the 16-bit free-run timer value is initialized to 0000H and a compare clear interrupt flag is set. When interrupt operation is allowed, an interrupt request is issued to the CPU. 228 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Timer counter data register (TCDT) Timer counter data register (TCDT) has the bit configuration shown below. Figure 12.2-7 Bit configuration of timer counter data register (TCDT) 000063H 000062H 15 T15 (R/W) 7 T07 (R/W) 14 T14 (R/W) 6 T06 (R/W) 13 12 T13 T12 (R/W) (R/W) 5 4 T05 T04 (R/W) (R/W) 11 T11 (R/W) 3 T03 (R/W) 10 T10 (R/W) 2 T02 (R/W) 9 T09 (R/W) 1 T01 (R/W) 8 T08 (R/W) 0 T00 (R/W) TCDT Timer counter data register Initial value 00000000B TCDT Timer counter data register Initial value 00000000B The timer counter data register (TCDT) is used to read the value of the 16-bit free-running timer counter. The counter value is cleared to "0000" by a reset. Writing to this register must be performed in the stopped (STOP = 1) state, and the written value defines the timer value. This register requires word access. The 16-bit free-running timer is initialized with the following causes: • Reset • Control status: clear bit (CLR) • Matching between the compare clear register of output compare and timer counter value (requiring mode setting). ■ Timer counter control status register (TCCS) Timer counter control status register (TCCS) has the bit configuration shown below. Figure 12.2-8 Bit configuration of timer counter control status register (TCCS) 15 14 13 12 000065H ECKE MSI2 (R/W) (R/W) (R/W) (R/W) 7 6 5 4 000064H IVF IVFE STOP MODE (R/W) (R/W) (R/W) (R/W) 11 MSI1 (R/W) 3 SCLR (R/W) 10 MSI0 (R/W) 2 CLK2 (R/W) 9 ICLR (R/W) 1 CLK1 (R/W) 8 ICRE (R/W) 0 CLK0 (R/W) TCCS Timer counter control/status register Initial value 0--00000B TCCS Timer counter control/status register Initial value 00000000B Timer counter control status register (TCCS) consists of bits that have the functions explained below. [Bit 15] ECKE This bit is used to select whether the count clock source of the 16-bit free-running timer is internal or external. Since the clock is changed soon after being written to this bit, change the bit setting when output compare and input capture are in the stopped state. 0 Internal clock source is selected (initial value) 1 Clock is input from external pin (FRCK) [Bits 14,13] Unused bits These bits are not used. 229 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [Bits 12, 11, 10] MSI2, MSI1, MSI0 These bits specify the count with which a compare clear interrupt is masked. It consists of 3bit reload counter that reloads the count value every time the counter value reaches "000B". During writing to this register, the count value is also loaded, where mask count = specified count (e.g., set to "010B" when masked twice and the third time is interrupted). However, if "000B" is set, no interrupt cause is masked. [Bit 9] ICLR This bit is the interrupt request flag for compare clear. If the compare clear register and 16bit free-running timer are found to have matching values by compare and the counter is cleared, this bit is set to "1". If the interrupt request permit bit (bit 8: ICRE) is set, an interrupt occurs. This bit is cleared by writing "0". Writing "1" has no effect. An instruction of the readmodify-write type always reads "1". 0 No interrupt request issued (initial value) 1 Interrupt request issued [Bit 8] ICRE This bit is the interrupt permit bit for compare clear. If this bit is set to "1" and the interrupt flag (bit 9: ICLR) is set to "1", then an interrupt occurs. 0 Interrupt prohibited (initial value) 1 Interrupt permitted [Bit 7] IVF This bit is the interrupt request flag of the 16-bit free-running timer. If the 16-bit free-running timer causes an overflow or mode setting results in a match between the compare clear register and compare results so that the counter is cleared, then the IVF bit is set to "1". If the interrupt request permit bit (bit 5: IVFE) is set, an interrupt occurs. This bit is cleared by writing "0". Writing "1" has no effect. An instruction of the read-modify-write type reads "1". 0 No interrupt request used (initial value) 1 Interrupt request used [Bit 6] IVFE This bit is the interrupt permit bit for the 16-bit free-running timer. If this bit is set to "1" when the write flag (bit 5: IVF) is set to "1", an interrupt occurs. 230 0 Interrupt prohibit (initial value) 1 Interrupt permit CHAPTER 12 16-BIT INPUT/OUTPUT TIMER [Bit 5] STOP This bit is for stopping the counting by the 16-bit free-running timer. If this bit is set to "1", the timer stops counting, and if it is set to "0", the timer starts counting. 0 Count permit (operation) (initial value) 1 Count prohibit (stop) If the 16-bit free-running timer stops counting, the output compare operation also stops. [Bit 4] MODE This bit specifies the initialize conditions of the 16-bit free-running timer. If set to "0", the reset and clear bit (bit 3: SCLR) initializes the count value. If set to "1", the reset and clear bit (bit 3: SCLR), in addition to matching with the compare clear register (CPCLR) value of the 16-bit free-running timer, initializes the counter value. 0 Initialized by reset and clear bit (initial value) 1 Initialized by reset, clear bit, and compare clear register The counter value initialization occurs at the point the counter value changes. [Bit 3] SCLR This bit is for initializing the value of the 16-bit free-running timer in operation to "0000". Writing "1" initializes the counter value to "0000". Writing "0" has no effect. The read value is always "0". The counter value initialization occurs at the point the counter value changes. 0 No effect (initial value) 1 Initializes the counter value to "0000" If it is initialized, write "0000" to the data register when the timer stops. [Bits 2, 1, 0] CLK2, CLK1, CLK0 These bits are used to select the count clock of the 16-bit free-running timer. Since the clock changes after this bit is written, change the bit setting when output compare and input capture are in the stopped state. CLK2 CLK1 CLK0 Count clock φ = 20MHz φ = 16MHz φ = 8MHz φ = 4MHz φ = 1MHz 0 0 0 φ 50 ns 6.25 ns 0.125 µs 0.25 µs 1.0 µs 0 0 1 φ/2 100 ns 0.125 µs 0.25 µs 0.5 µs 2.0 µs 0 1 0 φ/4 0.2 µs 0.25 µs 0.5 µs 1.0 µs 4.0 µs 0 1 1 φ/8 0.4 µs 0.5 µs 1.0 µs 2.0 µs 8.0 µs 1 0 0 φ/16 0.8 µs 1.0 µs 2.0 µs 4.0 µs 16.0 µs 1 0 1 φ/32 1.6 µs 2.0 µs 4.0 µs 8.0 µs 32.0 µs 1 1 0 φ/64 3.2 µs 4.0 µs 8.0 µs 16.0 µs 64.0 µs 1 1 1 φ/128 6.4 µs 8.0 µs 16.0 µs 32.0 µs 128.0 µs 231 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2.2 Output compare Output compare consists of a 16-bit compare register, compare output pin section, and control register. If the compare register of this module and the 16-bit free-running timer have matching values, the output level of the pin may be reversed and an interrupt may be generated. • A total of six compare registers are provided, and each operates independent of the other. With their settings, the two compare registers are used to control output. • Interrupt can be specified with compare matching. ■ List of output compare registers Figure 12.2-9 "Registers of output compare" shows a list of the registers of output compare. Figure 12.2-9 Registers of output compare 00004BH 00004DH 15 14 13 12 11 10 9 8 OCCP0 to 5 00004FH C15 C14 C13 C12 C11 C10 C09 C08 Compare register 000051H 000053H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXXB 000055H 00004AH 00004CH 7 6 5 4 3 2 1 0 OCCP0 to 5 00004EH C07 C06 C05 C04 C03 C02 C01 C00 Compare register 000050H 000052H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXXB 000054H 000057H 000059H 00005BH 15 (-) 14 (-) 13 (-) 12 11 10 9 8 OCS1/3/5 CMOD OTE1 OTE0 OTD1 OTD0 Control register (R/W) (R/W) (R/W) (R/W) (R/W) Initial value ---00000B 7 6 5 4 000056H 000058H ICP1 ICP0 ICE1 ICE0 00005AH (R/W) (R/W) (R/W) (R/W) 3 (-) 2 (-) 1 0 OCS0/2/4 CST1 CST0 Control register (R/W) (R/W) Initial value 0000--00B Note: To rewriting the compare register, within the compare interrupt routine or compare operation is disabled. Be sure not to occur simultaneously a compare match and writing the compare register. 232 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Block diagram of output compare Figure 12.2-10 "Block diagram of output compare" is a block diagram of output compare. Figure 12.2-10 Block diagram of output compare 16-bit timer counter value (T15 to T00) Compare control TQ OTE0 OUT0 (2) (4) OTE1 OUT1 (3) (5) Bus Compare register 0 (2) (4) 16-bit timer counter value (T15 to T00) CMOD TQ Compare control Compare register 1 (3) (5) ICP1 ICP0 ICE0 ICE0 Control section Control blocks Compare 1 (3) (5) interrupt Compare 0 (2) (4) interrupt ■ Compare register (OCCP0 to 5) Compare register (OCCP0 to 5) has the bit configuration shown below. Figure 12.2-11 Bit configuration of compare register (OCCP0 to 5) 00004BH 00004DH 15 14 13 12 11 10 9 8 OCCP0 to 5 00004FH C15 C14 C13 C12 C11 C10 C09 C08 Compare register 000051H 000053H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXXB 000055H 00004AH 00004CH 7 6 5 4 3 2 1 0 OCCP0 to 5 00004EH C07 C06 C05 C04 C03 C02 C01 C00 Compare register 000050H 000052H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value XXXXXXXXB 000054H The compare register (OCCP0 to 5) is a 16-bit register used to comparison with the 16-bit freerunning timer. The register has unspecified initial values, thus the start of operation must be enabled after the values are specified. This register uses word access. If this register and the 16-bit free-running timer have matching values, a compare signal is generated to set the output compare interrupt flag. If output enable is given, the output level corresponding to the compare register is reversed. 233 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Control register (OCS0 to 5) Control register (OCS0 to 5) has the bit configuration shown below. Figure 12.2-12 Bit configuration of control register (OCS0 to 5) 000057H 000059H 00005BH 15 (-) 14 (-) 13 (-) 12 11 10 9 8 OCS1/3/5 CMOD OTE1 OTE0 OTD1 OTD0 Control register (R/W) (R/W) (R/W) (R/W) (R/W) Initial value ---00000B 7 6 5 4 000056H 000058H ICP1C ICP0 ICE1 ICE0 00005AH (R/W) (R/W) (R/W) (R/W) 3 (-) 2 (-) 1 0 OCS0/2/4 CST1 CST0 Control register (R/W) (R/W) Initial value 0000--00B Control register (OCS0 to 5) consists of bits that have the functions explained below. [Bits 15, 14, 13] Unused bits These bits are not used. They are always set to "0". [Bit 12] CMOD This bit is for switching the pin output level reverse operation in compare matching if pin output is permitted (OTE = 1 or OTE0 = 1). • If CMOD = 0 (initial value), the level corresponding to the compare register is reversed. - OUT0/2/4: Level is reversed if a match for compare register 0/2/4 is found - OUT1/3/5: Level is reversed if a match for compare register 1/3/5 is found • If CMOD = 1, compare register 0 reverses the output level where CMOD = 0, although the pin (OUT1) output level corresponding to compare register 1 reverses the output level only when both of compare register 0 and compare register 1 have a respective match. If compare registers 0 and 1 have the same value, the operation is the same as that for one compare register. - OUT0/2/4: Level is reversed if a match for compare register 0/2/4 is found - OUT1/3/5: Level is reversed if a match for compare register 1/3/5 is found [Bits 11, 10] OTE1, OTE0 These bits permit pin output of output compare. This bit takes an initial value of "0". 0 General-purpose support (initial value) 1 Pin output of output compare • OTE1: Corresponds with output compare 1/3/5 • OTE0: Corresponds with output compare 0/2/4 [Bits 9, 8] OTD1, OTD0 These bits change the pin output level if pin output of output compare is permitted. The initial value of compare pin output is set to "0". A write operation is performed after the compare operation stops. In a read operation, the output value of the output compare pin is read. 234 0 Compare pin output set to "0" (initial value) 1 Compare pin output set to "1" CHAPTER 12 16-BIT INPUT/OUTPUT TIMER • OTD1: Corresponds to output compare 1/3/5 • OTD0: Corresponds to output compare 0/2/4 [Bits 7, 6] ICP1, ICP0 These bits are the interrupt flags for output compare. Set them to "1" if the compare register and 16-bit free-running timer have matching values. If the interrupt request bit (ICE1, ICE0) is set to "enabled", an output compare interrupt occurs. This bit is cleared if "0" is written. Writing "1" has no effect. An instruction of the read-modify type only reads "1". 0 No compare match (initial value) 1 Compare match • ICP1: Corresponds to output compare 1/3/5 • ICP0: Corresponds to output compare 0/2/4 [Bits 5, 4] ICE1, ICE0 These bits are the interrupt permit bits of output compare. If these bits are set to "1" and an interrupt flag (ICP1, ICP0) is set, an output compare interrupt occurs. 0 Output compare interrupt prohibit (initial value) 1 Output compare interrupt permit • ICE1: Corresponds to output compare 1/3/5 • ICE0: Corresponds to output compare 0/2/4 [Bits 3, 2] Unused bits These bits are not used. [Bits 1, 0] CST1, CST0 These bits permit a matching operation with the 16-bit free-running timer. 0 Compare operation prohibit (initial value) 1 Compare operation permit • CST1: Corresponds to output compare 1/3/5 • CST0: Corresponds to output compare 0/2/4 Before a compare operation is permitted, specify the compare register value. Note: Output compare operates in sync with the 16-bit free-running timer clock. Thus, if the 16-bit free-running timer stops, the compare operation also stops. 235 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.2.3 Input capture This module has a function for detecting a rising edge, a falling edge, and both edges of an externally input signal and for saving the 16-bit free-running timer value to a register. When an edge is detected, an interrupt may be generated. ■ Input capture Input capture consists of an input capture register and control register. Each input capture has the corresponding external input pin. • The valid edge of external input is selected from among 3 types: rising edge, falling edge, and both edges. • If a valid edge of the external input is detected, an interrupt may occur. ■ Block diagram of input capture Figure 12.2-13 "Block diagram of input capture" is a block diagram of input capture. Figure 12.2-13 Block diagram of input capture Edge detect Capture data register 0 EG11 EG10 EG01 EG00 Bus 16-bit timer counter value (T15 to T00) IN0 Edge detect Capture data register 1 ICP1 ICP0 ICE1 IN1 ICE0 Interrupt Interrupt 236 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ List of input capture registers Figure 12.2-14 "Input capture registers" shows a list of the input capture registers. Figure 12.2-14 Input capture registers 15 14 13 12 11 10 9 8 00005DH CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 00005FH (R) (R) (R) (R) (R) (R) (R) (R) IPCP0, 1 Input capture data register Initial value XXXXXXXXB 7 6 5 4 3 2 1 0 00005CH 00005EH CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 (R) (R) (R) (R) (R) (R) (R) (R) IPCP0, 1 Input capture data register Initial value XXXXXXXXB 7 6 5 4 3 2 1 0 ICS01 000060H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Control status register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B ■ Input capture data register (IPCP0, 1) The input capture data register (IPCP0, 1) has the bit configuration shown below. Figure 12.2-15 Bit configuration of input capture data register (IPCP0, 1) 15 14 13 12 11 10 9 8 00005DH 00005FH CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (R) (R) (R) (R) (R) (R) (R) (R) IPCP0, 1 Input capture data register Initial value XXXXXXXXB 7 6 5 4 3 2 1 0 00005CH CP07 CP06 CP05 CP04 CP03 CP02 CP01 CP00 00005EH (R) (R) (R) (R) (R) (R) (R) (R) IPCP0, 1 Input capture data register Initial value XXXXXXXXB The input capture data register (IPCP0, 1) is a register containing the 16-bit free-running timer value when a valid edge of the external pin input waveform is detected. This register uses word access. Writing to this register is not permitted. 237 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ■ Control status register (ICS01) The control status register (ICS01) has the bit configuration shown below. Figure 12.2-16 Bit configuration of control status register (ICS01) 7 6 5 4 3 2 1 0 ICS01 000060H ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00 Control status register (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B The control status register (ICS01) consists of bits that have the functions explained below. [Bits 7, 6] ICP1, ICP0 These bits are the interrupt flags of input capture. When a valid edge of the external input pin is detected, this bit is set to "1". If the interrupt permit bit (ICE1, ICE0) is set, an interrupt may occur when a valid edge is detected. This bit is cleared when "0" is written. Writing "1" has no effect. An instruction of the readmodify-write type always reads "1". 0 No valid edge detected (initial value) 1 Valid edge detected • ICP1: Corresponds to input capture 1 • ICP0: Corresponds to input capture 0 [Bits 5, 4] ICE1, ICE0 These bits are used as the interrupt permit bits of input capture. If this bit is set to "1" and the interrupt flag (ICP1, ICP0) is set, then an input capture interrupt occurs. 0 Interrupt prohibit (initial value) 1 Interrupt permit • ICE1: Corresponds to input capture 1 • ICE0: Corresponds to input capture 0 [Bits 3, 2, 1, 0] EG11, EG10, EG01, EG00 These bits specify the valid edge polarity of external input. Also, they are used to specify the enable of input capture operations. 238 EG11/EG01 EG10/EG00 Edge detect polarity 0 0 No edge detected (stop state) (initial value) 0 1 Rising edge detected 1 0 Falling edge detected 1 1 Both edges detected • EG11/EG10: Corresponds to input capture 1 • EG01/EG00: Corresponds to input capture 0 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3 16-bit Input/Output Timer Operation This section explains the operation and timing of the 16-bit input/output timer. ■ Operation and timing of 16-bit input/output timer The 16-bit input/output timer handles the operation and timing for the following items: • 16-bit free-running timer operation • 16-bit output compare operation • 16-bit input capture operation • 16-bit free-running timer timing • • • Count timing • Clear timing Output compare timing • Compare operation timing • Interrupt timing • Change timing of the output pin Timing of input capture • Capture timing to the input signal 239 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.1 Operation of 16-bit free-running timer This section explains the operation and timing of the 16-bit free-running timer. ■ Operation of 16-bit free-running timer The 16-bit free-running timer starts counting at a counter value of "0000" after a reset operation is cleared. This counter value is used as a reference time for 16-bit output compare and 16-bit input capture. The count value is cleared by a clear operation under the following conditions: • Overflow occurs • Compare match is found with the output compare value 0 (mode setting is required) • TCCS register CLR bit is set to "1" during operation • TCDC register is set to "0000" during operation • Reset occurs An interrupt occurs if an overflow is generated or if the value of compare register 0 matches compare results, causing clearing of the count value (a compare results match interrupt requires mode setting) Figure 12.3-1 "Timing chart of counter cleared because of overflow" shows the timing chart of the counter cleared because of an overflow. Figure 12.3-2 "Timing chart of counter cleared because of compare results match" shows the timing chart of the counter cleared because of a compare results match. Figure 12.3-1 Timing chart of counter cleared because of overflow Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Interrupt 240 Time CHAPTER 12 16-BIT INPUT/OUTPUT TIMER Figure 12.3-2 Timing chart of counter cleared because of compare results match Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare register value Time BFFFH Interrupt 241 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.2 Operation of 16-bit output compare 16-bit output compare compares the specified compare register value with the 16-bit free-running timer value, and if they match, it sets an interrupt request flag and reverses the output level. ■ Examples of output waveform Examples of output waveform are shown below. ❍ Example of output waveform where compare registers 0 and 1 are used Figure 12.3-3 "Example of output waveform where compare registers 0 and 1 are used (initial value of output = "0")" shows an example of output waveform where the initial value of output is specified as "0". Figure 12.3-3 Example of output waveform where compare registers 0 and 1 are used (initial value of output = "0") Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value Time BFFFH 7FFFH OUT0 OUT1 Compare 0 interrupt Compare 1 interrupt Two pairs of compare register may be used to change the output level (if CMOD = 1). 242 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER ❍ Example of output waveform from two pairs of compare registers Figure 12.3-4 "Example of output waveform from two pairs of compare registers (initial value of output = "0"" shows an example of output waveform where the initial value of output is specified as "0". Figure 12.3-4 Example of output waveform from two pairs of compare registers (initial value of output = "0") Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Reset Compare register 0 value Compare register 1 value Time BFFFH 7FFFH OUT0 Corresponding to compare 0 OUT1 Corresponding to compare 1 Compare 0 interrupt Compare 1 interrupt Note: To rewriting the compare register, within the compare interrupt routine or compare operation is disabled. Be sure not to occur simultaneously a compare match and writing the compare register. 243 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.3 Operation of 16-bit input capture 16-bit input capture is used to generate interrupts by reading and storing the 16-bit free-running timer value into the capture register if the specified edge is detected as being valid. ■ Example of input capture timing Figure 12.3-5 "Example of input capture timing" shows an example of input capture timing Figure 12.3-5 Example of input capture timing Counter value FFFFH BFFFH 7FFFH 3FFFH 0000H Time Reset IN0 IN1 Example of IN Capture 0 Unspecified 3FFFH 7FFFH Capture 1 Unspecified Example of capture Capture 0 interrupt Capture 1 interrupt Example-of-capture interrupt 244 Unspecified BFFFH 7FFFH CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.4 16-bit free-running timer timing The 16-bit free-running timer is incremented according to the timing of input clock (internal or external clock). If an external clock is selected, counting is performed at the rising edge. ■ Count timing of free-running timer Figure 12.3-6 "Count timing of free-running time" shows the count timing of the free-running timer. Figure 12.3-6 Count timing of free-running timer φ External clock input Count clock N Counter value N+1 The counter is cleared by either a reset, software, or a match with compare register 0. Counter clear by a reset or software occurs when a clear operation is performed. Counter clear because of a match with compare register 0 occurs in sync with count timing. ■ Clear timing of free-running timer (match with compare register 0) Figure 12.3-7 "Clear timing of free-running timer (match with compare register 0)" shows the clear timing of the free-running timer caused by a match with compare register 0. Figure 12.3-7 Clear timing of free-running timer (match with compare register 0) φ N Compare register value Compare match Counter value N 0000 245 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.5 Output compare timing The output compare timing is used to issue compare match signals when the freerunning timer and the compare register have matching values, to reverse the output value, and to generate interrupts. Output reverse timing at the compare match is in sync with the counter timing. ■ Interrupt timing Figure 12.3-8 "Interrupt timing of output compare" shows the interrupt timing of output compare. Figure 12.3-8 Interrupt timing of output compare φ Counter value N Compare register value N N+1 Compare match Compare match ■ Change timing of output pin Figure 12.3-9 "Change timing of output pin for output compare" shows the change timing of the output pin for output compare. Figure 12.3-9 Change timing of output pin for output compare Counter value Compare register value N N+1 N N+1 N Compare match signal Output pin Note: To rewriting the compare register, within the compare interrupt routine or compare operation is disabled. Be sure not to occur simultaneously a compare match and writing the compare register. 246 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 12.3.6 Timing of input capture This section describes a capture timing of the input signal for capture. ■ Capture timing to input signal Figure 12.3-10 "Capture timing of input signal for input capture" shows the capture timing of input signal for input capture. Figure 12.3-10 Capture timing of input signal for input capture φ Counter value Input capture N N+1 Valid edge Capture signal Capture register N+1 Interrupt 247 CHAPTER 12 16-BIT INPUT/OUTPUT TIMER 248 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER This chapter has an overview of the 8/16-bit up/down counter/timer, describes the configuration and functions of its registers, and explains the operation of the 8/16-bit up/down counter/timer. 13.1 "Overview" 13.2 "Registers for 8/16-bit Up/Down Counter/Timer " 13.3 "8/16-bit Up/Down Counter/Timer Operation" 249 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.1 Overview The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, eight bit reload/compare registers, and their control circuits. ■ Major functions of 8/16-bit up/down counter/timer • 8-bit count register used for counting in a range of 0 to 256 (in the 16 bits x one operation mode, counting in a range of 0 to 65535 is possible). • Four types of count modes can be selected for the count clock. • • Timer mode • Up/down count mode • Phase difference decremented mode (two times) • Phase difference decremented mode (eight times) In the timer mode, the count clock (for 16 MHz) is selected from two types of internal clocks: • 125 ns (8 MHz: frequency divided by 2) • 0.5 µs (2 MHz: frequency divided by 8) In the up/down count mode, a detect edge of the external pin input signal may be selected: • Falling edge detect • Rising edge detect • Both falling and rising edges • Edge detect prohibited • The phase difference count mode is suitable for counting encoder output such as motor, where encoder output from phases A, B, and C is used as input, thereby facilitating highprecision counting of rotation angle and rotations. • The ZIN pin is used to select from two types of functions: • 250 • • Counter clear function • Gate function Compare and reload functions are provided, where each function or a combination of them are available. Starting both functions allows up/down counting with any time width. • Compare function (an interrupt is issued during compare) • Compare function (an interrupt is issued and the counter is cleared during compare) • Reload function (an interrupt is issued and reloaded during compare) • Compare and reload functions (an interrupt is issued and the counter is cleared during compare, and an interrupt is issued and reloaded when an underflow occurs) • Compare and reload prohibited • Interrupt generation is controlled individually during compare, a reload (underflow), or an overflow. • The count direction flag identifies the count direction of the last counter operation CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER • An interrupt occurs when the count direction is switched ■ Block diagram of 8/16-bit up/down counter/timer Figure 13.1-1 "Block diagram of 8/16-bit up/down counter/timer (channel 0)" and Figure 13.1-2 "Block diagram of 8/16-bit up/down counter/timer (channel 1)" are block diagrams of the 8/16-bit up/down counter/timer. Figure 13.1-1 Block diagram of 8/16-bit up/down counter/timer (channel 0) Data bus 8 bits CGE1 ZIN0 CGE0 CGSC Edge/level detected RCR0 (reload/compare register 0) CTUT Reload control UCRE UDCC RLDE Counter clear 8 bits UDCR0 (up/down count register 0) Carry CMPF CES1 CES0 UDFF OVFF CMS1 CMS0 Count clock UDMS AIN0 BIN0 CITE UDIE Up/down count clock selection UDF1 UDF0 CDCF CFIE Prescaler CSTR Interrupt output CLKS 251 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER Figure 13.1-2 Block diagram of 8/16-bit up/down counter/timer (channel 1) Data bus 8 bits CGE1 ZIN1 CGE0 CGSC Edge/level detected RCR1 (reload/compare register 1) CTUT Reload control UCRE UDCC RLDE Counter clear 8 bits UDCR1 (up/down count register 1) CMPF UDFF OVFF CMS1 CMS0 CES1 CES0 M16E UDMS CITE UDIE Carry AIN1 BIN1 Count clock Up/down count clock selection Prescaler CLKS 252 UDF1 UDF0 CDCF CFIE CSTR Interrupt output CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2 Registers for 8/16-bit Up/Down Counter/Timer This section shows the configuration and explains the function of the 8/16-bit up/down counter/timer. ■ List of 8/16-bit up/down counter/timer registers Figure 13.2-1 "Registers for 8/16-bit up/down counter/timer" shows a list of registers for the 8/ 16-bit up/down counter/timer. Figure 13.2-1 Registers for 8/16-bit up/down counter/timer 15 87 0 UDCR1 RCR1 Reserve area CCRH 0 Reserve area CCRH 1 UDCR 0 RCR 0 CSR 0 CCRL 0 CSR 1 CCRL 1 8 bits 8 bits 7 UDCR 0 Address: 000068H D07 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00 Initial value 00000000B 15 UDCR 1 Address: 000069H D17 14 D16 13 D15 12 D14 11 D13 10 D12 9 D11 8 D10 Initial value 00000000B 7 RCR 0 D07 Address: 00006AH 6 D06 5 D05 4 D04 3 D03 2 D02 1 D01 0 D00 Initial value 00000000B 15 RCR 1 D17 Address: 00006BH 14 D16 13 D15 12 D14 11 D13 10 D12 9 D11 8 D10 Initial value 00000000B CSR0 7 6 5 4 3 2 1 0 Initial value Address: 000072H CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 00000000B CSR 1 Address: 000074H CCRL0 7 6 5 4 3 2 1 0 Address: 00006CH UDMS CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 CCRL1 Address: 000070H Initial value 0X00X000B 15 14 13 12 11 10 9 8 CCRH0 M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Address: 00006DH Initial value 00000000B CCRH1 Address: 000071H 15 - 14 13 12 11 10 9 8 CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 Initial value -0000000B 253 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.1 Counter control register H0 (CCRH0) This section shows the configuration and explains the function of counter control register H0 (CCRH0). ■ Counter control register H0 (CCRH0) The bit configuration of counter control register H0 (CCRH0) is shown below. Figure 13.2-2 Bit configuration of counter control register H0 (CCRH0) Bit 15 14 13 12 11 10 9 8 CCRH0 Address: 00006DH M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value 00000000B Counter control register H0 (CCRH0) consists of bits that have the functions explained below. [Bit 15] M16E (16-bit mode permit) This bit is used to select (switch) an operation mode of 8 bits x 2 channels or 16 bits x 1 channel. M16E Setting 16-bit mode permit 0 8 bits x 2 channels operation mode (initial value) 1 16 bits x 1 channel operation mode If this bit is rewritten after its start, the count value is not assured. [Bit 14] CDCF (count direction reversal flag) This bit is a flag that is set when the count direction is switched. It is set in the count start mode when the count direction is switched from either up to down or down to up. Only writing "0" is permitted, and "1" cannot be written. Read-modify-write type instructions return "1" irrespective of bit values. CDCF Direction reversal detection 0 No reversal of direction (initial value) 1 One or more reversals of direction [Bit 13] CFIE (count direction reversal interrupt enable) If CDCF is defined, this bit is used to control interrupt output to the CPU. An interrupt is generated if count direction changes even a single time in the count start mode. CFIE 254 Direction reversal interrupt output 0 Direction reversal interrupt output prohibit (initial value) 1 Direction reversal interrupt output permit CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 12] CLKS (built-in prescaler select) This bit is used to select the frequency of a built-in prescaler in the selection of the timer mode. It is valid in the timer mode, and only decrementing (down count) is permitted. CLKS Internal clock selected 0 2 machine cycles (initial value) 1 8 machine cycles If this bit is rewritten after its start, the count value is not assured. [Bits 11 to 10] CMS1, CMS0 (count mode selection) These bits are used to select the count mode. CMS1 CMS0 Count mode 0 0 Timer mode [decremented] (initial value) 0 1 Up/down count mode 1 0 Phase difference count mode: frequency multiplied by 2 1 1 Phase difference count mode: frequency multiplied by 4 If this bit is rewritten after its start, the count value is not assured. [Bits 9 to 8] CES1, CES0 (count clock edge selection) These bits are used to select the detect edge of external pins AIN and BIN in the up/down count mode. This setting is invalid in modes other than up/down count. CES1 CES0 Selected edge 0 0 Edge detect prohibit (initial value) 0 1 Falling edge detect 1 0 Rising edge detect 1 1 Both rising and falling edges detected If this bit is rewritten after its start, the count value is not assured. 255 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.2 Counter control register H1 (CCRH1) This section describes the configuration and explains the function of counter control register H1 (CCRH1). ■ Counter control register H1 (CCRH1) The bit configuration of the counter control register H1 (CCRH1) is shown below. Figure 13.2-3 Bit configuration of counter control register H1 (CCRH1) Bit CCRH1 Address: 000071H 15 - 14 13 12 11 10 9 8 CDCF CFIE CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W R/W R/W Initial value -0000000B Counter control register H1 (CCRH1) consists of bits that have the functions explained below. [Bit 14] CDCF (count direction reversal flag) This bit is set when the count direction changes. It is set in the count start mode when the count direction changes from up to down or from down to up. Only writing "0" is permitted, and "1" cannot be written. Read-modify-write type instructions return "1" irrespective of bit values. CDCF Direction reversal detection 0 No direction reversals (initial value) 1 One or more reversals of direction [Bit 13] CFIE (count direction reversal interrupt enable) This bit is used to control interrupt output if CDCF is defined. It generates an interrupt in the count start mode when the count direction changes. CFIE 256 Direction reversal interrupt output 0 Direction reversal interrupt output prohibit (initial value) 1 Direction reversal interrupt output permit CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 12] CLKS (built-in prescaler selection) This bit is used to select the frequency of the built-in prescaler when the timer mode is selected. This is only valid in the timer mode, where only decrementing is permitted. CLKS Selection internal clock 0 2 machine cycles (initial value) 1 8 machine cycles If this bit is rewritten after its start, the count value is not assured. [Bits 11 to 10] CMS1, CMS0 (count mode selection) These bits are used to select the count mode. CMS1 CMS0 Count mode 0 0 Timer mode [decremented] (initial value) 0 1 Up/down count mode 1 0 Phase difference count mode: frequency multiplied by 2 1 1 Phase difference count mode: frequency multiplied by 4 If this bit is rewritten after its start, the count value is not assured. [Bits 9 to 8] CES1, CES0 (count clock edge selection) These bits are used in the up/down count mode to detect a detect edge for external pins AIN and BIN. This setting is invalid in modes other than up/down count. CES1 CES0 Selected edge 0 0 Edge detect prohibit (initial value) 0 1 Falling edge detect 1 0 Rising edge detect 1 1 Both rising and falling edges detected If this bit is rewritten after its start, the count value is not assured. 257 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.3 Counter control register L0/1 (CCRL0/1) This section describes the configuration and explains the function of counter control register L0/1 (CCRL0/1). ■ Counter control register L0/1 (CCRL0/1) The bit configuration of counter control register L0/1 (CCRL0/1) is shown below. Figure 13.2-4 Bit configuration of counter control register L0/1 (CCRL0/1) Bit 7 6 5 4 3 2 1 0 CCRL0 Address: 00006CH UDMS CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 CCRL1 W R/W R/W W R/W R/W R/W Address: 000070H R/W Initial value 0X00X000B Counter control register L0/1(CCRL0/1) consists of bits that have the functions explained below. [Bit 7] UDMS (up/down counting mode selection) This bit is used to control the up/down counting at the falling edge of the BIN pin in the phase difference counter mode at frequency multiplied by 2. It is initialized to "0" by a reset. Read and write operations are possible. UDMS Operation 0 Decremented if the AIN pin value detected at the falling edge of the BIN pin is "H" (initial value) Incremented if AIN pin value detected at the BIN pin is "L" (initial value) 1 Decremented if the AIN pin value detected at the falling edge of the BIN pin is "L" Incremented if the AIN pin value detected at the falling edge of the BIN pin is "H" If this bit is rewritten after its start, the count value is not assured. [Bit 6] CTUT (counter write) This bit is used for transfers from RCR to UDCR. If this bit is set to "1", data is transferred from RCR to UDCR. Writing "0" has no effect. [Bit 5] UCRE (UDCR clear enable) This bit is used to control UDCR clear caused by compare. This does not affect the UDCR clear function (such as caused by the ZIN pin setting) other than clear because of compare generation. UCRE 258 Counter clear caused by compare 0 Counter clear prohibit (initial value) 1 Counter clear permit CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 4] RLDE (reload enable) This bit is used to control the start of the reload function. The RCR value is transferred to UDCR if an underflow occurs when the reload function starts. RLDE Reload function 0 Reload function prohibit (initial value) 1 Reload function permit [Bit 3] UDCC (UDCR clear) This bit is used to clear UDCR. Writing "0" to this bit clears UDCR to "0000H". Writing "1" has no effect. [Bit 2] CGSC (counter clear/gate selection) This bit is used to select a function of external pin ZIN. CGSC ZIN function 0 Count clear function (initial value) 1 Gate function [Bit 1 to 0] CGE1, CGE0 (counter clear/gate edge selection) These bits are used to select a detect edge/level for external pin ZIN. CGE1 CGE0 For selecting the counter clear function For selecting the gate function 0 0 Edge detect prohibited (initial value) Level detect prohibited (count disable) 0 1 Falling edge LOW level 1 0 Rising edge HIGH level 1 1 Setting is prohibited Setting is prohibited If this bit is rewritten after its start, the count value is not assured. 259 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.4 Counter status register 0/1 (CSR0/1) This section describes the configuration and explains the function of counter status register 0/1 (CSR0/1). ■ Counter status register 0/1 (CSR0/1) The bit configuration of the counter status register 0/1 (CSR0/1) is shown below. Figure 13.2-5 Bit configuration of counter status register 0/1(CSR0/1) Bit 7 6 5 4 3 2 1 0 CSR0 Address: 000072H CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0 CSR 1 R R Address: 000074H R/W R/W R/W R/W R/W R/W Initial value 00000000B Counter status register 0/1 (CSR0/1) consists of bits that have the functions explained below. [Bit 7] CSTR (count start) This bit is used to control the UDCR count start/stop operation. CSTR Count start/stop operation 0 Count operation stop (initial value) 1 Count operation start [Bit 6] CITE (compare interrupt output control) This bit is used to control permit/prohibit of interrupt output to the CPU if CMPF is defined (if a compare occurs). CITE Permit/prohibit of compare interrupt output 0 Compare interrupt output prohibited (initial value) 1 Compare interrupt output permitted [Bit 5] UDIE (overflow/underflow interrupt output control) This bit is used to control the permit/prohibit of interrupt output to the CPU if OVFF/UDFF is defined (if overflow/underflow occurs). 260 UDIE Permit/prohibit of overflow/underflow interrupt output 0 Overflow/underflow interrupt output prohibited (initial value) 1 Overflow/underflow interrupt output permitted CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER [Bit 4] CMPF (compare detect flag) This bit is a flag indicating that the UDCR and RCR values match each other after a comparison. Only writing "0" is permitted, and "1" cannot be written. Read-modify-write type instructions return "1" irrespective of bit values. CMPF Match/no match at compare detection 0 No match in compare results (initial value) 1 Match in compare results [Bit 3] OVFF (overflow detect flag) This bit is a flag indicating an overflow occurred. Only writing "0" is permitted, and "1" cannot be written. Read-modify-write type instructions return "1" irrespective of bit values. OVFF Overflow occurrence 0 No overflow occurred (initial value) 1 Overflow occurred [Bit 2] UDFF (underflow detect flag) This bit is a flag indicating that an underflow occurs. Writing "0" is only permitted but not writing "1". Read-modify-write type instructions return "1" irrespective of bit values. UDFF Underflow occurrence 0 No underflow occurred (initial value) 1 Underflow occurred [Bits 1 to 0] UDF1, UDF0 (up/down flag) These bits are used to indicate the last count operation (up/down) performed. Only reading is permitted but writing is not. UDF1 UDF0 Detect edge 0 0 No input (initial value) 0 1 Decremented 1 0 Incremented 1 1 Simultaneous up/down occurred 261 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.5 Up/down count register 0/1 (UDCR0/1) Up/down count register 0/1 (UDCR0/1) has the configuration and function explained below. ■ Up/down count register 0/1 (UDCR0/1) The bit configuration of the up/down count register 0/1 (UDCR0/1) is shown below. Figure 13.2-6 Bit configuration of up/down count register 0/1 (UDCR0/1) Bit 15 UDCR 1 D17 Address: 000069H R Bit 7 UDCR 0 D07 Address: 000068H R 14 D16 R 6 D06 R 13 D15 R 5 D05 R 12 D14 R 4 D04 R 11 D13 R 3 D03 R 10 D12 R 2 D02 R 9 D11 R 1 D01 R 8 D10 R 0 D00 R Initial value 00000000B Initial value 00000000B This register is an 8-bit count register. With an internal prescaler, AIN/BIN pin input, an up/down count operation is performed. It operates as a 16-bit count register in the 16-bit count mode. In this case, the high-order 8-bit setting of the control register is disabled. This register has no direct write operation. This register must be written via RCR. The value to be written to this register must first be written to RCR, and then it is transferred from RCR to this register by setting the CCRL: CTUT bit to "1" (reloading by software). This register uses word access for reading. 262 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.2.6 Reload/compare register 0/1 (RCR0/1) This section describes the configuration and explains the function of reload/compare register 0/1 (RCR0/1). ■ Reload/compare register 0/1 (RCR0/1) Reload/compare register 0/1 (RCR0/1) has the bit configuration shown below. Figure 13.2-7 Bit configuration of reload/compare register 0/1 (RCR0/1) 15 RCR1 Address: 00006BH D17 W 7 RCR0 Address: 00006AH D07 W 14 D16 W 6 D06 W 13 D15 W 5 D05 W 12 D14 W 4 D04 W 11 D13 W 3 D03 W 10 D12 W 2 D02 W 9 D11 W 1 D01 W 8 D10 W 0 D00 W Initial value 00000000B Initial value 00000000B Reload/compare registers 0/1 (RCR0/1) are 8-bit reload/compare registers. These registers are used to specify a reload value and compare value. The reload value and compare value have the same value and, by starting the reload function and compare function, an up/down count is available between the 00H to RCR values (16-bit operation mode: 0000H to RCR value). This register allows write-only operations but not read operations. By writing "1" to the CCR0/1: CTUT bit, this register value can be transferred to UDCR (reloading by software). Write to this register with word access. 263 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3 8/16-bit Up/Down Counter/Timer Operation This section explains different count modes in the 8/16-bit up/down counter/timer and the operation of the reload/compare function. ■ Selection of count mode The 8/16-bit up/down counter/timer has 4 types of count modes. These count modes are selected with CCRH: CMS1 or 0. Table 13.3-1 Selection of count mode CMS1, CMS0 Count mode 00B Timer mode (decremented) 01B Up/down count mode 10B Phase difference count mode: frequency multiplied by 2 11B Phase difference count mode: frequency multiplied by 4 ❍ Timer mode (decremented) In the timer mode, output of the internal prescaler is decremented. The built-in prescaler enables selection of either 2 machine cycles or 8 machine cycles with CCRH: CLKS. ❍ Up/down count mode In the up/down count mode, counting the input of external pins AIN and BIN enables an up/ down count. AIN pin input controls increments, and BIN pin input controls decrements. Input of the AIN pin and BIN pin indicates an edge detect, enabling selection of a detect edge with CCRH: CES1 and CES0. Table 13.3-2 Selection of count mode CES1, CES0 Detect edge 00B Edge detect prohibit 01B Falling edge detect 10B Rising edge detect 11B Both falling and rising edges detected ❍ Phase difference count mode (at frequency multiplied by 2/frequency multiplied by 4) In the phase difference count mode, to count the encoder phase difference between output signal phases A and B, the BIN pin input level is checked for counting if the AIN pin input edge is detected, and the AIN pin input level is checked for counting if the BIN pin input edge is detected. In the modes at frequency multiplied by 2 and frequency multiplied by 4, the phase difference is checked between AIN and BIN pin inputs. If the AIN pin is advanced, it is incremented and, if the BIN pin is advanced, it is decremented. 264 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER In the mode at frequency multiplied by 2, at the timing of both the rising and falling edges of the BIN pin, counting is done as required by checking for the AIN pin value. Count operations in this case are as follows: • Incremented if the AIN pin value detected at the rising edge of the BIN pin is "H" • Decremented if the AIN pin value detected at the rising edge of the BIN pin is "L" The AIN pin value detected at the falling edge of the BIN pin is selected from the following types 1) and 2): 1) Decremented if the AIN pin value detected, at the falling edge of BIN pin is "H" Incremented if the AIN pin value detected at the falling edge of the BIN pin is "L" 2) Decremented if the AIN pin value detected at the falling edge of the BIN pin is "L" Incremented if the AIN pin value detected at the falling edge of the BIN pin is "H" Figure 13.3-1 Outline of phase difference count mode (at frequency multiplied by 2) operation AIN pin BIN pin Count in falling edge detect (1) Count value 0 +1 1 +1 2 +1 3 +1 4 +1 5 -1 4 +1 5 -1 4 -1 3 -1 2 +1 1 +1 2 +1 3 +1 4 -1 3 +1 4 -1 1 -1 0 Count in falling edge detect (2) Count value 0 +1 1 -1 0 +1 1 -1 0 -1 3 +1 4 In the mode at frequency multiplied by 4, the AIN pin value is checked for counting at the timing of both the BIN pin rising and falling edges. BIN pin value is checked for counting at the timing of both the AIN pin rising and falling edges. Count operations for such cases are described below. • Incremented if the AIN pin value detected at the rising edge of the BIN pin is "H" • Decremented if the AIN pin value detected at the rising edge of the BIN pin is "L" • Decremented if the AIN pin value detected at the falling edge of the BIN pin is "H" • Incremented if the AIN pin value detected at the falling edge of the BIN pin is "L" • Decremented if the BIN pin value detected at the rising edge of the AIN pin is "H" • Incremented if the BIN pin value detected at the rising edge of the AIN pin is "L" • Incremented if the BIN pin value detected at the falling edge of the AIN pin is "H" • Decremented if the BIN pin value detected at the falling edge of the AIN pin is "L" 265 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER Figure 13.3-2 Outline of phase difference count mode (at frequency multiplied by 4) operation AIN pin BIN pin +1 +1 +1 +1 Count value 0 1 2 3 4 +1 +1 +1 +1 5 6 7 8 +1 +1 9 10 -1 9 +1 10 -1 9 -1 -1 -1 -1 8 7 6 5 -1 -1 -1 -1 4 3 2 1 In counting the encoder output, the input condition must be arranged by defining the relationship between the phases and pins shown below. Thus, high-precision detection can enable the rotation angle, rotation count, and rotation direction to be measured. • Inputting phase A to the AIN pin • Inputting phase B to the BIN pin • Inputting phase Z to the ZIN pin If this count mode is selected, the selection of detect edge via CCRH: CES1/0 and CCRL: CGE1/0 is disabled. 266 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.1 Reload/compare function The 8/16-bit up/down counter/timer has reload and compare functions. These two functions may be mixed for processing. ■ Reload and compare functions Table 13.3-3 "Selection of count mode" shows an example of selecting reload and compare functions. Table 13.3-3 Selection of count mode RLDE, UCRE Reload and compare functions 00B Reload/compare prohibit (initial value) 01B Compare permit 10B Reload permit 11B Reload/compare permit ■ Reload function At the start of the reload function, the RCR value is transferred to UDCR at the timing of the down-count clock next to the clock in which an underflow occurs. In this example, UDFF is specified, and an interrupt request occurs. In a mode where there is no down counting (decrement), the start of this function is disabled. Figure 13.3-3 Outline of reload function operation (0FFFFH) 0FFH Reload/interrupt generated Reload/interrupt generated RCR 00H Underflow Underflow 267 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ■ Compare function The compare function is available in any modes other than the timer mode. If RCR and UDCR values match at the start of the compare function, CMPF is specified and an interrupt request is generated. When the compare clear function starts, UDCR is cleared at the next timing of the incremented clock. In a mode where there is no up counting, the start of this function is disabled. Figure 13.3-4 Outline of compare function operation (0FFFFH) 0FFH Compare matched Compare matched RCR 0000H Counter cleared, interrupt generated Counter cleared, interrupt generated ■ Up/down count at any width When a reload/compare function starts, an up/down count is available at any width. The reload function is started when an underflow occurs to transfer RCR value to UDCR. The compare function clears UDCR if RCR and UDCR having matching values. Using both functions, an up/down count is performed in a range of 00H to RCR. Figure 13.3-5 Outline of operation where reload and compare functions start at one time (0FFFFH) 0FFH RCR 0000H Compare matched Counter clear Compare matched Counter clear Reload Reload Reload Underflow Underflow Underflow Compare matched Counter clear If a reload (underflow) occurs or compare finds a match, an interrupt can be generated to CPU. These interrupt outputs are controlled so that they are enabled independently. The timing of reload and clear operations for UDCR vary between the count start and stop modes. 268 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ❍ If reload or clear events are generated in a count operation All operations are in sync with the count clock. Figure 13.3-6 "Normal operation counting" shows an example of reloading 080H. Figure 13.3-6 Normal operation counting UDCR 065h 066h 080h 081h ↓ Synchronized with this clock Reload/clear event Count clock ❍ If reload and clear events are generated in a count operation If counting stops in the count clock sync wait mode (state where count input is held for synchronization), reload and clear operations are performed when the stop occurs. Figure 13.3-7 "Count stop operation in count clock sync signal wait mode" shows an example of reloading 080H. Figure 13.3-7 Count stop operation in count clock sync signal wait mode UDCR 065h 066h 080h Reload/clear event Count clock Count enable Enable (count permitted) Disable (count prohibited) ❍ If reload and clear events are generated in the count stop mode Operations are performed when an event occurs. Figure 13.3-8 "Operation when reload/clear event occurs in count stop mode" shows an example of reloading 080H. Figure 13.3-8 Operation when reload/clear event occurs in count stop mode UDCR 065h 080h Reload/clear event A clear operation caused by compare is performed if the UDCR and RCR values match and incrementing (up count) occurs. Even if the UDCR and RCR values match, no clear operation is performed if a down-count or count stop occurs subsequently. A clear operation is performed at the above timing for all events other than reset input. Reload is also performed at the above timing in any event. If clear and reload events occur at the same time, the clear event has priority. 269 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 13.3.2 Writing data to up/down count register (UDCR) Writing data directly to UDCR from a bus is not permitted. This section includes procedures for writing data to UDCR. ■ Writing data to UDCR Data can be written to UDCR with the following procedures: 1. Data to be written to UDCR is first saved to RCR. Make sure that RCR data is discarded. 2. Writing "1" to CCRH: CTUT transfers the data from RCR to UDCR. ■ Clearing the counter The following procedures are available for clearing the counter in addition to the above procedures: • Clearing with reset input (initialize) • Clearing with an edge input from the ZIN pin • Clearing by writing "0" to CCRH: UDCC • Clearing with the compare function Such a write operation is performed regardless of the occurrence of count start/stop. ■ Count clear/gate function The ZIN pin is selected by CCRH: CGSC for use as either a count clear or gate function. If the count clear function starts, the counter is cleared at the edge input from the ZIN pin. The edge of the ZIN pin input signal used to clear the count is selected using CCRL: CGE1/CGE0. This function is used to input the phase Z output of the encoder to the pin, enabling UDCR to be cleared at the start of encoder counting. If the gate function starts, the count is enabled or disabled depending on the level input from the ZIN pin. The level of the ZIN pin input signal used to enable the count is selected using CCRL: CGE1/CGE0. This function is available for all count modes. Table 13.3-4 Selection of ZIN pin function CGSC ZIN pin function CGE1, CGE0 0B Counter clear function 00B Detect prohibited Detect prohibited 1B Gate function 01B Rising edge Low level 10B Falling edge High level 270 Counter clear function Gate function CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER ■ Count direction flag, count direction reversal flag The count direction flag (UDF1, UDF0) indicates whether the last count operation was either an up-count or down-count if an up- or down-count was performed. By evaluating the count clock generated by input of both the AIN and BIN pins, a flag is updated at every count operation. If information on the current rotation direction is required for controlling the motor, it is identified by checking this flag. This function is available in all count modes. Table 13.3-5 Selection of count mode UDF1, UDF0 Count direction 00B Down count (decrement) 01B Up count (increment) 11B Up/down simultaneously generated (no count operation performed) The count direction reversal flag (CDCF) is set when the count direction is switched between counting up and counting down. When this flag is set, an interrupt is generated to the CPU. By referring to this interrupt and the count direction flag (UDF1, UDF0), changes of direction are identified. However, note that the direction indicated by the flag may be restored to the original one after one reversal of direction if the duration of the direction reversal is short and/or occurs repeatedly. Table 13.3-6 Count direction reversal flag CDCF Count direction reversal detection 0B No direction reversal 1B Direction reversal (one or more times) 271 CHAPTER 13 8/16-BIT UP/DOWN COUNTER/TIMER 272 CHAPTER 14 PWC TIMER This chapter provides an overview of the PWC timer, provides notes on its use, and explains the configuration and functions of its registers. 14.1 "Overview of PWC Timer" 14.2 "PWC Timer Registers" 14.3 "Operations of PWC Timer " 14.4 "Notes on PWC Timer Usage" 273 CHAPTER 14 PWC TIMER 14.1 Overview of PWC Timer The PWC timer is a 16-bit multifunctional up-count timer used to measure the pulse width of input signals. PWC: Pulse Width Count (for pulse width measurement) ■ PWC timer functions On the hardware level, the PWC timer consists of one 16-bit up-count timer, one input pulse divider and divide ratio control register, one measurement input pin, and three 16-bit control registers. When regarding each 16-bit control register as one channel, the PWC timer has a total of three channels. The PWC timer provides the following functions. ❍ Timer function • Each time the timer function has been set, an interrupt request will be generated • An internal clock used as a reference clock can be selected from three types. ❍ Pulse width measurement function 274 • Measures the time between any events input from the outside via the pulse input • An internal clock used as a reference clock can be selected from three types • Various measurement modes • H pulse width (rising edge to falling edge)/L pulse width (rising edge to falling edge) • Rising interval (rising edge to rising edge)/falling interval (falling edge to falling edge) • Measurement between edges (rising edge or falling edge to falling edge or rising edge) • An 8-bit input divider is used for divide measurement with "divide-by-22 x n" (n = 1,2,3,4) of the input pulse. • At the end of measurement, an interrupt can be generated. • Either one-time measurement or repeated measurement can be selected. CHAPTER 14 PWC TIMER ■ Block diagram of PWC timer Figure 14.1-1 "Block diagram of the PWC timer" shows a block diagram of the PWC timer. Figure 14.1-1 Block diagram of the PWC timer PWCR read Error detection ERR Internal clock(machine clock/4) PWCR 16 Reload Data transfer 16 Overflow Clock 22 16-bit up-count timer Clock divider F2MC-16 bus 2 Timer clear Control bit output Flag set, etc. Measurement end edge CKS1/CKS0 Count enabled Control circuit Start edge selection Measurement start edge End edge selection Divide ON/OFF Overflow interrupt request PWCSR PIS0/PIS1 Divider clear Input waveform comparator Edge detection Measurement end interrupt request 3 PWC0 PWC1 8-bit divider ERR CKS0/CKS1 Divide ratio selection 15 2 DIVR 275 CHAPTER 14 PWC TIMER 14.2 PWC Timer Registers This section describes the configuration and functions of the registers used in the PWC timer. ■ List of PWC timer registers Figure 14.2-1 "List of PWC timer registers" shows a list of the PWC timer registers. Figure 14.2-1 List of PWC timer registers 15 87 0 PWCSR0 - 2 (R/W) PWC0 - 2 (R/W) DIV0 - 2 (R/W) 14 13 12 11 10 9 000077H 15 00007BH STRT STOP EDIR EDIE OVIR OVIE ERR 00007FH (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R) 8 Reserved ( ) PWCSR0 - 2 PWC control/status register Initial value 0000000XB 7 6 5 4 3 2 1 0 PWCSR0 - 2 000076H 00007AH CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0 PWC control/status register 00007EH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000B 14 13 12 11 10 9 8 PWCR0 - 2 000079H 15 D15 D14 D13 D12 D11 D10 D9 D8 PWC data buffer register 00007DH 000081H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000 B 7 6 5 4 3 2 1 0 PWCR0 - 2 000078H 00007CH D7 D6 D5 D4 D3 D2 D1 D0 PWC data buffer register 000080H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Initial value 00000000 B 000082H 000084H 000086H 276 7 6 5 4 3 2 ( ) ( ) ( ) ( ) ( ) ( ) 1 0 PWCSR0 - 2 DIV1 DIV0 Divide ratio control register (R/W) (R/W) Initial value ------00B CHAPTER 14 PWC TIMER 14.2.1 PWC Control/Status Register (PWCSR0 to PWCSR2) This section describes the configuration and functions of the PWC control/status register (PWCSR0 to PWCSR2). ■ PWC control/status register (PWCSR0 to PWCSR2) Figure 14.2-2 "Bit configuration of the PWC control/status register (PWCSR0 to PWCSR2)" shows the bit configuration of the PWC control/status register (PWCSR0 to PWCSR2). Figure 14.2-2 Bit configuration of the PWC control/status register (PWCSR0 to PWCSR2) 14 13 12 11 10 9 000077H 15 00007BH STRT STOP EDIR EDIE OVIR OVIE ERR 00007FH (R/W) (R/W) (R) (R/W) (R/W) (R/W) (R) (0) (0) (0) (0) (0) (0) (0) 8 Bit No. Reserved (-) (X) Reading/writing Initial value 7 6 5 4 3 2 1 0 000076H 00007AH CKS1 CKS0 PIS1 PIS0 S/C MOD2 MOD1 MOD0 PWCSR 00007EH (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (0) (0) (0) Initial value The functions of bits in the PWC control/status register (PWCSR0 to PWCSR2) are described below. [Bits 15, 14] STRT, STOP (timer start bit, timer stop bit) These bits are used to start/restart/stop the 16-bit up-count timer. The operation state of the timer is returned in read operations. The tables below show the functions of the STRT and STOP bits. Table 14.2-1 Functions related to Write operations (operation control of 16-bit up-count timer) STRT STOP Operation control function 0 0 No function/no effect on operation 0 1 Timer start/restart (when counting is allowed) *1 1 0 Timer operation forcible stop (when counting is prohibited)*1 1 1 No function/no effect on operation *1: A clear bit-operation instruction is available 277 CHAPTER 14 PWC TIMER Table 14.2-2 Functions related to Read operations (indicating the operation state of the 16-bit up-count timer) STRT STOP Operation control function 0 0 Timer stop mode (not started or end of measurement) (initial value) 1 1 Timer count operation mode (measurement in progress) • At reset, initialized to 00B. • Reading and writing are allowed. However, the meaning of the register contents is different for write and read operations, as indicated in Table 14.2-1 "Functions related to Write operations (operation control of 16-bit up-count timer)" and Table 14.2-2 "Functions related to Read operations (indicating the operation state of the 16-bit up-count timer)". • The reading value returned in read-modify-write instructions is fixed at 11B for all bit values. • Writing the STRT/STOP bit to start/stop the timer can be performed for individual bits in order to execute bit operation instructions (bit clear). However, note that no bit operation instruction is available to read the operation state (the result of reading is always "operation in progress"). [Bit 13] EDIR (measurement end interrupt request flag) This bit is a flag that indicates the end of measurement in pulse width measurement. By setting this bit when measurement end interrupt sources are enabled (bit 12: EDIE = 1), a measurement end interrupt request is generated. EDIR Cause of setting or clearing Cause for setting Set when pulse width measurement ends (when the PWCR contains the measurement result) Cause of clearing Cleared when the PWCR (measurement result) is read • Initialized to "0" at reset. • Only reading is allowed. • Bit values cannot be changed by writing [Bit 12] EDIE (measurement end interrupt enable) This bit is used for control of measurement end interrupt requests when pulse width measurement is performed as shown in the table below. EDIE 278 Operation 0 Measurement end interrupt request output prohibited (no interrupts occur even if EDIR is set) [initial value] 1 Measurement end interrupt request output allowed (interrupt occurs if EDIR is set) • Initialized to "0" at reset • Reading or writing is allowed. CHAPTER 14 PWC TIMER [Bit 11] OVIR (timer overflow interrupt request flag) This bit is a flag used to indicate an overflow of the 16-bit up-count timer to the area from FFFFH to 0000H. If this bit is set when timer overflow interrupt requests are enabled (bit 10:OVIE = "1"), a timer overflow interrupt request is generated. OVIR Cause of setting or clearing Cause for setting Set if a timer overflow occurs (to the area from FFFFH to 0000H) Cause of clearing Writing "0" or clearing by µDMAC • Initialized to "0" at reset • Reading and writing are allowed; however, only writing "0" is effective, while writing "1" causes no changes in the bit value. • Read-modify-write type instructions return "1" irrespective of bit values. [Bit 10] OVIE (timer overflow interrupt request enable) This bit is used for control of measurement end interrupt requests during pulse width measurement, as shown in the following table. OVIE Operation 0 Overflow interrupt request output prohibited (No interrupts occur even if OVIR is set) [initial value] 1 Overflow interrupt request output allowed (An interrupt occurs if OVIE is set) • Initialized to "0" at reset. • Reading and writing are allowed. [Bit 9] ERR (Error Flag) This bit is a flag that indicates that, in the repeated measurement mode of pulse width measurement, a measurement operation has completed before the previous measurement result was read out from the PWCR. In this case, the PWCR value will be updated to the new measurement result while the immediately previous measurement result will be lost. Measurement will continue irrespective of the value of this bit. ERR Cause of setting or clearing Cause for setting This bit is set if a measurement result that has not been read out is overwritten by the next result. Cause of clearing This bit is cleared whenever the PWCR (measurement result) is read • Initialized to "0" at reset. • Only reading is allowed. Write operations have no effect. [Bit 8] Reserved bit This bit is reserved. 279 CHAPTER 14 PWC TIMER [Bits 7, 6] CKS1, CKS0 (clock selection) These bits are used to select one internal count clock out of the three types listed in Table Table 14.2-3 "Count clocks of the 16-bit up-count timer". Table 14.2-3 Count clocks of the 16-bit up-count timer CKS1 CKS0 Count clock selection 0 0 Divide-by-4 clock of the machine clock (0.25 µs for a machine clock of 16 MHz) [initial value] 0 1 Divide-by-16 clock of the machine clock (1.00 µs for a machine clock of 16 MHz) 1 0 Divide-by-32 clock of the machine clock (2.00 µs for a machine clock of 16 MHz) 1 1 Setting prohibited (result of setting is undefined) • Initialized to 00B at reset • Reading and writing are allowed. However, setting to 11B is prohibited. Note: Rewriting after timer start is prohibited. Rewrite only before the timer is started or when the timer is stopped. [Bits 5, 4] PIS1, PIS0 (Pulse width measurement input pin select) These bits are used to select the pulse width measurement input pin. Table 14.2-4 Selection of pulse width measurement input pin PIS1 PIS0 Input clock selection 0 0 (Selecting PWC0 pin) [initial value] 0 1 Two inputs selected for compare (rising edge compare) 1 0 Two inputs selected for compare (falling edge compare) 1 1 Setting prohibited (result of setting is undefined) • Initialized to 00B at reset. • Reading and writing are allowed. However, setting to 11B is prohibited. • This bit is only valid in PWC0. (PWC0/PWC1 are used for input). For details, refer to Section 14.3.6 "Operation in Pulse Width Measurement Mode". Note: Rewriting after timer start is prohibited. Write only before the timer is started or when the timer is stopped. 280 CHAPTER 14 PWC TIMER [Bit 3] S/C (Selection of Measurement Mode (one-shot/repeated)) This bit is used to select the measurement mode. Table 14.2-5 Selection of the measurement mode of the 16-bit up-count timer S/C 0 1 Measurement mode selection One-shot measurement mode [initial value] Repeated measurement mode Timer mode Pulse width No reload (one-shot) Stopped after one-time measurement With reload (reload timer) Repeated measurement: buffer register enabled • Initialized to "0" at reset. • Reading and writing are allowed. • Rewriting after timer start is prohibited. Write always either before the timer is started or after the timer is stopped. [Bits 2, 1, 0] MOD2, MOD1, MOD0 (Selection of operation mode or measurement edge) These bits are used to select the operation mode and an edge at which width measurement is performed. Table 14.2-6 Selection of operation mode or measurement edge for the 16-bit up-count timer MOD2 MOD1 MOD0 Selection of operation mode/measurement edge 0 0 0 Timer mode [initial value] 0 0 1 Timer mode (reload mode only) 0 1 0 Pulse width measurement mode between all edges (rising edge or falling edge to falling edge or rising edge) 0 1 1 Divide interval measurement mode (input divide enabled) 1 0 0 Interval measurement mode between rising edges (rising edge to rising edge) 1 0 1 "H"-level pulse width measurement mode (rising edge to falling edge) 1 1 0 "L"-level pulse width measurement mode (falling edge to rising edge) 1 1 1 Interval measurement mode between falling edges (falling edge to falling edge) • Initialized to 00B at reset. • Reading and writing are allowed. Note: Rewriting immediately after timer start is prohibited. Write always either before the timer is started or after the timer is stopped. 281 CHAPTER 14 PWC TIMER 14.2.2 PWC Data Buffer Register (PWCR0 to PWCR2) This section describes the configuration and functions of the PWC data buffer register (PWCR0 to 2). ■ PWC data buffer register (PWCR0 to PWCR 2) Figure 14.2-3 "Bit configuration of the PWC data buffer register (PWCR0 to 2)" shows the bit configuration of the PWC data buffer register (PWCR0 to PWCR2). Figure 14.2-3 Bit configuration of the PWC data buffer register (PWCR0 to 2) 14 13 12 11 10 9 8 PWCR 000079H 15 00007DH D15 D14 D13 D12 D11 D10 D9 D8 PWC data buffer register 000081H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (0) (0) (0) Initial value 000078H 00007CH 000080H 7 6 5 4 3 2 1 0 PWCR D7 D6 D5 D4 D3 D2 D1 D0 PWC data buffer register (R/W) (R/W) ((R/W))(R/W) (R/W) (R/W) ((R/W))(R/W) Reading/writing (0) (0) (0) (0) (0) (0) (0) (0) Initial value The function of the PWC data buffer register (PWCR0 to 2) depends on whether the timer mode is selected (by setting the PWCSR register bits 2 to 0 (MOD2 to 0)) or the pulse width set mode is selected. ❍ Timer mode (reading/writing allowed) In a reload timer operation (PWCSR bit 3:S/C = 1), the PWC data buffer register operates as a reload register to store reload data. In this case, both reading and writing are allowed. In one-shot timer operation mode (PWCSR bit 3:S/C = 0), the PWC data buffer register is used to directly access the up-count timer. In this case, both reading or writing are allowed, though writing can only be performed when the timer is stopped. Reading is available at any time, enabling the counter value to be read during counting. ❍ Pulse width measurement mode (Only reading allowed) In repeated measurement mode (PWCSR bit 3: S/C = 1), the PWC data buffer register operates as a buffer register to store the results of measurement. In this case, only reading is allowed. Write operations do not change the value of the register. In one-shot mode (PWCSR bit 3: S/C = 0), the PWC data buffer register is used to directly access the up-count timer. In this case, only reading is allowed. Write operations do not change the value of the register. Reading is available at any time, enabling the counter value to be read during counting. After the measurement ends, the PWC data buffer register stores the measurement result. Note: This register can only be accessed only via word transfer instructions. At reset, the register is initialized to 00B. 282 CHAPTER 14 PWC TIMER 14.2.3 Divide Ratio Control Register (DIVR0 to DIVR2) This section describes the configuration and functions of the divide ratio control register (DIVR0 to 2). ■ Divide ratio control register (DIVR0 to DIVR2) Figure 14.2-4 "Bit configuration of the divide ratio control register (DIVR0 to DIVR2)" shows the bit configuration of the divide ratio control register (DIVR0 to DIVR2). Figure 14.2-4 Bit configuration of the divide ratio control register (DIVR0 to DIVR2) 000082H 000084H 000086H 7 (-) (X) 6 (-) (X) 5 (-) (X) 4 (-) (X) 3 (-) (X) 2 (-) (X) 1 0 DIVR DIV1 DIV0 Divide ratio control register (R/W) (R/W) Reading/writing (0) (0) Initial value This register is only used in divide interval measurement mode (PWCSR: bits 2, 1, 0:MOD2, MOD1, MOD0 = 001); it is not used in other modes. In divide interval measurement mode, pulses input to the measurement pin are divided according to the divide ratio set in this register. This allows measuring the interval width. Table 14.2-7 Selection of divide ratio DIV1 DIV0 Count clock selection 0 0 Divide-by-4 [initial value] 0 1 Divide-by-16 1 0 Divide-by-64 1 1 Divide-by-256 • Initialized to 00B at reset • Reading and writing are allowed. Note: Rewriting after timer start is prohibited. Write always either before the timer is started or after it is stopped. 283 CHAPTER 14 PWC TIMER 14.3 Operations of PWC Timer This section describes the operations of the PWC timer. ■ Outline of PWC timer operations The PWC timer is a multifunction timer based on an 16-bit up-count timer, which integrates measurement input pins with the 8-bit input divide functions. The PWC timer has the two major functions listed below: • Timer function • Pulse width count function For either function, a counter clock can be selected among three types of clocks. The basic performance and operation of each function are described below. 284 CHAPTER 14 PWC TIMER 14.3.1 Operations of the Timer Function This timer is an up-count (incrementing) timer providing both reload and one-shot operations. ■ Operation of timer functions After the timer starts, its value is incremented at each pulse of the count clock. If an overflow occurs in the range FFFFH --> 0000H, an interrupt request may be generated. If an overflow is generated, the following operations may be performed depending on the mode: • In one-shot mode: Counting stops • In reload mode: Reload register data is reloaded into the timer to restart counting. Figure 14.3-1 "Operations of timer functions" shows the operations of the timer functions in oneshot mode and reload mode. Figure 14.3-1 Operations of timer functions [One-shot mode] (Solid line: timer count value) Overflow Overflow FFFFH Writing to PWCR (Restarting prohibited) 0000H Timer start OVIR flag set/timer stop Timer start OVIR flag set/timer stop Time [Reload mode] Timer count value Overflow Overflow Overflow Overflow Overflow FFFFH Reload PWCR write value 0000H Reload PWCR write Timer start * Reload Reload Reload * * Reload * Restart Reload * Timer stop Time *: OVIR flag set 285 CHAPTER 14 PWC TIMER 14.3.2 Operations of the Pulse Width Measurement Function With this function, the timer can be used to measure the time interval between any input pulse events. ■ Operations of the pulse width measurement function After the start of the pulse width measurement function, counting does not start before the specified measurement start edge is input. The timer is cleared to 0000H whenever a start edge is detected, and counting starts. Counting stops when a stop edge is detected. The counter value during this period is stored in the register. The end of measurement is detected by an interrupt. After measurement ends, the following operations are performed depending on the measurement mode: • In one-shot measurement mode: Operation is interrupted. • In repeated measurement mode: The timer value is transferred to the buffer register and the measurement is suspended until input of the next start edge. Figure 14.3-2 "Pulse width measurement operation (one-shot measurement mode/"H"-level pulse width measurement)" shows the operation in one-shot measurement mode. Figure 14.3-3 "Pulse width measurement operation (repeated measurement mode/"H"-level pulse width measurement)" shows the operation in repeated measurement mode. Figure 14.3-2 Pulse width measurement operation (one-shot measurement mode/"H"-level pulse width measurement) PWC input pulses to be measured (Solid line indicates timer count value) Timer count value FFFFH Timer clear 0000H Measurement Timer starts start Timer stop EDIR flag set (measurement end) 286 Time CHAPTER 14 PWC TIMER Figure 14.3-3 Pulse width measurement operation (repeated measurement mode/"H"-level pulse width measurement) PWC input pulses to be measured (Solid line indicates timer count value) Timer count value Overflow FFFFH Data transfer to PWCR Time clear Time clear 0000H Measurement Timer starts start Timer stop Timer start Time EDIR flag set (measurement end) EDIR flag set 287 CHAPTER 14 PWC TIMER 14.3.3 Selection of Count Clock and Operation Mode This section describes the selection of the count clock and the operation mode. ■ Count clock selection A timer count clock can be selected form among three types of internal clocks by setting PWCSR: bit 7 (CKS1) and bit 6 (CKS0). Table 14.3-1 "Count clock selection" shows how to select the count clock. Table 14.3-1 Count clock selection PWCSR/bits 7, 6: CKS1, 0 • Internal count clock selected 00B 1/4 of machine clock (0.25 µs for 16 MHz machine clock) [initial value] 01B 1/16 of machine clock (1.0 µs for 16 MHz machine clock) 10B 1/32 of machine clock (2.0 µs for 16 MHz machine clock) After reset, the divide-by-4 clock of the machine clock is initially selected. Note: Select the count clock before timer start. ■ Selection of operation mode The operation mode or measurement mode is selected by setting the PWCSR bits. • Selection of the operation mode: PWCSR: bits 2, 1, 0 (MOD2, MOD1, MOD0 bits) Selecting the timer mode/pulse width measurement mode and specifying the measurement edge. • Setting the measurement mode: PWCSR: bit 3 (S/C bit) Selecting between one-shot measurement/repeated measurement or reload/one-shot Table 14.3-2 "Settings of operation mode/measurement mode" shows the settings for selection of the operation mode/measurement mode. 288 CHAPTER 14 PWC TIMER Table 14.3-2 Settings of operation mode/measurement mode Operation mode Timer S/C MOD2 MOD1 MOD0 One-shot timer 0 0 0 0 Reload timer 1 0 0 0 One-shot measurement: buffer disabled 0 0 1 0 Repeated measurement: buffer enabled 1 0 1 0 One-shot measurement: buffer disabled 0 0 1 1 Repeated measurement: buffer enabled 1 0 1 1 One-shot measurement: buffer disabled 0 1 0 0 Repeated measurement: buffer enabled 1 1 0 0 One-shot measurement: buffer disabled 0 1 0 1 Repeated measurement: buffer enabled 1 1 0 1 One-shot measurement: buffer disabled 0 1 1 0 Repeated measurement: buffer enabled 1 1 1 0 One-shot measurement: buffer disabled 0 1 1 1 Repeated measurement: buffer enabled 1 1 1 1 Pulse width measurement Rising edge or falling edge to rising edge or falling edge Measurement between all edges Divide interval measurement (Divide-by 1 to 256) Rising edge to rising edge Interval measurement between rising edges Rising edge to falling edge "H"-level pulse width measurement Falling edge to rising edge L- pulse width measurement Falling edge to falling edge Interval measurement between falling edges • The one-shot timer is selected initially after reset. Note: Select the operation mode always before the start of the timer. 289 CHAPTER 14 PWC TIMER 14.3.4 Start and Stop of Timer/Pulse Width Measurement Start/restart/stop/forcible stop of each operation are controlled by setting the PWCSR: bits 15, 14 (STRT, STOP bits). ■ Start and Stop of timer/pulse width measurement Start/restart of the timer/pulse width measurement is initiated by setting the STRT bit to "0", while a forcible stop is initiated by setting the STOP bit to "0". However, this is only effective if the values are complementary to each other. When using instructions other than bit operation instructions (such as byte instructions), be sure to set only the bit combinations indicated in Table 14.3-3 "Function of STRT bit and STOP bit". Table 14.3-3 Function of STRT bit and STOP bit STRT STOP Function 0 1 Start/restart of timer/pulse width measurement 1 0 Forcible stop of timer/pulse width measurement When using bit operation instructions (the clear bit-operation instruction), special care is not required, since the hardware will ensure that only the combinations of values indicated in Table 14.3-3 "Function of STRT bit and STOP bit" are written. ■ Operation after measurement start The operation of timer mode and pulse width measurement mode after measurement start are as follows. ❍ Timer mode Count operation starts immediately. ❍ Pulse width measurement mode Counting will not start until the measurement start edge is detected. After the measurement start edge is detected, the 16-bit up-count timer is cleared to 0000B to start counting. 290 CHAPTER 14 PWC TIMER ■ Restart Restart is defined as a start operation (setting the STRT bit to "0") performed after entering timer/pulse width measurement mode. Restart operates as follows depending on the mode: ❍ One-shot timer mode Restart has no effect. ❍ Reload Timer Mode Reload is performed and operation continues. If a restart occurs at the same time as an overflow, the overflow flag (OVIR) is set. ❍ Pulse width measurement mode In the measurement start edge wait state, restart has an effect. In measurement mode, counting stops and the measurement start edge wait state is entered. If, in this mode, measurement end edge detection and restart occur at the same time, the measurement end flag (EDIR) is set. In repeated measurement mode, the result will be transferred to the PWCR. ■ Stop In one-shot timer mode or one-shot measurement mode, no explicit stop operation needs to be performed because counting will automatically stop at a timer overflow or at measurement end. However, in other modes, the timer must be forcibly stopped. Moreover, providing an explicit stop operation allows the timer to stop before it would stop automatically. ❍ Comparing and selection of two inputs If a forcible stop is performed before the edge selected via PWC1 has been detected, the first measurement result after restart of measurement will contain an error. Be sure to perform a forcible stop only after the PWC1 edge has been detected. ■ Confirmation of operation state The STRT/STOP bits, which have been explained above, operate as operation state indicator bits when read. Table 14.3-4 Function of the operation state indicator bits STRT STOP Operation state 0 0 Timer stop (except in measurement start edge wait state): Indicates that the timer has not started or that measurement has ended. 1 1 Timer counting is being performed or the system is in measurement start edge wait state Note: The same value is returned regardless of whether STRT or STOP bit is read. If these bits are read with read-modify-write instructions (such as bit operation instructions), 11B is always returned. Do not use read-modify-write instructions for reading. 291 CHAPTER 14 PWC TIMER 14.3.5 Timer Mode Operation This section describes the device operation in timer mode. ■ Clearing the timer In the following cases, the 16-bit up-count timer is cleared to 0000H: • At reset • If, in pulse width measurement mode, a measurement start edge is detected and counting starts ■ One-shot operation mode In one-shot operation mode, the timer count is incremented with every count clock pulse after timer start. If an overflow occurs while incrementing from FFFFH to 0000H, the timer automatically stops. If the PWCR is set to any value before timer start, counting will start with that value. In this case, the value that was previously set will not be preserved, and the PWCR value will always indicate the current count value. ■ Reload operation mode In reload operation mode, the timer is set to the reload value stored in PWCR, and the timer will be incremented with every count clock pulse after the timer starts. If an overflow occurs while incrementing from FFFFH to 0000H, the reload value in PWCR will be loaded again into the timer (reload operation), and counting will be repeated from that value. The timer does not stop until it is forcibly stopped due to writing the PWCSR: STOP bit, or due to a reset. The value set in the PWCR before the timer starts is retained during counting as a reload value, and will be loaded into the timer if a start/restart or an overflow occurs. If the value that is set in the PWCR changes during counting, this new, changed reload value will be used at the next overflow or timer restart. ■ Timer value and reload value In one-shot operation mode, the PWCR is directly accessed by the up-count timer. Any value written to the PWCR will also be written to the timer as is. When reading the PWCR while the timer is in progress, the value of the current timer count will be returned. If any value is set to the PWCR before the timer starts, counting will start from this value. In reload operation mode, accessing the count-up timer is prohibited. The PWCR operates as a reload register that stores a reload value. If a start/restart/overflow occurs, the timer is always set to the value stored in the PWCR. When reading the PWCR, the stored reload value will be returned. If the timer is placed in one-shot operation mode after the reload operation mode is forcibly canceled, the PWCR value and timer value are not specified. Be sure to always specify these values before using the timer. ■ Interrupt generation request In timer mode, an interrupt request may be generated due to a timer overflow. If an overflow occurs due to incrementing the counter, the overflow flag is set and an overflow request is generated, if such requests are allowed. 292 CHAPTER 14 PWC TIMER ■ Timer interval In one-shot operation mode, after PWCR is set to 0000H to start the timer, an overflow is generated after the count 65536 is reached and counting will stop. The time that elapses from start to stop can be calculated with the following formula: T1 = (65536 - n1) x t Where T1: time from start to stop [µs] n1: timer value stored in the PWCR at the start t: count clock interval [µ]s In reload operation mode, after PWCR is set to 0000H to start the timer, an overflow will be generated every time the counter reaches 65536. The reload interval time can be calculated with the following formula: TR = (65536 - nR) x t Where TR: reload interval (overflow interval) [µs] nR: reload value stored in PWCR t: count clock interval [µs] ■ Count clock and maximum interval In timer mode, the maximum interval is obtained when setting PWCR to the value 0000H. Count clock interval and maximum timer interval for the case when the machine clock (represented as Φ hereafter) is 16 MHz are shown in Table 14.3-5 "Count clock interval". Table 14.3-5 Count clock interval Count clock selection CSK1, 0 = 00: (Φ Φ /4) CSK1, 0 = 00: (Φ Φ /16) CSK1, 0 = 00: (Φ Φ/32) Count clock interval 0.25 µs 1.0 µs 2.0 µs Maximum timer interval 16.38 ms 65.5 ms 131.1 ms 293 CHAPTER 14 PWC TIMER ■ Timer Operation Flow Figure 14.3-4 "Operational flow of the timer" shows the operation flow of the timer. Various settings Figure 14.3-4 Operational flow of the timer Count clock selection Operation/measurement mode selection Interrupt flag clear Interrupt enable Set a PWCR value Restart Reload operation mode Start via the STRT bit Reload operation mode Load the PWCR value into the timer Start counter Start counter Incrementing Incrementing Overflow occurs → OVIR flag set → OVIR flag set Overflow occurs Stop of counting Operation stop 294 CHAPTER 14 PWC TIMER 14.3.6 Operation in Pulse Width Measurement Mode This section describes operation in pulse width measurement mode. ■ One-Shot measurement and repeated measurement There are two modes for pulse width measurement: a mode for one-time measurement and a mode for repeated measurement. The mode to use is selected via the PWCSR: S/C bit (Refer to Section 14.3.3 "Selection of the Count Clock and Operation Mode"). ❍ One-Shot Measurement Mode As soon as the first measurement end edge is detected, the timer counter will stop and the measurement end flag (EDIR) in the PWCSR is set, causing a stop of measurement (however, if restart occurs at the same time, the device will wait for measurement to start again). ❍ Repeated measurement mode If a measurement end edge is detected, the timer counter stops, the PWCSR's measurement end flag (EDIR) is set, and counting stops until the next measurement start edge is detected. As soon as the next measurement start edge is detected, the timer is cleared to 0000H, and measurement starts again. At the end of measurement, the measurement result of the timer is transferred to the PWCR. Note: Be sure to change the measurement mode only while the timer is stopped. ■ Measurement result data One-shot measurement mode and repeated measurement mode differ in handling of the measurement result, timer values, and PWCR functions. Measurement results in both modes are as follows: ❍ In one-shot measurement mode • The timer value while measurement is in progress can be obtained by reading the PWCR. • The end result data of measurement can be obtained by reading the PWCR after measurement has ended. ❍ In repeated measurement mode • At the end of measurement, the timer measurement result is transferred to the PWCR. • Reading the PWCR will return the immediately previously obtained measurement result, because the previous measurement result is kept during the measurement operation. The timer value while measurement is in progress cannot be read. If a measurement result is not read out before the next measurement operation ends, the measurement result will be overwritten with the next measurement result. In this case, an error flag (ERR) in the WCSR is set. The error flag (ERR) is automatically cleared by reading the PWCR. 295 CHAPTER 14 PWC TIMER ■ Selection of input pin The PWC timer provides three channels, PWC0, PWC1, and PWC2, that are used as input pins for pulse width measurement. Each of these channels can therefore be used independently. Combining PWC0 and PWC1 with PIS1 and PIS0 in PWCSR0 enables the time between each input waveform's rising and falling edges to be measured. Note that the PWC register used in this case is PWC0. Figure 14.3-5 "Input waveform and internal measurement waveform" shows the relationship between input waveform and internal measurement. Figure 14.3-5 Input waveform and internal measurement waveform PWC0 input waveform PWC1 input waveform The time between rising/falling edges can be obtained by measuring the width of "H" within t his internal measurement waveform. PWC internal measurement waveform when PIS1 and PIS0 = "01" PWC internal measurement waveform when PIS1 and PIS0 = "10" Note: • In comparing two inputs, start counting from PWC0 regardless of whether rising or falling edges are detected and stop with PWC1. • If necessary, change the detection mode of rising and falling edges after measurement ends. ■ Measurement mode and counter operation The measurement mode is selected from among five types depending on which portions of the input pulse are to be measured. For a high precision measurement of a high frequency pulse width, a dedicated mode is provided to arbitrarily divide the input pulse for interval measurement. Table 14.3-6 "List of measurement modes" shows a list of the measurement modes. Table 14.3-6 List of measurement modes Measurement mode MOD2 MOD1 MOD0 Measurement items (W: pulse width to be measured) W "H"-level pulse width measurement 1 0 1 Start of counting W Stop of counting Start Stop Measures the width of the "H" pulse. Start of counting (measurement): When rising edge is detected End of counting (measurement): When falling edge is detected 296 CHAPTER 14 PWC TIMER Table 14.3-6 List of measurement modes (Continued) Measurement mode MOD2 MOD1 MOD0 Measurement items (W: pulse width to be measured) W L- pulse width measurement 1 1 0 Start of counting W Stop of counting Start Stop Measures the width of the "L" pulse. Start of counting (measurement): When rising edge is detected End of counting (measurement): When falling edge is detected Interval measurement between rising edges W 1 0 0 W W Stop of counting Start of counting Start Stop Start Stop Measures the interval between rising edges. Start of counting (measurement): When rising edge is detected End of counting (measurement): When rising edge is detected Interval measurement between falling edges W 1 1 1 W W Stop of counting Start Start of counting Stop Start Stop Measures the interval between falling edges. Start of counting (measurement): When falling edge is detected End of counting (measurement): When falling edge is detected W Pulse width measurement for all edges 0 1 0 W W Stop of counting Start of counting Start Stop Start Stop Measures the pulse width between repeatedly input edges Start of counting (measurement): When an edge is detected End of counting (measurement): When an edge is detected 297 CHAPTER 14 PWC TIMER Table 14.3-6 List of measurement modes (Continued) Measurement mode MOD2 MOD1 MOD0 Measurement items (W: pulse width to be measured) W Divide interval measurement 0 1 W W Stop of counting 1 Start of counting (Example of divide-by-4) Start Stop Measures an interval by dividing the input pulse with a divide ratio selected in the divide ratio set register DIVR Start of counting (measurement): When a rising edge is detected soon after the start End of counting (measurement): When an interval ends after dividing In any mode, counting is not performed during the time from the start of counting to the input of the count start edge. When the count start edge is input, the timer is cleared to 0000H, and the timer counts until a count end edge is input. When a count end edge is entered, the following operations are executed: 1. Set the PWCSR's measurement end flag (EDIR) 2. Stop the timer count operation (except in cases when the edge is input for a restart) 3. In repeated measurement mode, the timer value (measurement result) is transferred to the PWCR, and the count operation is suspended until the next measurement start edge is entered. 4. In one-shot measurement mode, the measurement will end (unless restart is entered at the same time) If, in repeated measurement mode, pulse width measurement between all edges or divide measurement is performed, the end edge defines the next edge for measurement. ■ Minimum input pulse width The following restriction applies to pulses that are input to the pulse width measurement input pins (PWC2 to PWC0): • The pulse width must be four machine cycles or more (0.25 µs for a 16 MHz machine clock). ■ Pulse width/interval calculation method The pulse width/interval to be measured can be calculated with the following formula: TW = n x t / DIV [µ µs] Where TW: pulse width/interval to be measured [µs] n: measurement result data in PWCR t: count clock interval [µs] 298 CHAPTER 14 PWC TIMER DIV: divide ratio selected via the divide ratio register DIVR (use 1, except in divide frequency measurement mode) ■ Range for counting the pulse width/interval Depending on the selected combination of count clock and divide ratio of the input divider, the allowed pulse width/interval range for measurement will vary. Table 14.3-7 "List of pulse width measurement ranges" shows a list of measurement ranges when a machine clock (Φ, hereafter) of 16 MHz is applied. Table 14.3-7 List of pulse width measurement ranges Divide ratio No division Divide-by-4 Divide-by-16 Divide-by-64 Divide-by-256 DIV1 DIV0 CKS1,0=00 (Φ Φ/4) CKS1,0=00 (Φ Φ /16) CKS1,0=00 (Φ Φ /32) - - 0.25 µs to 16.38 ms [0.25 µs] 0.25 µs to 65.5 ms [1.6 µs] 0.25 µs to 131 ms [3.2 µs] 0 0 0.25 µs to 4.1 ms [6.25 µs] 0.25 µs to 16.38 ms [0.4 µs] 0.25 µs to 52.4 ms [0.8 µs] 0 1 0.25 µs to 1.024 ms [15.6 ns] 0.25 µs to 4.1 ms [1.6 µs] 0.25 µs to 13.1 ms [0.2 µs] 1 0 0.25 µs to 256 µs [3.91 µs] 0.25 µs to 1.024 ms [25 µs] 0.25 µs to 3.27 ms [50 ns] 1 1 0.25 µs to 64 µs [0.98 µs] 0.25 µs to 256 µs [6.25 µs] 0.25 µs to 817 µs [12.5 ns] Note: The value in [] indicates the resolution per bit. ■ Generation of interrupt requests In pulse width measurement mode, two types of interrupt requests can be generated, as listed below: ❍ Interrupt requests due to timer overflows If an overflow occurs due to incrementing in measurement mode, an overflow flag is set. If overflow interrupt requests are enabled, an interrupt request is generated. ❍ Interrupt requests due to the end of measurement If measurement end interrupt requests are enabled, an interrupt request is generated when a measurement end edge is detected and the PWCSR's measurement end flag (EDIR) is set. The measurement end flag EDIR is automatically cleared when the measurement result is read out from the PWCR. ■ Operational flow of pulse width measurement Figure 14.3-6 "Operational flow of pulse width measurement" shows the operational flow of pulse width measurement. 299 CHAPTER 14 PWC TIMER Various settings Figure 14.3-6 Operational flow of pulse width measurement Count clock selection Operation/measurement mode selection Interrupt flag clear Interrupt enable Restart Start with STRT bit Repeated measurement mode One-shot operation mode Measurement start edge detected Measurement start edge detected Clearing of timer Clearing of timer Start of counting Start of counting Incrementing Incrementing Overflow generated → OVIR flag set 300 Overflow → OVIR flag set Measurement end detected → EDIR flag set Measurement end detected → EDIR flag set Stop of counting Stop of counting Timer value transferred to PWCR Operation end CHAPTER 14 PWC TIMER 14.4 Notes on PWC Timer Usage This section provides notes on using the PWC timer. ■ Notes on PWC timer usage ❍ Notes on rewriting the register Overwriting the bits in the PWCSR is prohibited. Rewrite the register either before the timer is started or after the timer stops. • [Bits 7, 6] CKS1, CKS0 (clock selection) • [Bits 5, 4] PIS1, PIS0 (input signal selection) • [Bit 3] CKS1,CKS0 (clock selection) • [Bits 2, 1, 0] MOD2, MOD1, MOD0 (operation mode/measurement edge selection) • Rewriting DIVR during timer operation is prohibited. Rewrite it either before start or after stop of timer operation. ❍ Handling the measurement end flag in timer mode The value of the PWCSR's measurement end interrupt request flag (EDIR) is not significant in timer mode. Consequently, set the PWCSR's measurement end interrupt request bit (EDIE) to "0" if it is to be used in timer mode. ❍ Handling of STRT and STOP bits in the PWCSR Note that the meaning of these two bits is different depending on whether a write or read operation is performed (Refer to Section 14.2.1 "PWC Control/Status Register (PWCSR0 to PWCSR2)"). The read value returned in read-modify-write instructions is always 11B irrespective of the value of these bits. Be sure, therefore, not to use bit operation instructions for reading the operation state (these bits will always return "operation in progress"). However, bit operation instructions (such as bit clear) can be used for writing the STRT and STOP bits to start or stop the timer. ❍ Timer Clear In pulse width measurement mode, the timer is cleared at the measurement start edge. The timer data will therefore be invalid before the start of measurement. ❍ PWCR and timer values when the mode changes • If the timer is forcibly stopped and set to one-shot timer mode from reload timer mode, the timer value and the timer value stored in the PWCR will become unspecified. Be sure to define these values before using the timer. • If the timer is used in one-shot timer mode, the PWCR value is unspecified. Use the timer only after defining the value. • To switch the mode from pulse width measurement mode to timer mode, specify the PWCR value again before starting the timer. 301 CHAPTER 14 PWC TIMER ❍ Minimum pulse width The following restrictions apply to pulses that can be input to the pulse width measurement input pin. • Minimum pulse width: machine clock divided-by-2 (0.25 µs or more for 16 MHz machine clock) • Minimum input frequency: machine clock divided-by-4 (4 MHz or less for 16 MHz machine clock) If a pulse with lower width or higher frequency than specified above is input, correct operation cannot be assured. In the event that the input signal might contain noise, eliminate the noise using a filter externally from the chip before inputting the pulse. ❍ Divide frequency measurement mode In divide interval measurement mode, which is one of the pulse width measurement modes, the input pulse is divided. Note that the pulse width as calculated from the measurement results will therefore be an averaged value. ❍ Handling of clock selection bit Do not set [bits 7and 6] of the PWCR (clock selection bits CKS1 and CKS0) to 11B. ❍ Handling of reserved bit [bit 8] in the PWCR is reserved. If necessary, clear this bit by writing 0. ❍ Restart during operation Restarting after the count operation has been started may cause the following events depending on the timing of restart: • If, in reload timer mode, a restart occurs at the same time as an overflow: The restart is performed, but the overflow flag (OVIR) is set. • If, in pulse width one-shot measurement mode, a restart occurs at the same time as detection of a measurement end edge: Restart is performed when the measurement start edge wait state is entered, and the measurement end edge flag (EDIR) is set. • If, in pulse width repeated measurement mode, a restart occurs at the same time as measurement end edge detection: Restart is performed when the measurement start edge wait state is entered, but the measurement end edge flag (EDIR) is set and the measurement result is transferred to the PWCR. ❍ If the PWC timer is used in "H"-pulse or L- pulse width measurement mode of the repeated measurement mode If, after the end of pulse width measurement, the pulse width measurement start wait state is entered, the timer to be stopped might continue with the overflow flag (OVIR) being set before the pulse width measurement starts. In other words, even if no overflow occurs during the next pulse width measurement phase, the overflow flag may be set. Therefore, do not use the overflow flag when you use the PWC timer in "H"-pulse or "L"-pulse width measurement mode of repeated measurement mode. 302 CHAPTER 15 µ PG TIMER This chapter provides a block diagram of the µPG timer and explains the configuration and functions of its registers. 15.1 "Overview of µPG Timer" 15.2 "µPG Timer Registers" 15.3 "Timing Chart of µPG Timer" 303 CHAPTER 15 µPG TIMER 15.1 Overview of µ PG Timer The µPG timer is used to output pulses based on external input. ■ Block diagram of µPG timer Figure 15.1-1 "Block diagram of µPG timer" shows a block diagram of the µPG timer. Figure 15.1-1 Block diagram of µ PG timer MT00 MT01 Control circuit MT00 output latch Output enable 304 MT00 output latch EXTC CHAPTER 15 µPG TIMER 15.2 µPG Timer Registers This section describes the configurations of the registers used in the µPG timer and their functions. ■ Configuration of µ PG timer registers Figure 15.2-1 "Configuration of µPG timer registers" illustrates the configuration of the µPG timer registers. Figure 15.2-1 Configuration of µPG timer registers 7 6 5 4 3 00008EH PEN0 PE1 PE0 PMT1 PMT0 (R/W) (R/W) ((R/W))(R/W) (R/W) 2 (-) 1 (-) 0 (-) UPG Operation mode control register Initial value 00000----B ■ PG control/status register (PGCSR) The bit configuration of the PG control/status register (PGCSR) is shown below. 7 6 5 4 3 00008EH PEN0 PE1 PE0 PMT1 PMT0 (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) 2 (-) (-) 1 (-) (-) 0 (-) (-) PG Operation mode control register Reading/writing Initial value The functions of the bits in the PG control/status register (PGCSR) are listed below. [bit 7] PEN0 (operation enable) This bit is used to enable µPG timer operation. PEN0 • Function 0 Stop (retaining "L" level) (initial value) 1 PG operation allowed This bit is initialized at reset. [Bits 6, 5] PE1, PE0 (output enable) These bits are used to control the pulse output external pin. • PE1 PE0 Operation control function 0 0 General-purpose support pin (pulse output prohibited) (initial value) 0 1 MT00 pulse output pin only (output allowed) 1 0 MT01 pulse output pin only (output allowed) 1 1 MT00,MT01 pulse output pin (output allowed) These bits are initialized to 00B at reset. 305 CHAPTER 15 µPG TIMER [Bits 4, 3] PMT1,PMT0 (invert output) These bits are used to invert the output of each pulse. PMT1 PMT0 Operation control function 0 0 Waveform at the start (initial value) 0 1 Only MT00 inverted 1 0 Only MT01 inverted 1 1 MT00 and MT01 inverted • These bits are initialized to 00B at reset. • Reading and writing are allowed. [Bits 2, 1, 0] Undefined bits These bits are undefined and not used. In ordinary cases, set them to "000". 306 CHAPTER 15 µPG TIMER 15.3 Timing Chart of µPG Timer This section shows a timing chart for the µPG timer. ■ Timing chart of µ PG timer Figure 15.3-1 "Timing chart of input/output signals of the µPG timer" shows the timing chart of input and output signals for the µPG timer. Figure 15.3-1 Timing chart of input/output signals of the µPG timer Input waveform Output MT0 Output MT1 Inverted output MT0X Output MT1X ■ Notes on timing • Figure 15.3-1 "Timing chart of input/output signals of the µPG timer" shows the output waveform against the input waveform. The duty ratio is fixed at 50%. • In sync with the first rising pulse after start, the output starts from the 2nd rising pulse. • Two outputs for one input waveform are only issued using inversion control via the program. • For the input pulse (waveform at the EXTC pin), use an interval 10 times larger than one pulse of the internal clock (machine clock). • To write "11B" for the PE0 and PE1 of the PG control status register (allow output for all pins), keep the value at the input pin (EXTC) constant. Otherwise, if a pulse is input to the input pin (EXTC) when pin output is allowed, the width of the first output pulse may become shorter than that of the input pulse. 307 CHAPTER 15 µPG TIMER 308 CHAPTER 16 16-BIT RELOAD TIMER This chapter provides an overview of the 16-bit reload timer and its operation, and explains the configuration and functions of its registers. 16.1 "Overview of 16-Bit Reload Timer" 16.2 "16-Bit Reload Timer Registers" 16.3 "Operations of 16-Bit Reload Timer" 309 CHAPTER 16 16-BIT RELOAD TIMER 16.1 Overview of 16-Bit Reload Timer The 16-bit reload timer has two modes. In internal clock mode, countdown is performed in sync with one of three types of internal clocks. In event count mode, countdown is performed based on detection of any pulse edge input to the external pin. Either of these modes can be selected. ■ Outline of 16-bit reload timer For the 16-bit reload timer, an underflow is defined as an event where the count value changes from 0000H to FFFFH. Thus, counting (incrementing the value in the reload register by 1) will eventually generate an underflow. For the count operation, either reload mode, where an underflow causes repeated counting by reloading the count set value, or one-shot mode, where an underflow will stop counting, can be selected. A counter underflow can be used to generate an interrupt, which supports DTC. 310 CHAPTER 16 16-BIT RELOAD TIMER 16.1.1 Functions of the 16-Bit Reload Timer This section describes the functions of the 16-bit reload timer. ■ Operation modes of the 16-bit reload timer Clock mode Counting Reload mode Internal clock mode One-shot mode Event count mode (External clock mode) 16-bit reload timer operation Software trigger operation External trigger operation External gate input operation Reload mode Software trigger operation One-shot mode ■ Internal clock mode One type of counter clock can be selected among three types of internal clocks to enable the following operations: ❍ Software trigger operation Sets the TRG bits of the timer control status register (TMCSR) to "1" to start a counting operation. Trigger input can also be enabled by the TRG bit when external trigger input and external gate input are performed. ❍ External trigger operation Starts counting as soon as the selected edge (rising, falling edges, or both) is input to the TIN0 or TIN1 pin. ❍ External gate input operation Continues counting if a signal of the selected signal level ("L" or "H") is input to the TIN0 or TIN1 pin. ■ Event count mode (external clock mode) A mode in which countdown starts as soon as a signal with a valid edge selected (rising, falling, or both) is input to the TIN0 or TIN1 pin. This can also be used to provide an interval timer if an external clock with constant interval time is used. 311 CHAPTER 16 16-BIT RELOAD TIMER ■ Counter operation modes ❍ Reload mode If countdown causes an underflow("0000H" --> "FFFFH"), the specified count value is reloaded to continue with counting. An underflow can generate an interrupt request that can then be used to provide an interval timer. A toggle waveform that reverses itself at every underflow is output from the TOT0 pin. Count clock Internal clock External clock Count clock interval Interval time 21/ φ (0.125 µs) 0.125 µs to 8.192 ms 23/ φ (0.5 µs) 0.5 µs to 32.768 ms 25/ φ (2.0 µs) 2.0 µs to 131.1 ms 23/ φ (0.5 µs) 0.5 µs or more ❍ One-shot mode If countdown generates an underflow ("0000H" --> "FFFFH"), counting will stop. An underflow can be used to generate an interrupt. While counting is in progress, a square wave that indicates that counting is in progress is output from the TOT0 pin. Reference: The 16-bit reload timer can be used to trigger A/D converter operation. 312 CHAPTER 16 16-BIT RELOAD TIMER 16.1.2 Block Diagram of the 16-Bit Reload Timer This section shows a block diagram of the 16-bit reload timer. ■ Block diagram of the 16-bit reload timer Figure 16.1-1 Block diagram of the 16-bit reload timer Internal data bus TMRLR 16-bit reload register Reload signal TMR Reload control circuit 16-bit timer register (down-counter) UF CLK Count clock generation circuit Machine clock frequency φ 3 Prescaler Gate input Circuit to determine which clock is valid Clear Wait signal CLK To A/D converter Output signal generation circuit Pin (TIN0) Reversed Input control circuit Output signal generation circuit Clock selector External clock Function selection 3 Selection signal Pin (TOT0) EN 2 OUTL RELD Operation control circuit OUTE Timer control status register (TMCSR) 313 CHAPTER 16 16-BIT RELOAD TIMER 16.2 16-Bit Reload Timer Registers This section describes the configuration and functions of the registers used in the 16bit reload timer. ■ List of registers Figure 16.2-1 "16-bit reload timer registers" shows the registers of the 16-bit reload timer. Figure 16.2-1 16-bit reload timer registers 0000CBH 0000CAH 0000CDH 0000CCH 314 15 (-) (-) 14 (-) (-) 13 (-) (-) 12 (-) (-) 11 10 9 8 CSL1 CSL0 MOD2 MOD1 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) TMCSR Timer control status register (upper bits) Reading/writing Initial value 7 6 5 4 3 2 1 0 TMCSR MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register(lower bits) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (0) (0) (0) Initial value 15 14 13 12 11 10 9 8 TMR/TMRLR D15 D14 D13 D12 D11 D10 D09 D08 TMR/TMRLR (upper bits) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (X) (X) (X) (X) (X) (X) (X) (X) Initial value 7 6 5 4 3 2 1 0 TMR/TMRLR D07 D06 D05 D04 D03 D02 D01 D00 TTMR/TMRLR (lower bits) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (X) (X) (X) (X) (X) (X) (X) (X) Initial value CHAPTER 16 16-BIT RELOAD TIMER 16.2.1 Timer Control Status Register (TMCSR) This section describes the configuration and functions of the timer control status register (TMCSR). ■ Timer control status register (TMCSR) The timer control status register (TMCSR) is used to control the operation mode and interrupts of the16-bit reload timer. If CNTE = 0, bits other than UF/CNTE/TRG are modified. The figure below shows the bit configuration of the timer control status register (TMCSR). 0000CBH 0000CAH 15 (-) (-) 14 (-) (-) 13 (-) (-) 12 (-) (-) 11 10 9 8 CSL1 CSL0 MOD2 MOD1 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) TMCSR Timer control status register (upper bits) Reading/writing Initial value 7 6 5 4 3 2 1 0 TMCSR MOD0 OUTE OUTL RELD INTE UF CNTE TRG Timer control status register(lower bits) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (0) (0) (0) Initial value The functions of the bits in the timer control status register (TMCSR) are described below. [Bits 11, 10] CSL1, CLS0 (Clock selection) These bits are used to select the clock source using the count clock selection bit. Clock source (machine clock: φ = 16 MHz) CSL1 CSL0 0 0 φ/21 (0.125 µs) (initial value) 0 1 φ/23 (0.5 µs) 1 0 φ/25 (2.0 µs) 1 1 Event count mode [Bits 9, 8, 7] MOD2, MOD1, MOD0 These bits are used to set the operation mode and functions of the input/output pin functions. With MOD2 = 0, the input pin operates as a trigger. If an active edge is input to the input pin while count operation is in progress, the data from the reload register is loaded into the counter. With MOD2 = 1, the timer operates in gate counter mode and the input pin operates as a gate input. In this mode, the counter only counts when the active level is applied to the input pin. By combination of the MOD2 to MOD0 bits, the internal clock mode and event counter mode are selected from the modes listed in Table 16.2-1 "Internal clock mode (CLS1/0 = "00", "01", or "10")" and Table Table 16.2-2 "Event counter mode (CLS1, 0 = "11")". 315 CHAPTER 16 16-BIT RELOAD TIMER Table 16.2-1 Internal clock mode (CLS1/0 = "00", "01", or "10") MOD2 MOD1 MOD0 0 0 0 0 0 1 0 1 0 0 1 1 1 X 0 Input pin function Active edge or level Trigger invalid - Initial value Rising edge Trigger input Falling edge Both edges "L" level Gate input 1 X 1 "H" level Table 16.2-2 Event counter mode (CLS1, 0 = "11") MOD2 MOD1 MOD0 X 0 0 X 0 1 X 1 0 X 1 1 Input pin function Trigger invalid Active edge or level - Initial value Rising edge Trigger input Falling edge Both edges [Bit 6] OUTE (Output enable) This bit is used to control output enable. The TOT pin operates as a general-purpose port if the OUTE bit is set to "0", or as a timer output if the OUTE bit is set to "1". In reload mode, the output waveform becomes a toggle waveform. In one-shot mode, the TOT pin outputs a square wave that indicates that counting is in progress. OUTE Function 0 General-purpose port (initial value) 1 Timer output [Bit 5] OUTL (Output level) This bit is used to specify the output level of the TOT pin. Depending on whether OUTL is set to "0" or "1", the output pin level becomes reversed. 316 OUTL One-shot mode (RELD = 0) Reload mode (RELD = 1) 0 Square wave of "H"-level in counting mode 0 1 Square wave of "L" level in counting mode 1 X 1 0 X 1 1 Initial value CHAPTER 16 16-BIT RELOAD TIMER [Bit 4] RELD (Reload operation enable) This bit is used to enable reload operation. With RELD set to "1", the timer operates in reload mode. In this mode, the timer loads the reload register data into the counter and continues counting if an underflow occurs (when the counter value changes from 0000H to FFFFH). With RELD set to "0", the timer operates in one-shot mode. If an underflow occurs in this mode because the counter value changes from 0000H to FFFFH, counter operation stops. RELD Function 0 One-shot mode (initial value) 1 Reload mode [Bit 3] INTE (Timer interrupt request enable) This bit is used to enable timer interrupt requests. With INTE = 0, no interrupt request is generated even if UF is set to "1". INTE Function 0 Interrupt request output prohibited (initial value) 1 Interrupt request output allowed [Bit 2] UF (Timer interrupt request flag) This bit is used as a timer interrupt request flag. If an underflow occurs, UF is set to "1". It is cleared by writing "0" or by µDMA. Writing "1" has no effect. Read-modify-write instruction always return "1". UF At reading At writing 0 No counter underflow (initial value) This bit is cleared (initial value) 1 Counter underflow generated No change (no effect on operation) [Bit 1] CNTE (Timer counter enable) This bit is used to enable the timer counter. CNTE Function 0 Counter stopped (initial value) 1 Counter operation allowed (start trigger wait) 317 CHAPTER 16 16-BIT RELOAD TIMER [Bit 0] TRG (Software trigger) This bit operates as a software trigger bit. With TRG set to 1, a software trigger is applied to load the data from the timer reload register into the counter and to start counting. Writing "0" has no effect. Read operations always return "0". Only when CNTE = 1, this bit is valid irrespective of the operation mode. TRG 318 Function 0 No change (no effect on operation) (initial value) 1 Count operation start CHAPTER 16 16-BIT RELOAD TIMER 16.2.2 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) This section describes the configuration and functions of the 16-bit timer register (TMR)/16-bit reload register (TMRLR). ■ 16-Bit timer register (TMR)/16-bit reload register (TMRLR) The bit configuration of the 16-bit timer register (TMR)/16-bit reload register (TMRLR) is shown below. 0000CDH 15 14 13 12 11 10 9 8 D15 D14 D13 D12 D11 D10 D09 D08 TMR/TMLR (upper bits) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (X) (X) (X) (X) (X) (X) (X) (X) Initial value 7 6 5 4 3 2 1 0 0000CCH D07 D06 D05 D04 D03 D02 D01 D00 TMR/TMRLR (lower bits) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (X) (X) (X) (X) (X) (X) (X) (X) Initial value ■ 16-Bit timer register (TMR) This register is used to read the counter value of the 16-bit decrement counter. If counter operation is enabled (TMCSR: CNTE = 1) and counting starts, the value in the 16-bit reload register is loaded into this register to start count-down. In count stop state (TMCSR: CNTE = 0), the value of this register is retained. Note: This register can be read during counter operation, but always use a word transfer instruction (such as "MOVW A 003AH"). The 16-bit timer register (TMR) is functionally a read-only register, though it is allocated at the same address as the write-only 16-bit reload register (TMRLR). Thus, write operations will not affect the TMR value, even though writing to TMRLR is performed. 319 CHAPTER 16 16-BIT RELOAD TIMER ■ 16-Bit reload register (TMRLR) Regardless of the 16-bit reload timer operation, set this register to the initial counter value while counter operation is disabled (TMCSR: CNTE=0). When the counter is started by enabling counter operation (TMCSR: CNTE=1), the count-down will start from the value that was written to this register. The value set in this register is reloaded in reload mode if an underflow occurs, and count-down continues. In one-shot mode, the counter stops at FFFFH if an underflow occurs. Note: Write to this register only in counter stop mode (TMCSR: CNTE = 0), and always by using a word transfer instruction (such as "MOVW A 003AH"). The 16-bit reload register (TMRLR) is functionally a write-only register; however, it is allocated at the same address as the read-only 16-bit timer register (TMR). Thus, the valid returned value in read operations is the value of the TMR value. Read-modify-write (RMW) instructions (such as the INC or DEC instructions) cannot be used. 320 CHAPTER 16 16-BIT RELOAD TIMER 16.3 Operations of the 16-Bit Reload Timer This section describes the settings of the 16-bit reload timer and the state transitions during counter operation. ■ Settings of the 16-bit reload timer ❍ Settings for internal clock mode For interval timer operation, the settings shown in Figure 16.3-1 "Settings of internal clock mode" are required. Figure 16.3-1 Settings of internal clock mode 15 - TMCSR 14 13 12 - - - 11 10 9 8 7 6 5 4 3 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE 2 UF 1 0 CNTE TRG 1 Other than "11" Initial counter value setting (reload value) TMRLR : Bit used 1 : Set to 1 ❍ Settings for event counter mode For event counter mode operation, the settings shown in Figure 16.3-2 "Settings of event counter mode" are required. Figure 16.3-2 Settings of event counter mode 15 TMCSR - 14 13 12 - - - 11 10 9 8 7 6 5 4 3 CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE 2 UF 1 0 CNTE TRG 1 Other than "11" Initial counter value setting (reload value) TMRLR DDR9 : Bit used 1 : Set to 1 : Set the bit corresponding to the used pin to "0." 321 CHAPTER 16 16-BIT RELOAD TIMER 16.3.1 State Transitions During Counter Operation This section describes the state transitions during counter operation. ■ State transitions during counter operation Figure 16.3-3 State transition during counter operation STOP state CNTE=0, WAIT=1 TIN pin: Input disabled TOT pin: General-purpose input/output port 16-bit timer register: Retains the value at stop. Not specified immediately after reset Reset CNTE=0 CNTE=0 CNTE=1 TRG=0 WAIT state CNTE=1, WAIT=1 TIN pin: Valid for trigger input only TOT pin: 16-bit reload register value output 16-bit timer register: Retains the value at stop. Not specified until loading after reset TRG=1 (Software trigger) External trigger from TIN CNTE=1 TRG=1 UF=1 & RELD=0 (One-shot mode) 16-bit timer register: Count operation UF=1 & RELD=1 TRG=1 (Reload mode) (Software trigger) LOAD CNTE=1, WAIT=0 Loads the 16-bit reload register value Load end into the 16-bit timer register : State transition by hardware : State transition by register access WAIT : WAIT signal (internal signal) TRG : Software trigger bit (TMCSR) CNTE : Timer counter enable bit (TMCSR) : Timer interrupt request flag bit (TMCSR) UF RELD : Reload operation enable bit (TMCSR) 322 RUN state CNTE=1, WAIT=0 TIN pin: Functions as input pin of the 16-bit reload timer TOT pin: Functions as output pin of the 16-bit reload timer CHAPTER 16 16-BIT RELOAD TIMER 16.3.2 Operations of Internal Clock Mode (Reload Mode) The counter operates in sync with the internal count clock to count down the 16-bit counter and generate an interrupt request in case of counter underflow. The counter also outputs a toggle waveform from the timer output pin. ■ Operations of internal clock mode (reload mode) If, with count operation enabled (TMCSR: CNTE = 1), the software trigger bit (TMCSR: TRG) or external trigger is set to start the timer, the value in the reload register (TMRLR) is loaded into the counter, and counter operation starts. If both the counter enabled bit and the software trigger bit become "1" at the same time, counting will start as soon as counter operation is enabled. If the counter value causes an underflow(0000H --> FFFFH), the value in the 16-bit reload register (TMRLR) is loaded into the counter to continue with the counting operation. At this time, the underflow interrupt request flag bit (UF) is set to "1", and if the interrupt request enable bit (INTE) is set to "1", an interrupt request is generated. It is also possible to output a toggle waveform that is inverted at every underflow via the TOT pin. ❍ Software trigger operation With the TRG bit of the timer control status register (TMCSR) set to "1", the counter starts. Figure 16.3-4 "Count operation in reload mode (software trigger operation)" shows the software trigger operation for a reload. Figure 16.3-4 Count operation in reload mode (software trigger operation) Count clock Reload data Counter -1 0000H Reload data -1 0000H Reload data -1 0000H Reload data -1 Data load signal UF bit CNTE bit TRG bit T* TOT pin T : Machine cycle * : The time from trigger input to loading the reload data is 1T. 323 CHAPTER 16 16-BIT RELOAD TIMER ❍ External trigger operation The counter starts if a valid edge (either rising or falling can be selected) is input to the TIN pin. Figure 16.3-5 "Count operation in reload mode (external trigger operation)" shows the external trigger operation in reload mode. Figure 16.3-5 Count operation in reload mode (external trigger operation) Count clock Counter Reload data -1 0000H Reload data -1 0000H Reload data 0000H Reload data -1 -1 Data load signal UF bit CNTE bit TIN pin * TOT pin 2T to 2.5T T : Machine cycle * : The time from trigger input to loading the reload data is 1T. Note: The trigger pulse width input to the TIN pin shall be 2/φ or more. ❍ Gate input operation Counting starts when the software trigger bit (TRG) is set to "1" while the count enable bit (CNTE) of the timer control status register (TMCSR) is set to "1". Counting starts when a valid level ("L" level or "H" level can be selected) of gate input specified in the operation mode setting bits(MOD2, MOD1, and MOD0) is input to the TIN pins. Figure 16.3-6 Count operation in reload mode (software trigger, gate input operation) Count clock Counter Reload data -1 -1 -1 0000H Reload data -1 -1 Data load signal UF bit CNTE bit TRG bit TIN pin TOT pin T : Machine cycle *1: It takes 1T from trigger input to loading reload data. Note: The trigger pulse width input to the TIN pin shall be 2/φ or more. 324 CHAPTER 16 16-BIT RELOAD TIMER 16.3.3 Internal Clock Mode (One-Shot Mode) The counter is in synchronization with the internal count clock in this mode to count down the 16-bit counter and generate an interrupt request to the CPU at counter underflow. It also outputs a square wave from the TOT pin to indicate that counting is in progress. ■ Operation of Internal Clock mode (One-Shot Mode) When count operation is allowed (TMCSR: CNTE=1) and the timer is started by the software trigger bit (TMCSR: TRG) or external trigger, count operation will start. When both the count enable bit and software trigger bit are set to "1", counting will start at the same time counting becomes enabled. If the counter value causes an underflow (0000H --> FFFFH), the counter stops at FFFFH, and the underflow flag bit for interrupt requests (UF) is set to "1". If the enable bit for interrupt request (INTE) is set to "1", an interrupt request is generated. The TOT pin outputs a square wave to indicate that counting is in progress. ❍ Software Trigger Operation The counter will start as soon as the TRG bit of the timer control status registers (TMCSR) is set to "1". Figure 16.3-7 "Count operation in one-shot mode (software trigger operation)" shows the software trigger operation in one-shot mode. Figure 16.3-7 Count operation in one-shot mode (software trigger operation) Count clock Counter Reload data -1 0000H FFFFH -1 Reload data 0000H FFFFH Data load signal UF bit CNTE bit TRG bit TOT pin Waiting for start trigger input T : Machine cycle *1: It takes 1T from trigger input to loading reload data. 325 CHAPTER 16 16-BIT RELOAD TIMER ❍ External trigger operation When a valid edge (leading, trailing, or both can be selected) is input to the TIN pins, the counter will start operation. Figure 16.3-8 "Count operation in one-shot mode (external trigger operation)" shows the external trigger operation in one-shot mode. Figure 16.3-8 Count operation in one-shot mode (external trigger operation) Count clock Counter Reload data -1 0000H FFFFH Reload data -1 0000H FFFFH Data load signal UF bit CNTE bit TIN bit 2T to 2.5T TOT pin Waiting for start trigger input T: Machine cycle *1: It takes 2T to 2.5T from trigger input to loading reload data. Note: The trigger pulse width input to the TIN pin shall be 2/φ or more. ❍ Gate input operation When a valid level ("H" and "L" level can be selected) is input to the TIN pin, the counter starts operation. Figure 16.3-9 "Count operation in one-shot mode (software trigger, gate input operation)" shows the gate input operation in one-shot mode. Figure 16.3-9 Count operation in one-shot mode (software trigger, gate input operation) Count clock Counter Reload data -1 0000H FFFFH Reload data -1 0000H FFFFH Data load signal UF bit CNTE bit TRG bit TOT pin Waiting for start trigger input T : Machine cycle *1: It takes 1T from trigger input to loading reload data. Note: The trigger pulse width input to the TIN pin shall be 2/φ or more. 326 CHAPTER 16 16-BIT RELOAD TIMER 16.3.4 Event Count Mode In this mode, the counter counts input edges from the TIN pin to count down the 16-bit counter and generate an interrupt request to the CPU when a counter underflow occurs. The TOT pin can output either a toggle waveform or a square wave. ■ Event Count mode When count operation is allowed (TMCSR: CNTE=1) to start the counter (TMCSR: TRG=1), data from the 16-bit reload registers (TMRLR) is loaded into the counter for a countdown whenever a valid edge (leading or trailing can be selected) of pulses (external count clock) input to the TIN pin is detected. When both the count enable bit and software trigger bit are set to "1", counting will start as soon as counting becomes enabled. Operation in reload mode If the counter value has an underflow (0000H --> FFFFH), data from the 16-bit reload registers (TMRLR) is loaded into the counter to continue counting. In this case, an interrupt request is issued when the underflow flag bit for interrupt requests (UF) and enable bit for interrupt requests (TMCSR: INTE) are both set to "1". The TOT pin outputs a toggle waveform, which is reversed at every occurrence of underflow. Figure 16.3-10 "Count operation in reload mode (event count mode)" shows the counting operation in reload mode. Figure 16.3-10 Count operation in reload mode (event count mode) TIN pin Reload data Counter -1 0000H Reload data -1 0000H Reload data -1 0000H Reload data -1 Data load signal UF bit CNTE bit TRG bit *1 T TOT pin T: Machine cycle *1: It takes 1T from trigger input to loading reload data. Note: Both the "H" width and "L" width of clock input to the TIN pin shall be 4/φ or more. 327 CHAPTER 16 16-BIT RELOAD TIMER ❍ Operation in one-shot mode If the counter value causes an underflow (0000H --> FFFFH), the counter stops at FFFFH. In this case, the underflow request flag bit (UF) is set to "1". If the interrupt request output enable bit (INTE) is also set to "1", an interrupt request is generated. The TOT pin outputs a square wave that indicates counting in progress. Figure 16.3-11 "Counter operation in one-shot mode (event count mode)" shows the counter operation in one-shot mode. Figure 16.3-11 Counter operation in one-shot mode (event count mode) TIN pin Reload data Counter -1 0000H FFFFH -1 Reload data 0000H FFFFH Data load signal UF bit CNTE bit TRG bit {1 T TOT pin Waiting for start trigger input T : Machine cycle *1: It takes 1T from trigger input to loading reload data. Note: Both the "H" width and "L" width of clock input to the TIN pin shall be 4/φ or more. 328 CHAPTER 17 8/16-BIT PPG TIMER This chapter provides an overview of the 8/16-bit PPG timer and its operation, and explains the configuration and functions of its registers. 17.1 "Overview of 8/16-Bit PPG Timer" 17.2 "8/16-Bit PPG Timer Registers" 17.3 "Operations of 8/16-Bit PPG Timer" 329 CHAPTER 17 8/16-BIT PPG TIMER 17.1 Overview of 8/16-bit PPG Timer The 8/16-bit PPG timer is an 8-bit reload timer module used to output pulses based on the timer operation for PPG output. On the hardware level, the timer consists of six 8-bit decrement counters, twelve 8-bit reload timers, three 16-bit control registers, six external pulse output pins and six interrupt outputs. The MB90470 has six channels that can be used for 8-bit PPG, enabling paired operation of PPG0/PPG1, PPG2/PPG3, and PPG4/PPG5 for 16-bit PPG operation (3 channels). ■ Outline of 8/16-bit PPG timer specifications An outline of the 8/16-bit PPG timer functions is listed below: ❍ 8-bit PPG output 6 channel independent operation mode Provides independent PPG output operation with six channels. ❍ 16-bit PPG output operation mode Provides 16-bit PPG output operation with three channels. This is achieved by combining PPG0 + PPG1, PPG2 + PPG3 and PPG4 + PPG5. ❍ 8 + 8-bit PPG output operation mode PPG0 (PPG2/PPG4) output is used as PPG1 (PPG3/PPG5) clock input, enabling an arbitrary interval to be used for 8-bit PPG output. ❍ PPG output operation Provides an arbitrary interval and duty ratio for pulse wave output. Used in combination with an externally attached circuit for providing a D/A converter. 330 CHAPTER 17 8/16-BIT PPG TIMER 17.1.1 Block Diagram of the 8/16-Bit PPG Timer Block diagrams of channels 0/2/4 and channels 1/3/5 of the 8/16-bit PPG timer are shown below. ■ Block diagram of the 8/16-bit PPG timer Figure 17.1-1 "Block diagram of the 8/16-bit PPG timer (channels 0/2/4)" shows a block diagram of channels 0,2, and 4. Figure 17.1-2 "Block diagram of the 8/16-bit PPG timer (channels 1/3/5)" shows a block diagram of channels 1,3, and 5. Figure 17.1-1 Block diagram of the 8/16-bit PPG timer (channels 0/2/4) Peripheral clock: divide-by-16 PPG0/2/4 output allowed Peripheral clock: divide-by-8 Peripheral clock: divide-by-4 Peripheral clock: divide-by-2 Peripheral clock PPG0/2/4 A/D converter PPG0/2/4 output latch PEN0 S R Q IRQ PCNT(down-counter) ch1/3/5 borrow L/H selector Count clock select PUF0 Timebase counter output Main clock: divide-by-512 PIE0 L/H select PRLL PRLBH PPGC0 (operation mode control) PRLL L data bus H data bus 331 CHAPTER 17 8/16-BIT PPG TIMER Figure 17.1-2 Block diagram of the 8/16-bit PPG timer (channels 1/3/5) Peripheral clock: divide-by-16 Peripheral clock: divide-by-8 Peripheral clock: divide-by-4 PPG1/3/5 output enable PPG1/3/5 Peripheral clock: divide-by-2 Peripheral clock A/D converter PPG1/3/5 output latch PEN1 S R Q IRQ PCNT (down-counter) L/H selector Count clock select PUF0 Timebase counter output Main clock: divide-by-512 PIE0 L/H select PRLL PRLBH PPGC1 (operation mode control) PRLL L data bus H data bus 332 CHAPTER 17 8/16-BIT PPG TIMER 17.2 8/16-bit PPG Timer Registers This section describes the configuration and functions of the registers used in the 8/ 16-bit PPG timer. ■ List of 8/16-bit PPG timer registers Figure 17.2-1 "List of 8/16-bit PPG timer registers" shows a list of the registers of the 8/16-bit PPG timer. Figure 17.2-1 List of 8/16-bit PPG timer registers 7 00003AH 00003CH PEN0 00003EH (R/W) (0) 6 (-) (X) 5 4 3 PE00 PIE0 PUF0 (R/W) (R/W) (R/W) (0) (0) (0) 2 (-) (X) 1 0 PPGC0/2/4 - Reserved Operation mode control register (-) (-) Reading/writing (X) (1) Initial value 00003BH 15 00003DH PEN1 00003FH (R/W) (0) 14 (-) (X) 13 12 11 10 9 8 PE10 PIE1 PUF1 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (-) (0) (0) (0) (0) (0) (1) 7 6 5 4 3 2 1 0 000040H 000042H PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved 000044H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) PPGC1/3/5 Operation mode control register Reading/writing Initial value PPG01/PPG23/PPG45 Output control register Reading/writing Initial value 00002EH 000030H 7 6 5 4 3 2 1 0 PPLL0 to -5 000032H D07 D06 D05 D04 D03 D02 D01 D00 Reload register "L" 000034H 000036H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing 000038H (X) (X) (X) (X) (X) (X) (X) (X) Initial value 00002FH 15 14 13 12 11 10 9 8 PPLH0 to -5 000031H 000033H D15 D14 D13 D12 D11 D10 D09 D08 Reload register "H" 000035H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing 000037H (X) (X) (X) (X) (X) (X) (X) Initial value 000039H (X) 333 CHAPTER 17 8/16-BIT PPG TIMER 17.2.1 PPG0/2/4 Operation Mode Control Register (PPGC0) This section describes the configuration and functions of the PPG0/2/4 operation mode control register (PPGC0). ■ PPG0/2/4 operation mode control register (PPGC0) The PPG0/2/4 operation mode control register (PPGC0) is used to select the channel 0/2/4 operation mode, control the pin output, select the count clock, and control the trigger. The bit configuration of the PPG0/2/4 operation mode control register (PPGC0) is shown below. 7 00003AH 00003CH PEN0 00003EH (R/W) (0) 6 (-) (X) 5 4 3 PE00 PIE0 PUF0 (R/W) (R/W) (R/W) (0) (0) (0) 2 (-) (X) 1 0 PPGC0/2/4 - Reserved Operation mode control register (-) (-) Reading/writing (X) (1) Initial value The functions of the PPG0/2/4 operation mode control register (PPGC0) are described below. [Bit 7] PEN0: ppg Enable (operation enable) This bit is used to start PPG operation and select the operation mode. PEN0 Operation state 0 Operation stop ("L" level output is retained) 1 PPG operation enable • With this bit is set to "1", the PPG starts counting. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [Bit 5] PE00: ppg output enable 00 (PPG0/2/4 output pin enable) This bit is used to allow/prohibit pulse output via the pulse output external pin PPG0/2/4. 334 PE00 Operation state 0 General-purpose support pin (pulse output prohibited) 1 PPG0/2/4 pulse output (pulse output allowed) • This bit is initialized to "0" at reset. • Reading and writing are allowed. CHAPTER 17 8/16-BIT PPG TIMER [Bit 4] PIE0:ppg Interrupt enable (PPG interrupt enable) This bit is used to allow or prohibit PPG interrupts. PIE0 Operation state 0 Interrupts prohibited 1 Interrupts allowed • If PUF0 is changed to "1" while this bit is "1", an interrupt request is generated. If this bit is "0", no interrupts are generated. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [Bit 3] PUF0: ppg Underflow Flag (PPG counter underflow) This bit indicates the result of a PPG counter underflow detection. PUF0 Operation state 0 No PPG counter underflow detected 1 PPG counter underflow detected In 8-bit PPG6 channel mode (PPG0/1,PPG2/3,PPG4/5) and 8-bit prescaler/8- bit PPG mode, this bit is set to "1" if an underflow occurs because the counter value for channel 0/2/4 changes from 00H to FFH. In 16-bit PPG3 channel mode (PPG0/PPG1, PPG2/PPG3, PPG4/PPG5), this bit is set to "1" if the counter value of channel 1, 3, 5 or channel 0, 2, 4 changes from 0000H to FFFFH. Writing "0" clears this bit to "0". Writing "1" has no effect. Read-modify-write type instructions always return "1". • This bit is initialized to "0" at reset. • Reading and writing are allowed. [Bit 0] reserved bit This bit is reserved. When setting PPGC0, always set this bit to "1". 335 CHAPTER 17 8/16-BIT PPG TIMER 17.2.2 PPG1/3/5 Operation Mode Control Register (PPGC1) This section describes the configuration and functions of the PPG1/3/5 operation mode control register (PPGC1). ■ PPG1/3/5 operation mode control register (PPGC1) The PPG1/3/5 operation mode control register (PPGC1) is used to select the channel 1/3/5 operation mode, control pin output, and select the count clock. It is also used for trigger control. The bit configuration of the PPG1/3/5 operation mode control register (PPGC1) is shown below. 00003BH 15 00003DH PEN1 00003FH (R/W) (0) 14 (-) (X) 13 12 11 10 9 8 PE10 PIE1 PUF1 MD1 MD0 Reserved (R/W) (R/W) (R/W) (R/W) (R/W) (-) (0) (0) (0) (0) (0) (1) PPGC1/3/5 Operation mode control register Reading/writing Initial value The functions of the bits in the PPG1/3/5 operation mode control register (PPGC1) are described below. [Bit 15] PEN1: ppg Enable (operation enable) This bit is used to start PPG operation and select the operation mode. PEN0 Operation state 0 Operation stop ("L" level output is retained) 1 PPG operation enabled • When this bit is set to "1", PPG count starts. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [Bit 14] PE10: ppg output Enable 10 (PPG1/3/5 output pin enable) This bit is used to allow or prohibit pulse output to the pulse output external pin PPG1/3/5. PE00 336 Operation state 0 General-purpose port (pulse output prohibited) 1 PPG1/3/5 pulse output (pulse output allowed) • This bit is initialized to "0" at reset. • Reading and writing are allowed. CHAPTER 17 8/16-BIT PPG TIMER [Bit 12] PIE1: ppg Interrupt Enable (PPG interrupt enable) This bit is used to prohibit or allow PPG interrupts. PIE0 Operation state 0 Interrupts prohibited 1 Interrupts allowed If PUF0 is set to "1" when this bit is"1", an interrupt request is generated. When this bit is "0", no interrupts are generated. • This bit is initialized to "0" at reset. • Reading and writing are allowed. [Bit 11] PUF1: ppg Underflow Flag (PPG counter underflow) This bit is used to indicate the result of PPG counter underflow detection. PUF0 Operation state 0 No PPG counter underflow detected 1 PPG counter underflow detected In 8-bit PPG6 channel mode (PPG0/1,PPG2/3,PPG4/5) and 8-bit prescaler + 8-bit PPG mode, this bit is set to "1" when an underflow occurs because the counter value of channel 1, 3, 5 changes from 00H to FFH. In 16-bit PPG3 channel mode (PPG0/PPG1, PPG2/PPG3, PPG4/ PPG5), this bit is set to "1" when an underflow occurs because the counter value of channel 1, 3, 5 or channel 0, 2, 4 changes from 0000H to FFFFH. Writing "0" clears this bit to "0". Writing "1" has no effect. Read-modify-write type instructions will always return "1". • This bit is initialized to "0" at reset. • Reading and writing are allowed. 337 CHAPTER 17 8/16-BIT PPG TIMER [Bit 10, 9] MD1, 0: ppg count Mode (operation mode selection) These bits are used to select the PPG timer operation mode. MD1 MD0 Operation mode 0 0 8-bit PPG2 channel independent mode (x 3) 0 1 8-bit prescaler/8-bit PPG1ch 1 0 Reserved (setting prohibited) 1 1 16-bit PPG1 channel mode (x 3) • This bit is initialized to "0" at reset. • Reading and writing are allowed. Note: • Do not set these bits to "10". • To set these bits to "01", do not separately set the PEN0 bit of PPGC0 to "0" and the PEN1 bit of PPGC1 bit to "1". It is recommended that the PEN0 bit and the corresponding PEN1 bit be set to "11" or "00" at the same time. • To set these bits to "11", rewrite the contents of PPGC0/PPGC1 by word transfer and set the PEN0/PEN1 bits to "11" or "00" at the same time. [Bit 8] reserved bit This bit is reserved. When setting PPGC1, always set this bit to "1". 338 CHAPTER 17 8/16-BIT PPG TIMER 17.2.3 PPG0 to PPG5 Output Control Registers (PPG0/1, PPG2/3, PPG4/5) This section describes the configuration and functions of the PPG0 to PPG5 output control registers (PPG0/1, PPG2/3, PPG4/5). ■ PPG0 to PPG5 output control registers (PPG0/1, PPG2/3, PPG4/5) The bit configuration of the PPG0 to 5 output control registers (PPG0/1, PPG2/3, PPG4/5) is described below. 7 6 5 4 3 2 1 0 000040H 000042H PCS2 PCS1 PCS0 PCM2 PCM1 PCM0 Reserved Reserved 000044H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) (0) (0) (0) (0) PPG0/1, PPG2/3, PPG4/5 Output control register Reading/writing Initial value The functions of the bits in the PPG0 to PPG5 output control registers (PPG0/1, PPG2/3, PPG4/ 5) are described below. [Bits 7, 6, 5] PCS2 to 0:ppg Count Select (count clock selection) These bits are used to select the operation clock for the down counter of channels 1, 3, and 5. PCS2 PCS1 PCS0 Operation mode 0 0 0 Peripheral device clock (62.5 ns machine clock for 16 MHz) 0 0 1 Peripheral device clock/2 (125 ns machine clock for 16 MHz) 0 1 0 Peripheral device clock/4 (250 ns machine clock for 16 MHz) 0 1 1 Peripheral device clock/8 (500 ns machine clock for 16 MHz) 1 0 0 Peripheral device clock/16 (1 µs machine clock for 16 MHz) 1 1 1 Input clock from the timebase counter (29 x 250 ns = 128 µs oscillation for 4 MHz) • These bits are initialized to "000" at reset. • Reading and writing are allowed. Note: In 8-bit prescaler/8-bit PPG mode and in 16-bit PPG mode, setting bits PCS2 to 0 is disabled since the PPG of channels 1,3, and 5 receives the counter clock signal from channels 0,2, and 4. 339 CHAPTER 17 8/16-BIT PPG TIMER [Bits 4, 3, 2] PCM2 to 0: ppg Count Mode (count clock selection) These bits are used to select the operation clock for the down counter of channels 0, 2, and 4. PCM2 PCM1 PCM0 Operation mode 0 0 0 Peripheral device clock (62.5 ns machine clock for 16 MHz) 0 0 1 Peripheral device clock/2 (125 ns machine clock for 16 MHz) 0 1 0 Peripheral device clock/4 (250 ns machine clock for 16 MHz) 0 1 1 Peripheral device clock/8 (500 ns machine clock for 16 MHz) 1 0 0 Peripheral device clock/16 (1 µs machine clock for 16 MHz) 1 1 1 Input clock from the timebase counter (29 x 250 ns = 128 µs oscillation for 4 MHz) • These bits are initialized to "000" at reset. • Reading and writing are allowed. [Bits 1, 0] reserved bits These bits are reserved. When setting PPG01, PPG23, or PPG45, set these bits to "00". 340 CHAPTER 17 8/16-BIT PPG TIMER 17.2.4 Reload Registers (PPLL0 to PPLL5, PPLH0 to PPLH5) This section describes the configuration and functions of the reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5). ■ Reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5) The bit configuration of the reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5) is shown below. 00002EH 7 6 5 4 3 2 1 0 PPLL0 to -5 000030H 000032H D07 D06 D05 D04 D03 D02 D01 D00 Reload register "L" 000034H 000036H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write 000038H (X) (X) (X) (X) (X) (X) (X) (X) Initial value 00002FH 15 14 13 12 11 10 9 8 PPLH0 to -5 000031H 000033H D15 D14 D13 D12 D11 D10 D09 D08 Reload register "H" 000035H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write 000037H (X) (X) (X) (X) (X) (X) (X) (X) Initial value 000039H The reload registers (PPLL0 to PPLL5, PPLH0 to PPLH5) are 8-bit registers which each store a reload value for the down counter (PCNT). The registers have the following functions. • Register name Function PRLL Stores the L-side reload value PRLH Stores the H-side reload value Both registers can be read and written. Note: If PRLL and PRLH for channels 0/2/4 are set to different values in 8-bit prescaler/8-bit PPG mode, the PPR waveform of channels 1/3/5 may differ from cycle to cycle. It is therefore recommended that PRLL and PRLH for channels 0/2/4 be set to the same value. 341 CHAPTER 17 8/16-BIT PPG TIMER 17.3 Operations of 8/16-Bit PPG Timer The 8/16-bit PPG timer contains an 8-bit PPG unit for six channels (PPG0/1,PPG2/ 3,PPG4/5). In addition to independent operation, the channels can also be used in direct connection mode (PPG0 is used in combination with PPG1, PPG2 is used in combination with PPG3, and PPG4 is used in combination with PPG5). In total, three types of operation are therefore supported: independent operation, 8-bit prescaler/8bit PPG mode, and 16-bit PPG mode. ■ Outline of 8/16-bit PPG timer operation Each 8-bit PPG unit has two 8-bit reload registers, one L-side and one H-side register (PRLL, PRLH). The values in these registers are reloaded into the corresponding L/H sides of the 8-bit down counter (PCNT), and decremented at every clock pulse. The value of the output pin is inverted at reloading when a counter borrow occurs. This operation ensures that the output pin outputs pulses with an L/H width that corresponds to the reload register values. Operation start or restart are initiated by setting the corresponding bit in the register. The relationship between the reload operation and pulse output is shown below. Reload operation Pin output change PRLH --> PCNT PPG0/1[0 --> 1] rising If bit 4 of PPGC0 (PIE0) is set to "1" and bit 2 of PPGC1 (PIE1) is set to "1", a 00 to FF counter borrow for each counter (in 16-bit PPG mode, a 0000 to FFFF counter borrow) will cause an interrupt request. ■ Operation mode The 8/16-bit PPG timer has three operation modes: two-channel independent mode, 8-bit prescaler/8-bit PPG mode, and 16-bit PPG mode (the MB90470 has three channels per mode). Two-channel independent mode allows the two channels to be used independently as 8-bit PPGs. The PPG0 pin is connected to the output of channel 0, and the PPG1 pin is connected to the output of channel 1 (PPG2 to PPG5 correspond to channels 2 to 5). 8-bit prescaler/8-bit PPG mode is a mode in which channel 0 (channel 2 or channel 4) operates as bit prescaler, while channel 1 (channel 3 or channel 5) is counted with a borrow output of channel 0 (channel 2 or channel 4), which allows an 8-bit PPG waveform of an arbitrary interval to be output. The PPG0 (PPG2 or PPG4) pin is connected with the prescaler output of channel 0 (channel 2 or channel 4), and the PPG1 pin (PPG3, or PPG5) is connected with the PPG output of channel 1 (channel 3 or channel 5). 16-bit PPG1 channel mode (the MB90470 has 3 channels) is an operation mode in which channel 0 and channel 1 are directly connected (direct connection between channels 2 and 3 respectively with channels 4 and 5) to allow 16-bit PPG operation. Both PPG 0 and PPG1 are connected with the 16-bit PPG output. 342 CHAPTER 17 8/16-BIT PPG TIMER ■ PPG output operation For the 8/16-bit PPG timer, PPG operation of channel 0 (channel 2 or channel 4) is started by setting bit 7 of the PPGC0 register (PEN0) to "1". Similarly, PPG operation of channel 1 (channel 3 or channel 5) is started by setting bit 15 of the PPGC1 register (PEN1) to "1" to start counting. By subsequently setting bit 7 of the PPGC0 (PEN0) or bit 15 of the PPGC1 (PEN1) to "0", the count operation is stopped, and the pulse output level is fixed at L. In 8-bit prescaler/8-bit PPG mode, do not set channel 0 (channel 2 or channel 4) to stop mode and channel 1 (channel 3 or channel 5) to active mode. In 16-bit PPG mode, use bit 7 of the PPGC0 register (PEN0) and bit 15 of the PPGC1 register (PEN1) to control simultaneous start or stop of operation. In the following, the operation for PPG output is described. During PPG operation, a pulse signal with an arbitrary interval and duty ratio (ratio of "H"-level pulse width to "L"-level pulse width) is repeatedly output. After it starts to output the pulse signal, the PPG will not stop until operation stop is specified. Figure 17.3-1 "Output waveform during PPG output operation" shows the output waveform during PPG output. Figure 17.3-1 Output waveform during PPG output operation PEN Operation start by PEN (from L side) Output pin PPG T × (L + 1) (Start) T × (H + 1) L : PRLL value H : PRLH value T : peripheral clock (by PPGC clock selection) 343 CHAPTER 17 8/16-BIT PPG TIMER ■ Relationship between reload value and pulse width The width of the output pulse can be calculated by adding1 to the reload register value, and multiplying the result by the count clock interval. In other words, if the reload register value during 8-bit PPG operation is 00H, or that in 16-bit PPG operation is 0000H, the pulse width will be equal to one interval length of the count clock. If the reload register value during 8-bit PPG operation is FFH, the pulse width is equal to 256 intervals of the count clock, while the pulse width is equal to 65,536 intervals of the count clock if the reload register value during 16-bit PPG operation is FFFFH. The pulse width is expressed with the formula below: PL = T x (L + 1) PH = T x (H + 1) Where PL: Width of L pulse PH: Width of H pulse T: Input clock interval L: PRLL value H: PRLH value ■ Selection of count clock The 8/16-bit PPG timer uses the input from the peripheral device clock and timebase counter as a counter clock, allowing a selection from six types of count clock input. Bits 4 to 2 of the PPG01/23/45 registers (PCM2 to 0) are used to select the clock of channel 0 (channel 2 or channel 4), and bits 7 to 5 of the PPG01/23/45 registers (PCS2 to 0) are used to select the clock of channel 1 (channel 3, or channel5). The clock is selected from among the machine clock multiplied by 1/16 to 1, and the timebase counter input. Note: • In 8-bit prescaler/8-bit PPG mode and in 16-bit PPG mode, the value in bit 14 of the PPGC1 register (PCS1) is invalid. • If the input from timebase timer is used, the first count cycle after a trigger or stop event may be out of sync. If the timebase timer is initialized while the 8/16-bit PPG timer is running, cycles may be out of sync. • If, in 8-bit prescaler/8-bit PPG mode, channel 0/2/4 is in active mode and channel 1/3/5 is in stopped mode, the first count cycle may be out of sync when operation of channel 1 (channel 3 or channel 5) starts. ■ Pin output control of pulses Pulses generated by the 8/16-bit PPG timer are output from the external pins (PPG0 to 5). To output pulses from an external pin, set the bit corresponding to the pin to "1". For enabling PPG0/2/4 pin output, bit 5 of PPGC0 (PE0) is used, and for enabling PPG1/3/5 pin output, bit 3 of PPGC1 (PE1) is used. If the respective bit is set to "0" (initial value), the external pin does not output pulses, but is used as a general-purpose port. In 16-bit PPG mode, PPG0 to PPG5 output the same waveform. For this reason, it is sufficient to enable pin output for either of the corresponding pins to obtain the same output. In 8-bit prescaler/8-bit PPG mode, PPG0/2/4 output a toggle waveform of the 8- bit prescaler, and PPG1/3/5 output a waveform of 8-bit PPG. 344 CHAPTER 17 8/16-BIT PPG TIMER Output waveform in this mode is illustrated in Figure 17.3-2 "Waveform in 8-bit prescaler/8-bit PPG mode output operation". Figure 17.3-2 Waveform in 8-bit prescaler/8-bit PPG mode output operation PH0 PL0 PPG0 PPG1 PH1 PL1 The pulse width shown in Figure 17.3-2 "Waveform in 8-bit prescaler/8-bit PPG mode output operation" can be expressed with the following formulas. PL0 = T x (L0 + 1) PH0 = T x (L0 + 1) PL1 = T x (L0 + 1) x (L1 + 1) PH1 = T x (L0 + 1) x (H1 + 1) Where L0: PRLL value of channel 0 and PRLH value of channel 1 L1: PRLL value of channel 1 H1: PRLH value of channel 1 T: input clock cycle PH0: H pulse width of PPG0 PL0: L pulse width of PPG0 PH1: H pulse width of PPG1 PL1: L pulse width of PPG1 Note: Set PRLL of channel 0 and PRLH of channel 1 to the same value. ■ Interrupts of the 8/16-Bit PPG timer The interrupt unit of the 8/16-bit PPG timer becomes active as soon as a counter borrow occurs after count-down from the reload value has already reached zero. In 8-bit PPG2 channel mode or 8-bit prescaler/9-bit PPG mode (3 are channels provided for MB90470), each borrow will cause a separate interrupt request. In 16-bit PPG mode, however, PUG0 and PUG1 will be set at the same time when a borrow from the 16-bit counter occurs. To unify interrupt sources, only one of either PIE0 or PIE1 is allowed. Interrupt sources are also cleared at the same time for PUF0 and PUF1. 345 CHAPTER 17 8/16-BIT PPG TIMER ■ Initial value of hardware components The hardware components of the 8/16-bit PPG timer are initialized to the following values at reset. < Registers > < pulse output > < interrupt request unit > PPG0 PPG1 PPG01 PPG0 PPG1 PE0 PE1 IRQ0 IRQ1 → → → → → → → → → 0X000001 00000001 XXXXXX00 "L" "L" Output prohibited Output prohibited "L" "L" Hardware components other than above mentioned are not initialized. ■ Write timing to the reload register It is recommended that word transfer instructions be used for writing data to the reload registers PRLL and PRLH in modes other than 16-bit PPG mode. Writing data to the register two times by separate byte transfer instructions may result in an unexpected output pulse width, depending on the timing. Figure 17.3-3 "Timing chart of writing to the reload register" shows the timing for writing to the reload register. Figure 17.3-3 Timing chart of writing to the reload register PPG0 A B A B C B C D C D (1) In Figure 17.3-3 "Timing chart of writing to the reload register", PRLL is changed from A to C before (1), and the PRLH value is changed from B to D after (1). However, since the PRL values at (1) are PRLL = C and PRLH = B, the pulses for the L-side count of C and the H-side count of B are generated only once. Similarly, to write data to the PRL of channels 0/2/4 and channels 1/ 3/5, use a long word transfer instruction or use a word transfer instruction in the order channel 0 --> channel 1 (respectively channel 2 --> channel 3, channel 4 --> channel 5). In this mode, data is temporarily written from channels 0/2/4 to the PRL; when data is then written from channels 1/ 3/5 to the PRL, it is actually written to the PRL of channel 0/2/4. In modes other than 16-bit PPG mode, writing to channel 0/2/4 and channel 1/3/5 are performed independently. Figure 17.3-4 "Flowchart of the PRL write operation" shows a flowchart of the PRL write operation. Figure 17.3-4 Flowchart of the PRL write operation Write data for PRL of ch0 Writing from ch0 in a mode other than 16-bit PPG mode Temporary latch Write data for PRL of ch1 Writing from ch1 in a mode other than 16-bit PPG mode Write data for ch1 PRL of ch0 346 PRL of ch1 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT This chapter provides an overview of the DTP/external interrupt unit, its operation, and explains the configuration and functions of its registers. 18.1 "Overview of DTP/External Interrupt Unit" 18.2 "DTP/External Interrupt Unit Registers" 18.3 "Operation of DTP/External Interrupt Unit" 18.4 "Notes on DTP/External Interrupt Unit Usage" 347 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.1 Overview of DTP/External Interrupt Unit The DTP (Data Transfer Peripheral) unit is a peripheral control section located between the peripheral units outside the device and the F2MC-16LX CPU. It is used to receive DMA request or interrupt requests from the external peripheral device, and report such requests to the F2MC-16LX CPU to start µDMA or interrupt handling. ■ Overview of DTP/external interrupt unit For µDMA, the request level can be selected from two types, "H" and "L". External interrupt requests can be selected from four types: rising and falling edges and "H" and "L" signals. ■ Block diagram of DTP/external interrupt unit Figure 18.1-1 "Block diagram of DTP/external interrupt unit" shows a block diagram of the DTP/ external interrupt. Figure 18.1-1 Block diagram of DTP/external interrupt unit F2MC-16 bus 4 4 4 8 348 Interrupt/DTP enable register Gate Source F/F Interrupt/DTP source register Request level setting register Edge detection circuit 4 Request input CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.2 DTP/External Interrupt Unit Registers This section describes the configuration and functions of the registers used in the DTP/external interrupt unit. ■ List of registers of DTP/external interrupt unit Figure 18.2-1 "List of DTP/external interrupt unit registers" shows a list of the registers of the DTP/external interrupt unit. Figure 18.2-1 List of DTP/external interrupt unit registers 7 Bit Address: 00000CH EN7 15 Bit Address: 00000DH ER7 7 Bit Address: 00000EH LB3 15 Bit Address: 00000FH LB7 6 EN6 14 ER6 6 LA3 14 LA7 5 4 EN5 EN4 13 12 ER5 ER4 5 4 LB2 LA2 13 12 LB6 LA6 3 EN3 11 ER3 3 LB1 11 LB5 2 EN2 10 ER2 2 LA1 10 LA5 1 EN1 9 ER1 1 LB0 9 LB4 0 EN0 8 ER0 0 LA0 8 LA4 Interrupt/DTP enable register (ENIR) Interrupt/DTP source register (EIRR) Request level setting register (ELVR) Request level setting register (ELVR) ■ Interrupt/DTP enable register (ENIR: Enable interrupt request register) The bit configuration of the interrupt/DTP enable register (ENIR) is shown below. ENIR address: 00000CH 7 EN7 R/W 6 EN6 R/W 5 4 EN5 EN4 R/W R/W 3 EN3 R/W 2 EN2 R/W 1 EN1 R/W 0 EN0 R/W Initial value 00000000B The Interrupt/DTP enable register (ENIR) uses a device pin as external interrupt/DTP request input, and determines whether to start a function for generating a request for the interrupt controller. The pins corresponding to register bits set to "1" are used as external interrupt/DTP request input for generating a request for the interrupt controller. The pins corresponding to bits set to "0" retain external interrupt/DTP request input sources, but are not used for generating requests for the interrupt controller. 349 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT ■ Interrupt/DTP source register (EIRR: External interrupt request register) The bit configuration of the interrupt/DTP source register (EIRR) is shown below. 15 EIRR Address: 00000DH ER7 R/W 14 ER6 R/W 13 12 ER5 ER4 R/W R/W 11 ER3 R/W 10 ER2 R/W 9 ER1 R/W 8 Initial value ER0 00000000B R/W --- (However, the applicable value is different for read and write operations) The interrupt/DTP source register (EIRR) is used in read operations to indicate whether a corresponding external interrupt/DTP request exists. In write operations, the register is used to clear the flip-flop for the request. If a register bit returns "1" in a read operation, the pin corresponding to this bit carries an external interrupt/DTP request. By setting "0", the request flip-flop corresponding to the bit is cleared. Writing "1" has no effect. Read-modify-write instructions always return "1". Note: Reading by read-modify-write type instructions always returns "1". If multiple external interrupt request outputs are enabled (ENIR: EN7 to EN0=1), only the bits for which the CPU accepts an interrupt (bits for which "1" was set in ER3 to ER0) are cleared. No other bits must be cleared unconditionally. ■ Request level setting register (ELVR: External level register) The bit configuration of the request level setting register (ELVR) is shown below. Address: 00000EH Address: 00000FH 7 LB3 R/W 15 LB7 R/W 6 LA3 R/W 14 LA7 R/W 5 4 LB2 LA2 R/W R/W 13 12 LB6 LA6 R/W R/W 3 LB1 R/W 11 LB5 R/W 2 LA1 R/W 10 LA5 R/W 1 LB0 R/W 9 LB4 R/W 0 LA0 R/W 8 LA4 R/W Initial value 00000000B Initial value 00000000B The request level setting register (ELVR) is used to select a request detection level. Two bits are assigned for each pin, as shown in Table Table 18.2-1 "ELVR assignment (LA0 to LA7, LB0 to LB7)". If the setting for a request input indicates a level, the corresponding level will be set again when it is cleared, provided the input is active. Table 18.2-1 ELVR assignment (LA0 to LA7, LB0 to LB7) 350 LBx LAx Operation 0 0 Request by "L" level 0 1 Request by "H" level 1 0 Request by rising edge 1 1 Request by falling edge CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.3 Operations of DTP/External Interrupt Unit This section describes the operations of the DTP/external interrupt unit. ■ Operation of external interrupt unit If, after an external interrupt request has been set, the interrupt source specified in the ELVR register is input to the corresponding pin, the external interrupt unit will generate an interrupt request signal for the interrupt controller. Interrupts that are generated by the interrupt controller at the same time will be distinguished by priority. The interrupt controller will generate an interrupt request to the F2MC-16LX CPU if the interrupt from the corresponding resource has the highest priority. The F2MC-16LX CPU compares the interrupt level mask register (ILM) in the processor status (PS) with the interrupt request level. If the request level is found to be higher than the value expressed by the ILM bits, the hardware interrupt handling microprogram starts immediately after the currently executed instruction is completed. Figure 18.3-1 "External interrupt operation" shows the operational flow for external interrupts. Figure 18.3-1 External interrupt operation External interrupt/DTP unit F2MC-16LXCPU Interrupt controller Other request ELVR ICRyy Interrupt source CMP CMP EIRR ENIR IL ICFxx ILM INTA The interrupt handling microprogram reads data from the interrupt vector area and generates an interrupt acknowledge signal for the interrupt controller. After that, it transfers the jump destination address of the macro instruction, which is obtained from the interrupt vector, to the program counter, and execution continues with the user's interrupt handling program. 351 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT ■ DTP operation To start µDMA in a user program, the following initialization operations are performed: The I/O address pointer in the µDMA descriptor is set to the register address allocated in 000000H0000FFH, and the buffer address pointer is set to the start address of the memory buffer. The operational sequence for DTP is almost the same as that for external interrupts. In particular, the operational sequence until the CPU starts the microprogram for handling hardware interrupts is exactly the same. At the start of µDMA, the corresponding read or write signal is transferred to the external peripheral device whose address was specified, and data transfer is performed. Ensure that the external peripheral device withdraws the interrupt request within three machine cycles after data transfer. At the end of data transfer, the descriptor is updated, and a signal to clear the interrupt source is generated by the interrupt controller. After receiving the signal, the DTP unit clears the flip-flop that retains the interrupt source and waits for the next request. Figure 18.3-2 "Timing for withdrawing an external interrupt request at the end of DTP operation" shows the timing for withdrawing the external interrupt signal at the end of DTP operation. Figure 18.3-3 "Example of interface with an external peripheral device" shows an example for an interface with the external peripheral device. Figure 18.3-2 Timing for withdrawing an external interrupt request at the end of DTP operation ↑ Rising edge request or "H"-level request Interrupt source Internal operation * µDMA for transferring from I/O register to memory Descriptor selection/read Address bus pin Read address Write address Read data Data bus pin Read signal Write data (1) Write signal (2) Withdrawn within 3 machine cycles Data bus or address bus Internal bus Register External peripheral unit Figure 18.3-3 Example of interface with an external peripheral device IRQ DTP Withdrawn within 3 machine cycles after the end of transfer MB90470 352 (2) (1) INT CORE MEMORY CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT 18.4 Notes on DTP/External Interrupt Unit Usage This section provides notes on using the DTP/external interrupt unit. ■ Conditions for external connection of peripheral devices For support by the DTP unit, external peripheral devices must be able to automatically clear a request after successful data transfer. If a transfer request fails to be withdrawn within three machine cycles after the transfer operation starts (interim value), the DTP unit will proceed as if a new transfer request had been generated. ■ Procedure for DTP/external interrupt unit operation Set the values of registers in the DTP/external interrupt unit as follows: (1) Set the bits for the registers to be enabled to "disable". (2) Set the bits of the request level setting register. (3) Clear the bits in the source register. (4) Set the bits for the registers to be enabled to "enable". Steps (3) and (4) allow simultaneous writing by word-length specification. To set the contents of DTP/external interrupt unit registers, first disable the registers to be enabled. Before enabling the registers to be enabled again, clear the source register in order to avoid accidental generation of an interrupt source in register set mode or interrupt enabled mode. 353 CHAPTER 18 DTP/EXTERNAL INTERRUPT UNIT ■ External interrupt request level • If edge input has been selected for the request input level, at least a pulse width of three machine cycles is required for detecting requests. • If level input has been selected for the request input level, note that an external request that has been input remains active with respect to the interrupt controller even if it is no longer being input, since the interrupt controller contains an internal source retention circuit. To withdraw a request with respect to the interrupt controller, the source retention circuit must be cleared. Figure 18.4-1 Clearing the source retention circuit when setting the request level Interrupt source Level detection Source F/F (source retention circuit) Enable gate To interrupt controller Source is retained until cleared Figure 18.4-2 Interrupt sources and requests to the interrupt controller when interrupts are enabled Interrupt source H level Interrupt request to interrupt controller Turned to inactive by clearing source F/F Note: Edge detection cannot be used to return from watch mode. 354 CHAPTER 19 8/10-BIT A/D CONVERTER This chapter provides an overview of the 8/10-bit A/D converter and its operation, and explains the configuration and functions of its registers. 19.1 "Overview of 8/10-bit A/D Converter" 19.2 "8/10-bit A/D Converter Registers" 19.3 "Operations of 8/10-bit A/D Converter" 19.4 "Conversion Data Protection Function" 19.5 "Precautions When Using the 8/10-bit A/D Converter" 355 CHAPTER 19 8/10-BIT A/D CONVERTER 19.1 Overview of 8/10-bit A/D Converter The A/D converter converts analog input voltages into digital values. This section describes the features and provides a block diagram of the 8/10-bit A/D converter. ■ Features of the 8/10-bit A/D converter The 8/10-bit A/D converter features the following functions: • Conversion speed: as fast as 6.13 µs per channel (98 machine cycles/machine clock at 16 MHz, sampling time included) • Sampling time: as fast as 3.75 µs per channel (60 machine cycles/machine clock at 16 MHz) • RC-type sequential comparison conversion system with sample and hold circuit • 8- or 10-bit resolution can be selected • Analog input by program via eight channels • Single conversion mode: Selection and conversion of a single channel • Scan conversion mode: Several channels can be converted in succession. A maximum of eight channels can be programmed. • Continuous conversion mode: Conversion of the specified channels is performed repeatedly. • Stop conversion mode: Pauses after conversion of one channel is completed and stands by until next activation is triggered. (Conversion starts can be synchronized) When A/D conversion ends, an interrupt request for end of A/D conversion can be generated to the CPU. This interrupt starts µDMA, enabling the transfer of data resulting from A/D conversion to memory. The converter is therefore suitable for continuous processing. As the start source, software, external triggers (falling edge) and the timer (rising edge) can be selected. 356 CHAPTER 19 8/10-BIT A/D CONVERTER ■ Block diagram of 8/10-bit A/D converter Figure 19.1-1 "Block diagram of 8/10-bit A/D converter" shows a block diagram of the 8/10-bit A/ D converter. Figure 19.1-1 Block diagram of 8/10-bit A/D converter AVCC AVRH AVSS D/A converter Sequential comparison register Comparator Data bus AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Input circuit MPX Decoder Sample and hold circuit Data registers ADCR1,2 A/D control register 1 A/D control register 2 ADTG ADCS1,2 Trigger start Timer start Timer (PPG1 output) φ Operation clock Prescaler 357 CHAPTER 19 8/10-BIT A/D CONVERTER 19.2 8/10-bit A/D Converter Registers This section describes the configuration and function of the registers used in the 8/10bit A/D converter. ■ Registers of 8/10-bit A/D converter Figure 19.2-1 "Registers of 8/10-bit A/D converter" illustrates the registers of 8/10-bit A/D Converter. Figure 19.2-1 Registers of 8/10-bit A/D converter 8 7 15 0 ADCS2 ADCS1 ADCR2 ADCR1 8 bits 8 bits 7 6 5 4 3 2 1 0 bit Address: 000046H MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 Control status 14 13 12 11 10 9 8 bit 15 registers Address: 000047H BUSY INT INTE PAUS STS1 STS0 STRT (ADCS1,ADCS2) 7 6 5 4 3 2 1 0 bit Address: 000048H D7 D6 D5 D4 D3 D2 D1 D0 Data registers 14 13 12 11 10 9 8 (ADCR1,ADCR2) bit 15 Address: 000049H S10 ST1 ST0 CT1 CT0 D9 D8 358 CHAPTER 19 8/10-BIT A/D CONVERTER 19.2.1 Control Status Register 1 (ADCS1) The Control Status Register 1 (ADCS1) controls the A/D converter and displays the status of operation. ■ Control status register 1 (ADCS1) The bit configuration of the Control Status Register 1 (ADCS1) is illustrated below. bit 7 6 5 4 3 2 1 0 ADCS1 MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 Address: 000046H 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Initial value Bit attribute Note: Do not rewrite Control Status Register 1 (ADCS1) during A/D conversion. The function of each bit of the Control Status Register (ADCS1) is described below. [Bits 7, 6] MD1, MD0: A/D converter MoDe set (operation mode) These bits specify the operation mode. Operation modes that can be selected are shown below. MD1, MD0 Operation mode 00 Single mode, all ongoing operations can be restarted 01 Single mode, ongoing operations cannot be restarted 10 Continuous mode, ongoing operations cannot be restarted 11 Stop mode, ongoing operations cannot be restarted The functions of each mode are as follows: • Single mode: A/D conversion is continuously performed from the specified channels in the range of ANS2 to ANS0, to the specified channels in the range of ANE2 to ANE0. Operation stops when one cycle of conversion operations ends. • Continuous mode: A/D conversion is repeated from the specified channels in the range of ANS2 to ANS0, to the specified channels in the range of ANE2 to ANE0. • Stop mode: A/D conversion is performed from the specified channels in the range of ANS2 to ANS0, to the specified channels in the range of ANE2 to ANE0. After that, operation stops. Resuming conversion is triggered by a start source. These bits are initialized to "00" at reset. Each operation mode operates as follows: • After start of A/D conversion in continuous or stop mode, conversion will continue until operation is stopped via the BUSY bit. • Operation in each operation mode is stopped by setting the BUSY bit to "0". • "Restart disable" in the single, continuous, and stop modes affects all start operations by timer, external trigger, and software. 359 CHAPTER 19 8/10-BIT A/D CONVERTER [Bits 5, 4, 3] ANS2, ANS1, ANS0: ANalog Start channel set Set a start channel for A/D conversion using these bits. At the startup of the A/D converter, A/D conversion starts with the channel selected by these bits. • • ANS2 ANS1 ANS0 Start channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 During read out • These bits are used for reading conversion channels during A/D conversion. • When conversion stops in stop mode, the previous conversion channels will be read out. These bits are initialized to "000B" at reset The read values of these bits are updated during A/D conversion, and before A/D conversion starts, the previous conversion channel will be read even if these bits have already been set to the new value. [Bits 2, 1, 0] ANE2, ANE1, ANE0: ANalog End channel set These bits specify the end channel for A/D conversion. 360 ANE2 ANE1 ANE0 End channel 0 0 0 AN0 0 0 1 AN1 0 1 0 AN2 0 1 1 AN3 1 0 0 AN4 1 0 1 AN5 1 1 0 AN6 1 1 1 AN7 • Specifying the same channels as for ANS2 to ANS0 will result in one-channel conversion. (Single conversion) • If continuous mode or stop mode is set, the channels specified by ANS2 to ANS0 will be set again when conversion of the channels specified by these bits ends. CHAPTER 19 8/10-BIT A/D CONVERTER • If ANS < ANE, conversion will start with channel ANS; after conversion has been performed up to channel 7, the setting channel will be set to Channel 0, and conversion will be performed up to ANE. • These bits are initialized to "000B" at reset. Example: Channel setting: Single Mode with ANS = Channel 6 and ANE = Channel 3 Operation: Conversion channel Ch6 --> Ch7 --> Ch0 --> Ch1 --> Ch2 --> Ch3 361 CHAPTER 19 8/10-BIT A/D CONVERTER 19.2.2 Control Status Register 2 (ADCS2) The Control Status Register 2 (ADCS2) is used for A/D converter control and status display. ■ Control status register 2 (ADCS2) The bit configuration of the control status register 2 (ADCS2) is illustrated below. bit 15 14 13 12 11 10 9 8 ADCS2 BUSY INT INTE PAUS STS1 STS0 STRT Reserved Address: 000047H 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W W R/W Initial value Read/write The function of each bit of the control status register (ADCS2) is described below. [Bit 15] BUSY: busy flag and stop • During reading: This bit indicates A/D converter operation. It is set when A/D conversion starts and cleared when A/D conversion ends. • During writing: Setting this bit by writing "0" during A/D operation will forcibly stop operation. Use this bit to force stopping in continuous mode or stop mode. When the bit is used for operation display, it cannot be set by writing "1". RMW-instructions will always return "1". In single mode, this bit is cleared when A/D conversion ends. In continuous and stop mode, the bit is not cleared until operation is stopped by writing "0". This bit is initialized to "0" at reset. Note: Do not execute forced stop and software start simultaneously. (BUSY = 0, STRT = 1) [Bit 14] INT: Interrupt This bit is a data indication bit. This bit will be set when conversion data is written to the ADCR. Setting this bit when bit 5 (INTE) is "1" generates an interrupt request. If µDMA is enabled, µDMA will be started. Writing "1" has no effect. Write "0" and use a µDMA interrupt clear signal to clear. Initialized to "0" at reset. Also read the caution remark in Section 19.4 "Conversion Data Protection Function". Note: Clear this bit by writing "0"only while A/D conversion is not being performed. 362 CHAPTER 19 8/10-BIT A/D CONVERTER [Bit 13] INTE: interrupt enable This bit is used to enable or disable interrupts at conversion end. • 0: Interrupts prohibited • 1: Interrupts allowed Set this bit when using µDMA. An interrupt request will then trigger µDMA start. This bit is initialized to "0" at reset. Also read the caution remark in Section 19.4 "Conversion Data Protection Function". [Bit 12] PAUS: A/D converter pause This bit is set when A/D conversion pauses. There is only one register for storing the results of A/D conversion. When conversion is performed continuously, conversion results have to be transferred by µDMA, or data stored previously will be overwritten. To prevent overwriting data, the next conversion result cannot be stored before the contents of the data register has been transferred by µDMA, and A/D conversion will be stopped in between. The A/D converter resumes conversion as soon as data transfer by µDMA ends. This register is effective only when µDMA is used. Also read the caution remark in Section 19.4 "Conversion Data Protection Function". This bit is initialized to "0" at reset. [Bits 11 and 10] STS1, STS0: start source select These bits are initialized to "00" at reset. These bits select A/D start sources. STS1 STS0 Function 0 0 Software start 0 1 Start by an external pin trigger and by software 1 0 Start by timer and software 1 1 Start by an external pin trigger, timer, and software In a mode for which two start sources apply, the first of the sources to occur will trigger start. Start sources become effective from the time they are written. Exercise caution when rewriting during A/D operation. • When an external pin trigger is selected, a falling edge is detected. • When the external trigger input level is "L", A/D conversion will start as soon as when this bit is rewritten. • The output of PPG1 is selected at the time the timer is selected. Note: When starting the A/D converter by an external trigger or an internal timer, set A/D startup source bit STS1 or 0 of the ADCS2 register. Set the input value of the internal timer and the external trigger only on the side that is in inactive state. If set on the active side, the A/D converter might start to operate immediately. For setting STS1 and STS0, set in the state of ADTG-1 input and internal timer (PPG1) = 0 output. 363 CHAPTER 19 8/10-BIT A/D CONVERTER [Bit 9] STRT: start • Set this bit by writing "1" to start A/D conversion. • For restarting, write this bit again. • When stop mode is set, operation cannot be restarted by an operational function. • This bit is initialized to "0" at reset. • The bite/words instructions read "1". • The read-modify-write type instructions read "0". Note: Do not execute forced stop and software start simultaneously. (BUSY = 0, STRT = 1) [Bit 8] Reserved In write operations, write "0". 364 CHAPTER 19 8/10-BIT A/D CONVERTER 19.2.3 Data Registers (ADCR2 and ADCR1) The bit configurations and functions of the data registers (ADCR2 and ADCR1) are explained below. ■ Data registers (ADCR2 and ADCR1) The function of each bit of the data registers (ADCR2 and ADCR1) is described below. bit ADCR1 Address: 000048H 7 D7 X R bit 15 ADCR2 S10 Address: 000049H 0 W 6 D6 X R 14 ST1 0 W 5 D5 X R 13 ST0 0 W 4 D4 X R 12 CT1 0 W 3 D3 X R 11 CT0 0 W 2 D2 X R 10 X R 1 D1 X R 9 D9 X R 0 D0 X R 8 D8 X R Initial value Read/write Initial value Read/write The data registers (ADCR2 and ADCR1) are registers for storing conversion results as digital values. The upper two bits of conversion values are stored in ADCR2, while the lower eight bits are stored in ADCR1. The values of these registers are updated at the end of each conversion. Normally, the last conversion value is stored. The S10-bits must be rewritten if A/D operation stops before conversion ends. Rewriting after conversion may result in an undefined ADCR data. To read ADCR with 10-bit mode specified, always use a word move instruction. The ADCR registers have a conversion data protection function. Refer to Section 19.4 "Conversion Data Protection Function". Do not write data to these registers during A/D operation. When S10 is set to "0", conversion results will be output in units of ten bits; when S10 is set to "1", conversion results will be output in units of eight bits. ST1 ST0 0 0 0 Sampling time setting bit Compare time setting bit CT1 CT0 20 machine cycles (1.0 µS@20MHz) 0 0 44 machine cycles (2.2 µS@20MHz) 1 32 machine cycles (1.6 µS@20MHz) 0 1 66 machine cycles (3.3 µS@20MHz) 1 0 48 machine cycles (2.4 µS@20MHz) 1 0 88 machine cycles (4.4 µS@20MHz) 1 1 128 machine cycles (6.4 µS@20MHz) 1 1 176 machine cycles (8.8 µS@20MHz) Note 1: Setting ST1 and ST0 = 00 or CT1 and CT0 = 00 when operating at 20MHz will sometimes prevent the proper analog voltages from being obtained. 365 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3 Operations of 8/10-bit A/D Converter The 8/10-bit A/D converter operates based on a sequential comparison method and has a 10-bit resolution. The 8/10-bit A/D converter has only one combined 10-bit register for storing results of conversion. Data in the individual data conversion registers (ADCR2 and ADCR1) is updated whenever one conversion operation ends. The converter therefore does not support continuous conversion processing. It is recommended that conversion be performed while transferring conversion data to memory using the µDMA function of F2MC-16LX. This section describes the operations of the 8/10-bit A/D converter. ■ Operation modes The operation modes used by the converter are described below. ❍ Single Mode In this mode, analog input set by the bits ANS and ANE is sequentially converted. The converter stops conversion operation when conversion up to the end channel set by the bit ANE is finished. If the start and end channels are the same, one-channel conversion will be performed. (ANS = ANE) Example: ANS = 000, ANE = 011 Start --> AN0 --> AN1 --> AN2 --> AN3 --> End ANS = 010, ANE = 010 Start --> AN2 --> End ❍ Continuous Mode In this mode, analog input set by the bits ANS and ANE is sequentially converted. The converter continues conversion operation by returning to ANS analog input when conversion up to the end channel set by the bit ANE is finished. One-channel conversion operation will continue if the start and end channels are the same. (ANS = AME) Example: ANS = 000, ANE = 011 Start --> AN0 --> AN1 --> AN2 --> AN3 --> AN0 ...... --> Repeat ANS = 010, ANE = 010 Start --> AN2 --> AN2 --> AN2 ...... --> Repeat When conversion is performed in continuous mode, conversion will be repeated until the BUSY bit is set by writing "0". Set the BUSY bit to "0" to forcibly stop operation. When operation is stopped forcibly, data before the completion of conversion will be stored in the conversion registers. 366 CHAPTER 19 8/10-BIT A/D CONVERTER Note: In a forced stop, conversion operation will stop before completion. ❍ Stop Mode In this mode, analog input specified by the bits ANS and ANE is sequentially converted. However, conversion operation stops temporarily after conversion of each channel. Start again to release the stop. Analog input of ANS will be resumed and A/D conversion will continue when conversion up to the end channel specified by the bit ANE ends. One-channel conversion will be performed if the start and end channels are the same. (ANS = ANE) Example: ANS = 000, ANE = 011 Start --> AN0 --> Stop --> Activate --> AN1 --> Stop --> Activate --> --> AN2 --> Stop --> Activate --> AN3 --> Stop --> Activate --> ...... Repeat ANS = 010, ANE = 010 Start --> AN2 --> Stop --> Activate --> AN2 --> Stop --> Activate --> ...... Repeat Only startup sources specified by STS1 and 0 can be used in this mode. Operation in this mode enables synchronizing the start of multiple conversions. ■ Conversion operation using µDMA Figure 19.3-1 "Example of operation flow (in continuous mode) from start of A/D conversion to transfer of conversion data" shows an example of the operational flow (in continuous mode) from start of A/D conversion to transfer of conversion data. The result of the decision operation marked by " settings of µDMA. " in the diagram is decided based on the Figure 19.3-1 Example of operation flow (in continuous mode) from start of A/D conversion to transfer of conversion data A/D Conversion Start Sample and hold µDMA start Conversion Data transfer Interrupt processing Conversion end Interrupt clear Interrupt triggered 367 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3.1 Example of µDMA Start in Single Mode An example of µ DMA start in The Single Mode is described below. ■ Example of µDMA start in single mode The following example is based on the conditions described below: • Conversion finishes after conversion up to analog input (AN1 to AN3). • Conversion data is transferred to addresses 200H to 206H. • Start by software • The highest interrupt level is used Setting item Sample code MOV ICR14,#00H Operation Sets highest interrupt level and enables interrupts MOV BAPL,#00H MOV BAPM,#02H Address to transfer conversion data to MOV BAPH,#00H µDMA setting MOV DMACS,#18H Transfers word data and increments the destination address after transfer. Data transfer from µDMA to memory MOV IOA,#48H Stores A/D conversion results in registers MOV DCT,#03H Performs three transfers, matching the number of conversions. MOVW DERL,#8000H Setting for the µDMA enable register (EN15) MOV ADCS1,#0BH Single mode, start channel AN1, end channel AN3 MOV ADCS2,#A2H Software start, A/D conversion start A/D converter setting WBTC io ADCS2:7 µDMA end sequence - MOV ADCS2,#000h Resource interrupt clear MOVW DSRL,#0000h µDMA status register clear RETI Reset from interrupt ICR14: Interrupt control register BAPL: Buffer address pointer lower BAPM: Buffer address pointer middle BAPH: Buffer address pointer higher ISCS: Status register I0A: Address register DCT: Data counter Figure 19.3-2 "Sample operation flow for µDMA operation in single mode" shows an example of the operational flow for start of conversion. 368 CHAPTER 19 8/10-BIT A/D CONVERTER Figure 19.3-2 Sample operation flow for µDMA operation in single mode Start AN1 Interrupt → µDMA transfer AN2 Interrupt → µDMA transfer AN3 Interrupt → µDMA transfer End Interrupt sequence Performed in parallel 369 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3.2 Example of µDMA Start in Continuous Mode An example of µ DMA start in the continuous mode is described below. ■ Example of µDMA start in continuous mode The following example of start operation is based on the conditions described below: • Analog input (AN3 to AN5) is converted, and two items of data for conversion are obtained from each channel. • Conversion data is transferred to addresses 600H to 60CH. • Start by an external edge • Highest interrupt level Setting item Sample code MOV ICR14,#00H Operation Sets highest interrupt level and enables interrupts MOV BAPL,#00H MOV BAPM,#06H Address to transfer conversion data to MOV BAPH,#00H µDMA setting MOV DMACS,#18H Transfers word data and increments the destination address after transfer. Data transfer from µDMA to memory MOV IOA,#48H Stores A/D conversion results in registers MOV DCT,#06H Performs six transfers, matching the number of conversions. MOVW DERL,#8000H Setting for the µDMA enable register (EN15) MOV ADCS1,#9DH Single Mode, start channel AN3, end channel AN5 MOV ADCS2,#A4H Start by external edge, start of A/D conversion WBTC io ADCS2:7 - MOV ADCS2,#000h Resource interrupt clear MOVW DSRL,#0000h µDMA status register clear RETI Reset from interrupt A/D converter setting µDMA end sequence ICR14: Interrupt control register BAPL: Buffer address pointer lower BAPM: Buffer address pointer middle BAPH: Buffer address pointer higher ISCS: Status register I0A: Address register DCT: Data counter 370 CHAPTER 19 8/10-BIT A/D CONVERTER Figure 19.3-3 "Sample operation flow for µDMA operation in continuous mode" shows a sample operation flow for start processing. Figure 19.3-3 Sample operation flow for µDMA operation in continuous mode Start AN3 Interrupt → µDMA transfer AN4 Interrupt → µDMA transfer AN5 Interrupt → µDMA transfer After completing all 6 transfer sessions Interrupt sequence End 371 CHAPTER 19 8/10-BIT A/D CONVERTER 19.3.3 Example of µDMA Start in Stop Mode An example of µ DMA start in stop mode is described below. ■ Example of µDMA start in stop mode The following example is based on the conditions described below: • Analog input (AN3) is converted 12 times in preset intervals. • Conversion data is transferred to addresses 600H to 618H. • Conversion is started by an external edge • Interrupts have the highest interrupt level Setting item Sample code MOV ICR14,#00H Operation Sets highest interrupt level and enables interrupts MOV BAPL,#00H MOV BAPM,#06H Address to transfer conversion data to MOV BAPH,#00H µDMA setting MOV DMACS,#18H Transfers word data and increments the destination address after transfer. Data transfer from µDMA to memory MOV IOA,#48H Stores A/D conversion results in registers MOV DCT,#0CH Performs three transfers, matching the number of conversions. MOVW DERL,#8000H Setting for the µDMA enable register (EN15) MOV ADCS1,#DBH Continuous mode, start channel AN3, end channel AN3 (one-channel conversion) MOV ADCS2,#A4H Start by external edge, start of A/D conversion A/D converter setting WBTC io ADCS2:7 µDMA end sequence MOV ADCS2,#000h Resource interrupt clear MOVW DSRL,#0000h µDMA status register clear RETI Reset from interrupt ICR14: Interrupt control register BAPL: Buffer address pointer lower BAPM: Buffer address pointer middle BAPH: Buffer address pointer higher ISCS: Status register I0A: Address register DCT: Data counter 372 - CHAPTER 19 8/10-BIT A/D CONVERTER Figure 19.3-4 "Sample operation flow of µDMA start operation in stop mode" shows a sample operation flow for the start operation. Figure 19.3-4 Sample operation flow of µDMA start operation in stop mode Start AN3 Stop Start by external edge Interrupt → µDMA transfer After completing all 12 transfer sessions Interrupt sequence End 373 CHAPTER 19 8/10-BIT A/D CONVERTER 19.4 Conversion Data Protection Function This 8/10-bit A/D converter has a conversion data protection function to enable continuous conversion and saving of multiple data items by µDMA. ■ Conversion data protection function The 8/10-bit A/D converter has only a single conversion data register. In continuous A/D conversion, conversion data is lost when the next conversion operation ends and its result is stored in the register. To prevent this, the A/D converter stops without storing a conversion result to the register in cases when a conversion has been completed, but the result of the previous conversion has not been transferred yet to memory via µDMA. The stop is canceled after the data has been transferred by µDMA. Provided conversion data is transferred normally, A/D conversion is performed without pausing. ■ Caution when using the conversion data protection function There is a relationship between the INT and INTE bits of ADCS2 and the operation of the conversion data protection function. The conversion data protection function operates only in the interrupt enabled state (INTE = 1). In interrupt disabled state (INTE = 0), this function does not operate. In continuous A/D conversion, conversion results will be stored in succession and older results are lost. If µDMA is not used in the interrupt enabled state (INTE = 1), the INT bit will not be cleared and the data protection function becomes effective, stopping the operation of the 8/10-bit A/D converter. Clear the INT bit in this case to cancel the stop. When interrupts are disabled during DMAC operation while A/D conversion is stopped, data in the conversion data registers will sometimes change before A/D conversion starts and data is transferred. Data that was stored during the stop will be lost if data conversion is restarted during operation stop. 374 CHAPTER 19 8/10-BIT A/D CONVERTER ■ Operation flow of conversion data protection function operation (when DMAC is used) Figure 19.4-1 "Operation flow of conversion data protection function (when DMAC is used)" shows the operation flow of the conversion data protection function. Figure 19.4-1 Operation flow of conversion data protection function (when DMAC is used) µDMA setting The operation flow for the case in which the A/D converter is not running is omitted. Start of continuous A/D conversion First conversion finished Caution: Conversion data will be lost if conversion is restarted during a stop. Store the result in the data register µDMA start Second conversion finished End of µDMA YES NO Store the result in the data register Third conversion finished A/D converter pause YES µDMA ends See CAUTION. NO µDMA starts Continued All conversions finished µDMA starts Interrupt routine End A/D converter stop 375 CHAPTER 19 8/10-BIT A/D CONVERTER 19.5 Precautions When Using the 8/10-bit A/D Converter This section explains precautions required when the 8/10-bit A/D converter is used. ■ Start by external trigger/internal trigger Whether to start the A/D converter by an external trigger or the internal timer is specified using the STS1 and STS0 A/D startup source bits of the ADCS2 Register. Specify the input values of the external trigger and internal timer only in the inactive state. Making these setting in the active state will sometimes cause an immediate start of operation. When STS1 and STS0 are set, perform conversion with ADTG = 1 input and internal timer (PPG1) = 0 output. ■ Handling of analog input pins Be sure to set the ADER bits corresponding to the pins used in analog input to "1". bit 7 6 5 4 3 2 1 0 Initial value Address: 00001FH ADE7 ADE6 ADE5 ADE4 ADE3 ADE2 ADE1 ADE0 11111111B R/W R/W R/W R/W R/W R/W R/W R/W The settings for pin control of the pins of Port 6 are as follows: • 0: Port input/output mode • 1: Analog input mode At reset, "1" will be set. 376 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE This chapter provides an overview of the expanded I/O serial interface and its operation, and explains the configuration and functions of its registers. 20.1 "Overview of Expanded I/O Serial Interface" 20.2 "Registers of Expanded I/O Serial Interface" 20.3 "Operations of Expanded I/O Serial Interface" 377 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.1 Overview of Expanded I/O Serial Interface The expanded I/O serial interface is a serial I/O interface with an 8-bit/1-channel configuration that is used to transfer data by clock synchronization. For data transfer, LSB first or MSB first can be selected. ■ Overview of expanded I/O serial interface The expanded I/O serial interface has the following two operation modes: • Internal shift clock mode: This mode transfers data by synchronization with the internal clock. • External shift clock mode: This mode transfers data by synchronization with a clock that is supplied via an external pin (SCK). Data can also be transferred in this mode by using a general-purpose port that shares the external pin (SCK). ■ Block diagram of expanded I/O serial interface Figure 20.1-1 "Block diagram of expanded I/O serial interface" shows a block diagram of the expanded I/O serial interface. Figure 20.1-1 Block diagram of expanded I/O serial interface Internal data bus Initial value D7 to D0 (LSB First) (MSB First) D0 to D7 Select transfer direction SIN1, 2 Read Write SDR (Serial data register) SOT1, 2 SCK1, 2 Control circuit Shift clock counter Internal clock 2 1 0 SMD2 SMD1 SMD0 SIE SIR BUSY STOP STRT MODE BDS SOE SCOE Interrupt request Internal data bus 378 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2 Registers of Expanded I/O Serial Interface This section describes the configuration and functions of the registers used by the expanded I/O serial interface. ■ Registers of expanded I/O serial interface Figure 20.2-1 "Registers of the expanded I/O serial interface" shows the registers used by the expanded I/O serial interface. Figure 20.2-1 Registers of the expanded I/O serial interface 15 14 13 12 Address: 000027H SMD2 SMD1 SMD0 SIE 00002BH Address: 000026H 00002AH Address: 000028H 00002CH Address: 000029H 00002DH 7 - 6 - 5 - 4 - 7 D7 6 D6 5 D5 4 D4 15 MD (R/W) 14 (-) 13 (-) 12 (-) 11 10 9 8 SIR BUSY STOP STRT 3 2 MODE BDS 3 D3 2 D2 1 0 SOE SCOE 1 D1 Serial mode control status register (SMCS) 0 D0 Serial data register (SDR) 11 10 9 8 Communication prescaler DIV3 DIV2 DIV1 DIV0 control register (R/W) (R/W) (R/W) (R/W) Reading/writing 379 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2.1 Serial Mode Control Status Register (SMCS) This section describes the configuration and functions of the serial mode control status register (SMCS). ■ Serial mode control status register (SMCS) The serial mode control status register (SMCS) controls the data transfer mode of serial I/O operations. The bit configuration of the serial mode control status register (SMCS) is illustrated below. SMCS 15 14 13 12 address: 000027H SMD2 SMD1 SMD0 SIE 00002BH R/W R/W R/W R/W 7 - SMCS address: 000026H 00002AH 6 - 5 - 4 - 11 10 9 8 Initial value SIR BUSY STOP STRT 00000010B R/W R/W R/W R/W ↑ ↑ Note 1 Note 2 3 2 MODE BDS R/W R/W 1 0 Initial value SOE SCOE ----0000B R/W R/W Note 1: Only "0" can be written Note 2: Only "1" can be written. Reading always returns "0." The functions of the bits of the serial mode control status register (SMCS) are described below. [Bits 15, 14, 13] SMD2, SMD1 and SMD0: Serial Shift Clock Mode (Shift clock select) These bits select the serial shift clock mode. Table 20.2-1 "Settings of serial shift clock mode" shows the settings for the serial shift clock mode. Table 20.2-1 Settings of serial shift clock mode Select the serial shift clock mode as follows: φ=16MHz φ=8MHz φ=4MHz SMD2 SMD1 SMD0 div=8 380 0 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 1 0 1 div=4 div=4 1MHz 1MHz 500KHz 500KHz 500KHz 250KHz 125KHz 125KHz 62.5KHz 62.5KHz 62.5KHz 31.2KHz 31.2KHz 31.2KHz 15.6KHz External shift clock mode reserved reserved Setting of communication prescaler (SDCR) Division factor 2 4 16 32 64 Recommended machine clock speed MD DIV3 DIV2 D1IV DIV0 (Machine clock) Div 1 2 3 4 5 6 7 8 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2MHz 4MHz 6MHz 8MHz 10MHz 12MHz 14MHz 16MHz CHAPTER 20 EXPANDED I/O SERIAL INTERFACE At reset, the settings will be initialized to "000". These bits cannot be rewritten while data transfer is in progress. The shift clock can be selected from among five internal clocks and one external clock. Shifting is performed externally. The combinations of SMD2, 1, 0 = "110" and "111" are reserved and must not be set. Shifting can also be performed for individual instructions by setting SC0E = 0 to select the clock and using a port that shares the pins SCK1 and SCK2. [Bit 12] SIE: Serial I/O Interrupt Enable This bit controls serial I/O interrupt requests as shown below. 0 Serial I/O interrupts prohibited (initial value) 1 Serial I/O interrupts allowed • This bit is initialized to "0" at reset • This bit can be read and written. [Bit 11] SIR: Serial I/O Interrupt Request This bit is set to "1" when serial data transfer ends. When this bit becomes "1" in the interrupt enabled state (SIE = "1"), an interrupt request to the CPU will be generated. The condition for clearing this bit depends on the MODE bit: • Cleared by setting the SIR bit to "0" in a write operation when the MODE bit is "0". • Cleared by reading the SDR or by writing, when the MODE bit is "1". • Cleared by reset or by writing "1" for the STOP bit regardless of the value of the MODE bit. • Writing "1" for this bit has no effect. • Read-modify-write instructions always return "1". [Bit 10] BUSY (transfer status display) This bit indicates whether serial transfer is currently being executed. BUSY Operation state 0 Operation is stopped or the serial data register is in the R/W wait state (initial value) 1 Serial transfer take place • This bit is initialized to "0" at reset. • This bit can only be read. 381 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE [Bit 9] STOP (Stop bit) This bit is used to forcibly interrupt serial transfer. Setting this bit to "1" will result in operation stop because of STOP = 1. STOP Operation 0 Normal operation 1 Stop of transfer because of STOP = 1. (initial value) • This bit is initialized to "0" at reset. • This bit can be read and written. [Bit 8] STRT: Start (start bit) This bit is used to start serial transfer. Write "1" in the stopped state to start transfer. Writing "1" will be ignored during serial transfer operation or when in serial shift register R/W wait state. • Writing "0" has no effect. • Read operations always return "0". [Bit 3] MODE (serial mode selection) This bit selects the condition to start from the stopped state. Rewriting this bit during operation is prohibited. MODE Operation 0 STRT = 1 will start operation. (initial value) 1 Started by reading/writing the serial data register. • This bit is initialized to "0" at reset. • This bit can be read and written. • This bit is set to "1" at µDMA start. [Bit 2] BDS: Bit Direction Select (Selection of transfer direction) This bit selects whether to start transfer with the LSB side (LSB first) or MSB side (MSB first) during input and output of serial data. 0 LSB first (initial value) 1 MSB first • This bit is initialized to "0" at reset. • This bit can be read and written. Note: Specify the transfer direction before writing data to the SDR. 382 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE [Bit 1] SOE: Serial Out Enable (Enable serial output) This bit is used for control of the external output pins (SOT1 and 2) for serial I/O. 0 General-purpose port pin (initial value) 1 Serial data output • This bit is initialized to "0" at reset. • This bit can be read and written. [Bit 0] SCOE: SCK1 Output Enable (Enable shift clock output) This bit controls output of the external input/output pins (SCK1 and 2) for the serial clock. 0 Use of general-purpose port pins, transfer for each instruction (initial value) 1 Shift clock output pin Set to "0" when transferring data for each instruction in external shift clock mode. • Initialized to "0" at reset. • This bit can be read and written. 383 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2.2 Serial Shift Data Register (SDR) This section describes the configuration and functions of the serial shift data register (SDR). ■ Serial shift data register (SDR) The bit configuration of the serial shift data register (SDR) is illustrated below. 7 SDR address: 000028H D7 00002CH R/W 6 D6 R/W 5 4 D5 D4 R/W R/W 3 D3 R/W 2 D2 R/W 1 D1 R/W 0 D0 R/W The serial shift register (SDR) stores transfer data of the serial I/O unit. The SDR cannot be read or written during data transfer. 384 Initial value XXH (Undefined) CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.2.3 Dedicated Prescaler Control Register (SDCR) This section describes the configuration and functions of the dedicated prescaler control register (SDCR). ■ Dedicated prescaler control register (SDCR) The bit configuration of the dedicated prescaler control register (SDCR) is illustrated below. 7 SDCR address: 000029H MD 00002DH R/W 6 - 5 - 4 - 3 2 1 0 DIV3 DIV2 DIV1 DIV0 R/W R/W R/W R/W Initial value 0---0000B The functions of the bits of the dedicated prescaler control register (SDCR) are described below. [Bit 15] MC: Machine clock device moDe select This bit is used to enable operation of the communication prescaler. 0 The communication prescaler stops. 1 The communication prescaler operates. [Bits 11, 10, 9, 8] DIV3, DIV2, DIV1, DIV0: DIVide3 to 0 These bits determine the division factor of the machine clocks. DIV3 to 0 Division Ratio 0000B Division by 1 0001B Division by 2 0010B Division by 3 0011B Division by 4 0100B Division by 5 0101B Division by 6 0110B Division by 7 0111B Division by 8 Note: When changing the clock division factor, allow for a clock stabilization time of two clock cycles before data transfer. 385 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3 Operation of Expanded I/O Serial Interface The expanded I/O serial interface consists of the serial mode control status register (SMCS) and shift register (SDR). This interface is used for input and output of 8-bit serial data. This section describes the operations of the expanded I/O serial interface. ■ Overview of operation of expanded I/O serial interface Input and output with the serial data input/output function are performed as follows: ❍ Serial data input By synchronizing the shift register with the falling edges of a serial shift clock (external or internal clock), data is output to the serial output pin (SOT1 pin) in bit sequences. ❍ Serial data output Synchronized with the rising edge of a serial shift clock (external or internal clock), data is input to the SDR (shift register) from a serial input pin (Pin SIN1). The shift direction (data transfer beginning with the MSB or LSB) can be specified by the bit direction specify (BDS) bit of the serial mode control status register (SMCS). After data transfer is completed, the operation enters the stop state or data register R/W wait state as determined by the MODE bit of the serial mode control status register (SMCS). Perform the following operation to change from each state to the transfer state: 386 • For return from the stop state, set the STOP bit to "0" and write "1" to the STRT bit to set it. (STOP and STRT can be set simultaneously) • For return from the R/W wait state of the serial shift data register, perform a read or write operation for the data register. CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.1 Shift Clock Modes The shift clock has two modes, the internal shift clock mode and the external shift clock mode. These two modes are specified by the setting of the SMCS. Change the mode only when the serial I/O interface is not operating. This condition can be determined by reading the BUSY bit. ■ Internal shift clock mode This mode operates based on an internal clock, and a shift clock with a duty ratio of 50% is supplied via the SCK pin for synchronous timing output. One bit of data is transferred for each clock. The data transfer speed can be calculated as follows: Transfer speed (S) = A Internal clock machine cycle (A) "A" is the division ratio indicated by the SMD bit of SMCS. (φ ÷ div)/2, (φ ÷ div)/22, (φ ÷ div)/24, (φ ÷ div)/25, (φ ÷ div)/26 ■ External shift clock mode In synchronization with an external shift clock supplied via the SCK pin, one bit of data is transferred for each clock. Data can be transferred at a speed up to 1/(8 machine cycles). For example, data can be transferred at a speed of up to 2 MHz when one machine cycle is 62.5 µs. Transfer for individual instructions can be achieved making the following settings: • Select the external shift clock mode and set the SCOE bit of SMCS to "0". • Write "1" to the direction register of the port that shares the SCK pin, then set the port to output mode. After making the above settings, write "1" and "0" to the data register (PDR) to obtain the value of the port that is output to the SCK pin for supplying the external clock for data transfer. Start the shift clock as soon as the "H"-level is input. Note: Writing to the SMCS and SDR during serial I/O operation is prohibited. 387 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.2 Operational States of Serial I/O Units Four serial I/O states are used, namely, STOP, Halt, SDR R/W Wait, and Transfer. ■ Operational states of serial I/O units ❍ STOP State The shift counter is initialized at reset or by writing "1" to the STOP bit of SMCS, resulting in SIR = 0. For returning from the STOP state, set STOP = 0 and STRT= 1 (these bits can be set simultaneously). Because the STOP bit has a higher priority than the STRT bit, data transfer will not be executed even when STRT = 1 is set while STOP = 1. ❍ Halt State When the MODE Bit is set to "0", the BUSY and SIR bit of SMCS will become BUSY = 0 and SIR = 1 after data transfer ends. The counter will then be initialized and set to the Halt state. For returning from the Halt state, set STRT = 1 to resume data transfer operation. ❍ Serial Data Register R/W Wait State When the MODE Bit of SMCS is "1" and serial transfer ends, this will result in BUSY = 0 and SIR = 1 and the serial data register R/W Wait state will be entered. If the interrupt enable register is set to "enable", the applicable block will issue an interrupt signal. When returning from the R/W Wait state, data transfer operation will be resumed as soon as a read or write operation is performed for the serial data register. ❍ Transfer State In this state, serial transfer is performed if BUSY = 1. Depending on the setting of the MODE bit, the Halt or R/W Wait state will be entered. Figure 20.3-1 "State transitions during operation of expanded I/O serial interface" shows the state transitions during operation. Figure 20.3-2 "Concept of read and write of serial data registers" illustrates the concept of reading and writing the serial data register. 388 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE Figure 20.3-1 State transitions during operation of expanded I/O serial interface Reset STOP=0 & STRT=0 Transfer end STOP STOP=1 STRT=0, BUSY=0 MODE=0 MODE=0 STOP=0 & & STOP=0 STRT=1 & End STOP=1 STRT=0, BUSY=0 STOP=0 & STRT=1 Transfer operation STOP=1 Serial data register R/W Wait MODE = 1 / End / STOP = 0 STRT=1, BUSY=1 SDR R/W & MODE=1 STRT=1, BUSY=0 MODE=1 Serial data Figure 20.3-2 Concept of read and write of serial data registers SOT Data bus Read SIN Write Interrupt output Expanded I/O serial interface Data bus Read Write CPU (1) (2) Interrupt input Data bus Interrupt controller 1. For MODE = 1, data transfer is ended by the shift clock counter. A read/write Wait state will be entered after SIR is set to 1. If the SIE bit is "1", an interrupt signal is generated. An interrupt signal will not be generated; however, if the SIE is inactive or when data transfer is stopped by setting the STOP bit by writing "1". 2. As soon as the serial data register is read or written, the interrupt request will be cleared and serial transfer will start. 389 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.3 Start/Stop Timing and Input/Output Timing of Shift Operation Start/stop timing and input/output timing of the shift operation are described below. ■ Start/Stop timing and input/output timing of shift operation • Start Set the STOP bit and STRT bit of SMCS to "0" and "1", respectively. • Stop Operation is stopped by the end of data transfer or as soon as STOP = 1. - If operation stopped because of STOP = 1: Stop is performed while SIR is "0", regardless of the MODE bit. - For an operation stop because of the end of data transfer: SIR is set to "1" and data transfer is stopped regardless of the MODE Bit. Irrespective of the MODE bit, the BUSY bit becomes "1" in the serial data transfer state and "0" during the stop state or R/W wait state. Read this bit for checking the data transfer state. Timing charts illustrating the operation in various modes and the stop operation are provided below. D07 to D00 in the diagram represent output data. ❍ Internal shift clock mode (LSB First) Figure 20.3-3 Start/stop timing and input/output timing in shift operation (using the internal clock) SCK1,2 STRT Output of "1" (Transfer end) (Transfer start) When MODE=0 BUSY SOT1,2 DO0 DO7 (Data hold) ❍ External shift clock mode (LSB first) Figure 20.3-4 Start/stop timing and input/output timing in shift operation (using the external clock) SCK1,2 STRT (Transfer start) (Transfer end) When MODE=0 BUSY SOT1,2 390 DO0 DO7 (Data hold) CHAPTER 20 EXPANDED I/O SERIAL INTERFACE ❍ Instruction shift in external shift clock mode (LSB first) During instruction shift, "H" will be output if the PDR bit corresponding to SCK is set to "1" and "L" will be output if the bit is set to "0". (If SCOE = 0 when external shift clock mode is selected.) Figure 20.3-5 Instruction shift in external shift clock mode SCK1,2 PDR SCK bit "0" STRT PDR SCK bit "1" PDR SCK bit "0" (Transfer end) If MODE = 0 BUSY DO6 SOT1,2 DO7 (Data hold) ❍ Stop by STOP = 1 (LSB first, internal clock used) Figure 20.3-6 Stop timing when the STOP bit is set to "1" SCK1,2 STRT Output of "1" (Transfer end) (Transfer start) If MODE = 0 BUSY STOP DO3 SOT1,2 DO4 DO5 (Data hold) ■ Operation during serial data transfer During serial data transfer, data from the serial output pin (SOT2) is output at a falling edge of the shift clock. Data from the serial input pin (SIN) is input at a rising edge. ❍ LSB first (if the BDS bit is "0") Figure 20.3-7 Input and output shift timing (LSB first) SCK1,2 SIN1,2 SIN input DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DO4 DO5 DO6 DO7 SOT output SOT1,2 DO0 DO1 DO2 DO3 ❍ MSB first (If the BDS bit is "1") Figure 20.3-8 Input and output shift timing (MSB first) SCK1,2 SIN1,2 SIN input DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 DO3 DO2 DO1 DO0 SOT output SOT1,2 DO7 DO6 DO5 DO4 391 CHAPTER 20 EXPANDED I/O SERIAL INTERFACE 20.3.4 Interrupt Function The expanded I/O serial interface can generate interrupt requests for the CPU. ■ Interrupt function of expanded I/O serial interface An interrupt request is output to the CPU when the SIR bit, which acts as an interrupt flag, is set at the end of data transfer provided that the SIE bit of the SMCS, which enables interrupts, is "1". Figure 20.3-9 "Timing for interrupt signal output" shows the timing for output of interrupt signals. Figure 20.3-9 Timing for interrupt signal output SCK1,2 (Transfer end) BUSY SIR * For MODE = 1 SIE=1 SDR RD/WR SOT1,2 392 DO6 DO7 (Data hold) CHAPTER 21 UART This chapter provides an overview of the UART, its operation, and explains the configuration and functions of its registers. 21.1 "Overview of the UART" 21.2 "UART Registers" 21.3 "UART Operations" 21.4 "Precautions on Using the UART" 21.5 "UART Program Example" 393 CHAPTER 21 UART 21.1 Overview of the UART The UART is a serial I/O port for asynchronous (start-stop) communications or CLK synchronous communication. ■ UART features The UART has the following features: 394 • Full-duplex double buffer • Both asynchronous (start-stop) and CLK synchronous communication (no start bit and stop bit) are available • Support of multiprocessor mode • Dedicated built-in baud rate generator • In asynchronous transfer: 76923/38461/19230/9615/500K/250Kbps • In CLK synchronous transfer: 16Mbps/8Mbps/4Mbps/2Mbps/1Mbps/500Kbps • Free baud rate setting via external clock • Internal clock supplied by PPG1 can be used • Data length: 7 bits (asynchronous normal mode only)/8 bits • Master/slave communication function (in multiprocessor mode): 1 (master) to n (slaves) communication enabled • Error detection function (parity, framing, overrun) • Transfer signal: NRZ code • DMAC support (reception/transmission) CHAPTER 21 UART ■ UART block diagram Figure 21.1-1 "Block diagram of the UART" shows a block diagram of the UART. Figure 21.1-1 Block diagram of the UART Control signal Reception interrupt (to CPU) Dedicated baud rate generator PPG1 (internal connection) External clock SCK0 Clock selector circuit Reception Transmission clock Send interrupt (to CPU) clock SIN0 Reception control circuit Transmission control circuit Start-bit detector circuit Transmission start circuit Reception bit counter Transmission bit counter Reception parity counter Transmission parity counter SOT0 Reception state detection circuit Reception shifter DMAC reception error transmission signal (to CPU) Transmission shifter Reception control circuit Transmission start SIDR SODR F2MC-16LX BUS SMR register MD1 PEN PE MD0 P ORE CS2 SBL FRE CS1 CS0 SCR register CL A/D SSR register RDRF TDRE REC BDS SCKE REX RIE SOE TXE TIE Control signal 395 CHAPTER 21 UART 21.2 UART Registers This section describes the configuration and functions of the registers used by the UART. ■ List of UART registers Figure 21.2-1 "List of UART registers" lists the UART registers. Figure 21.2-1 List of UART registers 15 8 7 CDCR SCR SSR 0 SMR SIDR(R)/SODR(W) 8 bits (R/W) (R/W) (R/W) 8 bits 7 6 5 4 3 2 1 0 000020H MD1 MD0 CS2 CS1 CS0 Reserved SCKE SOE Serial mode register (SMR) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (X) (0) (0) Initial value 15 14 13 12 11 10 9 8 000021H PEN P SBL CL A/D REC RXE TXE Serial control (SCR) (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (1) (0) (0) Initial value 000022H 000023H 000025H 7 6 5 4 3 2 1 0 Serial input register (SIDR)/ D7 D6 D5 D4 D3 D2 D1 D0 serial output register (SODR) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (X) (X) (X) (X) (X) (X) (X) (X) Initial value 15 PE (R) (0) 14 13 12 11 10 9 8 ORE FRE RDRF TDRE BDS RIE TIE Serial status register (SSR) (R) (R) (R) (R) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (1) (0) (0) (0) Initial value 15 14 MD SRST (R/W) (R/W) (0) (0) 13 (-) (-) 12 (-) (-) 11 10 9 8 DIV3 DIV2 DIV1 DIV0 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) Communication prescaler control register (CDCR) Reading/writing Initial value Note: When setting a UART register, set the communication mode while the converter is not in operation. When the communication mode is changed while operation is in progress, the data in send/receive operations cannot be assured. 396 CHAPTER 21 UART 21.2.1 Serial Mode Register (SMR) This section describes the configuration and functions of the serial mode register. ■ Serial mode register (SMR) The bit configuration of the serial mode register (SMR) is illustrated below. 7 6 5 4 3 2 1 0 000020H MD1 MD0 CS2 CS1 CS0 Reserved SCKE SOE Serial mode register (SMR) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (X) (0) (0) Initial value The functions of the bits of the serial mode register (SMR) are as follows. [Bits 7, 6] MD1, MD0: Mode Select These bits are used to select the UART operation mode. Mode MD1 MD0 Operation mode 0 0 0 Asynchronous (start-stop) normal mode 1 0 1 Asynchronous (start-stop) multiprocessor mode 2 1 0 CLK synchronous mode - 1 1 Setting prohibited In Mode 1, the CLK asynchronous mode (multiprocessor mode), several slave CPUs are connected to one host CPU. The MB90470 cannot distinguish the data format of reception data; therefore, it supports only the master in multiprocessor mode. The parity check function cannot be used. Set the PEN bit of the SCR Register to "0". [Bits 5, 4, 3] CS2, CS1, CS0: Clock Select These bits select the baud rate clock sources. When a dedicated baud rate generator is selected, the baud rate will be determined at the same time. CS2 to 0 000B to 101B Clock input Dedicated baud rate generator 110B Internal clock 111B External clock • PPG1 will be selected in the MB90470 if an internal clock is selected. • The use of the clock division ratio 1/1 (CS-CS0 = 000B) during synchronous transfer is prohibited. [Bit 2] not used This bit is not used. 397 CHAPTER 21 UART [Bit 1] SCKE: SCLK Enable This bit specifies whether to use SCK0 as a clock input pin or as a clock output pin during communication in CLK Synchronous Mode (Mode 2). Set this bit to "0" in CLK asynchronous mode or external clock mode. • 0: SCK0 functions as clock input pin. • 1: SCK0 functions as clock output pin. Note: An external clock source must be selected in advance when specifying use as a clock input pin via this bit. [Bit 0] SOE: Serial Output Enable This bit specifies whether to use the external pin (SOT0), which is used also as a generalpurpose I/O port pin, as a serial input pin or as an I/O port pin. 398 • 0: The pin functions as a general-purpose I/O port pin. • 1: The pin functions as the serial data output pin (SOT0). CHAPTER 21 UART 21.2.2 Serial Control Register (SCR) This section describes the configuration and functions of the serial control register (SCR). ■ Serial control register (SCR) The bit configuration of the Serial Control Register (SCR) is illustrated below. 15 14 13 12 11 10 9 8 P SBL CL A/D REC RXE TXE Serial control (SCR) 000021H PEN (R/W) (R/W) (R/W) (R/W) (R/W) (W) (R/W) (R/W) Reading/writing (0) (0) (0) (0) (0) (1) (0) (0) Initial value The functions of the bits of the serial control register (SCR) are as follows: [Bit 15] PEN: Parity ENable This bit specifies whether to add a parity bit during transmission and to detect it during receiving when processing serial data. 0 No parity 1 Parity provided Note: Parity can be added only in normal mode (Mode 0) in asynchronous (start-stop) communication mode. Parity cannot be added in multiprocessor mode (Mode 1) or in CLK synchronous communication (Mode 2). [Bit 14] P: Parity This bit specifies whether to use even or odd parity in data communications with parity. 0 Even parity 1 Odd parity [Bit 13] SBL: Stop Bit Length This bit specifies the bit length of the stop bit, which is a frame end mark in asynchronous (start-stop) communication. 0 1 stop bit 1 2 stop bits 399 CHAPTER 21 UART [Bit 12] CL: Character Length This bit specifies the data length of one frame to be sent or received. 0 7-bit data 1 8-bit data Note: Only the normal mode (Mode 0) in asynchronous (start-stop) communications can handle 7bit data. Use 8-bit data only in multiprocessor mode (Mode 1) or CLK synchronous communication (Mode 2). [Bit 11] A/D: Address/Data This bit specifies the data format for frames to be sent and received in multiprocessor mode (Mode 1) during asynchronous (start-stop) communication. 0 Data frame 1 Address frame [Bit 10] REC: Receiver Error Clear This bit clears the error flags (PE, ORE, FRE) of the SSR Register. Writing "1" has no effect. Read operations always return "1". [Bit 9] REX: Receiver Enable This bit controls the reception state of the UART. 0 Disables reception operation 1 Enables reception operation If reception operation becomes disabled while reception is in progress (while data is input to the reception shift register), reception operation will only be disabled after reception of the frame is completed and the reception data is stored in the reception data buffer register (SIDR). [Bit 8] TEX: Transmitter Enable This bit controls the UART transmission states. 0 Disables transmission operation 1 Enables transmission operation If transmission operation becomes disabled while transmission is in progress (while data is output from the transmission register), transmission operation will only be disabled after the transmission data buffer register SODR no longer contains transmission data. Transmission is resumed by synchronization with an internal serial clock after writing a value to the transmission data buffer register (SODR). Disabling of transmission (TEX = 0) is invalid when the TDRE Flag is "0". 400 CHAPTER 21 UART 21.2.3 Serial Input/Output Register (SIDR/SODR) This section describes the configuration and functions of the serial input/output register (SIDR/SODR). ■ Serial input/output register (SIDR/SODR) The bit configuration of the serial input/output register (SIDR/SODR) is illustrated below. 000022H 7 6 5 4 3 2 1 0 Serial input register (SIDR)/ D7 D6 D5 D4 D3 D2 D1 D0 serial output register (SODR) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Reading/writing (X) (X) (X) (X) (X) (X) (X) (X) Initial value The first bit (D7) of the serial input/output register (SIDR/SODR) will become invalid when the stored data elements are 7 bits long. Always set the TDRE of the SSR register to "1" when writing data elements to the SODR Register. Note: Write data elements at this address by the same method as that in writing data elements in the SODR Register. This address is read by the same method as that used in reading addresses of the SIDR Register. 401 CHAPTER 21 UART 21.2.4 Serial Status Register (SSR) This section describes the configuration and functions of the serial status register (SSR). ■ Serial status register (SSR) The bit configuration of the serial status register (SSR) is illustrated below. 000023H 15 PE (R) (0) 14 13 12 11 10 9 8 ORE FRE RDRF TDRE BDS RIE TIE Serial status register (SSR) (R) (R) (R) (R) (R/W) (R/W) (R/W) Reading/writing (0) (0) (0) (1) (0) (0) (0) Initial value The SSR provides a flag that represent the UART status. The functions of the serial status register (SSR) bits are described below. [Bit 15] PE: Parity Error This bit acts as an interrupt request flag that is set when a parity error occurs during receiving. Set the REC bit (bit 10) of the SSR register to "0" to clear a flag that has been set. The data in the SIDR becomes invalid when this bit is set. 0 No parity error 1 Parity error detected [Bit 14] ORE: Over Run Error This bit is an interrupt request flag that is set in case an overrun error occurs during reception. Set the REC bit (bit 10) of the SSR register to "0" to clear a flag that has been set. The data in the SIDR becomes invalid when this bit is set. 0 No overrun error 1 Overrun error detected [Bit 13] FRE: FRaming Error This bit is an interrupt request flag that is set in case a framing error occurs during reception. Set the REC bit (bit 10) of the SSR register to "0" to clear a flag that has been set. The data in the SIDR becomes invalid when this bit is set. 0 No framing error 1 Framing error detected [Bit 12] RDRF: Receiver Data Register Full This bit is an interrupt request flag that indicates that the SIDR register has stored reception data. This flag is set when reception data is loaded into the SIDR register and is cleared automatically when the SIDR register is reads. 402 CHAPTER 21 UART 0 No reception data 1 Reception data loaded [Bit 11] TDRE: Transmitter Data Register Empty This bit acts as an interrupt request flag that indicates that transmission data can be written to the SODR register. This flag is cleared when transmission data is written to the SODR register. The flag will be set again reset to indicate that the next item of transmission data can be written as soon as written data has been loaded into the transmission shift unit and data transfer starts. 0 Prohibit writing of transmission data 1 Allow writing of transmission data [Bit 10] BDS This bit is used to control the selection of a data transfer direction. 0 Serial data is transferred starting with the LSB side. (LSB first) 1 Serial data is transferred starting with the MSB side. (MSB first) Note: When this bit is rewritten after writing data to the SDR register to switch between the upper side and lower side of data, the data in the serial status register becomes invalid in read and write operations. [Bit 9] RIE: Receiver Interrupt Enable This bit controls reception interrupts. 0 Prohibit interrupts. 1 Allow interrupts. In addition to PE, ORE, and FRE errors, normal reception by RDRF also acts as reception interrupt source. [Bit 8] TIE: Transmitter Interrupt Enable This bit controls send interrupts. 0 Prohibit interrupts. 1 Allow interrupts. Note: If transmission operation becomes disabled during transmission, the transmission operation stops after no more data remains in the transmission data buffer (SODR1). For writing "0", wait a predefined time after data has been written to SODR1. In clock asynchronous transfer mode, the term "predefined time" means 1/16 the time corresponding to the baud rate using in clock asynchronous transfer mode. In clock synchronous transfer mode, this term refers to the time corresponding to the baud rate. 403 CHAPTER 21 UART 21.2.5 Communication Prescaler Control Register (CDCR) This section describes the configuration and functions of the communication prescaler control register (CDCR). ■ Communication prescaler control register (CDCR) The bit configuration of the communication prescaler control register (CDCR) is illustrated below. 15 14 MD SRST (R/W) (R/W) (0) (0) 000025H 13 (-) (-) 12 (-) (-) 11 10 9 8 DIV3 DIV2 DIV1 DIV0 (R/W) (R/W) (R/W) (R/W) (0) (0) (0) (0) Communication prescaler control register (CDCR) Reading/writing Initial value The UART operation clocks are obtained by dividing the machine clock. The converter is designed so that constant baud rates with respect to various machine clocks are obtained through the communication prescaler. The CDCR is a register that controls machine clock division. [Bit 15] MD: Machine clock divide moDe select This bit is used to enables operation of the communication prescaler. 0 The communication prescaler stops. 1 The communication prescaler operates. [Bits 14] SRST: Set ReSeT This bit resets all operations of the UART. It initializes all data and register values. 0 Initial value (has no effect) 1 Forced reset Note: Setting this bit will forcibly clear all data and register values. All setting values will return to their initial values. Data being transferred as well as saved data will be invalid until the respective settings have been made again. 404 CHAPTER 21 UART [Bits 11, 10, 9, 8] DIV3, DIV2, DIV1, DIV0: DIVide3 to 0 These bits are used to determine the division ratios of the machine clocks. DIV3 to 0 Division Ratio 0000B Division by 1 0001B Division by 2 0010B Division by 3 0011B Division by 4 0100B Division by 5 0101B Division by 6 0110B Division by 7 0111B Division by 8 Note: • When changing the clock division factor, allow for a clock stabilization time of two clock cycles before data transfer. • The use of the clock division ratio 1/1 (CS2 to CS0 = 000B) during synchronous transfer is prohibited. 405 CHAPTER 21 UART 21.3 UART Operations This section describes the operations of the UART. ■ Operation modes UART has the operation modes shown below. The modes can be changed by setting values in the SMR and SCR Registers. Mode 0 Parity Data length Provided/not provided 7 Provided/not provided 8 1 None 8 + 1 (*1) 2 None 8 Operation mode Stop bit length Asynchronous (start-stop) normal mode 1 bit or 2 bits (*2) Asynchronous (start-stop) multiprocessor mode CLK synchronous mode None *1: The "+1" term represents the address/data selection bit (A/D) used in communication control. *2: Only one bit can be detected as stop bit during reception. The stop bit length in asynchronous (start-stop) mode can only be specified for send operations. The bit length in reception operations is always one bit. Only the modes above are supported for operation; do not set any other mode. UART operation mode 1 is used only for the master in master/slave connection. ❍ Connection between CPUs 1:1 connection (normal mode) or master/slave connection (multiprocessor mode) can be selected. The data length, whether or not to add a parity bit, synchronization, and other specifications for these two systems must be the same across all CPUs. The following operation modes can be selected: 406 • In 1:1 connection (normal mode), the same operation mode, either operation mode 0 or operation mode 2, must be selected for both CPUs. Select Operation Mode 0 for asynchronous operation. Select Operation Mode 2 for synchronous operation. • In master/slave connection (multiprocessor mode), use Operation Mode 1. Select operation mode 1 and use this device as the master. For this type of connection, select "no parity". CHAPTER 21 UART ■ UART clock selection ❍ Dedicated Baud Rate Generator - Asynchronous baud rate = Φ / (prescaler division ratio) / (asynchronous transfer clock division ratio) - Synchronous baud rate = Φ / (prescaler division ratio) / (synchronous transfer clock division ratio) Φ: Machine clock • The division ratios provided by the prescaler (common for asynchronous/synchronous operation) are listed in Table 21.3-1 "List of UART registers". Table 21.3-1 List of UART registers • MD DIV3 to 0 DIV 0 - Stop 1 0000B 1 1 0001B 2 1 0010B 3 1 0011B 4 1 0100B 5 1 0101B 6 1 0110B 7 1 0111B 8 For the division ratios of the synchronous transfer clock, see Table 21.3-2 "Division ratios of the synchronous transfer clock". Table 21.3-2 Division ratios of the synchronous transfer clock CS2 CS1 CS0 CLK synchronous Calculation formula SCK0 0 0 0 - (Φ / DIV)/1 (Φ / DIV)/1 0 0 1 8M (Φ / DIV)/2 (Φ / DIV)/2 0 1 0 4M (Φ / DIV)/4 (Φ / DIV)/4 0 1 1 2M (Φ / DIV)/8 (Φ / DIV)/8 1 0 0 1M (Φ / DIV)/16 (Φ / DIV)/16 1 0 1 500K (Φ / DIV)/32 (Φ / DIV)/32 Φ: Calculated based on the machine clock (internal frequency f=16 MHz) for DIV=1. Note: A clock division ratio of 1/1 (CS2-CS0=000B) cannot be used during synchronous transfer. 407 CHAPTER 21 UART • For the division ratios of the asynchronous transfer clock, see Table 21.3-3 "Division ratios of the asynchronous transfer clock". Table 21.3-3 Division ratios of the asynchronous transfer clock CS2 CS1 CS0 Non-CLK synchronous Calculation formula SCK0 0 0 0 76923 (Φ / DIV)/(8 x 13 x 2) (Φ / DIV)/(13 x 2) 0 0 1 38461 (Φ / DIV)/(8 x 13 x 4) (Φ / DIV)/(13 x 4) 0 1 0 19230 (Φ / DIV)/(8 x 13 x 8) (Φ / DIV)/(13 x 8) 0 1 1 9615 (Φ / DIV)/(8 x 13 x 16) (Φ / DIV)/(13 x 16) 1 0 0 500K (Φ / DIV)/(8 x 2 x 2) (Φ / DIV)/2 1 0 1 250K (Φ / DIV)/(8 x 2 x 4) (Φ / DIV)/4 Φ: Calculated based on the machine clock (internal frequency f=16 MHz) for DIV=1. 408 CHAPTER 21 UART ❍ Internal timer The applicable baud rate when CS2 to CS0 are set to "110" and the internal timer (PPG1) is selected can be calculated by the following expressions: Asynchronous (start-stop): (Φ Φ / N) /(16 x 2 x (n + 1)) CLK synchronous: (Φ Φ / N)/(2 x (n + 1)) N: Count clock source of the timer (PPG1) n: Reload value of the timer (PPG1) Table 21.3-4 "Relationship between baud rate and reload value (machine clock frequency: 7.3728 MHz)" shows the relationship between the baud rate and reload value when the machine clock frequency is 7.3728 MHz. Table 21.3-4 Relationship between baud rate and reload value (machine clock frequency: 7.3728 MHz) Reload value Clock asynchronous (Start-Stop) Baud rate Clock synchronous N = 21 (divide-by-2 of machine clock) N = 23 (divide-by-8 of machine clock) N = 21 (divide-by-2 of machine clock) N = 23 (divide-by-8 of machine clock) 38400 2 - 47 11 19200 5 - 95 23 9600 11 2 191 47 4800 23 5 383 95 2400 47 11 767 191 1200 95 23 1535 383 600 191 47 3071 767 300 383 95 6143 1535 Note 1: "-" indicates that a setting is prohibited ❍ External Clock The baud rate when CS2 to CS0 are set to "111" can be calculated by the following expressions: Asynchronous (start-stop): f / 16 CLK synchronous: f' f can be up to 1/2 of the machine clock at maximum. f' can be up to 1/8 of the machine clock at maximum. 409 CHAPTER 21 UART 21.3.1 Operation in Asynchronous Mode (Operation Modes 0 and 1) Transfer operation becomes asynchronous when the UART is used in Operation Mode 0 (normal mode) or in Operation Mode 1 (multiprocessor mode). ■ Operation in asynchronous mode (operation modes 0 and 1) ❍ Transfer data format Transfer data always starts with a start bit ("L"-level), a transfer operation of a specified bit length is performed LSB first, and transfer ends with a stop bit ("H"-level). • In Operation Mode 0, data items without parity are fixed at a length of 7 bits, while data items with parity have a length of 8 bits. • In Operation Mode 1, the data length is fixed at 8 bits and a parity bit is not added. Instead, an A/D (address/data selection bit) is added. Figure 21.3-1 Transfer data format (asynchronous mode) Operation Mode 0 ST D0 D1 D2 D3 D4 D5 D6 D7*1/P*2 SP Operation Mode 1 ST D0 D1 D2 D3 D4 D5 D6 D7 A/D *1 : D7 (Data bit 7) ..... without parity *2 : P (Parity bit) ......... with parity SP ST : Start bit SP : Stop bit A/D : Address/data selection bit in Operation Mode 1 (multiprocessor mode) ❍ Send Operation When the transmission data empty flag bit (SSR: TDRE) is "1", send data is written to the output data register (SODR). The data is sent if send operation is enabled (SCR: TXE = 1) at that time. Send data is sent to the send shift register and sending starts. The TDRE Flag is then reset to "1" to enable setting of the next item of send data. If transmission interrupt requests are enabled (SSR: TIE = 1), a transmission interrupt request is output to request writing of the send data to the SODR. The TDRE flag is cleared to "0" when send data has been written to the SODR. 410 CHAPTER 21 UART ❍ Reception Operation Reception is always performed if reception operation is enabled (SCR: REX = 1). When the start bit is detected, one frame of data is received in accordance with the data format determined by the control register (SCR). When the error flag is set after one frame has been received, the reception data full flag bit (SSR: RDRF) is set to "1". If reception interrupt requests are enabled (SSR: RIE = 1), a reception interrupt request is output in this case. Each flag of the status register (SSR) is checked. If reception was performed normally, the input data register (SIDR) is read; if an error is detected, error processing is performed. The RDRF flag is cleared to "0" after reception data is read from the SIDR. ❍ Detecting the start bit Implement the following settings to detect the start bit: • Set the communication line level to H (attach the mark level) before the communication period. • Specify reception permission (RXE = H) while the communication line level is H (mark level). • Do not specify reception permission (RXE = H) for periods other than the communication period (without mark level). Otherwise, data is not received correctly. • After the stop bit is detected (the RDRF flag is set to 1), specify reception inhibition (RXE = L) while the communication line level is H (mark level). Figure 21.3-2 Normal operation Communication period Non-communication period Mark level Start bit SIN ST Non-communication period Stop bit Data D0 D1 D0 D1 D2 D3 D4 D5 D6 D7 SP (Sending 01010101b) RXE Receive clock Sampling clock Receive clock (8 pulse) Recognition by the microcontroller ST Generating sampling clocks by dividing the receive clock by 16 D2 D3 D4 D5 D6 D7 SP (Receiving 01010101b) Note that specifying reception permission at the timing shown below obstructs the correct recognition of the input data (SIN) by the microcontroller. • Example of operation if reception permission (RXE = H) is specified while the communication line level is L. Figure 21.3-3 Error operation Communication period Non-communication period Mark level SIN (Sending 01010101b) RXE Start bit ST D0 Non-communication period Stop bit Data D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D6 D7 D5 D6 D7 SP SP Receive clock Sampling clock Recognition by the microcontroller ST recognition (Receiving 10101010b) PE,ORE,FRE Occurrence of a reception error 411 CHAPTER 21 UART ❍ Stop bit Use of one or two stop bits can be selected for sending. The receiving unit, however, will only identify the first stop bit. ❍ Error detection • Mode 0: Parity errors, overrun errors, and frame errors can be detected. • Mode 1: Overrun and frame errors can be detected. Parity errors cannot be detected. ❍ Parity 0 Parity can be used only in Operation Mode 0 (asynchronous and normal modes). Whether to use parity can be set with the PEN bit, while use of even or odd parity can be selected with the P Bit of the control register (SDR). Parity cannot be used in operation mode 1 (asynchronous and multiprocessor modes) and Operation Mode 2 (synchronous and normal modes). Figure 21.3-4 "Transfer data format when using parity" shows the data format for send and receive data when parity is used. The items "ST" and "SP" in the diagram indicate the "start bit" and "stop bit" respectively. Figure 21.3-4 Transfer data format when using parity SIN0 ST SP 1 SOT0 0 1 1 0 0 during reception with even parity 0 ST A parity error has occurred (SCR: P = 0) SP Sending of even parity 1 SOT0 0 1 1 0 0 1 ST (SCR: P = 0) SP 1 0 1 Data 1 0 0 0 Parity Note: Parity cannot be used in Operation Modes 1 and 2. 412 Sending of odd parity (SCR: P = 1) CHAPTER 21 UART 21.3.2 Operation in Synchronous Mode (Operation Mode 2) The transfer operation becomes clock-synchronous when the UART operates in Operation Mode 2 (normal mode). ■ Operation in synchronous mode (operation mode 2) ❍ Transfer Data Format In synchronous mode, 8-bit data is transferred LSB first, and no start bit or stop bit are added. Figure 21.3-5 "Transfer data format (in synchronous mode)" shows the data format in synchronous mode: Figure 21.3-5 Transfer data format (in synchronous mode) Send data write Mark level Send and receive clock RXE,TXE Send and receive data 1 LSB 0 1 1 0 0 Data 1 0 MSB ❍ Clock Supply In a clock synchronous (expanded I/O serial) operation, a number of clock pulses equivalent to the number of bits in the transmission data must be supplied during transmission. When an internal clock (dedicated baud rate generator or internal timer) is selected, a data reception synchronous clock will be supplied automatically when data is sent. If an external clock is selected, the output data register (SODR) in the UART of the transmission side system must contain data. After confirmation that TDRE of the SSR is 0, clock pulses for one byte must be supplied correctly from the outside. Always set the mark level "H" before and after sending data. ❍ Error Detection Only overrun errors can be detected. Parity and framing errors cannot be detected. 413 CHAPTER 21 UART ❍ Initialization The appropriate setting values for the control registers when using synchronous mode are shown below. [Mode register (SMR)] • MD1 and MD0: "10" • CS2, CS1, CS0: Specify the clock determined by the clock selector. • SCKE: "1" if the dedicated baud rate generator or internal clock is used, "0" when the external clock is used. • SOE: "1" for sending. "0" for only receiving. [Control register (SCR)] • PEN: "0" • P, SBL, A/D: These bits have no effect. • CL: "1" (8-bit data) • REC: "0" (Error flag clear for initialization) • RXE: TXE: Ensure that at least one of RXE and TXE is "1". [Status Register (SSR)] • RIE: "1" when interrupts are used. "0" if no interrupts are used. • TIE: "0" ❍ Communication start Start communication by writing to the Output Data Register (SODR). Note that temporary data must be written to the SODR before starting communication, even when receiving data. ❍ Communication end After the end of transmission of one data frame, the RDRF flag of the status register (SSR) is set to "1". During reception, check the overrun error flag bit (SSR: ORE) and decide whether communication has been performed normally. 414 CHAPTER 21 UART 21.3.3 Two-Way Communication Function (Normal Mode) Normal serial two-way communication in a 1:1 connection can be performed in Operation Modes 0 and 2. The synchronization type is "asynchronous" for Operation Mode 0 and "synchronous" for Operation Mode 2. ■ Register settings in two-way communication Set the registers as shown in Figure 21.3-6 "Register settings in two-way communication" before starting two-way communication. Figure 21.3-6 Register settings in two-way communication 15 14 13 12 Bit SCR/SMR PEN P SBL CL Mode 0 1 Mode 2 0 11 10 9 8 7 6 5 4 3 2 1 0 AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE 0 0 0 0 1 0 SSR, SIDR/SODR PE ORE FRE TDRF Mode 0 Mode 2 - RIE TIE Set conversion data (during write)/store reception data (during read) DDR7*1 P77 P76 P75 P74 P73 P72 P71 P70 *1 : When UART0 is used, set the bits 1 and 2 of DDR7. : Bit used : Bit not used 1 : Set to "1" 0 : Set to "0" : Set "0" when pin input is used ■ Connection between CPUs in two-way communication Figure 21.3-7 "Connection between CPUs in two-way communication" shows the connection between CPUs in two-way communication. Figure 21.3-7 Connection between CPUs in two-way communication SOT0 SOT0 SIN0 SCK0 SIN0 SCK0 Output CPU1 Input CPU2 415 CHAPTER 21 UART ■ Communication procedure for two-way communication function Communication is started by the sending side with an arbitrary timing when data for transmission is ready. The receiving side receives the transmission data and periodically returns ANS (in this example, separately for each byte). Figure 21.3-8 "Communication procedure for two-way communication function" illustrates the procedure for communication with the two-way communication function. Figure 21.3-8 Communication procedure for two-way communication function (Transmission side) (Transmission side) Start Setting the operation mode (Matching the setting of the sending side setting) Setting the operation mode (0 or 2) Sending data Communication after storing 1-byte data in UODR NO Reception data available? YES NO Reception data available? YES Reading and processing reception data Sending data Reading and processing reception data Sending 1-byte data (ANS) 416 CHAPTER 21 UART 21.3.4 Master/Slave Communication Function (Multiprocessor Mode) The UART enables communication in a master/slave connection in which more than one slave CPU is connected. Operation Mode 1 is used in this case. The UART itself can be used only as the master system. ■ Register settings in master/slave communication Set the registers as shown in Figure 21.3-9 "Register settings in master/slave communication" before starting master-slave communication. Figure 21.3-9 Register settings in master/slave communication 15 14 13 12 Bit SCR/SMR PEN P SBL CL 1 Mode 1 0 SSR, SIDR/SODR PE ORE FRE TDRF Mode 1 DDR7*1 11 10 9 8 7 6 5 4 3 2 1 0 AD REC RXE TXE MD1 MD0 CS2 CS1 CS0 BCH SCKE SOE 0 0 1 0 - RIE TIE Set conversion data (during write)/store reception data (during read) P77 P76 P75 P74 P73 P72 P71 P70 *1 : When UART0 is used, set the bits 1 and 2 of DDR7. : Bit used : Bit not used 1 : Set to "1" 0 : Set to "0" : Set "0" when pin input is used 417 CHAPTER 21 UART ■ Connection between CPUs in master/slave communication Figure 21.3-10 "Connection between CPUs in master/slave communication" shows the connection between CPUs in master/slave communication. Figure 21.3-10 Connection between CPUs in master/slave communication SOT0 SIN0 SOT SIN SOT SIN Master CPU Slave CPU #0 Slave CPU #0 ■ Function selection Table 21.3-5 "Function selection in master/slave communication" lists settings for selecting the communication method in master/slave communication. Table 21.3-5 Function selection in master/slave communication Operation mode Master CPU Slave CPU Sending and reception of addresses Parity Synchronous operation Stop bit None Asynchronous 1 or 2 bits AD = "1" + 8-bit address Mode 1 Sending and reception of data Data AD = "0" + 8-bit address ■ Communication procedure of master/slave communication function Communication is started by the master CPU sending address data. Address data is data for which the AD bit is "1"; the address is used to select the slave CPU that becomes the communication destination. Each slave CPU interprets the address data by a program. If the address data matches the address assigned to the system, communication (transfer of ordinary data) with the master CPU is established. Figure 21.3-11 "Procedure for communication using the master/slave communication function" shows the procedure for communication using the master/slave communication function. 418 CHAPTER 21 UART Figure 21.3-11 Procedure for communication using the master/slave communication function (Master CPU) Start Set operation mode 1 The SIN pin is specified as serial data input Specify one-byte data (address data) for selecting the slave CPUs in D0 to D7, and send data (AD = 1) Set AD to "0" Enable reception Communication with slave CPUs Communication end? NO YES Communications with other slave CPUs? END NO YES Prohibit reception operation 419 CHAPTER 21 UART 21.4 Precautions on Using the UART This section lists caution remarks applying to the use of the UART. ■ Precautions on using the UART ❍ Enabling operation The control register (SCR) of the UART contains operation enable bits for enabling sending and receiving, namely, TXT (sending) and RXE (reception). By default (as initial value), both sending and receiving must be disabled to stop data transfer. If required, data transfer can also be disabled during operation. ❍ Communication Mode Setting Set the communication mode while the converter is not in operation. Transmission and reception data cannot be assured if the mode is changed during data transmission or reception. ❍ Synchronous mode The clock synchronous mode (Operation Mode 2) of the UART uses a clock control (expanded I/O serial) operation, and a start bit or stop bit is not added to data. ❍ Transmission data empty flag bit By default (as initial value), the transmission data empty flag bit (TDRE of SSR) is set to "1" (no transmission data, transmission data can be written). Therefore, when transmission interrupt requests are enabled (TIE = 1 of SSR), a transmission interrupt request will be triggered immediately. Be sure that the send data is available before setting the TIE flag to "1". ❍ Clock division ratio of 1/1 in synchronous transfer The use of a cock division ratio 1/1 (CS2 to CS0 = 000B) in synchronous transfer is prohibited. 420 CHAPTER 21 UART 21.5 UART Program Example This section provides and explains a sample program for the UART. ■ UART program example ❍ Specification of processing Serial transmission and reception are executed using the two-way communication function (normal mode) of the UART. • Operation mode 0, asynchronous operation, data length of 8 bits, 2 stop bits, and no parity are set. • P70 (SIN0) and P72 (SCK0) are used for communication. • A dedicated baud rate generator is used, and a baud rate of about 9600bps is set. • The character "13H" is sent from the SOT0 pin, and the data is received using an interrupt. • The machine clock frequency (φ) is 16 MHz. 421 CHAPTER 21 UART ❍ Sample code ICR11 EQU 0000BBH ; Control register for UART send interrupts ICR12 EQU 0000BDH ; Control register for UART reception interrupts DDR7 EQU 000017H ; Port-7 direction register SMR EQU 000020H ; Mode register SCR EQU 000021H ; Control register SIDR EQU 000022H ; Input data register SODR EQU 000022H ; Output data register SSR EQU 000023H ; Status register REC EQU SCR:2 ; Reception error flag clear bit ;---- Main Program -----------------------------------------------------------CODE CSEG ABS=0FFH SRAER: ; : ; Initialize stack pointer (SP) and other ; processing elements AND CXCR,#0BFH ; Disable interrupts MOV I:ICR13,#00H ; Interrupt level 0 (Highest) MOV I:DDR7,#00000000B ; Set SIN0 pin as input MOV I:SMR,#00010001B ; Operation mode 0 (asynchronous) ; Select use of dedicated baud rate ; generator (9615 bps) ; Disable clock output disable, enable data ; output MOV I:SSR,#00010011B ; No parity, 2-bit stop bit ; Data length of 8 bits, reception error ; flag clear ; Enable transmission/reception MOV I:SSR,#00000010B ; Disable send interrupts, enable reception ; interrupts MOV I:SODR,#13H ; Write send data MOV ILM,#07H ; Set ILM in the PS to Level 7 OR CCR,&40H ; Enable interrupts LOOP: MOV A,#00H ; Infinite loop MOV A,#01H BRA LOOP ;---- Interrupt Program ------------------------------------------------------WARI: MOV A,SIDR ; Read reception data CLRB I:REC ; Clear reception interrupt request flag ; : ; User processing ; : RETI ; Return from interrupt CODE ENDS ;---- Vector Setting ---------------------------------------------------------VECT CSEG ABS=0FFH ORG 0FF6C ; Vector set to Interrupt #36 (24H) DSL WARI ORG 0FFDCH ; Reset vector setting DSL START DB 00H ; Single chip mode setting VECT ENDS 422 CHAPTER 22 I2C INTERFACE This chapter provides an overview of the I2C interface and its operation, and explains the configuration and functions of its registers. 22.1 "Overview of I2C Interface" 22.2 "Registers of I2C Interface" 22.3 "I2C Interface Operation" 423 CHAPTER 22 I2C INTERFACE 22.1 Overview of I2C Interface The I2C interface is a serial I/O port supporting the Inter IC BUS, allowing master/slave devices to operate over the I2C bus. ■ I2C interface function The I2C interface has the following functions. 424 • Master/slave transmit/receive • Arbitration function • Clock synchronization function • Slave address/general call address detection function • Transfer direction detection function • Repeated issuance of start conditions and start condition detection function • Bus error detection function CHAPTER 22 I2C INTERFACE ■ Block diagram of the I2C interface Figure 22.1-1 "Block Diagram of I2C Interface" shows a block diagram of the I2C interface. Figure 22.1-1 Block Diagram of I2C Interface F2MC-16X bus ICCR EN I2C enable ICCR Clock divider 1 5 6 7 8 CS4 Peripheral clock Clock selector 1 CS3 Clock divider 2 2 4 8 16 32 64 128 256 CS2 CS1 CS0 Sync Clock selector 2 Shift clock edge change timing IBSR BB RSC LRB Shift clock generator Bus busy Repeat start Last Bit Start/stop condition detection Transmit/ receive TRX Error First Byte FBT Arbitration lost detection AL IBCR SCL BER BEIE Interrupt request INTE IRQ SDA INT IBCR SCC MSS ACK GCAA End Start Master ACK permit Start/stop condition generation GC-ACK permit IDAR IBCR AAS GCA Slave Global call Slave address compare IADR 425 CHAPTER 22 I2C INTERFACE 22.2 I2C Interface Registers This section describes the configuration and functions of the I2C interface registers. ■ List of I2C interface registers ❍ Bus status register (IBSR) Bus status register Address: 000088H 7 6 5 4 3 2 1 0 Bit number BB RSC AL LRB TRX AAS GCA FBT Read/write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (0) (0) 14 13 12 11 10 9 8 IBSR ❍ Bus control register (IBCR) Bus control register Address: 000089H Read/write Initial value 15 BER BEIE SCC MSS ACK GCAA INTE INT Bit number IBCR (R/W)(R/W)(R/W)(R/W)(R/W)(R/W) (R/W)(R/W) (0) (0) (0) (0) (0) (0) (0) (0) 4 3 2 1 0 ❍ Clock control register (ICCR) Clock control register Address: 00008AH 7 6 5 - - EN CS4 CS3 CS2 CS1 CS0 Read/write (-) (-) (R/W) (R/W)(R/W)(R/W)(R/W)(R/W) Initial value (-) (-) (0) (X) (X) (X) (X) (X) Bit number ICCR ❍ Address register (IADR) Address register Address: 00008BH 15 14 13 12 11 10 9 8 - A6 A5 A4 A3 A2 A1 A0 Read/write (-) (R/W)(R/W) (R/W)(R/W)(R/W)(R/W)(R/W) Initial value (-) (X) (X) (X) (X) (X) (X) (X) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit number IADR ❍ Data register (IDAR) Data register Address: 00008CH Read/write Initial value 426 (R/W)(R/W)(R/W) (R/W)(R/W)(R/W)(R/W)(R/W) (X) (X) (X) (X) (X) (X) (X) (X) Bit number IDAR CHAPTER 22 I2C INTERFACE 22.2.1 Bus Status Register (IBSR) This section describes the configuration and functions of the bus status register (IBSR). ■ Bus status register (IBSR) The diagram below shows the bit configuration of the bus status register (IBSR). Bus status register Address: 000088H 7 6 5 4 3 2 1 0 BB RSC AL LRB TRX AAS GCA FBT Read/write (R) (R) (R) (R) (R) (R) (R) (R) Initial value (0) (0) (0) (0) (0) (0) (0) (0) Bit number IBSR The functions of bits in the bus status register (IBSR) are described below. [Bit 7] BB: Bus Busy This bit is used to indicate the I2C bus status. 0 Stop condition is detected 1 Start condition is detected (bus is used) [Bit 6] RSC: Repeated Start Condition This bit is used to detect a repeated start condition. 0 Repeated start condition is not detected 1 Start condition is detected again when bus is used. This bit is cleared by setting the INT bit to "0" for addressing in a mode other than slave mode if a start condition is detected in bus idle state or if a stop condition is detected. [Bit 5] AL: Arbitration Lost This bit is used to detect the arbitration lost state. 0 Arbitration lost is not detected. 1 Arbitration lost is generated in master transfer mode, or the MSS bit is set to "1" while another system is using the bus. Cleared if the INT bit is set to "0". [Bit 4] LRB: Last Received bit This bit is an acknowledge storage bit used to store an acknowledgement from the reception side. This bit is cleared if a start or stop condition is detected. 427 CHAPTER 22 I2C INTERFACE [Bit 3] TRX: Transfer/Receive This bit is used to indicate transmission or reception for data transfer. 0 Reception 1 Transmission [Bit 2] AAS: Addressed As Slave This bit is used to detect the addressing mode. 0 Addressing was performed in a mode other than slave mode. 1 Addressing was performed in slave mode. This bit is cleared if a start or stop condition is detected. [Bit 1] GCA: General Call Address This bit is used to detect the general call address (00H). 0 No general call address is received in slave mode. 1 A general call address is received in slave mode. This bit is cleared if a start or stop condition is detected. [Bit 0] FBT: First Byte Transfer This bit is used to detect the first byte. 0 The data received is not byte one. 1 The data received is byte one (address data). This bit is cleared if the INT bit is set to "0" or addressing was performed in a mode other than slave mode, even though the bit was set to "1" because of detection of a start condition. 428 CHAPTER 22 I2C INTERFACE 22.2.2 Bus Control Register (IBCR) This section describes the configuration and functions of the bus control register (IBCR). ■ Bus control register (IBCR) The diagram below shows the bit configuration of the bus control register (IBCR). Bus control register Address: 000089H Read/write 15 14 13 12 11 10 9 8 BER BEIE SCC MSS ACK GCAA INTE INT Bit number IBCR (R/W)(R/W)(R/W)(R/W)(R/W)(R/W) (R/W)(R/W) Initial value (0) (0) (0) (0) (0) (0) (0) (0) The functions of bits in the bus control register (IBCR) are as follows. [Bit 15] BER: Bus ERror This bit is a bus error interrupt request flag. The function of this flag in write and read operations is different. (During writing) 0 Bus error interrupt request flag is cleared. 1 Not applicable (During reading) 0 No bus error was detected. 1 An illegal start or stop condition was detected in data transfer mode. If this bit is set, the EN bit of the ICCR register is cleared and the I2C interface enters the stop state with the data transfer interrupted. [Bit 14] BEIE: Bus Error Interrupt Enable This bit is used to enable bus error interrupts. 0 Bus error interrupts prohibited 1 Bus error interrupts allowed If, with this bit set to "1", the BER bit is set to "1", an interrupt is generated. 429 CHAPTER 22 I2C INTERFACE [Bit 13] SCC: Start Condition Continue This bit is used to generate a start condition. 0 Not applicable 1 Start condition is generated again in master transfer mode. Read operations always return "0" for this bit. [Bit 12] MSS: Master Slave Select This bit is used to select between master mode and slave mode. 0 After the stop condition is generated and transferred, the device enters slave mode. 1 The device enters master mode, the start condition is generated, and transfer starts. This bit is cleared if arbitration lost is detected in master transfer mode. The device then enters slave mode. [Bit 11] ACK: ACKnowledge This bit is used to allow ACK generation when data is received. 0 No Acknowledge generated. 1 Acknowledge generated. This bit is invalid if address data is received in slave mode. [Bit 10] GCAA: General Call Address Acknowledge This bit is used to enable Acknowledge generation when a general call address is received. 0 No Acknowledge generated. 1 Acknowledge generated. [Bit 9] INTE: INTerrupt Enable This bit is used to enable interrupts. 0 Interrupts prohibited 1 Interrupts allowed If this bit is set to "1" when the INT bit is set to "1", an interrupt is generated. 430 CHAPTER 22 I2C INTERFACE [Bit 8] INT: INTerrupt This bit is used as a transfer end interrupt request flag. (During writing) 0 Clears the transfer end interrupt request flag 1 Not applicable (During reading) 0 Transfer has not ended 1 This bit is set if the following conditions are met when one byte including an acknowledge bit is transferred: • Byte transferred in bus master transfer • Byte transferred in slave mode with addressing • General call address is received • Arbitration lost occurs • Attempt to generate a start condition while other systems use the bus. If this bit is "1", the SCL line is kept at the "L" level. This bit is cleared by writing "0" before the SCL line is opened for transfer of the next byte. Alternatively, this bit is reset to "0" if, in master mode, a start or stop condition is generated. ■ Notes on using the bus control register (IBCR) The following precautions relate to conflicts among the SCC, MSS, and INT bits. Writing to the SCC, MSS, and INT bits at the same time will cause a conflict between transfer of the next byte and generation of start or stop conditions. In this case, the priority is specified as follows. ❍ Next byte transfer and stop condition generation If the INT and MSS bits are set to "0", setting of the MSS bit to "0" has priority and the stop condition is generated. ❍ Next byte transfer and start condition generation If the INT bit is set to "0" and the SCC bit is set to "1", setting of the SCC bit to "1" has priority and the start condition is generated. ❍ Start condition generation and stop condition generation Setting the SCC bit to "1" and the MSS bit to "0" at the same time is prohibited. 431 CHAPTER 22 I2C INTERFACE 22.2.3 Clock Control Register (ICCR) This section describes the configuration and functions of the clock control register (ICCR). ■ Clock control register (ICCR) The diagram below shows the bit configuration of the clock control register (ICCR). Clock control register Address: 00008AH 7 6 5 - - EN 4 3 2 1 0 CS4 CS3 CS2 CS1 CS0 Read/write (-) (-) (R/W) (R/W)(R/W)(R/W)(R/W)(R/W) Initial value (-) (-) (0) (X) (X) (X) (X) Bit number ICCR (X) The functions of the clock control register (ICCR) are as follows. [Bits 7, 6] Unused These bits are unused. [Bit 5] EN: ENable This bit is used to enable I2C interface operation. 0 Operation disabled 1 Operation enabled • When this bit is set to "0", each bit of the BSR register and the BCR register (except for the BER and BEIE bits) is cleared. • Setting the BER bit clears this bit. [Bits 4 to 0] CS4-0: Clock Period Select 4-0 These bits are used to set the frequency of the serial clock. The shift clock frequency fsck is set in this register according to the following formula. fsck = φ m×n+4 φ: Machine clock Note: The "+ 4" term in the formula reflects the minimum overhead for checking whether the output level of the SCL pin has changed. If the rising edge of the SCL pin is delayed or a slave device delays the clock, the overhead increases. Do not set the serial clock frequency to 100 kHz or more. The values for m and n must be as shown in Table 22.2-1 "Serial clock frequency settings" for CS4-0. 432 CHAPTER 22 I2C INTERFACE Table 22.2-1 Serial clock frequency settings m CS4 CS3 n CS2 CS1 CS0 5 0 0 4 0 0 0 6 0 1 8 0 0 1 7 1 0 16 0 1 0 8 1 1 32 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 433 CHAPTER 22 I2C INTERFACE 22.2.4 Address Register (IADR) This section describes the configuration and functions of the address register (IADR). ■ Address register (IADR) The diagram below shows the bit configuration of the address register (IADR). Address register Address: 00008BH 15 14 13 12 11 10 9 8 - A6 A5 A4 A3 A2 A1 A0 Read/write (-) (R/W)(R/W) (R/W)(R/W)(R/W)(R/W)(R/W) Initial value (-) (X) (X) (X) (X) (X) (X) Bit number IADR (X) [Bit 14 to 8] A6 to A0 These bits are used as a register to specify the slave address. In slave mode, received address data is compared with the data in the DAR register. If the data matches, the device transmits an acknowledge signal to the master. 434 CHAPTER 22 I2C INTERFACE 22.2.5 Data Register (IDAR) This section describes the configuration and functions of the data register (IDAR). ■ Data register (IDAR) The diagram below shows the bit configuration of the data register (IDAR). Data register Address: 00008CH Read/write Initial value 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Bit number IDAR (R/W)(R/W)(R/W) (R/W)(R/W)(R/W)(R/W)(R/W) (X) (X) (X) (X) (X) (X) (X) (X) [Bit 7] D7 to D0 These bits are used as data bits. These bits constitute a data register for serial transfer starting with the MSB. If data is received (TRX = 0), the data output value becomes "1". With respect to writing, this register consists of a double buffer. If the bus is active (BB = 1), write data is loaded separately for each byte transfer operation into the register for serial transfer. When the register is directly read for serial transfer, note that the receive data is only valid if the INT bit is set. 435 CHAPTER 22 I2C INTERFACE 22.3 I2C Interface Operation The I2C bus performs communication using two bidirectional bus lines that consist of one serial data line (SDA) and one serial clock line (SCL). The I2C interface has instead two open drain input/output pins (SDA, SCL) that allow hard-wired logic to be used. ■ Start condition If the bus is open (BB = 0, MSS = 0) and the MSS bit is set to "1", the I2C interface enters master mode and the start condition is generated as well. Even if the bus is active (BB = 1) in master mode, the start condition will be generated again if the SCC bit is set to "1". There are two ways to generate the start condition: • In the state where the bus is not used (MSS = 0 * BB = 0 * INT = 0 * AL = 0), setting of the MSS bit to "1" • In interrupt state and bus master mode (MSS = 1 * BB = 1 * INT = 1 * AL = 0), setting of the SCC bit to "1" If the MSS bit is set to "1" when the system uses the bus (in idle state), the AL bit is set to "1". In states other than the above, setting the MSS bit and SCC bit to "1" is ignored. ■ Stop condition If the MSS bit is set to "0" in master mode (MSS = 1), a stop condition is generated and the devices enter slave mode. A stop condition is generated when the following conditions exist: • MSS is set to "0" if the MSS bit is set to "0" in bus master mode and in interrupt state (MSS = 1 * BB = 1 * INT = 1 * AL = 0). In the other modes, setting the MSS bit to "0" is ignored. ■ Addressing If, in master mode, a start condition is generated by setting BB = 1 and TRX = 1, the contents of the IDAR register are output starting with the MSB. When, after the address data has been transmitted, Acknowledge is received from the slave, the TRX bit is set to the opposite value of bit 0 of the transmitted data (IDAR register: bit 0 after transmission). In slave mode, after a start condition is generated by setting BB = 1 and TRX = 0, transmitted data from the master is received in the IDAR register. After the address data has been received, the IDAR register and IADR register are compared. If the contents of these registers match, AAS is set to "1", and Acknowledge is transmitted to the master. Next, the TRX bit is set to the same value as bit 0 of the received data (IDAR register: bit 0 after reception). ■ Arbitration If, when a master transmits, another master transmits data at the same time, arbitration occurs. If the signal of the locally transmitted data represents "1" and the data on the SDA line is represented by the "L" level, AL is set to "1" on the assumption that local arbitration is lost. As previously described, AL is set to "1" when a start generation occurs, even though the bus is active at the time. Setting AL to "1" results in MSS = 0 and TRX = 0, and the device enters slave reception mode. 436 CHAPTER 22 I2C INTERFACE ■ Acknowledge Acknowledge is transmitted from the receiving side to the transmitting side. The ACK bit is used to represent an Acknowledge upon data reception. If data is transmitted, an Acknowledge from the receive side is stored in the LRB bit. If no Acknowledge is received from the master side (receiving device) after reception from the slave (transmitting side), the TRX bit is set to "0" and the device enters slave reception state. The master device will in this case generate a stop condition when the slave opens the SCL line. ■ Bus error If the following conditions are satisfied, it can be assumed that a bus error occurred, and the I2C interface will enter stop mode. • If an I2C bus basic standard violation is detected in data transfer mode (when an Ack bit is included). • If a stop condition is detected in master mode • If an I2C bus basic standard violation is detected in bus idle mode. ■ Other considerations ❍ Processing after arbitration lost is detected When arbitration lost is detected, the software has to determine whether local addressing was applied. If arbitration lost occurs, the device enters slave mode on the hardware level, and after 1-byte transfer has been completed, both the CLK line and DATA line are set to "L" level. Consequently, without proper addressing, both the CLK line and DATA line will be immediately opened. With addressing, slave transmission or slave reception will have been set up before the CLK line and DATA line are opened (all of these preparations must be performed by software) ❍ Interrupt sources when arbitration lost is detected If arbitration lost is detected, an interrupt source is not generated immediately, but only after the transfer of one byte is completed. If arbitration lost is detected, the device enters slave mode on the hardware level. Even if this occurs in slave mode, a total of nine clocks will be output before the interrupt source is generated. Since interrupt sources are not generated immediately, no processing is performed after arbitration lost occurs. 437 CHAPTER 22 I2C INTERFACE ❍ Interrupt conditions There is only one interrupt that can be generated related to the I2C bus. The interrupt source is generated either after the end of the transfer of one byte, or because another predefined interrupt condition was met. Since there is only one interrupt, which of multiple interrupt conditions responsible for the interrupt must be identified by checking flags in the interrupt routine. Possible interrupt conditions after transfer of one byte has been performed are listed below. • Interrupt in bus master mode • Interrupt during slave mode with addressing • Interrupt after a general call address is received • "Arbitration lost" occurred ❍ Transfer speed Note that the maximum transfer speed of the I2C bus is 100 kHz (the frequency of the serial clock). 438 CHAPTER 23 CHIP SELECTION FACILITY This chapter provides an overview of the chip selection facility and its operation, and explains the configuration and functions of its registers. 23.1 "Overview of Chip Selection Facility" 23.2 "Registers of Chip Selection Facility" 23.3 "Operation of the Chip Selection Facility" 439 CHAPTER 23 CHIP SELECTION FACILITY 23.1 Overview of Chip Selection Facility The chip selection facility is a module used to generate a chip selection signal for simplified external connection of memory. It contains four chip selection output pins. The chip selection facility enables a memory area within the hardware to be specified via an output setting register, and if the device detects an access to that external address, it outputs a selection signal via the corresponding pin. ■ Features of the chip selection facility The chip selection facility contains two 8-bit registers for each output pin. One register (CARx) is used to specify the upper 8 bits of the corresponding detection address, allowing addresses within 64 KB to be specified. Another register (CMRx) is used to mask the corresponding bits of the address so that values above 64 KB can be specified for the area to be detected. In external bus hold mode, CS output is set to high impedance mode. ■ Block diagram of the chip selection facility Figure 23.1-1 "Block diagram of the chip selection facility" shows a block diagram of the chip selection facility. F2MC-16LX bus Figure 23.1-1 Block diagram of the chip selection facility CMRx CARx Chip selection pin output A23-16 440 CHAPTER 23 CHIP SELECTION FACILITY 23.2 Registers of Chip Selection Facility This section describes the configuration and functions of the registers used by the chip selection facility. ■ List of registers used for the chip selection facility Figure 23.2-1 "List of registers for the chip selection facility" lists the registers for the chip selection facility. Figure 23.2-1 List of registers for the chip selection facility 8 15 7 0 (R/W) CAR0 CMR0 (R/W) CAR1 CMR1 (R/W) CAR2 CMR2 (R/W) CAR3 CMR3 (R/W) CALR CSCR (R/W) 0000C0H 7 6 5 4 3 2 1 0 0000C2H M7 M6 M5 M4 M3 M2 M1 M0 CMRx Chip selection area MASK register 0000C4H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write 0000C6H Initial value (0) (0) (0) (0) (1) (1) (1) (1) 0000C1H 15 14 13 12 11 10 9 8 0000C3H A7 A6 A5 A4 A3 A2 A1 A0 0000C5H (R/W) (R/W) (R/W) (R/W) (R/W) (W) 0000C7H 0000C8H 0000C9H (R/W) (R/W) (1) (1) (1) (1) (1) (1) (1) (1) 7 6 5 4 3 2 1 0 CARx Chip selection area register Read/write Initial value CSCR - - - - OPL3 OPL2 OPL1 OPL0 Chip selection control register (-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W) Read/write (-) (-) (-) (-) 15 14 13 12 - - - - ACTL3 ACTL2 ACTL1 ACTL0 (-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W) (-) (-) (-) (-) (0) (0) (0) (*) 11 10 9 8 (0) (0) (0) (0) Initial value CALR Chip selection active level register Read/write Initial value 441 CHAPTER 23 CHIP SELECTION FACILITY 23.2.1 Chip Select Area MASK Register (CMRx) This section describes the configuration and functions of the chip selection area MASK register (CMRx). ■ Chip selection area MASK register (CMRx) The diagram below shows the bit configuration of the chip selection area MASK register (CMRx). 0000C0H 7 6 5 4 3 2 1 0 0000C2H M7 M6 M5 M4 M3 M2 M1 M0 CMRx Chip selection area MASK register 0000C4H (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) (R/W) Read/write 0000C6H Initial value (0) (0) (0) (0) (1) (1) (1) (1) [bit7-0]M7-M0 [Bit 7-0] M7-M0 These bits are used to specify an address decode area for the chip selection pin. Set the corresponding bit to "1" for masking. These bits are used to specify an area of 128 KB or more. Note: If all bits are masked, no external access is activated. 442 CHAPTER 23 CHIP SELECTION FACILITY 23.2.2 Chip Selection Area Register (CARx) This section describes the configuration and functions of the chip selection area register (CARx). ■ Chip selection area register (CARx) The diagram below shows the bit configuration of the chip selection area register (CARx). 0000C1H 15 14 13 12 11 10 9 8 0000C3H A7 A6 A5 A4 A3 A2 A1 A0 0000C5H (R/W) (R/W) (R/W) (R/W) (R/W) (W) 0000C7H (1) (1) (1) (1) (1) (1) (R/W) (R/W) (1) (1) CARx Chip select control register Read/write Initial value [bit7-0]A7-A0 [Bit 7-0] A7-A0 These bits are used to set the address decode area for the chip select pin. They specify the upper 8 bits of the address value, allowing an address within 64 KB to be specified. Note: The chip selection facility is not active for internal accesses such as access to built-in RAM, built-in ROM, and built-in I/O area. 443 CHAPTER 23 CHIP SELECTION FACILITY 23.2.3 Chip Selection Control Register (CSCR) This section describes the configuration and functions of the chip selection control register (CSCR). ■ Chip selection control register (CSCR) The diagram below shows the bit configuration of the chip selection control register (CSCR). 0000C8H 7 6 5 4 - - - - OPL3 OPL2 OPL1 OPL0 3 Chip selection control register (-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W) Read/write (-) (-) (-) (-) (0) 2 (0) 1 (0) 0 (*) CSCR Initial value [Bit 7-4] Unused bits These bits are unused. In read operations, the return value for these bits is undefined. [Bit 3-0] OPL3-0 These bits are used to specify whether CS3-0 are output to the external pin. The operational settings are as follows: • "0": Decode output from each CS3-0 pin is prohibited • "1": Decode output from each CS3-0 pin is allowed Note: 444 • The initial value of OPL0 is set to "1" in external vector mode, and set to "0" in internal vector mode. • Enabling or disabling CS3-0 output must be performed after all settings have been made. • Change settings during operation only after prohibiting output. CHAPTER 23 CHIP SELECTION FACILITY 23.2.4 Chip Selector Active Level Register (CALR) This section describes the configuration and functions of the chip selector active level register (CALR). ■ Chip selector active level register (CALR) The diagram below shows the bit configuration of the chip selector active level register (CALR). 0000C9H 15 14 13 12 - - - - ACTL3 ACTL2 ACTL1 ACTL0 11 Chip selector active level register (-) (-) (-) (-) (R/W) (R/W) (R/W) (R/W) Read/write (-) (-) (-) (-) (0) 10 (0) 9 (0) 8 (0) CALR Initial value [Bit 15-12] Unused bits These bits are unused. In read operations, the return value for these bits is undefined. [Bit 11-8] ACTL3-0 These bits are used to set the active level of each CS3-0 pin. The operational settings are as follows. • "0": Each CS3-0 pin outputs "L" after decoding. • "1": Each CS3-0 pin outputs "H" after decoding. Note: • Before changing the active level, prohibit output via the chip selection control register. • Writing these bits in units of words is prohibited. Always write these bits in units of bytes. This will prevent the enabling of output at the same time that the active level is changed. 445 CHAPTER 23 CHIP SELECTION FACILITY 23.3 Operation of the Chip Selection Facility This section describes the operations of the chip selection facility. ■ Outline of operations When the CPU accesses program or data, the chip selection facility is activated if a match between the upper 8 bits of an address and CAR0/1/2/3 is detected. Addresses for which the corresponding bits in CSM0/1/2/3 are set to "1" are ignored, and decoding becomes possible for an area from 64 KB to 16 MB. During internal accesses (access to the I/O area, the built-in RAM, or the built-in ROM), the chip selection facility is not active. ■ Example of using the chip selection facility Figure 23.3-1 "Example of using the chip selection facility" shows an example of using the chip selection facility. Figure 23.3-1 Example of using the chip selection facility [Example 1] Address 11111110 CMR0 Matching 00000000 CAR0 11111110 XXXXXXXX XXXXXXXX FEXXXXXXH CS0 active [Example 2] 446 Address 11111110 CMR0 Matching 00001111 CAR0 11111010 XXXXXXXX XXXXXXXX FEXXXXXXH CS0 active CHAPTER 23 CHIP SELECTION FACILITY ■ Notes on using the chip selection facility • The CS0 pin always becomes active if used in external vector mode. In the address space F00000 to FFFFFF (1 MB), which is the initial value, always use this pin only for accesses to program ROM, since the corresponding decode signal will be output immediately after a reset. In this case, the active level of the CS0 pin is set to "L", and "H" is output at reset. In internal vector mode, this pin, like the CS3-1 pins, is used as a general-purpose port. Therefore, switch to the output state after the corresponding settings have been made. • Only enable output after the settings of the chip selection area register, mask register, and active level register have been made. • Note that, since the chip selection output is shared with pins P90 to P93, chip selection output will not be available while the resource assigned to this pin is in use. • If the pin is set to the hold state when the external bus is used, output is disabled and the pin is set to high impedance mode. In these cases, always set the shared general-purpose port to act as an input. • In sleep or stop mode, the chip selection facility is not active. Note that it cannot be used by the built-in DMA at these times. 447 CHAPTER 23 CHIP SELECTION FACILITY 448 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION This chapter explains the address match detection function and its operation. 24.1 "Overview of Address Match Detection Function" 24.2 "Block Diagram of Address Match Detection Function" 24.3 "Configuration of Address Match Detection Function" 24.4 "Explanation of Operation of Address Match Detection Function" 24.5 "Program Example of Address Match Detection Function" 449 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.1 Overview of Address Match Detection Function If the address of the instruction to be processed next to the instruction currently processed by the program matches the address set in the detect address setting registers, the address match detection function forcibly replaces the next instruction to be processed by the program with the INT9 instruction to branch to the interrupt processing program. Since the address match detection function can use the INT9 interrupt for instruction processing, the program can be corrected by patch processing. ■ Overview of Address Match Detection Function • The address of the instruction to be processed next to the instruction currently processed by the program is always held in the address latch through the internal bus. The address match detection function always compares the value of the address held in the address latch with that of the address set in the detect address setting registers. When these compared values match, the next instruction to be processed by the CPU is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed. • There are two detect address setting registers (PADR0 and PADR1), each of which has an interrupt enable bit. The generation of an interrupt due to a match between the address held in the address latch and the address set in the detect address setting registers can be enabled and disabled for each register. 450 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.2 Block Diagram of Address Match Detection Function The address match detection module consists of the following blocks: • Address latch • Address detection control register (PACSR) • Detect address setting registers (RADR) ■ Block Diagram of Address Match Detection Function Figure 24.2-1 "Block Diagram of the Address Match Detection Function" shows the block diagram of the address match detection function. Figure 24.2-1 Block Diagram of the Address Match Detection Function PADR0 (24bit) Detect address setting register 0 PADR1 (24bit) Comparator Internal data bus Address latch INT9 instruction (INT9 interrupt generation) Detect address setting register 1 PACSR Reserved Reserved Reserved Reserved AD1E Reserved AD0E Reserved Address detection control register (PACSR) Reserved: Always set to "0" ❍ Address latch The address latch stores the value of the address output to the internal data bus. ❍ Address detection control register (PACSR) The address detection control register enables or disables output of an interrupt at an address match. ❍ Detect address setting registers (PADR0, PADR1) The detect address setting registers set the address that is compared with the value of the address latch. Notes: The addresses of the detect address setting register are 1FF0H to 1FF5H and are included in the RAM area. Therefore, the access to the RAM area should not be performed during the use of this function. 451 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3 Configuration of Address Match Detection Function This section details the registers used by the address match detection function. ■ List of Registers and Reset Values of Address Match Detection Function Figure 24.3-1 List of Registers and Reset Values of Address Match Detection Function bit Address detection control register (PACSR) bit Detect address setting register 0 (PADR0) : High bit Detect address setting register 0 (PADR0) : Middle bit Detect address setting register 0 (PADR0) : Low bit Detect address setting register 1 (PADR1) : High bit Detect address setting register 1 (PADR1) : Middle bit Detect address setting register 1 (PADR1) : Low ×: Undefined 452 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 × × × × × × × × 15 14 13 12 11 10 9 8 × × × × × × × × 7 6 5 4 3 2 1 0 × × × × × × × × 7 6 5 4 3 2 1 0 × × × × × × × × 15 14 13 12 11 10 9 8 × × × × × × × × 7 6 5 4 3 2 1 0 × × × × × × × × CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3.1 Address Detection Control Register (PACSR) The address detection control register (PACSR) enables or disables output of an interrupt at an address match. When an address match is detected when output of an interrupt at an address match is enabled, the INT9 interrupt is generated. ■ Address Detection Control Register (PACSR) Figure 24.3-2 Address Detection Control Register (PACSR) 7 6 5 4 3 2 1 0 Reset value 00000000 B Address 009EH R/W R/W R/W R/W R/W R/W R/W R/W bit 0 Reserved bit Reserved 0 Always set to "0" bit 1 Address match detection enable bit 0 AD0E 0 Disables address match detection in PADR0 1 Enables address match detection in PADR0 bit 2 Reserved bit Reserved 0 Always set to "0" bit 3 Address match detection enable bit 1 AD1E 0 Disables address match detection in PADR1 1 Enables address match detection in PADR1 bit 4 Reserved bit Reserved 0 Always set to "0" bit 5 Reserved bit Reserved 0 Always set to "0" bit 6 Reserved bit Reserved 0 Always set to "0" bit 7 Reserved bit Reserved R/W : Read/Write : Reset value 0 Always set to "0" 453 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION Table 24.3-1 Functions of Address Detection Control Register (PACSR) Bit Name 454 Function bit 0 reserved: reserved bit Always set to 0. bit 1 AD0E: Address match detection enable bit 0 The address match detection operation with the detect address setting register 0 (PADR1) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting register 0 (PADR0) matches with the value of address latch at enabling the address match detect operation (AD0E = 1), the INT9 instruction is immediately executed. bit 2 reserved: reserved bit Always set to 0. bit 3 AD1E: Address match detection enable bit 1 The address match detection operation with the detect address setting register 1 (PADR1) is enabled or disabled. When set to 0: Disables the address match detection operation. When set to 1: Enables the address match detection operation. • When the value of detect address setting registers 1 (PADR1) matches with the value of address latch at enabling the address match detection operation (AD0E = 1), the INT9 instruction is immediately executed. bit 4 to bit 7 reserved: reserved bit Always set to 0. CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.3.2 Detect Address Setting Registers (PADR0H and PADR1) The value of an address to be detected is set in the detect address setting registers. When the address of the instruction processed by the program matches the address set in the detect address setting registers, the next instruction is forcibly replaced by the INT9 instruction, and the interrupt processing program is executed. ■ Detect Address Setting Registers Figure 24.3-3 Detect Address Setting Registers (PADR0 and PADR1) PADR0, PADR1: High Address 1FF2H, 1FF5H bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Reset value D23 D22 D20 D19 D18 XXXXXXXX B D21 D17 D16 R/W R/W R/W R/W R/W R/W R/W R/W bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 PADR0, PADR1: Middle Address 1FF1H, 1FF4H D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 PADR0, PADR1: Low Address 1FF0H, 1FF3H Reset value XXXXXXXX B D7 D6 D5 D4 D3 D2 D1 D0 Reset value XXXXXXXX B R/W R/W R/W R/W R/W R/W R/W R/W R/W : Read/Write X : Undefined 455 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION ■ Functions of Detect Address Setting Registers • There are two detect address setting registers (PADR0 and PADR1) that consist of a high byte (bank), middle byte, and low byte, totaling 24 bits. Table 24.3-2 Address Setting of Detect Address Setting Registers Register Name Detect address setting register 0 (PADR0) Detect address setting register 1 (PADR1) Interrupt Output Enable Address Setting High PACSR: AD0E PACSR: AD1E Set the upper 8 bits of detect address 0 (bank). Middle Set the middle 8 bits of detect address 0. Low Set the lower 8 bits of detect address 0. High Set the upper 8 bits of detect address 1 (bank). Middle Set the middle 8 bits of detect address 1. Low Set the lower 8 bits of detect address 1. • In the detect address setting registers (PADR0 and PADR1), starting address (first byte) of instruction to be replaced by INT9 instruction should be set. Figure 24.3-4 Setting of Starting Address of Instruction Code to be Replaced by INT9 Set to detect address (High : FFH, Middle : 00H, Low : 1FH) Notes: 456 Address Instruction code FF001C : FF001F : FF0022 : A8 00 00 4A 00 00 4A 80 08 Mnemonic MOVW MOVW MOVW RW0, #0000 A, #0000 A,#0880 • When an address of other than the first byte is set to the detect address setting register (PADR0 and PADR1), the instruction code is not replaced by INT9 instruction and a program of an interrupt processing is not be performed. When the address is set to the second byte or subsequent, the address set by the instruction code is replaced by "01" (INT9 instruction code) and, which may cause malfunction. • The detect address setting registers (PADR0 and PADR1) should be set after disabling the address match detection (PACSR: AD0E = 0 or AD1E = 0) of corresponding address match control registers. If the detect address setting registers are changed without disabling the address match detection, the address match detection function will work immediately after an address match occurs during writing address, which may cause malfunction. • The address match detection function can be used only for addresses of the internal ROM area. If addresses of the external memory area are set, the address match detection function will not work and the INT9 instruction will not be executed. CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4 Explanation of Operation of Address Match Detection Function If the addresses of the instructions executed in the program match those set in the detection address setting registers (PADR0 and PADR1), the address match detection function will replace the first instruction with the INT9 instruction (01H) to branch to the interrupt processing program. ■ Operation of Address Match Detection Function Figure 24.4-1 "Operation of Address Match Detection Function" shows the operation of the address match detection function when the detect addresses are set and an address match is detected. Figure 24.4-1 Operation of Address Match Detection Function Program execution The instruction address to be executed by program matches detect address setting register 0 Address Instruction code FF001C : FF001F : FF0022 : A8 00 00 4A 00 00 4A 80 08 Mnemonic MOVW MOVW MOVW RW0, #0000 A, #0000 A, #0880 Replaced by INT9 instruction (01H) ■ Setting Detect Address 1. Disable the detection address setting register 0 (PADR0) where the detect address is set for address match detection (PACSR: AD0E = 0). 2. Set the detect address in the detection address setting register 0 (PADR0). Set "FFH" at the higher bits of the detection address setting register 0 (PADR0), "00H" at the middle bits, and "1FH" at the lower bits. 3. Enable the detect address setting register 0 (PADR0) where the detect address is set for address match detection (PACSR: AD0E = 1). ■ Program Execution 1. If the address of the instruction to be executed in the program matches the set detect address, the first instruction code at the matched address is replaced by the INT9 instruction code (01H). 2. INT9 instruction is executed. INT9 interrupt is generated and then interrupt processing program is executed. 457 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.4.1 Example of using Address Match Detection Function This section gives an example of patch processing for program correction using the address match detection function. ■ System Configuration and E2PROM Memory Map ❍ System configuration Figure 24.4-2 "Example of System Configuration using Address Match Detection Function" gives an example of the system configuration using the address match detection function. Figure 24.4-2 Example of System Configuration using Address Match Detection Function Serial E2PROM Interface MCU F2MC16LX E2PROM Storing patch program Pull up resistor SIN Connector (UART) Storing patch program from the outside 458 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION ■ E2PROM Memory Map Figure 24.4-3 "Allocation of E2PROM Patch Program and Data" shows the allocation of the patch program and data at storing the patch program in E2PROM. Figure 24.4-3 Allocation of E2PROM Patch Program and Data E2PROM Address PADR0 PADR1 0000H Patch program byte count 0001H Detect address 0 (Low) 0002H Detect address 0 (Middle) 0003H Detect address 0 (High) 0004H Patch program byte count 0005H Detect address 1 (Low) 0006H Detect address 1 (Middle) 0007H Detect address 1 (High) 0010H Patch program 0 (main body) 0020H Patch program 1 (main body) For patch program 0 For patch program 1 ❍ Patch program byte count The total byte count of the patch program (main body) is stored. If the byte count is "00H", it indicates that no patch program is provided. ❍ Detect address (24 bits) The address where the instruction code is replaced by the INT9 instruction code due to program error is stored. This address is set in the detection address setting registers (PADR0 and PADR1). ❍ Patch program (main body) The program executed by the INT9 interrupt processing when the program address matches the detect address is stored. Patch program 0 is allocated from any predetermined address. Patch program 1 is allocated from the address indicating <starting address of patch program 0 + total byte count of patch program 0>. 459 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION ■ Setting and Operating State ❍ Initialization • E2PROM data are all cleared to "00H". ❍ Occurrence of program error • By using the connector (UART), information about the patch program is transmitted to the MCU (F2MC-16LX) from the outside according to the allocation of the E2PROM patch program and data. • The MCU (F2MC-16LX) stores the information received from outside in the E2PROM. ❍ Reset sequence • After reset, the MCU (F2MC-16LX) reads the byte count of the E2PROM patch program to check the presence or absence of the correction program. • If the byte count of the patch program is not "00H", the higher, middle and lower bits at detect addresses 0 and 1 are read and set in the detection address setting registers 0 and 1 (PADR0 and PADR1). The patch program (main body) is read according to the byte count of the patch program and written to RAM in the MCU (F2MC-16LX). • he patch program (main body) is allocated to the address where the patch program is executed in the INT9 interrupt processing by the address match detection function. • Address match detection is enabled (PACSR: AD0E = 1, AD1E = 1) ❍ INT9 Interrupt processing • Interrupt processing is performed by the INT9 instruction. The MB90470 series has no interrupt request flag by address match detection. Therefore, if the stack information in the program counter is discarded, the detect address cannot be checked. When checking the detect address, check the value of program counter stacked in the interrupt processing routine. • The patch program is executed, branching to the normal program. 460 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION ■ Operation of Address Match Detection Function at Storing Patch Program in E2PROM Figure 24.4-4 "Operation of Address Match Detection Function at Storing Patch Program in E2ROM" shows the operation of the address match detection function at storing the patch program in E2PROM. Figure 24.4-4 Operation of Address Match Detection Function at Storing Patch Program in E2ROM 000000 H (3) Patch program RAM Detection address setting register E2PROM (1) Detection address setting (reset sequence) Serial E2PROM interface . Patch program byte count . Address for address detection . Patch program ROM (2) (4) Program error FFFFFF H (1) Execution of detection address setting of reset sequence and normal program (2) Branch to patch program which expanded in RAM with INT9 interrupt processing by address match detection (3) Patch program execution by branching of INT9 processing (4) Execution of nomal program which branches from patch program 461 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION ■ Flow of Patch Processing Figure 24.4-5 "Flow of Patch Processing" shows the flow of patch processing using the address match detection function. Figure 24.4-5 Flow of Patch Processing E2PROM MB90470 I/O area 000000H 000100H Register/RAM area 000400H Patch program 000480H RAM area RAM Stack area 0000 H Patch program byte count : 80H 0001 H Detect address (Low) : 00H 0002 H Detect address (Middle) : 80H 0003 H Detect address (High) : FFH 0010 H Patch program 000900H Detection address setting register 0090 H FFFFH FF0000H FF8000H ROM Program error FF8050H FFFFFF H YES Reset INT9 Read the 00H of E2PROM Branch to patch program JMP 000400H Execution of patch program 000400H to 000480H E2PROM : 0000H =0 NO End of patch program JMP FF8050H Read detect address E2PROM : 0001H to 0003H ↓ MCU : Set to PADR0 Read patch program E2PROM : 0010H to 008FH ↓ MCU : 000400H to 00047FH Enable address match detection (PACSR : AD0E = 1) Execution of normal program NO 462 Program address = PADR0 YES INT9 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 24.5 Program Example of Address Match Detection Function This section gives a program example for the address match detection function. ■ Program Example for Address Match Detection Function ❍ Processing specifications If the address of the instruction to be executed by the program matches the address set in the detection address setting register (PADR0), the INT9 instruction is executed. ❍ Coding example PACSR EQU 00009EH ; Address detection control register PADRL EQU 001FF0H ; Detection address setting register 0 (Low) PADRM EQU 001FF1H ; Detection address setting register 0 (Middle) PADRH EQU 001FF2H ; Detection address setting register 0 (High) ; ;-----Main program--------------------------------------------------------------CODE CSEG START: ; Stack pointer (SP), etc., ; already reset MOV PADRL,#00H ; Set address detection register 0 (Low) MOV PADRM,#00H ; Set address detection register 0 (Middle) MOV PADRH,#00H ; Set address detection register 0 (High) ; MOV I:PACSR,#00000010B ; Enable address match : processing by user : LOOP: : processing by user : BAR LOOP ;-----Interrupt program---------------------------------------------------------WARI: : processing by user : BETI ; Return from interrupt processing CODE ENDS ;-----Vector setting------------------------------------------------------------VECT CSEG ABS=0FFH ORG 00FFDCH DSL WARI ORG 00FFDCH ; Set reset vector DSL START DB 00H ; Set to single-chip mode VECT ENDS END START 463 CHAPTER 24 ADDRESS MATCH DETECTION FUNCTION 464 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE This chapter describes the functions of the ROM mirror function selection module. 25.1 "Overview of ROM Mirror Function Selection Module" 25.2 "ROM Mirror Function Select Register (ROMM)" 465 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE 25.1 Overview of ROM Mirror Function Select Module The ROM mirror function selection module is used to select, via register settings, whether the contents of the FF bank ROM can be read from 00 bank. ■ Block diagram of the ROM mirror function selection module Figure 25.1-1 "Block diagram of the ROM mirror function selection module" shows a block diagram of the ROM mirror function selection module. Figure 25.1-1 Block diagram of the ROM mirror function selection module F2MC-16LX bus ROM mirror function selection Address area FF bank 00 bank ROM ■ Registers of the ROM mirror function select module The following diagram shows configuration of the ROM mirror function select module. Bit ROMM address: 00006FH 466 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 MI W Initial value -------1R CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE 25.2 ROM Mirror Function Select Register (ROMM) This section describes the configuration and functions of the ROM mirror function selection register (ROMM). ■ ROMM (ROM mirror function select register) The diagram below shows the bit configuration of the ROM mirror function selection register (ROMM). Bit ROMM address: 00006FH 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 MI W Initial value -------1R [Bit8] MI • If set to "1", ROM data in the FF bank can be read via Bank 00. • If set to "0", reading via Bank 00 is not enabled. • This bit is a write-only bit. Note: • Do not access this register while accesses to address 004000H to 00FFFFH are in progress. • At the start of the ROM mirror function, addresses FF4000H to FFFFFFH are mirrored at the addresses 004000H to 00FFFFH in Bank 00. ROM addresses of FF3FFFH or below are not mirrored in Bank 00 even if the ROM mirror function is enabled. 467 CHAPTER 25 ROM MIRROR FUNCTION SELECTION MODULE 468 CHAPTER 26 2M BIT FLASH MEMORY This chapter describes the functions and operations of the 2M bit flash memory. The following three operations are available for writing data to, or erasing data from, flash memory. • Writing/erasing via the program • Writing via a serial programmer • Using a flash memory programmer This document will explain the operations for writing/erasing via the program and writing via a serial programmer. 26.1 "Overview of 2M Bit Flash Memory" 26.2 "Sector Configuration of 2M Bit Flash Memory" 26.3 "Control Status Register (FMCS)" 26.4 "Method for Starting the Flash Memory's Automatic Algorithm" 26.5 "Verifying the Execution State of the Automatic Algorithm" 26.6 "Flash Memory Write/Erase Operations" 469 CHAPTER 26 2M BIT FLASH MEMORY 26.1 Overview of 2M Bit Flash Memory In the CPU memory map, the 2M bit flash memory is allocated in banks FC-FF, and the operations for using the flash memory interface circuit, read access, and program access from the CPU are provided just as they are for mask ROM. Writing data to flash memory and erasing data from flash memory is enabled with instructions from the CPU via the flash memory interface circuit. Thus, the contents of the flash memory can be rewritten in implementation mode under control from the built-in CPU, enabling the efficient tuning of programs and data. Selector operations, such as enable sector protect, are not available. ■ Features of the 2M bit flash memory The 2M bit flash memory has the following features: • 256K words x 8 bits/128K words x 16 bits (16K + 8K + 8K + 32K + 64K + 64K + 64K) sector configuration • Automatic program algorithm (Embedded Algorithm, which is the same as that for the MBM29F400TA) • Built-in erasure suspend/erasure resume functions • Detection of completion of write/erase operations using data polling and a toggle bit • Detection of completion of write/erase operations using CPU interrupts • Compatibility with JEDEC-standard commands • Sector-level erasure is available (any combination of sectors is allowed) • Minimum write/erase count: up to 10,000 Embedded Algorithm is a trademark of Advanced Micro Devices, Inc. ■ Methods for writing/erasing flash memory Flash memory cannot be written and read at the same time. Write/read operations of programs operating on flash memory must therefore be implemented in the following steps: Data must first be copied to RAM, then the program operates on the RAM data, and finally the result is written back to flash memory. In other words, program execution must be performed without intermediate accesses to flash memory. ■ Flash memory control status register (FMCS) The following diagram shows the bit configuration of the flash memory control status register (FMCS) used by the flash memory. Bit number 7 6 Address: 0000AEH INTE RDYINT Read/write Initial value 470 5 WE (R/W) (R/W) (R/W) (0) (0) (0) 4 3 2 1 0 RDY Reserved LPM1 Reserved LPM0 (W) (W) (R/W) (W) (R/W) (X) (0) (0) (0) (0) CHAPTER 26 2M BIT FLASH MEMORY 26.2 Sector Configuration of 2M Bit Flash Memory This section describes the sector configuration of the 2M bit flash memory. ■ Sector configuration Figure 26.2-1 "Sector Configuration of 2M Bit Flash Memory" shows the sector configuration of the 2M bit flash memory. The figure indicates the upper and lower addresses of each sector. In accesses from the CPU, SA0 is allocated in the FC bank register, SA1 is allocated in the FD bank register, SA2 is allocated in the FE bank register, and SA3-6 are allocated in the FF bank register. Figure 26.2-1 Sector Configuration of 2M Bit Flash Memory Flash memory CPU address FFFFFFH *Programmer address 7FFFFH FFC000H FFBFFFH 7C000H 7BFFFH FFA000H FF9FFFH 7A000H 79FFFH FF8000H FF7FFFH 78000H 77FFFH FF0000H FEFFFFH 70000H 6FFFFH FE0000H FDFFFFH 60000H 5FFFFH FD0000H FCFFFFH 50000H 4FFFFH FC0000H 40000H SA6 (16K bytes) SA5 ( 8K bytes) SA4 ( 8K bytes) SA3 (32K bytes) SA2 (64K bytes) SA1 (64K bytes) SA0 (64K bytes) ❍ Programmer Address The programmer address shown in Figure 26.2-1 "Sector Configuration of 2M Bit Flash Memory" is the address corresponding to the CPU address when data is written to the flash memory with a parallel programmer. When using a general-purpose programmer for write/erase operations, this address is used for write/erase operations. 471 CHAPTER 26 2M BIT FLASH MEMORY 26.3 Control Status Register (FMCS) The control status register (FMCS) is used for write/erase operations on flash memory via the registers in the flash memory interface circuit. ■ Control status register (FMCS) The diagram below shows the bit configuration of the control status register (FMCS). Bit number 7 6 Address: 0000AEH INTE RDYINT Read/write Initial value 5 WE (R/W) (R/W) (R/W) (0) (0) (0) 4 3 2 1 0 RDY Reserved LPM1 Reserved LPM0 (W) (W) (R/W) (W) (R/W) (X) (0) (0) (0) (0) The bits in the control status register (FMCS) have the following functions. [Bit 7] INTE: INTerrupt Enable This bit is used to generate an interrupt to the CPU due to the end of a flash memory write/ erase access. If the INTE bit is set to "1" and the RDYINT bit is set to "1", an interrupt is issued to the CPU. If the INTE bit is set to "0", no interrupt is issued. 0 Interrupt at the end of write/erase operations prohibited 1 Interrupt at the end of write/erase operations allowed [Bit 6] RDYINT: ReaDY INTerrupt This bit is used to indicate the operation state of the flash memory. At the end of a flash memory write/erase operation, this bit is normally set to "1". When this bit remains "0" after the end of a flash memory write/erase operation, further flash memory write/erase operations are not allowed. Only after this bit has been set to "1" at the end of a write/erase operations is the next write/erase operation for flash memory allowed. This bit is cleared by writing "0". Writing "1" has no effect. This bit is set to "1" according to the end timing of the flash memory automatic algorithm (Refer to Section 26.4 "Method for Starting the Flash Memory's Automatic Algorithm"). Read-modify-write (RMW) instructions always return "1" for this bit. 472 0 Write/erase operation in progress 1 End of write/erase operation end (interrupt request generation) CHAPTER 26 2M BIT FLASH MEMORY [Bit 5] WE: Write Enable This bit is a write-enable bit for the flash memory area. If this bit is "1", a command sequence that targets banks FC - FF (refer to Section 26.4 "Method for Starting the Flash Memory's Automatic Algorithm") will result in a write/erase operation in the flash memory area. If this bit is "0", no write/erase signals are generated. This bit is used for initiating write/erase commands with respect to the flash memory. In order to prevent accidental writing of any data to the flash memory, Fujitsu recommends always setting this bit to "0" whenever no write/erase operations are to be executed. 0 Flash memory write/erase prohibited 1 Flash memory write/erase allowed [Bit 4] RDY: ReadDY This bit is used to allow flash memory write/erase operations to be performed. If this bit is "0", write/erase operations with respect to the flash memory are not allowed. However, suspend commands, such as read/reset and sector erase suspend, can be accepted in this state. 0 Write/erase operation in progress 1 End of write/erase operation (next data write/erase operation is enabled) [Bit 3] Reserve bit This bit is reserved. Always set this bit to "0" for ordinary use. [Bit 1] Unused bit This bit is unused. Always set this bit to "0" for ordinary use. [Bit 2, 0] LPM1, LPM0: Low Power Mode These bits are used to reduce flash memory power consumption. If these bits are set to "00", flash memory operations are performed normally. If these bits are set to "01", "10" or "11", however, access to flash memory according to the select signal will be performed in low power consumption mode. In this case, access time increases significantly compared to access with LPM = "00", and memory access will be disabled during high-speed operation of the CPU. To use this mode, use a CPU with a frequency 4 MHz, 8 MHz, or 10 MHz. LPM1 LPM0 Power consumption mode 0 0 Normal power consumption mode 0 1 Power saving mode (operation with an internal operation frequency of 4MHz) 1 0 Power saving mode (operation with an internal operation frequency of 8MHz) 1 1 Power saving mode (operation with an internal operation frequency of 10MHz) Note: • For a CPU operation frequency of 10 MHz or higher, always use normal mode. 473 CHAPTER 26 2M BIT FLASH MEMORY ■ End timing of the automatic algorithm Figure 26.3-1 "Relationship among automatic algorithm end timing, RDYINT bit and RDY bit" shows the relationship among the end timing of the automatic algorithm, the RDYINT bit, and the RDY bit. The RDYINT bit and RDY bit do not change at the same time. Write programs in such a way that one bit or the other will be used for decision. Figure 26.3-1 Relationship among automatic algorithm end timing, RDYINT bit and RDY bit End timing of the automatic algorithm RDYINT bit RDY bit One machine cycle 474 CHAPTER 26 2M BIT FLASH MEMORY 26.4 Method for Starting the Flash Memory's Automatic Algorithm There are four kinds of commands for starting the automatic algorithm for flash memory: read/reset, write, and chip erase. For sector erase operations, control of suspension and resuming is provided. ■ Command sequence table Table 26.4-1 "Command sequence table" lists the commands used for flash memory write/erase operations. Although the data for writing to the command register is indicate in units of bytes, use word access during actual operations. (The contents of the upper byte are ignored in this case). Table 26.4-1 Command sequence table 1st bus write cycle 2nd bus write cycle 3rd bus write cycle 4th bus write cycle 5th bus write cycle 6th bus write cycle Bus write cycle Address Data Address Data Address Data Address Data Address Data Address Data Read/reset (*1) 1 FxXXXX XXF0 - - - - - - - - - - Read/reset (*1) 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXF0 RA RD - - - - Write program 4 FxAAAA XXAA Fx5554 XX55 FxAAAA XXA0 PA (even) PD (word) - - - - Chip erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 FxAAAA XX10 Sector erase 6 FxAAAA XXAA Fx5554 XX55 FxAAAA XX80 FxAAAA XXAA Fx5554 XX55 SA (even) XX30 Command sequence Sector erase suspend Entering xxB0H at address "FxXXXX" will suspend a erasure in sector erase mode. Sector erase resume Entering xx30H at address "FxXXXX" will resume erasure in sector erase suspend mode. Note1: The address Fx in the table represents FF, FE, FD or FC. Specify the actual value corresponding to the bank to be accessed in each operation. Note2: The address in the table indicates the value in the CPU memory map. Addresses and data are indicated in hexadecimal representation; "X" indicates an arbitrary value. RA: Read address PA: Write address. Only even addresses can be specified. SA: Sector address (Refer to Section 26.2 "Sector Configuration of 2M Bit Flash Memory") RD: Read data PD: Write data; only words can be specified *1: Both read and reset commands allow the flash memory to be reset to read mode. 475 CHAPTER 26 2M BIT FLASH MEMORY 26.5 Verifying the Execution State of the Automatic Algorithm The flash memory contains dedicated hardware indicating the internal operation state of the flash memory and whether operations have been completed that can be used to control the operational flow of write/erase operations via the automatic algorithm. The automatic algorithm can verify the operation state of the built-in flash memory using the sequence of hardware accesses described below. ■ Hardware sequence flags The hardware sequence flags consist of the four bits DQ7, DQ6, DQ5, and DQ3. These bits have the following functions: DQ7 is the data polling flag, DQ6 is the toggle bit flag, DQ5 is the timing limit excess flag, and DQ3 is the sector erase timer flag. The hardware sequence flags can therefore be used to confirm that writing or chip sector erase has been completed or that erase code write is valid. To reference the hardware sequence flag, read the address of the sector for the internal flash memory after the corresponding command sequence has been set (refer to Table 26.4-1 "Command sequence table"). Table 26.5-1 "Bit assignments of hardware sequence flags" shows the bit assignments of the hardware sequence flags. Table 26.5-1 Bit assignments of hardware sequence flags Bit number 7 6 5 4 3 2 1 0 Hardware sequence flag DQ7 DQ6 DQ5 - DQ3 - - - To check whether automatic write/chip sector erase is in progress, check either the hardware sequence flags or the RDY bit of the flash memory control register (FMCS) to determine whether the last write operation has already ended. After the end of a write/erase operation, the operational state returns to read/reset. During actual programming, perform the subsequent operations, such as reading data, only after checking either flag for whether automatic writing/ erasing has ended. Similarly, whether a sector erase code can be issued again can be verified with the hardware sequence flag. The hardware sequence flags are described below. Table 26.5-2 "List of hardware sequence flag functions" lists the hardware sequence flag functions. 476 CHAPTER 26 2M BIT FLASH MEMORY Table 26.5-2 List of hardware sequence flag functions State DQ7 DQ6 DQ5 DQ3 DQ7 --> DATA: 7 Toggle --> DATA: 6 0 --> DATA: 5 0 --> DATA: 3 0 --> 1 Toggle --> Stop 0 --> 1 1 0 Toggle 0 0 --> 1 Erase operation --> sector erase suspend (sector being erased) 0 --> 1 Toggle --> 1 0 1 --> 0 Sector erase suspend --> erase resume (sector being erased) 1 --> 0 1 --> Toggle 0 0 --> 1 DATA: 7 DATA: 6 DATA: 5 DATA: 3 DQ7 Toggle 1 0 0 Toggle 1 1 Write operation --> write completed (specifying the write address) Chip sector erase operation --> erase completed State change in normal operation mode Sector erase wait --> erase start Sector erase suspend mode (sector not being erased) Operational error During write operation During chip sector erase operation 477 CHAPTER 26 2M BIT FLASH MEMORY 26.5.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is a flag that is used to indicate via the data polling function whether execution of the automatic algorithm is in progress or has ended. ■ State transitions of the data polling flag (DQ7) ❍ State changes during normal operation Operation state Write operation --> completed Chip sector erase --> completed Sector erase wait --> start Sector erase --> erase suspend (sector being erased) Sector erase suspend --> resume (sector being erased) Sector erased Suspend mode Sector not being erased DQ7 DQ7 --> DATA: 7 0 --> 1 0 0 --> 1 1 --> 0 DATA: 7 ❍ State changes in operation error mode Operation state Write operation Chip sector erase operation DQ7 DQ7 0 --> 1 ■ Write operation During read accesses while the automatic write algorithm is executed, bit 7 of the last data item written to flash memory is referenced and output, regardless of the specified address. If the read operation is performed at the time when the automatic write algorithm has ended, the read value of bit 7 for the specified address in flash memory is output. ■ Chip/sector erase operation When the chip erase/sector erase algorithm is being executed, "0" is returned in read operations of the flash memory, either for the sector currently erased in sector erase mode, or independently of addressing in chip erase mode. "1" is output when the chip erase/sector erase algorithm has ended. 478 CHAPTER 26 2M BIT FLASH MEMORY ■ Sector erase suspend Read operations of the flash memory while sector erase is suspended will return "1" if an address for the sector being erased has been specified, or will return the read value of bit 7 (DATA: 7) for the specified data item will be output in other cases. Which sector is being erased, and whether that sector is in sector suspend state, can be identified by referring to the toggle bit flag (DQ6). Note: If the automatic algorithm starts, read accesses to the specified address are not effective. In data read operations, the other bits can be output provided the end of data polling flag (DQ7) is set. Thus, read data after the end of the automatic algorithm only after the read access that confirms the end of data polling. 479 CHAPTER 26 2M BIT FLASH MEMORY 26.5.2 Toggle Bit Flag (DQ6) Like the data polling flag (DQ7), the toggle bit flag (DQ6) is a flag mainly used to indicate whether the automatic algorithm is being executed or has ended. In the case of the toggle bit flag, a toggle bit function is used for that purpose. ■ State transitions of the toggle bit flag (DQ6) ❍ State transitions in normal operation Operation state Write operation --> completed Chip sector erase --> completed Sector erase wait --> start Sector erase --> erase suspend (sector being erased) Sector erase suspend --> resume (sector being erased) Sector erased Suspend mode Sector not being erased DQ6 Toggle --> DATA: 6 Toggle --> Stop Toggle Toggle --> 1 1 --> Toggle DATA: 6 ❍ State transitions in operation error mode Operation state Write operation Chip sector erase operation DQ6 Toggle Toggle ■ Write/chip sector erase operations In the case of repeated read accesses when the automatic write algorithm and the chip sector erase algorithm are being executed, the flash memory toggles between output of 1 and 0 in toggle mode for each read operation independent of addressing. When repeated read accesses are performed when the automatic write algorithm and chip/sector erase algorithm have ended, the flash memory stops with the toggle operation of bit 6, and instead outputs bit 6 (DATA: 6) of the read value for the specified address. ■ Sector erase suspend If read access is performed when a sector erase operation is suspended, the flash memory outputs "1" when the specified address belongs to the sector being erased. In other cases, bit 6 (DATA: 6) of the read value for the specified address will be output. Reference: If, in write operations, the sector to be written is rewrite-protected, toggle operation is performed for about 2 µs before the operation ends without any data being rewritten. If, in erase operation, all sectors selected are rewrite-protected, toggle operation is performed for about 100 µs before the device returns to the read/reset state without any data being changed. 480 CHAPTER 26 2M BIT FLASH MEMORY 26.5.3 Timing Limit Excess Flag (DQ5) The timing limit excess flag (DQ5) is used to indicate when the execution of the automatic algorithm exceeds the time (internal pulse count) specified in the internal flash memory. ■ State transitions of the timing limit excess flag (DQ5) ❍ State transitions in normal operation Operation state Write operation --> completed Chip sector erase --> completed Sector erase wait --> start Sector erase --> erase suspend (sector being erased) Sector erase suspend --> resume (sector being erased) Sector erased Suspend mode Sector not being erased DQ5 0 --> DATA: 5 0 --> 1 0 0 0 DATA: 5 ❍ State transitions in operation error mode Operation state Write operation Chip sector erase operation DQ5 1 1 ■ Write/chip sector erase operation If a read access is performed after a writing operation occurs or the chip sector erase automatic algorithm starts, "0" is output if the specified time (for write/erase operations) is not exceeded, while "1" is output if this time is exceeded. This operation is independent of whether the automatic algorithm is being executed or has ended, thus allowing whether a failure has occurred during a write/erase operation to be determined. If this flag indicates "1" while the automatic algorithm is still being executed according to the data polling function or toggle bit function, it can be assumed that a failure during a write operation has occurred. For example, if there is an attempt to write "1" to a flash memory address whose corresponding value has already been set to "0", a failure occurs. In this case, the flash memory will be locked, and the automatic algorithm will not end. As a result, the data polling flag (DQ7) will output that there is no valid data. The toggle bit flag (DQ6) will continue with the toggle operation until the time limit is exceeded, and the timing limit excess flag (DQ5) will output "1". This indicates that the flash memory is not defective, but was used incorrectly. If this state occurs, execute the reset command. 481 CHAPTER 26 2M BIT FLASH MEMORY 26.5.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) indicates whether the device is waiting for the end of sector erase after starting of the sector erase command. ■ State transitions of sector erase timer flag (DQ3) ❍ State changes during normal operation Operation state Write operation --> completed Chip sector erase --> completed Sector erase wait --> start Sector erase --> erase suspend (sector being erased) Sector erase suspend --> resume (sector being erased) Sector erased Suspend mode Sector not being erased DQ3 0 --> DATA: 3 1 0 --> 1 1 --> 0 0 --> 1 DATA: 3 ❍ State changes in operation error mode Operation state Write operation Chip sector erase operation DQ3 0 1 ■ Sector erase operation In read accesses after the sector erase command starts, the flash memory outputs "0", irrespective of the address specified by the address signal for the sector that issued the command, or it outputs "1" if the sector erase waiting time was exceeded. If the data polling function or toggle bit function shows that the erase algorithm is being executed and this flag is set to "1", erasure under internal control will start. Subsequent commands other than writing the sector erase code or erase suspend are ignored until the erasure is completed. If this flag is set to "0", the flash memory will accept writing of the sector erase code. Fujitsu recommends checking the state of the flag before subsequent sector erase codes are written to verify the operational state of the device. If a second state check returns "1", the erase code for an additional sector may not have been accepted. ■ Sector erase suspend If read access is performed when a sector erase operation is suspended, the flash memory outputs "1" for an address of a sector being erased. Otherwise, the read value of bit 3 (DATA: 3) for the corresponding address will be output. 482 CHAPTER 26 2M BIT FLASH MEMORY 26.6 Flash Memory Write/Erase Operations This section describes various operation procedures after issuing the automatic algorithm start command, including flash memory read/reset, write, chip erase, sector erase, sector erase suspend and sector erase resume. ■ Flash memory write/erase The flash memory performs a bus write cycle according to the command sequence (see Table 26.4-1 "Command sequence table") for operations such as read/reset, write, chip erase, sector erase, sector erase suspend, and erase resume to execute the automatic algorithm. Write cycle to each bus must be executed consecutively. The end of the automatic algorithm can be detected with such functions as the data polling function. After a normal end, the operational state returns to the read/reset state. This section describes the following items related to flash memory write/erase operations. • Setting the flash memory to read/reset state • Writing data • Erasing all data (entire chip erase) • Erasing arbitrary data (sector erase) • Suspending sector erase • Resuming sector erase 483 CHAPTER 26 2M BIT FLASH MEMORY 26.6.1 Setting the Flash Memory to Read/Reset State This section describes the procedures for issuing read/reset commands and setting the flash memory state to read/reset. ■ Setting the flash memory to the read/reset state To set the flash memory to the read/reset state, continuously send the read/reset command in the command sequence table (see Table 26.4-1 "Command sequence table") to the relevant sector in the flash memory. Read/reset commands use two types of command sequences: execution in one bus operation and execution in three bus operations. There are no basic differences in between command sequences. The read/reset state is the initial state of the flash memory. It occurs at power-on or at normal end of a command. The read/reset state is a state in which the device waits for input of other commands. The read/reset state enables data to be read with normal read accesses. Program access from the CPU is performed in the same way that it is for mask ROM. However, this command does not require that a data read operation end normally: This command is mainly used to initialize the automatic algorithm if a command does not end for some reason. 484 CHAPTER 26 2M BIT FLASH MEMORY 26.6.2 Writing Data to Flash Memory This section describes the procedures for issuing a write command to write data to the flash memory. ■ Writing data to flash memory To start the automatic data write algorithm for the flash memory, repeatedly send the write command in the command sequence table (see Table 26.4-1 "Command sequence table") to the relevant sector in the flash memory. When data writing to the target address is completed in the 4th cycle, the automatic algorithm, and therefore automatic writing, will start. ❍ Address specification method Only an even write address can be specified in the write data cycle. Specifying an odd address will cause a failure during writing. It is necessary to write to even addresses in word units. Any order of addresses or even addresses exceeding the sector boundary are acceptable in write operations. However, a single write command can only write one word of data. ❍ Notes on writing data An already written item of data cannot be overwritten by another item in a writing operation. When an item of data is overwritten, the data polling algorithm (DQ7) or toggle operation (DQ6) will not end and the flash memory element will be judged to be defective. Consequently, the specified time for writing will be exceeded, and either the timing limit excess flag (DQ6) will indicate an error, or it will falsely appear as if overwriting had been successful, but subsequent read operations in the read/reset state will nevertheless return the original value. A data item can only be overwritten by performing a erase operation in between. During execution of automatic write, all other commands are ignored. Note that if a hardware reset starts while a write operation is in progress, the data that is written to the address is not assured. 485 CHAPTER 26 2M BIT FLASH MEMORY ■ Operation for writing to flash memory Figure 26.6-1 "Example of the Flash Memory Write Procedure" shows an example of the procedure for writing to flash memory. Using the hardware sequence flag (see Section 25.5, "Verifying the Execution State of the Automatic Algorithm"), the operational state of the automatic algorithm operating on the flash memory can be determined. In this example, the data polling flag (DQ7) is used to indicate the end of writing. During the flag check, data is read from the last address data was written to. The data polling flag (DQ7) changes at the same time as the timing limit excess flag (DQ5). Even if the timing limit excess flag (DQ5) is "1", the data polling flag bit (DQ7) must be checked again. Since the toggle bit flag (DQ6) also stops the toggle operation when the timing limit excess flag bit (DQ5) is set to "1", the toggle bit flag (DQ6) must be checked again in this case. Figure 26.6-1 Example of the Flash Memory Write Procedure Start of write operation FMCS:WE(bit5) Enable flash memory write Write command sequence (1) FxAAAA XXAA (2) Fx5554 XX55 (3) FxAAAA XXA0 (4) Write address write data Next address Internal address read Data polling(DQ7) Data Data 0 Timing limit(DQ5) 1 Internal address read Data Data polling(DQ7) Data Write error Last address FMCS:WE(bit5) Flash memory write prohibited Write completed 486 Check by hardware sequence flag CHAPTER 26 2M BIT FLASH MEMORY 26.6.3 Erasing All Data in the Flash Memory (Chip Erase) This section describes the procedure for issuing the chip erase command to erase all data in the flash memory. ■ Erasing all data in the flash memory (chip erase) To erase all data in the flash memory, repeatedly send the chip erase command in the command sequence table (see Table 26.4-1 "Command sequence table") to the relevant sector in the flash memory. The chip erase command is executed in six bus operations. When the write operation is completed in the 6th cycle, the chip erase operation will start. During the chip erase operation, the user does not need to write to the flash memory before erasing; during execution of the automatic erase algorithm, "0" will automatically be written to all cells of the flash memory for verification before erasure. 487 CHAPTER 26 2M BIT FLASH MEMORY 26.6.4 Erasing Arbitrary Data in Flash Memory (Sector Erase) This section describes the procedure for issuing a sector erase command to erase an arbitrary sector in flash memory. This procedure allows either erasure of individual sectors or erasure of multiple sectors at the same time to be specified. ■ Erasing arbitrary data in the flash memory (sector erase) To erase an arbitrary sector in flash memory, repeatedly send the sector erase command in the command sequence table (see Table 26.4-1 "Command sequence table") to the relevant sector in the flash memory. ❍ Method for specifying a sector The sector erase command is performed in six bus operations. To start a sector erase wait of 50µs, write the sector erase code (30H) in the 6th cycle to an arbitrary even address in the target sector that can be accessed. To erase multiple sectors using the above procedure, write the erase code (30H) sequentially to the addresses of the target sector to be erased. ❍ Notes on specifying multiple sectors Erase operation starts when the sector erase wait time of 50 µs has elapsed after the last sector erase code has been written. In other words, to erase multiple sectors at the same time, enter the next erase sector address and erase code (which must be entered in the 6th cycle of the command sequence) within 50 µs. After this time limit is exceeded, the sector address or erase code may not be accepted. Whether the next sector erase code can be written can be checked using the sector erase timer (hardware sequence flag:DQ3). In this case, the address for reading the sector erase timer must also specify the sector to be erased. ■ Procedure for sector erasure The hardware sequence flag (see Section 26.5 "Verifying the Execution State of the Automatic Algorithm") can be used to identify the operational state of the automatic algorithm operating on the internal flash memory. Figure 26.6-2 "Example of sector erase procedure for flash memory" shows an example of the procedure for sector erasure of the flash memory. In this example, the toggle bit flag (DQ6) is used to check for the end of erasure. Be sure that the data read in the flag check is data from the sector to be read. The toggle bit flag (DQ6) stops the toggle operation when the timing limit excess flag (DQ5) changes to "1". Therefore, even if DQ5 is "1", check the toggle bit flag (DQ6) again. The data polling flag (DQ7) also changes when the timing limit excess flag (DQ5) changes. Therefore, check the data polling flag (DQ7) again. 488 CHAPTER 26 2M BIT FLASH MEMORY Figure 26.6-2 Example of sector erase procedure for flash memory Start of deletion FMCS:WE(bit5) Flash memory deletion enabled Delete command sequence (1) FxAAAA XXAA (2) Fx5554 XX55 (3) FxAAAA XX80 (4) FxAAAA XXAA (5) Fx5554 XX55 (6) Enter code to the delete sector (30H) Y Any other delete sector? N Internal address read 1 N Next sector Internal address read 2 Y Sector Erase completed ? Y Toggle bit(DQ6) Data 1 (DQ6) = data 2 (DQ6) N 0 Timing limit(DQ5) 1 Internal address read 1 Internal address read 2 N Toggle bit(DQ6) Data 1 (DQ6) = data 2 (DQ6) Y Delete error N Last sector Y FMCS:WE(bit5) Flash memory deletion disabled Delete completed Check using hardware sequence flag 489 CHAPTER 26 2M BIT FLASH MEMORY 26.6.5 Suspending Sector Erasure for the Flash Memory This section describes the procedure for issuing the sector erase suspend command to suspend a sector erase operation for the flash memory. During erase suspension, data can be read from any sector that is not subject to erasure. ■ Suspending sector erasure for the flash memory To suspend sector erasure for the flash memory, repeatedly send the sector erase suspend command in the command sequence table (see Table 26.4-1 "Command sequence table") to the internal flash memory. The sector erase suspend command is used to suspend the erasure during a sector erase operation, allowing data from a sector that is not being erased to be read. In this state, only reading is allowed; writing is prohibited. This command is enabled only in sector erase mode, including within the erase wait time, and ignored in chip erase mode or during write operations. This operation is executed by writing the erase suspend code (B0H). To do so, specify an arbitrary address in flash memory. During the erase suspend state, repeatedly issued erase suspend commands are ignored. If a sector erase suspend command is entered during the sector erase wait time, sector erase wait ends immediately, the erase operation is interrupted, and the operational state changes to erase stop. If a erase suspend command is entered during a sector erase operation after the sector erase wait time, the system enters the erase suspend mode after 15 µs have elapsed or earlier. 490 CHAPTER 26 2M BIT FLASH MEMORY 26.6.6 Resuming the Sector Erasure of Flash Memory This section describes the procedure for issuing the sector erase resume command and resuming a suspended flash memory sector erase operation. ■ Resuming the sector erasure of flash memory To resume a suspended sector erase operation, repeatedly send the sector erase resume command in the command sequence table (see Table 26.4-1 "Command sequence table") to the internal flash memory. The sector erase resume command is used to resume a sector erasure from the sector erase suspend mode caused by a sector erase suspend command. This command is executed by writing the erase restart code (30H) while specifying an arbitrary address in the flash memory area. Issuing the sector erase restart command again during a sector erase operation will be ignored. 491 CHAPTER 26 2M BIT FLASH MEMORY 492 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION This chapter shows an example of a serial programming connection using the AF220/ AF210/AF120/AF110 Flash Micro-computer Programmer by Yokogawa Digital Computer Corporation. 27.1 "Basic Configuration" 27.2 "Oscillation Clock Frequency and Serial Clock Input Frequency" 27.3 "System Configuration of Flash Microcomputer Programmer" 27.4 "Examples of Serial Programming Connection" 493 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.1 Basic Configuration The MB90F474/MB90F476 supports serial onboard writing (Fujitsu standard) of the flash ROM. This section provides the related specifications. ■ Basic configuration Figure 27.1-1 "Basic configuration of example serial programming connection" shows the basic configuration for the example serial programming connection. Fujitsu standard serial onboard writing uses the Yokogawa Digital Computer Corporation flash microcomputer programmer. Figure 27.1-1 Basic configuration of example serial programming connection Host interface cable (AZ201) RS232C Flash MicroController Programmer + memory card Common general-purpose cable (AZ210) CLK synchronous serial connection MB90F474, MB90F476 User system Operable in stand-alone mode For information on the functions of and operational procedures related to the flash microcomputer programmer (AF220/AF210/AF120/AF110), the general-purpose common cable (AZ210) for connection, and the connector, contact Yokogawa Digital Computer Corporation. 494 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION ■ Pins used for Fujitsu standard serial onboard writing Table 27.1-1 "Function of pins" shows the functions of the related pins. Table 27.1-1 Function of pins Pin MD2, MD1, MD0 Function Description Mode pin Setting MD2=1, MD1=1, and MD0=0 to enter the serial programming mode. X0, X1 Oscillation pin As, in the serial programming mode, CPU internal operation clock is the PLL clock multiplied-by-1, the internal operation clock frequency is equal to the oscillation clock frequency. Consequently, the frequencies that can be input to the highspeed oscillation input pin for serial writing are from 1 to 20 MHz. P80, P81 Programming program start pin Set P80 to an input of "L" level and P81 to an input of "H" level. RST Reset pin SIN0 Serial data input pin SOT0 Serial data output pin SCK0 Serial clock input pin VCC Power voltage supply pin If the programming voltage (VCC = 3 V ± 10%) is supplied from the user system, connection with the flash microcomputer programmer is not required. VSS GND pin Must be shared with GND of the flash microcomputer programmer. - Use UART0 for CLK sync mode. Figure 27.1-2 Pin control circuit AF220/AF210/AF120/AF110 Write control pin 10 KΩ MB90F474, MB90F476 Write control pin AF220/AF210/AF120/AF110 /TICS pin User Note: To use the P80, P81, SIN0, SOT0, and SCK0 pins within the user system as well, the control circuit shown in the Figure 27.1-2 "Pin control circuit" is required. Using the flash microcomputer programmer’s/TICS signal, the user circuit can be disconnected in serial programming mode. Refer to the connection example. 495 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.2 Oscillation Clock Frequency and Serial Clock Input Frequency The serial clock frequencies that can be used for input to the MB90F474/MB90F476 can be derived from the following formulas. Change the serial clock input frequency corresponding to the oscillation clock frequency used based on the settings of the flash microcomputer programmer. ■ Oscillation clock frequency and serial clock input frequency Calculate the serial clock frequency that can be input as follows: Serial clock frequency to be input = 0.125 x oscillation clock frequency Table 27.2-1 "Example of serial clock frequency calculation" shows a calculation example. Table 27.2-1 Example of serial clock frequency calculation Oscillation clock frequency Maximum serial clock frequency that can be input to microcomputer Maximum serial clock frequency that can be set for AF220/AF210/AF120/AF110 Maximum serial clock frequency that can be set for AF200 4 MHz 500kHz 500kHz 500kHz 8 MHz 1MHz 850kHz 500kHz 16 MHz 2MHz 1.25MHz 500kHz 496 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.3 System Configuration of Flash Microcomputer Programmer This section describes the system configuration of flash microcomputer programmer. ■ System Configuration of the Flash Microcomputer Programmer Table 27.3-1 "System configuration of the flash microcomputer programmer" shows the system configuration of the flash microcomputer programmer. Table 27.3-1 System configuration of the flash microcomputer programmer Type AF220/AC4P Main body Function Model with built-in Ethernet interface /100 V to 220 V power adapter AF210/AC4P Standard model /100 V to 220 V power adapter AF120/AC4P Model with built-in single key Ethernet interface /100 V to 220 V power adapter AF110/AC4P Single key model /100 V to 220 V power adapter AZ221 Programmer dedicated RS232C cable for PC/AT AZ210 Standard target probe (a) length: 1 m FF201 Fujitsu F2MC-16LX flash microcomputer control module AZ290 Remote controller /P2 2MB PC Card (Option) FLASH memory capacity up to 128 KB supported /P4 4MB PC Card (Option) FLASH memory capacity of up to 512 KB supported Inquiries: Yokogawa Digital Computer Corporation Telephone number: (81)-42-333-6224 497 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.4 Examples of Serial Programming Connection This section shows examples of serial programming connections in various modes. ■ Examples of Serial Programming Connections Examples for the following two types of connections are shown below. 498 • Example of connection in single-chip mode (using power from the user system) • Example minimum connection with flash microcomputer programmer (using power from the user system) CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.4.1 Example of Connection in Single-Chip Mode (Using Power from User System) In the user system, mode pins MD2 and MD0, which are set to single-chip mode, are supplied with the inputs MD2=1 and MD0=0 by TAUX3 and TMODE of AF220/AF210/ AF120/AF110, and the system is set to serial programming mode (serial programming mode: MD2, MD1, MD0="110"). ■ Example of Connection in Single-Chip Mode (Using Power from User System) Figure 27.4-1 Example of serial programming connection in single chip mode for MB90F474/MB90F476 (power supplied from the user system) AF220/AF210/AF120/AF110 Flash Micro-Controller Programmer TAUX3 User system MB90F474, Connector DX10-28S MB90F476 MD2 (19) 10 kΩ 10kΩ MD1 10 kΩ TMODE (12) MD0 X0 1MHz to 20MHz X1 TAUX (23) /TICS (10) P80 10 KΩ User 10 kΩ 10 kΩ /TRES (5) RST 10 kΩ User P81 TTXD (13) SIN0 TRXD (27) (6) SOT0 TCK TVcc GND SCK0 (2) Power supplied from user (7, 8, 14, 15, 21, 22, 1, 28) Pin 14 Pins 3, 4, 9, 11, 16, 17, 18, 20, 24, 25, and 26 are open. Vss Pin 1 DX10-28S Pin 28 DX10-28S: DX10-28S: write angle type Vcc Pin 15 Pin assignments of connector (Hirose Electric) 499 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION Figure 27.4-2 Pin control circuit MB90F474, MB90F476 Write control pin AF220/AF210/AF120/AF110 Write control pin AF220/AF210/AF120/AF110 10 KΩ /TICS pin User Note: 500 • Similarly to P80, using the SIN0, SOT0, and SCK0 pins in the user system requires a control circuit as shown in Figure 27.4-2 "Pin control circuit" (the user circuit is disconnected in serial programming mode by the flash microcomputer programmer’s "/TICS" signal). • Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off. CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION 27.4.2 Example of Minimum Connection with Flash Microcomputer Programmer (Using Power from the User System) If, in serial programming mode, pins (MD2, MD0 and P00) are set as shown below, MD2, MD0, and P00 do not need to be connected with the flash microcomputer programmer. ■ Example of Minimum Connection with Flash Microcomputer Programmer (Using Power from the User System) Figure 27.4-3 Example of minimum connection with flash micro-computer programmer of MB90F474/ MB90F476 (using power from the user system) AF220/AF210/AF120/AF110 Flash Micro-Controller Programmer User system MB90F474, MB90F476 10 kΩ Serial write 1 MD2 Serial write 1 10 kΩ 10 kΩ MD1 10 kΩ 10 kΩ MD0 Serial write 0 10 kΩ X0 1MHz to 20MHz X1 P80 Serial write 0 10 kΩ 10 kΩ User circuit P81 Serial write 1 User circuit Connector DX10-28S /TRES TTXD TRXD 10 kΩ (5) RST (13) SIN0 SOT0 (27) (6) TCK TVcc SCK0 (2) (7, 8, 14, 15, 21, 22, 1, 28) GND Power supplied from user Pin 14 Pins 3, 4, 9, 11, 12, 16, 17, 18, 20, 23, 24, 25, and 26 are open. Vss Pin 1 DX10-28S Pin 28 DX10-28S: write angle type Vcc Pin 15 Pin assignments of connector(Hirose Electric) 501 CHAPTER 27 EXAMPLES OF MB90F474/MB90F476 SERIAL PROGRAMMING CONNECTION Figure 27.4-4 Pin control circuit MB90F474, MB90F476 Write control pin AF220/AF210/AF120/AF110 Write control pin 10 KΩ AF220/AF210/AF120/AF110 /TICS pin User Note: 502 • Using the pins SIN0, SOT0, and SCK0 in the user system requires a control circuit as shown in Figure 27.4-4 "Pin control circuit" (the user circuit is disconnected in serial programming mode by the flash microcomputer programmer’s "/TICS" signal). • Connect to AF220/AF210/AF120/AF110 when the power of the user system is turned off. APPENDIX The appendix provides the memory map and lists the instructions used in the F2MC16LX. APPENDIX A "Memory Map" APPENDIX B "Instructions" 503 APPENDIX APPENDIX A Memory Map Memory space is divided according to three usage modes. ■ Memory space The memory space is divided according to three usage modes shown in Figure A-1 "Memory Map". Figure A-1 Memory Map Single chip Internal ROM/external bus External ROM/external bus FFFFFFH ROM area ROM area Address #1 010000H ROM area Image of bank FF ROM area Image of bank FF 004000H *1 Address #2 RAM Register RAM Register RAM Register 000100H 0000D0H Peripheral Peripheral Peripheral 000000H : Internal : External : No access *1: Models in which address #2 duplicates 004000H have no external area. Table A-1 "Relationship between addresses #1 and #2 by product type" shows the relationship between address #1 and address #2 for each product type. 504 APPENDIX A Memory Map Table A-1 Relationship between addresses #1 and #2 by product type Type Address #1 Address #2 MB90473 FE0000H 002900H MB90474 FC0000H 004000H MB90477/478 FC0000H 002100H MB90F474 FC0000H 004000H MB90V470 (FC0000H) 004000H The ROM contents of bank FF can be viewed as an image in the upper part of bank 00, allowing the C compiler's small model to be more efficiently utilized. Because the lower 16 bits are identical, pointer declarations do not require the "far" specification to reference the table in ROM. For example, an access to 00C000H will actually be performed as access to the ROM contents at FFC000H. However, if the ROM area in bank FF exceeds 48 KB, it is not possible to view all areas via their image in bank 00. For this reason, an image of the area from FF4000H to FFFFFFH can be seen in bank 00, while an image of the area from FF0000H to FF3FFFH can only be viewed via bank FF. 505 APPENDIX ■ I/O maps Table A-2 "I/O Map" shows the addresses assigned to the registers for each peripheral function. Table A-2 I/O Map Address Register Abbreviation Access Resource Initial value 00H Port 0 data register PDR0 R/W Port 0 XXXXXXXX 01H Port 1 data register PDR1 R/W Port 1 XXXXXXXX 02H Port 2 data register PDR2 R/W Port 2 XXXXXXXX 03H Port 3 data register PDR3 R/W Port 3 XXXXXXXX 04H Port 4 data register PDR4 R/W Port 4 XXXXXXXX 05H Port 5 data register PDR5 R/W Port 5 XXXXXXXX 06H Port 6 data register PDR6 R/W Port 6 XXXXXXXX 07H Port 7 data register PDR7 R/W Port 7 11XXXXXX 08H Port 8 data register PDR8 R/W Port 8 XXXXXXXX 09H Port 9 data register PDR9 R/W Port 9 XXXXXXXX 0AH Port A data register PDRA R/W Port A ----XXXX 0BH Port 3 timer input enable register UDRE R/W U/D timer input control XX000000 0CH Interrupt/DTP enable register ENIR R/W 0DH Interrupt/DTP enable register EIRR R/W 0EH Request level setting register 0FH Request level setting register 10H Port 0 direction register DDR0 R/W Port 0 00000000 11H Port 1 direction register DDR1 R/W Port 1 00000000 12H Port 2 direction register DDR2 R/W Port 2 00000000 13H Port 3 direction register DDR3 R/W Port 3 00000000 14H Port 4 direction register DDR4 R/W Port 4 00000000 15H Port 5 direction register DDR5 R/W Port 5 00000000 16H Port 6 direction register DDR6 R/W Port 6 00000000 17H Port 7 direction register DDR7 R/W Port 7 --000000 18H Port 8 direction register DDR8 R/W Port 8 00000000 19H Port 9 direction register DDR9 R/W Port 9 00000000 1AH Port A direction register DDRA R/W Port A ----0000 1BH Port 4 pin register ODR4 R/W Port 4 (OD control) 00000000 1CH Port 0 resistor register RDR0 R/W Port 0 (PULLUP) 00000000 506 R/W 00000000 DTP/external interrupt 00000000 00000000 ELVR R/W 00000000 APPENDIX A Memory Map Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value 1DH Port 1 resistor register RDR1 R/W Port 1 (PULLUP) 00000000 1EH Port 7 pin register ODR7 R/W Port 7 (OD control) --000000 1FH Analog input enable register ADER R/W Port 5, A/D 11111111 20H Serial mode register 0 SMR0 R/W 00000X00 21H Serial control register 0 SCR0 R/W 00000100 22H Serial input register/serial output register SIDR0/ SODR0 R/W XXXXXXXX 23H Serial status register SSR0 R/W 00001000 UART0 Reserved area 24H Communication prescaler (UART) 25H Clock division control register CDCR R/W 26H Serial mode control status register 0 SMCS0 R/W 27H Serial mode control status register 0 SMCS0 R/W 28H Serial data register SDR0 R/W 29H Clock division control register SDCR0 R/W 2AH Serial mode control status register 1 SMCS1 R/W 2BH Serial mode control status register 1 SMCS1 R/W 2CH Serial data register SDR1 R/W 2DH Clock division control register SDCR1 R/W 2EH PPG reload register L (ch0) PRLL0 R/W XXXXXXXX 2FH PPG reload register H (ch0) PRLH0 R/W XXXXXXXX 30H PPG reload register L (ch1) PRLL1 R/W XXXXXXXX 31H PPG reload register H (ch1) PRLH1 R/W XXXXXXXX 32H PPG reload register L (ch2) PRLL2 R/W XXXXXXXX 33H PPG reload register H (ch2) PRLH2 R/W 34H PPG reload register L (ch3) PRLL3 R/W 35H PPG reload register H (ch3) PRLH3 R/W XXXXXXXX 36H PPG reload register L (ch4) PRLL4 R/W XXXXXXXX 37H PPG reload register H (ch4) PRLH4 R/W XXXXXXXX 38H PPG reload register L (ch5) PRLL5 R/W XXXXXXXX 39H PPG reload register H (ch5) PRLH5 R/W XXXXXXXX 00--0000 ----0000 SCI1 (ch0) 00000010 XXXXXXXX Communication prescaler (SCI0) 0---0000 ----0000 SCI2 (ch1) 00000010 XXXXXXXX Communication prescaler (SCI1) 8/16-bit PPG (ch0-5) 0---0000 XXXXXXXX XXXXXXXX 507 APPENDIX Table A-2 I/O Map (Continued) Address Register Abbreviation Access 3AH PPG0 operation mode control register PPGC0 R/W 0X000XX1 3BH PPG1 operation mode control register PPGC1 R/W 0X000001 3CH PPG2 operation mode control register PPGC2 R/W 3DH PPG3 operation mode control register PPGC3 R/W 0X000001 3EH PPG4 operation mode control register PPGC4 R/W 0X000XX1 3FH PPG5 operation mode control register PPGC5 R/W 0X000001 40H PPG0, 1 output control register PPG01 R/W 41H 42H PPG2, 3 output control register PPG4, 5 output control register 00000000 PPG23 R/W 8/16-bit PPG 00000000 PPG45 R/W 8/16-bit PPG 00000000 ADCS1 R/W ADCS2 R/W 00000000 Control status register 00000000 A/D converter ADCR1 R XXXXXXXX ADCR2 R 00000XXX OCCP0 R/W Data register 49H 508 8/16-bit PPG Reserved area 47H 48H 0X000XX1 8/16-bit PPG (ch0-5) Reserved area 45H 46H Initial value Reserved area 43H 44H Resource 4AH Output compare register (ch0) lower 4BH Output compare register (ch0) upper 4CH Output compare register (ch1) lower 4DH Output compare register (ch1) upper 4EH Output compare register (ch2) lower 4FH Output compare register (ch2) upper 50H Output compare register (ch3) lower 51H Output compare register (ch3) upper 52H Output compare register (ch4) lower 53H Output compare register (ch4) upper 54H Output compare register (ch5) lower 55H Output compare register (ch5) upper XXXXXXXX XXXXXXXX XXXXXXXX OCCP1 R/W XXXXXXXX XXXXXXXX OCCP2 OCCP3 R/W R/W 16-bit output timer output compare (ch0-5) XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX OCCP4 R/W XXXXXXXX XXXXXXXX OCCP5 R/W XXXXXXXX APPENDIX A Memory Map Table A-2 I/O Map (Continued) Address Register Abbreviation Access 56H Output compare control register (ch0) OCS0 R/W 0000--00 57H Output compare control register (ch1) OCS1 R/W ---00000 58H Output compare control register (ch2) OCS2 R/W 59H Output compare control register (ch3) OCS3 R/W 5AH Output compare control register (ch4) OCS4 R/W 0000--00 5BH Output compare control register (ch5) OCS5 R/W ---00000 5CH Input capture register (ch0) lower R XXXXXXXX 5DH Input capture register (ch0) upper 5EH Input capture register (ch1) lower 5FH Input capture register (ch1) upper 60H Input capture control register Resource 16-bit output timer output compare (ch0-5) Initial value 0000--00 ---00000 IPCP0 R R IPCP1 61H R ICS01 16-bit output timer input capture (ch0, 1) R/W XXXXXXXX XXXXXXXX XXXXXXXX 00000000 Reserved area 62H Timer data register lower TCDT R/W 00000000 63H Timer data register upper TCDT R/W 00000000 64H Timer control status register TCCS R/W 65H Timer control status register TCCS R/W 66H Compare clear register lower CPCLR R/W 67H Compare clear register upper 68H Up/down count register ch0 UDCR0 R 00000000 69H Up/down count register ch1 UDCR1 R 00000000 6AH Reload compare register ch0 RCR0 W 6BH Reload compare register ch1 RCR1 W 6CH Counter control register lower ch0 CCRL0 R/W 0X00X000 6DH Counter control register upper ch0 CCRH0 R/W 00000000 6EH 00000000 0--00000 XXXXXXXX XXXXXXXX 8/16-bit up/down timer counter 00000000 00000000 Reserved area 6FH ROM mirror function select register ROMM W 70H Counter control register lower ch1 CCRL1 R/W 71H Counter control register upper ch1 CCRH1 R/W 72H Count status register ch0 CSR0 R/W 73H 74H 16-bit output timer free-run timer ROM mirror function -------1 0X00X000 8/16-bit up/down timer counter -0000000 00000000 Reserved area Count status register ch1 CSR1 R/W 8/16-bit UDC 00000000 509 APPENDIX Table A-2 I/O Map (Continued) Address Register Access PWCSR0 R/W 16-bit PWC timer (ch0) PWC0 data buffer register PWCR0 00000000 PWC1 control status register PWCSR1 R/W 16-bit PWC timer (ch1) PWC1 data buffer register PWCR1 00000000 PWC2 control status register PWCSR2 R/W 16-bit PWC timer (ch2) PWC2 data buffer register PWCR2 PWC0 divide ratio register PWC1 divide ratio register R/W PWC (ch0) ------00 DIVR1 R/W PWC (ch1) ------00 PWC (ch2) ------00 Reserved area PWC2 divide ratio register DIVR2 R/W Reserved area 87H 88H I2C bus status register IBSR R 00000000 89H I2C bus control register IBCR R/W 00000000 8AH I2C bus clock select register ICCR R/W 8BH I2C bus address register IADR R/W -XXXXXXX 8CH I2C bus data register IDAR R/W XXXXXXXX 8DH 8EH I2C --0XXXXX Reserved area µPG status register 8FH to 9BH PGCSR R/W µPG 0000---- Use prohibited 9CH µDMA status register DSRL R/W µDMA 00000000 9DH µDMA status register DSRH R/W µDMA 00000000 9EH 510 DIVR0 Reserved area 85H 86H 00000000 00000000 83H 84H 0000000X R/W 81H 82H 00000000 00000000 7FH 80H 0000000X R/W 7DH 7EH 00000000 00000000 7BH 7CH 0000000X R/W 79H 7AH Initial value 00000000 PWC0 control status register 77H 78H Resource Reserved area 75H 76H Abbreviation Use prohibited APPENDIX A Memory Map Table A-2 I/O Map (Continued) Address Register Abbreviation Access Resource Initial value 9FH Delay interrupt source generate/ delete register DIRR R/W Delay interrupt generate module -------0 A0H Power saving mode register LPMCR R/W Saving power 00011000 A1H Clock select register CKSCR R/W Saving power 11111100 A2H to A3H Reserved area A4H µDMA stop status register DSSR R/W µDMA 00000000 A5H Automatic ready function selection register ARSR W External pin 0011--00 A6H External address signal control register HACR W External pin 00000000 A7H Bus control signal control register EPSR W External pin 1000*10- A8H Watchdog control register WDTC R/W Watchdog timer XXXXX111 A9H Timebase timer control register TBTC R/W Timebase timer 1XX00100 AAH Watch timer control register WTC R/W Watch timer 10001000 ABH Reserved area ACH µDMA control register DERL R/W µDMA 00000000 ADH µDMA control register DERH R/W µDMA 00000000 AEH Flash memory control status register FMCR R/W Flash memory I/F 000X0000 Use prohibited AFH B0H Interrupt control register 00 ICR00 R/W XXXX0111 B1H Interrupt control register 01 ICR01 R/W XXXX0111 B2H Interrupt control register 02 ICR02 R/W XXXX0111 B3H Interrupt control register 03 ICR03 R/W XXXX0111 B4H Interrupt control register 04 ICR04 R/W XXXX0111 B5H Interrupt control register 05 ICR05 R/W XXXX0111 B6H Interrupt control register 06 ICR06 R/W B7H Interrupt control register 07 ICR07 R/W XXXX0111 B8H Interrupt control register 08 ICR08 R/W XXXX0111 B9H Interrupt control register 09 ICR09 R/W XXXX0111 BAH Interrupt control register 10 ICR10 R/W XXXX0111 BBH Interrupt control register 11 ICR11 R/W XXXX0111 BCH Interrupt control register 12 ICR12 R/W XXXX0111 Interrupt controller XXXX0111 511 APPENDIX Table A-2 I/O Map (Continued) Address Register Abbreviation Access BDH Interrupt control register 13 ICR13 R/W BEH Interrupt control register 14 ICR14 R/W BFH Interrupt control register 15 ICR15 R/W XXXX0111 C0H Chip selection MASK register 0 CMR0 R/W 00001111 C1H Chip selection area register 0 CAR0 R/W 11111111 C2H Chip selection MASK register 0 CMR1 R/W 00001111 C3H Chip selection area register 0 CAR1 R/W 11111111 C4H Chip selection MASK register 0 CMR2 R/W C5H Chip selection area register 0 CAR2 R/W C6H Chip selection MASK register 0 CMR3 R/W 00001111 C7H Chip selection area register 0 CAR3 R/W 11111111 C8H Chip selection control register CSCR R/W ----000* C9H Chip selection control active level register CALR R/W ----0000 Control status register TMCSR R/W CAH CDH XXXX0111 Interrupt controller XXXX0111 00001111 Chip selection facility 11111111 ----0000 16-bit reload timer 16-bit timer register/16-bit reload register TMR/ TMRLR R/W CEH to CFH Reserved area D0H to FFH External area 100H to #H RAM area 512 Initial value 00000000 CBH CCH Resource XXXXXXXX APPENDIX A Memory Map ■ Interrupt sources, interrupt vectors, and interrupt control registers Table A-3 "Relationship between interrupt sources and interrupt vector/interrupt control registers" shows the relationship between interrupt sources and the interrupt vector/interrupt control registers. Table A-3 Relationship between interrupt sources and interrupt vector/interrupt control registers Interrupt source EI2OS clear µDMA channel number Interrupt vector Interrupt control register Number Address Number Address Reset #8 FFFFDCH - - INT9 instruction #9 FFFFD8H - - Exception #10 FFFFD4H - - ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH INT0 0 #11 FFFFD0H INT1 x #12 FFFFCCH INT2 x #13 FFFFC8H INT3 x #14 FFFFC4H INT4 x #15 FFFFC0H INT5 x #16 FFFFBCH INT6 x #17 FFFFB8H INT7 x #18 FFFFB4H PWC1 x #19 FFFFB0H PWC2 x #20 FFFFACH PWC0 1 #21 FFFFA8H PPG0/PPG1 counter borrow 2 #22 FFFFA4H PPG2/PPG3 counter borrow 3 #23 FFFFA0H PPG4/PPG5 counter borrow 4 #24 FFFF9CH 8/16-bit U/D counter timer compare/ underflow/overflow/up-down reverse (ch0, ch1) x #25 FFFF98H Input capture (ch0) 5 #26 FFFF94H Input capture (ch1) 6 #27 FFFF90H Output compare (ch0) match 8 #28 FFFF8CH Output compare (ch1) match 9 #29 FFFF88H Output compare (ch2) match 10 #30 FFFF84H Output compare (ch3) match x #31 FFFF80H Output compare (ch4) match x #32 FFFF7CH 513 APPENDIX Table A-3 Relationship between interrupt sources and interrupt vector/interrupt control registers µDMA channel number Number Address Output compare (ch5) match x #33 FFFF78H UART transmit completed 11 #34 FFFF74H 16-bit free-run timer/16-bit reload timer 12 #35 FFFF70H UART receive completed 7 #36 FFFF6CH SI01 13 #37 FFFF68H SI02 14 #38 FFFF64H x #39 FFFF60H 15 #40 FFFF5CH x #41 FFFF58H Interrupt source I2C interface EI2OS clear x A/D FLASH write/delete, timebase timer/ watch timer *1 x Delay interrupt generate module x x Interrupt vector #42 Interrupt control register Number Address ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH FFFF54H : Interrupt clear signal clears the interrupt request flag. A stop request is issued. : Interrupt clear signal clears the interrupt request flag. x: Interrupt clear signal will not clear the interrupt request flag. *1: Make sure that FLASH write/delete operations are not used during operation of the timebase timer and watch timer. Note 1: If the same interrupt number is assigned to two interrupt sources, the resource is cleared only if both interrupt request flags are cleared by DMAC interrupt clear signals. Therefore, if either of two interrupt functions uses the DMAC function, the other interrupt function cannot be used. Set the relevant resource's interrupt request enable bit to "0" and use software polling processing to handle this situation. 514 APPENDIX B Instructions APPENDIX B Instructions Appendix B describes the instructions used by the F2MC-16LX. B.1 "Instruction Types" B.2 "Addressing" B.3 "Direct Addressing" B.4 "Indirect Addressing" B.5 "Execution Cycle Count" B.6 "Effective Address Field" B.7 "How to Read the Instruction List" B.8 "F2MC-16LX Instruction List" B.9 "Instruction Map" 515 APPENDIX B.1 Instruction Types The F2MC-16LX supports 351 types of instructions. Addressing is enabled by using an effective address field of each instruction or using the instruction code itself. ■ Instruction Types The F2MC-16LX supports the following 351 types of instructions: 516 • 41 transfer instructions (byte) • 38 transfer instructions (word or long word) • 42 addition/subtraction instructions (byte, word, or long word) • 12 increment/decrement instructions (byte, word, or long word) • 11 comparison instructions (byte, word, or long word) • 11 unsigned multiplication/division instructions (word or long word) • 11 signed multiplication/division instructions (word or long word) • 39 logic instructions (byte or word) • 6 logic instructions (long word) • 6 sign inversion instructions (byte or word) • 1 normalization instruction (long word) • 18 shift instructions (byte, word, or long word) • 50 branch instructions • 6 accumulator operation instructions (byte or word) • 28 other control instructions (byte, word, or long word) • 21 bit operation instructions • 10 string instructions APPENDIX B Instructions B.2 Addressing With the F2MC-16LX, the address format is determined by the instruction effective address field or the instruction code itself (implied). When the address format is determined by the instruction code itself, specify an address in accordance with the instruction code used. Some instructions permit the user to select several types of addressing. ■ Addressing The F2MC-16LX supports the following 23 types of addressing: • Immediate (#imm) • Register direct • Direct branch address (addr16) • Physical direct branch address (addr24) • I/O direct (io) • Abbreviated direct address (dir) • Direct address (addr16) • I/O direct bit address (io:bp) • Abbreviated direct bit address (dir:bp) • Direct bit address (addr16:bp) • Vector address (#vct) • Register indirect (@RWj j = 0 to 3) • Register indirect with post increment (@RWj+ j = 0 to 3) • Register indirect with displacement (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) • Long register indirect with displacement (@RLi + disp8 i = 0 to 3) • Program counter indirect with displacement (@PC + disp16) • Register indirect with base index (@RW0 + RW7, @RW1 + RW7) • Program counter relative branch address (rel) • Register list (rlst) • Accumulator indirect (@A) • Accumulator indirect branch address (@A) • Indirectly-specified branch address (@ear) • Indirectly-specified branch address (@eam) 517 APPENDIX ■ Effective Address Field Table B.2-1 "Effective address field" lists the address formats specified by the effective address field. Table B.2-1 Effective address field Code Representation 00 R0 RW0 RL0 01 R1 RW1 (RL0) 02 R2 RW2 RL1 03 R3 RW3 (RL1) 04 R4 RW4 RL2 05 R5 RW5 (RL2) 06 R6 RW6 RL3 07 R7 RW7 (RL3) 08 @RW0 09 @RW1 Address format Default bank Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. None DTB DTB Register indirect 0A @RW2 ADB 0B @RW3 SPB 0C @RW0+ DTB 0D @RW1+ DTB Register indirect with post increment 0E @RW2+ ADB 0F @RW3+ SPB 10 @RW0+disp8 DTB 11 @RW1+disp8 DTB Register indirect with 8-bit displacement 12 @RW2+disp8 ADB 13 @RW3+disp8 SPB 14 @RW4+disp8 DTB 15 @RW5+disp8 DTB Register indirect with 8-bit displacement 16 @RW6+disp8 ADB 17 @RW7+disp8 SPB 18 @RW0+disp16 DTB 19 @RW1+disp16 DTB Register indirect with 16-bit displacement 518 1A @RW2+disp16 ADB 1B @RW3+disp16 SPB 1C @RW0+RW7 1D @RW1+RW7 1E @PC+disp16 1F addr16 DTB Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address DTB PCB DTB APPENDIX B Instructions B.3 Direct Addressing An operand value, register, or address is specified explicitly in direct addressing mode. ■ Direct Addressing ❍ Immediate addressing (#imm) Specify an operand value explicitly (#imm4/ #imm8/ #imm16/ #imm32). Figure B.3-1 Example of immediate addressing (#imm) MOVW A, #01212H (This instruction stores the operand value in A.) Before execution A 2233 4455 After execution A 4 4 5 5 1 2 1 2 (Some instructions transfer AL to AH.) ❍ Register direct addressing Specify a register explicitly as an operand. Table B.3-1 "Direct addressing registers" lists the registers that can be specified. Figure B.3-2 "Example of register direct addressing" shows an example of register direct addressing. Table B.3-1 Direct addressing registers General-purpose register Special-purpose register Byte R0, R1, R2, R3, R4, R5, R6, R7 Word RW0, RW1, RW2, RW3, RW4, R5W, RW6, RW7 Long word RL0, RL1, RL2, RL3 Accumulator A, AL Pointer SP *1 Bank PCB, DTB, USB, SSB, ADB Page DPR Control PS, CCR, RP, ILM *1: One of the user stack pointer (USP) and system stack pointer (SSP) is selected and used depending on the value of the S flag bit in the condition code register (CCR). For branch instructions, the program counter (PC) is not specified in an instruction operand but is specified implicitly. 519 APPENDIX Figure B.3-2 Example of register direct addressing MOV R0, A (This instruction transfers the eight low-order bits of A to the general-purpose register R0.) Before execution A 0716 2534 After execution A 0716 2564 Memory space R0 ?? Memory space R0 34 ❍ Direct branch addressing (addr16) Specify an offset explicitly for the branch destination address. The size of the offset is 16 bits, which indicates the branch destination in the logical address space. Direct branch addressing is used for an unconditional branch, subroutine call, or software interrupt instruction. Bits 23 to 16 of the address are specified by the program bank register (PCB). Figure B.3-3 Example of direct branch addressing (addr16) JMP 3B20H (This instruction causes an unconditional branch by direct branch addressing in a bank.) Before execution After execution PC 3 C 2 0 PCB 4 F PC 3 B 2 0 Memory space 4F3C22H 4F3C21H 4F3C20H 3B 20 62 4F3B20H Next instruction JMP 3B20H PCB 4 F ❍ Physical direct branch addressing (addr24) Specify an offset explicitly for the branch destination address. The size of the offset is 24 bits. Physical direct branch addressing is used for unconditional branch, subroutine call, or software interrupt instruction. Figure B.3-4 Example of direct branch addressing (addr24) JMPP 333B20H (This instruction causes an unconditional branch by direct branch 24-bit addressing.) Before execution After execution 520 PC 3 C 2 0 PC 3 B 2 0 PCB 4 F Memory space 4F3C23H 4F3C22H 4F3C21H 4F3C20H 33 3B 20 63 333B20H Next instruction PCB 3 3 JMPP 333B20H APPENDIX B Instructions ❍ I/O direct addressing (io) Specify an 8-bit offset explicitly for the memory address in an operand. The I/O address space in the physical address space from 000000H to 0000FFH is accessed regardless of the data bank register (DTB) and direct page register (DPR). A bank select prefix for bank addressing is invalid if specified before an instruction using I/O direct addressing. Figure B.3-5 Example of I/O direct addressing (io) MOVW A, i:0C0H (This instruction reads data by I/O direct addressing and stores it in A.) Before execution A 0716 2534 Memory space 0000C1H 0000C0H After execution A FF EE 2534 FFEE ❍ Abbreviated direct addressing (dir) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Figure B.3-6 Example of abbreviated direct addressing (dir) MOVW S;20H, A (This instruction writes the contents of the eight low-order bits of A in abbreviated direct addressing mode.) Before execution 4455 A 66 After execution A DTB 7 7 4455 66 Memory space 1212 776620H 1212 DTB 7 7 ?? Memory space 776620H 12 ❍ Direct addressing (addr16) Specify the 16 low-order bits of a memory address explicitly in an operand. Address bits 16 to 23 are specified by the data bank register (DTB). A prefix instruction for access space addressing is invalid for this mode of addressing. Figure B.3-7 Example of direct addressing (addr16) BRA 3B20H (This instruction causes an unconditional relative branch.) Before execution PC 3C20 PCB 4 F Memory space 4F3C22H 4F3C21H 4F3C20H After execution PC 3B20 FF FE 60 BRA 3B20H PCB 4 F 4F3B20H 521 APPENDIX ❍ I/O direct bit addressing (io:bp) Specify bits in physical addresses 000000H to 0000FFH explicitly. Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-8 Example of I/O direct bit addressing (io:bp) SETB I:0C1H: (This instruction sets bits by I/O direct bit addressing.) Memory space Before execution 0000C1H 00 After execution 0000C1H 01 ❍ Abbreviated direct bit addressing (dir:bp) Specify the eight low-order bits of a memory address explicitly in an operand. Address bits 8 to 15 are specified by the direct page register (DPR). Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-9 Example of abbreviated direct bit addressing (dir:bp) SETB S:10H:0 (This instruction sets bits by abbreviated direct bit addressing.) Memory space Before execution DTB 5 5 DPR 6 6 556610H 00 Memory space After execution DTB 5 5 DPR 6 6 556610H 01 ❍ Direct bit addressing (addr16:bp) Specify arbitrary bits in 64 kilobytes explicitly. Address bits 16 to 23 are specified by the data bank register (DTB). Bit positions are indicated by ":bp", where the larger number indicates the most significant bit (MSB) and the lower number indicates the least significant bit (LSB). Figure B.3-10 Example of direct bit addressing (addr16:bp) SETB 2222H:0 (This instruction sets bits by direct bit addressing.) Memory space Before execution DTB 5 5 552222H 00 Memory space After execution 522 DTB 5 5 552222H 01 APPENDIX B Instructions ❍ Vector Addressing (#vct) Specify vector data in an operand to indicate the branch destination address. There are two sizes for vector numbers: 4 bits and 8 bits. Vector addressing is used for a subroutine call or software interrupt instruction. Figure B.3-11 Example of vector addressing (#vct) CALLV #15 (This instruction causes a branch to the address indicated by the interrupt vector specified in an operand.) Before execution PC 0000 PCB F F After execution PC Memory space FFFFE1H FFFFE0H D0 00 FFC000H EF D000 PCB F F CALLV #15 Table B.3-2 CALLV vector list Instruction Vector address L Vector address H CALLV #0 XXFFFEH XXFFFFH CALLV #1 XXFFFCH XXFFFDH CALLV #2 XXFFFAH XXFFFBH CALLV #3 XXFFF8H XXFFF9H CALLV #4 XXFFF6H XXFFF7H CALLV #5 XXFFF4H XXFFF5H CALLV #6 XXFFF2H XXFFF3H CALLV #7 XXFFF0H XXFFF1H CALLV #8 XXFFEEH XXFFEFH CALLV #9 XXFFECH XXFFEDH CALLV #10 XXFFEAH XXFFEBH CALLV #11 XXFFE8H XXFFE9H CALLV #12 XXFFE6H XXFFE7H CALLV #13 XXFFE4H XXFFE5H CALLV #14 XXFFE2H XXFFE3H CALLV #15 XXFFE0H XXFFE1H Note: A PCB register value is set in XX. Note: When the program bank register (PCB) is FFH, the vector area overlaps the vector area of IN #vct8 (#0 to #7). Use vector addressing carefully (see Table B.3-2 "CALLV vector list"). 523 APPENDIX B.4 Indirect Addressing In indirect addressing mode, an address is specified indirectly by the address data of an operand. ■ Indirect Addressing ❍ Register indirect addressing (@RWj j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. Figure B.4-1 Example of register indirect addressing (@RWj j = 0 to 3) MOVW A, @RW1 (This instruction reads data by register indirect addressing and stores it in A.) Before execution A 0716 2534 RW1 D 3 0 F DTB 7 8 After execution A Memory space 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 0 F DTB 7 8 ❍ Register indirect addressing with post increment (@RWj+ j = 0 to 3) Memory is accessed using the contents of general-purpose register RWj as an address. After operand operation, RWj is incremented by the operand size (1 for a byte, 2 for a word, or 4 for a long word). Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0 or RW1 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 is used, or additional data bank register (ADB) when RW2 is used. If the post increment results in the address of the register that specifies the increment, the incremented value is referenced after that. In this case, if the next instruction is a write instruction, priority is given to writing by an instruction and, therefore, the register that would be incremented becomes write data. 524 APPENDIX B Instructions Figure B.4-2 Example of register indirect addressing with post increment (@RWj+ j = 0 to 3) MOVW A, @RW1+ (This instruction reads data by register indirect addressing with post increment and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 After execution A 78D310H 78D30FH FF EE 2534 FFEE RW1 D 3 1 1 DTB 7 8 ❍ Register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) Memory is accessed using the address obtained by adding an offset to the contents of generalpurpose register RWj. Two types of offset, byte and word offsets, are used. They are added as signed numeric values. Address bits 16 to 23 are indicated by the data bank register (DTB) when RW0, RW1, RW4, or RW5 is used, system stack bank register (SSB) or user stack bank register (USB) when RW3 or RW7 is used, or additional data bank register (ADB) when RW2 or RW6 is used. Figure B.4-3 Example of register indirect addressing with offset (@RWi + disp8 i = 0 to 7, @RWj + disp16 j = 0 to 3) MOVW A, @RW1+10H (This instruction reads data by register indirect addressing with an offset and stores it in A.) Before execution A 0716 2534 Memory space RW1 D 3 0 F DTB 7 8 78D320H 78D31FH FF EE (+10H) After execution A 2534 FFEE RW1 D 3 0 F DTB 7 8 ❍ Long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) Memory is accessed using the address that is the 24 low-order bits obtained by adding an offset to the contents of general-purpose register RLi. The offset is 8-bits long and is added as a signed numeric value. Figure B.4-4 Example of long register indirect addressing with offset (@RLi + disp8 i = 0 to 3) MOVW A, @RL2+25H (This instruction reads data by long register indirect addressing with an offset and stores it in A.) Before execution A RL2 0716 2534 F382 4B02 Memory space 824B28H 824B27H FF EE (+25H) After execution A 2534 FFEE RL2 F382 4B02 525 APPENDIX ❍ Program counter indirect addressing with offset (@PC + disp16) Memory is accessed using the address indicated by (instruction address + 4 + disp16). The offset is one word long. Address bits 16 to 23 are specified by the program bank register (PCB). Note that the operand address of each of the following instructions is not deemed to be (next instruction address + disp16): • DBNZ eam, rel • DWBNZ eam, rel • CBNE eam, #imm8, rel • CWBNE eam, #imm16, rel • MOV eam, #imm8 • MOVW eam, #imm16 Figure B.4-5 Example of program counter indirect addressing with offset (@PC + disp16) MOVW A, @PC+20H (This instruction reads data by program counter indirect addressing with a offset and stores it in A.) Before execution A 0716 2534 PCB C 5 PC 4 5 5 6 After execution A 2534 FFEE PCB C 5 PC 4 5 5 A Memory space C5457BH C5457AH FF EE C5455AH +20H C54559H +4 C54558H C54557H C54556H 00 20 9E 73 MOVW A, @PC+20H ❍ Register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) Memory is accessed using the address determined by adding RW0 or RW1 to the contents of general-purpose register RW7. Address bits 16 to 23 are indicated by the data bank register (DTB). Figure B.4-6 Example of register indirect addressing with base index (@RW0 + RW7, @RW1 + RW7) MOVW A, @RW1+RW7 (This instruction reads data by register indirect addressing with a base index and stores it in A.) Before execution A 0716 RW1 D 3 0 F 2534 DTB 7 8 + RW7 0 1 0 1 After execution A 2534 FFEE RW1 D 3 0 F RW7 0 1 0 1 526 DTB 7 8 Memory space 78D411H 78D410H FF EE APPENDIX B Instructions ❍ Program counter relative branch addressing (rel) The address of the branch destination is a value determined by adding an 8-bit offset to the program counter (PC) value. If the result of addition exceeds 16 bits, bank register incrementing or decrementing is not performed and the excess part is ignored, and therefore the address is contained within a 64-kilobyte bank. This addressing is used for both conditional and unconditional branch instructions. Address bits 16 to 23 are indicated by the program bank register (PCB). Figure B.4-7 Example of program counter relative branch addressing (rel) BRA 3B20H (This instruction causes an unconditional relative branch.) Before execution PC 3C20 PCB 4 F Memory space 4F3C22H 4F3C21H 4F3C20H After execution PC 3B20 FF FE 60 BRA 3B20H PCB 4 F 4F3B20H Next instruction ❍ Register list (rlst) Specify a register to be pushed onto or popped from a stack. Figure B.4-8 Configuration of the register list MSB LSB RW7 RW6 RW5 RW4 RW3 RW2 RW1 RW0 A register is selected when the corresponding bit is 1 and deselected when the bit is 0. 527 APPENDIX Figure B.4-9 Example of register list (rlist) POPW RW0, RW4 (This instruction transfers memory data indicated by the SP to multiple word registers indicated by the register list.) SP 34FA SP RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 SP 02 01 04 03 Memory space Memory space SP 34FEH 34FDH 34FCH 34FBH 34FAH 04 03 02 01 34FE 04 03 02 01 34FEH 34FDH 34FCH 34FBH 34FAH After execution Before execution ❍ Accumulator indirect addressing (@A) Memory is accessed using the address indicated by the contents of the low-order bytes (16 bits) of the accumulator (AL). Address bits 16 to 23 are specified by a mnemonic in the data bank register (DTB). Figure B.4-10 Example of accumulator indirect addressing (@A) MOVW A, @A (This instruction reads data by accumulator indirect addressing and stores it in A.) Before execution A 0716 2534 DTB B B After execution A 0716 FFEE DTB B B 528 Memory space BB2535H BB2534H FF EE APPENDIX B Instructions ❍ Accumulator indirect branch addressing (@A) The address of the branch destination is the content (16 bits) of the low-order bytes (AL) of the accumulator. It indicates the branch destination in the bank address space. Address bits 16 to 23 are specified by the program bank register (PCB). For the Jump Context (JCTX) instruction, however, address bits 16 to 23 are specified by the data bank register (DTB). This addressing is used for unconditional branch instructions. Figure B.4-11 Example of accumulator indirect branch addressing (@A) JMP @A (This instruction causes an unconditional branch by accumulator indirect branch addressing.) Before execution PC 3C20 PCB 4 F A 6677 3B20 PC 3B20 PCB 4 F Memory space 4F3C20H 4F3B20H After execution A 61 JMP @A Next instruction 6677 3B20 ❍ Indirect specification branch addressing (@ear) The address of the branch destination is the word data at the address indicated by ear. Figure B.4-12 Example of indirect specification branch addressing (@ear) JMP @@RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution 3C20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC Memory space 4F3C21H 4F3C20H 4F3B20H After execution 3B20 PCB 4 F PW0 7 F 4 8 DTB 2 1 PC 217F49H 217F48H 08 73 JMP @@RW0 Next instruction 3B 20 ❍ Indirect specification branch addressing (@eam) The address of the branch destination is the word data at the address indicated by eam. Figure B.4-13 Example of indirect specification branch addressing (@eam) JMP @RW0 (This instruction causes an unconditional branch by register indirect addressing.) Before execution PC 3C20 PCB 4 F 4F3C21H 4F3C20H PW0 3 B 2 0 After execution PC 3B20 Memory space PCB 4 F 4F3B20H 00 73 JMP @RW0 Next instruction PW0 3 B 2 0 529 APPENDIX B.5 Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. ■ Execution Cycle Count The number of cycles required for instruction execution (execution cycle count) is obtained by adding the number of cycles required for each instruction, "correction value" determined by the condition, and the number of cycles for instruction fetch. In the mode of fetching an instruction from memory such as internal ROM connected to a 16-bit bus, the program fetches the instruction being executed in word increments. Therefore, intervening in data access increases the execution cycle count. Similarly, in the mode of fetching an instruction from memory connected to an 8-bit external bus, the program fetches every byte of an instruction being executed. Therefore, intervening in data access increases the execution cycle count. In CPU intermittent operation mode, access to a general-purpose register, internal ROM, internal RAM, internal I/O, or external data bus causes the clock to the CPU to halt for the cycle count specified by the CG0 and CG1 bits of the low power consumption mode control register. Therefore, for the cycle count required for instruction execution in CPU intermittent operation mode, add the "access count x cycle count for the halt" as a correction value to the normal execution count. 530 APPENDIX B Instructions ■ Calculating the Execution Cycle Count Table B.5-1 "Execution cycle counts in each addressing mode" lists execution cycle counts and Table B.5-2 "Cycle count correction values for counting execution cycles" and Table B.5-3 "Cycle count correction values for counting instruction fetch cycles" summarize correction value data. Table B.5-1 Execution cycle counts in each addressing mode (a) (*1) Code Operand 00 | 07 Ri Rwi RLi 08 | 0B Execution cycle count in each addressing mode Register access count in each addressing mode See the instruction list. See the instruction list. @RWj 2 1 0C | 0F @RWj+ 4 2 10 | 17 @RWi+disp8 2 1 18 | 1B @RWi+disp16 2 1 1C 1D 1E 1F @RW0+RW7 @RW1+RW7 @PC+disp16 addr16 4 4 2 1 2 2 0 0 *1: (a) is used for List". (cycle count) and B (correction value) in B.8 "F2MC-16LX Instruction 531 APPENDIX Table B.5-2 Cycle count correction values for counting execution cycles (b) byte (*1) Operand (c) word (*1) (d) long (*1) Cycle count Access count Cycle count Access count Cycle count Access count Internal register +0 1 +0 1 +0 2 Internal memory Even address +0 1 +0 1 +0 2 Internal memory Odd address +0 1 +2 2 +4 4 External data bus 16-bit even address +1 1 +1 1 +2 2 External data bus 16-bit odd address +1 1 +4 2 +8 4 External data bus 8-bits +1 1 +4 2 +8 4 *1: (b), (c), and (d) are used for Instruction List". (cycle count) and B (correction value) in B.8 "F2MC-16LX Note: When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. Table B.5-3 Cycle count correction values for counting instruction fetch cycles Byte boundary Word boundary Internal memory - +2 External data bus 16-bits - +3 External data bus 8-bits +3 - Instruction Note: 532 • When an external data bus is used, the cycle counts during which an instruction is made to wait by ready input or automatic ready must also be added. • Actually, instruction execution is not delayed by every instruction fetch. Therefore, use the correction values to calculate the worst case. APPENDIX B Instructions B.6 Effective Address Field Table B.6-1 "Effective address field" shows the effective address field. ■ Effective Address Field Table B.6-1 Effective address field Code Representation 00 01 R0 R1 RW0 RW1 RL0 (RL0) 02 03 R2 R3 RW2 RW3 RL1 (RL1) 04 05 R4 R5 RW4 RW5 RL2 (RL2) 06 07 R6 R7 RW6 RW7 RL3 (RL3) 08 09 @RW0 @RW1 0A 0B @RW2 @RW3 0C 0D @RW0+ @RW1+ 0E 0F @RW2+ @RW3+ 10 11 @RW0+disp8 @RW1+disp8 12 13 @RW2+disp8 @RW3+disp8 14 15 @RW4+disp8 @RW5+disp8 16 17 @RW6+disp8 @RW7+disp8 18 19 @RW0+disp16 @RW1+disp16 1A 1B @RW2+disp16 @RW3+disp16 1C 1D 1E 1F Address format Byte count of extended address part (*1) Register direct: Individual parts correspond to the byte, word, and long word types in order from the left. - Register indirect 0 Register indirect with post increment 0 Register indirect with 8-bit displacement 1 Register indirect with 16-bit displacement 2 @RW0+RW7 @RW1+RW7 Register indirect with index Register indirect with index 0 0 @PC+disp16 addr16 PC indirect with 16-bit displacement Direct address 2 2 *1: Each byte count of the extended address part applies to + in the # (byte count) column in B.8 "F2MC-16LX Instruction List". 533 APPENDIX B.7 How to Read the Instruction List Table B.7-1 "Description of items in the instruction list" describes the items used in the F2MC-16LX Instruction List, and Table B.7-2 "Explanation on symbols in the instruction list" describes the symbols used in the same list. ■ Description of instruction presentation items and symbols Table B.7-1 Description of items in the instruction list Item Mnemonic # Description Uppercase, symbol: Represented as is in the assembler. Lowercase: Rewritten in the assembler. Number of following lowercase: Indicates bit length in the instruction. Indicates the number of bytes. Indicates the number of cycles. See Table B.2-1 "Effective address field" for the alphabetical letters in items. RG B Operation 534 Indicates the number of times a register access is performed during instruction execution. The number is used to calculate the correction value for CPU intermittent operation. Indicates the correction value used to calculate the actual number of cycles during instruction execution. The actual number of cycles during instruction execution can be determined by adding the value in the column to this value. Indicates the instruction operation. LH Indicates the special operation for bits 15 to 08 of the accumulator. Z: Transfers 0. X: Transfers after sign extension. -: No transfer AH Indicates the special operation for the 16 high-order bits of the accumulator. *: Transfers from AL to AH. -: No transfer Z: Transfers 00 to AH. X: Transfers 00H or FFH to AH after AL sign extension. APPENDIX B Instructions Table B.7-1 Description of items in the instruction list (Continued) Item I S T N Description Each indicates the state of each flag: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), C (carry). *: Changes upon instruction execution. -: No change Z: Set upon instruction execution. X: Reset upon instruction execution. Z V C RMW Indicates whether the instruction is a Read Modify Write instruction (reading data from memory by the I instruction and writing the result to memory). *: Read Modify Write instruction -: Not Read Modify Write instruction Note: Cannot be used for an address that has different meanings between read and write operations. Table B.7-2 Explanation on symbols in the instruction list Symbol A Explanation The bit length used varies depending on the 32-bit accumulator instruction. Byte: Low-order 8 bits of byte AL Word: 16 bits of word AL Long word: 32 bits of AL and AH AH 16 high-order bits of A AL 16 low-order bits of A SP Stack pointer (USP or SSP) PC Program counter PCB Program bank register DTB Data bank register ADB Additional data bank register SSB System stack bank register USB User stack bank register SPB Current stack bank register (SSB or USB) DPR Direct page register brg1 DTB, ADB, SSB, USB, DPR, PCB, SPB brg2 DTB, ADB, SSB, USB, DPR, SPB 535 APPENDIX Table B.7-2 Explanation on symbols in the instruction list (Continued) Symbol Ri R0, R1, R2, R3, R4, R5, R6, R7 RWi RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RWj RW0, RW1, RW2, RW3 RLi RL0, RL1, RL2, RL3 dir Abbreviated direct addressing addr16 Direct addressing addr24 Physical direct addressing ad24 0-15 Bits 0 to 15 of addr24 ad24 16-23 Bits 16 to 23 of addr24 io I/O area (000000H to 0000FFH) #imm4 4-bit immediate data #imm8 8-bit immediate data #imm16 16-bit immediate data #imm32 32-bit immediate data ext (imm8) 16-bit data obtained by sign extension of 8-bit immediate data disp8 8-bit displacement disp16 16-bit displacement bp Bit offset vct4 Vector number (0 to 15) vct8 Vector number (0 to 255) ( )b Bit address rel PC relative branch ear Effective addressing (code 00 to 07) eam Effective addressing (code 08 to 1F) rlst 536 Explanation Register list APPENDIX B Instructions B.8 F2MC-16LX Instruction List Table B.8-1 "41 Transfer instructions (byte)" to Table B.8-18 "10 String instructions" list the instructions used by the F2MC-16LX. ■ F2MC-16LX Instruction List Table B.8-1 41 Transfer instructions (byte) Mnemonic # MOV A,dir MOV A,addr16 MOV A,Ri MOV A,ear MOV A,eam MOV A,io MOV A,#imm8 MOV A,@A MOV A,@RLi+disp8 MOVN A,#imm4 MOVX A,dir MOVX A,addr16 MOVX A,Ri MOVX A,ear MOVX A,eam MOVX A,io MOVX A,#imm8 MOVX A,@A MOVX A,@RWi+disp8 MOVX A,@RLi+disp8 MOV dir,A MOV addr16,A MOV Ri,A MOV ear,A MOV eam,A MOV io,A MOV @RLi+disp8,A MOV Ri,ear MOV Ri,eam MOV ear,Ri MOV eam,Ri MOV Ri,#imm8 MOV io,#imm8 MOV dir,#imm8 MOV ear,#imm8 MOV eam,#imm8 MOV @AL,AH / MOV @A,T XCH A,ear XCH A,eam XCH Ri,ear XCH Ri,eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ RG 3 4 2 2 3 + (a) 3 2 3 10 1 3 4 2 2 3 + (a) 3 2 3 5 10 3 4 2 2 3 + (a) 3 10 3 4 + (a) 4 5 + (a) 2 5 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2 x (b) 0 2 x (b) Operation byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RLi)+disp8) byte (A) <-- imm4 byte (A) <-- (dir) byte (A) <-- (addr16) byte (A) <-- (Ri) byte (A) <-- (ear) byte (A) <-- (eam) byte (A) <-- (io) byte (A) <-- imm8 byte (A) <-- ((A)) byte (A) <-- ((RWi)+disp8) byte (A) <-- ((RLi)+disp8 byte (dir) <-- (A) byte (addr16) <-- (A) byte (Ri) <-- (A) byte (ear) <-- (A) byte (eam) <-- (A) byte (io) <-- (A) byte ((RLi)+disp8) <-- (A) byte (Ri) <-- (ear) byte (Ri) <-- (eam) byte (ear) <-- (Ri) byte (eam) <-- (Ri) byte (Ri) <-- imm8 byte (io) <-- imm8 byte (dir) <-- imm8 byte (ear) <-- imm8 byte (eam) <-- imm8 byte ((A)) <-- (AH) byte (A) <--> (ear) byte (A) <--> (eam) byte (Ri) <--> (ear) byte (Ri) <--> (eam) L H A H I S T N Z V C R M W Z Z Z Z Z Z Z Z Z Z X X X X X X X X X X Z Z - * * * * * * * * * * * * * * * * * * - - - * * * * * * * * * R - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - * * * * * * * * * * * * * * * * * * * * * * * * - - - - Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 537 APPENDIX Table B.8-2 38 Transfer instructions (byte) Mnemonic # MOVW A,dir MOVW A,addr16 MOVW A,SP MOVW A,RWi MOVW A,ear MOVW A,eam MOVW A,io MOVW A,@A MOVW A,#imm16 MOVW A,@RWi+disp8 MOVW A,@RLi+disp8 MOVW dir,A MOVW addr16,A MOVW SP,A MOVW RWi,A MOVW ear,A MOVW eam,A MOVW io,A MOVW @RWi+disp8,A MOVW @RLi+disp8,A MOVW RWi,ear MOVW MOVW ear,Rwi MOVW eam,Rwi MOVW RWi,#imm16 MOVW io,#imm16 MOVW ear,#imm16 MOVW eam,#imm16 MOVW @AL,AH / MOVW @A,T XCHW A,ear XCHW A,eam XCHW RWi, ear XCHW RWi, eam MOVL A,ear MOVL A,eam MOVL A,#imm32 MOVL ear,A MOVL eam,A 2 3 3 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 2 2+ 5 2 2+ RG 3 4 1 2 2 3 + (a) 3 3 2 5 10 3 4 1 2 2 3 + (a) 3 5 10 3 4 + (a) 4 5 + (a) 2 5 2 4 + (a) 3 4 5 + (a) 7 9 + (a) 4 5 + (a) 3 4 5 + (a) 0 0 0 1 1 0 0 0 2 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 2 0 0 2 0 B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2 x (c) 0 2 x (c) 0 (d) 0 0 (d) Operation word (A) <-- (dir) word (A) <-- (addr16) word (A) <-- (SP) word (A) <-- (RWi) word (A) <-- (ear) word (A) <-- (eam) word (A) <-- (io) word (A) <-- ((A)) word (A) <-- imm16 word (A) <-- ((RWi)+disp8) word (A) <-- ((RLi)+disp8) word (dir) <-- (A) word (addr16) <-- (A) word (SP) <-- (A) word (RWi) <-- (A) word (ear) <-- (A) word (eam) <-- (A) word (io) <-- (A) word ((RWi)+disp8) <-- (A) word ((RLi)+disp8) <-- (A) word (RWi) <-- (ear) word (RWi) <-- (eam) word (ear) <-- (RWi) word (eam) <-- (RWi) word (RWi) <-- imm16 word (io) <-- imm16 word (ear) <-- imm16 word (eam) <-- imm16 word ((A)) <-- (AH) word (A) <--> (ear) word (A) <-- >(eam) word (RWi) <--> (ear) word (RWi) <--> (eam) long (A) <-- (ear) long (A) <-- (eam) long (A) <-- imm32 long (ear1) <-- (A) long(eam1) <-- (A) L H A H I S T N Z V C R M W - * * * * * * * * * * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 538 APPENDIX B Instructions Table B.8-3 42 Addition/subtraction instructions (byte, word, long word) Mnemonic # RG B ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 x (b) 0 0 (b) 0 SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A,dir A,ear A,eam ear,A eam,A A A,ear A,eam A 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4 + (a) 3 5 + (a) 2 3 4 + (a) 3 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2 x (b) 0 0 (b) 0 ADDW ADDW ADDW ADDW ADDW ADDW ADDCW ADDCW SUBW SUBW SUBW SUBW SUBW SUBW SUBCW SUBCW ADDL ADDL ADDL SUBL SUBL SUBL A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A A,ear A,eam A,#imm16 ear,A eam,A A,ear A,eam A,ear A,eam A,#imm32 A,ear A,eam A,#imm32 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 2+ 5 2 2+ 5 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 6 7+(a) 4 6 7+(a) 4 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0 0 0 (c) 0 0 2 x (c) 0 (c) 0 0 (c) 0 0 2 x (c) 0 (c) 0 (d) 0 0 (d) 0 Operation byte (A) <-- (A) + imm8 byte (A) <-- (A) + (dir) byte (A) <-- (A) + (ear) byte (A) <-- (A) + (eam) byte (ear) <-- (ear) + (A) byte (eam) <-- (eam) + (A) byte (A) <-- (AH) + (AL) + (C) byte (A) <-- (A) + (ear)+ (C) byte (A) <-- (A) + (eam)+ (C) byte (A) <-- (AH) + (AL) + (C) (decimal) byte (A) <-- (A) - imm8 byte (A) <-- (A) - (dir) byte (A) <-- (A) - (ear) byte (A) <-- (A) - (eam) byte (ear) <-- (ear) - (A) byte (eam) <-- (eam) - (A) byte (A) <-- (AH) - (AL) - (C) byte (A) <-- (A) - (ear) - (C) byte (A) <-- (A) - (eam) - (C) byte (A) <-- (AH) - (AL) - (C) (decimal) word (A) <-- (AH) + (AL) word (A) <-- (A) + (ear) word (A) <-- (A) + (eam) word (A) <-- (A) + imm16 word (ear) <-- (ear) + (A) word (eam) <-- (eam) + (A) word (A) <-- (A) + (ear) + (C) word (A) <-- (A) + (eam) + (C) word (A) <-- (AH) - (AL) word (A) <-- (A) - (ear) word (A) <-- (A) - (eam) word (A) <-- (A) - imm16 word (ear) <-- (ear) - (A) word (eam) <-- (eam) - (A) word (A) <-- (A) - (ear) - (C) word (A) <-- (A) - (eam) - (C) long (A) <-- (A) + (ear) long (A) <-- (A) + (eam) long (A) <-- (A) + imm32 long (A) <-- (A) - (ear) long (A) <-- (A) - (eam) long (A) <-- (A) - imm32 L H A H I S T N Z V C R M W Z Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Z Z Z Z Z Z Z Z - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 539 APPENDIX Table B.8-4 12 Increment/decrement instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W INC ear 2 3 2 0 byte (ear) <-- (ear) + 1 - - - - - * * * - - INC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) + 1 - - - - - * * * - * DEC ear 2 3 2 0 byte (ear) <-- (ear) - 1 - - - - - * * * - - DEC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) - 1 - - - - - * * * - * INCW ear 2 3 2 0 word (ear) <-- (ear) + 1 - - - - - * * * - - INCW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) + 1 - - - - - * * * - * DECW ear 2 3 2 0 word (ear) <-- (ear) - 1 - - - - - * * * - - DECW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) - 1 - - - - - * * * - * INCL ear 2 7 4 0 long (ear) <-- (ear) + 1 - - - - - * * * - - INCL eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) + 1 - - - - - * * * - * DECL ear 2 7 4 0 long (ear) <-- (ear) - 1 - - - - - * * * - - DECL eam 2+ 9+(a) 0 2 x (d) long (eam) <-- (eam) - 1 - - - - - * * * - * Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. Table B.8-5 11 Compare instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W CMP A 1 1 0 0 byte (AH) - (AL) - - - - - * * * * - CMP A,ear 2 2 1 0 byte (A) - (ear) - - - - - * * * * - CMP A,eam 2+ 3+(a) 0 (b) byte (A) - (eam) - - - - - * * * * - CMP A,#imm8 2 2 0 0 byte (A) - imm8 - - - - - * * * * - CMPW A 1 1 0 0 word (AH) - (AL) - - - - - * * * * - CMPW A,ear 2 2 1 0 word (A) - (ear) - - - - - * * * * - CMPW A,eam 2+ 3+(a) 0 (c) word (A) - (eam) - - - - - * * * * - CMPW A,#imm16 3 2 0 0 word (A) - imm16 - - - - - * * * * - CMPL A,ear 2 6 2 0 long (A) - (ear) - - - - - * * * * - CMPL A,eam 2+ 7+(a) 0 (d) long (A) - (eam) - - - - - * * * * - CMPL A,#imm32 5 3 0 0 long (A) - imm32 - - - - - * * * * - Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 540 APPENDIX B Instructions Table B.8-6 11 Unsigned multiplication/division instructions (word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W DIVU A 1 *1 0 0 word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) - - - - - - - * * - DIVU A,ear 2 *2 1 0 word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) - - - - - - - * * - DIVU A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) - - - - - - - * * - DIVUW A,ear 2 *4 1 0 long (A) / word (ear) quotient --> word (A) remainder --> word (ear) - - - - - - - * * - DIVUW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient --> word (A) remainder --> word (eam) - - - - - - - * * - MULU A 1 *8 0 0 byte (AH) * byte (AL) --> word (A) - - - - - - - - - - MULU A,ear 2 *9 1 0 byte (A) * byte (ear) --> word (A) - - - - - - - - - - MULU A,eam 2+ *10 0 (b) byte (A) * byte (eam) --> word (A) - - - - - - - - - - MULUW A 1 *11 0 0 word (AH) * word (AL) --> Long (A) - - - - - - - - - - MULUW A,ear 2 *12 1 0 word (A) * word (ear) --> Long (A) - - - - - - - - - - MULUW A,eam 2+ *13 0 (c) word (A) * word (eam) --> Long (A) - - - - - - - - - - *1: 3: Division by 0 7: Overflow 15: Normal *2: 4: Division by 0 8: Overflow 16: Normal *3: 6+(a): Division by 0 9+(a): Overflow 19+(a): Normal *4: 4: Division by 0 7: Overflow 22: Normal *5: 6+(a): Division by 0 8+(a): Overflow 26+(a): Normal *6: (b): Division by 0 or overflow 2 x (b): Normal *7: (c): Division by 0 or overflow 2 x (c): Normal *8: 3: Byte (AH) is 0. 7: Byte (AH) is not 0. *9: 4: Byte (ear) is 0. 8: Byte (ear) is not 0. *10: 5+(a): Byte (eam) is 0, 9+(a): Byte (eam) is not 0. *11: 3: Word (AH) is 0. 11: Word (AH) is not 0. *12: 4: Word (ear) is 0. 12: Word (ear) is not 0. *13: 5+(a): Word (eam) is 0. 13+(a): Word (eam) is not 0. Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 541 APPENDIX Table B.8-7 11 Signed multiplication/division instructions (word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W DIV A 2 *1 0 0 word (AH) / byte (AL) quotient --> byte (AL) remainder --> byte (AH) Z - - - - - - * * - DIV A,ear 2 *2 1 0 word (A) / byte (ear) quotient --> byte (A) remainder --> byte (ear) Z - - - - - - * * - DIV A,eam 2+ *3 0 *6 word (A) / byte (eam) quotient --> byte (A) remainder --> byte (eam) Z - - - - - - * * - DIVW A,ear 2 *4 1 0 long (A) / word (ear) quotient --> word (A) remainder --> word (ear) - - - - - - - * * - DIVW A,eam 2+ *5 0 *7 long (A) / word (eam) quotient --> word (A) remainder --> word (eam) - - - - - - - * * - MUL A 2 *8 0 0 byte (AH) * byte (AL) --> word (A) - - - - - - - - - - MUL A,ear 2 *9 1 0 byte (A) * byte (ear) --> word (A) - - - - - - - - - - MUL A,eam 2+ *10 0 (b) byte (A) * byte (eam) --> word (A) - - - - - - - - - - MULW A 2 *11 0 0 word (AH) * word (AL) --> Long (A) - - - - - - - - - - MULW A,ear 2 *12 1 0 word (A) * word (ear) --> Long (A) - - - - - - - - - - MULW A,eam 2+ *13 0 (c) word (A) * word (eam) --> Long (A) - - - - - - - - - - *1: *2: *3: *4: 3: Division by 0, 8 or 18: Overflow, 18: Normal 4: Division by 0, 11 or 22: Overflow, 23: Normal 5+(a): Division by 0, 12+(a) or 23+(a): Overflow, 24+(a): Normal When dividend is positive; 4: Division by 0, 12 or 30: Overflow, 31: Normal When dividend is negative; 4: Division by 0, 12 or 31: Overflow, 32: Normal *5: When dividend is positive; 5+(a): Division by 0, 12+(a) or 31+(a): Overflow, 32+(a): Normal When dividend is negative; 5+(a): Division by 0, 12+(a) or 32+(a): Overflow, 33+(a): Normal *6: (b): Division by 0 or overflow, 2 x (b): Normal *7: (c): Division by 0 or overflow, 2 x (c): Normal *8: 3: Byte (AH) is 0, 12: result is positive, 13: result is negative *9: 4: Byte (ear) is 0, 13: result is positive, 14: result is negative *10: 5+(a): Byte (eam) is 0, 14+(a): result is positive, 15+(a): result is negative *11: 3: Word (AH) is 0, 16: result is positive, 19: result is negative *12: 4: Word (ear) is 0, 17: result is positive, 20: result is negative *13: 5+(a): Word (eam) is 0, 18+(a): result is positive, 21+(a): result is negative Notes: 542 • The execution cycle count found when an overflow occurs in a DIV or DIVW instruction may be a pre-operation count or a post-operation count depending on the detection timing. • When an overflow occurs with DIV or DIVW instruction, the contents of the AL are destroyed. • See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. APPENDIX B Instructions Table B.8-8 39 Logic 1 instructions (byte, word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W AND A,#imm8 2 2 0 0 byte (A) <-- (A) and imm8 - - - - - * * R - - AND A,ear 2 3 1 0 byte (A) <-- (A) and (ear) - - - - - * * R - - AND A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) and (eam) - - - - - * * R - - AND ear,A 2 3 2 0 byte (ear) <-- (ear) and (A) - - - - - * * R - - AND eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) and (A) - - - - - * * R - * OR A,#imm8 2 2 0 0 byte (A) <-- (A) or imm8 - - - - - * * R - - OR A,ear 2 3 1 0 byte (A) <-- (A) or (ear) - - - - - * * R - - OR A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) or (eam) - - - - - * * R - - OR ear,A 2 3 2 0 byte (ear) <-- (ear) or (A) - - - - - * * R - - OR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) or (A) - - - - - * * R - * XOR A,#imm8 2 2 0 0 byte (A) <-- (A) xor imm8 - - - - - * * R - - XOR A,ear 2 3 1 0 byte (A) <-- (A) xor (ear) - - - - - * * R - - XOR A,eam 2+ 4+(a) 0 (b) byte (A) <-- (A) xor (eam) - - - - - * * R - - XOR ear,A 2 3 2 0 byte (ear) <-- (ear) xor (A) - - - - - * * R - - XOR eam,A 2+ 5+(a) 0 2 x (b) byte (eam) <-- (eam) xor (A) - - - - - * * R - * NOT A 1 2 0 0 byte (A) <-- not (A) - - - - - * * R - - NOT ear 2 3 2 0 byte (ear) <-- not (ear) - - - - - * * R - - NOT eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- not (eam) - - - - - * * R - * ANDW A 1 2 0 0 word (A) <-- (AH) and (A) - - - - - * * R - - ANDW A,#imm16 3 2 0 0 word (A) <-- (A) and imm16 - - - - - * * R - - ANDW A,ear 2 3 1 0 word (A) <-- (A) and (ear) - - - - - * * R - - ANDW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) and (eam) - - - - - * * R - - ANDW ear,A 2 3 2 0 word (ear) <-- (ear) and (A) - - - - - * * R - - ANDW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) and (A) - - - - - * * R - * ORW A 1 2 0 0 word (A) <-- (AH) or (A) - - - - - * * R - - ORW A,#imm16 3 2 0 0 word (A) <-- (A) or imm16 - - - - - * * R - - ORW A,ear 2 3 1 0 word (A) <-- (A) or (ear) - - - - - * * R - - ORW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) or (eam) - - - - - * * R - - ORW ear,A 2 3 2 0 word (ear) <-- (ear) or (A) - - - - - * * R - - ORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) or (A) - - - - - * * R - * XORW A 1 2 0 0 word (A) <-- (AH) xor (A) - - - - - * * R - - XORW A,#imm16 3 2 0 0 word (A) <-- (A) xor imm16 - - - - - * * R - - XORW A,ear 2 3 1 0 word (A) <-- (A) xor (ear) - - - - - * * R - - XORW A,eam 2+ 4+(a) 0 (c) word (A) <-- (A) xor (eam) - - - - - * * R - - XORW ear,A 2 3 2 0 word (ear) <-- (ear) xor (A) - - - - - * * R - - XORW eam,A 2+ 5+(a) 0 2 x (c) word (eam) <-- (eam) xor (A) - - - - - * * R - * NOTW A 1 2 0 0 word (A) <-- not (A) - - - - - * * R - - NOTW ear 2 3 2 0 word (ear) <-- not (ear) - - - - - * * R - - NOTW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- not (eam) - - - - - * * R - * Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 543 APPENDIX Table B.8-9 6 Logic 2 instructions (long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W ANDL A,ear 2 6 2 0 long (A) <-- (A) and (ear) - - - - - * * R - - ANDL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) and (eam) - - - - - * * R - - ORL A,ear 2 6 2 0 long (A) <-- (A) or (ear) - - - - - * * R - - ORL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) or (eam) - - - - - * * R - - XORL A,ear 2 6 2 0 long (A) <-- (A) xor (ear) - - - - - * * R - - XORL A,eam 2+ 7+(a) 0 (d) long (A) <-- (A) xor (eam) - - - - - * * R - - Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. Table B.8-10 6 Sign inversion instructions (byte, word) Mnemonic # NEG A 1 NEG ear NEG eam NEGW RG B Operation L H A H I S T N Z V C R M W 2 0 0 byte (A) <-- 0 - (A) X - - - - * * * * - 2 3 2 0 byte (ear) <-- 0 - (ear) - - - - - * * * * - 2+ 5+(a) 0 2 x (b) byte (eam) <-- 0 - (eam) - - - - - * * * * * A 1 2 0 0 word (A) <-- 0 - (A) - - - - - * * * * - NEGW ear 2 3 2 0 word (ear) <-- 0 - (ear) - - - - - * * * * - NEGW eam 2+ 5+(a) 0 2 x (c) word (eam) <-- 0 - (eam) - - - - - * * * * * Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. Table B.8-11 1 Normalization instruction (long word) NRML Mnemonic # A,R0 2 *1 RG B 1 0 *1: 4 when all accumulators have a value of 0; otherwise, 6+(R0) 544 Operation long (A) <-- Shifts to the position where '1' is set for the first time. byte (RD) <-- Shift count at that time L H A H I S T N Z V C R M W - - - - - - * - - - APPENDIX B Instructions Table B.8-12 18 Shift instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W RORC A 2 2 0 0 byte (A) <-- With right rotation carry - - - - - * * - * - ROLC A 2 2 0 0 byte (A) <-- With left rotation carry - - - - - * * - * - RORC ear 2 3 2 0 byte (ear) <-- With right rotation carry - - - - - * * - * - RORC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- With right rotation carry - - - - - * * - * * ROLC ear 2 3 2 0 byte (ear) <-- With left rotation carry - - - - - * * - * - ROLC eam 2+ 5+(a) 0 2 x (b) byte (eam) <-- With left rotation carry - - - - - * * - * * ASR A,R0 2 *1 1 0 byte (A) <-- Arithmetic right shift (A, 1 bit) - - - - - * * - * - LSR A,R0 2 *1 1 0 byte (A) <-- Logical right barrel shift (A, R0) - - - - - * * - * - LSL A,R0 2 *1 1 0 byte (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - ASRW A 1 2 0 0 word (A) <-- Arithmetic right shift (A, 1 bit) - - - - * * * - * - LSRW A/SHRW A 1 2 0 0 word (A) <-- Logical right shift (A, 1 bit) - - - - * R * - * - LSLW A/SHLW A 1 2 0 0 word (A) <-- Logical left shift (A, 1 bit) - - - - - * * - * - ASRW A,R0 2 *1 1 0 word (A) <-- Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRW A,R0 2 *1 1 0 word (A) <-- Logical right barrel shift (A, R0) - - - - * * * - * - LSLW A,R0 2 *1 1 0 word (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - ASRL A,R0 2 *2 1 0 long (A) <-- Arithmetic right barrel shift (A, R0) - - - - * * * - * - LSRL A,R0 2 *2 1 0 long (A) <-- Logical right barrel shift (A, R0) - - - - * * * - * - LSLL A,R0 2 *2 1 0 long (A) <-- Logical left barrel shift (A, R0) - - - - - * * - * - *1: 6 when R0 is 0; otherwise, 5 + (R0) *2: 6 when R0 is 0; otherwise, 6 + (R0) Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 545 APPENDIX Table B.8-13 31 Branch 1 instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W BZ/BEQ rel 2 *1 0 0 Branch on (Z) = 1 - - - - - - - - - - BNZ/BNE rel 2 *1 0 0 Branch on (Z) = 0 - - - - - - - - - - BC/BLO rel 2 *1 0 0 Branch on (C) = 1 - - - - - - - - - - BNC/BHS rel 2 *1 0 0 Branch on (C) = 0 - - - - - - - - - - BN rel 2 *1 0 0 Branch on (N) = 1 - - - - - - - - - - BP rel 2 *1 0 0 Branch on (N) = 0 - - - - - - - - - - BV rel 2 *1 0 0 Branch on (V) = 1 - - - - - - - - - - BNV rel 2 *1 0 0 Branch on (V) = 0 - - - - - - - - - - BT rel 2 *1 0 0 Branch on (T) = 1 - - - - - - - - - - BNT rel 2 *1 0 0 Branch on (T) = 0 - - - - - - - - - - BLT rel 2 *1 0 0 Branch on (V) nor (N) = 1 - - - - - - - - - - BGE rel 2 *1 0 0 Branch on (V) nor (N) = 0 - - - - - - - - - - BLE rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 1 - - - - - - - - - - BGT rel 2 *1 0 0 Branch on ((V) xor (N)) or (Z) = 0 - - - - - - - - - - BLS rel 2 *1 0 0 Branch on (C) or (Z) = 1 - - - - - - - - - - BHI rel 2 *1 0 0 Branch on (C) or (Z) = 0 - - - - - - - - - - BRA rel 2 *1 0 0 Unconditional branch - - - - - - - - - - JMP @A 1 2 0 0 word (PC) <-- (A) - - - - - - - - - - JMP addr16 3 3 0 0 word (PC) <-- addr16 - - - - - - - - - - JMP @ear 2 3 1 0 word (PC) <-- (ear) - - - - - - - - - - JMP @eam 2+ 4+(a) 0 (c) word (PC) <-- (eam) - - - - - - - - - - JMPP @ear *3 2 5 2 0 word (PC) <-- (ear), (PCB) <-- (ear+2) - - - - - - - - - - JMPP @eam *3 2+ 6+(a) 0 (d) word (PC) <-- (eam), (PCB) <-- (eam+2) - - - - - - - - - - JMPP addr24 4 4 0 0 word (PC) <-- ad24 0-15, (PCB) <-- ad24 16-23 - - - - - - - - - - CALL @ear *4 2 6 1 (c) word (PC) <-- (ear) CALL addr16 *5 2+ 7+(a) 0 2 x (c) word (PC) <-- (eam) CALL @eam *4 3 6 0 (c) word (PC) <-- addr16 - - - - - - - - - - CALLV #vct4 *5 1 7 0 2 x (c) Vector call instruction - - - - - - - - - - CALLP @ear *6 2 10 2 2 x (c) word (PC) <-- (ear)0-15, (PCB) <-- (ear)16-23 - - - - - - - - - - CALLP @eam *6 2+ 11+(a) 0 *2 - - - - - - - - - - CALLP addr24 *7 4 10 0 2 x (c) word (PC) <-- addr0-15, (PCB) <-- addr16-23 word (PC) <-- (eam)0-15, (PCB) <-- (eam)16-23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - *1: 4 when a branch is made; otherwise, 3 *2: 3 x (c) + (b) *3: Read (word) of branch destination address *4: W: Save to stack (word) R: Read (word) of branch destination address *5: Save to stack (word) *6: W: Save to stack (long word), R: Read (long word) of branch destination address *7: Save to stack (long word) Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 546 APPENDIX B Instructions Table B.8-14 19 Branch 2 instructions Mnemonic # RG B Operation L A H H I S T N Z V C R M W CBNE A,#imm8,rel 3 *1 0 0 Branch on byte (A) not equal to imm8 - - - - - * * * * CWBNE A,#imm16,rel 4 *1 0 0 Branch on word (A) not equal to imm16 - - - - - * * * * - CBNE ear,#imm8,rel 4 *2 1 0 Branch on byte (ear) not equal to imm8 - - - - - * * * * - CBNE eam,#imm8,rel *9 4+ *3 0 (b) Branch on byte (eam) not equal to imm8 - - - - - * * * * - CWBNE ear,#imm16,rel 5 *4 1 0 Branch on word (ear) not equal to imm16 - - - - - * * * * - CWBNE eam,#imm16,rel*9 5+ *3 0 (c) Branch on word (eam) not equal to imm16 - - - - - * * * * - DBNZ ear,rel 3 *5 2 0 Branch on byte (ear) = (ear) - 1, (ear) not equal to 0 - - - - - * * * - - DBNZ eam,rel 3+ *6 2 2 x (b) Branch on byte (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * * - * DWBNZ ear,rel 3 *5 2 0 - - - - - * * * - - DWBNZ eam,rel 3+ *6 2 2 x (c) Branch on word (eam) = (eam) - 1, (eam) not equal to 0 - - - - - * * * - * INT #vct8 2 20 0 8 x (c) Software interrupt - - R S - - - - - - INT addr16 3 16 0 6 x (c) Software interrupt - - R S - - - - - - INTP addr24 Branch on word (ear) = (ear) - 1, (ear) not equal to 0 4 17 0 6 x (c) Software interrupt - - R S - - - - - - INT9 1 20 0 8 x (c) Software interrupt - - R S - - - - - - RETI 1 *8 0 *7 Return from interrupt - - * * * * * * * - 2 6 0 (c) Saves the old frame pointer in the stack upon entering the function, then sets the new frame pointer and reserves the local pointer area. - - - - - - - - - - 1 5 0 (c) Recovers the old frame pointer from the stack upon exiting the function. - - - - - - - - - - LINK #imm8 UNLINK RET *10 1 4 0 (c) Return from subroutine - - - - - - - - - - RETP *11 1 6 0 (d) Return from subroutine - - - - - - - - - - *1: 5 when a branch is made; otherwise, 4 *2: 13 when a branch is made; otherwise, 12 *3: 7+(a) when a branch is made; otherwise, 6+(a) *4: 8 when a branch is made; otherwise, 7 *5: 7 when a branch is made; otherwise, 6 *6: 8+(a) when a branch is made; otherwise, 7+(a) *7: 3 x (b) + 2 x (c) when jumping to the next interruption request; 6 x (c) when returning from the current interruption *8: 15 when jumping to the next interruption request; 17 when returning from the current interruption *9: Do not use RWj+ addressing mode with a CBNE or CWBNE instruction. *10: Return from stack (word) *11: Return from stack (long word) Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 547 APPENDIX Table B.8-15 28 Other control instructions (byte, word, long word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W PUSHW A 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (A) - - - - - - - - - - PUSHW AH 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (AH) - - - - - - - - - - PUSHW PS 1 4 0 (c) word (SP) <-- (SP) - 2, ((SP)) <-- (PS) - - - - - - - - - - PUSHW rlst 2 *3 *5 *4 (SP) <-- (SP) - 2n, ((SP)) <-- (rlst) - - - - - - - - - - POPW A 1 3 0 (c) word (A) <-- ((SP)), (SP) <-- (SP) + 2 - * - - - - - - - - POPW AH 1 3 0 (c) word (AH) <-- ((SP)), (SP) <-- (SP) + 2 - - - - - - - - - - POPW PS 1 4 0 (c) word (PS) <-- ((SP)), (SP) <-- (SP) + 2 - - * * * * * * * - POPW rlst 2 *2 *5 *4 (rlst) <-- ((SP)), (SP) <-- (SP) - - - - - - - - - - JCTX @A 1 14 0 6 x (c) Context switch instruction - - * * * * * * * - AND CCR,#imm8 2 3 0 0 byte (CCR) <-- (CCR) and imm8 - - * * * * * * * - OR CCR,#imm8 2 3 0 0 byte (CCR) <-- (CCR) or imm8 - - * * * * * * * - MOV RP,#imm8 2 2 0 0 byte (RP) <-- imm8 - - - - - - - - - - MOV ILM,#imm8 2 2 0 0 byte (ILM) <-- imm8 - - - - - - - - - - MOVEA RWi,ear 2 3 1 0 word (RWi) <-- ear - - - - - - - - - - MOVEA RWi,eam 2+ 2+(a) 1 0 word (RWi) <-- eam - - - - - - - - - - MOVEA A,ear 2 1 0 0 word (A) <-- ear - * - - - - - - - - MOVEA A,eam 2+ 1+(a) 0 0 word (A) <-- eam - * - - - - - - - - ADDSP #imm8 2 3 0 0 word (SP) <-- ext(imm8) - - - - - - - - - - ADDSP #imm16 3 3 0 0 word (SP) <-- imm16 - - - - - - - - - - MOV A,brg1 2 *1 0 0 byte (A) <-- (brg1) Z * - - - * * - - - MOV brg2,A 2 1 0 0 byte (brg2) <-- (A) - - - - - * * - - - NOP 1 1 0 0 No operation - - - - - - - - - - ADB 1 1 0 0 Prefix code for AD space access - - - - - - - - - - DTB 1 1 0 0 Prefix code for DT space access - - - - - - - - - - PCB 1 1 0 0 Prefix code for PC space access - - - - - - - - - - SPB 1 1 0 0 Prefix code for SP space access - - - - - - - - - - NCC 1 1 0 0 Prefix code for flag no-change - - - - - - - - - - CMR 1 1 0 0 Prefix code for common register bank - - - - - - - - - - *1: PCB, ADB, SSB, USB, SPB: 1 DTB, DPR: 2 *2: 7 + 3 x (POP count) + 2 x (POP last register number), 7 when RLST = 0 (no transfer register) *3: 29 + 3 x (PUSH count) - 3 x (PUSH last register number), 8 when RLST = 0 (no transfer register) *4: (POP count) x (c) or (PUSH count) x (c) *5: (POP count) or (PUSH count) Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 548 APPENDIX B Instructions Table B.8-16 21 Bit operand instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W MOVB A,dir:bp 3 5 0 (b) byte (A) <-- (dir:bp)b Z * - - - * * - - - MOVB A,addr16:bp 4 5 0 (b) byte (A) <-- (addr16:bp)b Z * - - - * * - - - MOVB A,io:bp 3 4 0 (b) byte (A) <-- (io:bp)b Z * - - - * * - - - MOVB dir:bp,A 3 7 0 2 x (b) bit (dir:bp)b <-- (A) - - - - - * * - - * MOVB addr16:bp,A 4 7 0 2 x (b) bit (addr16:bp)b <-- (A) - - - - - * * - - * MOVB io:bp,A 3 6 0 2 x (b) bit (io:bp)b <-- (A) - - - - - * * - - * SETB dir:bp 3 7 0 2 x (b) bit (dir:bp)b <-- 1 - - - - - - - - - * SETB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b <-- 1 - - - - - - - - - * SETB io:bp 3 7 0 2 x (b) bit (io:bp)b <-- 1 - - - - - - - - - * CLRB dir:bp 3 7 0 2 x (b) bit (dir:bp)b <-- 0 - - - - - - - - - * CLRB addr16:bp 4 7 0 2 x (b) bit (addr16:bp)b <-- 0 - - - - - - - - - * CLRB io:bp 3 7 0 2 x (b) bit (io:bp)b <-- 0 - - - - - - - - - * BBC dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 0 - - - - - - * - - - BBC addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 0 - - - - - - * - - - BBC io:bp,rel 4 *2 0 (b) Branch on (io:bp) b = 0 - - - - - - * - - - BBS dir:bp,rel 4 *1 0 (b) Branch on (dir:bp) b = 1 - - - - - - * - - - BBS addr16:bp,rel 5 *1 0 (b) Branch on (addr16:bp) b = 1 - - - - - - * - - - BBS io:bp,rel 4 *1 0 (b) Branch on (io:bp) b = 1 - - - - - - * - - - SBBS addr16:bp,rel 5 *3 0 2 x (b) Branch on (addr16:bp) b = 1, bit = 1 - - - - - - * - - * WBTS io:bp 3 *4 0 *5 Waits until (io:bp) b = 1 - - - - - - - - - - WBTC io:bp 3 *4 0 *5 Waits until (io:bp) b = 0 - - - - - - - - - - *1: 8 when a branch is made; otherwise, 7 *2: 7 when a branch is made; otherwise, 6 *3: 10 when the condition is met; otherwise, 9 *4: Undefined count *5: Until the condition is met Note: See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. Table B.8-17 6 Accumulator operation instructions (byte, word) Mnemonic # RG B Operation L H A H I S T N Z V C R M W SWAP 1 3 0 0 byte (A)0-7 <--> (A)8-15 - - - - - - - - - - SWAPW / XCHW A,T 1 2 0 0 word (AH) <--> (AL) - * - - - - - - - - EXT 1 1 0 0 Byte sign extension X - - - - * * - - - EXTW 1 2 0 0 Word sign extension - X - - - * * - - - ZEXT 1 1 0 0 Byte zero extension Z - - - - R * - - - ZEXTW 1 1 0 0 Word zero extension - z - - - R * - - - 549 APPENDIX Table B.8-18 10 String instructions Mnemonic # RG B Operation L H A H I S T N Z V C R M W MOVS / MOVSI 2 *2 *5 *3 byte transfer @AH+ <-- @AL+, counter = RW0 - - - - - - - - - - MOVSD 2 *2 *5 *3 byte transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCEQ / SCEQI 2 *1 *5 *4 byte search @AH+ <-- AL, counter RW0 - - - - - * * * * - SCEQD 2 *1 *5 *4 byte search @AH- <-- AL, counter RW0 - - - - - * * * * - FILS / FILSI 2 6m+6 *5 *3 byte fill @AH+ <-- AL, counter RW0 - - - - - * * - - - MOVSW / MOVSWI 2 *2 *5 *6 word transfer @AH+ <-- @AL+, counter = RW0 - - - - - - - - - - MOVSWD 2 *2 *5 *6 word transfer @AH- <-- @AL-, counter = RW0 - - - - - - - - - - SCWEQ / SCWEQI 2 *1 *5 *7 word search @AH+ - AL, counter = RW0 - - - - - * * * * - SCWEQD 2 *1 *5 *7 word search @AH- - AL, counter = RW0 - - - - - * * * * - FILSW / FILSWI 2 6m+6 *5 *6 word fill @AH+ <-- AL, counter = RW0 - - - - - * * - - - *1: 5 when RW0 is 0, 4 + 7 x (RW0) when the counter expires, or 7n + 5 when a match occurs *2: 5 when RW0 is 0; otherwise, 4 + 8 x (RW0) *3: (b) x (RW0) + (b) x (RW0) When the source and destination access different areas, calculate the (b) item individually. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) When the source and destination access different areas, calculate the (c) item individually. *7: (c) x n Note: m: RW0 value (counter value), n: Loop count See Table B.5-1 "Execution cycle counts in each addressing mode" and Table B.5-2 "Cycle count correction values for counting execution cycles" for information on (a) to (d) in the table. 550 APPENDIX B Instructions B.9 Instruction Map Each F2MC-16LX instruction code consists of 1 or 2 bytes. Therefore, the instruction map consists of multiple pages. Table B.9-2 "Basic page map" to Table B.9-21 "XCHW RWi, ea instruction (first byte = 7FH)" summarize the F2MC-16LX instruction map. ■ Structure of Instruction Map Figure B.9-1 Structure of instruction map Basic page map : Byte 1 Bit operation instructions Character string operation instructions 2-byte instructions ea instructions x 9 : Byte 2 An instruction such as the NOP instruction that ends in one byte is completed within the basic page. An instruction such as the MOVS instruction that requires two bytes recognizes the existence of byte 2 when it references byte 1, and can check the following one byte by referencing the map for byte 2. Figure B.9-2 "Correspondence between actual instruction code and instruction map" shows the correspondence between an actual instruction code and instruction map. 551 APPENDIX Figure B.9-2 Correspondence between actual instruction code and instruction map Some instructions do not contain byte 2. Length varies depending on the instruction. Instruction code Byte 1 Byte 2 Operand Operand ... [Basic page map] XY +Z [Extended page map] (*1) UV +W *1 The extended page map is a generic name of maps for bit operation instructions, character string operation instructions, 2-byte instructions, and ea instructions. Actually, there are multiple extended page maps for each type of instructions. An example of an instruction code is shown in Table B.9-1 "Example of an instruction code". Table B.9-1 Example of an instruction code Byte 1 (from basic page map) Byte 2 (from extended page map) NOP 00 +0=00 - AND A, #8 30 +4=34 - MOV A, ADB 60 +F=6F 00 +0=00 @RW2+d8, #8rel 70 +0=70 F0 +2=F2 Instruction 552 2-byte instruction Character string operation instruction Bit operation instruction Ri,ea ea instruction 9 ea instruction 8 ea instruction 7 ea instruction 6 ea instruction 5 ea instruction 4 ea instruction 3 ea instruction 2 ea instruction 1 APPENDIX B Instructions Table B.9-2 Basic page map 553 APPENDIX Table B.9-3 Bit operation instruction map (first byte = 6CH) 554 APPENDIX B Instructions Table B.9-4 Character string operation instruction map (first byte = 6EH) 555 APPENDIX 556 A A DIVU MULW MUL A Table B.9-5 2-byte instruction map (first byte = 6FH) Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited Use prohibited APPENDIX B Instructions Table B.9-6 ea instruction 1 (first byte = 70H) 557 APPENDIX Table B.9-7 ea instruction 2 (first byte = 71H) 558 APPENDIX B Instructions Table B.9-8 ea instruction 3 (first byte = 72H) 559 APPENDIX Table B.9-9 ea instruction 4 (first byte = 73H) 560 APPENDIX B Instructions Table B.9-10 ea instruction 5 (first byte = 74H) 561 APPENDIX Table B.9-11 ea instruction 6 (first byte = 75H) 562 APPENDIX B Instructions Table B.9-12 ea instruction 7 (first byte = 76H) 563 APPENDIX Table B.9-13 ea instruction 8 (first byte = 77H) 564 APPENDIX B Instructions Table B.9-14 ea instruction 9 (first byte = 78H) 565 APPENDIX Table B.9-15 MOVEA RWi, ea instruction (first byte = 79H) 566 APPENDIX B Instructions Table B.9-16 MOV Ri, ea instruction (first byte = 7AH) 567 APPENDIX Table B.9-17 MOVW RWi, ea instruction (first byte = 7BH) 568 APPENDIX B Instructions Table B.9-18 MOV ea, Ri instruction (first byte = 7CH) 569 APPENDIX Table B.9-19 MOVW ea, Rwi instruction (first byte = 7DH) 570 APPENDIX B Instructions Table B.9-20 XCH Ri, ea instruction (first byte = 7EH) 571 APPENDIX Table B.9-21 XCHW RWi, ea instruction (first byte = 7FH) 572 INDEX The index follows on the next page. This is listed in alphabetic order. 573 INDEX Index Symbols #microDMA start in continuous mode, example of ................................................................... 370 #microDMA start in single mode, example of....... 368 #microDMA start in stop mode, example of ......... 372 #microDMA, conversion operation using.............. 367 #microPG timer register, configuration of............. 305 #microPG timer, block diagram of ........................ 304 #microPG timer, timing chart of............................ 307 Numerics 16-bit free-running timer register, list of................ 227 16-bit free-running timer, block diagram of........... 228 16-bit free-running timer, operation of .................. 240 16-bit input/output timer register, configuration of ................................................................... 226 16-bit input/output timer, configuration and function of ................................................................... 224 16-bit input/output timer, operation and timing of ................................................................... 239 16-bit reload register (TMRLR)..................... 319, 320 16-bit reload register, setting of............................ 321 16-bit reload timer, block diagram of.................... 313 16-bit reload timer, operation mode of ................. 311 16-bit reload timer, outline of................................ 310 16-bit timer register (TMR) ................................... 319 16-bit timer register (TMR)/16-bit reload register (TMRLR) .................................................... 319 2M bit flash memory, feature of............................ 470 8/10-bit A/D converter, block diagram of.............. 357 8/10-bit A/D converter, feature of .........................356 8/10-bit A/D converter, register of ........................ 358 8/16-bit PPG timer operation, outline of ............... 342 8/16-bit PPG timer specification, outline of .......... 330 8/16-bit PPG timer, block diagram of ...................331 8/16-bit PPG timer, Interrupt of ............................ 345 8/16-bit up/down counter/timer register, list of ..... 253 8/16-bit up/down counter/timer, block diagram of ................................................................... 251 8/16-bit up/down counter/timer, major function of ................................................................... 250 A access mode ........................................................ 158 accumulator (A) ...................................................... 29 574 acknowledge ........................................................ 437 address field, effective ................................. 518, 533 address generation type ........................................ 23 address register (IADR) ....................................... 434 addressing ................................................... 436, 517 addressing type by bank ........................................ 24 addressing, direct................................................. 519 addressing, indirect.............................................. 524 analog input enable register (ADER) ................... 188 analog input pin, handling of ................................ 376 arbitration ............................................................. 436 asynchronous mode (operation modes 0 and 1), operation in ................................................ 410 automatic algorithm.............................................. 474 automatic ready function selection register (ARSR) ................................................................... 166 B bank select prefix ................................................... 38 basic configuration ............................................... 494 block diagram............................................... 164, 225 block diagram of MB90470 ...................................... 5 buffer address pointer (BAP) ................................. 77 buffer address pointer register (BAP) .................... 87 bus control register (IBCR) .................................. 429 bus control register (IBCR), note on using........... 431 bus control signal selection register (EPCR) ....... 169 bus error............................................................... 437 bus mode ............................................................. 158 bus mode setting bit (M1, M0) ............................. 161 bus status register (IBSR).................................... 427 C calculating execution cycle count......................... 531 capture timing to input signal ............................... 247 chip selection area MASK register (CMRx) ......... 442 chip selection area register (CARx) ..................... 443 chip selection control register (CSCR)................. 444 chip selection facility, block diagram of................ 440 chip selection facility, example of using ............... 446 chip selection facility, feature of ........................... 440 chip selection facility, list of register used for....... 441 chip selection facility, note on using..................... 447 chip selector active level register (CALR) ............ 445 INDEX chip/sector sector erase operation....................... 478 clearing counter ................................................... 270 clearing timer ....................................................... 292 clock control register (ICCR) ................................ 432 clock generator, block diagram of, ....................... 116 clock mode........................................................... 129 clock mode, change of ......................................... 121 clock selection register (CKSCR), configuration of ................................................................... 118 clock supply map ................................................. 115 clock supplying function ............................... 191, 198 clock, overview of................................................. 114 command sequence table.................................... 475 common register bank prefix (CMR) ...................... 39 communication prescaler control register (CDCR) ................................................................... 404 compare clear register (CPCLR).......................... 228 compare function ................................................. 268 compare register (OCCP0 to 5) ........................... 233 conditioncode register (CCR)................................. 31 configuration of extended intelligent I/O service (El2OS) descriptor (ISD) .............................. 83 configuration of interrupt control register (ICR)...... 52 continuous prefix code ........................................... 40 control register (OCS0 to 5) ................................. 234 control status register (FMCS) ............................. 472 control status register (ICS01) ............................. 238 control status register 1 (ADCS1) ........................ 359 control status register 2 (ADCS2) ........................ 362 conversion data protection function ..................... 374 conversion data protection function operation (when DMAC is used), operation flow of .............. 375 conversion data protection function, caution when using................................................. 374 count clear/gate function...................................... 270 count clock ........................................................... 293 count clock selection............................................ 288 count clock, selection of....................................... 344 count direction flag............................................... 271 count direction reversal flag ................................. 271 count mode, selection of ...................................... 264 counter control register H0 (CCRH0) ................... 254 counter control register H1 (CCRH1) ................... 256 counter control register L0/1 (CCRL0/1) .............. 258 counter operation ................................................. 296 counter operation mode ....................................... 312 counter status register 0/1 (CSR0/1) ................... 260 counting pulse width/interval, range for ............... 299 CPU intermittent operation mode................. 129, 136 CPU operation mode ............................................128 CPU specification ...................................................22 current consumption .............................................128 cycle count, execution ..........................................530 D data count register (DCT) .......................................85 data counter (DCT).................................................75 data polling flag (DQ7), state transitions of ..........478 data register (ADCR2 and ADCR1)......................365 data register (IDAR)..............................................435 dedicated prescaler control register (SDCR)........385 dedicated register ...................................................27 delay interrupt event module, block diagram of......99 delay interrupt event module, list of register in .......99 delay interrupt event module, note on using.........100 delay interrupt event module, operation of ...........100 different mode (S1, S0), setting bit of ...................160 direct addressing ..................................................519 direct page register (DPR)......................................36 divide ratio control register (DIVR0 to DIVR2) ......283 DMA control status register (DMACS)....................76 DMA descriptor.......................................................73 DMA processing procedure ....................................78 DQ3 ......................................................................482 DQ5 ......................................................................481 DQ6 ......................................................................480 DQ7 ......................................................................478 DTP operation ......................................................352 DTP/external interrupt unit operation, procedure for ...................................................................353 DTP/external interrupt unit, block diagram of .......348 DTP/external interrupt unit, list of register ............349 DTP/external interrupt unit, overview of ...............348 E effective address field...................................518, 533 enable interrupt request register...........................349 end timing of automatic algorithm.........................474 erasing all data in flash memory (chip erase).......487 erasing arbitrary data in flash memory (sector erase) ...................................................................488 event count mode .................................................327 event count mode (external clock mode)..............311 executing undefined instruction, exception processing interrupt by .................................93 execution cycle count ...........................................530 execution cycle count, calculating ........................531 expanded I/O serial interface, block diagram of ...378 575 INDEX expanded I/O serial interface, interrupt function of ................................................................... 392 expanded I/O serial interface, overview of ........... 378 expanded I/O serial interface, overview of operation of ................................................................386 expanded I/O serial interface, register of ............. 379 extended intelligent I/O service (EI2OS)................. 81 extended intelligent I/O service (EI2OS) (time for each transfer), processing time for.............. 90 extended intelligent I/O service (EI2OS) status register (ISCS) ............................................. 86 extended intelligent I/O service (EI2OS), processing procedure of .............................. 88 extended intelligent I/O service (EI2OS), processing specification of sample program for .................................................. 97 extended intelligent I/O service (EI2OS), setting procedure of ..................................... 89 external address output control register (HACR) ................................................................... 168 external bus 16-bit data bus mode, pin state in ........................................................... 149, 151 external bus 8-bit data bus mode .........................150 external bus 8-bit data bus mode, pin state in ..... 152 external connection of peripheral device, conditions for.............................................. 353 external interrupt request level ............................. 354 external interrupt request register ........................ 350 external interrupt unit, operation of ...................... 351 external level register ........................................... 350 external memory access control signal ................ 172 external memory access, I/O signal pin for .......... 164 external pin in each mode, operation of ............... 163 external shift clock mode......................................387 external trigger ..................................................... 376 external-reset pin, block diagram of ..................... 106 F F2MC-16LX instruction list.................................... 537 flag change suppress prefix ................................... 39 flash memory control status register (FMCS)....... 470 flash memory to the read/reset state, setting ....... 484 flash memory write/erase ..................................... 483 flash memory, operation for writing to .................. 486 flash memory, resuming sector erasure of ........... 491 flash memory, suspending sector erasure for ......490 flash memory, writing data to ............................... 485 flash microcomputer programmer (using power from user system), example of minimum connection ................................................................... 501 576 flash microcomputer programmer, system configuration of .......................................... 497 free-running timer (match with compare register 0), clear timing of ............................................ 245 free-running timer, count timing of ....................... 245 fujitsu standard serial onboard writing, pin use for ................................................................... 495 function selection ................................................. 418 G general-purpose register........................................ 28 general-purpose register (register bank)................ 37 H handling device, note on ........................................ 19 hardware component, initial value ....................... 346 hardware interrupt function .................................... 55 hardware interrupt operation.................................. 59 hardware interrupt operation flow .......................... 60 hardware interrupt processing time........................ 65 hardware interrupt, configuration of ....................... 56 hardware interrupt, procedure for using................. 61 hardware interrupt, return from .............................. 58 hardware interrupt, starting .................................... 58 hardware interrupt, suppressing ............................ 56 hardware sequence flag....................................... 476 hold function, operation of.................................... 178 I I/O circuit type ........................................................ 16 I/O map ................................................................ 506 I/O port, function of .............................................. 182 I/O port, register for.............................................. 183 I/O register address pointer (IOA).......................... 75 I/O register address pointer register (I/OA)............ 85 I2C interface function ........................................... 424 I2C interface register, list of.................................. 426 I2C interface, block diagram of............................. 425 indirect addressing............................................... 524 input capture ........................................................ 236 input capture data register (IPCP0, 1) ................. 237 input capture register, list of................................. 237 input capture timing, example of .......................... 244 input capture, block diagram of............................ 236 input pin, selection of ........................................... 296 input resistor register (RDR0, ROR1) .................. 187 input/output timing................................................ 390 instruction map, structure of................................. 551 INDEX instruction presentation item and symbol, description of ............................................. 534 instruction type..................................................... 516 internal clock mode .............................................. 311 internal clock mode (one-shot mode), operation of ................................................................... 325 internal clock mode (reload mode), operation of ................................................................... 323 internal shift clock mode ...................................... 387 internal trigger ...................................................... 376 interrupt control register ................................. 45, 513 interrupt control register (ICR00 to ICR15) function ..................................................................... 49 interrupt control register (ICR00 to ICR15), configuration of ............................................ 49 interrupt control register (ICR00 to ICR15), function of each bit in .................................................... 53 interrupt control register function ........................... 48 interrupt control register, list of............................... 47 interrupt control registers (ICR).............................. 52 interrupt factor........................................................ 45 interrupt generation request................................. 292 interrupt level mask register (ILM) ......................... 33 interrupt operation.................................................. 43 interrupt processing, sample program for .............. 96 interrupt request, generation of............................ 299 interrupt source .................................................... 513 interrupt suppress iinstruction ................................ 40 interrupt suppress instruction................................. 40 interrupt timing ..................................................... 246 interrupt vector ......................................... 44, 45, 513 interrupt, change to .............................................. 153 interrupt, type and function of, ............................... 42 interrupt/DTP enable register............................... 349 interrupt/DTP source register............................... 350 interval timer function........................................... 190 interval timer function (timebase timer), operation of ................................................................... 197 L low-power consumption mode control register (LPMCR)................................................... 133 low-power consumption mode control register, accessing................................................... 135 low-power consumption mode, operational state in ................................................................... 147 low-power control circuit, block diagram of .......... 131 M machine clock ...................................................... 122 main clock mode...................................................121 master/slave communication function, communication procedure of ......................418 master/slave communication, connection between CPUs in ......................................................418 master/slave communication, register setting in...417 maximum interval .................................................293 MB90470 feature ......................................................2 measurement mode..............................................296 measurement result data......................................295 measurement start, operation after ......................290 memory map...........................................................23 memory space ......................................................504 microDMA.............................................................196 microDMA function .................................................69 microDMA operation...............................................72 microDMA processing time (time per one-time transfer) ..........................79 microDMA register, list of .......................................70 microPG timer.......................................................307 minimum input pulse width ...................................298 mode data.....................................................160, 162 mode fetch............................................................108 mode pin.......................................................107, 162 mode pin (MD2 to MD0), setting of.......................159 mode setting .........................................................158 mode, type of........................................................171 multi-byte length in memory space, allocation of data of ......................................26 multi-byte length, access to data of ........................26 multiple interrupt operation .....................................63 multiple interrupt, example of .................................63 multiplex 8-bit external bus mode.........................150 multiplex mode .....................................................179 N non-multiplex 16-bit external bus mode, pin state in ...................................................................151 non-multiplex 8-bit external bus mode, pin state in ...................................................................152 non-multiplex mode ..............................................179 note on handling the power supply.........................20 Notes on accessing the low-power consumption made control register (LPMCR)..................155 O one-shot measurement.........................................295 one-shot mode. operation in.................................328 one-shot operation mode......................................292 577 INDEX operation mode ............................ 158, 342, 366, 406 operation mode, selection of ................................ 288 operation of extended intelligent I/O service (EI2OS) ..................................................................... 82 operation state, confirmation of............................ 291 operation, outline of.............................................. 446 opscillator and external clock, connection of........ 126 oscillation clock frequency ................................... 496 oscillation stabilization wait time........... 104, 125, 154 oscillation stabilization wait time, timer function for ................................................................... 197 other consideration............................................... 437 output compare register, list of ............................. 232 output compare, block diagram of ........................ 233 output pin register (ODR7, ODR4) ....................... 187 output pin, change timing of ................................. 246 output waveform, examples of ............................. 242 P package dimension (LQFP-100) .............................. 6 package dimension (QFP-100) ................................ 7 PG control/status register (PGCSR)..................... 305 pin assignment diagram (LQFP-100) .......................9 pin assignment diagram (QFP-100) ......................... 8 pin function............................................................. 10 pin output control of pulse .................................... 344 pin state................................................................150 pin state after mode data is read.......................... 111 pin state during reset............................................111 PLL clock mode.................................................... 121 PLL clock multiplication rate, selection of............. 122 Port direction register (DRR0 to DRRA)............... 185 port register (PDR0 to PDRA) .............................. 184 PPG output operation........................................... 343 PPG0 to PPG5 output control register (PPG0/1,PPG2/3,PPG4/5) .........................339 PPG0/2/4 operation mode control register (PPGC0) ................................................................... 334 PPG1/3/5 operation mode control register (PPGC1) ................................................................... 336 prefix instruction ..................................................... 40 processor status (PS)............................................. 31 product configuration................................................4 program count bank register (PCB)........................ 35 program counter (PC) ............................................ 34 pulse width ........................................................... 344 pulse width measurement function, operation of ................................................................... 286 pulse width measurement, operational flow of ..... 299 578 pulse width/interval calculation method ............... 298 PWC control/status register (PWCSR0 to PWCSR2) ................................................................... 277 PWC data buffer register (PWCR0 to PWCR 2) .. 282 PWC Timer function............................................. 274 PWC timer operation, outline of ........................... 284 PWC timer register, list of .................................... 276 PWC timer usage, note on................................... 301 PWC timer, block diagram of ............................... 275 R ready function ...................................................... 175 register bank pointer (RP)...................................... 32 register, list of............................................... 165, 314 reload and compare function ............................... 267 reload function ..................................................... 267 reload mode ......................................................... 323 reload operation mode ......................................... 292 reload register ...................................................... 341 reload register, write timing to.............................. 346 reload value ................................................. 292, 344 reload/compare register 0/1 (RCR0/1)................. 263 repeated measurement........................................ 295 request level setting register ................................ 350 reset factor ........................................... 102, 104, 110 reset state waiting for stable oscillation ............... 105 reset-factor bit .............................................. 109, 110 restart................................................................... 291 restting, overview of ............................................. 107 ROM mirror function selection module................. 466 ROM mirror function selection module, block diagram of ........................................ 466 ROM mirror function selection module, register of ................................................................... 466 ROMM (ROM mirror function select register) ...... 467 S sector configuration.............................................. 471 sector delete timer flag (DQ3), state transitions of ................................................................... 482 sector erase operation ......................................... 482 sector erase suspend........................... 479, 480, 482 sector erasure, procedure for............................... 488 serial clock input frequency.................................. 496 serial control register (SCR)................................. 399 serial data transfer, operation during ................... 391 serial I/O unit, operational states of ..................... 388 serial input/output register (SIDR/SODR) ............ 401 serial mode control status register (SMCS) ......... 380 INDEX serial mode register (SMR) .................................. 397 serial programming connection, example of ........ 498 serial shift data register (SDR)............................. 384 serial status register (SSR) .................................. 402 shift operation ...................................................... 390 single chip mode, pin state in............................... 148 single-chip mode (using power from user system), example of connection in ........................... 499 sleep mode, canceling ......................................... 139 sleep mode, change to......................................... 138 software interrupt operation ................................... 68 software interrupt, note on ..................................... 68 software interrupt, return from................................ 67 software interrupt, start of ...................................... 67 stack area .............................................................. 95 stack operation during return from interrupt processing ................................................... 95 stack operation when interrupt processing start .... 94 standby mode ...................................................... 129 standby mode by interrupt, cancellation of .......... 153 standby mode, change to..................................... 153 standby mode, operational states in .................... 137 start condition....................................................... 436 start/stop timing.................................................... 390 state transition diagram........................................ 146 state transitions during counter operation............ 322 stop ...................................................................... 291 stop condition....................................................... 436 stop mode, canceling ........................................... 144 stop mode, change to .......................................... 144 STP, SLP, and TMD bit, priority of....................... 135 structure of instruction map.................................. 551 sub-clock mode.................................................... 121 sub-clock stable oscillation wait function ............. 221 switching clock mode ................................... 154, 155 synchronous mode (operation mode 2), operation in ................................................................... 413 system stack pointer (SSP).................................... 30 T timebase timer control register (TBTC)................ 194 timebase timer interrupt ....................................... 196 timebase timer mode, canceling .......................... 140 timebase timer mode, change to.......................... 140 timebase timer, block diagram of ......................... 192 timebase timer, notes on using ............................ 199 timebase timer, operation of ................................ 200 timebase timer, sample program of ..................... 201 timer control status register (TMCSR) ................. 315 timer counter control status register (TCCS) ........229 timer counter data register (TCDT).......................229 timer function, operation of ...................................285 timer interval .........................................................293 timer operation flow ..............................................294 timer value ............................................................292 timer/pulse width measurement, start and stop of ...................................................................290 timing limit excess flag (DQ5), state transition of ...................................................................481 timing, note on ......................................................307 toggle bit flag (DQ6), state transition of ................480 two-way communication function, communication procedure for ..............................................416 two-way communication, connection between CPU in ...................................................................415 two-way communication, register setting in..........415 type of instruction .................................................516 U UART block diagram ............................................395 UART clock selection ...........................................407 UART feature........................................................394 UART program example.......................................421 UART register, list of ............................................396 UART, precautions on using.................................420 up/down count at any width ..................................268 up/down count register 0/1 (UDCR0/1) ................262 up/down timer input enable register (UDER)........188 user stack pointer (USP) ........................................30 W wacth counter .......................................................220 watch mode, canceling .........................................142 watch mode, change to ........................................142 watch timer control register (WTC), configuration of ...................................................................218 watch timer, block diagram of...............................217 watch timer, function of.........................................216 watch timer, interval interrupt function of..............220 watchdog timer control register (WDTC) ..............206 watchdog timer specifying function, clock source for ...................................................................220 watchdog timer, block diagram of.........................208 watchdog timer, function of...................................204 watchdog timer, note on using..............................212 watchdog timer, operation of ................................210 watchdog timer, sample program for ....................213 write operation ......................................................478 579 INDEX write/chip sector erase operation .................480, 481 writing data to UDCR ........................................... 270 580 writing/erasing flash memory, methods for .......... 470 CM44-10115-3E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL F2MC-16LX 16-BIT MICROCONTROLLER MB90470 Series HARDWARE MANUAL July 2003 the third edition Published FUJITSU LIMITED Edited Business Promotion Dept. Electronic Devices