HT9B92 RAM Mapping 36×4 LCD Driver Feature Applications • Logic Operating Voltage: 2.4V~5.5V • Leisure products • Integrated oscillator circuitry • Games • Bias: 1/2 or 1/3; Duty: 1/4 • Telephone display • Internal LCD bias generation with voltage-follower buffers • Audio Combo display • External VLCD pin to supply LCD operating voltage • Kitchen Appliance display • Video Player display • Support I2C-bus serial interface • Measurement equipment display • Selectable LCD Frame Frequencies • Household appliance • Up to 36×4 bits RAM for display data storage • Consumer electronics • Maximum Display patterns: 36×4 patterns - 36 segments and 4 commons General Description • Versatile blinking modes: off, 0.5Hz, 1Hz, 2Hz The HT9B92 device is a memory mapping and multi-function LCD controller driver. The maximum display segments of the device are 144 patterns (36 segments and 4 commons) display. The software configuration feature of the HT9B92 device makes it suitable for multiple LCD applications including LCD modules and display subsystems. The HT9B92 device communicates with most microprocessors/ microcontrollers via a two-wire bidirectional I2C-bus interface. • Write address auto-increment • Support Power Save Mode for low power consumption • Manufactured in silicon gate CMOS process • Package Types: 48-pin TSSOP/LQFP Rev. 1.10 1 December 12, 2014 HT9B92 Block Diagram TEST2 Power_on reset VSS SEG0 SDA SCL 8 Display RAM I2C Controller Segment driver output OSCIN Internal Oscillator Timing generator SEG35 VDD COM0 - OP1 + LCD Voltage Selector Column driver output COM3 - OP0 + VLCD LCD bias generator TEST1 Rev. 1.10 2 December 12, 2014 HT9B92 Pin Assignment 48 2 47 3 46 4 45 5 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 36 35 34 33 32 31 30 29 28 27 26 25 24 37 23 38 22 39 21 40 20 41 HT9B92 19 42 48 LQFP-A 18 43 44 17 16 45 15 46 14 47 13 48 1 2 3 4 5 6 7 8 9 10 11 12 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 TEST2 SDA SCL OSCIN TEST1 VSS VDD VLCD COM3 COM2 COM1 COM0 SEG35 SEG34 SEG33 SEG32 SEG31 1 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 SEG31 SEG32 SEG33 SEG34 SEG35 COM0 COM1 COM2 COM3 VLCD VDD VSS TEST1 OSCIN SCL SDA TEST2 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 HT9B92 48 TSSOP-A Pin Description Pin Name Type Description Serial Data Input/Output pin Serial Data (SDA) Input/Output for 2-wire I2C interface is an NMOS open drain structure SDA I/O SCL I Serial Clock Input pin Serial Data (SCL) is a clock input for 2-wire I2C interface OSCIN I External Clock Input pin The external and internal clock mode can be selected by the command. When the internal oscillator circuitry is used, this pin must be connected to VSS TEST1 I Test mode input pin When this pin is connected to VDD, the device will enter the test mode TEST2 I Power on reset control pin The internal power on reset circuitry will be enabled if this pin is connected to VSS. If this pin is connected to VDD, the internal power on reset circuitry will be disabled and the reset function will be performed by executing the software reset command COM0~COM3 O LCD Common outputs SEG0~SEG35 O LCD Segment outputs VDD — Positive power supply VSS — Negative power supply, ground VLCD — LCD power supply pin Rev. 1.10 3 December 12, 2014 HT9B92 Approximate Internal Connections SCL, SDA (for Schmitt trigger type) COM0~COM3; SEG0~SEG35 VDD OSCIN VDD VLCD VSS VLCD VSS VSS VSS TEST1, TEST2 VDD VSS Absolute Maximum Ratings SupplyVoltage .......................... VSS-0.3V to VDD+6.5V Storage Temperature ........................... -55°C to 150°C Input Voltage ............................ VSS-0.3V to VDD+0.3V Operating Temperature.......................... -40°C to 85°C Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Rev. 1.10 4 December 12, 2014 HT9B92 D.C. Characteristics Symbol Parameter VSS=0V; VDD=2.4V~5.5V; Ta=-40 to +85°C Test Condition VDD Condition Min. Typ. Max. Unit VDD Operating Voltage — — 2.4 — 5.5 V VLCD LCD operating voltage — — 0 — VDD-2.4 V VIH Input high Voltage — SCL, SDA, TEST1, TEST2 0.7VDD — VDD V VIL Input low Voltage — SCL, SDA, TEST1, TEST2 0 — 0.3VDD V IIL Input leakage current — VIN=VSS or VDD -1 — 1 μA IOL Low level output current 6 — — mA 9 — — mA — 7.5 15 μA — 12 20 μA 3.3V No load, 1/3bias, B type inversion, Ta=25°C, LCD display off, fLCD=80Hz, VLCD pin is connected to VSS, 5.0V Power save mode=Low Current2 mode — — 1 μA — — 2 μA 3.3V 2.0 4.0 6.5 kW 1.5 3.0 4.5 kW 250 400 — μA IDD ISTB1 RPL IOL1 Operating Current Standby Current Pull-Low Resistance LCD Common Sink Current 3.3V 5.0V 3.3V No load, 1/3bias, B type inversion, Ta=25°C, LCD display on, fLCD=80Hz, VLCD pin is connected to VSS, 5.0V Power save mode=Low Current2 mode 5.0V — IOH1 LCD Common Source Current — IOL2 LCD Segment Sink Current — IOH2 LCD Segment Source Current — Rev. 1.10 VOL=0.4V for SDA pin For OSCIN pin VDD-VLCD=3.3V, VOL=0.33V VDD-VLCD=5V, VOL=0.5V 500 800 — μA VDD-VLCD=3.3V, VOH=2.97V -140 -230 — μA VDD-VLCD=5V, VOH=4.5V -300 -500 — μA VDD-VLCD=3.3V, VOL=0.33V 250 400 — μA VDD-VLCD=5V, VOL=0.5V 500 800 — μA VDD-VLCD=3.3V, VOH=2.97V -140 -230 — μA VDD-VLCD=5V, VOH=4.5V -300 -500 — μA 5 December 12, 2014 HT9B92 A.C. Characteristics Symbol fLCD1 fLCD2 Parameter LCD Frame Frequency LCD Frame Frequency VSS=0V,VDD=2.4V~5.5V, Ta=-40 to +85°C Test Condition Min. Typ. Max. Ta=25°C, internal oscillator is used, Display control command: P[4:3]="00" 72.0 80.0 88.0 Ta=25°C, internal oscillator is used, Display control command: P[4:3]="01" 63.9 71 78.1 Ta=25°C, internal oscillator is used, Display control command: P[4:3]="10" 57.6 64.0 70.4 Ta=25°C, internal oscillator is used, Display control command: P[4:3]="11" 47.7 53.0 58.3 Ta=-40 to 85°C, internal oscillator is used, Display control command: P[4:3]="00" 56.0 80.0 104.0 Ta=-40 to 85°C, internal oscillator is used, Display control command: P[4:3]="01" 49.7 71.0 92.3 Ta=-40 to 85°C, internal oscillator is used, Display control command: P[4:3]="10" 44.8 64.0 83.2 Ta=-40 to 85°C, internal oscillator is used, Display control command: P[4:3]="11" 37.1 53.0 68.9 Condition VDD 3.3V 2.4~ 5.5V Unit Hz Hz VPOR VDD Start Voltage to ensure Poewr-on Reset — — — — 100 mV RRVDD VDD Rise Rate to ensure Power-on Reset — — 0.05 — — V/ms tPOR Minimum Time for VDD to remain at VPOR to ensure Power-on Reset — — 10 — — ms Note: fLCD=1/tLCD I2C Interface Characteristics Symbol Unless otherwise specified, VSS=0V; VDD=2.4V~5.5V; Ta=-40 to +85°C Parameter Condition Min. Max. Unit — — 400 kHz Time in which the bus must be free before a new transmission can start 1.3 — μs After this period, the first clock pulse is generated 0.6 — μs — 1.3 — μs — 0.6 — μs 0.6 — μs — 0 — ns — 100 — ns Note — 0.3 μs Note — 0.3 μs 0.6 — μs — 0.9 μs — 50 ns fSCL Clock frequency tBUF bus free time tHD: STA Start condition hold time tLOW SCL Low time tHIGH SCL High time tSU: STA Start condition setup time tHD: DAT Data hold time tSU: DAT Data setup time tR SDA and SCL rise time tF SDA and SCL fall time tSU: STO Stop condition set-up time — tAA Output Valid from Clock — tSP Input Filter Time Constant (SDA and SCL Pins) Only relevant for repeated START condition Noise suppression time Note: These parameters are periodically sampled but not 100% tested. Rev. 1.10 6 December 12, 2014 HT9B92 Timing Diagrams I2C Timing SDA tBUF tSU:DAT tf tLOW tSP tHD:STA tr SCL tHD:SDA S tHD:DAT tSU:STA tHIGH tAA tSU:STO P Sr S SDA OUT Power On Reset Timing Note: 1. If the conditions of Reset timing are not satisfied in power ON/OFF sequence, the internal Power on Reset (POR) circuit will not operate normally. 2. If it is difficult to meet power on reset timing conditions, please execute software reset command after Power on. Rev. 1.10 7 December 12, 2014 HT9B92 Functional Description Column Driver Outputs The LCD drive section includes 4 column outputs COM0~COM3 which should be connected directly to the LCD panel. The column output signals are generated in accordance with the selected LCD drive mode. The unused column outputs should be left open-circuit if less than 4 column outputs are required. Power-On Reset When the power is applied, the device is initialized by an internal power-on reset circuit. The status of the internal circuits after initialization is as follows: • All common outputs are set to VSS. • All segment outputs are set to VSS. • LCD Driver Output Waveform: A-type inversion. Address Pointer • Internal oscillator is selected. The addressing mechanism for the display RAM is implemented using the address pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the address pointer by the Display Data Input command. • The 1/3 bias drive mode is selected. • LCD bias generator is in an off state. • LCD Display and internal oscillator are in off states. • Power save mode is set to normal current. • Frame Frequency is set to 80Hz. • Blinking function is switched off. Display Memory – RAM Structure Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. The display RAM is static 36×4 bits RAM which stores the LCD data. Logic “1” in the RAM bit-map indicates the “on” state of the corresponding LCD segment; similarly, logic 0 indicates the “off” state. System Oscillator The contents of the RAM data are directly mapped to the LCD data. The first RAM column corresponds to the segments operated with respect to COM0. In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with COM1, COM2 and COM3 respectively. The following diagram is a data transfer format for I2C interface. The timing for the internal logic and the LCD drive signals are generated by the internal oscillator or external clock source input. The System Clock frequency (fSYS) determines the LCD frame frequency. During initial system power on the System Oscillator will be in the stop state. Segment Driver Outputs MSB The LCD drive section includes up to 36 segment outputs SEG0~SEG35 which should be connected directly to the LCD panel. The segment output signals are generated in accordance with the multiplexed common signals and with the data resident in the display latch. The unused segment outputs should be left open-circuit. Rev. 1.10 SDA Data LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 COM0 COM1 COM2 COM3 COM0 COM1 COM2 COM3 Address n Address n+1 LCD Display Output Data Transfer Format for I2C bus 8 December 12, 2014 HT9B92 Address COM0 COM1 COM2 COM3 Output 00H SEG0 01H SEG1 02H SEG2 03H SEG3 04H SEG4 05H SEG5 06H SEG6 07H SEG7 08H SEG8 09H SEG9 0AH SEG10 0BH SEG11 0CH SEG12 0DH SEG13 0EH SEG14 0FH SEG15 10H SEG16 11H SEG17 12H SEG18 13H SEG19 14H SEG20 15H SEG21 16H SEG22 17H SEG23 18H SEG24 19H SEG25 1AH SEG26 1BH SEG27 1CH SEG28 1DH SEG29 1EH SEG30 1FH SEG31 20H SEG32 21H SEG33 22H SEG34 23H SEG35 RAM Data Bit 3 Bit 2 Bit 1 Bit 0 Note: The LCD display RAM address is specified by the Address Set command and the address will be automatically incremented by one after a 4-bit data is shifted in. Rev. 1.10 9 December 12, 2014 HT9B92 LCD Bias Generator Fractional LCD biasing voltages, known as 1/2 or 1/3 bias voltage, are obtained from an internal voltage divider of three series resistors connected between VLCD and VDD. The centre resistor can be switched out of circuits to provide a 1/2 bias voltage level configuration. LCD Drive Mode Waveforms • When the LCD drive mode is selected as 1/4 duty and 1/2 bias, the waveform and LCD display is shown as follows: AAType Typeinversion inversion BBType Typeinversion inversion tLCD COM0 COM0 COM1 COM1 COM2 COM2 COM3 COM3 SEG n SEG n SEG n+1 SEG n+1 SEG n+2 SEG n+2 SEG n+3 SEG n+3 LCD LCDsegment segment tLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM0 Vop/2 COM0 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM1 Vop/2 COM1 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM2 Vop/2 COM2 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 COM3 Vop/2 COM3 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n Vop/2 SEG n VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n+1 Vop/2 SEG n+1 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n+2 Vop/2 SEG n+2 VLCD VLCD VLCD VLCD VDD VDD VDD VDD Vop/2 Vop/2 Vop/2 SEG n+3 Vop/2 SEG n+3 VLCD VLCD VLCD VLCD State1 State1 (on) (on) State2 State2 (off) (off) Waveforms for 1/4 duty drive mode with 1/2 bias (VOP=VDD-VLCD) Note: tLCD=1/fLCD Rev. 1.10 10 December 12, 2014 HT9B92 • When the LCD drive mode is selected as 1/4 duty and 1/3bias, the waveform and LCD display is shown as follows: BBType Typeinversion inversion AAType Typeinversion inversion COM0 COM0 VDD VDD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 COM0 COM0 VLCD VLCD COM1 COM1 VLCD VLCD VDD VDD VDD VDD 2Vop/3 2Vop/3 COM1 COM1 VLCD VLCD COM2 COM2 VDD VDD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 COM2 COM2 VDD VDD 2Vop/3 2Vop/3 COM3 COM3 VLCD VLCD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 SEG n SEG n VLCD VLCD SEG n+1 SEG n+1 VLCD VLCD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 SEG n+1 SEG n+1 Vop/3 Vop/3 VLCD VLCD VDD VDD VDD VDD 2Vop/3 2Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 SEG n+2 SEG n+2 VLCD VLCD 2Vop/3 2Vop/3 Vop/3 Vop/3 VLCD VLCD Vop/3 Vop/3 VLCD VLCD VDD VDD SEG n+3 SEG n+3 Vop/3 Vop/3 VDD VDD VLCD VLCD SEG n+2 SEG n+2 Vop/3 Vop/3 VDD VDD Vop/3 Vop/3 State2 State2 (off) (off) VLCD VLCD 2Vop/3 2Vop/3 Vop/3 Vop/3 State1 State1 (on) (on) Vop/3 Vop/3 VDD VDD VLCD VLCD SEG n SEG n Vop/3 Vop/3 VLCD VLCD VLCD VLCD COM3 COM3 Vop/3 Vop/3 2Vop/3 2Vop/3 Vop/3 Vop/3 LCD LCDsegment segment tLCD tLCD VDD VDD SEG n+3 SEG n+3 2Vop/3 2Vop/3 Vop/3 Vop/3 VLCD VLCD Waveforms for 1/4 duty drive mode with 1/2 bias (VOP=VDD-VLCD) Note: tLCD=1/fLCD Rev. 1.10 11 December 12, 2014 HT9B92 Blinking Function Data Validity The data on the SDA line must be stable during the high period of the serial clock. The high or low state of the data line can only change when the clock signal on the SCL line is Low as shown in the diagram. The device contains versatile blinking capabilities. The whole display can be blinked at frequencies selected by the Blinking Frequency command. The blinking frequency is a subdivided ratio of the system frequency. The ratio between the system oscillator and blinking frequencies depends on the blinking mode in which the device is operating, as shown in the following table: Blinking Mode Blinking frequency (Hz) 0 Blink off 1 0.5 2 1 3 2 SDA SCL Data line stable; Data valid Change of data allowed START and STOP Conditions • A high to low transition on the SDA line while SCL is high defines a START condition. • A low to high transition on the SDA line while SCL is high defines a STOP condition. Frame Frequency • START and STOP conditions are always generated by the master. The bus is considered to be busy after the START condition. The bus is considered to be free again a certain time after the STOP condition. The device provides four frame frequencies selected with the Frame Frequency command known as 80Hz, 71Hz, 64Hz and 53Hz respectively. Mode Frame frequency (Hz) @ VDD=3.3V 0 80 1 71 2 64 3 53 • The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition. In some respects, the START(S) and repeated START (Sr) conditions are functionally identical. SDA SDA SCL I2C Serial Interface I C Operation 2 P START condition STOP condition Byte Format Every byte put on the SDA line must be 8-bit long. The number of bytes that can be transmitted per transfer is unrestricted. Each byte has to be followed by an acknowledge bit. Data is transferred with the most significant bit, MSB, first. The device supports I C serial interface. The I C bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line, SDA, and a serial clock line, SCL. Both lines are connected to the positive supply via pull-up resistors. When the bus is free, both lines are high. Devices connected to the bus must have open-drain or open-collector outputs to implement a wired-or function. Data transfer is initiated only when the bus is not busy. 2 Rev. 1.10 SCL S 2 P SDA Sr SCL 12 S or Sr 1 2 7 8 9 ACK 1 2 3-8 9 ACK P or Sr December 12, 2014 HT9B92 in no operation. Acknowledge • Each bytes of eight bits is followed by one acknowledge bit. This Acknowledge bit is a low level placed on the bus by the receiver. The master generates an extra acknowledge related clock pulse. • The HT9B92 device address bits are “0111110”. When an address byte is sent, the device compares the first seven bits after the START condition. If they match, the device outputs an Acknowledge on the SDA line. • A slave receiver which is addressed must generate an Acknowledge, ACK, after the reception of each byte. 0 • The device that acknowledges must pull down the SDA line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. 7 8 9 Slave Addressing • The slave address byte is the first byte received following the START condition form the master device. The first seven bits of the first byte make up the slave address. This device only supports the write operation and therefore, the eighth data bit, R/W, which is used to define a read or write operation will be fixed at a “0” state. If the R/W bit is set to 1 to execute a read operation, it will result 1 1 1 0 The start address can only be set from 00H to 1FH. The start address which is greater than 1FH will be regarded as a command. Therefore, it is recommended that the start address should be set from 00H to 1FH. Slave Address 0 0 • Display RAM Single Data Byte A display RAM data byte write operation requires a START condition, a slave address with a write control bit, a valid Register Address byte, a Data byte and a STOP condition. clock pulse for acknowledgement S 1 • Compound Command Type A Compound Command write operation requires a START condition, a slave address with a write control bit, a command byte, up to two command setting bytes and a STOP condition for a compound command write operation. S START condition 1 • Single Command Type A Single Command write operation requires a START condition, a slave address with a write control bit, a command byte and a STOP condition for a single command write operation. acknowledge 2 1 Byte Write Operation not acknowledge 1 1 I2C Interface Write Operation Data Output by Transmitter SCL From Master 1 LSB R/W=0 • A master receiver must signal an end of data to the slave by generating a not-acknowledge, NACK, bit on the last byte that has been clocked out of the slave. In this case, the master receiver must leave the data line high during the 9th pulse to not acknowledge. The master will generate a STOP or repeated START condition. Data Outptu by Receiver Slave Address MSB Command byte 1 1 0 0 1 P Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Write ACK ACK 1st I C Single Command Type Write Operation 2 0 1 1 1 1 Command setting Command byte Slave Address S 1 0 0 1 Write 1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACK ACK 1st P Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ACK ACK 3rd I2C Compound Command Type Write Operation Slave Address S 0 1 1 1 1 Register Address byte 1 0 0 Write 0 0 0 A4 A3 ACK A2 Data byte A1 D7 A0 D6 ACK D5 D4 D3 D2 D1 P D0 ACK I2C Display RAM Single Data Byte Write Operation Rev. 1.10 13 December 12, 2014 HT9B92 Command Summary Display RAM Page Write Operation After a START condition the slave address with a write control bit is placed on the bus followed with the specified display RAM Register Address of which the contents are written into the internal address pointer. The data to be written into the memory will be transmitted next. The internal address pointer will be incremented by 1 after a 4-bit data is shifted in. Then the acknowledge clock pulse will be received after an 8-bit data is shifted. After the internal address point reaches the maximum memory address, 23H, the address pointer will be reset to 00H. It is strongly recommended to write the display RAM data from address 00H to 23H using the Display RAM Page Write Operation. The bit 7 denoted as “C” here is the control bit which is used to determine that the next byte is the display RAM data or command byte. C bit 0 1 1 1 1 1 0 0 0 Write Data byte D7 D6 th n D5 D4 D3 1 Next byte is command. 0 0 A4 A3 A2 A1 A0 Address n ACK ACK Data byte D2 ( n+1) data Next byte is Display RAM data. Register Address byte Slave Address S Remark 0 D1 th D0 D7 data D6 (n+2) D5 th D4 D3 data Data byte D2 D1 ( n+3) th D0 D7 data ACK D6 (N-1) ACK D5 th D4 data D3 D2 N th D1 P D0 data ACK ACK I C Interface N Bytes Display RAM Data Write Operation 2 Display RAM Address Setting Command This command is used to define the start address of the display RAM. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Address Pointer C 0 0 A4 A3 A2 A1 A0 Note Display RAM memory start address Note: 1. The address ranges from 00H to 1FH. 2. It is strongly recommended to write the display RAM data from address 00H to 23H at one time. 3. Power on status: the address will be set to 00H. 4. If the programmed command is not defined, the function will not be affected. Drive Mode Setting Command This command is used to control the LCD bias and display on/off. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 Bias and Display on/off setting C 1 0 X P3 P2 X X Note — Note: P2 Bias 0 1/3 bias (default) 1 1/2 bias P3 LCD Display On/Off 0 Off (default) 1 On ●●Power on status: The 1/3 bias drive mode is selected and the LCD display is switched off. ●●If the programmed command is not defined, the function will not be affected. Rev. 1.10 14 December 12, 2014 HT9B92 Display Control Command This command is used to select the Current mode according to the characteristics of the LCD panel for achieving high display quality and LCD driver output waveform set and frame frequency select. Function (MSB) Bit7 Bit6 Display Control Setting C 0 Bit5 Bit4 Bit3 Bit2 1 P4 P3 P2 Bit1 (LSB) Bit0 P1 P0 Note — Note: P [1:0] Power Save Mode 00 Low Current2 Mode 01 Low Current1 Mode 10 Normal Current Mode 11 High Current Mode P2 Current Consumption Remark x 0.5 ●●The data listed here is for reference only. The actual data depends upon the panel load. ●●Please meet the condition: VDD−VLCD≥3V when used in High current mode. x 0.67 x 1 (default) x 1.8 LCD Driver Output Waveform 0 A Type inversion (default) 1 B Type inversion Remark P [4:3] Frame Frequency @VDD=3.3V (Hz) Remark 00 80 (default) 01 71 10 64 11 53 ●●The data listed here is for reference only. The actual data depends upon the panel load. ●●Please meet the condition: VDD−VLCD≥3V when used in High current mode. ●●The setting of the frame frequency, LCD output waveform and current mode will influence the display image qualities. Please select a proper display setting suitable for the current consumption and display image quality with LCD panel. Mode Flicker Frame Frequency O LCD Driver Output Waveform O Image Quality/Contrast O Power Save Mode O ●●If the programmed command is not defined, the function will not be affected. Rev. 1.10 15 December 12, 2014 HT9B92 Software Reset and Oscillator Mode Setting Command This command is used to select the system oscillator source and to initiate a software reset. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 System Oscillator Setting and Software Reset P1 C 1 1 Software Reset 0 No Operation (default) 1 Initiate a Software Reset 0 1 X Bit1 P1 (LSB) Bit0 Note P0 — Remark When a “Software Reset” is executed, the device will be reset to an initial condition. Other settings can be configured after Software reset is completed. P0 Oscillator Mode 0 Internal Oscillator (default) Remark ●●When the internal oscillator is used, the OSCIN pin must be connected to VSS or open-circuit. ●●When the external clock mode is selected, the external clock External Clock Input Mode is supplied on the OSCIN pin. 1 When the software reset is executed, the device is initialized by an internal power-on reset circuit. The status of the internal circuits after initialization is as follows: ●●All common outputs are set to VSS. ●●All segment outputs are set to VSS. ●●LCD Driver Output Waveform: A-type inversion. ●●Internal oscillator source is selected. ●●1/3 bias is selected. ●●LCD bias generator is off state. ●●LCD Display and system oscillation are off state. ●●Power save mode is set to normal current. ●●Frame Frequency is set to 80Hz. ●●Blinking function is switched off. Note that if the programmed command is not defined, the function will not be affected. Blinking Frequency Setting Command This command defines the blinking frequency of the display modes. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Blinking Frequency setting C 1 1 1 0 X Bit1 (LSB) Bit0 Note P1 P0 — Note: P [1:0] Blinking Frequency 00 Blinking off (default) 01 0.5 Hz 10 1 Hz 11 2 Hz Remark — ●●Power on status: Blinking function is switched off. ●●If the programmed command is not defined, the function will not be affected. Rev. 1.10 16 December 12, 2014 HT9B92 All Pixels On/Off Setting Command This command controls that all pixels are switched on or off when the LCD normally displays. Function (MSB) Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 (LSB) Bit0 All Pixels On/Off setting C 1 1 1 1 1 P1 Note P0 — Note: P [1:0] Blinking Frequency Remark 00 Normal Display (default) 01 All Pixels Off ●●This command is only available when the LCD is normally displayed. The display RAM contents will not be changed when this command is executed. ●●All pixels are switched on or off regardless of the display RAM data when the relevant setting is selected. 10 All Pixels On 11 All Pixels Off ●●Power on status: Normal display. ●●If the programmed command is not defined, the function will not be affected. Operation Flow Chart Access procedures are illustrated below using flowcharts. Initialization Display Data Write (Address Setting) Power On Start Software Reset Setting Address setting Internal LCD Bias Setting Display data RAM write LCD Blinking Frequency Setting Display on LCD Current Mode Setting Next processing LCD Frame Frequency Setting LCD Output Waveform Setting Oscillator Source Input Mode Setting Next processing Rev. 1.10 17 December 12, 2014 HT9B92 Display Quality or Operating Current (Power Save Mode) Setting Start Reduce operating current or enhance display quality. Display quality 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. A type inversion 3. High current mode Operating current 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. Low Current 2 mode Screen Flicker ? 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. B type inversion 3. Low Current 2 mode No YES 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. Low Current 1 mode Screen Flicker ? 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. B type inversion 3. Low Current 1 mode No YES 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. Normal Current mode Screen Flicker ? 1. Please select Frame rate from 80, 71, 64, 53Hz according to LCD panel characteristic. 2. B type inversion 3. Normal Current mode No YES 1. Operating current decreases in order of 80Hz → 71Hz → 64Hz → 53Hz 2. B type inversion 3. High Current mode Rev. 1.10 18 December 12, 2014 HT9B92 Application Circuit Internal Oscillator Circuit Mode VLCD VR* Note: * Adjust VR to fit LCD display. VDD VDD 0.1uF 4.7kΩ 4.7kΩ VDD COM SCL MCU 4 HT9B92 SDA LCD Panel SEG 36 VSS VSS VSS OSCIN TEST1 TEST2 External Clock Input Mode VLCD VR* Note: * Adjust VR to fit LCD display. VDD VDD 0.1uF 4.7kΩ 4.7kΩ VDD COM SCL MCU SDA 4 HT9B92 LCD Panel SEG 36 VSS VSS VSS OSCIN TEST1 TEST2 Rev. 1.10 19 December 12, 2014 HT9B92 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the package information. Additional supplementary information with regard to packaging is listed below. Click on the relevant section to be transferred to the relevant website page. • Further Package Information (include Outline Dimensions, Product Tape and Reel Specifications) • Packing Meterials Information • Carton information Rev. 1.10 20 December 12, 2014 HT9B92 48-pin TSSOP Outline Dimensions Symbol Nom. Max. A — — 0.047 A1 0.002 — 0.006 A2 0.031 0.039 0.041 B 0.007 — 0.011 C 0.004 — 0.008 D 0.488 0.492 0.496 E — 0.319 BSC — E1 0.236 0.240 0.244 e — 0.020 BSC — L 0.018 0.024 0.030 L1 — 0.039 BSC — y — 0.004 — θ 0° ― 8° Symbol Rev. 1.10 Dimensions in inch Min. Dimensions in mm Min. Nom. Max. A — — 1.20 A1 0.05 — 0.15 A2 0.80 1 1.05 B 0.17 — 0.27 C 0.09 — 0.20 D 12.40 12.50 12.60 E — 8.10 BSC — E1 6.00 6.10 6.20 e — 0.50 BSC — L 0.45 0.60 0.75 L1 — 1.0 BSC — y — 0.10 — θ 0° ― 8° 21 December 12, 2014 HT9B92 48-pin LQFP (7mm×7mm) Outline Dimensions Symbol Dimensions in inch Min. Nom. Max. A — 0.354 BSC — B — 0.276 BSC — C — 0.354 BSC — D — 0.276 BSC — E — 0.020 BSC — F 0.007 0.009 0.011 G 0.053 0.055 0.057 H — — 0.063 I 0.002 — 0.006 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° ― 7° Symbol Rev. 1.10 Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.50 BSC — F 0.17 0.22 0.27 G 1.35 1.40 1.45 H — — 1.60 I 0.05 — 0.15 J 0.45 0.60 0.75 K 0.09 — 0.20 α 0° ― 7° 22 December 12, 2014 HT9B92 Copyright© 2014 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 1.10 23 December 12, 2014