48f50ev150.pdf

HT48F50E
I/O Flash Type MCU with EEPROM
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0075E MCU Reset and Oscillator Circuits Application Note
Features
· Operating voltage:
· Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
fSYS=12MHz: 4.5V~5.5V
at VDD=5V
· 6-level subroutine nesting
· Bit Manipulation Instructions
· Multi-programmable Flash Type Program Memory:
· Table Read Function
4096´15
· 63 Powerful Instructions
· EEPROM Data Memory:256´8
· All Instructions executed in 1 or 2 Machine Cycles
· RAM Data Memory:160´8
· Low Voltage Reset Function
· Max. 33 bidirectional I/O with Pull-high Options
· Full Suite of Supported Hardware and Software
· External Interrupt Input shared with an I/O line
Tools Available
· An 8-bit programmable Timer/Event Counter with
· Flash program memory can be re-programmed up to
overflow interrupt and 8-stage perscaler
100,000 times
· A 16-bit programmable Timer/Event Counter with
· Flash program memory data retention > 10 years
overflow interrupt
· EEPROM data memory can be re-programmed up to
· Two Timer External Inputs
1,000,000 times
· Crystal and RC System Oscillator
· EEPROM data memory data retention > 10 years
· Watchdog Timer Function
· ISP (In-System Programming) interface
· PFD/Buzzer Driver Outputs
· 28-pin SKDIP/SOP/SSOP, 48-pin SSOP package
· Power Down and Wake-up Feature for Power Saving
Operation
General Description
The device utilises a Flash type Program Memory, and
therefore have multi-programmable capabilities offering
the advantages of easy and efficient program updates.
The non-volatile internal EEPROM also offers the capability of storing information such as product part numbers, calibration data and other specific product
information. etc. The device is fully supported by the
Holtek range of fully functional development and programming tools, providing a means for fast and efficient
product development cycles.
The HT48F50E is an 8-bit high-performance, RISC architecture microcontroller devices specifically designed
for multiple I/O control product applications. Device flexibility is enhanced with their internal special features
such as power-down and wake-up functions, oscillator
options, buzzer driver, etc. These features combine to
ensure applications require a minimum of external components and therefore reduce overall product costs.
Having the advantages of low-power consumption,
high-performance, I/O flexibility as well as low-cost,
these devices have the versatility to suit a wide range of
application possibilities such as industrial control, consumer products, subsystem controllers, etc.
Rev. 1.50
1
July 28, 2009
HT48F50E
Block Diagram
F la s h P r o g r a m
M e m o ry
R A M D a ta
M e m o ry
E E P R O M
D a ta M e m o ry
W a tc h d o g T im e r
O s c illa to r
R e s e t
C ir c u it
In - c ir c u it
P r o g r a m m in g C ir c u itr y
8 - b it
R IS C C o re
I/O
P o rts
T im e r s
P r o g r a m m a b le
F re q u e n c y G e n e ra to r
S ta c k
R C /C ry s ta l
O s c illa to r
W a tc h d o g
T im e r
L o w
V o lta g e
R e s e t
In te rru p t
C o n tr o lle r
Pin Assignment
1
4 8
P B 6
P B 4
2
4 7
P B 7
P A 3
3
4 6
P A 4
P A 2
4
4 5
P A 5
P A 1
5
4 4
P A 6
P A 0
6
4 3
P A 7
P B 3
7
4 2
N C
P B 2
8
4 1
N C
P B 1 /B Z
9
4 0
N C
P B 0 /B Z
1 0
3 9
N C
P B 5
1
2 8
P B 6
N C
1 1
3 8
O S C 2
P B 4
2
2 7
P B 7
N C
1 2
3 7
O S C 1
P A 3
3
2 6
P A 4
N C
1 3
3 6
V D D
P A 2
4
2 5
P A 5
N C
1 4
3 5
R E S
P A 1
5
2 4
P A 6
P D 7
1 5
3 4
T M R 1
P A 0
6
2 3
P A 7
P D 6
1 6
3 3
P D 3
P B 3
7
2 2
O S C 2
P D 5
1 7
3 2
P D 2
P B 2
8
2 1
O S C 1
P D 4
1 8
3 1
P D 1
P B 1 /B Z
9
2 0
V D D
V S S
1 9
3 0
P D 0
P B 0 /B Z
1 0
1 9
R E S
P G 0 /IN T
2 0
2 9
P C 7
V S S
1 1
1 8
P C 5 /T M R 1
T M R 0
2 1
2 8
P C 6
P G 0 /IN T
1 2
1 7
P C 4
P C 0
2 2
2 7
P C 5
P C 0 /T M R 0
1 3
1 6
P C 3
P C 1
2 3
2 6
P C 4
P C 1
1 4
1 5
P C 2
P C 2
2 4
2 5
P C 3
H T 4 8 F 5 0 E
2 8 S K D IP -A /S O P -A /S S O P -A
Rev. 1.50
P B 5
H T 4 8 F 5 0 E
4 8 S S O P -A
2
July 28, 2009
HT48F50E
Pin Description
Pin Name
PA0~PA7
I/O
Configuration
Option
Description
Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up
Pull-high*
input by configuration option. Software instructions determine if the pin is a
Wake-up
I/O
CMOS output or input. Configuration options determine if all pins on this port
CMOS/Schmitt
have pull-high resistors and if the inputs are Schmitt Trigger or non-Schmitt
Trigger Input
Trigger.
I/O
Pull-high*
I/O or BZ/BZ
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if all pins on this port have pull-high resistors. Pins PB0 and PB1 are
pin-shared with BZ and BZ, respectively.
PC0~PC7
I/O
Pull-high*
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. A configuration option determines if
all pins on this port have pull-high resistors.
PD0~PD7
I/O
Pull-high*
Bidirectional 8-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt trigger input. A configuration option determines if
all pins on this port have pull-high resistors.
I/O
Pull-high*
Bidirectional 1-bit input/output port. Software instructions determine if the pin
is a CMOS output or Schmitt Trigger input. A configuration option determines
if the pin has a pull-high resistor. PG0 is pin-shared with external interrupt pin
INT.
TMR0
I
¾
Timer/Event Counter 0 external Schmitt trigger input pin (without pull-high resistor).
TMR1
I
¾
Timer/Event Counter 1 external Schmitt trigger input pin (without pull-high resistor).
OSC1
OSC2
I
O
RES
I
¾
Schmitt Trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground
PB0/BZ
PB1/BZ
PB2~PB7
PG0/INT
Note:
OSC1, OSC2 are connected to an external RC network or external crystal,
determined by configuration option, for the internal system clock. If the RC
Crystal or RC
system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency.
1. Each pin on PA can be programmed through a configuration option to have a wake-up function.
2. Individual pins cannot be selected to have pull-high resistors. If the pull-high configuration is chosen for
a particular port, then all input pins on this port will be connected to pull-high resistors.
3. Configuration options determine if the pins on PA are CMOS inputs or Schmitt trigger inputs.
4. Pins PC5~PC7 and PD0~7 only exist on the 48-pin package. On the 28-pin package, these pins are not
available.
5. Unbounded pins should be setup as outputs or as inputs with pull-high resistors to conserve power.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
IOL Total ..............................................................150mA
Total Power Dissipation .....................................500mW
Operating Temperature...........................-40°C to 85°C
IOH Total............................................................-100mA
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed
in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
Rev. 1.50
3
July 28, 2009
HT48F50E
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
VDD
IDD1
Operating Voltage
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
¾
fSYS=12MHz
4.5
¾
5.5
V
¾
1
2
mA
¾
3
5
mA
¾
1
2
mA
¾
2.5
4
mA
¾
4
8
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
3V
Operating Current (RC OSC)
No load, fSYS=4MHz
No load, fSYS=4MHz
5V
ISTB1
Standby Current (WDT Enabled)
5V
No load, fSYS=8MHz
3V
No load,
system HALT
5V
ISTB2
Unit
2.2
3V
Operating Current
(Crystal OSC, RC OSC)
Max.
fSYS=4MHz
Operating Current (Crystal OSC)
IDD3
Typ.
¾
5V
IDD2
Min.
Conditions
3V
Standby Current (WDT Disabled)
5V
No load,
system HALT
VIL1
Input Low Voltage for I/O Ports
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
VLVR
Low Voltage Reset
¾
LVR enabled
2.7
3.0
3.3
V
IOL
4
8
¾
mA
I/O Port Sink Current
10
20
¾
mA
-2
-4
¾
mA
-5
-10
¾
mA
3V
VOL=0.1VDD
5V
IOH
3V
I/O Port Source Current
VOH=0.9VDD
5V
RPH
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
Pull-high Resistance
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
fSYS
fTIMER
tWDTOSC
Rev. 1.50
System Clock
(RC OSC, Crystal OSC)
Timer I/P Frequency (TMR)
Min.
Typ.
Max.
Unit
Conditions
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
4.5V~5.5V
400
¾
12000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
¾
4.5V~5.5V
0
¾
12000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
Watchdog Oscillator Period
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July 28, 2009
HT48F50E
Test Conditions
Symbol
Parameter
VDD
Min.
Typ.
Max.
Unit
11
23
46
ms
8
17
33
ms
1024
¾
*tSYS
Conditions
tWDT1
Watchdog Time-out Period
(WDT Internal Clock Source)
3V
tWDT2
Watchdog Time-out Period
(Instruction Clock Source)
¾
Without WDT prescaler
¾
tRES
External Reset Low Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
1024
¾
*tSYS
tLVR
Low Voltage Reset Time
¾
¾
1
¾
2
ms
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
Without WDT prescaler
5V
Wake-up from HALT
Note: *tSYS=1/fSYS
EEPROM - A.C. Characteristics
Symbol
Parameter
Ta=25°C
VCC=5V±10%
VCC=2.2V±10%
Unit
Min.
Max.
Min.
Max.
0
2
0
1
MHz
fSK
Clock Frequency
tSKH
SK High Time
250
¾
500
¾
ns
tSKL
SK Low Time
250
¾
500
¾
ns
tCSS
CS Setup Time
50
¾
100
¾
ns
tCSH
CS Hold Time
0
¾
0
¾
ns
tCDS
CS Deselect Time
250
¾
250
¾
ns
tDIS
DI Setup Time
100
¾
200
¾
ns
tDIH
DI Hold Time
100
¾
200
¾
ns
tPD1
DO Delay to ²1²
¾
250
¾
500
ns
tPD0
DO Delay to ²0²
¾
250
¾
500
ns
tSV
Status Valid Time
¾
250
¾
250
ns
tPR
Write Cycle Time
¾
5
¾
5
ms
Rev. 1.50
5
July 28, 2009
HT48F50E
System Architecture
A key factor in the high-performance features of the
Holtek range of microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found within RISC
microcontrollers providing increased speed of operation
and enhanced performance. The pipelining scheme is
implemented in such a way that instruction fetching and
instruction execution are overlapped, hence instructions
are effectively executed in one cycle, with the exception
of branch or call instructions. An 8-bit wide ALU is used
in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation,
increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the
Accumulator and the ALU. Certain internal registers are
implemented in the Data Memory and can be directly or
indirectly addressed. The simple addressing methods of
these registers along with additional architectural features ensure that a minimum of external components is
required to provide a functional I/O control system with
maximum reliability and flexibility.
Program Counter is incremented at the beginning of the
T1 clock during which time a new instruction is fetched.
The remaining T2~T4 clocks carry out the decoding and
execution functions. In this way, one T1~T4 clock cycle
forms one instruction cycle. Although the fetching and
execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the
microcontroller ensures that instructions are effectively
executed in one instruction cycle. The exception to this
are instructions where the contents of the Program
Counter are changed, such as subroutine calls or
jumps, in which case the instruction will take one more
instruction cycle to execute.
When the RC oscillator is used, OSC2 is freed for use as
a T1 phase clock synchronizing pin. This T1 phase clock
has a frequency of fSYS/4 with a 1:3 high/low duty cycle.
For instructions involving branches, such as jump or call
instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as
the program takes one cycle to first obtain the actual
jump or call address and then another cycle to actually
execute the branch. The requirement for this extra cycle
should be taken into account by programmers in timing
sensitive applications
Clocking and Pipelining
The main system clock, derived from either a Crystal/Resonator or RC oscillator is subdivided into four internally generated non-overlapping clocks, T1~T4. The
O s c illa to r C lo c k
( S y s te m C lo c k )
P h a s e C lo c k T 1
P h a s e C lo c k T 2
P h a s e C lo c k T 3
P h a s e C lo c k T 4
P ro g ra m
C o u n te r
P ip e lin in g
P C
P C + 1
F e tc h In s t. (P C )
E x e c u te In s t. (P C -1 )
P C + 2
F e tc h In s t. (P C + 1 )
E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 )
E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
M O V A ,[1 2 H ]
2
C A L L D E L A Y
3
C P L [1 2 H ]
4
:
5
:
6
1
D E L A Y :
F e tc h In s t. 1
E x e c u te In s t. 1
F e tc h In s t. 2
E x e c u te In s t. 2
F e tc h In s t. 3
F lu s h P ip e lin e
F e tc h In s t. 6
E x e c u te In s t. 6
F e tc h In s t. 7
N O P
Instruction Fetching
Rev. 1.50
6
July 28, 2009
HT48F50E
Program Counter
The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might
cause program branching, so an extra cycle is needed
to pre-fetch. Further information on the PCL register can
be found in the Special Function Register section.
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL², that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
Stack
This is a special part of the memory which is used to
save the contents of the Program Counter only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and can neither be
read from nor written to. The activated level is indexed
by the Stack Pointer, SP, which can also neither be read
from nor written to. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter
are pushed onto the stack. At the end of a subroutine or
an interrupt routine, signaled by a return instruction,
RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the
Stack Pointer will point to the top of the stack.
When executing instructions requiring jumps to
non-consecutive addresses such as a jump instruction,
a subroutine call, interrupt or reset, etc., the
microcontroller manages program control by loading the
required address into the Program Counter. For conditional skip instructions, once the condition has been
met, the next instruction, which has already been
fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained.
If the stack is full and an enabled interrupt takes place,
the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack
Pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack
overflow. Precautions should be taken to avoid such
cases which might cause unpredictable program
branching.
The lower byte of the Program Counter, known as the
Program Counter Low register or PCL, is available for
program control and is a readable and writable register.
By transferring data directly into this register, a short
program jump can be executed directly, however, as
only this low byte is available for manipulation, the
jumps are limited to the present page of memory, that is
256 locations. When such program jumps are executed
it should also be noted that a dummy cycle will be inserted.
Program Counter Bits
Mode
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0
Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1
Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Skip
Program Counter + 2
Loading PCL
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
PC11 PC10
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program Counter
Note:
PC11~PC8: Current Program Counter bits
@[email protected]: PCL bits
#11~#0: Instruction code address bits
S11~S0: Stack register bits
Rev. 1.50
7
July 28, 2009
HT48F50E
P ro g ra m
C o u n te r
Special Vectors
Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
S ta c k L e v e l 1
S ta c k L e v e l 2
S ta c k
P o in te r
S ta c k L e v e l 3
· Location 000H
P ro g ra m
M e m o ry
This vector is reserved for use by the device reset for
program initialisation. After a device reset is initiated, the
program will jump to this location and begin execution.
S ta c k L e v e l 4
· Location 004H
S ta c k L e v e l 5
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if
the external interrupt is enabled and the stack is not
full.
S ta c k L e v e l 6
Arithmetic and Logic Unit - ALU
The arithmetic-logic unit or ALU is a critical area of the
microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main
microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or
logical operations after which the result will be placed in
the specified register. As these ALU calculation or operations may result in carry, borrow or other status
changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the
following functions:
· Location 008H
This internal vector is used by the Timer/Event Counter 0. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter interrupt is enabled and the stack
is not full.
· Location 00CH
This internal vector is used by the Timer/Event Counter 1. If a counter overflow occurs, the program will
jump to this location and begin execution if the
timer/event counter interrupt is enabled and the stack
is not full.
· Arithmetic operations ADD, ADDM, ADC, ADCM,
SUB, SUBM, SBC, SBCM, DAA
H T 4 8 F 5 0 E
0 0 0 H
· Logic operations AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
0 0 4 H
· Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
0 0 8 H
· Increment and Decrement INCA, INC, DECA, DEC
· Branch decision JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA,
0 0 C H
SDZA, CALL, RET, RETI
Flash Program Memory
0 1 0 H
The Program Memory is the location where the user
code or program is stored. For this device the Program
Memory is a Flash type, which means it can be programmed and reprogrammed a large number of times,
allowing the user the convenience of code modification
using the same device. By using the appropriate programming tools, these devices offer users the flexibility
to conveniently debug and develop their applications
while also offering a means of field programming.
0 1 4 H
In itia lis a tio n
V e c to r
E x te rn a l
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 0
In te rru p t V e c to r
T im e r /E v e n t C o u n te r 1
In te rru p t V e c to r
0 1 8 H
F F F H
1 5 b its
Program Memory Structure
Organization
The Program Memory has a capacity of 4K by 15 bits.
The Program Memory is addressed by the Program
Counter and also contains data, table information and
interrupt entries. Table data, which can be setup in any
location within the Program Memory, is addressed by a
separate table pointer register.
Rev. 1.50
Look-up Table
Any location within the Program Memory can be defined
as a look-up table where programmers can store fixed
data. To use the look-up table, the table pointer must
first be setup by placing the lower order address of the
look up data to be retrieved in the table pointer register,
TBLP. This register defines the lower 8-bit address of
the look-up table.
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July 28, 2009
HT48F50E
After setting up the table pointer, the table data can be
retrieved from the current Program Memory page or last
Program Memory page using the ²TABRDC[m]² or
²TABRDL [m]² instructions, respectively. When these instructions are executed, the lower order table byte from
the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the
Program Memory will be transferred to the TBLH special
register. Any unused bits in this transferred higher order
byte will have uncertain values.
Table Program Example
The following example shows how the table pointer and
table data is defined and retrieved from the HT48F50E
device. This example uses raw table data located in the
last page which is stored there using the ORG statement. The value at this ORG statement is ²0F00H²
which refers to the start address of the last page within
the 4K Program Memory of the microcontroller. The table pointer is setup here to have an initial value of ²06H².
This will ensure that the first data read from the data table will be at the Program Memory address ²0F06H² or 6
locations after the start of the last page. Note that the
value for the table pointer is referenced to the first address of the present page if the ²TABRDC [m]² instruction is being used. The high byte of the table data which
in this case is equal to zero will be transferred to the
TBLH register automatically when the ²TABRDL [m]² instruction is executed.
The following diagram illustrates the addressing/data
flow of the look-up table:
P ro g ra m C o u n te r
H ig h B y te
P ro g ra m
M e m o ry
T B L P
T B L H
S p e c ifie d b y [m ]
L o w
H ig h B y te o f T a b le C o n te n ts
B y te o f T a b le C o n te n ts
Look-up Table
tempreg1
tempreg2
:
:
db
db
?
?
; temporary register #1
; temporary register #2
mov
a,06h
; initialise table pointer - note that this address
; is referenced
mov
tblp,a
:
:
; to the last page or present page
tabrdl
dec
tempreg1
tblp
tabrdl
:
:
;
;
;
;
transfers value in table referenced by table pointer
to tempregl
data at prog. memory address ²0F06H² transferred to
tempreg1 and TBLH
; reduce value of table pointer by one
tempreg2
;
;
;
;
;
;
transfers value in table referenced by table pointer
to tempreg2
data at prog.memory address ²0F05H² transferred to
tempreg2 and TBLH
in this example the data ²1AH² is transferred to
tempreg1 and data ²0FH² to register tempreg2
org
300h
dc
00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh
:
:
Rev. 1.50
; sets initial address of HT48F50E last page
9
July 28, 2009
HT48F50E
in-circuit programming of the devices are beyond the
scope of this document and will be supplied in supplementary literature.
Because the TBLH register is a read-only register and
cannot be restored, care should be taken to ensure its
protection if both the main routine and Interrupt Service
Routine use table read instructions. If using the table
read instructions, the Interrupt Service Routines may
change the value of the TBLH and subsequently cause
errors if used again by the main routine. As a rule it is
recommended that simultaneous use of the table read
instructions should be avoided. However, in situations
where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any
main routine table-read instructions. Note that all table
related instructions require two instruction cycles to
complete their operation.
C o n n e c to r
PA0
Serial data input/output
Serial clock
Device reset
VDD
Power supply
VSS
Ground
V S S
D a ta
P A 0
C lo c k
P A 4
R e s e t
R E S
The RAM Data Memory is a volatile area of 8-bit wide
RAM internal memory and is the location where temporary information is stored. Divided into two sections, the
first of these is an area of RAM where special function
registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and
written to directly under program control, however,
some remain protected from user manipulation. The
second area of RAM Data Memory is reserved for general purpose use. All locations within this area are read
and write accessible under program control.
Function
PA4
G ro u n d
RAM Data Memory
The provision of Flash type Program Memory gives the
user and designer the convenience of easy upgrades
and modifications to their programs on the same device.
As an additional convenience, Holtek has provided a
means of programming the microcontroller in-circuit.
This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller, and then
programming or upgrading the program at a later stage.
This enables product manufacturers to easily keep their
manufactured products supplied with the latest program
releases without removal and re-insertion of the device.
RES
V D D
In-circuit Programming Interface
In Circuit Programming
Pin Name
P o w e r
Organization
The RAM Data Memory is subdivided into two banks,
known as Bank 0 and Bank 1, all of which are implemented in 8-bit wide RAM. Most of the RAM Data Memory is located in Bank 0 which is also subdivided into two
sections, the Special Purpose Data Memory and the
General Purpose Data Memory. The start address of the
RAM Data Memory for all devices is the address ²00H²,
and the last Data Memory address is ²FFH². Registers
which are common to all microcontrollers, such as ACC,
PCL, etc., have the same Data Memory address.
The Program Memory and EEPROM memory can both
be programmed serially in-circuit using a 5-wire interface. Data is downloaded and uploaded serially on a
single pin with an additional line for the clock. Two additional lines are required for the power supply and one
line for the reset. The technical details regarding the
Table Location Bits
Instruction
b11
b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
TABRDC [m]
PC11
PC10
PC9
PC8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
PC11~PC8: Current Program Counter bits
@[email protected]: Table Pointer TBLP bits
Rev. 1.50
10
July 28, 2009
HT48F50E
Special Purpose Data Memory
H T 4 8 F 5 0 E
0 0 H
1 F H
2 0 H
5 0 H
6 0 H
F F H
S p e c ia l P u r p o s e
D a ta M e m o ry
This area of Data Memory, is located in Bank 0, where
registers, necessary for the correct operation of the
microcontroller, are stored. Most of the registers are
both readable and writable but some are protected and
are readable only, the details of which are located under
the relevant Special Function Register section. Note
that for locations that are unused, any read instruction to
these addresses will return the value ²00H². Although
the Special Purpose Data Memory registers are located
in Bank 0, they will still be accessible even if the Bank
Pointer has selected Bank 1.
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
: U n u s e d , re a d a s "0 0 "
Bank 0 RAM Data Memory Structure
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
Bank 1 of the RAM Data Memory contains only one special function register, known as the EECR register,
which is used for EEPROM control and located at address ²40H² for all devices.
4 0 H
E E C R
Bank 1 RAM Data Memory Structure
Note:
Most of the RAM Data Memory bits can be directly manipulated using the ²SET [m].i² and
²CLR [m].i² instructions with the exception of a
few dedicated bits. The RAM Data Memory can
also be accessed through the Memory Pointer
registers MP0 and MP1.
General Purpose Data Memory
All microcontroller programs require an area of
read/write memory where temporary data can be stored
and retrieved for use later. It is this area of RAM memory
that is known as General Purpose Data Memory. This
area of Data Memory is fully accessible by the user program for both read and write operations. By using the
²SET [m].i² and ²CLR [m].i² instructions individual bits
can be set or reset under program control giving the
user a large range of flexibility for bit manipulation in the
Data Memory.
5 F H
6 0 H
F F H
H T 4
IA
M
IA
M
8 F 5 0 E
R 0
P 0
R 1
P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
T M R 0
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
P D
P D C
P G
P G C
G e n e ra l P u rp o s e
D a ta M e m o ry
(1 6 0 B y te s )
: U n u s e d , re a d a s "0 0 "
Special Purpose Data Memory Structure
Rev. 1.50
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July 28, 2009
HT48F50E
Special Function Registers
rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1. Acting as a
pair, IAR0 and MP0 can together only access data from
Bank 0, while the IAR1 and MP1 register pair can access data from both Bank 0 and Bank 1. As the Indirect
Addressing Registers are not physically implemented,
reading the Indirect Addressing Registers indirectly will
return a result of ²00H² and writing to the registers indirectly will result in no operation.
To ensure successful operation of the microcontroller,
certain internal registers are implemented in the RAM
Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts,
watchdog, etc., as well as external functions such as I/O
data control. The location of these registers within the
RAM Data Memory begins at the address ²00H². Any
unused Data Memory locations between these special
function registers and the point where the General Purpose Memory begins is reserved for future expansion
purposes, attempting to read data from these locations
will return a value of ²00H².
Memory Pointer - MP0, MP1
For this device, two 8-bit Memory Pointers, known as
MP0 and MP1 are provided. These Memory Pointers
are physically implemented in the Data Memory and can
be manipulated in the same way as normal registers
providing a convenient way with which to address and
track data. When any operation to the relevant Indirect
Addressing Registers is carried out, the actual address
that the microcontroller is directed to, is the address
specified by the related Memory Pointer. MP0, together
with Indirect Addressing Register, IAR0, are used to access data from Bank 0 only, while MP1 and IAR1 are
used to access data from both Bank 0 and Bank 1.
Indirect Addressing Register - IAR0, IAR1
The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register
space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data
manipulation uses these Indirect Addressing Registers
and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in
no actual read or write operation to these registers but
The following example shows how to clear a section of four RAM locations already defined as locations adres1 to
adres4.
data .section ¢data¢
adres1
db ?
adres2
db ?
adres3
db ?
adres4
db ?
block db ?
code .section at 0 ¢code¢
org 00h
start:
mov
mov
mov
mov
a,04h
; setup size of block
block,a
a,offset adres1; Accumulator loaded with first RAM address
mp0,a
; setup memory pointer with first RAM address
loop:
clr
inc
sdz
jmp
IAR0
mp0
block
loop
; clear the data at address defined by MP0
; increment memory pointer
; check if last memory location has been cleared
continue:
The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.
Rev. 1.50
12
July 28, 2009
HT48F50E
Bank Pointer - BP
another, it is necessary to do this by passing the data
through the Accumulator as no direct transfer between
two registers is permitted.
The RAM Data Memory is divided into two Banks,
known as Bank 0 and Bank 1. With the exception of the
EECR register, all of the Special Purpose Registers and
General Purpose Registers are contained in Bank 0.
Bank 1 contains only one register, which is the
EEPROM Control Register, known as EECR. Selecting
the required Data Memory area is achieved using the
Bank Pointer. If data in Bank 0 is to be accessed, then
the BP register must be loaded with the value ²00²,
while if data in Bank 1 is to be accessed, then the BP
register must be loaded with the value ²01².
Program Counter Low Register - PCL
To provide additional program control functions, the low
byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area
of the Data Memory. By manipulating this register, direct
jumps to other program locations are easily implemented. Loading a value directly into this PCL register
will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only
jumps within the current Program Memory page are permitted. When such operations are used, note that a
dummy cycle will be inserted.
Using Memory Pointer MP0 and Indirect Addressing
Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer. The EECR
register is located at memory location 40H in Bank 1 and
can only be accessed indirectly using memory pointer
MP1 and the indirect addressing register, IAR1, after the
BP register has first been loaded with the value ²01².
Data can only be read from or written to the EEPROM
via this register.
Look-up Table Registers - TBLP, TBLH
These two special function registers are used to control
operation of the look-up table which is stored in the Program Memory. TBLP is the table pointer and indicates
the location where the table data is located. Its value
must be setup before any table read commands are executed. Its value can be changed, for example using the
²INC² or ²DEC² instructions, allowing for easy table data
pointing and reading. TBLH is the location where the
high order byte of the table data is stored after a table
read data instruction has been executed. Note that the
lower order table data byte is transferred to a user defined location.
The Data Memory is initialised to Bank 0 after a reset,
except for the WDT time-out reset in the Power Down
Mode, in which case, the Data Memory bank remains
unaffected. It should be noted that Special Function
Data Memory is not affected by the bank selection,
which means that the Special Function Registers can be
accessed from within either Bank 0 or Bank 1. Directly
addressing the Data Memory will always result in Bank 0
being accessed irrespective of the value of the Bank
Pointer.
Watchdog Timer Register - WDTS
The Watchdog feature of the microcontroller provides
an automatic reset function giving the microcontroller a
means of protection against spurious jumps to incorrect
Program Memory addresses. To implement this, a timer
is provided within the microcontroller which will issue a
reset command when its value overflows. To provide
variable Watchdog Timer reset times, the Watchdog
Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register.
By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be
setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128.
Accumulator - ACC
The Accumulator is central to the operation of any
microcontroller and is closely related with operations
carried out by the ALU. The Accumulator is the place
where all intermediate results from the ALU are stored.
Without the Accumulator it would be necessary to write
the result of each calculation or logical operation such
as addition, subtraction, shift, etc., to the Data Memory
resulting in higher programming and timing overheads.
Data transfer operations usually involve the temporary
storage function of the Accumulator; for example, when
transferring data between one user defined register and
b 7
b 0
B P 0
B a n k P o in te r
B P 0
0
1
D a ta M e m o ry
B a n k 0
B a n k 1
N o t u s e d , m u s t b e re s e t to "0 "
Rev. 1.50
13
July 28, 2009
HT48F50E
Status Register - STATUS
· TO is cleared by a system power-up or executing the
²CLR WDT² or ²HALT² instruction. TO is set by a
WDT time-out.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO).
These arithmetic/logical operation and system management flags are used to record the status and operation of
the microcontroller.
In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the subroutine
can corrupt the status register, precautions must be
taken to correctly save it.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO
flag can be affected only by a system power-up, a WDT
time-out or by executing the ²CLR WDT² or ²HALT² instruction. The PDF flag is affected only by executing the
²HALT² or ²CLR WDT² instruction or during a system
power-up.
Interrupt Control Register - INTC
This 8-bit register, known as the INTC register, controls
the operation of both external and internal timer interrupts. By setting various bits within this register using
standard bit manipulation instructions, the enable/disable function of the external and timer interrupts can be
independently controlled. A master interrupt bit within
this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on
or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing
the ²RETI² instruction.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
· C is set if an operation results in a carry during an ad-
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
Note:
In situations where other interrupts may require
servicing within present interrupt service routines, the EMI bit can be manually set by the
program after the present interrupt service routine has been entered.
· AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is
cleared.
Timer/Event Counter Registers
· Z is set if the result of an arithmetic or logical operation
This device contains an 8-bit Timer/Event Counter and a
16-bit Timter/Event counter, which have the associated
registers known as TMR0, TMR1H and TMR1L, and are
the locations where the timers¢s 8-bit and 16-bit values
are located. The associated control registers, known as
TMR0C and TMR1C, contains the setup information for
these two timers.
is zero; otherwise Z is cleared.
· OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit,
or vice versa; otherwise OV is cleared.
· PDF is cleared by a system power-up or executing the
²CLR WDT² instruction. PDF is set by executing the
²HALT² instruction.
b 7
b 0
T O
P D F
O V
Z
A C
C
S T A T U S R e g is te r
A r
C a
A u
Z e
ith m e
r r y fla
x ilia r y
r o fla g
O v e r flo w
g
tic /L o g ic O p e r a tio n F la g s
c a r r y fla g
fla g
S y s te m M
P o w e r d o w
W a tc h d o g
N o t im p le m
a n
n
tim
e
a g e m e n t F la g s
fla g
e - o u t fla g
n te d , re a d a s "0 "
Status Register
Rev. 1.50
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July 28, 2009
HT48F50E
Input/Output Ports and Control Registers
storage allows information such as product identification
numbers, calibration values, specific user data, system
setup data or other product information to be stored directly within the product microcontroller.
Within the area of Special Function Registers, the I/O
registers and their associated control registers play a
prominent role. All I/O ports have a designated register
correspondingly labeled as PA, PB, PC, etc. These labeled I/O registers are mapped to specific addresses
within the Data Memory as shown in the Data Memory
table, which are used to transfer the appropriate output
or input data on that port. with each I/O port there is an
associated control register labeled PAC, PBC, PCC,
etc., also mapped to specific addresses with the Data
Memory. The control register specifies which pins of that
port are set as inputs and which are set as outputs. To
setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set
low. During program initialization, it is important to first
setup the control registers to specify which pins are outputs and which are inputs before reading data from or
writing data to the I/O ports. One flexible feature of these
registers is the ability to directly program single bits using the ²SET [m].i² and ²CLR [m].i² instructions. The
ability to change I/O pins from output to input and vice
versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices.
EEPROM Data Memory Structure
The internal EEPROM Data Memory has a capacity of
256´8 bits. Unlike the Program Memory and RAM Data
Memory, the EEPROM Data Memory is not directly
mapped and is therefore not directly accessible in the
same way as the other types of memory. Instead it has
to be accessed indirectly through the EEPROM Control
Register.
Accessing the EEPROM Data Memory
The EEPROM Data Memory is accessed using a set of
seven instructions. These instructions control all functions of the EEPROM such as read, write, erase, enable
etc. The internal EEPROM structure is similar to that of a
standard 3-wire EEPROM, for which four pins are used
for transfer of instruction, address and data information.
These are the Chip Select pin, CS, Serial Clock pin, SK,
Data In pin, DI and the Data Out pin, DO. All actions related to the EEPROM must be conducted through the
EECR register which is located in Bank 1 of the RAM
Data Memory, in which each of these four EEPROM
pins is represented by a bit in the EECR register. By manipulating these four bits in the EECR register, in accordance with the accompanying timing diagrams, the
microcontroller can communicate with the EEPROM
and carry out the required functions, such as reading
and writing data.
EEPROM Control Register - EECR
This register is used to control all operations to and from
the EEPROM Data Memory. As the EEPROM Data
Memory is not mapped like the other memory types, all
data to and from the EEPROM must be made through
this register. The EECR register is located in Bank 1 of
the Data Memory, so before use the Bank Pointer must
be setup to a value of ²1². The EECR register can only
be read and written to indirectly using the MP1 address
pointer.
Bit No.
EEPROM Data Memory
One of the special features within all these devices is
their internal EEPROM Data Memory. EEPROM, which
stands for Electrically Erasable Programmable Read
Only Memory, is by its nature a non-volatile form of
memory, with data retention even when its power supply
is removed. By incorporating this kind of data memory a
whole new host of application possibilities are made
available to the designer. The availability of EEPROM
EEPROM Function
0~3
¾
Not implemented bit, read as ²0²
4
CS
EEPROM Data Memory select
5
SK
Serial Clock: Used to clock data
into and out of the EEPROM
6
DI
Data Input: Instructions, address
and data information are written to
the EEPROM on this pin
7
DO
Data Output: Data from the
EEPROM is readout with this bit.
Will be in a high-impedance condition if no data is being read.
EECR Register - Control Bit Functions
b 7
D O
Label
b 0
D I
S K
C S
E E C R
N o
E E
E E
E E
E E
t im
P R
P R
P R
P R
p le
O M
O M
O M
O M
m e n te
D a ta
S e r ia
S e r ia
S e r ia
d ,
M
l C
l D
l D
re
e m
lo
a
a
a d a s "0 "
o r y S e le c t
c k In p u t
ta In p u t
ta O u tp u t
EEPROM Control Register
Rev. 1.50
15
July 28, 2009
HT48F50E
The related instruction is transmitted to the EEPROM
via the DI bit, after CS has first been set to ²1² to enable
the EEPROM and a start bit ²1² has been transmitted.
For the READ, WRITE and ERASE instructions, each of
the three instructions has its own two bit related instruction code. The 9-bit address should then be transmitted.
The address is transmitted in MSB first format.
When reading data from the EEPROM, the data will
clocked out on the rising edge of SK and appear on DO.
The DO pin will normally be in a high-impedance condition unless a READ statement is being executed. When
writing to the EEPROM the data must be presented first
on DI and then clocked in on the rising edge of SK. After
all the instruction, address and data information has
been transmitted, CS should be cleared to ²0² to terminate the instruction transmission. Note that after power
on the EEPROM must be initialised as described.
For the other four instructions, ²EWEN², ²EWDS²,
²ERAL² and ²WRAL², after the start bit has been transmitted a ²00² instruction code should then follow. The
9-bit address information should then follow. The first
two bits of this address is instruction dependant as
shown in the table while the remaining bits have don¢t
care values and can be either high or low.
As indirect addressing is the only way to access the
EECR register, all read and write operations to this register must take place using the Indirect Addressing Register, IAR1, and the Memory Pointer, MP1. Because the
EECR control register is located in Bank 1 of the RAM
Data Memory at location 40H, the MP1 Memory Pointer
must first be set to the value 40H and the Bank Pointer
set to ²1².
After any write or erase instruction is issued, the internal
write function of the EEPROM will be used to write the
data into the device. As this internal write operation uses
the EEPROM¢s own internal clock, no further instructions will be accepted by the EEPROM until the internal
write function has ended. After power on and before any
instruction is issued the EEPROM must be properly initialised to ensure proper operation.
EEPROM Data Memory Instruction Set
Control over the internal EEPROM, to execute functions
such as read, write, disable, enable etc., is implemented
through instructions of which there are a total of seven.
C S
tC
S S
tC
tS
S K
tD
D I
IS
tS
K H
K L
tC
t D IH
V a lid D a ta
tP
D S
S H
V a lid D a ta
tP
D 0
D 1
D O
Clocking Data In and Out of the EEPROM
Instruction
Function
Start Bit
Instruction
Code
Address
Data
READ
Read Out Data Byte(s)
1
10
X, A7~A0
D7~D0
ERASE
Erase Single Data Byte
1
11
X, A7~A0
¾
WRITE
Write Single Data Byte
1
01
X, A7~A0
D7~D0
EWEN
Erase/Write Enable
1
00
11 XXXXX XX
¾
EWDS
Erase/Write Disable
1
00
00 XXXXX XX
¾
ERAL
Erase All
1
00
10 XXXXX XX
¾
WRAL
Write All
1
00
01 XXXXX XX
D7~D0
Instruction Set Summary
Rev. 1.50
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HT48F50E
READ
WRITE
The ²READ² instruction is used to read out one or more
bytes of data from the EEPROM Data Memory. To instigate a ²READ² instruction, the CS bit should be set high,
followed by a high start bit and then the instruction code
²10², all transmitted via the DI bit. For this device, a
dummy bit must be inserted between the last bit of the
instruction code and the MSB of the address. The address information should then follow with the MSB being
transmitted first. After the last address bit, A0, has been
transmitted, the data can be clocked out, bit D7 first, on
the rising edge of the SK clock signal and can be read
via the DO bit. However, a dummy ²0² bit will first precede the reading of the first data bit, D7. After the full
byte has been read out, the internal address will be automatically incremented allowing the next consecutive
data byte to be read out without entering further address
data. As long as the CS bit remains high, data bit D7 of
the next address will automatically follow data bit D0 of
the previous address with no dummy ²0² being inserted
between them. The address will keep incrementing in
this way until CS returns to a low value. DO will normally
be in a high impedance condition until the ²READ² instruction is executed. Note that as the ²READ² instruction is not affected by the condition of the ²EWEN² or
²EWDS² instruction, the READ command is always
valid and independent of these two instructions.
The ²WRITE² instruction is used to write a single byte of
data into the EEPROM. To instigate a WRITE instruction, the CS bit should be set high, followed by a high
start bit and then the instruction code ²01², all transmitted via the DI bit. For this device, a dummy bit must be
inserted between the last bit of the instruction code and
the MSB of the address. The address information
should then follow with the MSB bit being transmitted
first. After the last address bit, A0, has been transmitted,
the data can be immediately transmitted MSB first. After
all the WRITE instruction code, address and data have
been transmitted, the data will be written into the
EEPROM when the CS bit is cleared to zero. The
EEPROM does this by executing an internal write-cycle,
which will first erase and then write the previously transmitted data byte into the EEPROM. This process takes
place internally using the EEPROM¢s own internal clock
and does not require any action from the SK clock. No
further instructions can be accepted by the EEPROM
until this internal write-cycle has finished. To determine
when the write cycle has ended, CS should be again
brought high and the DO bit polled. If DO is low this indicates that the internal write-cycle is still in progress,
however, the DO bit will change to a high value when the
internal write-cycle has ended. Before a ²WRITE² instruction is transmitted an ²EWEN² instruction must
have been transmitted at some point earlier to ensure
that the erase/write function of the EEPROM is enabled.
tC
C S
D S
S K
D I
0
1
1
S ta r t b it
A 7
A 0
0
D O
D 7
D 0
D 7
T h e a d d r e s s is a u to m a tic a lly in c r e m e n te d a t th is p o in t.
READ Timing
tC
D S
V e r ify
C S
S ta n d b y
S K
D I
1
0
1
A 7
A 1
A 0
D 7
D 0
S ta r t b it
tS
V
B u s y
D O
tP
R
WRITE Timing
Rev. 1.50
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July 28, 2009
HT48F50E
EWEN/EWDS
cycle has ended, CS should be again brought high and
the DO bit polled. If D0 is low this indicates that the internal write-cycle is still in progress, however the D0 bit will
change to a high value when the internal write-cycle has
ended. Before an ²ERAL² instruction is transmitted an
²EWEN² instruction must have been transmitted at
some point earlier to ensure that the erase/write function
of the EEPROM is enabled.
The ²EWEN² instruction is the Erase/Write Enable instruction and the ²EWDS² instruction is the Erase/Write
Disable instruction. To instigate an ²EWEN² or ²EWDS²
instruction, the CS bit should first be set high, followed
by a high start bit and then the instruction code ²00². For
the ²EWEN² instruction, a ²11² should then be transmitted and for the ²EWDS² instruction a ²00² should be
transmitted. Following on from this, 7-bits of ²don¢t care²
data should then be transmitted to complete the instruction. If the device is already in the Erase Write Disable
mode then no write or erase operations can be executed
thus protecting the internal EEPROM data. Before any
write or erase instruction is executed an ²EWEN² instruction must be issued. After the ²EWEN² instruction
is executed, the device will remain in the Erase Write
Enable mode until a subsequent ²EWDS² instruction is
issued or until the device is powered down.
WRAL
The WRAL instruction is used to write the same data
into the entire EEPROM. To instigate this instruction, the
CS bit should be set high, followed by a high start bit and
then the instruction code ²00². Following on from this, a
²01² should then be transmitted. This should be followed by 7-bits of ²don¢t care² data. The data information should then follow with the MSB bit being
transmitted first. After the instruction code and data
have been transmitted, the data will be written into the
EEPROM when the CS bit is cleared to zero. The
EEPROM does this by executing an internal write-cycle.
This process takes place internally using the
EEPROM¢s own internal clock and does not require any
action from the SK clock. No further instructions can be
accepted by the EEPROM until this internal write-cycle
has finished. To determine when the write cycle has
ended, CS should be again brought high and the DO bit
polled. If D0 is low this indicates that the internal
write-cycle is still in progress, however the D0 bit will
change to a high value when the internal write-cycle has
ended. Before a ²WRAL² instruction is transmitted an
²EWEN² instruction must have been transmitted at
some point earlier to ensure that the erase/write function
of the EEPROM is enabled. The WRAL instruction will
automatically erase any previously written data making
it unnecessary to first issue an erase instruction.
ERAL
The ²ERAL² instruction is used to erase the whole contents of the EEPROM memory. After it has been executed all the data in the EEPROM will be set to ²1². To
instigate this instruction, the CS bit should be set high,
followed by a high start bit and then the instruction code
²00². Following on from this, a ²10² should then be
transmitted. This should be followed by 7-bits of ²don¢t
care² data to complete the instruction. After the ²ERAL²
instruction code has been transmitted, the EEPROM
data will be erased when the CS bit is cleared to zero.
The EEPROM does this by executing an internal
write-cycle. This process takes place internally using
the EEPROM¢s own internal clock and does not require
any action from the SK clock. No further instructions can
be accepted by the EEPROM until this internal
write-cycle has finished. To determine when the write
C S
S ta n d b y
S K
1
D I
0
0
S ta r t b it
E W E N = 1 1
E W D S = 0 0
X X X X X X X - - 7 - b it d o n 't c a r e
EWEN/EWDS Timing
tC
D S
V e r ify
C S
S ta n d b y
S K
D I
1
S ta r t b it
0
0
1
0
X X X X X X X - - 7 - b it d o n 't c a r e
tS V
B u s y
D O
tP
R
ERAL Timing
Rev. 1.50
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July 28, 2009
HT48F50E
tC
D S
V e r ify
C S
S ta n d b y
S K
D I
1
S ta r t b it
0
0
0
D 7
1
D 0
X X X X X X X - - 7 - b it d o n 't c a r e
tS V
B u s y
D O
tP
R
WRAL Timing
ERASE
Internal Write Cycle
The ²ERASE² instruction is used to erase data at a
specified address. The data at the address specified will
be set to ²1². To instigate an ²ERASE² instruction, the
CS bit should be set high, followed by a high start bit and
then the instruction code ²11², all transmitted via the DI
bit. For this device, a dummy bit must be inserted between the last bit of the instruction code and the MSB of
the address. The address information should then follow
with the MSB bit being transmitted first. After all the
²ERASE² instruction code and address have been
transmitted, the data at the specified address will be
erased when the CS bit is cleared to zero. The
EEPROM does this by executing an internal write cycle
which will set all data at the specified address to ²1².
This process takes place internally using the
EEPROM¢s own internal clock and does not require any
action from the SK clock. No further instructions can be
accepted by the EEPROM until the write cycle has finished. To determine when the write cycle has ended, the
CS should be again brought high and the DO bit polled.
If the DO bit is low this indicates that the write-cycle is
still in progress, however, the DO bit will change to a
high value when the write-cycle has ended. Before an
²ERASE² instruction is transmitted, an ²EWEN² instruction must have been transmitted at some point earlier to
ensure that the erase/write function of the EEPROM is
enabled.
The write or erase instructions, ²WRITE², ²ERASE²,
²ERAL² or ²WRAL² will all use the EEPROM¢s internal
write cycle function. As this function is completely internally timed, the SK clock is not required. As the MCU has
no control over the timing of this write cycle, it must still
have some way of knowing when the internal write cycle
has completed. This is because, when the internal write
cycle is executing, the EEPROM will not accept any further instructions from the MCU. The MCU must therefore
wait until the write cycle has finished before sending any
further instructions.
One way for the MCU to know when the write cycle has
terminated is to poll the DO bit after the CS bit has issued a low pulse. The low going edge of this CS bit
pulse will initiate the internal write cycle, when the bit is
returned high the DO bit will go low to indicated that the
write cycle is in progress. When the DO bit returns high
this indicates that the internal write cycle has ended and
that the EEPROM is ready to receive further instructions.
tC
D S
V e r ify
C S
S ta n d b y
S K
D I
1
1
1
A 7
A 6
A 5
A 1
A 0
S ta r t b it
tS
V
B u s y
D O
tP
R
ERASE Timing
Rev. 1.50
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HT48F50E
Is s u e in s tr u c tio n
A d d re s s , D a ta
C S
In te r n a l w r ite c y c le in itia te d
tC
D S
d e la y
C S
tS
V
d e la y
D O
N o
D O
= "1 "
w ill g o lo w h e r e to in d ic a te in te r n a l
w r ite c y c le s till in p r o g r e s s
Y e s
In te r n a l w r ite
c y c le fin is h e d
Internal Write Cycle Busy Polling
Initialising the EEPROM
gle address in the EEPROM. The initialisation
procedure can then be terminated by issuing an EWDS
instruction, however at this point, if actual user data is to
be imminently written to the EEPROM, this last step is
optional.
After the MCU is powered on and if the EEPROM is to
be used, it must be initialised in a specific way before
any user instructions are transmitted. This is achieved
by first transmitting an EWEN instruction, then by issuing a WRITE instruction to write random data to any sin-
The following is an example program of how this can be implemented:
mov
A,01h
mov
BP,A
; set to bank 1
mov
A,40h
mov
MP1,A
; set MP1 to EECR address
call EWEN
; subroutine to run EWEN instructions
mov
A, 7Fh
mov
EEADDR, A
mov
A, 55h
mov
EEDATA, A
call WRITE
; subroutine to run WRITE instruction
; write 55h data to address 7Fh
call EWDS
; optional subroutine to run EWDS instruction
EEPROM Program Examples
The following short programs gives examples of how to send instructions, read and write to the EEPROM. These programs can form a basis of understanding as to how the internal EEPROM memory is to be used to store and retrieve
data.
Example 1 - Definitions and Sending Instructions to the EEPROM
_CS
EQU
IAR1.4
; EEPROM lines setup to have a corresponding
_SK
EQU
IAR1.5
; Bit in the Indirect Addressing Register IAR1
_DI
EQU
IAR1.6
; EEPROM can only be indirectly addressed using
; MP1
_DO
EQU
IAR1.7
_EECR EQU
40H
; Setup address of the EEPROM control register
C_Addr_Length
EQU 8
; Address length - 8-bits
C_Data_Length
EQU 8
; Data length - always 8-bits
;
DATA .SECTION at 70h ¢DATA¢
EE_command
DB ?
; Stores the read or write instruction
; information
ADDR
DB
?
; Store write data or read data address
WR_Data
DB ?
; Store read or write data
COUNT
DB
?
; Temporary counter
;
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20
July 28, 2009
HT48F50E
WriteCommand:
MOV
A,3
MOV
SET
COUNT,A
_SK
CLR
_SK
WriteCommand_0:
CLR
_DI
SZ
EE_command.7
SET
_DI
SET
_SK
CLR
_SK
CLR
C
RLC
EE_command
SDZ
COUNT
JMP
WriteCommand_0
CLR
_DI
RET
; Write instruction code subroutine
; Read, write and erase instructions are 3 bits
; long
; Dummy bit transmission for 256x8 bit EEPROM Memory
; capacity
; Not required for 128x8 bit EEPROM Memory capacity devices
; Prepare the transmitted bit
; Check value of highest instruction code bit
; Get next bit of instruction code
; Check if last bit has been transmitted
Example 2 - Transmitting an Address to the EEPROM
WriteAddr:
; Write address subroutine
MOV
A,C_Addr_Length
; Setup address length
MOV
COUNT,A
SET
_SK
; Dummy bit transmission for 256´8 bit EEPROM Memory
; capacity
CLR
_SK
; Not required for 128x8 bit EEPROM Memory capacity devices
WriteAddr_0:
CLR
_DI
SZ
ADDR.7
; Check value of address MSB
SET
_DI
CLR
C
RLC
ADDR
; Get next address bit
SET
_SK
CLR
_SK
SDZ
COUNT
; Check if address LSB has been written
JMP
WriteAddr_0
CLR
_DI
RET
Example 3 - Writing Data to the EEPROM
WriteData:
MOV
A,C_Data_Length
; Setup data length
MOV
COUNT,A
WriteData_0:
CLR
_DI
SZ
WR_Data.7
; Check value of data MSB
SET
_DI
CLR
C
RLC
WR_Data
; Get next address bit
SET
_SK
CLR
_SK
SDZ
COUNT
; Check if data LSB has been written
JMP
WriteData_0
CLR
_CS
; CS low edge initiates internal write cycle
SET
_CS
; CS high edge allows DO to be used to indicate
; end of write cycle
SNZ
_DO
; Poll for DO high to indicate end of write
; cycle
JMP
$-1
RET
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HT48F50E
Example 4 - Reading Data from the EEPROM
ReadData:
MOV
A,C_Data_Length
; Setup data length
MOV
COUNT,A
CLR
WR_Data
ReadData_0:
CLR
C
RLC
WR_Data
SET
_SK
SZ
_DO
; check value of data MSB
SET
WR_Data.0
CLR
_SK
SDZ
COUNT
; check if LSB has been received
JMP
ReadData_0
MOV
A,WR_Data
RET
Input/Output Ports
other low-power applications. Various methods exist to
wake-up the microcontroller, one of which is to change
the logic condition on one of the Port A pins from high to
l o w . A f t e r a ² H A L T ² i n st r u ct i o n f o r ce s t h e
microcontroller into entering a HALT condition, the processor will remain idle or in a low-power state until the
logic condition of the selected wake-up pin on Port A
changes from high to low. This function is especially
suitable for applications that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature.
Holtek microcontrollers offer considerable flexibility on
their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins,
the user is provided with an I/O structure to meet the
needs of a wide range of application possibilities.
This device provides 33 bidirectional input/output lines
labeled with port names PA, PB, PC, PD and PG. These
I/O ports are mapped to the RAM Data Memory with
specific addresses as shown in the Special Purpose
Data Memory table. All of these I/O ports can be used
for input and output operations. For input operation,
these ports are non-latching, which means the inputs
must be ready at the T2 rising edge of instruction ²MOV
A,[m]², where m denotes the port address. For output
operation, all the data is latched and remains unchanged until the output latch is rewritten.
I/O Port Control Registers
Each I/O port has its own control register PAC, PBC,
PCC, PDC and PGC, to control the input/output configuration. With this control register, each CMOS output or
input with or without pull-high resistor structures can be
reconfigured dynamically under software control. Each
pin of the I/O ports is directly mapped to a bit in its associated port control register. For the I/O pin to function as
an input, the corresponding bit of the control register
must be written as a ²1². This will then allow the logic
state of the input pin to be directly read by instructions.
When the corresponding bit of the control register is
written as a ²0², the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions
can still be used to read the output register. However, it
should be noted that the program will in fact only read
the status of the output data latch and not the actual
logic status of the output pin. Note that there is an additional configuration option for Port A that can select
whether the inputs on this port are Schmitt Trigger types
or non-Schmitt Trigger types. Inputs for the other ports
are all Schmitt Trigger type.
Pull-high Resistors
Many product applications require pull-high resistors for
their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, all I/O pins, when configured as an input have
the capability of being connected to an internal pull-high
resistor. These pull-high resistors are selectable via
configuration options and are implemented using a
weak PMOS transistor. Note that if the pull-high option
is selected, then all I/O pins on that port will be connected to pull-high resistors, individual pins cannot be
selected for pull-high resistor options.
Port A Wake-up
Each device has a HALT instruction enabling the
microcontroller to enter a Power Down Mode and preserve power, a feature that is important for battery and
Rev. 1.50
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HT48F50E
· External Timer/Event Counter Input
Pin-shared Functions
This device contains an 8-bit Timer/Event Counter 0
which has an external pin known as TMR0 and a
16-bit Timer/Event Counter 1 which has an external
pin known as TMR1. These two external timer pins
are individual input pins in 48-pin package but are
pin-shared with I/O pin PC0 or PC5 in 28-pin package
by internal wire bond. If these shared pins are to be
used as Timer/Event Counter inputs, then the
Timer/Event Counters must be configured to be in the
Event Counter or Pulse Width Measurement Mode.
This is achieved by setting the appropriate bits in the
relevant Timer/Event Counter Control Registers.
These pins must also be setup as inputs by setting the
appropriate bits in the Port Control Register. Pull-high
resistor option can also be selected via the appropriate port pull-high configuration option. If these shared
pins are to be used as normal I/O pins, then the external timer input functions must be disabled, by ensuring that the corresponding Timer/Event Counters are
configured to be in the Off Mode or Timer Mode.
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design
constraints on designers but by supplying pins with
multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the
multi-function I/O pins is set by configuration options
while for others the function is set by application program control.
· Buzzer
The buzzer pins BZ and BZ are pin-shared with I/O
pins PB0 and PB1. The buzzer function is selected via
a configuration option and remains fixed after the device is programmed. Note that the corresponding bits
of the port control register, PBC, must setup the pins
as outputs to enable the buzzer outputs. If the PBC
port control register has setup the pins as inputs, then
the pins will function as normal logic inputs with the
usual pull-high options, even if the buzzer configuration option has been selected.
· I/O Pin Structures
The following diagrams illustrate the I/O pin internal
structures. As the exact logical construction of the I/O
pin may differ from these drawings, they are supplied
as a guide only to assist with the functional understanding of the I/O pins. Note also that the specified
pins refer to the largest device package, therefore not
all pins specified will exist on all devices.
· External Interrupt Input
The external interrupt pin INT is pin-shared with the
I/O pin PG0. For the shared function pin to operate as
an external interrupt pin and not as a normal I/O pin,
the corresponding external interrupt enable bits in the
INTC interrupt control register must be correctly set.
For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used
as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC register must be disabled.
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P A 0 ~ P A 7
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
R e a d D a ta R e g is te r
S y s te m
U
X
S c h m itt T r ig g e r In p u t O p tio n
W a k e -u p
W a k e - u p O p tio n
PA Input/Output Port
Rev. 1.50
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July 28, 2009
HT48F50E
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
D D
W e a k
P u ll- u p
Q
S
C h ip R e s e t
P B 0 /B Z
P B 1 /B Z
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
P B 0 D a ta B it
B Z ( P B 1 o n ly )
B Z ( P B 0 o n ly )
M
R e a d D a ta R e g is te r
U
X
U
B Z O p tio n
X
PB0~PB1 Input/Output Port
V
P u ll- H ig h
O p tio n
C o n tr o l B it
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
W e a k
P u ll- u p
Q
S
C h ip R e s e t
D D
P B 2 ~
P C 0 ~
P D 0 ~
P G 0
IN T /T
S h a re
R e a d C o n tr o l R e g is te r
D a ta B it
Q
D
W r ite D a ta R e g is te r
C K
S
Q
M
R e a d D
IN
T M R
T M R
a ta
T (P
0 (P
1 (P
R e g is
G 0 o n
C 0 o n
C 5 o n
te
ly
ly
ly
r
)
U
P B 7
P C 7
P D 7
M R 0 /T M R 1
d P in s
X
)
)
PB, PC, PD and PG Input/Output Ports
Programming Considerations
instructions, a read-modify-write operation takes place.
The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then
rewrite this data back to the output ports.
Within the user program, one of the first things to consider is port initialization. After a reset, all of the I/O data
and port control registers will be set high. This means
that all I/O pins will default to an input state, the level of
which depends on the other connected circuitry and
whether pull-high options have been selected. If the port
control registers, PAC, PBC, PCC, PDC and PGC, are
then programmed to setup some pins as outputs, these
output pins will have an initial high output value unless
the associated port data registers, PA, PB, PC, PD and
PG, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide
by loading the correct values into the appropriate port
control register or by programming individual bits in the
port control register using the ²SET [m].i² and ²CLR
[m].i² instructions. Note that when using these bit control
Rev. 1.50
T 1
S y s te m
T 2
T 3
T 4
T 1
T 2
T 3
T 4
C lo c k
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
Port A has the additional capability of providing wake-up
functions. When the device is in the Power Down Mode,
various methods are available to wake the device up.
One of these is a high to low transition of any of the Port
A pins. Single or multiple pins on Port A can be setup to
have this function.
24
July 28, 2009
HT48F50E
Timer/Event Counters
being provided on the external timer pin. The pin has the
name TMR0 or TMR1 and is pin-shared with an I/O pin.
Depending upon the condition of the T0E or T1E bit in
the Timer Control Register, each high to low, or low to
high transition on the external timer input pin will increment the Timer/Event Counter by one.
The provision of timers form an important part of any
microcontroller, giving the designer a means of carrying
out time related functions. This device contains two
count-up timers of 8-bit and 16-bit capacities
respectively. As each timer has three different operating
modes, they can be configured to operate as a general
timer, an external event counter or as a pulse width
measurement device. The provision of an internal
prescaler for the 8-bit Timer/Event Counter to the clock
circuitry gives added range to the timer.
Configuring the Timer/Event Counter Input Clock
Source
The Timer/Event Counter¢s clock can originate from various sources. The system clock source is used when the
Timer/Event Counter 0 is in the timer mode or in the
pulse width measurement mode. The system clock is divided by a prescaler, the division ratio of which is conditioned by the Timer Control Register named TMR0C bits
T0PSC2~T0PSC0. The instruction clock source (system clock source divided by 4) is used when the
Timer/Event Counter 1 is in the timer mode or in the
pulse width measurement mode. The external clock
source is used when the Timer/Event Counter is in the
event counting mode, the clock source being provided
on the external timer pin, TMR0 or TMR1. Depending
upon the condition of the T0E or T1E bit, each high to
low, or low to high transition on the external timer pin will
increment the counter by one.
There are two types of registers related to the
Timer/Event Counters. The first is the register that contains the actual value of the Timer/Event Counter and
into which an initial value can be preloaded, and is
known as TMR0, TMR1H or TMR1L. Reading from this
register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer
Control Register, which defines the timer options and
determines how the Timer/Event Counter is to be used,
and has the name TMR0C or TMR1C. This device can
have the timer clocks configured to come from the internal clock sources. In addition, the timer clock source can
also be configured to come from the external timer pins.
The external clock source is used when the Timer/Event
Counter is in the event counting mode, the clock source
D a ta B u s
P r e lo a d R e g is te r
T 0 P S C 2 ~ T 0 P S C 0
(1 /2 ~ 1 /2 5 6 )
fS
Y S
8 - S ta g e P r e s c a le r
T 0 M 1
R e lo a d
T 0 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
T M R 0
O v e r flo w
to In te rru p t
T im e r /E v e n t C o u n te r
T 0 O N
8 - B it T im e r /E v e n t C o u n te r
¸
2
B Z
B Z
T 0 E
8-bit Timer/Event Counter Structure
D a ta B u s
L o w B y te
B u ffe r
T 1 M 1
fS
T M R 1
Y S
/4
1 6 - b it T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
T 1 M 0
T im e r /E v e n t C o u n te r
M o d e C o n tro l
H ig h B y te
T 1 O N
L o w
R e lo a d
O v e r flo w
to In te rru p t
B y te
1 6 - B it T im e r /E v e n t C o u n te r
¸
2
B Z
B Z
T 1 E
16-bit Timer/Event Counter Structure
Rev. 1.50
25
July 28, 2009
HT48F50E
Timer Registers - TMR0, TMR1L/TMR1H
should be written first when preloading data into the
16-bit timer registers. It must also be noted that to read
the contents of the low byte timer register, a read to the
high byte timer register must be executed first to latch
the contents of the low byte timer register into its associated low byte buffer. After this has been done, the low
byte timer register can be read in the normal way. Note
that reading the low byte timer register will result in reading the previously latched contents of the low byte buffer
and not the actual contents of the low byte timer register.
The timer registers are special function registers located
in the Special Purpose RAM Data Memory and are the
places where the actual timer values are stored. For
8-bit Timer/Event Counter 0, this register is known as
TMR0. For 16-bit Timer/Event Counter 1, the timer registers are known as TMR1L and TMR1H. The value in
the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from
the initial value loaded by the preload register to the full
count of FFH for the 8-bit timer or FFFFH for the 16-bit
timer at which point the timer overflows and an internal
interrupt signal is generated. The timer value will then
be reset with the initial preload register value and continue counting.
Timer Control Register - TMR0C, TMR1C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their control register, which has the
name TMR0C or TMR1C. It is the Timer Control Register together with its corresponding timer register that
control the full operation of the Timer/Event Counter.
Before the Timer/Event Counter can be used, it is essential that the Timer Control Register is fully programmed with the right data to ensure its correct
operation, a process that is normally carried out during
program initialisation.
To achieve a maximum full range count of FFH for the
8-bit timer or FFFFH for the 16-bit timer, the preload registers must first be cleared to all zeros. It should be
noted that after power-on, the preload register will be in
an unknown condition. Note that if the Timer/Event
Counter is switched off and data is written to its preload
registers, this data will be immediately written into the
actual timer registers. However, if the Timer/Event
Counter is enabled and counting, any new data written
into the preload data registers during this period will remain in the preload registers and will only be written into
the timer registers the next time an overflow occurs.
To choose which of the three modes the Timer/Event
Counter is to operate in, either in the timer mode, the
event counting mode or the pulse width measurement
mode, bits 7 and 6 of the Timer Control Register, which
are known as the bit pair T0M1/T0M0 or T1M1/T1M0,
must be set to the required logic levels. The Timer/Event
Counter on/off bit, which is bit 4 of the Timer Control
Register and known as T0ON or T1ON, provides the basic on/off control of the Timer/Event Counter. Setting the
bit high allows the Timer/Event Counter to run, clearing
the bit stops it running. For 8-bit Timer/Event Counter 0
with prescaler, bits 0~2 of the Timer Control Register determine the division ratio of the input clock prescaler.
The prescaler bit settings have no effect if an external
clock source is used. If the Timer/Event Counter is in the
event count or pulse width measurement mode, the active transition edge level type is selected by the logic
level of bit 3 of the Timer Control Register which is
known as T0E or T1E.
For the 16-bit Timer/Event Counter which has both low
byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be note
when using instructions to preload data into the low byte
timer register, namely TMR1L, the data will only be
placed in a low byte buffer and not directly into the low
byte timer register. The actual transfer of the data into
the low byte timer register is only carried out when a
write to its associated high byte timer register, namely
TMR1H, is executed. On the other hand, using instructions to preload data into the high byte timer register will
result in the data being directly written to the high byte
timer register. At the same time the data in the low byte
buffer will be transferred into its associated low byte
timer register. For this reason, the low byte timer register
Rev. 1.50
26
July 28, 2009
HT48F50E
b 7
T 0 M 1 T 0 M 0
b 0
T 0 O N
T 0 E
T 0 P S C 2 T 0 P S C 1 T 0 P S C 0
T M R 0 C
R e g is te r
T im e r P r e s c a le r R a te
T 0 P S C 2 T 0 P S C 1 T 0
0
0
0
0
1
0
1
0
0
1
0
1
1
1
1
1
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
S e le c t
P S C 0 T im e r
1 :2
0
1 :4
1
1 :8
0
1 :1
1
1 :3
0
1 :6
1
1 :1
0
1 :2
1
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
R a te
6
2
4
2 8
5 6
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c
T 0 M 0
T 0 M 1
n o
0
0
e v
1
0
tim
0
1
1
1
p u
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
b 7
T 1 M 1 T 1 M 0
b 0
T 1 O N
T 1 E
T M R 1 C
R e g is te r
N o t im p le m e n te d , r e a d a s " 0 "
E v
1 :
0 :
P u
1 :
0 :
e n t C
c o u n
c o u n
ls e W
s ta rt
s ta rt
o u n te r A c tiv e E d g
t o n fa llin g e d g e
t o n r is in g e d g e
id th M e a s u r e m e n
c o u n tin g o n r is in g
c o u n tin g o n fa llin g
e S e le c t
t A c tiv e E d g e S e le c t
e d g e , s to p o n fa llin g e d g e
e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le
1 : e n a b le
0 : d is a b le
N o t im p le m e n te d , r e a d a s " 0 "
O p e r a tin g M o d e S e le c
T 1 M 0
T 1 M 1
n o
0
0
e v
1
0
tim
0
1
p u
1
1
t
m o d
e n t c
e r m
ls e w
e a v a ila b le
o u n te r m o d e
o d e
id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
Rev. 1.50
27
July 28, 2009
HT48F50E
Configuring the Timer Mode
In this mode, the external timer pin, TMR0 or TMR1, is
used as the Timer/Event Counter clock source, however
it is not divided by the internal prescaler. After the other
bits in the Timer Control Register have been setup, the
enable bit T0ON or T1ON, which is bit 4 of the Timer
Control Register, can be set high to enable the
Timer/Event Counter to run. If the Active Edge Select bit
T0E or T1E, which is bit 3 of the Timer Control Register,
is low, the Timer/Event Counter will increment each time
the external timer pin receives a low to high transition. If
the Active Edge Select bit is high, the counter will increment each time the external timer pin receives a high to
low transition. When it is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, INTC, is reset to
zero.
In this mode, the Timer/Event Counter can be utilised to
measure fixed time intervals, providing an internal interrupt signal each time the Timer/Event Counter overflows. To operate in this mode, the Operating Mode
Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the Timer
Control Register must be set to the correct value as
shown.
Bit7 Bit6
Control Register Operating Mode
Select Bits for the Timer Mode
1
0
In this mode the internal clock, fSYS is used as the internal clock for 8-bit Timer/Event Counter 0 and fSYS/4 is
used as the internal clock for 16-bit Timer/Event Counter 1. However, the clock source, fSYS, for 8-bit timer is
further divided by a prescaler, the value of which is det e rm in e d b y t h e P r es c al e r R a t e S e l e ct b i t s
T0PSC2~T0PSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control
Register have been setup, the enable bit T0ON or
T1ON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter to run.
Each time an internal clock cycle occurs, the
Timer/Event Counter increments by one. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, INTC, is reset to zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as an event
counter input pin, two things have to happen. The first is
to ensure that the Operating Mode Select bits in the
Timer Control Register place the Timer/Event Counter in
the Event Counting Mode, the second is to ensure that
the port control register configures the pin as an input. It
should be noted that in the event counting mode, even if
the microcontroller is in the Power Down Mode, the
Timer/Event Counter will continue to record externally
changing logic events on the timer input pin. As a result
when the timer overflows it will generate a timer interrupt
and corresponding wake-up source.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be recorded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair, T0M1/T0M0
or T1M1/T1M0, in the Timer Control Register must be
set to the correct value as shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Configuring the Pulse Width Measurement Mode
In this mode, the Timer/Event Counter can be utilised to
measure the width of external pulses applied to the external timer pin. To operate in this mode, the Operating
Mode Select bit pair, T0M1/T0M0 or T1M1/T1M0, in the
Timer Control Register must be set to the correct value
as shown.
Bit7 Bit6
0
1
Control Register Operating Mode
Bit7 Bit6
Select Bits for the Pulse Width Measure1
1
ment Mode
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+ 1
Timer Mode Timing Diagram
E x te r n a l T im e r
P in In p u t
T 0 E o r T 1 E = 1
In c re m e n t
T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
Event Counter Mode Timing Diagram
Rev. 1.50
28
July 28, 2009
HT48F50E
In this mode the internal clock, fSYS is used as the internal clock for 8-bit Timer/Event Counter 0 and fSYS/4 is
used as the internal clock for 16-bit Timer/Event Counter 1. However, the clock source, fSYS, for 8-bit timer is
further divided by a prescaler, the value of which is det e rm in e d b y t h e P r es c al e r R a t e S e l e ct b i t s
T0PSC2~T0PSC0, which are bits 2~0 in the Timer Control Register. After the other bits in the Timer Control
Register have been setup, the enable bit T0ON or
T1ON, which is bit 4 of the Timer Control Register, can
be set high to enable the Timer/Event Counter, however
it will not actually start counting until an active edge is received on the external timer pin.
Timer/Event Counter is full and overflows, an interrupt
signal is generated and the Timer/Event Counter will reload the value already loaded into the preload register
and continue counting. The interrupt can be disabled by
ensuring that the Timer/Event Counter Interrupt Enable
bit in the Interrupt Control Register, INTC, is reset to
zero.
As the external timer pin is shared with an I/O pin, to ensure that the pin is configured to operate as a pulse
width measurement pin, two things have to happen. The
first is to ensure that the Operating Mode Select bits in
the Timer Control Register place the Timer/Event Counter in the Pulse Width Measurement Mode, the second
is to ensure that the port control register configures the
pin as an input.
If the Active Edge Select bit T0E or T1E, which is bit 3 of
the Timer Control Register, is low, once a high to low
transition has been received on the external timer pin,
TMR0 or TMR1, the Timer/Event Counter will start
counting until the external timer pin returns to its original
high level. At this point the enable bit will be automatically reset to zero and the Timer/Event Counter will stop
counting. If the Active Edge Select bit is high, the
Timer/Event Counter will begin counting once a low to
high transition has been received on the external timer
pin and stop counting when the external timer pin returns to its original low level. As before, the enable bit
will be automatically reset to zero and the Timer/Event
Counter will stop counting. It is important to note that in
the Pulse Width Measurement Mode, the enable bit is
automatically reset to zero when the external control
signal on the external timer pin returns to its original
level, whereas in the other two modes the enable bit can
only be reset to zero under program control.
Programmable Frequency Divider (PFD) and Buzzer
Application
Operating similar to a programmable frequency divider,
the buzzer function within the microcontroller provides a
means of producing a variable frequency output suitable
for applications, such as piezo-buzzer driving or other
interfaces requiring a precise frequency generator.
The BZ and BZ are a complimentary pair and pin-shared
with I/O pins, PB0 and PB1. The function is selected via
configuration option, however, if not selected, the pins
can operate as normal I/O pins. Note that the BZ pin is
the inverse of the BZ pin generating a kind of differential
output and supplying more power to connected interfaces such as buzzers.
The clock source for the buzzer circuit can come from
the timer 0 or timer 1 overflow signal selected via the
configuration option. The output frequency is controlled
by loading the required values into the timer prescaler
and timer registers to give the required division ratio.
The counter will begin to count-up from this preload register value until full, at which point an overflow signal is
generated, causing both the BZ and BZ outputs to
change state. The counter will then be automatically reloaded with the preload register value and continue
counting-up.
The residual value in the Timer/Event Counter, which
can now be read by the program, therefore represents
the length of the pulse received on the external timer
pin. As the enable bit has now been reset, any further
transitions on the external timer pin will be ignored. Not
until the enable bit is again set high by the program can
the timer begin further pulse width measurements. In
this way, single shot pulse measurements can be easily
made.
It should be noted that in this mode the Timer/Event
Counter is controlled by logical transitions on the external timer pin and not by the logic level. When the
If the configuration option has selected the buzzer function, then for both buzzer outputs to operate, it is essen-
E x te r n a l T im e r
P in In p u t
T 0 O N o r T 1 O N
( w ith T 0 E o r T 1 E = 0 )
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o u n te r
+ 1
T im e r
+ 2
+ 3
+ 4
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f T 1 .
Pulse Width Measure Mode Timing Diagram
Rev. 1.50
29
July 28, 2009
HT48F50E
T im e r O v e r flo w
B u z z e r C lo c k
P B 0 D a ta
B Z O u tp u t a t P B 0
B Z O u tp u t a t P B 1
PFD Output Control
Programming Considerations
tial that the Port B control register PBC bit 0 and PBC bit
1 are setup as outputs. If only one pin is setup as an output, the other pin can still be used as a normal data input
pin. However, if both pins are setup as inputs then the
buzzer will not function. The buzzer outputs will only be
activated if bit PB0 is set to ²1². This output data bit is
used as the on/off control bit for the buzzer outputs.
Note that the BZ and BZ outputs will both be low if the
PB0 output data bit is cleared to ²0². The condition of
data bit PB1 has no effect on the overall control of the
BZ and BZ pins.
When configured to run in the timer mode, the internal
system clock and instruction clock (system clock divided
by 4) are used as the internal timer clock sources for
8-bit and 16-bit timers resepctively and are therefore
synchronized with the overall operation of the
microcontroller. In this mode, when the appropriate
timer register is full, the microcontroller will generate an
internal interrupt signal directing the program flow to the
respective internal interrupt vector. For the pulse width
measurement mode, the internal system clock or instruction clock is also used as the timer clock source but
the timer will only run when the correct logic condition
appears on the external timer input pin. As this is an external event and not synchronised with the internal timer
clock, the microcontroller will only see this external
event when the next timer clock pulse arrives. As a result there may be small differences in measured values
requiring programmers to take this into account during
programming. The same applies if the timer is configured to be in the event counting mode which again is an
external event and not synchronised with the internal
system or timer clock.
Using this method of frequency generation, and if a
crystal oscillator is used for the system clock, very precise values of frequency can be generated.
Prescaler
The 8-bit timer in the device possesses a prescaler. Bits
2~0 of the Timer Control Register TMR0C, named
T0PSC2~T0PSC0,define the prescaling stages of the
internal clock source of the 8-bit Timer/Event Counter.
I/O Interfacing
The Timer/Event Counter, when configured to run in the
event counter or pulse width measurement mode, requires the use of an external pin for correct operation.
As the external timer pin is pin-shared with an I/O pin, it
must be configured correctly to ensure it is setup for use
as a Timer/Event Counter input and not as a normal I/O
pin. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width
measurement mode. In 28-pin package, the associated
Port Control Register bits for the external timer input
pins must be set high to ensure that these pins are setup
as an inputs. Any pull high configuration for these pins
will remain valid even if these pins are used as
Timer/Event Counter inputs. In 48-pin package, the external timer input pins are independent pins without
pull-high resistors and not pin-shared with I/O pins.
There are not any Port Control Register bits that will affect the Timer/Event Counters function.
Rev. 1.50
When the Timer/Event Counter is read or if data is written to the preload registers, the clock is inhibited to
avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are
properly initialised before using them for the first time.
The associated timer interrupt enable bits in the interrupt control register must be properly set otherwise the
internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source
control bits in timer control register must also be correctly set to ensure the timer is properly configured for
the required application. It is also important to ensure
that an initial value is first loaded into the timer register
before the timer is switched on; this is because after
power-on the initial value of the timer register is unknown. After the timer has been initialised the timer can
be turned on and off by controlling the enable bit in the
30
July 28, 2009
HT48F50E
timer control register. Note that setting the timer enable
bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit
modification, may lead to improper timer operation if executed as a single timer control register byte write instruction.
Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be
woken up from its Power-down condition. To prevent
such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the
HALT instruction to enter the Power Down Mode.
Timer Program Example
When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control
register will be set. If the timer interrupt is enabled this
will in turn generate an interrupt signal. However irrespective of whether the timer interrupt is enabled or not,
a Timer/Event counter overflow will also generate a
wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter
is in the Event Counting Mode and if the external signal
continues to change state. In such a case, the
org
reti
org
jmp
org
jmp
04h
This program example shows how the Timer/Event
Counter registers are setup, along with how the interrupts are enabled and managed. Note how the
Timer/Event Counter is turned on, by setting bit 4 of the
Timer Control Register. The Timer/Event Counter can
be turned off in a similar way by clearing the same bit.
This example program sets the Timer/Event Counter
tobe in the timer mode, which uses the internal system
clock as the clock source.
; external interrupt vector
08h
; Timer/Event Counter 0 interrupt vector
tmr0int
; jump here when Timer/Event Counter 0 overflows
0ch
; Timer/Event Counter 1 interrupt vector
tmr1int
; jump here when Timer/Event Counter 1 overflows
:
org
20h
; main program
:
;internal Timer/Event Counter 0 interrupt routine
tmr0int:
:
; Timer/Event Counter 0 main program placed here
:
reti
:
;internal Timer/Event Counter 1 interrupt routine
tmr1int:
:
; Timer/Event Counter 1 main program placed here
:
reti
:
begin:
;setup Timer/Event Counter 0 registers
mov
a,09bh
; setup preload value for Timer/Event Counter 0 - timer counts from
; this value to FFH
mov
tmr0,a ;
mov
a,081h
; setup Timer control register TMR0C
mov
tmr0c,a
; timer mode and prescaler set to /4
;setup Timer/Event
mov
a,09bh
mov
tmr1l,a
mov
a,0e8h
mov
tmr1h,a
mov
a,080h
mov
tmr1c,a
Counter 1 registers
; setup low byte preload value for Timer/Event Counter 1
; low byte must be setup before high byte
; setup high byte preload value for Timer/Event Counter 1
;
; setup Timer control register TMR1C
; Timer/Event Counter 1 has no prescaler and clock source is fSYS/4
; setup interrupt register
mov
a,00dh ; enable master interrupt and timer interrupts
mov
intc,a
:
set
tmr0c.4
; start Timer/Event Counter 0 - note mode bits must be previously setup
set
tmr1c.4
; start Timer/Event Counter 1 - note mode bits must be previously setup
Rev. 1.50
31
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HT48F50E
Interrupts
with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then
fetch its next instruction from this interrupt vector. The
instruction at this vector will usually be a JMP statement
which will take program execution to another section of
program which is known as the interrupt service routine.
Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated
with a RETI statement, which retrieves the original Program Counter address from the stack and allows the
microcontroller to continue with normal execution at the
point where the interrupt occurred.
Interrupts are an important part of any microcontroller
system. When an external event or an internal function
such as a Timer/Event Counter requires microcontroller
attention, their corresponding interrupt will enforce a
temporary suspension of the main program allowing the
microcontroller to direct attention to their respective
needs. The device contains a single external interrupt
and two internal timer interrupt functions. The external
interrupt is controlled by the action of the external INT
pin, while the internal interrupts are controlled by the
Timer/Event Counters overflow.
Interrupt Register
The various interrupt enable bits, together with their associated request flags, are shown in the following diagram with their order of priority.
Overall interrupt control, which means interrupt enabling
and request flag setting, is controlled by a single INTC
register, which is located in the RAM Data Memory. By
controlling the appropriate enable bits in this register
each individual interrupt can be enabled or disabled.
Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global
enable flag if cleared to zero will disable all interrupts.
Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests occur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
Interrupt Operation
A Timer/Event Counter overflow or the external interrupt
line being pulled low will all generate an interrupt request by setting their corresponding request flag, if their
appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of
the next instruction to be executed, will be transferred
onto the stack. The Program Counter will then be loaded
b 7
b 0
T 1 F
T 0 F
E IF
E T 1 I
E T 0 I
E E I
E M I
IN T C
R e g is te r
M a s te r In te r r u p t G lo b a l E n a b le
1 : g lo b a l e n a b le
0 : g lo b a l d is a b le
E x te r n a l In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 0 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
T im e r /E v e n t C o u n te r 1 In te r r u p t E n a b le
1 : e n a b le
0 : d is a b le
E x te r n a l In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g
1 : a c tiv e
0 : in a c tiv e
N o im p le m e n te d , r e a d a s " 0 "
Interrupt Control Register
Rev. 1.50
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July 28, 2009
HT48F50E
A u to m a tic a lly C le a r e d b y IS R
M a n u a lly S e t o r C le a r e d b y S o ftw a r e
A u to m a tic a lly D is a b le d b y IS R
C a n b e E n a b le d M a n u a lly
P r io r ity
E x te rn a l In te rru p t
R e q u e s t F la g E IF
E E I
T im e r /E v e n t C o u n te r 0
In te r r u p t R e q u e s t F la g T 0 F
E T 0 I
T im e r /E v e n t C o u n te r 1
In te r r u p t R e q u e s t F la g T 1 F
E T 1 I
E M I
H ig h
In te rru p t
P o llin g
L o w
Interrupt Structure
Interrupt Priority
Timer/Event Counter Interrupts
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the
following table shows the priority that is applied. These
can be masked by resetting the EMI bit.
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I or ET1I, must first be set. An
actual Timer/Event Counter interrupt will take place
when the Timer/Event Counter request flag, T0F or T1F,
is set, a situation that will occur when the Timer/Event
Counter overflows. When the interrupt is enabled, the
stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H or 0CH, will take place. When the interrupt is
serviced, the timer interrupt request flag, T0F or T1F, will
be automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Interrupt Source
Priority
External Interrupt
1
Timer/Event Counter 0 Overflow
2
Timer/Event Counter 1 Overflow
3
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the INTC register can prevent simultaneous occurrences.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the INTC register until the corresponding interrupt is serviced or until the request flag is cleared by a
software instruction.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI, must
first be set. An actual external interrupt will take place
when the external interrupt request flag, EIF, is set, a situation that will occur when a high to low transition appears
on the INT line. The external interrupt pin is pin-shared
with an I/O pin PG.0 and can only be configured as an external interrupt pin if the corresponding external interrupt
enable bit in the INTC register has been set. The pin must
also be setup as an input by setting the corresponding
PGC.0 bit in the port control register. When the interrupt
is enabled, the stack is not full and a high to low transition
appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 04H, will take
place. When the interrupt is serviced, the external interrupt request flag, EIF, will be automatically reset and the
EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor configuration options on this pin will remain valid even if the pin is used as
an external interrupt input.
Rev. 1.50
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode. Only the
Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the
interrupt service program, which may corrupt the desired control sequence, then the contents should be
saved in advance.
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HT48F50E
Reset and Initialisation
inhibited. After the RES line reaches a certain voltage
value, the reset delay time tRSTD is invoked to provide
an extra delay time after which the microcontroller will
begin normal operation. The abbreviation SST in the
figures stands for System Start-up Timer.
A reset function is a fundamental part of any
microcontroller ensuring that the device can be set to
some predetermined condition irrespective of outside
parameters. The most important reset condition is after
power is first applied to the microcontroller. In this case,
internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready
to execute the first program instruction. After this
power-on reset, certain important internal registers will
be set to defined states before the program commences. One of these registers is the Program Counter,
which will be reset to zero forcing the microcontroller to
begin program execution from the lowest Program
Memory address.
V D D
0 .9 V
R E S
tR
D D
S T D
S S T T im e - o u t
In te rn a l R e s e t
Power-On Reset Timing Chart
For most applications a resistor connected between
VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES
pin should be kept as short as possible to minimise
any stray noise interference.
In addition to the power-on reset, situations may arise
where it is necessary to forcefully apply a reset condition
when the microcontroller is running. One example of this
is where after power has been applied and the
microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain
unchanged allowing the microcontroller to proceed with
normal operation after the reset line is allowed to return
high. Another type of reset is when the Watchdog Timer
overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup.
V D D
1 0 0 k W
R E S
0 .1 m F
V S S
Basic Reset Circuit
For applications that operate within an environment
where more noise is present the Enhanced Reset Circuit shown is recommended.
Another reset exists in the form of a Low Voltage Reset,
LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage
falls below a certain threshold.
0 .0 1 m F
V D D
1 0 0 k W
Reset Functions
R E S
There are five ways in which a microcontroller reset can
occur, through events occurring both internally and externally:
1 0 k W
0 .1 m F
V S S
· Power-on Reset
Enhanced Reset Circuit
The most fundamental and unavoidable reset is the
one that occurs after power is first applied to the
microcontroller. As well as ensuring that the Program
Memory begins execution from the first memory address, a power-on reset also ensures that certain
other registers are preset to known conditions. All the
I/O port and port control registers will power up in a
high condition ensuring that all pins will be first set to
inputs.
Although the microcontroller has an internal RC reset
function, if the VDD power supply rise time is not fast
enough or does not stabilise quickly at power-on, the
internal reset function may be incapable of providing
proper reset operation. For this reason it is recommended that an external RC network is connected to
the RES pin, whose additional time delay will ensure
that the RES pin remains low for an extended period
to allow the power supply to stabilise. During this time
delay, normal operation of the microcontroller will be
More information regarding external reset circuits is
located in Application Note HA0075E on the Holtek
website.
· RES Pin Reset
This type of reset occurs when the microcontroller is
already running and the RES pin is forcefully pulled
low by external hardware such as an external switch.
In this case as in the case of other reset, the Program
Counter will reset to zero and program execution initiated from this point.
R E S
0 .4 V
0 .9 V
D D
D D
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
RES Reset Timing Chart
Rev. 1.50
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July 28, 2009
HT48F50E
· Low Voltage Reset - LVR
Reset Initial Conditions
The microcontroller contains a low voltage reset circuit
in order to monitor the supply voltage of the device,
which is selected via a configuration option. If the supply
voltage of the device drops to within a range of
0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For
a valid LVR signal, a low voltage, i.e., a voltage in the
range between 0.9V~VLVR must exist for greater than the
value tLVR specified in the A.C. characteristics. If the low
voltage state does not exceed 1ms, the LVR will ignore it
and will not perform a reset function.
The different types of reset described affect the reset
flags in different ways. These flags, known as PDF and
TO are located in the status register and are controlled
by various microcontroller operations, such as the
Power Down function or Watchdog Timer. The reset
flags are shown in the table:
TO PDF
L V R
tR
S T D
S S T T im e - o u t
RESET Conditions
0
0
RES reset during power-on
u
u
RES or LVR reset during normal operation
1
u
WDT time-out reset during normal operation
1
1
WDT time-out reset during Power Down
Note: ²u² stands for unchanged
In te rn a l R e s e t
The following table indicates the way in which the various components of the microcontroller are affected after
a power-on reset occurs.
Low Voltage Reset Timing Chart
· Watchdog Time-out Reset during Normal Operation
Item
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except
that the Watchdog time-out flag TO will be set to ²1².
W D T T im e - o u t
tR
S T D
S S T T im e - o u t
In te rn a l R e s e t
WDT Time-out Reset during Normal Operation
Timing Chart
Condition After RESET
Program Counter
Reset to zero
Interrupts
All interrupts will be disabled
WDT
Clear after reset, WDT begins
counting
Timer/Event
Counter
Timer Counter will be turned off
Prescaler
The Timer Counter Prescaler will
be cleared
Input/Output Ports I/O ports will be setup as inputs
· Watchdog Time-out Reset during Power Down
Stack Pointer
The Watchdog time-out Reset during Power Down is
a little different from other kinds of reset. Most of the
conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to
²0² and the TO flag will be set to ²1². Refer to the A.C.
Characteristics for tSST details.
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure
reliable continuation of normal program execution after
a reset occurs, it is important to know what condition the
microcontroller is in after a particular reset occurs. The
following table describes how each type of reset affects
each of the microcontroller internal registers. Note that
where more than one package type exists the table will
reflect the situation for the larger package type.
W D T T im e - o u t
tS
S T
S S T T im e - o u t
WDT Time-out Reset during Power Down
Timing Chart
Rev. 1.50
Stack Pointer will point to the top
of the stack
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July 28, 2009
HT48F50E
HT48F50E
Reset (Power-on)
RES or LVR Reset
WDT Time-out
(Normal Operation)
WDT Time-out
(HALT)
MP0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
MP1
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
PCL
0000 0000
0000 0000
0000 0000
0000 0000
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
Register
TBLH
--xx xxxx
--uu uuuu
--uu uuuu
--uu uuuu
WDTS
0000 0111
0000 0111
0000 0111
uuuu uuuu
STATUS
--00 xxxx
--uu uuuu
-- 1u uuuu
--11 uuuu
INTC
--00 -000
--00 -000
--00 -000
--uu -uuu
TMR0
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
TMR1H
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1L
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PA
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PCC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
uuuu uuuu
PG
---- ---1
---- ---1
---- ---1
---- ---u
PGC
---- ---1
---- ---1
---- ---1
---- ---u
Note:
²u² stands for unchanged
²x² stands for unknown
²-² stands for unimplemented
Rev. 1.50
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HT48F50E
Oscillator
Various oscillator options offer the user a wide range of
functions according to their various application requirements. Two types of system clocks can be selected
while various clock source options for the Watchdog
Timer are provided for maximum flexibility. All oscillator
options are selected through the configuration options.
Crystal Frequency
The two methods of generating the system clock are:
Crystal Oscillator C1 and C2 Values
· External crystal/resonator oscillator
· External RC oscillator
C1
C2
CL
12MHz
TBD
TBD
TBD
8MHz
TBD
TBD
TBD
4MHz
TBD
TBD
TBD
1MHz
TBD
TBD
TBD
Note:
One of these two methods must be selected using the
configuration options.
More information regarding the oscillator is located in
Application Note HA0075E on the Holtek website.
1. C1 and C2 values are for guidance only.
2. CL is the crystal manufacturer specified
load capacitor value.
Crystal Recommended Capacitor Values
External Crystal/Resonator Oscillator
Resonator C1 and C2 Values
Resonator Frequency
The simple connection of a crystal across OSC1 and
OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most
resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two
small value external capacitors, C1 and C2. The exact
values of C1 and C2 should be selected in consultation
C1
C2
3.58MHz
TBD
TBD
1MHz
TBD
TBD
455kHz
TBD
TBD
Note:
C1 and C2 values are for guidance only.
Resonator Recommended Capacitor Values
External RC Oscillator
C 1
In te r n a l
O s c illa to r
C ir c u it
O S C 1
R p
R f
C a
C b
C 2
Using the external system RC oscillator requires that a
resistor, with a value between 24kW and 1MW, is connected between OSC1 and VDD, and a capacitor is connected to ground. The generated system clock divided
by 4 will be provided on OSC2 as an output which can
be used for external synchronization purposes. Note
that as the OSC2 output is an NMOS open-drain type, a
pull high resistor should be connected if it to be used to
monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency
can vary with VDD, temperature and process variations
and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies
are required.For the value of the external resistor ROSC
refer to the Holtek website for typical RC Oscillator vs.
Temperature and VDD characteristics graphics. Note
that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown
on the diagram does not influence the frequency of oscillation.
T o in te r n a l
c ir c u its
O S C 2
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d .
2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic
c a p a c ita n c e o f a r o u n d 7 p F .
Crystal/Resonator Oscillator
with the crystal or resonator manufacturer¢s specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to
assist with oscillation start up.
Internal Ca, Cb, Rf Typical Values @ 5V, 25°C
Ca
Cb
Rf
8pF
10pF
800kW
V
Oscillator Internal Component Values
R
D D
O S C
O S C 1
4 7 0 p F
fS
Y S
/4 N M O S O p e n D r a in
O S C 2
External RC Oscillator
Rev. 1.50
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July 28, 2009
HT48F50E
tion must be made to the I/O pins on the device. All
high-impedance input pins must be connected to either
a fixed high or low level as any floating input pins could
create internal oscillations and result in increased current consumption. Care must also be taken with the
loads, which are connected to I/Os, which are setup as
outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external
circuits that do not draw current, such as other CMOS
inputs. Also note that additional standby current will also
be required if the configuration options have enabled the
Watchdog Timer internal oscillator.
Watchdog Timer Oscillator
The WDT oscillator is a fully self-contained free running
on-chip RC oscillator with a typical period of 65ms at 5V
requiring no external components. When the device enters the Power Down Mode, the system clock will stop
running but the WDT oscillator continues to free-run and
to keep the watchdog active. However, to preserve
power in certain applications the WDT oscillator can be
disabled via a configuration option.
Power Down Mode and Wake-up
Power Down Mode
Wake-up
All of the Holtek microcontrollers have the ability to enter
a Power Down Mode, also known as the HALT Mode or
Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely
low standby current level. This occurs because when
the device enters the Power Down Mode, the system
oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device
maintains its present internal condition, it can be woken
up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power
supply constantly maintained to keep the device in a
known condition but where the power supply capacity is
limited such as in battery applications.
After the system enters the Power Down Mode, it can be
woken up from one of various sources listed as follows:
· An external reset
· An external falling edge on Port A
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, however, if the
device is woken up by a WDT overflow, a Watchdog
Timer reset will be initiated. Although both of these
wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a
system power-up or executing the clear Watchdog
Timer instructions and is set when executing the ²HALT²
instruction. The TO flag is set if a WDT time-out occurs,
and causes a wake-up that only resets the Program
Counter and Stack Pointer, the other flags remain in
their original status.
Entering the Power Down Mode
There is only one way for the device to enter the Power
Down Mode and that is to execute the ²HALT² instruction in the application program. When this instruction is
executed, the following will occur:
Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin
to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the ²HALT² instruction.
· The system oscillator will stop running and the appli-
cation program will stop at the ²HALT² instruction.
· The Data Memory contents and registers will maintain
their present condition.
· The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT
oscillator. The WDT will stop if its clock source originates from the system clock.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related
interrupt is disabled or the interrupt is enabled but the
stack is full, in which case the program will resume execution at the instruction following the ²HALT² instruction.
In this situation, the interrupt which woke-up the device
will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or
when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is
not full, in which case the regular interrupt response
takes place. If an interrupt request flag is set to ²1² before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be
cleared.
Standby Current Considerations
As the main reason for entering the Power Down Mode
is to keep the current consumption of the MCU to as low
a value as possible, perhaps only in the order of several
micro-amps, there are other considerations which must
also be taken into account by the circuit designer if the
power consumption is to be minimized. Special atten-
Rev. 1.50
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July 28, 2009
HT48F50E
source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be
noted that when the system enters the Power Down
Mode, as the system clock is stopped, then the WDT
clock source will also be stopped. Therefore the WDT
will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate
in noisy environments, using the internal WDT oscillator
is therefore the recommended choice.
No matter what the source of the wake-up event is, once
a wake-up situation occurs, a time period equal to 1024
system clock periods will be required before normal system operation resumes. However, if the wake-up has
originated due to an interrupt, the actual interrupt subroutine execution will be delayed by an additional one or
more cycles. If the wake-up results in the execution of
the next instruction following the ²HALT² instruction, this
will be executed immediately after the 1024 system
clock period delay has ended.
Under normal program operation, a WDT time-out will
initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a
WDT time-out occurs, only the Program Counter and
Stack Pointer will be reset. Three methods can be
adopted to clear the contents of the WDT and the WDT
prescaler. The first is an external hardware reset, which
means a low level on the RES pin, the second is using
the watchdog software instructions and the third is via a
²HALT² instruction.
Watchdog Timer
The Watchdog Timer is provided to prevent program
malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events
such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT
clock is supplied by one of two sources selected by configuration option: its own self-contained dedicated internal WDT oscillator, or the instruction clock which is the
system clock divided by 4. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation.
There are two methods of using software instructions to
clear the Watchdog Timer, one of which must be chosen
by configuration option. The first option is to use the single ²CLR WDT² instruction while the second is to use
the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will
clear the WDT while for the second option, both ²CLR
WDT1² and ²CLR WDT2² must both be executed to
successfully clear the WDT. Note that for this second
option, if ²CLR WDT1² is used to clear the WDT, successive executions of this instruction will have no effect,
only the execution of a ²CLR WDT2² instruction will
clear the WDT. Similarly, after the ²CLR WDT2² instruction has been executed, only a successive ²CLR WDT1²
instruction can clear the Watchdog Timer.
The internal WDT oscillator has an approximate period
of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal
period of 17ms. Note that this period can vary with VDD,
temperature and process variations. For longer WDT
time-out periods the WDT prescaler can be utilized. By
writing the required value to bits 0, 1 and 2 of the WDTS
register, known as WS0, WS1 and WS2, longer time-out
periods can be achieved. With WS0, WS1 and WS2 all
equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s.
A configuration option can select the instruction clock,
which is the system clock divided by 4, as the WDT clock
b 7
b 0
W S 2
W S 1
W S 0
W D T S R e g is te r
W D T p r e s c a le r r a te s e le c t
W D T R
W S 0
W S 1
W S 2
1 :1
0
0
0
1 :2
1
0
0
1 :4
0
1
0
1 :8
1
1
0
1 :1
0
0
1
1 :3
1
0
1
1
:6
0
1
1
1 :1
1
1
1
a te
6
2
4
2 8
N o t u s e d
Watchdog Timer Register
Rev. 1.50
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HT48F50E
C L R W D T 1 F la g
C L R W D T 2 F la g
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
1 o r 2 In s tr u c tio n s
fS
Y S
/4
W D T O s c illa to r
C L R
W D T C lo c k S o u r c e
C o n fig u r a tio n O p tio n
C L R
8 - b it C o u n te r
(¸ 2 5 6 )
7 - b it P r e s c a le r
W D T C lo c k S o u r c e
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog Timer
Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the Flash Type Program Memory device during the programming process. During the development process, these options are selected using the
HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later by the application software.
All options must be defined for proper system function, the details of which are shown in the table.
No.
Options
1
Watchdog Timer: enable or disable
2
Watchdog Timer clock source: WDT oscillator or fSYS/4
3
CLRWDT instructions: 1 or 2 instructions
4
PA0~PA7: wake-up enable or disable (bit option)
5
PA, PB, PC, PD and PG: pull-high enable or disable (by port)
6
PA input type: CMOS or Schmitt Trigger
7
Buzzer function: enable or normal I/O
8
Buzzer clock source: Timer 0 or Timer 1
9
System oscillator: Crystal or RC
10
LVR function: enable or disable
Application Circuits
V
D D
V D D
R e s e t
C ir c u it
1 0 0 k W
0 .1 m F
P A 0 ~ P A 7
R E S
P B 2 ~ P B 7
P C 0 ~ P C 7
P D 0 ~ P D 7
P B 0 /B Z
0 .1 m F
P B 1 /B Z
T M R 0
V S S
T M R 1
O S C
C ir c u it
O S C 1
H T 4 8 F 5 0 E
S e e O s c illa to r
S e c tio n
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O S C 2
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Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
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Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
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Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
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Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
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Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
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CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
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CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
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INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
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OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending
when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
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RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
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SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
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HT48F50E
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
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HT48F50E
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.50
52
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HT48F50E
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.50
53
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HT48F50E
Package Information
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
Rev. 1.50
F
I
G
Dimensions in mil
Min.
Nom.
Max.
A
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
¾
¾
375
54
July 28, 2009
HT48F50E
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
a
F
· MS-013
Symbol
Rev. 1.50
Dimensions in mil
Min.
Nom.
Max.
A
393
¾
419
B
256
¾
300
C
12
¾
20
C¢
697
¾
713
D
¾
¾
104
E
¾
50
¾
F
4
¾
12
G
16
¾
50
H
8
¾
13
a
0°
¾
8°
55
July 28, 2009
HT48F50E
28-pin SSOP (150mil) Outline Dimensions
1 5
2 8
A
B
1 4
1
C
C '
G
H
D
E
Symbol
Rev. 1.50
a
F
Dimensions in mil
Min.
Nom.
Max.
A
228
¾
244
B
150
¾
157
C
8
¾
12
C¢
386
¾
394
D
54
¾
60
E
¾
25
¾
F
4
¾
10
G
22
¾
28
H
7
¾
10
a
0°
¾
8°
56
July 28, 2009
HT48F50E
48-pin SSOP (300mil) Outline Dimensions
4 8
2 5
A
B
2 4
1
C
C '
G
H
D
E
Symbol
Rev. 1.50
a
F
Dimensions in mil
Min.
Nom.
Max.
A
395
¾
420
B
291
¾
299
C
8
¾
12
C¢
613
¾
637
D
85
¾
99
E
¾
25
¾
F
4
¾
10
G
25
¾
35
H
4
¾
12
a
0°
¾
8°
57
July 28, 2009
HT48F50E
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
2.0±0.5
24.8+0.3/-0.2
30.2±0.2
SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±1.5
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.50
2.0±0.5
16.8+0.3/-0.2
22.2±0.2
58
July 28, 2009
HT48F50E
SSOP 48W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330.0±1.0
B
Reel Inner Diameter
100.0±0.1
C
Spindle Hole Diameter
13.0+0.5/-0.2
D
Key Slit Width
T1
Space Between Flange
T2
Reel Thickness
Rev. 1.50
2.0±0.5
32.2+0.3/-0.2
38.2±0.2
59
July 28, 2009
HT48F50E
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
P
B 0
K 0
A 0
R e e l H o le
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.5+0.1/-0.0
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
P1
Cavity to Perforation (Length Direction)
A0
Cavity Length
10.85±0.10
B0
Cavity Width
18.34±0.10
K0
Cavity Depth
2.97±0.10
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
21.3±0.1
4.0±0.1
2.0±0.1
SSOP 28S (150mil)
Symbol
Description
Dimensions in mm
16.0±0.3
W
Carrier Tape Width
P
Cavity Pitch
8.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
D
Perforation Diameter
1.55+0.10/-0.00
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
6.5±0.1
B0
Cavity Width
10.3±0.1
K0
Cavity Depth
2.1±0.1
7.5±0.1
t
Carrier Tape Thickness
0.30±0.05
C
Cover Tape Width
13.3±0.1
Rev. 1.50
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HT48F50E
P 0
D
P 1
t
E
F
W
D 1
C
B 0
K 1
P
K 2
A 0
R e e l H o le ( C ir c le )
IC
p a c k a g e p in 1 a n d th e r e e l h o le s
a r e lo c a te d o n th e s a m e s id e .
R e e l H o le ( E llip s e )
SSOP 48W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
32.0±0.3
P
Cavity Pitch
16.0±0.1
E
Perforation Position
1.75±0.10
F
Cavity to Perforation (Width Direction)
14.2±0.1
D
Perforation Diameter
2 Min.
D1
Cavity Hole Diameter
1.50+0.25/-0.00
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
12.0±0.1
B0
Cavity Width
16.2±0.1
K1
Cavity Depth
2.4±0.1
K2
Cavity Depth
3.2±0.1
t
Carrier Tape Thickness
0.35±0.05
C
Cover Tape Width
25.5±0.1
Rev. 1.50
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July 28, 2009
HT48F50E
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor (China) Inc. (Dongguan Sales Office)
Building No. 10, Xinzhu Court, (No. 1 Headquarters), 4 Cuizhu Road, Songshan Lake, Dongguan, China 523808
Tel: 86-769-2626-1300
Fax: 86-769-2626-1311
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538, USA
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2009 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.50
62
July 28, 2009
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