A6282 Datasheet

A6282
16-Channel Constant-Current LED Driver
Features and Benefits
Description
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The A6282 device is designed for LED display applications. This
CMOS device includes an input shift register, accompanying
data latches, and 16 MOS constant current sink drivers.
16 constant-current outputs, up to 50 mA each
LED output voltage up to 12 V
3.0 to 5.5 V logic supply range
Schmitt trigger inputs for improved noise immunity
Power-On Reset (POR), all register bits = 0
Low-power CMOS logic and latches
High data input rate: 30 MHz
Output current accuracy: between channels < ±3% and
between ICs ±7%, over the full operating temperature
range
▪ Internal UVLO and thermal shutdown (TSD) circuitry
The CMOS shift registers and latches allow direct interfacing
with microprocessor-based systems. With a 3.3 or 5 V logic
supply, typical serial data input rates can reach up to 30 MHz.
The LED drive current level can be set by a single external
resistor, selected by the application designer. A serial data
output permits cascading of multiple devices in applications
requiring additional drive lines.
The A6282 is available in two 24-terminal packages: QFN
(package ES) and TSSOP (LP), which have an exposed
thermal pad. Both packages are lead (Pb) free with 100% matte
tin leadframe plating.
Packages:
24-pin TSSOP
with exposed thermal pad
(Package LP)
Applications include the following:
▪ Monocolor, multicolor, or full-color LED display
▪ Monocolor, multicolor, or full-color LED signboard
▪ Display backlighting
▪ Multicolor LED lighting
24-contact QFN
4 mm × 4 mm × 0.75 mm
(Package ES)
Not to scale
Typical Application
VLED
10 μF
10 μF
SDI
Controller
SDI
CLK
CLK
LE
LE
OE
OE
OUT0
OUT15
SDI
SDO
VDD
VDD
100 nF
A6282
GND
REXT
IC 1
CLK
LE
OUT15
SDO
VDD
GND
OE
VDD
100 nF
A6282
REXT
IC 2
Cascaded A6282 devices
6282-DS, Rev. 4
OUT0
A6282
16-Channel Constant-Current LED Driver
Selection Guide
Part Number
Package
Packing
A6282EESTR-T
4 mm × 4 mm QFN, 24 pins, exposed thermal pad
1500 pieces per 7-in. reel
A6282ELPTR-T
TSSOP, 24 pins, exposed thermal pad
4000 pieces per 13 in. reel
Absolute Maximum Ratings
Characteristic
Supply Voltage*
Symbol
Notes
Rating
Unit
VDD
–0.3 to 5.5
V
OUTx Current (any single output)
IO
60
mA
Input Voltage Range*
VI
–0.3 to VDD + 0.3
V
–0.3 to 13.2
V
LED Load Supply Range*
VOE, VLE, VCLK, VSDI
VLED
ESD Rating
Operating Temperature Range (E)
Junction Temperature
Storage Temperature Range
HBM (JEDEC JESD22-A114, Human Body Model)
2.0
kV
CDM (JEDEC JESD22-C101, Charged Device Model)
1.0
kV
–40 to 85
°C
TA
TJ(max)
150
°C
Tstg
–55 to 150
°C
*With respect to ground.
Thermal Characteristics
Characteristic
Package Thermal Resistance
Test Conditions1
ES package, 4-layer PCB based on JEDEC standard
LP packge, 4-layer PCB based on JEDEC standard
Symbol
RθJA
Value
37
28
Units
°C/W
°C/W
*Additional thermal information available on the Allegro website.
Allowable Package Power Dissipation (W)
5.0
4.0
Pa
ck
ag
e
3.0
Pa
ck
LP
,R
QJ
A
ag
eE
S,
28
°C
/W
QJ
2.0
=
R
A
=3
7°
C/
W
1.0
0
25
50
75
100
125
Ambient Temperature (°C)
150
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
2
A6282
16-Channel Constant-Current LED Driver
Functional Block Diagram
VDD
UVLO and TSD
SDI
SDO
Serial - Parallel Shift Register
CLK
OE
Control Logic
Block
LE
Latches
Output Control Drivers
REXT
IO
Regulator
Exposed Pad
(ET and LP packages)
OUT15
GND OUT0 OUT1
VLED
Inputs and Outputs Equivalent Circuits
Resistor values are equivalent resistance and not tested
VDD
CLK, SDI,
LE, Ō¯Ē
500 Ω
VDD
10 Ω
SDO
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
3
A6282
16-Channel Constant-Current LED Driver
Pin-out Diagrams
SDO
19 OUT11
20 OUT12
21 OUT13
22 OUT14
23 OUT15
24 OE
Top-down views
18 OUT10
1
GND 1
24 VDD
SDI 2
23 REXT
CLK 3
22 SDO
LE 4
21 OE
17 OUT9
OUT0 5
16 OUT8
OUT1 6
4
15 OUT7
OUT2 7
18 OUT13
SDI
5
14 OUT6
OUT3 8
17 OUT12
CLK
6
13 OUT5
OUT4 9
16 OUT11
OUT5 10
15 OUT10
OUT6 11
14 OUT9
OUT7 12
13 OUT8
OUT4 12
OUT3 11
9
OUT1
OUT2 10
8
GND
PAD
7
3
LE
2
VDD
OUT0
REXT
ES Package
20 OUT15
PAD
19 OUT14
LP Package
Terminal List Table
CLK
GND
LE
Number
ES
LP
6
3
4
1
7
4
¯¯Ē¯
Ō
24
21
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
OUT10
OUT11
OUT12
OUT13
OUT14
OUT15
PAD
REXT
SDI
SDO
VDD
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
–
2
5
1
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
–
23
2
22
24
Name
Description
Clock; data shift clock input terminal
Logic supply ground and load supply ground
Latch Enable input terminal
Output Enable input terminal, active low (when Ō
¯¯Ē¯ = high, all OUTx outputs are forced off; when Ō
¯¯Ē¯ = low,
on/off status of OUTx outputs is controlled by the state of the latches
Constant current outputs
Exposed pad for enhanced thermal dissipation; not connected internally, connect to GND
Reference current terminal; sets output current for all channels
Serial Data In terminal
Serial Data Out terminal
Logic Supply terminal
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
4
A6282
16-Channel Constant-Current LED Driver
ELECTRICAL CHARACTERISTICS at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic
Logic Supply Voltage Range
LED Load Supply Output Voltage
Undervoltage Lockout
Output Current
Output Current Shift
Output to Output Matching Error3
Output Current Regulation
Output Leakage Current
Logic Input Voltage
Logic Input Voltage Hysteresis
Logic Input Current
SDO Voltage
Supply Current4
Symbol
Test Conditions
Operating
VDD
VLED
Operating
VDD 0 → 5.0 V
VDD(UV)
VDD 5 → 0.0 V
VDD = 4.5 to 5.5 V, VDS(x) = 1 V,
REXT = 374 
VDD = 3.0 to 3.6 V, VDS(x) = 1 V,
REXT = 374 
IO
VDD = 4.5 to 5.5 V, VDS(x) = 1 V,
REXT = 910 
VDD = 3.0 to 3.6 V, VDS(x) = 1 V,
REXT = 910 
VDD = 5.5 V, VDS(x) = 1 V, REXT = 910 Ω,
%∆IO
TA = 25°C; between one output on and
all outputs on
VDS = 1 V, REXT = 374 , all outputs on
Err
VDS = 1 V, REXT = 910 , all outputs on
VDD = 5.5 V, VDS(x) = 1 to 3 V,
REXT = 374 , all outputs on
VDD = 5.5 V, VDS(x) = 1 to 3 V,
REXT = 910 , all outputs on
%IO(reg)
VDD = 3.6 V, VDS(x) = 1 to 3 V,
REXT = 374 , all outputs on
VDD = 3.6 V, VDS(x) = 1 to 3 V,
REXT = 910 , all outputs on
IDSS
VOH = 12 V
VIH
VIL
VIhys
All digital inputs
II
All digital inputs
IOL = 1 mA
VOL
VOH
IOH = –1 mA
REXT = 3.8 k, VOE = 5 V
IDD(OFF) REXT = 910 , VOE = 5 V
REXT = 374 , VOE = 5 V
All outputs on, REXT = 910 , VO = 1 V,
data transfer 30 MHz
IDD(ON)
All outputs on, REXT = 374 , VO = 1 V,
data transfer 30 MHz
Min.
3.0
–
2.5
2.3
Typ.2
5.0
–
2.7
2.5
Max.
5.5
12.0
2.9
2.7
Unit
V
V
V
V
47.4
51.1
54.5
mA
46.5
50.1
53.5
mA
19.8
21.4
22.8
mA
19.5
21.0
22.4
mA
–
–
±1
%
–
–
+1.0
+1.0
+3.0
+3.0
%
%
–
1.7
3
%/V
–
2.4
4
%/V
–
1.2
2
%/V
–
1.8
3
%/V
–
0.8×VDD
GND
250
–1
–
VDD – 0.5
–
–
–
–
–
–
–
–
–
–
–
–
–
0.5
VDD
0.2×VDD
900
1
0.5
–
6
16
40
μA
V
V
mV
μA
V
V
mA
mA
mA
–
–
20
mA
–
–
45
mA
Continued on the next page…
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
5
A6282
16-Channel Constant-Current LED Driver
ELECTRICAL CHARACTERISTICS (continued), at TA1 = 25°C, VDD = 3.0 to 5.5 V, unless otherwise noted
Characteristic
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Reference Voltage at External
Resistor REXT
Symbol
Test Conditions
TJTSD
Temperature increasing
TJTSDhys
VEXT
REXT = 374 
Min.
–
–
Typ.2
165
15
Max.
–
–
Unit
°C
°C
–
1.21
–
V
1Tested
at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
3Err = (I (min or max) – I (av)) / I (av). I (av) is the average current of all outputs. I (min or max) is the output current with the greatest
O
O
O
O
O
difference from IO(av).
4Recommended operating range: V = 1.0 to 3.0 V.
O
2Typical
SWITCHING CHARACTERISTICS at TA1 = 25°C, VDD = VIH = 5.0 V, VDS = 1 V, VIL = 0 V, REXT = 910 Ω, IO = 21.4 mA, VL = 2 V,
RL = 51 Ω, CL = 15 pF (see also Timing Diagrams section)
Characteristic
Symbol
Test Conditions
Clock Frequency
fCLK
CLK
Clock Frequency (cascaded devices)
fCLKC
Min.
Typ.2
Max.
Unit
–
–
30
MHz
CLK
–
–
25
MHz
Clock Pulse Duration
twh0
CLK = high
16
–
–
ns
LE Pulse Duration
twh1
LE = high
20
–
–
ns
tsu0
SDI to CLK↑
10
–
–
ns
tsu1
CLK↑ to LE↑
10
–
–
ns
th0
CLK↑ to SDI
10
–
–
ns
th1
LE↓ to CLK↑
10
–
–
ns
tr0
SDO, 10/90% points (measurement circuit A)
–
–
16
ns
tr1
OUTx, VDD = 5 V,10/90% points (measurement circuit B)
–
10
30
ns
tf0
SDO, 10/90% points (measurement circuit A)
–
–
16
ns
tf1
Setup Time
Hold Time
Rise Time
Fall Time
Propagation Delay Time
Output Enable Pulse Duration
OUTx, VDD = 5 V,10/90% points (measurement circuit B)
–
10
30
ns
tpd0
CLK↑ to SDO↑↓ (measurement circuit A)
–
–
30
ns
tpd1
¯¯Ē
¯ ↓ to OUTx↑↓ (measurement circuit B)
Ō
–
–
60
ns
tpd2
LE↑ to OUTx↑↓ (measurement circuit B)
–
–
60
ns
(see Timing Diagrams section)
60
–
–
ns
tw(OE)
1Tested
at 25°C. Specifications are assured by design and characterization over the operating temperature range of –40°C to 85°C.
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for
individual units, within the specified maximum and minimum limits.
2Typical
Parameter Measurement Circuits
VL
A6282
A6282
RL
SDO
OUTx
CL
15 pF
(A) Circuit for tf0 , tpd0 , and tr0
(B) Circuit for tf1 , tpd1 , tpd2 , and tr1 .
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
6
A6282
16-Channel Constant-Current LED Driver
Timing Diagrams
Normal Operation
t wh0
CLK
t
su0
t h0
SDI
t pd0
t
10%
SDO
t
t
r0
f0
90%
50%
t wh1
su1
LE
Low = All Outputs Enabled
OE
t pd2
H ig h = O u tp u t o n
OUTx
(current)
Low = Output off
Disabling Outputs
t w (OE)
OE
50%
50%
t pd1
OUTx
(current)
t pd1
t
f1
t
r1
90%
50%
10%
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
7
A6282
16-Channel Constant-Current LED Driver
Operating Characteristics
Channel Maximum Constant Output Current
versus External Reference Resistance
Channel Output Current versus Output Voltage
VDD = 5.0 V
60
50
45
50
35
4.5 to 5.0
3.0 to 3.6
IO (mA)
IO(max) (mA)
VDD (V)
40
REXT = 470 Ω
40
30
30
25
REXT = 910 Ω
20
20
15
10
10
5
0
0.3
0
1.0
2.0
3.0 4.0 5.0
0
0.3 0.6
0.9 1.2
REXT (kΩ)
1.5 1.8 2.1
2.4 2.7
3.0
VDS (V)
Input-Output Truth Table
Serial
Data
Input
(SDI)
Shift Register Contents
Clock
Input
(CLK)
I0
I1
I2
…
I15
Serial
Data
Out
(SDO)
H
H R0 R1 …
R15
R14
L
L R0 R1 …
R15
R14
X
R0 R1 R2 …
R15
R15
X
X
X X
…
P0 P1 P2 …
P15
Latch
Enable
Input
(LE)
X
L
P15
H
Latch Contents
I0
I1
I2
…
R0 R1 R2 …
P15
I15
X X
…
Output Contents
I15
L
(Outputs on)
P15
I0
I1
I2
…
R15
P0 P1 P2 …
X
Output
Enable
Input
¯¯Ē¯ )
( Ō
X
H
(Outputs off)
P0 P1 P2 …
H
H H …
H
L = Low logic (voltage) level, H = High logic (voltage) level, X = Don’t care, P = Present state, R = Previous state
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
8
A6282
16-Channel Constant-Current LED Driver
Functional Description
Normal Operation
Serial data present at the SDI (Serial Data In) input is transferred
to the shift register on the transition from logic 0 to logic 1 of the
CLK (Clock) input pulse. On succeeding CLK pulses, the register
shifts data towards the SDO (Serial Data Out) output. The serial
data must appear at the input prior to the rising edge of the CLK
waveform.
Data present in any register is transferred to the respective latch
when the LE (Latch Enable) input is high (serial-to-parallel conversion). The latches continue to accept new data as long as LE is
held high (level triggered).
Applications where the latches are bypassed (LE tied high)
¯ (Output Enable) input be high during serial
require that the Ō¯¯Ē
¯ is high, the output sink drivers are disabled
data entry. When Ō¯¯Ē
(off). The data stored in the latches is not affected by the state
¯ . With Ō¯¯Ē
¯ active (low), the outputs are controlled by the
of Ō¯¯Ē
state of their respective latches.
Setting Maximum Channel Current
The maximum output current per channel is set by a single external resistor, REXT, which is placed between the REXT pin and
GND. The voltage on REXT, VEXT, is set by an internal band gap
and is 1.21 V, typical.
The maximum channel output current can be calculated as:
IO(max) = (18483.1/ REXT) + 0.67 , for VDD = 3.0 to 3.6 V ,
or
IO(max) = (18841.2/ REXT) + 0.68 , for VDD = 4.5 to 5.5 V ,
where REXT is the value of the user-selected external resistor,
which should not be less than 374 Ω.
A chart of the maximum per channel (OUT0 to OUT15) constant
output current, IO(max), at various values of REXT , is shown in
the Operating Characteristics section.
Undervoltage Lockout
The A6282 includes an internal undervoltage lockout (UVLO)
circuit that disables the outputs in the event that the logic supply
voltage drops below a minimum acceptable level. This feature
prevents the display of erroneous information, a necessary function for some critical applications. Upon recovery of the logic
supply voltage after a UVLO event, all internal shift registers and
latches are set to 0. The A6282 is then in normal mode.
Thermal Shutdown Protection
If the junction temperature exceeds the threshold temperature,
TJTSD , 165°C typical, the outputs will be turned off until the junction temperature cools down through the thermal shutdown hysteresis, 15°C typical. The shift register and output latches register
will remain active during a thermal shutdown event. Therefore,
there is no need to reset the data in the output latches.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
A6282
16-Channel Constant-Current LED Driver
Application Information
Load Supply Voltage (VLED)
This device is designed to operate with driver voltage drops (VDS)
of 1.0 to 3.0V. If higher voltages are dropped across the driver,
package power dissipation will increase. To minimize package
power dissipation, it is recommended to use the lowest possible
load supply voltage, VLED, or to set a series voltage drop, VDROP ,
according to the following formula:
VDROP = VLED – VF – VDS ,
where VF is the LED forward voltage. For reference, typical LED
forward voltages are:
LED Type
VF (V)
White
Blue
Green
Yellow
Amber
Red
Infrared
UV
3.5 to 4.0
3.0 to 5.5
1.8 to 2.5
2.0 to 2.5
1.9 to 3.0
1.6 to 2.5
1.2 to 1.8
3.0 to 4.0
1. Place the REXT resistor as close as possible to the REXT
pin and GND pin. This will minimize parasitic inductance and
capacitance.
2. Use a separate line to the device GND pin for REXT, and separate lines for the decoupling capacitors. The lines should join at
ground. This star grounding will improve output load regulation
and minimize any chance of oscillation.
The REXT ground line should carry only the small current from
the internal voltage reference at REXT. The high AC currents
flowing through the decoupling capacitors and their resistive and
inductive PCB lines cause noise (ground bounce) on the capacitor
ground lines. Such noise could disturb the reference voltage at
REXT and promote oscillation. Connect the exposed thermal pad
of the ES and LP packages to the power ground, along with the
decoupling capacitors, and not to the ground line for REXT.
3. Keep the output drive lines (OUT0 through OUT15) away
from the REXT pin to avoid coupling of the output signal into
the reference for the current sources. Output lines should not run
adjacent to the REXT pin or directly under the REXT pin.
VDROP = IO× RDROP for a single driver, for a Zener diode (VZ),
or for a series string of silicon diodes (approximately 0.7 V per
diode) for a group of drivers (these configurations are shown
in the figure below). If the available voltage source will cause
unacceptable power dissipation and series resistors or diodes are
undesirable, a voltage regulator can be used to provide VLED.
4. Use decoupling capacitors on the VDD pin and the LED supply bus. Place the logic decoupling capacitor (0.1 μF, one for
each A6282) as close as possible to the VDD pin. Use at least one
10 μF capacitor from the LED supply line to device ground for at
least every two A6282s.
Pattern Layout
To save pins and board space, the A6282 uses one pin for both
logic ground and power ground. Therefore, achieving optimal
performance requires careful attention to layout. Following the
suggestions below will improve the analog performance and logic
noise immunity.
Package Power Dissipation
The maximum allowable package power dissipation based on
package type is determined by:
VLED
VLED
VLED
VDROP
VDROP
VDROP
VF
VF
VF
VDS
VDS
VDS
Typical application voltage drops
5. Use multilayer boards if possible.
PD(max) = (150 – TA) / RJA ,
where RJA is the thermal resistance of the package, determined
experimentally. Power dissipation levels based on the package are
shown in the Thermal Characteristics table.
The actual package power dissipation is determined by:
PD(act) = DC × (VDS × IO× 16) + (VDD× IDD) ,
where DC is the duty cycle. The value 16 is the maximum
number of available device outputs, representing the worst-case
scenario (displaying all 16 LEDs). When the load supply voltage,
VLED, is greater than 3 to 5 V, and PD(act) > PD(max), an external
voltage reducer (VDROP) must be used (figure at left). Reducing
DC will also reduce power dissipation. The ES and LP packages
contain an exposed thermal pad on the bottom of the package
for enhanced heat dissipation. Connect this pad to a large power
ground plane using thermal vias. JEDEC documents JESD51-3
and JESD51-5 give suggestions for PCB and thermal via designs.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
A6282
16-Channel Constant-Current LED Driver
Package ES, 4 mm x 4 mm, 24-pin QFN with Exposed Thermal Pad
0.30
4.00 ±0.15
1
2
0.50
24
24
0.90
1
2
A
2.10
4.00 ±0.15
4.10
2.10
4.10
25X
D
SEATING
PLANE
0.08 C
+0.05
0.25 –0.07
0.75 ±0.05
0.50
C
C
PCB Layout Reference View
For Reference Only
(reference JEDEC MO-220WGGD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
+0.15
0.40 –0.10
B
2.10
2
1
C Reference land pattern layout (reference IPC7351
QFN50P400X400X80-25W6M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances; when
mounting on a multilayer PCB, thermal vias at the exposed thermal pad land
can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)
D Coplanarity includes exposed thermal pad and terminals
24
2.10
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
11
A6282
16-Channel Constant-Current LED Driver
Package LP, 24-pin TSSOP with Exposed Thermal Pad
7.80 ±0.10
4° ±4
24
0.65
0.45
+0.05
0.15 –0.06
B
3.00
4.40 ±0.10
6.40 ±0.20
A
1
6.10
(1.00)
2
4.32
0.25
24X
SEATING
PLANE
0.10 C
+0.05
0.25 –0.06
3.00
0.60 ±0.15
0.65
1.20 MAX
0.15 MAX
C
SEATING PLANE
GAUGE PLANE
1.65
4.32
C
PCB Layout Reference View
For reference only
(reference JEDEC MO-153 ADT)
Dimensions in millimeters
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
A Terminal #1 mark area
B Exposed thermal pad (bottom surface)
C Reference land pattern layout (reference IPC7351
TSOP65P640X120-25M); all pads a minimum of 0.20 mm from all
adjacent pads; adjust as necessary to meet application process
requirements and PCB layout tolerances; when mounting on a multilayer
PCB, thermal vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
A6282
16-Channel Constant-Current LED Driver
Copyright ©2008-2013, Allegro MicroSystems, LLC
Allegro MicroSystems, LLC reserves the right to make, from time to time, such departures from the detail specifications as may be required to
permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that
the information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, LLC assumes no responsibility for its
use; nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
13
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