ENA1869 D

Ordering
Orderingnumber
number: :ENA1869A
ENA1951
LC87F2W48A
CMOS IC
50K-byte FROM and 1536-byte RAM integrated
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F2W48A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 50K-byte flash ROM (On-boardprogrammable), 1536-byte RAM, an On-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with a
prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface, an
asynchronous/synchronous SIO interface, a UART interface (full duplex), two 12-bit PWM channels, a 14-channel
AD converter with 12-/8-bit resolution selector, a system clock frequency divider, an infrared remote controller
receiver circuit, and a 24-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programming with wide range, 2.7 to 5.5V, of voltage source.
• Block-erasable in 128 byte units
• Writable in 2-byte units
• 51200 × 8 bits
RAM
• 1536 × 9 bits
Minimum Bus Cycle
• 83.3ns (12MHz) VDD=2.7V to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00
83111HKIM 20101027-S00001 No.A1869-1/26
LC87F2W48A
Minimum instruction cycle time
• 250ns (12MHz) VDD=2.7 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports I/O direction can be designated in 1-bit units
• Dedicated oscillator ports/input ports
• Reset pin
• On-chip Debugger pin
• Power pins
38 (P0n, P1n, P2n, P31 to P36, P70 to P73,
PWM0, PWM1, XT2, CF2)
2 (XT1, CF1)
1 (RES)
1 (OWP0)
6 (VSS1 to 3, VDD1 to 3)
Timers
• Timer 0: 16 bit timer / counter with capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) × 2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs)
+ 8-bit timer/counter with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8 bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs)
(The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Base Timer
(1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock,
and timer 0 prescaler output.
(2) Interrupts are programmable in 5 different time schemes
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2) Can generate output real-time.
Serial Interface
• SIO 0: 8-bit synchronous serial interface
(1) LSB first/MSB first mode selectable
(2) Built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tCYC)
(3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of
data transmission possible in 1-byte units)
• SIO 1: 8-bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8-data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8-data bits, stop detect)
No.A1869-2/26
LC87F2W48A
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2-bit in continuous data transmission)
• Built-in baudrate generator
AD Converter: 12 bits/8 bits × 14 channels
• 12 bits/8 bits AD converter resolution selectable
PWM: Multifrequency 12-bit PWM × 2 channels
 Infrared Remote Controller Receiver Circuit
1) Noise rejection function (noise filter time constant: Approx. 120μs when the 32.768kHz crystal oscillator is
selected as the reference clock source)
2) Supports data encording systems such as PPM (Pulse Position Modulation) and Manchester encording
3) X’tal HOLD mode release function
Clock Output Function
• Can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the
system clock.
• Can generate the source clock for the subclock.
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Interrupts
• 24 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests of
the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level
takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest vector
address takes precedence.
No.
Vector Address
Level
Interrupt Source
1
00003H
X or L
INT0
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4/REMOREC2
4
0001BH
H or L
INT3/INT5/BT0/BT1
5
00023H
H or L
T0H
6
0002BH
H or L
T1L/T1H
7
00033H
H or L
SIO0/UART1 receive
8
0003BH
H or L
SIO1/UART transmit
9
00043H
H or L
ADC/T6/T7
H or L
Port 0/T4/T5/PWM0,1
10
0004BH
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (List of interrupt source flag function)
(1) Shows a list of interrupt source flags that caused a branching to a particular vector address
(shown in the table above.)
Subroutine Stack Levels: 768 levels (the stack is allocated in RAM.)
High-speed Multiplication/Division Instructions
• 16 bits × 8 bits
(5 tCYC execution time)
• 24 bits × 16 bits
(12 tCYC execution time)
• 16 bits ÷ 8 bits
(8 tCYC execution time)
• 24 bits ÷ 16 bits
(12 tCYC execution time)
No.A1869-3/26
LC87F2W48A
Oscillation Circuits
• Internal oscillation circuits
1) Low-speed RC oscillation circuit:
For system clock (100kHz)
2) Medium-speed RC oscillation circuit:
For system clock (1MHz)
3) Frequency variable RC oscillation circuit: For system clock (6 to 10MHz)
(1) Adjustable in ±0.5% (typ) step from a selected center frequency.
(2) Measures oscillation clock using a input signal from XT1 as a reference.
• External oscillation circuits
1) Low speed crystal oscillation circuit:
For low-speed system clock, with internal Rf
2) Hi-speed CF oscillation circuit:
For system clock, with internal Rf
(1) Both the CF and crystal oscillator circuits stop operation on a system reset.
System Clock Divider function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) There are three ways of resetting the HALT mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are four ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except base timer
and infrared remote controller receiver circuit.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are six ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) System resetting by watchdog timer
(3) Having an interrupt source established at either INT0, INT1, INT2, INT4, or INT5
* INT0 and INT1 X'tal HOLD mode reset is available only when level detection is set.
(4) Having an interrupt source established at port 0
(5) Having an interrupt source established in the base timer circuit
(6) Having an interrupt source established in the infrared remote controller receiver circuit
Onchip Debugger
• Supports software debugging with the IC mounted on the target board.
Data Security Function (Flash versions only)
• Protects the program data stored in flash memory from unauthorized read or copy.
Note: This data security function does not necessarily provide absolute data security.
No.A1869-4/26
LC87F2W48A
Package Form
• SQFP48 (7×7) (Lead-/Halogen-free type)
Development Tools
• On-chip-debugger: TCB87-TypeC (1 wire version) + LC87F2W48A
Flash ROM Programming Boards
Package
Programming boards
SQFP48 (7×7)
W87F55256SQ
Package Dimensions
unit : mm (typ)
3163B
36
0.5
9.0
7.0
25
24
48
13
7.0
9.0
37
1
12
0.5
0.18
0.15
(1.5)
0.1
1.7max
(0.75)
SANYO : SQFP48(7X7)
No.A1869-5/26
LC87F2W48A
P27/INT5/T1IN
P26/INT5/T1IN
P25/INT5/T1IN
P24/INT5/T1IN
P23/INT4/T1IN
P22/INT4/T1IN
P21/URX/INT4/T1IN
P20/UTX/INT4/T1IN
P07/T7O/AN7
P06/T6O/AN6
P05/CKO/AN5
P04/AN4
36
35
34
33
32
31
30
29
28
27
26
25
Pin Assignment
P36
37
24
P03/AN3
P35
38
23
P02/AN2
VDD3
39
22
P01/AN1
VSS3
40
21
P00/AN0
P34
41
20
VSS2
P33
42
19
VDD2
P32
43
18
PWM0
P31
44
17
PWM1
OWP0
45
16
P17/T1PWMH/BUZ
P70/INT0/T0LCP/AN8
46
15
P16/T1PWML
P71/INT1/T0HCP/AN9
47
14
P15/SCK1
P72/INT2/T0IN
48
13
P14/SI1/SB1
7
8
9
CF2/AN13
VDD1
P10/SO0
12
6
CF1/AN12
P13/SO1
5
VSS1
11
4
XT2/AN11
P12/SCK0
3
XT1/AN10
10
2
RES
P11/SI0/SB0
1
P73/INT3/T0IN/RMIN
LC87F2W48A
Top view
SQIP48 (7×7) “Lead-/Halogen-free type”
SQFP
NAME
SQFP
NAME
SQFP
NAME
1
P73/INT3/T0IN/RMIN
17
PWM1
33
P24/INT5/T1IN
2
RES
18
PWM0
34
P25/INT5/T1IN
3
XT1/AN10
19
VDD2
35
P26/INT5/T1IN
4
XT2/AN11
20
VSS2
36
P27/INT5/T1IN
5
VSS1
21
P00/AN0
37
P36
6
CF1/AN12
22
P01/AN1
38
P35
7
CF2/AN13
23
P02/AN2
39
VDD3
8
VDD1
24
P03/AN3
40
VSS3
9
P10/SO0
25
P04/AN4
41
P34
10
P11/SI0/SB0
26
P05/CKO/AN5
42
P33
11
P12/SCK0
27
P06/T6O/AN6
43
P32
12
P13/SO1
28
P07/T7O/AN7
44
P31
13
P14/SI1/SB1
29
P20/UTX/INT4/T1IN
45
OWP0
14
P15/SCK1
30
P21/URX/INT4/T1IN
46
P70/INT0/T0LCP/AN8
15
P16/T1PWML
31
P22/INT4/T1IN
47
P71/INT1/T0HCP/AN9
16
P17/T1PWMH/BUZ
32
P23/INT4/T1IN
48
P72/INT2/T0IN
No.A1869-6/26
LC87F2W48A
System Block Diagram
Interrupt control
IR
PLA
Flash ROM
Standby control
X’tal
MediumSpeed RC
LowSpeed RC
Clock
generator
CF
PC
RES
WDT
Reset control
VMRC
ACC
B register
SIO0
Bus interface
SIO1
Port 0
C register
ALU
Timer 0
Port 1
Timer 1
Port 2
PSW
Timer 4
Port 3
RAR
Timer 5
Port 7
RAM
Timer 6
ADC
Stack pointer
Timer 7
UART1
Watchdog timer
Base timer
PWM0/1
Infrared remote controller
receiver circuit
On-chip debugger
INT0-2, INT4, 5
INT3 (Noise filter)
No.A1869-7/26
LC87F2W48A
Pin Description
Pin Name
I/O
Description
Option
VSS1 to VSS3
-
- power supply pins
VDD1 to VDD3
-
+ power supply pin
No
• 8-bit I/O port
Yes
Port 0
I/O
No
• I/O specifiable in 1-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 1-bit units.
• HOLD reset input
• Port 0 interrupt input
• Pin functions
P05: System clock output
P06: Timer 6 toggle output
P07: Timer 7 toggle output
P00(AN0) to P07(AN7): AD converter input
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1PWML output
P17: Timer 1PWMH output/beeper output
Port 2
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P20 to P27
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20: UART transmit
P21: UART receive
P20 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Port 3
P31 to P36
I/O
Rising
Falling
INT4
enable
enable
INT5
enable
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
Falling
• 6-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
Continued on next page.
No.A1869-8/26
LC87F2W48A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input HOLD reset input/timer 0 event input/timer 0L capture input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input/
Infrared remote controller receiver input
P70(AN8), P71(AN9): AD converter input
• Interrupt acknowledge type
PWM0
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising &
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
• PWM0 output port
Falling
No
• General-purpose I/O available
PWM1
I/O
• PWM1 output port
No
• General-purpose I/O available
RES
I/O
XT1
Input
External reset Input/internal reset output
No
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
AD converter input port: AN10
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port: AN11
CF1
Input
• Ceramic resonator input pin
No
• Shared pins
General-purpose input port
AD converter input port: AN12
CF2
I/O
• Ceramic resonator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port: AN13
OWP0
I/O
On-chip Debugger pin
No
No.A1869-9/26
LC87F2W48A
On-chip Debugger Pin Connection Requirements
For the treatment of the on-chip debugger pins, refer to the separately available documents entitled “RD87 On-chip
Debugger Installation Manual”
Recommended Unused Pin Connections
Recommended Unused Pin Connections
Port Name
Board
Software
P00 to P07
Open
Output low
P10 to P17
Open
Output low
P20 to P27
Open
Output low
P31 to P36
Open
Output low
P70 to P73
Open
Output low
PWM0, PWM1
Open
Output low
XT1
Pulled low with a 100kΩ resistor or less
General-purpose input port
XT2
Open
Output low
CF1
Pulled low with a 100kΩ resistor or less
General-purpose input port
CF2
Open
Output low
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
P00 to P07
P10 to P17
P20 to P27
P31 to P36
Option Selected
in Units of
Option Type
Output Type
Pull-up Resistor
1
CMOS
Programmable (Note 1)
2
Nch-open drain
Programmable (Note 1)
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
Programmable
1 bit
1 bit
1 bit
P70
-
No
Nch-open drain
P71 to P73
-
No
CMOS
Programmable
PWM0, PWM1
-
No
CMOS
No
XT1
-
No
XT2
-
No
Input for 32.768kHz crystal oscillator
(Input only)
No
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose
No
output mode)
CF1
-
No
CF2
-
No
Input for ceramic resonator oscillator
(Input only)
No
Output for ceramic resonator oscillator
(Nch-open drain when in general-purpose
No
output mode)
Note 1: The control of the presence or absence of the programmable pull-up resistors for port 0 and the switching
between low- and high-impedance pull-up connection is exercised in 1-bit units.
No.A1869-10/26
LC87F2W48A
User Option Table
Option name
Port output type
Option to be Applied on
P00 to P07
Option Selected in Units of
1 bit
P31 to P36
Program start
1 bit
Nch-open drain
CMOS

1 bit

1 bit
Nch-open drain
CMOS
Nch-open drain
00000h

-
Nch-open drain
CMOS

P20 to P27
Option selection
CMOS

P10 to P17
address
Flash-ROM Version
-
0FE00h
Note: To reduce VDD1 signal noise and to increase the duration of the backup battery supply, VSS1, VSS2, and VSS3
should connect to each other and they should also be grounded.
Example 1: During backup in hold mode, port output ‘H’ level is supplied from the back-up capacitor.
Back-up
capacitor
Power
Supply
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
Example 2: During backup in hold mode, output is not held high and its value in unsettled.
Back-up
capacitor
Power
Supply
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.A1869-11/26
LC87F2W48A
Absolute Maximum Ratings at Ta=25°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Maximum Supply voltage
Symbol
Pins
VDD1, VDD2, VDD3
Input voltage
VDD max
VI
Input/Output
VIO
Ports 0, 1, 2, 3
voltage
Conditions
VDD1=VDD2=VDD3
XT1, CF1, RES
Specification
VDD[V]
min
typ
max
unit
-0.3
+6.5
-0.3
VDD+0.3
-0.3
VDD+0.3
V
Port 7
PWM0, PWM1
XT2, CF2
Peak output
IOPH(1)
Ports 0, 1, 2, 3
current
High level output current
Mean output
Per 1 applicable pin
-10
IOPH(2)
PWM0, PWM1
Per 1 applicable pin
-20
IOPH(3)
P71 to P73
Per 1 applicable pin
-5
IOMH(1)
Ports 0, 1, 2, 3
CMOS output select
Per 1 applicable pin
current
(Note 1-1)
CMOS output selected
-7.5
IOMH(2)
PWM0, PWM1
Per 1 applicable pin
IOMH(3)
P71 to P73
Per 1 applicable pin
Total output
IOAH(1)
P71 to P73
Total of all applicable pins
-10
current
IOAH(2)
Port 0
Total of all applicable pins
-25
IOAH(3)
Port 1
Total of all applicable pins
PWM0, PWM1
IOAH(4)
Ports 0, 1
Total of all applicable pins
PWM0, PWM1
IOAH(5)
Port 2
Total of all applicable pins
P35, P36
Peak output
-15
-3
-25
-45
-25
IOAH(6)
P31 to P34
Total of all applicable pins
-25
IOAH(7)
Ports 2, 3
Total of all applicable pins
-45
IOPL(1)
P02 to P07
Per 1 applicable pin
current
Ports 1, 2, 3
20
mA
PWM0, PWM1
IOPL(2)
P00, P01
Per 1 applicable pin
IOPL(3)
Port 7
Per 1 applicable pin
30
10
XT2, CF2
Low level output current
Mean output
IOML(1)
P02 to P07
current
Ports 1, 2, 3
(Note 1-1)
PWM0, PWM1
Per 1 applicable pin
15
IOML(2)
P00, P01
Per 1 applicable pin
IOML(3)
Port 7
Per 1 applicable pin
20
7.5
XT2, CF2
Total output
IOAL(1)
current
Port 7
Total of all applicable pins
15
XT2, CF2
IOAL(2)
Port 0
Total of all applicable pins
IOAL(3)
Port 1
Total of all applicable pins
45
45
PWM0, PWM1
IOAL(4)
Ports 0, 1
Total of all applicable pins
80
PWM0, PWM1
IOAL(5)
Port 2
Total of all applicable pins
45
P35, P36
Power dissipation
IOAL(6)
P31 to P34
Total of all applicable pins
45
IOAL(7)
Ports 2, 3
Total of all applicable pins
60
Pdmax(1)
SQFP48(7×7)
Ta=-40 to +85°C
129
Package only
Pdmax(2)
mW
Ta=-40 to +85°C
383
Package with thermal
resistance board (Note 1-2)
Operating
Topr
temperature range
Storage
temperature range
Tstg
-40
85
-55
125
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Note 1-2: SEMI standards thermal resistance board (size: 76.1×114.3×1.6 tmm, glass epoxy) is used.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A1869-12/26
LC87F2W48A
Allowable Operating Conditions at Ta=-40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Operating
VDD
VDD1=VDD2=VDD3
0.245μs≤tCYC≤200μs
VHD
VDD1=VDD2=VDD3
RAM and register contents
supply voltage
Memory
sustaining
sustained in HOLD mode.
min
typ
max
2.7
5.5
2.0
5.5
unit
supply voltage
High level
VIH(1)
input voltage
Ports 1, 2, 3
P71 to P73
2.7 to 5.5
P70 port input/
interrupt side
0.3VDD
VDD
+0.7
PWM0, PWM1
VIH(2)
VIH(3)
Port 0
2.7 to 5.5
Port 70 watchdog
timer side
VIH(4)
Low level
VIL(1)
input voltage
0.3VDD
VDD
+0.7
2.7 to 5.5
0.9VDD
VDD
2.7 to 5.5
0.75VDD
VDD
4.0 to 5.5
VSS
2.7 to 4.0
VSS
4.0 to 5.5
VSS
2.7 to 4.0
VSS
2.7 to 5.5
VSS
2.7 to 5.5
VSS
0.25VDD
2.7 to 5.5
0.245
200
2.7 to 5.5
0.1
12
3.0 to 5.5
0.2
24.4
V
XT1, XT2, CF1, CF2
RES
Ports 1, 2, 3
P71 to P73
0.1VDD
+0.4
P70 port input/
interrupt side
0.2VDD
PWM0, PWM1
VIL(2)
VIL(3)
Port 0
Port 70 watchdog
timer side
VIL(4)
Instruction
tCYC
cycle time
(Note 2-1)
External
FEXCF
XT1, XT2, CF1, CF2
RES
CF1
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
μs
CF2 pin open
system clock
System clock frequency division
frequency
ratio=1/1
External system clock duty=50±5%
CF2 pin open
System clock frequency division
ratio=1/2
External system clock duty=50±5%
Oscillation
FmCF(1)
CF1, CF2
frequency
range
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
FmCF(3)
CF1, CF2
(Note 2-2)
10MHz ceramic oscillation
See Fig. 1.
2.7 to 5.5
12
2.7 to 5.5
10
2.7 to 5.5
4
2.7 to 5.5
4
MHz
4MHz ceramic oscillation.
CF oscillation normal amplifier size
selected. (CFLAMP=0)
See Fig. 1.
4MHz ceramic oscillation.
CF oscillation low amplifier size
selected. (CFLAMP=1)
See Fig. 1.
Note 2-1: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-2: See Tables 1 and 2 for the oscillation constants.
Continued on next page.
No.A1869-13/26
LC87F2W48A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Oscillation
FmVMRC
frequency
(VM3FRQ1/0=0/1)
range
(Note 2-3)
(Note 2-2)
FmRC
Internal Medium-speed RC
oscillation
FmSRC
FsX’tal
Internal Low-speed RC oscillation
XT1, XT2
32.768kHz crystal oscillation
See Fig. 3.
Frequency
OpVMRC
variable RC
min
typ
max
unit
Frequency variable RC oscillation.
2.7 to 5.5
8.0
MHz
2.7 to 5.5
0.5
1.0
2.0
2.7 to 5.5
50
100
200
kHz
2.7 to 5.5
32.768
Frequency variable RC oscillation.
(VM3FRQ1/0=0/1)
oscillation
2.7 to 5.5
6
8
10
2.7 to 5.5
3.6
7.0
11
2.7 to 5.5
0.7
1.5
2.3
2.7 to 5.5
0.2
0.5
1.1
MHz
usable range
Frequency
VmADJ(1)
Each step of V3RCHBn
VmADJ(2)
Each step of V3FCHBn
VmADJ(3)
Each step of V3DCHn
variable RC
oscillation
adjustment
range
%
Note 2-2: See Tables 1 and 2 for the oscillation constants.
Note 2-3: When switching the system clock, allow an oscillation stabilization time of 100μs or longer after the
multifrequency RC oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
No.A1869-14/26
LC87F2W48A
Electrical Characteristics at Ta=-40 to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
Ports 0, 1, 2, 3
Output disabled
Port 7
RES
Pull-up resistor off
PWM0, PWM1
VIN=VDD
(Including output Tr's off leakage
min
typ
max
unit
2.7 to 5.5
1
2.7 to 5.5
1
2.7 to 5.5
15
current)
IIH(2)
Low level input
XT1, XT2, CF2
Input port selected
IIH(3)
CF1
VIN=VDD
VIN=VDD
IIL(1)
Ports 0, 1, 2, 3
Output disabled
Port 7
RES
Pull-up resistor off
current
PWM0, PWM1
VIN=VSS
(Including output Tr's off leakage
2.7 to 5.5
-1
2.7 to 5.5
-1
μA
current)
IIL(2)
High level
XT1, XT2, CF2
Input port selected
IIL(3)
CF1
VIN=VSS
VIN=VSS
2.7 to 5.5
-15
VOH(1)
Ports 0, 1, 2, 3
IOH=-1mA
4.5 to 5.5
VDD-1
IOH=-0.35mA
2.7 to 5.5
VDD
-0.4
IOH=-6mA
4.5 to 5.5
VDD-1
IOH=-1.4mA
2.7 to 5.5
VDD
-0.4
output voltage
P71 to P73
VOH(2)
VOH(3)
PWM0, PWM1
P05(System clock
VOH(4)
output function
used)
Low level
output voltage
V
VOL(1)
Ports 0, 1, 2, 3
IOL=10mA
4.5 to 5.5
1.5
VOL(2)
PWM0, PWM1
IOL=1.4mA
2.7 to 5.5
0.4
VOL(3)
P00, P01
IOL=25mA
4.5 to 5.5
1.5
IOL=4mA
2.7 to 5.5
0.4
VOL(4)
VOL(5)
Port 7, XT2, CF2
IOL=1.4mA
2.7 to 5.5
Pull-up
Rpu(1)
Ports 0, 1, 2, 3
4.5 to 5.5
15
35
80
resistance
Rpu(2)
Port 7
VOH=0.9VDD
When Port 0 selected
2.7 to 5.5
18
50
230
low-impedance pull-up.
Rpu(3)
Port 0
VOH=0.9VDD
When Port 0 selected
0.4
kΩ
2.7 to 5.5
100
210
400
high-impedance pull-up.
Hysteresis
VHYS
Ports 1, 2, 3, 7
RES, XT2
CP
All pins
voltage
Pin capacitance
For pins other than that under test:
VIN=VSS, f=1MHz, Ta=25°C
2.7 to 5.5
0.1VDD
V
2.7 to 5.5
10
pF
No.A1869-15/26
LC87F2W48A
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
min
See Fig. 6.
tSCKH(1)
2.7 to 5.5
pulse width
tSCKHA(1)
1
tCYC
Continuous data transmission/
4
Serial clock
See Fig. 6.
(Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
CMOS output selected
4/3
See Fig. 6
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.7 to 5.5
pulse width
tSCKHA(2)
1/2
Continuous data transmission/
reception mode
tSCKH(2)
CMOS output selected.
+2tCYC
See Fig. 6.
Data setup time
Serial input
unit
1
reception mode
tsDI(1)
SB0(P11),
Must be specified with
SI0(P11)
respect to rising edge of
SIOCLK.
Data hold time
See Fig. 6.
thDI(1)
tSCKH(2)
+(10/3)
tCYC
tCYC
0.05
2.7 to 5.5
0.05
Input clock
Output delay
tdD0(1)
time
SO0(P10),
Continuous data
SB0(P11)
transmission/reception mode
(1/3)tCYC
+0.08
(Note 4-1-3)
tdD0(2)
Synchronous 8-bit mode
(Note 4-1-3)
tdD0(3)
Output clock
Serial output
max
2
pulse width
High level
typ
(Note 4-1-3)
μs
1tCYC
2.7 to 5.5
+0.08
(1/3)tCYC
+0.08
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: When using the serial clock input in the continuous data transmission/reception mode, make sure, at the
beginning of continuous data transmission/reception, that the interval from the time SI0RUN is set while
the serial clock is high till the first falling edge of the serial clock is longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A1869-16/26
LC87F2W48A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
min
See Fig. 6.
2.7 to 5.5
pulse width
High level
tSCK(4)
Low level
tSCKL(4)
1
SCK1(P15)
CMOS output selected
2
See Fig. 6.
1/2
2.7 to 5.5
tSCK
tSCKH(4)
1/2
Serial input
pulse width
Data setup time
tsDI(2)
Data hold time
SB1(P14),
Must be specified with
SI1(P14)
respect to rising edge of
SIOCLK.
thDI(2)
0.05
2.7 to 5.5
See Fig. 6.
tdD0(4)
SO1(P13),
Must be specified with
SB1(P14)
respect to falling edge of
Serial output
Output delay time
unit
1
pulse width
High level
max
tCYC
tSCKH(3)
Frequency
typ
2
pulse width
Output clock
Serial clock
VDD[V]
0.05
μs
SIOCLK.
Must be specified as the
time to the beginning of
(1/3)tCYC
2.7 to 5.5
+0.08
output state change in
open drain output mode.
See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
Event inputs for timer 0 or 1 are
INT2(P72),
enabled.
min
typ
2.7 to 5.5
1
2.7 to 5.5
2
2.7 to 5.5
64
2.7 to 5.5
256
2.7 to 5.5
4
2.7 to 5.5
200
max
unit
INT4(P20 to P23),
INT5(P24 to P27)
tPIH(2)
INT3(P73) when
Interrupt source flag can be set.
tPIL(2)
noise filter time
Event inputs for timer 0 are enabled.
constant is 1/1
tPIH(3)
INT3(P73) when
Interrupt source flag can be set.
tPIL(3)
noise filter time
Event inputs for timer 0 are enabled.
tCYC
constant is 1/32
tPIH(4)
INT3(P73) when
Interrupt source flag can be set.
tPIL(4)
noise filter time
Event inputs for timer 0 are enabled.
constant is 1/128
tPIH(5)
RMIN(P73)
tPIL(5)
tPIL(6)
Recognized by the infrared remote
controller receiver circuit as a signal.
RES
Resetting is enabled.
RMCK
(Note 5-1)
μs
Note 5-1: Represents the period of the reference clock (1 to 128 tCYC or the source frequency of the subclock) for the
infrared remote controller receiver circuit.
No.A1869-17/26
LC87F2W48A
AD Converter Characteristics at VSS1 = VSS2 = VSS3 = 0V
<12bits AD Converter Mode at Ta = -40 to +85°C>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07),
AN8(P70),
accuracy
AN9(P71),
Conversion
TCAD
AN10(XT1),
time
AN11(XT2),
Analog input
input current
max
unit
12
bit
3.0 to 5.5
±16
(Note 6-1)
2.7 to 3.6
±20
See Conversion time calculation
4.5 to 5.5
32
115
formulas. (Note 6-2)
3.0 to 5.5
64
115
2.7 to 3.6
410
425
2.7 to 5.5
VSS
VDD
AN12(CF1),
See Conversion time calculation
AN13(CF2)
formulas. (Note 6-2)
VAIN
IAINH(1)
analog channel
VAIN=VDD
2.7 to 5.5
IAINL(1)
except AN12
VAIN=VSS
2.7 to 5.5
IAINH(2)
AN12
VAIN=VDD
2.7 to 5.5
VAIN=VSS
2.7 to 5.5
IAINL(2)
typ
(Note 6-1)
voltage range
Analog port
min
2.7 to 5.5
LSB
μs
V
1
-1
μA
15
-15
<8bits AD Converter Mode at Ta = -40 to +85°C>
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P00) to
Absolute
ET
AN7(P07),
Conversion
TCAD
time
bit
±1.5
See Conversion time calculation
4.5 to 5.5
20
70
AN10(XT1),
formulas. (Note 6-2)
3.0 to 5.5
40
70
2.7 to 3.6
250
265
2.7 to 5.5
VSS
VDD
AN13(CF2)
See Conversion time calculation
formulas. (Note 6-2)
VAIN
voltage range
input current
unit
AN9(P71),
AN12(CF1),
Analog port
max
8
2.7 to 5.5
AN11(XT2),
Analog input
typ
2.7 to 5.5
(Note 6-1)
AN8(P70),
accuracy
min
IAINH(1)
analog channel
VAIN=VDD
2.7 to 5.5
IAINL(1)
except AN12
VAIN=VSS
2.7 to 5.5
IAINH(2)
AN12
VAIN=VDD
2.7 to 5.5
VAIN=VSS
2.7 to 5.5
IAINL(2)
LSB
μs
V
1
-1
15
μA
-15
Conversion time calculation formulas:
12bits AD Converter Mode: TCAD(Conversion time)= ((52/(AD division ratio))+2)×(1/3)×tCYC
8bits AD Converter Mode: TCAD(Conversion time)=((32/(AD division ratio))+2)×(1/3)×tCYC
<Recommended Operating Conditions>
AD conversion time (TCAD)
External
Operating supply
System division ratio
Cycle time
AD division
oscillation (FmCF)
voltage range (VDD)
(SYSDIV)
(tCYC)
ratio (ADDIV)
12bit AD
4.5V to 5.5V
1/1
250ns
1/8
34.8μs
21.5μs
3.0V to 5.5V
1/1
250ns
1/16
69.5μs
42.8μs
8bit AD
CF-12MHz
4.5V to 5.5V
1/1
300ns
1/8
41.8μs
25.8μs
3.0V to 5.5V
1/1
300ns
1/16
83.4μs
51.4μs
CF-10MHz
3.0V to 5.5V
1/1
750ns
1/8
104.5μs
64.5μs
2.7V to 3.6V
1/1
750ns
1/32
416.5μs
256.5μs
CF-4MHz
Note 6-1: The quantization error (±1/2LSB) must be excluded from the absolute accuracy. The absolute accuracy must
be measured in the microcontroller's state in which no I/O operations occur at the pins adjacent to the analog
input channel.
Note 6-2: The conversion time refers to the period from the time an instruction for starting a conversion process till the
time the conversion results register(s) are loaded with a complete digital conversion value corresponding to
the analog input value.
The conversion time is 2 times the normal-time conversion time when:
• The first AD conversion is performed in the 12-bit AD conversion mode after a system reset.
• The first AD conversion is performed after the AD conversion mode is switched from 8-bit to 12-bit
conversion mode.
No.A1869-18/26
LC87F2W48A
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
Specification
Pin/
Conditions
Remarks
VDD[V]
• FmCF=12MHz ceramic oscillation mode
consumption
VDD1
=VDD2
current
=VDD3
• System clock set to 12MHz side
(Note 7-1)
• FsX’tal=32.768kHz crystal oscillation mode
min
typ
max
2.7 to 5.5
4.5
9.5
2.7 to 3.6
2.7
6.5
3.0 to 5.5
5
10.5
3.0 to 3.6
3
7.2
2.7 to 5.5
4
8.2
2.7 to 3.6
2.4
5.8
2.7 to 5.5
2
4.3
2.7 to 3.6
1.3
3
2.7 to 5.5
0.8
2.1
2.7 to 3.6
0.5
1.2
2.7 to 5.5
0.5
1.8
2.7 to 3.6
0.3
0.95
2.7 to 5.5
3.5
6.8
2.7 to 3.6
2.3
5.2
2.7 to 5.5
58
200
unit
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(2)
• CF1=24MHz external clock
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to CF1 side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(3)
• FmCF=10MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 10MHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDOP(4)
• FmCF=4MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
mA
• 1/1 frequency division ratio
IDDOP(5)
• CF oscillation low amplifier size selected.
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDOP(6)
• External FmCF oscillation stopped.
• FsX’tal=32.768kHz Crystal oscillation mode
• System clock set to internal Medium speed RC
oscillation.
• Internal Low speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDOP(7)
• External FmCF oscillation stopped.
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz with Frequency
variable RC oscillation
• Internal Low speed and Medium speed RC
oscillation stopped.
• 1/1 frequency division ratio
IDDOP(8)
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal Low speed RC
oscillation.
μA
• Internal Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
2.7 to 3.6
37
135
• 1/1 frequency division ratio
Note 7-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Continued on next page.
No.A1869-19/26
LC87F2W48A
Continued from preceding page.
Parameter
Normal mode
Symbol
IDDOP(9)
Specification
Pin/
Conditions
Remarks
VDD[V]
• External FmCF oscillation stopped.
consumption
VDD1
= VDD2
current
= VDD3
• System clock set to 32.768kHz side
(Note 7-1)
• FsX’tal=32.768kHz crystal oscillation mode
2.7 to 5.5
min
typ
max
38
unit
130
μA
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
2.7 to 3.6
12
65
2.7 to 5.5
2
3.1
2.7 to 3.6
0.9
1.7
3.0 to 5.5
2.2
3.5
3.0 to 3.6
1
2
2.7 to 5.5
1.8
2.8
2.7 to 3.6
0.8
1.5
2.7 to 5.5
1
1.6
2.7 to 3.6
0.4
0.8
2.7 to 5.5
0.5
1
2.7 to 3.6
0.2
0.5
2.7 to 5.5
0.35
0.8
2.7 to 3.6
0.15
0.4
• 1/2 frequency division ratio
HALT mode
VDD1
= VDD2
HALT mode
consumption
IDDHALT(1)
current
= VDD3
• FsX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
• FmCF=12MHz ceramic oscillation mode
• System clock set to 12MHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(2)
HALT mode
• CF1=24MHz external clock
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to CF1 side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
IDDHALT(3)
HALT mode
• FmCF=10MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 10MHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(4)
HALT mode
• FmCF=4MHz ceramic oscillation mode
mA
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(5)
HALT mode
• CF oscillation low amplifier size selected.
(CFLAMP=1)
• FmCF=4MHz ceramic oscillation mode
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/4 frequency division ratio
IDDHALT(6)
HALT mode
• External FmCF oscillation stopped.
• FsX’tal=32.768kHz crystal oscillation mode
• System clock set to internal Medium speed RC
oscillation
• Internal Low speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
Note 7-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
Continued on next page.
No.A1869-20/26
LC87F2W48A
Continued from preceding page
Parameter
HALT mode
Symbol
IDDHALT(7)
Specification
Pin/
Conditions
remarks
VDD[V]
HALT mode
consumption
VDD1
= VDD2
current
= VDD3
• FsX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
• External FmCF oscillation stopped.
min.
typ.
2.7 to 5.5
max.
1.5
2.4
• System clock set to 8MHz with Frequency
mA
variable RC oscillation
• Internal Low speed and Medium speed RC
unit
2.7 to 3.6
1
1.6
2.7 to 5.5
18
74
2.7 to 3.6
9
40
oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(8)
HALT mode
• External FsX’tal and FmCF oscillation stopped.
• System clock set to internal Low speed RC
oscillation.
• Internal Medium speed RC oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/1 frequency division ratio
IDDHALT(9)
μA
HALT mode
• External FmCF oscillation stopped.
• FsX’tal=32.768kHz crystal oscillation mode
2.7 to 5.5
27
95
2.7 to 3.6
5.5
42
2.7 to 5.5
0.04
20
2.7 to 3.6
0.03
10
2.7 to 5.5
25
88
2.7 to 3.6
4.5
38
• System clock set to 32.768 kHz side
• Internal Low speed and Medium speed RC
oscillation stopped.
• Frequency variable RC oscillation stopped.
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
VDD1
= VDD2
current
= VDD3
HOLD mode
• CF1=VDD or open
(External clock mode)
(Note 7-1)
Timer HOLD
IDDHOLD(2)
μA
Timer HOLD mode
mode
• CF1=VDD or open (External clock mode)
consumption
• FsX’tal=32.768kHz crystal oscillation mode
current
(Note 7-1)
Note 7-1: Values of the consumption current do not include current that flows into the output transistors and internal
pull-up resistors.
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
programming
VDD1
= VDD2
current
= VDD3
Onboard
IDDFW
min
typ
max
unit
Only current of the Flash block.
2.7 to 5.5
Programming
tFW(1)
Erasing time
time
tFW(2)
Programming time
5
10
mA
20
30
ms
40
60
μs
2.7 to 5.5
No.A1869-21/26
LC87F2W48A
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD[V]
Transfer rate
UBR
UTX(P20),
2.7 to 5.5
URX(P21)
Data length:
Stop bits:
Parity bits:
min
typ
16/3
max
unit
8192/3
tCYC
7, 8, and 9 bits (LSB first)
1 bit (2-bit in continuous data transmission)
None
Example of Continuous 8-bit Data Transmission Mode Processing (first transmit data=55H)
Start bit
Stop bit
Start of
transmission
End of
transmission
Transmit data (LSB first)
UBR
Example of Continuous 8-bit Data Reception Mode Processing (first receive data=55H)
Stop bit
Start bit
End of
reception
Receive data (LSB first)
Start of
reception
UBR
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
• CF oscillation normal amplifier size selected (CFLAMP=0)
Oscillation
Nominal
Vendor
Frequency
Name
12MHz
Circuit Constant
Oscillator Name
C1
C2
Rf1
Rd1
Operating
Stabilization Time
Voltage Range
(Symbol: tmsCF)
[V]
typ
max
[ms]
[ms]
[pF]
[pF]
[Ω]
[Ω]
CSTCE12M0G52-R0
(10)
(10)
Open
680
2.7 to 5.5
0.03
CSTCE10M0G52-R0
(10)
(10)
Open
680
2.7 to 5.5
0.03
0.03
Remarks
10MHz
CSTLS10M0G53-B0
(15)
(15)
Open
680
2.7 to 5.5
CSTCE8M00G52-R0
(10)
(10)
Open
1.0k
2.7 to 5.5
0.03
CSTLS8M00G53-B0
(15)
(15)
Open
1.0k
2.7 to 5.5
0.03
CSTCR6M00G53-R0
(15)
(15)
Open
1.5k
2.7 to 5.5
0.05
0.03
8MHz
MURATA
Internal
C1,C2
6MHz
CSTLS6M00G53-B0
(15)
(15)
Open
1.5k
2.7 to 5.5
CSTCR4M00G53-R0
(15)
(15)
Open
1.5k
2.7 to 5.5
0.05
CSTLS4M00G53-B0
(15)
(15)
Open
1.5k
2.7 to 5.5
0.03
4MHz
No.A1869-22/26
LC87F2W48A
• CF oscillation low amplifier size selected (CFLAMP=1)
Oscillation
Nominal
Vendor
Frequency
Name
4MHz
Circuit Constant
Oscillator Name
C1
C2
Rf1
Operating
Stabilization Time
Voltage Range
(Symbol: tmsCF)
Rd1
[V]
typ
max
[ms]
[ms]
Remarks
[pF]
[pF]
[Ω]
[Ω]
CSTCR4M00G53-R0
(15)
(15)
Open
1.0k
2.7 to 5.5
0.07
Internal
CSTLS4M00G53-B0
(15)
(15)
Open
1.0k
2.7 to 5.5
0.05
C1,C2
MURATA
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after an
instruction for starting the main clock oscillation circuit or the time interval that is required for the oscillation to get
stabilized (when oscillation is enabled before HOLD or X’tal HOLD mode is entered) after that mode is released (see
Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with
which the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Frequency
Operating
Circuit Constant
Vendor Name
C3
C4
Rf2
Rd2
[pF]
[pF]
[Ω]
[Ω]
18
18
Open
560k
Range
[V]
(Symbol: tmsXtal)
typ
max
[s]
[s]
1.5
3.0
Remarks
Applicable
EPSON
32.768kHz
Voltage
Oscillator Name
Oscillation
Stabilization Time
MC-306
TOYOCOM
2.7 to.5.5
CL value=
12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit or the time interval that is required for the oscillation to get
stabilized (when oscillation is enabled before HOLD mode is entered) after that mode is released (see Figure 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
XT1
CF2
CF1
XT2
Rf2
Rf1
Rd2
Rd1
C1
C2
C3
C4
CF
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A1869-23/26
LC87F2W48A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Medium-speed RC oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Instruction for enabling oscillation executed
Operating mode
Unpredictable
Reset
Instruction execution
Reset Time and Oscillation Stabilizing Time
HOLD reset signal
HOLD reset signal absent
HOLD reset signal valid
Medium-speed RC oscillation
or
Low-speed RC oscillation
tmsCF
CF1, CF2
(Note)
tmsXtal
XT1, XT2
(Note)
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
(Note: When oscillation is enabled before HOLD mode is entered.)
Figure 4 Oscillation Stabilization Times
No.A1869-24/26
LC87F2W48A
VDD
Note:
Determine the value of CRES and RRES so
that the reset signal is present for a period of
200μs after the supply voltage goes beyond
the lower limit of the IC’s operating voltage.
RRES
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
DI8
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial Input/Output Wave Forms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A1869-25/26
LC87F2W48A
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application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental
damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual
performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical
experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use
as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in
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any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
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PS No.A1869-26/26
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