ENA0928 D

Ordering
Ordering number
number :: ENA0928
ENA0928
LC87F5R96B
CMOS IC
FROM 98K byte, RAM 4096 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F5R96B is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 98K-byte flash ROM (onboard
programmable), 4096-byte RAM, On-chip debugging function, sophisticated 16-bit timers/counters (may be divided
into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers
with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous SIO interface
(with automatic block transmission/reception capabilities), an asynchronous/synchronous SIO port, two UART ports
(full duplex), an 8-bit 11-channel AD converter, two 12-bit PWM channels, a system clock frequency divider, and a
27-source 10-vector interrupt feature.
Features
Flash ROM
• Capable of on-board-programing with wide range, 2.7 to 5.5V, of voltage source
• Block-erasable in 128 byte units
• 100352 × 8 bits (Address: 00000H to 17FFFH, 1F800H to 1FFFFH)
RAM
• 4096 × 9 bits
Minimum Bus Cycle Time
• 83.3ns (12MHz)
VDD=2.8 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 5.5V
• 500ns (2MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
Minimum Instruction Cycle Time (tCYC)
• 250ns (12MHz)
VDD=2.8 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 5.5V
• 1.5μs (2MHz)
VDD=2.2 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
• Power pins
46 (P1n, P2n, P3n, P70 to P73, P80 to P86, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.00
91207HKIM 20070810-S00010 No. A0928-1/22
LC87F5R96B
Timers
• Timer 0: 16-bit timer/counter with a capture register
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register) ×2 channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with an 8-bit capture register)
+ 8-bit counter (with an 8-bit capture register)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with a 16-bit capture register)
Mode 3: 16-bit counter (with a 16-bit capture register)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter
with an 8-bit prescaler (with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2 channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8 bits can be used as PWM.)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs)
• Base timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes.
High-speed Clock Counter
1) Can count clocks with a maximum clock rate of 24MHz (at a main clock of 12MHz).
2) Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
UART: 2 channels
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit (2 bit in continuous data transmission)
• Built-in baudrate generator (with baudrates of 16/3 to 8192/3 tCYC)
AD Converter: 8 bits × 11 channels
PWM: Multifrequency 12-bit PWM × 2 channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
1) Noise filtering function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
2) The noise filtering function is available for the INT3, T0IN, or T0HCP signal at P73. When P73 is read with an
instruction, the signal level at that pin is read regardless of the availability of the noise filtering function.
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
No.A0928-2/22
LC87F5R96B
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 27 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt
requests of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer0/base timer1
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
INT0
7
00033H
H or L
SIO0/UART1 receive/UART2 receive
8
0003BH
H or L
SIO/UART1 transmit/UART2 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
Subroutine Stack Levels: 2048 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits (5 tCYC execution time)
• 24-bits × 16-bits (12 tCYC execution time)
• 16-bits ÷ 8-bits (8 tCYC execution time)
• 24-bits ÷ 16-bits (12 tCYC execution time)
Oscillation Circuits
• RC oscillation circuit (internal)
• CF oscillation circuit
• Crystal oscillation circuit
• Multifrequency RC oscillation circuit (internal)
: For system clock
: For system clock, with internal Rf
: For low-speed system clock
: For system clock
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 250ns, 500ns, 1.0μs, 2.0μs, 4.0μs, 8.0μs, 16.0μs, 32.0μs, and
64.0μs (at a main clock rate of 12MHz).
No.A0928-3/22
LC87F5R96B
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt.
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the lower level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
On-chip Debugger Function
• Permits software debugging with the test device installed on the target board.
Package Form
• QIP64E (14 × 14) : “Lead-free type”
Development Tools
• Evaluation (EVA) chip
• Emulator
• On-chip-debugger
: LC87EV690
: EVA62S + ECB876600D + SUB875M00 + POD64QFP
ICE-B877300 + SUB875M00 + POD64QFP
: TCB87-TypeB + LC87F5R96B
Programming Boards
Package
Programming boards
QIP64E(14 × 14)
W87F50256Q
Flash ROM Programmer
Maker
Flash Support
Group,
Inc.(Single)
Model
AF9708/09/09B
(including product of Ando Electric Co.,Ltd)
AF9723(Main body)
Flash Support
(including product of Ando Electric Co.,Ltd)
Group, Inc.(Gang)
AF9833(Unit)
(including product of Ando Electric Co.,Ltd)
Support version(Note)
Device
Revision : After Rev.02.73
LC87F76C8A
Revision : After Rev.02.29
LC87F5NC8A
Revision : After Rev.01.88
Application Version:
Our company
SKK/SKK Type-B/SKK DBG Type-B
After 1.04
(SANYO FWS)
Chip Data Version:
LC87F5R96B
After2.11
No.A0928-4/22
LC87F5R96B
Package Dimensions
unit : mm (typ)
3159A
33
32
64
17
14.0
49
1
17.2
48
0.8
17.2
14.0
16
0.35
0.8
0.15
0.1
3.0max
(2.7)
(1.0)
P31
P30
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC4
PC3
PC2
PC1
PC0
P86/AN6
P85/AN5
P84/AN4
P83/AN3
Pin Assignment
PC5/DBGP0
SANYO : QIP64E(14X14)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
P32/UTX1
P71/INT1/T0HCP/AN9
50
31
P33/URX1
P72/INT2/T0IN/NKIN
51
30
P34/UTX2
P73/INT3/T0IN
52
29
P35/URX2
RES
53
28
P36
XT1/AN10
P70/INT0/T0LCP/AN8
54
27
P37
XT2/AN11
55
26
P27/INT5/T1IN
VSS1
56
25
P26/INT5/T1IN
CF1
57
24
P25/INT5/T1IN
CF2
58
23
P24/INT5/T1IN/INT7
VDD1
LC87F5R96B
59
22
P23/INT4/T1IN
P80/AN0
60
21
P22/INT4/T1IN
P81/AN1
61
20
P21/INT4/T1IN
8
9 10 11 12 13 14 15 16
P05/CKO
7
P04
6
P03
5
P02
4
P01
3
P00
2
VSS2
1
VDD2
P06/T6O
PWM3
17
PWM2
64
P17/T1PWMH/BUZ
P11/SI0/SB0
P15/SCK1
P07/T7O
P16/T1PWML
P20/INT4/T1IN/INT6
18
P14/SI1/SB1
19
63
P13/SO1
62
P12/SCK0
P82/AN2
P10/SO0
Top view
QIP64E(14×14) “Lead-free Type”
No.A0928-5/22
LC87F5R96B
System Block Diagram
Interrupt control
IR
PLA
Standby control
CF
X’tal
Clock
generator
RC
Flash ROM
MRC
PC
SIO0
Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B register
Timer 1
Port 2
C register
Timer 4
Port 7
ALU
Timer 5
Port 8
Timer 6
ADC
PSW
Timer 7
INT0 to INT7
noise filter
RAR
Base timer
Port 3
RAM
PWM2/3
Port C
Stack pointer
UART1
Watchdog timer
UART2
On-chip debugger
No.A0928-6/22
LC87F5R96B
Pin Description
Pin Name
I/O
Description
Option
VSS1, VSS2
VSS3
-
- Power supply pin
No
VDD1, VDD2
VDD3
-
+ Power supply pin
No
• 8-bit I/O port
Yes
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistor can be turned on and off in 4-bit units
• HOLD release input
• Port 0 interrupt input
• Shared Pins
P05: Clock output (system clock/can selected from sub clock)
P06: Timer 6 toggle output
P07: Timer 7 toggle output
Port 1
I/O
Yes
• 8-bit I/O port
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P10: SIO0 data output
P11: SIO0 data input/bus I/O
P12: SIO0 clock I/O
P13: SIO1 data output
P14: SIO1 data input/bus I/O
P15: SIO1 clock I/O
P16: Timer 1 PWML output
P17: Timer 1 PWMH output/beeper output
Port 2
P20 to P27
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistor can be turned on and off in 1-bit units
• Other functions
P20: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT6 input/timer 0L capture 1 input
P21 to P23: INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
P24: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input/INT7 input/timer 0H capture 1 input
P25 to P27: INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/
timer 0H capture input
• Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising/
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.A0928-7/22
LC87F5R96B
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
• 4-bit I/O port
No
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistor can be turned on and off in 1-bit units
• Shared Pins
P70: INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71: INT1 input/HOLD reset input/timer 0H capture input
P72: INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/
high speed clock counter input
P73: INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
AD converter input port: AN8 (P70), AN9 (P71)
• Interrupt acknowledge type
Port 8
I/O
Rising
Falling
INT0
enable
enable
INT1
enable
enable
INT2
enable
INT3
enable
Rising/
H level
L level
disable
enable
enable
disable
enable
enable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
• 7-bit I/O port
No
• I/O specifiable in 1-bit units
P80 to P86
• Shared Pins
AD converter input port : AN0 (P80) to AN6 (P86)
PWM2
I/O
PWM3
Port 3
• PWM2 and PWM3 output ports
No
• General-purpose I/O available
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P30 to P37
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
P32: UART1 transmit
P33: UART1 receive
P34: UART2 transmit
P35: UART2 receive
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistor can be turned on and off in 1-bit units
• Pin functions
DBGP0 to DBGP2(PC5 to PC7): On-chip Debugger
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
AD converter input port : AN10
XT2
I/O
Must be connected to VDD1 if not to be used.
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.A0928-8/22
LC87F5R96B
Port Output Types
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port
Options Selected
in Units of
Option Type
P00 to P07
1 bit
1
P10 to P17
1 bit
Output Type
Pull-up Resistor
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
P70
-
No
Nch-open drain
Programmable
P71 to P73
-
No
CMOS
Programmable
P80 to P86
-
No
Nch-open drain
No
-
No
CMOS
No
1 bit
1
CMOS
Programmable
2
Nch-open drain
Programmable
P20 to P27
P30 to P37
PWM2, PWM3
PC0 to PC7
1 bit
XT1
-
No
Input for 32.768kHz crystal oscillator (Input only)
No
XT2
-
No
Output for 32.768kHz crystal oscillator
No
(Nch-open drain when in general-purpose output mode)
Note 1: Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1: Make the following connection to minimize the noise input to the VDD1 pin and prolong the backup time.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
(Example 1) When backup is active in the HOLD mode, the high level of the port outputs is supplied by the
backup capacitors.
Back-up
capacitor
LSI
VDD1
Power
Supply
VDD2
VDD3
VSS1 VSS2 VSS3
(Example 2) The high-level output at the ports is unstable when the HOLD mode backup is in effect.
Back-up
capacitor
Power
Supply
LSI
VDD1
VDD2
VDD3
VSS1 VSS2 VSS3
No.A0928-9/22
LC87F5R96B
Absolute Maximum Ratings at Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
Input voltage
VI(1)
XT1, CF1
Input/Output voltage
VIO(1)
Ports 0, 1, 2
VDD1=VDD2=VDD3
voltage
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports 7, 8
-0.3
Ports 3, C
VDD+0.3
PWM0, PWM1, XT2
Peak output
IOPH(1)
current
CMOS output select
Per 1 application pin
-10
IOPH(2)
PWM2, PWM3
Per 1 application pin.
-20
IOPH(3)
P71 to P73
Per 1 application pin.
-5
IOMH(1)
Ports 0, 1, 2
CMOS output select
Ports 3, C
Per 1 application pin
IOMH(2)
PWM2, PWM3
Per 1 application pin
IOMH(3)
P71 to P73
Per 1 application pin
Total output
ΣIOAH(1)
P71 to P73
Total of all applicable pins
current
ΣIOAH(2)
Port 1
Total of all applicable pins
Mean output
High level output current
Ports 0, 1, 2
Ports 3, C
current
(Note1-1)
PWM2, PWM3
ΣIOAH(3)
ΣIOAH(4)
Ports 0, 2
Total of all applicable pins
Ports 0, 1, 2
Total of all applicable pins
PWM2, PWM3
Peak output
ΣIOAH(5)
Port 3
ΣIOAH(6)
ΣIOAH(7)
IOPL(1)
current
-7.5
-10
-3
-10
-25
-25
-45
Total of all applicable pins
-25
Port C
Total of all applicable pins
-25
Ports 3, C
Total of all applicable pins
-45
P02 to P07
Per 1 application pin.
Ports 1, 2
20
Ports 3, C
mA
PWM2, PWM3
Low level output current
Mean output
IOPL(2)
P00, P01
Per 1 application pin.
30
IOPL(3)
Ports 7, 8, XT2
Per 1 application pin.
10
IOML(1)
P02 to P07
Per 1 application pin.
current
Ports 1, 2
(Note1-1)
Ports 3, C
15
PWM2, PWM3
IOML(2)
Total output
P00, P01
Per 1 application pin.
20
7.5
IOML(3)
Ports 7, 8, XT2
Per 1 application pin.
ΣIOAL(1)
Port 7
Total of all applicable pins
current
15
P83 to P86, XT2
ΣIOAL(2)
P80 to P82
Total of all applicable pins
15
ΣIOAL(3)
Ports 7, 8, XT2
Total of all applicable pins
20
ΣIOAL(4)
Port 1
Total of all applicable pins
45
PWM2, PWM3
ΣIOAL(5)
Ports 0, 2
Total of all applicable pins
ΣIOAL(6)
Ports 0, 1, 2
Total of all applicable pins
45
80
PWM2, PWM3
ΣIOAL(7)
Port 3
Total of all applicable pins
45
ΣIOAL(8)
Port C
Total of all applicable pins
45
ΣIOAL(9)
Ports 3, C
Total of all applicable pins
Power dissipation
Pd max
QIP64E(14×14)
Ta=-40 to +85°C
Operating ambient
Topr
temperature
Storage ambient
Tstg
temperature
80
300
-40
+85
-55
+125
mW
°C
Note 1-1: The mean output current is a mean value measured over 100ms.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.A0928-10/22
LC87F5R96B
Allowable Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Operating
VDD(1)
VDD1=VDD2=VDD3
supply voltage
(Note2-1)
Memory
VHD
VDD1=VDD2=VDD3
sustaining
0.245μs≤ tCYC≤200μs
min
typ
max
2.8
unit
5.5
0.367μs≤ tCYC≤200μs
2.5
5.5
1.47μs≤ tCYC≤200μs
2.2
5.5
2.0
5.5
RAM and register contents
sustained in HOLD mode
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2
P71 to P73
2.2 to 5.5
P70 port input/
0.3VDD
VDD
+0.7
interrupt side
VIH(2)
Ports 0, 8, 3, C
2.2 to 5.5
PWM2, PWM3
VIH(3)
Port P70 watchdog
VIH(4)
XT1, XT2, CF1,RES
VIL(1)
Ports 1, 2
voltage
0.9VDD
VDD
2.2 to 5.5
0.75VDD
4.0 to 5.5
VSS
VDD
0.1VDD
+0.4
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
0.25VDD
2.8 to 5.5
0.245
200
2.5 to 5.5
0.367
200
2.2 to 5.5
1.47
200
• CF2 pin open
2.8 to 5.5
0.1
12
• System clock frequency
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
2
• CF2 pin open
2.8 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.1
16
2.2 to 5.5
0.1
4
P71 to P73
P70 port input/
Interrupt side
VIL(2)
Ports 0, 8, 3, C
PWM2, PWM3
VIL(3)
Port 70 watchdog
timer side
VIL(4)
Instruction cycle
XT1, XT2, CF1, RES
tCYC
time
(Note2-2)
External system
FEXCF(1)
CF1
clock frequency
VDD
+0.7
2.2 to 5.5
timer side
Low level input
0.3VDD
V
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
μs
division rate=1/1
• External system clock
MHz
duty=50±5%
division rate=1/2
Oscillation
FmCF(1)
CF1, CF2
See Fig. 1.
frequency
range
12MHz ceramic oscillation
FmCF(2)
CF1, CF2
(Note2-3)
8MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
FmRC
Internal RC oscillation
FmMRC
Frequency variable RC
oscillation source oscillation
FsX’tal
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
2.8 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
0.3
1.0
2.5 to 5.5
16
2.2 to 5.5
32.768
MHz
2.0
kHz
Note 2-1: VDD must be held greater than or equal to 2.7V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at
a division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.A0928-11/22
LC87F5R96B
Electrical Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
High level input
IIH(1)
current
IIH(2)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports 3, C
RES
VIN=VDD
(Including output Tr's off leakage
PWM2, PWM3
current))
XT1, XT2
For input port specification
VIN=VDD
Low level input
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports 3, C
RES
VIN=VSS
(Including output Tr's off leakage
PWM2, PWM3
current))
current
IIL(2)
2.2 to 5.5
15
2.2 to 5.5
-1
2.2 to 5.5
-1
-15
VDD-1
VDD
Ports 0, 1, 2
IOH=-1mA
voltage
VOH(2)
Ports 3, C
IOH=-0.4mA
VOH(3)
IOH=-0.2mA
Ports 71 to 73
VOH(5)
VOH(6)
1
2.2 to 5.5
CF1
VOH(1)
IOH=-0.4mA
IOH=-0.2mA
PWM2, PWM3
IOH=-10mA
VOH(7)
IOH=-1.6mA
VOH(8)
IOH=-1mA
unit
2.2 to 5.5
4.5 to 5.5
IIL(3)
max
1
For input port specification
High level output
typ
2.2 to 5.5
XT1, XT2
VIN=VSS
VIN=VSS
VOH(4)
min
3.0 to 5.5
-0.4
2.2 to 5.5
VDD
-0.4
3.0 to 5.5
VDD
-0.4
2.2 to 5.5
VDD
-0.4
4.5 to 5.5
VDD
-1.5
3.0 to 5.5
VDD
-0.4
2.2 to 5.5
VDD
-0.4
V
Low level output
VOL(1)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports 3, C
IOL=1.6mA
3.0 to 5.5
0.4
VOL(3)
IOL=1mA
2.2 to 5.5
0.4
Ports 7, 8
IOL=1.6mA
3.0 to 5.5
0.4
VOL(5)
XT2
IOL=1mA
2.2 to 5.5
0.4
VOL(6)
P00, P01
IOL=30mA
4.5 to 5.5
1.5
VOL(7)
IOL=5mA
3.0 to 5.5
0.4
VOL(8)
IOL=2.5mA
2.2 to 5.5
0.4
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.2 to 5.5
18
35
150
VOL(4)
Pull-up resistance
Hysteresis voltage
PWM2, PWM3,
Rpu(1)
Ports 0, 1, 2, 7
Rpu(2)
Ports 3, C
VHYS
RES
Ports 1, 2, 7
Pin capacitance
CP
All pins
μA
kΩ
2.2to 5.5
0.1VDD
V
2.2 to 5.5
10
pF
• For pins other than that under
test: VIN=VSS
• f=1MHz
• Ta=25°C
No.A0928-12/22
LC87F5R96B
Serial I/O Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Input clock
Parameter
Symbol
Frequency
tSCK(1)
Low level
tSCKL(1)
Specification
Pins
Conditions
/Remarks
SCK0(P12)
VDD[V]
• See Fig. 6.
tSCKH(1)
2.2 to 5.5
pulse width
tSCKHA(1)
tCYC
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.2 to 5.5
pulse width
tSCKHA(2)
1/2
• Continuous data
tSCKH(2)
transmission/reception mode
+2tCYC
• CMOS output selected
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with respect to
rising edge of SIOCLK
2.2 to 5.5
0.03
2.2 to 5.5
0.03
• See fig. 6.
Data hold time
Input clock
Output
thDI(1)
tdD0(1)
delay time
SO0(P10),
SB0(P11),
• Continuous data
transmission/reception mode
2.2 to 5.5
• (Note 4-1-3)
tdD0(2)
(1/3)tCYC
+0.05
μs
• Synchronous 8-bit mode
• (Note 4-1-3)
tdD0(3)
Output clock
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
2.2 to 5.5
1tCYC
+0.05
• (Note 4-1-3)
2.2 to 5.5
(1/3)tCYC
+0.15
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.A0928-13/22
LC87F5R96B
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Input clock
Symbol
Frequency
tSCK(3)
Low level
tSCKL(3)
Specification
Pins/
Conditions
Remarks
SCK1(P15)
VDD[V]
• See Fig. 6.
2.2 to 5.5
pulse width
High level
Frequency
SCK1(P15)
• CMOS output selected.
tSCKL(4)
2
1/2
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14)
SI1(P14),
• Must be specified with respect to
rising edge of SIOCLK
• See fig. 6.
Data hold time
thDI(2)
0.03
2.2 to 5.5
0.03
Output delay
Serial output
tsDI(2)
unit
1
2.2 to 5.5
pulse width
High level
max
1
• See Fig. 6.
Low level
typ
tCYC
tSCKH(3)
tSCK(4)
min
2
pulse width
Output clock
Serial clock
Parameter
time
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect to
falling edge of SIOCLK
• Must be specified as the time to
the beginning of output state
2.2 to 5.5
(1/3)tCYC
+0.05
change in open drain output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.A0928-14/22
LC87F5R96B
Pulse Input Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1 are
min
typ
max
unit
enabled.
INT2(P72)
2.2 to 5.5
INT4(P20 to P23),
1
INT5(P24 to P27),
INT6(P20)
INT7(P24)
tCYC
tPIH(2)
INT3(P73) when noise filter
• Interrupt source flag can be set.
tPIL(2)
time constant is 1/1.
• Event inputs for timer 0 are enabled.
tPIH(3)
INT3(P73) when noise filter
• Interrupt source flag can be set.
tPIL(3)
time constant is 1/32
• Event inputs for timer 0 are enabled.
tPIH(4)
INT3(P73) when noise filter
• Interrupt source flag can be set.
tPIL(4)
time constant is 1/128
• Event inputs for timer 0 are enabled.
tPIL(5)
RES
Resetting is enabled.
2.2 to 5.5
2
2.2 to 5.5
64
2.2 to 5.5
256
2.2 to 5.5
200
μs
AD Converter Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Resolution
N
AN0(P80) to
Absolute
ET
AN6(P86),
(Note 6-1)
Conversion time
AN9(P71),
AD conversion time=32×tCYC
AN10(XT1),
(when ADCR2=0)
(Note 6-2)
4.5 to 5.5
AN11(XT2),
3.0 to 5.5
AD conversion time=64×tCYC
(when ADCR2=1)
(Note 6-2)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
max
unit
8
bit
±1.5
3.0 to 5.5
AN8(P70),
Analog input
typ
3.0 to 5.5
accuracy
TCAD
min
11.74
97.92
(tCYC=
(tCYC=
0.367μs)
3.06μs)
23.53
97.92
(tCYC=
(tCYC=
0.735μs)
3.06μs)
15.68
97.92
(tCYC=
(tCYC=
0.245μs)
1.53μs)
23.49
97.92
(tCYC=
(tCYC=
0.376μs)
1.53μs)
VSS
VDD
1
-1
LSB
μs
V
μA
Note 6-1: The quantization error (±1/2 LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.A0928-15/22
LC87F5R96B
Consumption Current Characteristics at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Normal mode
IDDOP(1)
consumption
VDD1
=VDD2
current
=VDD3
(Note 7-1)
min
typ
max
unit
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
9.1
18.5
2.8 to 4.5
5.3
13.5
4.5 to 5.5
6.7
14
2.5 to 4.5
3.8
10
4.5 to 5.5
2.7
6
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(2)
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 8MHz side
IDDOP(3)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDOP(4)
• FmCF=4MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
mA
• System clock set to 4MHz side
IDDOP(5)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.2 to 4.5
1.45
3.8
4.5 to 5.5
0.95
4.3
2.2 to 4.5
0.53
3.0
4.5 to 5.5
1.25
5.2
2.2 to 4.5
0.67
4.2
4.5 to 5.5
38
112
• 1/1 frequency division ratio.
IDDOP(6)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to internal RC oscillation
IDDOP(7)
• frequency variable RC oscillation stopped
•1/2 frequency division ratio.
IDDOP(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 1MHz with frequency
IDDOP(9)
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
IDDOP(10)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
μA
• System clock set to 32.768kHz side.
IDDOP(11)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
2.2 to 4.5
19
72
4.5 to 5.5
3.2
7.5
2.8 to 5.5
1.8
4
• 1/2 frequency division ratio.
HALT mode
IDDHALT(1)
consumption
current
(Note 7-1)
VDD1
=VDD2
=VDD3
• HALT mode
• FmCF=12MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
mode
• System clock set to 12MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(2)
mA
• HALT mode
• FmCF=8MHz ceramic oscillation mode
• FmX’tal=32.768kHz by crystal oscillation
4.5 to 5.5
2.4
5.3
2.5 to 4.5
12.5
2.8
mode
IDDHALT(3)
• System clock set to 8MHz side
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
Continued on next page.
No.A0928-16/22
LC87F5R96B
Continued from preceding page.
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
• HALT mode
consumption
VDD1
=VDD2
current
=VDD3
• FmX’tal=32.768kHz by crystal oscillation
HALT mode
IDDHALT(4)
• FmCF=4MHz ceramic oscillation mode
min
typ
max
4.5 to 5.5
1
2.3
2.2 to 4.5
0.5
1.3
4.5 to 5.5
0.33
0.9
unit
mode
(Note 7-1)
• System clock set to 4MHz side
IDDHALT(5)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
• 1/1 frequency division ratio.
IDDHALT(6)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz by crystal oscillation
mA
mode
IDDHALT(7)
• System clock set to internal RC oscillation
• frequency variable RC oscillation stopped
2.2 to 4.5
0.17
0.7
4.5 to 5.5
1
3.8
2.2 to 4.5
0.5
2.7
4.5 to 5.5
18
73
2.2 to 4.5
5
65
4.5 to 5.5
0.035
20
2.2 to 4.5
0.015
16
4.5 to 5.5
16
65
2.2 to 4.5
3.5
52
•1/2 frequency division ratio.
• HALT mode
IDDHALT(8)
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 1MHz with frequency
IDDHALT(9)
variable RC oscillation
• Internal RC oscillation stopped
• 1/2 frequency division ratio.
IDDHALT(10)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX'tal=32.768kHz by crystal oscillation
mode.
• System clock set to 32.768kHz side.
IDDHALT(11)
• Internal RC oscillation stopped
• frequency variable RC oscillation stopped
μA
• 1/2 frequency division ratio.
HOLD mode
consumption
current
Timer HOLD
IDDHOLD(1)
VDD1
• CF1=VDD or open (External clock mode)
IDDHOLD(2)
IDDHOLD(3)
• Timer HOLD mode
mode
consumption
• HOLD mode
• CF1=VDD or open (External clock mode)
• FmX'tal=32.768kHz by crystal oscillation
IDDHOLD(4)
current
mode
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors
F-ROM Programming Characteristics at Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Onboard
IDDFW(1)
VDD1
min
typ
max
unit
• Without CPU current
programming
2.70 to 5.5
5
10
mA
current
Programming
tFW(1)
• Erasing
2.7 to 5.5
20
30
ms
time
tFW(2)
• programming
2.7 to 5.5
40
60
μs
No.A0928-17/22
LC87F5R96B
UART (Full Duplex) Operating Conditions at Ta = -40°C to +85°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pins/Remarks
Conditions
VDD[V]
Transfer rate
UBR
min
typ
max
unit
8192/3
tCYC
P32 (UTX1),
P33 (URX1),
2.5 to 5.5
P34 (UTX2),
16/3
P35 (URX2)
Data length : 7/8/9 bits (LSB first)
Stop bits : 1-bit (2-bit in continuous data transmission)
Parity bits : None
Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data = 55H)
Stop bit
Start bit
Start of
transmission
Transmit data (LSB first)
End of
transmission
UBR
Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data = 55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR
VDD1, VSS1 Terminal Condition
It is necessary to place capacitors between VDD1 and VSS1 as describe below.
• Place capacitors as close to VDD1 and VSS1 as possible.
• Place capacitors so that the length of each terminal to the each leg of the capacitor be equal (L1 = L1’, L2 = L2’).
• Place high capacitance capacitor C1 and low capacitance capacitor C2 in parallel.
• Capacitance of C2 must be more than 0.1μF.
• Use thicker pattern for VDD1 and VSS1.
L2
L1
VSS1
C1
C2
VDD1
L1’
L2’
No.A0928-18/22
LC87F5R96B
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Nominal
Vendor
Frequency
Name
Circuit Constant
Oscillator Name
12MHz
Operating
Oscillation
Voltage
Stabilization Time
C1
C2
Rf1
Rd1
Range
[pF]
[pF]
[Ω]
[Ω]
CSTCE12M0G52-R0
(10)
(10)
Open
CSTCE10M0G52-R0
(10)
(10)
CSTLS10M0G53-B0
(15)
(15)
Remarks
typ
max
[V]
[ms]
[ms]
470
2.6 to 5.5
0.03
0.5
Open
470
2.4 to 5.5
0.03
0.5
Internal C1,C2
Open
680
2.6 to 5.5
0.03
0.5
Internal C1,C2
Internal C1,C2
10MHz
MURATA
CSTCE8M00G52-R0
(10)
(10)
Open
680
2.3 to 5.5
0.03
0.5
Internal C1,C2
CSTLS8M00G53-B0
(15)
(15)
Open
1k
2.5 to 5.5
0.03
0.5
Internal C1,C2
CSTCR4M00G53-R0
(15)
(15)
Open
1.5k
2.2 to 5.5
0.03
0.5
Internal C1,C2
CSTLS4M00G53-B0
(15)
(15)
Open
1.5k
2.2 to 5.5
0.03
0.5
Internal C1,C2
8MHz
4MHz
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Fig. 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
SEIKO
TOYOCOM
Circuit Constant
Oscillator Name
MC-306
Operating Voltage
C3
C4
Rf2
Rd2
[pF]
[pF]
[Ω]
[Ω]
18
18
Open
560k
Range
[V]
2.2 to 5.5
Oscillation
Stabilization Time
typ
max
[s]
[s]
1.2
3.0
Remarks
Applicable
CL value=12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure. 4).
Note: The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
Rf1
XT1
Rd1
XT2
Rf2
Rd2
C1
C2
CF
C3
C4
X’tal
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.A0928-19/22
LC87F5R96B
VDD
Operating VDD lower
limit
0V
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
Operating mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal
absent
HOLD reset signal VALID
Internal RC
oscillation
tmsCF
CF1, CF2
tmsX’tal
XT1, XT2
State
HOLD
HALT
HOLD Release Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.A0928-20/22
LC87F5R96B
VDD
RRES
Note:
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKLA
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.A0928-21/22
LC87F5R96B
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