EN8297 D

Ordering number : EN8297A
LC87F5JC8A
CMOS IC
FROM 128K byte, RAM 4096 byte on-chip
http://onsemi.com
8-bit 1-chip Microcontroller
Overview
The LC87F5JC8A is an 8-bit microcomputer that, centered around a CPU running at a minimum bus cycle time of
83.3ns, integrates on a single chip a number of hardware features such as 128K byte flash ROM (onboard
programmable), 4096 byte RAM, an on-chip debugger, sophisticated 16-bit timers/counters (may be divided into 8bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit PWMs), four 8-bit timers with
a prescaler, a 16-bit timer with a prescaler (may be divided into 8-bit timers), a base timer serving as a time-of-day
clock,
a high-speed clock counter, a synchronous SIO interface (with automatic block transmission/reception capabilities),
an asynchronous/synchronous SIO interface, a UART interface (full duplex), an 8-bit 11-channel AD converter, two
12-bit PWM channels, a system clock frequency divider, ROM correction function, and a 26-source 10-vector
interrupt feature.
Features
Flash ROM
• Capable of on-board-programing with wide range, 3.0 to 5.5V, of voltage source.
• Block-erasable in 128 byte units
• 131072 × 8-bits (LC87F5JC8A)
RAM
• 4096 × 9-bits (LC87F5JC8A)
Minimum Bus Cycle
• 83.3ns (12MHz)
VDD=3.0 to 5.5V
• 125ns (8MHz)
VDD=2.5 to 5.5V
• 500ns (2MHz)
VDD=2.2 to 5.5V
Note: The bus cycle time here refers to the ROM read speed.
* This product is licensed from Silicon Storage Technology, Inc. (USA).
Semiconductor Components Industries, LLC, 2013
May, 2013
Ver.1.05
20707HKIM 20060222-S00012 No.8297-1/25
LC87F5JC8A
Minimum Instruction Cycle Time
• 250ns (12MHz)
VDD=3.0 to 5.5V
• 375ns (8MHz)
VDD=2.5 to 5.5V
• 1.5μs (2MHz)
VDD=2.2 to 5.5V
Ports
• Normal withstand voltage I/O ports
Ports whose I/O direction can be designated in 1-bit units
Ports whose I/O direction can be designated in 4-bit units
• Normal withstand voltage input port
• Dedicated oscillator ports
• Reset pins
• Power pins
46 (P1n, P2n, P70 to P73, P80 to P86, PBn, PCn,
PWM2, PWM3, XT2)
8 (P0n)
1 (XT1)
2 (CF1, CF2)
1 (RES)
6 (VSS1 to 3, VDD1 to 3)
Timers
• Timer 0: 16-bit timer/counter with two capture registers.
Mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) × 2-channels
Mode 1: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) + 8-bit counter
(with two 8-bit capture registers)
Mode 2: 16-bit timer with an 8-bit programmable prescaler (with two 16-bit capture registers)
Mode 3: 16-bit counter (with two 16-bit capture registers)
• Timer 1: 16-bit timer/counter that supports PWM/toggle outputs
Mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter with an 8-bit prescaler
(with toggle outputs)
Mode 1: 8-bit PWM with an 8-bit prescaler × 2-channels
Mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs)
(toggle outputs also possible from the lower-order 8-bits)
Mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (The lower-order 8-bits can be used as PWM)
• Timer 4: 8-bit timer with a 6-bit prescaler
• Timer 5: 8-bit timer with a 6-bit prescaler
• Timer 6: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 7: 8-bit timer with a 6-bit prescaler (with toggle output)
• Timer 8: 16-bit timer
Mode 0: 8-bit timer with an 8-bit prescaler ×2-channels
Mode 1: 16-bit timer with an 8-bit prescaler
* Timer 8 is not supported in this version of Emulator. Please use on-chip-debugger for debugging when developing
software.
• Base Timer
1) The clock is selectable from the subclock (32.768kHz crystal oscillation), system clock, and timer 0 prescaler
output.
2) Interrupts programmable in 5 different time schemes
High-speed Clock Counter
1. Can count clocks with a maximum clock rate of 20MHz (at a main clock of 10MHz).
2. Can generate output real-time.
SIO
• SIO0: 8-bit synchronous serial interface
1) LSB first/MSB first mode selectable
2) Built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tCYC)
3) Automatic continuous data transmission (1 to 256 bits, specifiable in 1 bit units, suspension and resumption of
data transmission possible in 1 byte units)
• SIO1: 8-bit asynchronous/synchronous serial interface
Mode 0: Synchronous 8-bit serial I/O (2- or 3-wire configuration, 2 to 512 tCYC transfer clocks)
Mode 1: Asynchronous serial I/O (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tCYC baudrates)
Mode 2: Bus mode 1 (start bit, 8 data bits, 2 to 512 tCYC transfer clocks)
Mode 3: Bus mode 2 (start detect, 8 data bits, stop detect)
No.8297-2/25
LC87F5JC8A
UART
• Full duplex
• 7/8/9 bit data bits selectable
• 1 stop bit(2-bit in continuous data transmission)
• Built-in baudrate generator
AD Converter: 8-bit × 11-channels
PWM: Multifrequency 12-bit PWM × 2-channels
Remote Control Receiver Circuit (sharing pins with P73, INT3, and T0IN)
• Noise rejection function (noise filter time constant selectable from 1 tCYC, 32 tCYC, and 128 tCYC)
Watchdog Timer
• External RC watchdog timer
• Interrupt and reset signals selectable
Clock Output Function
1) Able to output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 as system clock.
2) Able to output oscillation clock of sub clock.
Interrupts
• 26 sources, 10 vector addresses
1) Provides three levels (low (L), high (H), and highest (X)) of multiplex interrupt control. Any interrupt requests
of the level equal to or lower than the current interrupt are not accepted.
2) When interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest
level takes precedence over the other interrupts. For interrupts of the same level, the interrupt into the smallest
vector address takes precedence.
No.
Vector Address
Level
1
00003H
X or L
INT0
Interrupt Source
2
0000BH
X or L
INT1
3
00013H
H or L
INT2/T0L/INT4
4
0001BH
H or L
INT3/INT5/base timer
5
00023H
H or L
T0H/INT6
6
0002BH
H or L
T1L/T1H/INT7
7
00033H
H or L
SIO0/UART1 receive/T8L/T8H
8
0003BH
H or L
SIO1/UART1 transmit
9
00043H
H or L
ADC/T6/T7
10
0004BH
H or L
Port 0/T4/T5/PWM2, PWM3
• Priority levels X > H > L
• Of interrupts of the same level, the one with the smallest vector address takes precedence.
• IFLG (list of interrupt source flag function)
3) Shows a list of interrupt source flags that caused a branching to a particular vector address (shown in the
diagram above).
Subroutine Stack Levels: 2048 levels (the stack is allocated in RAM)
High-speed Multiplication/Division Instructions
• 16-bits × 8-bits
(5 tCYC execution time)
• 24-bits × 16-bits
(12 tCYC execution time)
• 16-bits ÷ 8-bits
(8 tCYC execution time)
• 24-bits ÷ 16-bits
(12 tCYC execution time)
No.8297-3/25
LC87F5JC8A
Oscillation Circuits
• RC oscillation circuit (internal):
• CF oscillation circuit:
• Crystal oscillation circuit:
• Frequency variable RC oscillation circuit (internal):
For system clock
For system clock, with internal Rf
For low-speed system clock, with internal Rf
For system clock
System Clock Divider Function
• Can run on low current.
• The minimum instruction cycle selectable from 300ns, 600ns, 1.2μs, 2.4μs, 4.8μs, 9.6μs, 19.2μs, 38.4μs, and 76.8μs
(at a main clock rate of 10MHz).
Standby Function
• HALT mode: Halts instruction execution while allowing the peripheral circuits to continue operation.
1) Oscillation is not halted automatically.
2) Canceled by a system reset or occurrence of an interrupt
• HOLD mode: Suspends instruction execution and the operation of the peripheral circuits.
1) The CF, RC, and crystal oscillators automatically stop operation.
2) There are three ways of resetting the HOLD mode.
(1) Setting the reset pin to the low level.
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
• X'tal HOLD mode: Suspends instruction execution and the operation of the peripheral circuits except the base
timer.
1) The CF and RC oscillators automatically stop operation.
2) The state of crystal oscillation established when the X'tal HOLD mode is entered is retained.
3) There are four ways of resetting the X'tal HOLD mode.
(1) Setting the reset pin to the low level
(2) Setting at least one of the INT0, INT1, INT2, INT4, and INT5 pins to the specified level
(3) Having an interrupt source established at port 0
(4) Having an interrupt source established in the base timer circuit
ROM Correction Function
• Executes the correction program on detection of a match with the program counter value.
• Correction program area size: 128 bytes
On-chip Debugger
• Supports software debugging with the IC mounted on the target board.
Package Form
• QIP64E (14×14):
• TQFP64J (10×10):
• TQFP64J (7×7):
Development Tools
• Evaluation chip:
• Emulator:
• On-chip debugger:
Lead-free type
Lead-free type
Lead-free type
LC87EV690
EVA62S + ECB876600D + SUB875800 + POD64QFP or POD64SQFP
ICE-B877300 + SUB875800 + POD64QFP or POD64SQFP
TCB87-TypeA or TCB87-TypeB+LC87F5JC8A
No.8297-4/25
LC87F5JC8A
Flash ROM Programming Boards
Package
Programming boards
QIP64E (14×14)
W87F50256Q
TQFP64J (10×10)
W87F57256SQ
TQFP64J (7×7)
W87F58256TQ7
Flash ROM Programmer
Maker
Flash Support Group, Inc.
Model
Single
(Formerly Ando Electric
Co., Ltd.)
Our company
AF9708/AF9709/
Supported version (Note)
After 02.40
Device
LC87F5JC8A FAST
AF9709B
Gang
AF9723 (Main body)
After 02.04
AF9833 (Unit)
After 01.84
SKK (Sanyo FWS)
After 1.02C (Install CD)
LC87F5JC8A
Note: Please check the latest version.
No.8297-5/25
LC87F5JC8A
Package Dimensions
Package Dimensions
unit : mm (typ)
3159A
unit : mm (typ)
3310
12.0
17.2
14.0
33
64
17
17
1
16
0.18
0.125
(1.25)
0.15
SANYO : TQFP64J(10X10)
0.1
3.0max
(2.7)
1.2 MAX
(1.0)
(1.0)
0.35
0.8
16
0.5
0.1
1
0.5
32
17.2
14.0
64
49
10.0
32
49
33
12.0
48
0.8
10.0
48
SANYO : QIP64E(14X14)
Package Dimensions
unit : mm (typ)
3289
9.0
33
32
64
17
7.0
49
1
16
0.4
0.16
9.0
48
0.5
7.0
0.125
0.1
1.2max
(1.0)
(0.5)
SANYO : TQFP64J(7X7)
No.8297-6/25
LC87F5JC8A
PB1
PB0
VSS3
VDD3
PC7/DBGP2
PC6/DBGP1
PC5/DBGP0
PC4
PC3
PC2
PC1
PC0
P86/AN6
P85/AN5
P84/AN4
P83/AN3
Pin Assignment
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
P70/INT0/T0LCP/AN8
49
32
PB2
P71/INT1/T0HCP/AN9
50
31
PB3
P72/INT2/T0IN
51
30
PB4
P73/INT3/T0IN
52
29
PB5
RES
53
28
PB6
XT1/AN10
54
27
PB7
XT2/AN11
55
26
P27/INT5/T1IN
VSS1
56
25
P26/INT5/T1IN
CF1
57
24
P25/INT5/T1IN
LC87F5JC8A
P22/INT4/T1IN
P81/AN1
61
20
P21/URX/INT4/T1IN
P82/AN2
62
19
P20/UTX/INT4/T1IN/INT6/T0LCP1
P10/SO0
63
18
P07/T7O
P11/SI0/SB0
64
17
P06/T6O
8
9 10 11 12 13 14 15 16
P05/CKO
7
P04
6
P03
5
P02
4
P01
3
P00
2
VSS2
1
VDD2
21
PWM3
60
PWM2
P80/AN0
P17/T1PWMH/BUZ
P23/INT4/T1IN
P16/T1PWML
22
P15/SCK1
P24/INT5/T1IN/INT7/T0HCP1
P14/SI1/SB1
23
59
P13/SO1
58
P12/SCK0
CF2
VDD1
Top view
QIP64E(14×14) “Lead-free Type”
TQFP64J(10×10) “Lead-free Type”
TQFP64J(7×7) “Lead-free Type”
No.8297-7/25
LC87F5JC8A
System Block Diagram
Interrupt control
IR
ROM correct
Standby control
CF
MRC
Flash ROM
Clock
generator
RC
PLA
X’tal
PC
SIO0
Bus interface
SIO1
Port 0
ACC
Timer 0
Port 1
B register
Timer 1
Port 2
C register
Timer 4
Port 7
ALU
Timer 5
Port 8
Timer 6
ADC
PSW
Timer 7
INT0 to 7
Noise filter
RAR
Timer 8
Port B
RAM
Base timer
Port C
Stack pointer
PWM2/3
UART1
Watchdog timer
On-chip debugger
No.8297-8/25
LC87F5JC8A
Pin Description
Pin Name
VSS1
VSS2
VSS3
VDD1
I/O
Description
Option
-
-Power supply pin
No
-
+Power supply pin
No
• 8-bit I/O port
Yes
VDD2
VDD3
Port 0
I/O
• I/O specifiable in 4-bit units
P00 to P07
• Pull-up resistors can be turned on and off in 4-bit units.
• HOLD reset input
• Port 0 interrupt input
• Shared pins
P05 : Clock output (system clock/can selected from sub clock)
P06 : Timer 6 toggle output
P07 : Timer 7 toggle output
Port 1
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
P10 to P17
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P10 : SIO0 data output
P11 : SIO0 data input/bus I/O
P12 : SIO0 clock I/O
P13 : SIO1 data output
P14 : SIO1 data input/bus I/O
P15 : SIO1 clock I/O
P16 : Timer 1PWML output
P17 : Timer 1PWMH output/beeper output
Port 2
P20 to P27
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
• Pull-up resistors can be turned on and off in 1-bit units.
• Pin functions
P20 : UART transmit
P21 : UART receive
P20 to P23 : INT4 input/HOLD reset input/timer 1 event input/timer 0L capture input/timer
0H capture input
P24 to P27 : INT5 input/HOLD reset input/timer 1 event input/timer 0L capture input/timer
0H capture input
P20 : INT6 input/timer 0L capture 1 input
P24 : INT7 input/timer 0H capture 1 input
Interrupt acknowledge type
Rising
Falling
INT4
enable
enable
INT5
enable
enable
INT6
enable
INT7
enable
Rising &
H level
L level
enable
disable
disable
enable
disable
disable
enable
enable
disable
disable
enable
enable
disable
disable
Falling
Continued on next page.
No.8297-9/25
LC87F5JC8A
Continued from preceding page.
Pin Name
Port 7
I/O
I/O
Description
Option
No
• 4-bit I/O port
• I/O specifiable in 1-bit units
P70 to P73
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
P70 : INT0 input/HOLD reset input/timer 0L capture input/watchdog timer output
P71 : INT1 input/HOLD reset input/timer 0H capture input
P72 : INT2 input/HOLD reset input/timer 0 event input/timer 0L capture input/High speed clock
counter input
P73 : INT3 input (with noise filter)/timer 0 event input/timer 0H capture input
AD converter input port : AN8 (P70), AN9 (P71)
Interrupt acknowledge type
Port 8
I/O
Rising &
Rising
Falling
INT0
enable
enable
disable
enable
enable
INT1
enable
enable
disable
enable
enable
INT2
enable
enable
enable
disable
disable
INT3
enable
enable
enable
disable
disable
Falling
• 7-bit I/O port
H level
L level
No
• I/O specifiable in 1-bit units
P80 to P86
• Shared pins
AD converter input : port: AN0 (P80) to AN6 (P86)
PWM2
I/O
PWM3
Port B
• PWM2 and PWM3 output ports
No
• General-purpose I/O available
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PB0 to PB7
• Pull-up resistors can be turned on and off in 1-bit units.
Port C
I/O
• 8-bit I/O port
Yes
• I/O specifiable in 1-bit units
PC0 to PC7
• Pull-up resistors can be turned on and off in 1-bit units.
• Shared pins
On-chip debugger pins : DBGP0 to DBGP2 (PC5 to PC7)
RES
Input
Reset pin
No
XT1
Input
• 32.768kHz crystal oscillator input pin
No
• Shared pins
General-purpose input port
AD converter input port : AN10
Must be connected to VDD1 if not to be used.
XT2
I/O
• 32.768kHz crystal oscillator output pin
No
• Shared pins
General-purpose I/O port
AD converter input port : AN11
Must be set for oscillation and kept open if not to be used.
CF1
Input
CF2
Output
Ceramic resonator input pin
No
Ceramic resonator output pin
No
No.8297-10/25
LC87F5JC8A
Port Output Configuration
The table below lists the types of port outputs and the presence/absence of a pull-up resistor.
Data can be read into any input port even if it is in the output mode.
Port Name
Option Selected
in Units of
P00 to P07
1-bit
P10 to P17
1-bit
P20 to P27
1-bit
Option Type
Output Type
Pull-Up Resistor
1
CMOS
Programmable (Note 1)
2
Nch-open drain
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
Nch-open drain
Programmable
P70
-
No
P71 to P73
-
No
CMOS
Programmable
P80 to P86
-
No
Nch-open drain
No
PWM2, PWM3
-
No
CMOS
No
1
CMOS
Programmable
2
Nch-open drain
Programmable
1
CMOS
Programmable
2
Nch-open drain
Programmable
PB0 to PB7
1-bit
PC0 to PC7
1-bit
XT1
-
No
-
No
XT2
Input for 32.768kHz crystal oscillator
(Input only)
No
Output for 32.768kHz crystal oscillator
(Nch-open drain when in general-purpose
No
output mode)
Note 1 : Programmable pull-up resistors for port 0 are controlled in 4-bit units (P00 to 03, P04 to 07).
*1 : Connect the IC as shown below to minimize the noise input to the VDD1 pin.
Be sure to electrically short the VSS1, VSS2, and VSS3 pins.
LSI
VDD1
Power
supply
For backup *2
VDD2
VDD3
VSS1
VSS2
VSS3
*2 : The internal memory is sustained by VDD1. If none of VDD2 and VDD3 are backed up, the high level output at
the ports are unstable in the HOLD backup mode, allowing through current to flow into the input buffer and thus
shortening the backup time.
Make sure that the port outputs are held at the low level in the HOLD backup mode.
No.8297-11/25
LC87F5JC8A
Absolute Maximum Ratings / Ta = 25°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Maximum supply
VDD max
VDD1, VDD2, VDD3
VDD1=VDD2=VDD3
voltage
Input voltage
VI(1)
XT1, CF1
Input/output voltage
VIO(1)
Ports 0, 1, 2
min
typ
max
-0.3
+6.5
-0.3
VDD+0.3
unit
V
Ports 7, 8
-0.3
Ports B, C
VDD+0.3
PWM2, PWM3, XT2
Peak output
IOPH(1)
current
High level output current
Mean output
CMOS output select
Per 1 applicable pin
PWM2, PWM3
Per 1 applicable pin
-20
IOPH(3)
P71 to P73
Per 1 applicable pin
-5
IOMH(1)
Ports 0, 1, 2
CMOS output select
Ports B, C
Per 1 applicable pin
IOMH(2)
PWM2, PWM3
Per 1 applicable pin
IOMH(3)
P71 to P73
Per 1 applicable pin
Total output
ΣIOAH(1)
P71 to P73
Total of all applicable pins
current
ΣIOAH(2)
Port 1
Total of all applicable pins
PWM2, PWM3
ΣIOAH(3)
Ports 0, 2
Total of all applicable pins
ΣIOAH(4)
Ports 0, 1, 2
Total of all applicable pins
PWM2, PWM3
Peak output
-10
IOPH(2)
current
(Note 1-1)
Ports 0, 1, 2
Ports B, C
-7.5
-15
-3
-10
-25
-25
-45
ΣIOAH(5)
Port B
Total of all applicable pins
-25
ΣIOAH(6)
Port C
Total of all applicable pins
-25
ΣIOAH(7)
Ports B, C
Total of all applicable pins
-45
P02 to P07
Per 1 applicable pin
IOPL(1)
current
Ports 1, 2
20
Ports B, C
PWM2, PWM3
IOPL(2)
P00, P01
Per 1 applicable pin
IOPL(3)
Ports 7, 8
Per 1 applicable pin
XT2
Low level output current
Mean output
IOML(1)
P02 to P07
current
Ports 1, 2
(Note 1-1)
Ports B, C
30
mA
10
Per 1 applicable pin
15
PWM2, PWM3
IOML(2)
P00, P01
Per 1 applicable pin
IOML(3)
Ports 7, 8
Per 1 applicable pin
XT2
Total output
ΣIOAL(1)
current
Port 7
Total of all applicable pins
P83 to P86, XT2
ΣIOAL(2)
P80 to P82
Total of all applicable pins
ΣIOAL(3)
Ports 7, 8
Total of all applicable pins
XT2
ΣIOAL(4)
Port 1
Total of all applicable pins
PWM2, PWM3
ΣIOAL(5)
Ports 0, 2
Total of all applicable pins
ΣIOAL(6)
Ports 0, 1, 2
Total of all applicable pins
PWM2, PWM3
20
7.5
15
15
20
45
45
80
ΣIOAL(7)
Port B
Total of all applicable pins
45
ΣIOAL(8)
Port C
Total of all applicable pins
45
ΣIOAL(9)
Ports B, C
Total of all applicable pins
80
Note 1-1: The mean output current is a mean value measured over 100ms.
Continued on next page.
No.8297-12/25
LC87F5JC8A
Continued from preceding page.
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Power dissipation
Operating ambient
Pd max
Topr
temperature
Storage ambient
temperature
Tstg
QIP64E (14×14)
min
Ta= -20 to +70°C
typ
max
unit
377
TQFP64J (10×10)
246
TQFP64J (7×7)
164
-20
+70
-55
+125
mW
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
No.8297-13/25
LC87F5JC8A
Recommended Operating Range / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Operating
VDD(1)
VDD1=VDD2=VDD3
0.245μs ≤ tCYC ≤ 200μs
min
typ
max
3.0
unit
5.5
supply voltage
0.367μs ≤ tCYC ≤ 200μs
2.5
5.5
(Note 2-1)
1.47μs ≤ tCYC ≤ 200μs
2.2
5.5
2.0
5.5
Memory
VHD
VDD1=VDD2=VDD3
sustaining
RAM and register contents
sustained in HOLD mode.
supply voltage
High level input
VIH(1)
voltage
Ports 1, 2
P71 to P73
2.2 to 5.5
P70 port input
0.3VDD
VDD
+0.7
/interrupt side
VIH(2)
Ports 0, 8, B, C
2.2 to 5.5
PWM2, PWM3
VIH(3)
Port 70 watchdog
timer side
VIH(4)
XT1, XT2, CF1
RES
Low level input
VIL(1)
voltage
Ports 1, 2
P71 to P73
P70 port input
/interrupt side
VIL(2)
Ports 0, 8, B, C
PWM2, PWM3
VIL(3)
Port 70 watchdog
timer side
VIL(4)
XT1, XT2, CF1
RES
Instruction cycle
tCYC
time
(Note 2-2)
External system
FEXCF(1)
CF1
clock frequency
• CF2 pin open
0.3VDD
VDD
+0.7
2.2 to 5.5
0.9VDD
VDD
2.2 to 5.5
0.75VDD
VDD
4.0 to 5.5
VSS
2.2 to 4.0
VSS
4.0 to 5.5
VSS
2.2 to 4.0
VSS
2.2 to 5.5
VSS
2.2 to 5.5
VSS
0.25VDD
3.0 to 5.5
0.245
200
2.5 to 5.5
0.367
200
2.2 to 5.5
1.47
200
3.0 to 5.5
0.1
12
2.5 to 5.5
0.1
8
2.2 to 5.5
0.1
2
V
0.1VDD
+0.4
0.2VDD
0.15VDD
+0.4
0.2VDD
0.8VDD
-1.0
μs
• System clock frequency
division ratio=1/1
• External system clock duty
=50 ± 5%
• CF2 pin open
3.0 to 5.5
0.2
24.4
• System clock frequency
2.5 to 5.5
0.2
16
2.2 to 5.5
0.2
4
division ratio=1/2
Oscillation
FmCF(1)
CF1, CF2
frequency range
(Note 2-3)
12MHz ceramic oscillation
See Fig. 1.
FmCF(2)
CF1, CF2
8MHz ceramic oscillation
See Fig. 1.
FmCF(3)
CF1, CF2
4MHz ceramic oscillation
See Fig. 1.
FmRC
Internal RC oscillation
FmMRC
Frequency variable RC
oscillation source oscillation
FsX’tal
XT1, XT2
32.768kHz crystal oscillation
See Fig. 2.
3.0 to 5.5
12
2.5 to 5.5
8
2.2 to 5.5
4
2.2 to 5.5
0.3
1.0
2.2 to 5.5
16
2.2 to 5.5
32.768
MHz
MHz
2.0
kHz
Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.
Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at a
division ratio of 1/2.
Note 2-3: See Tables 1 and 2 for the oscillation constants.
No.8297-14/25
LC87F5JC8A
Electrical Characteristics / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
High level input
IIH(1)
current
IIH(2)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
RES
VIN=VDD
(Including output Tr's off leakage
PWM2, PWM3
current)
XT1, XT2
IIH(3)
CF1
VIN=VDD
IIL(1)
Ports 0, 1, 2
Output disabled
Ports 7, 8
Pull-up resistor off
Ports B, C
RES
VIN=VSS
(Including output Tr's off leakage
PWM2, PWM3
current)
current
IIL(2)
XT1, XT2
typ
For input port specification
VIN=VSS
2.2 to 5.5
1
2.2 to 5.5
1
2.2 to 5.5
15
2.2 to 5.5
-1
2.2 to 5.5
-1
IIL(3)
CF1
VIN=VSS
2.2 to 5.5
-15
High level output
VOH(1)
Ports 0, 1, 2
IOH= -1mA
4.5 to 5.5
VDD-1
voltage
VOH(2)
Ports B, C
IOH= -0.4mA
3.0 to 5.5
VDD-0.4
IOH= -0.2mA
2.2 to 5.5
VDD-0.4
IOH= -0.4mA
3.0 to 5.5
VDD-0.4
IOH= -0.2mA
2.2 to 5.5
VDD-0.4
IOH= -10mA
4.5 to 5.5
VDD-1.5
VOH(7)
IOH= -1.6mA
3.0 to 5.5
VDD-0.4
VOH(8)
IOH= -1mA
2.2 to 5.5
VDD-0.4
VOH(3)
VOH(4)
P71 to P73
VOH(5)
VOH(6)
PWM2, PWM3
max
VOL(1)
Ports 0, 1, 2
IOL=10mA
4.5 to 5.5
1.5
voltage
VOL(2)
Ports B, C
IOL=1.6mA
3.0 to 5.5
0.4
IOL=1mA
2.2 to 5.5
0.4
Pull-up resistance
Hysteresis voltage
PWM2, PWM3
VOL(4)
Ports 7, 8
IOL=1.6mA
3.0 to 5.5
0.4
VOL(5)
XT2
IOL=1mA
2.2 to 5.5
0.4
VOL(6)
P00, P01
IOL=30mA
4.5 to 5.5
1.5
VOL(7)
IOL=5mA
3.0 to 5.5
0.4
VOL(8)
IOL=2.5mA
2.2 to 5.5
VOH=0.9VDD
4.5 to 5.5
15
35
80
2.2 to 5.5
18
50
150
Rpu(1)
Ports 0, 1, 2, 7
Rpu(2)
Ports B, C
VHYS
RES
Pin capacitance
CP
All pins
0.4
kΩ
2.2 to 5.5
Ports 1, 2, 7
μA
V
Low level output
VOL(3)
unit
For input port specification
VIN=VDD
Low level input
min
0.1
VDD
V
For pins other than that under test:
VIN=VSS
f=1MHz
2.2 to 5.5
10
pF
Ta=25°C
No.8297-15/25
LC87F5JC8A
Serial I/O Characteristics at Ta=-20 to +70°C, VSS1=VSS2=VSS3=0V
1. SIO0 Serial I/O Characteristics (Note 4-1-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
VDD[V]
Frequency
tSCK(1)
Low level
tSCKL(1)
SCK0(P12)
See Fig. 6.
tSCKH(1)
2.2 to 5.5
pulse width
tSCKHA(1)
tCYC
4
• (Note 4-1-2)
Frequency
tSCK(2)
SCK0(P12)
• CMOS output selected
4/3
• See Fig. 6.
Output clock
Low level
tSCKL(2)
1/2
pulse width
High level
tSCK
tSCKH(2)
2.2 to 5.5
pulse width
tSCKHA(2)
1/2
• Continuous data
transmission/reception mode
tSCKH(2)
• CMOS output selected
+2tCYC
• See Fig. 6.
Data setup time
Serial input
unit
1
• Continuous data
transmission/reception mode
tsDI(1)
SB0(P11),
SI0(P11)
Data hold time
tSCKH(2)
+(10/3)
tCYC
tCYC
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
thDI(1)
0.03
2.2 to 5.5
0.03
Input clock
Output delay
tdD0(1)
time
SO0(P10),
SB0(P11)
• Continuous data
(1/3)tCYC
transmission/reception mode
+0.05
• (Note 4-1-3)
tdD0(2)
μs
• Synchronous 8-bit mode
1tCYC
• (Note 4-1-3)
TdD0(3)
Output clock
Serial output
max
1
• See Fig. 6.
Serial clock
typ
2
pulse width
High level
min
(Note 4-1-3)
+0.05
2.2 to 5.5
(1/3)tCYC
+0.05
Note 4-1-1: These specifications are theoretical values. Add margin depending on its use.
Note 4-1-2: To use serial-clock-input in continuous trans/rec mode, a time from SI0RUN being set when serial clock is
"H" to the first negative edge of the serial clock must be longer than tSCKHA.
Note 4-1-3: Must be specified with respect to falling edge of SIOCLK. Must be specified as the time to the beginning of
output state change in open drain output mode. See Fig. 6.
No.8297-16/25
LC87F5JC8A
2. SIO1 Serial I/O Characteristics (Note 4-2-1)
Specification
Parameter
Symbol
Pin/Remarks
Conditions
Input clock
Frequency
tSCK(3)
Low level
tSCKL(3)
SCK1(P15)
See Fig. 6.
Frequency
SCK1(P15)
• CMOS output selected
tSCKL(4)
1
2
1/2
2.2 to 5.5
pulse width
High level
tSCK
tSCKH(4)
1/2
pulse width
Serial input
Data setup time
SB1(P14),
SI1(P14)
• Must be specified with respect
to rising edge of SIOCLK.
• See Fig. 6.
Data hold time
thDI(2)
0.03
2.2 to 5.5
0.03
Output delay time
Serial output
tsDI(2)
unit
1
• See Fig. 6.
Low level
max
tCYC
tSCKH(3)
tSCK(4)
typ
2
2.2 to 5.5
pulse width
High level
min
pulse width
Output clock
Serial clock
VDD[V]
tdD0(4)
SO1(P13),
SB1(P14)
μs
• Must be specified with respect
to falling edge of SIOCLK.
• Must be specified as the time
to the beginning of output
2.2 to 5.5
state change in open drain
(1/3)tCYC
+0.05
output mode.
• See Fig. 6.
Note 4-2-1: These specifications are theoretical values. Add margin depending on its use.
No.8297-17/25
LC87F5JC8A
Pulse Input Conditions / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
High/low level
tPIH(1)
INT0(P70),
• Interrupt source flag can be set.
pulse width
tPIL(1)
INT1(P71),
• Event inputs for timer 0 or 1
INT2(P72),
min
typ
max
unit
are enabled.
INT4(P20 to P23),
2.2 to 5.5
1
2.2 to 5.5
2
2.2 to 5.5
64
INT5(P24 to P27),
INT6(P20),
INT7(P24)
tPIH(2)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(2)
noise filter time
• Event inputs for timer 0 are enabled.
tCYC
constant is 1/1
tPIH(3)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(3)
noise filter time
• Event inputs for timer 0 are enabled.
constant is 1/32
tPIH(4)
INT3(P73) when
• Interrupt source flag can be set.
tPIL(4)
noise filter time
• Event inputs for timer 0 are enabled.
2.2 to 5.5
256
Resetting is enabled.
2.2 to 5.5
200
constant is 1/128
tPIL(5)
RES
μs
AD Converter Characteristics / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Resolution
N
AN0(P80) to
Absolute
ET
AN6(P86),
Conversion
TCAD
time
AN9(P71),
AD conversion time=32 × tCYC
AN10(XT1),
(when ADCR2=0) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
AD conversion time=64 × tCYC
(when ADCR2=1) (Note 6-2)
4.5 to 5.5
3.0 to 5.5
VAIN
3.0 to 5.5
voltage range
Analog port
IAINH
VAIN=VDD
3.0 to 5.5
input current
IAINL
VAIN=VSS
3.0 to 5.5
max
unit
8
bit
±1.5
3.0 to 5.5
AN11(XT2)
Analog input
typ
3.0 to 5.5
(Note 6-1)
AN8(P70),
accuracy
min
15.68
97.92
(tCYC=
(tCYC=
0.49μs)
3.06μs)
23.52
97.92
(tCYC=
(tCYC=
0.735μs)
3.06μs)
18.82
97.92
(tCYC=
(tCYC=
0.294μs)
1.53μs)
47.04
97.92
(tCYC=
(tCYC=
0.735μs)
1.53μs)
VSS
VDD
1
-1
LSB
μs
V
μA
Note 6-1: The quantization error (±1/2LSB) is excluded from the absolute accuracy value.
Note 6-2: The conversion time refers to the interval from the time the instruction for starting the converter is issued till
the time the complete digital value corresponding to the analog input value is loaded in the required register.
No.8297-18/25
LC87F5JC8A
Current Dissipation Characteristics / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Parameter
Normal mode
Symbol
IDDOP(1)
Specification
Pin/
Conditions
Remarks
VDD [V]
• FmCF=12MHz
consumption
VDD1
=VDD2
current
=VDD3
• FmX’tal=32.768kHz crystal
(Note 7-1)
min
typ
max
unit
ceramic oscillation mode
4.5 to 5.5
8.7
22
3.0 to 3.6
5
12.5
4.5 to 5.5
10
24.5
3.0 to 3.6
5.5
14
4.5 to 5.5
6.6
16.5
3.0 to 3.6
3.8
9.6
2.5 to 3.0
2.5
7.4
4.5 to 5.5
2.5
6.3
3.0 to 3.6
1.4
3.5
2.2 to 3.0
0.9
2.7
4.5 to 5.5
0.75
3.1
3.0 to 3.6
0.4
1.7
2.2 to 3.0
0.28
1.35
4.5 to 5.5
1.3
5.4
3.0 to 3.6
0.7
3.1
2.2 to 3.0
0.5
2.4
4.5 to 5.5
35
115
3.0 to 3.6
18
65
2.2 to 3.0
12
46
oscillation mode
• System clock set to 12MHz side
IDDOP(2)
• Internal RC oscillation stopped
• Frequency variable RC
oscillation stopped
• 1/1 frequency division ratio
IDDOP(3)
• CF1=24MHz external clock
• FmX’tal=32.768kHz crystal
oscillation mode
• System clock set to CF1 side
IDDOP(4)
• Internal RC oscillation stopped
• Frequency variable RC
oscillation stopped
• 1/2 frequency division ratio
IDDOP(5)
• FmCF=8MHz
ceramic oscillation mode
• FmX’tal=32.768kHz crystal
IDDOP(6)
oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
IDDOP(7)
• Frequency variable RC
oscillation stopped
• 1/1 frequency division ratio
IDDOP(8)
mA
• FmCF=4MHz
ceramic oscillation mode
• FmX’tal=32.768kHz crystal
IDDOP(9)
oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
IDDOP(10)
• Frequency variable RC
oscillation stopped
• 1/2 frequency division ratio
IDDOP(11)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal
oscillation mode
IDDOP(12)
• System clock set to internal RC
oscillation
IDDOP(13)
• Frequency variable RC oscillation
stopped
• 1/2 frequency division ratio
IDDOP(14)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal
IDDOP(15)
oscillation mode
• Internal RC oscillation stopped
• System clock set to 1MHz with
IDDOP(16)
frequency variable RC oscillation
• 1/2 frequency division ratio
IDDOP(17)
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal
oscillation mode
IDDOP(18)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
IDDOP(19)
μA
• Frequency variable RC oscillation
stopped
• 1/2 frequency division ratio
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
Continued on next page.
No.8297-19/25
LC87F5JC8A
Continued from preceding page.
Parameter
Symbol
IDDHALT(1)
Conditions
Remarks
consumption
VDD1
=VDD2
current
=VDD3
HALT mode
Specification
Pin/
VDD [V]
min
typ
max
unit
• HALT mode
• FmCF=12MHz
4.5 to 5.5
3.6
8.2
3.0 to 3.6
2
4.6
4.5 to 5.5
4.7
10.5
3.0 to 3.6
2.5
5.8
4.5 to 5.5
2.6
5.9
3.0 to 3.6
1.4
3.3
2.5 to 3.0
1
2.5
4.5 to 5.5
1.15
2.65
3.0 to 3.6
0.6
1.5
2.2 to 3.0
0.4
1.1
4.5 to 5.5
0.37
1.3
3.0 to 3.6
0.2
0.75
2.2 to 3.0
0.13
0.54
4.5 to 5.5
1
3.5
3.0 to 3.6
0.55
2
2.2 to 3.0
0.37
1.5
4.5 to 5.5
18.5
68
3.0 to 3.6
10
38
2.2 to 3.0
6.5
26
• HOLD mode
4.5 to 5.5
0.05
20
• CF1=VDD or open (External clock mode)
3.0 to 3.6
0.03
12
2.2 to 3.0
0.02
8
ceramic oscillation mode
• FmX’tal=32.768kHz crystal oscillation mode
(Note 7-1)
• System clock set to 12MHz side
IDDHALT(2)
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio
IDDHALT(3)
• HALT mode
• CF1=24MHz external clock
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to CF1 side
IDDHALT(4)
• Internal RC oscillation stopped
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio
IDDHALT(5)
• HALT mode
• FmCF=8MHz
ceramic oscillation mode
IDDHALT(6)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 8MHz side
• Internal RC oscillation stopped
IDDHALT(7)
• Frequency variable RC oscillation stopped
• 1/1 frequency division ratio
IDDHALT(8)
mA
• HALT mode
• FmCF=4MHz
ceramic oscillation mode
IDDHALT(9)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to 4MHz side
• Internal RC oscillation stopped
IDDHALT(10)
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio
IDDHALT(11)
• HALT mode
• FmCF=0Hz (oscillation stopped)
IDDHALT(12)
• FmX’tal=32.768kHz crystal oscillation mode
• System clock set to internal RC oscillation
IDDHALT(13)
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio
IDDHALT(14)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(15)
• Internal RC oscillation stopped
• System clock set to 1MHz with
IDDHALT(16)
frequency variable RC oscillation
• 1/2 frequency division ratio
IDDHALT(17)
• HALT mode
• FmCF=0Hz (oscillation stopped)
• FmX’tal=32.768kHz crystal oscillation mode
IDDHALT(18)
• System clock set to 32.768kHz side
• Internal RC oscillation stopped
IDDHALT(19)
• Frequency variable RC oscillation stopped
• 1/2 frequency division ratio
HOLD mode
IDDHOLD(1)
consumption
IDDHOLD(2)
current
Timer HOLD
mode
IDDHOLD(3)
IDDHOLD(4)
• Timer HOLD mode
4.5 to 5.5
16
58
IDDHOLD(5)
• CF1=VDD or open (External clock mode)
3.0 to 3.6
8.5
32
2.2 to 3.0
5
20
• FmX’tal=32.768kHz crystal oscillation mode
consumption
current
VDD1
IDDHOLD(6)
μA
Note 7-1: The consumption current value includes none of the currents that flow into the output Tr and internal pull-up
resistors.
No.8297-20/25
LC87F5JC8A
F-ROM Programming Characteristics / Ta = +10°C to +55°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Pin/Remarks
Conditions
VDD [V]
Onboard
IDDFW(1)
VDD1
programming
min
typ
max
unit
• 128 byte programming
• Erasing current included
3.0 to 5.5
25
40
mA
3.0 to 5.5
22.5
45
ms
current
Programming
tFW(1)
• 128 byte programming
time
• Erasing current included
• Time for setting up 128 byte data is
excluded.
UART (Full Duplex) Operating Conditions / Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = 0V
Specification
Parameter
Symbol
Transfer rate
UBR
Pin/Remarks
Conditions
VDD [V]
2.2 to 5.5
UTX(P20),
min
typ
16/3
max
unit
8192/3
tCYC
URX(P21)
Data length:
Stop bits:
Parity bits:
7/8/9 bits (LSB first)
1-bit
None
*Example of Continuous 8-bit Data Transmission Mode Processing (First Transmit Data=55H)
Stop bit
Start bit
Start of
transmission
Transmit data (LSB first)
End of
transmission
UBR
*Example of Continuous 8-bit Data Reception Mode Processing (First Receive Data=55H)
Stop bit
Start bit
Start of
reception
Receive data (LSB first)
End of
reception
UBR
No.8297-21/25
LC87F5JC8A
Characteristics of a Sample Main System Clock Oscillation Circuit
Given below are the characteristics of a sample main system clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 1 Characteristics of a Sample Main System Clock Oscillator Circuit with a Ceramic Oscillator
Circuit Constant
Nominal
Vendor
Frequency
Name
12MHz
8MHz
4MHz
MURATA
MURATA
MURATA
Oscillator Name
CSTCE12M0G52-R0
CSTCE8M00G52-R0
Oscillation
Voltage
Stabilization Time
C1
C2
Rf
Rd1
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[ms]
[ms]
(10)
(10)
1M
680
3.0 to 5.5
0.1
0.5
(10)
CSTCR4M00G53-R0
Operating
(10)
(15)
1M
(15)
680
1M
2.5 to 5.5
2.2k
0.1
2.2 to 5.5
0.5
0.2
0.6
Remarks
Internal
C1, C2
Internal
C1, C2
Internal
C1, C2
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after VDD
goes above the operating voltage lower limit (see Figure 4).
Characteristics of a Sample Subsystem Clock Oscillator Circuit
Given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a Our
designated oscillation characteristics evaluation board and external components with circuit constant values with which
the oscillator vendor confirmed normal and stable oscillation.
Table 2 Characteristics of a Sample Subsystem Clock Oscillator Circuit with a Crystal Oscillator
Nominal
Vendor
Frequency
Name
32.768kHz
SEIKO
EPSON
Circuit Constant
Oscillator Name
Operating
Oscillation
Voltage
Stabilization Time
C3
C4
Rf
Rd2
Range
typ
max
[pF]
[pF]
[Ω]
[Ω]
[V]
[s]
[s]
18
18
Open
560k
2.2 to 5.5
1.4
3.0
Remarks
Applicable
MC-306
CL value =
12.5pF
The oscillation stabilization time refers to the time interval that is required for the oscillation to get stabilized after the
instruction for starting the subclock oscillation circuit is executed and to the time interval that is required for the
oscillation to get stabilized after the HOLD mode is reset (see Figure 4).
Note : The components that are involved in oscillation should be placed as close to the IC and to one another as possible
because they are vulnerable to the influences of the circuit pattern.
CF1
CF2
XT1
Rf
XT2
Rf
Rd1
C1
C2
Rd2
C3
C4
X’tal
CF
Figure 1 CF Oscillator Circuit
Figure 2 XT Oscillator Circuit
0.5VDD
Figure 3 AC Timing Measurement Point
No.8297-22/25
LC87F5JC8A
VDD
Operating VDD
lower limit
0V
Power supply
Reset time
RES
Internal RC
oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
Operating mode
Reset
Unpredictable
Instruction execution
Reset Time and Oscillation Stabilizing Time
HOLD reset signal
HOLD reset signal
absent
HOLD reset signal valid
Internal RC
oscillation
tmsCF
CF1, CF2
tmsXtal
XT1, XT2
State
HOLD
HALT
HOLD Reset Signal and Oscillation Stabilization Time
Figure 4 Oscillation Stabilization Times
No.8297-23/25
LC87F5JC8A
VDD
RRES
Note :
Determine the value of CRES and RRES so that the
reset signal is present for a period of 200μs after the
supply voltage goes beyond the lower limit of the IC’s
operating voltage.
RES
CRES
Figure 5 Reset Circuit
SIOCLK:
DATAIN:
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DATAOUT:
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DI7
DI8
DO7
DO8
Data RAM
transfer period
(SIO0 only)
tSCK
tSCKH
tSCKL
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Data RAM
transfer period
(SIO0 only)
tSCKL
tSCKHA
SIOCLK:
tsDI
thDI
DATAIN:
tdDO
DATAOUT:
Figure 6 Serial I/O Output Waveforms
tPIL
tPIH
Figure 7 Pulse Input Timing Signal Waveform
No.8297-24/25
LC87F5JC8A
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