EN4828 D

Ordering number : EN4828A
LC75852E
LC75852W
http://onsemi.com
CMOS LSI
Asynchronous Silicon Gate
1/2 Duty LCD Driver
with On-Chip Key Input Function
Overview
The LC75852E and LC75852W are 1/2 duty dynamic LCD display drivers. In addition to being able to directly
drive LCD panels with up to 90 segments, they can also control up to four general-purpose output ports. These
products also include a key scan circuit which allows them to accept input from keypads with up to 30 keys. This
allows end product front panel wiring to be simplified.
Features
 Up to 30 key inputs (Key scan is only performed when a key is pressed.)
 1/2 duty – 1/2 bias (up to 90 segments)
 Sleep mode and the all segments off function can be controlled from serial data.
 Segment output port/general-purpose output port usage can be controlled from serial data.
 Serial data I/O supports CCB format communication with the system controller.
 High generality since display data is displayed directly without decoder intervention
 Reset pin that can establish the initial state.
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter
Symbol
Maximum supply voltage
Input voltage
Output voltage
Conditions
Ratings
Unit
0.3 to +7.0
V
OSC, CE, CL, DI, RES, KI1 to KI5
0.3 to VDD+0.3
V
OSC, DO, S1 to S45, COM1, COM2, KS1 to KS6, P1 to P4
0.3 to VDD+0.3
V
100
A
VDD max
VIN
VDD
VOUT
IOUT1
S1 to S45
IOUT2
COM1, COM2, KS1 to KS6
1
IOUT3
P1 to P4
5
Allowable power dissipation
Pd max
Ta = 85C
Operating temperature
Topr
40 to +85
C
Storage temperature
Tstg
55 to +125
C
Output current
200
mA
mW
Package Dimensions
17.2
14.0
12.0
64
48
0.5
10.0
[ LC75852W ]
SQFP64(10X10)
33
49
32
10.0
17.2
32
49
14.0
[ LC75852E ]
QIP64E(14X14)
33
64
17
17
1
1
16
0.8
0.35
16
0.5
0.15
12.0
48
0.8
unit : mm (typ)
0.18
0.15
(1.25)
0.1
0.1
3.0max
1.7max
(2.7)
(1.5)
(1.0)

CCB is ON Semiconductor® ’s original format. All addresses are managed
by ON Semiconductor® for this format.

CCB is a registered trademark of Semiconductor Components Industries, LLC.
Semiconductor Components Industries, LLC, 2013
July, 2013
63096HA (OT)/N1594TH (OT) B8-1326, 1328 No.4828-1/16
LC75852E, 75852W
Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
Symbol
Conditions
VDD
VDD
VIH1
VIH2
VIL
min
typ
max
Unit
4.5
6.0
V
CE, CL, DI, RES
0.8 VDD
VDD
V
KI1 to KI5
0.6 VDD
VDD
V
0
0.2 VDD
V
CE, CL, DI, RES, KI1 to KI5
Recommended external
resistance
ROSC
OSC
62
kΩ
Recommended external
capacitance
COSC
OSC
680
pF
Guaranteed oscillator range
fOSC
OSC
25
50
100
kHz
Data setup time
tds
CL, DI: Figure 1
160
ns
Data hold time
tdh
CL, DI: Figure 1
160
ns
CE wait time
tcp
CE, CL: Figure 1
160
ns
CE setup time
tcs
CE, CL: Figure 1
160
ns
CE hold time
tch
CE, CL: Figure 1
160
ns
High-level clock pulse width
tøH
CL: Figure 1
160
ns
Low-level clock pulse width
tøL
CL: Figure 1
160
Rise time
tr
CE, CL, DI: Figure 1
160
Fall time
tf
CE, CL, DI: Figure 1
160
DO output delay time
tdc
DO, RPU = 4.7 kΩ, CL = 10 pF*: Figure 1
1.5
DO rise time
tdr
DO, RPU = 4.7 kΩ, CL = 10 pF*: Figure 1
1.5
RES switching time
t2
Figure 2
ns
ns
ns
10
µs
µs
µs
Note: * Since DO is an open-drain output, these values differ depending on the pull-up resistor RPU and the load capacitance CL.
Electrical Characteristics in the Allowable Operating Ranges
Parameter
Symbol
Conditions
Hysteresis
VH
CE, CL, DI, RES, KI1 to KI5
Input high-level current
IIH
CE, CL, DI, RES: VI = 6.0 V
Input low-level current
IIL
CE, CL, DI, RES: VI = 0 V
Input floating voltage
VIF
KI1 to KI5
Pull-down resistance
RPD
KI1 to KI5: VDD = 5.0 V
Output off leakage current
Output high-level voltage
Output low-level voltage
Output middle-level voltage
Current drain
min
typ
max
Unit
0.1 VDD
V
5.0
–5.0
µA
0.05 VDD
50
µA
100
V
250
kΩ
6.0
µA
IOFFH
DO: VO = 6.0 V
VOH1
KS1 to KS6: IO = –1 mA
VDD – 1.0
V
VOH2
P1 to P4: IO = –1 mA
VDD – 1.0
V
VOH3
S1 to S45: IO = –10 µA
VDD – 1.0
V
VOH4
COM1, COM2: IO = –100 µA
VDD – 0.6
VOL1
KS1 to KS6: IO = 50 µA
VOL2
V
3.0
V
P1 to P4: IO = 1 mA
1.0
V
VOL3
S1 to S45: IO = 10 µA
1.0
V
VOL4
COM1, COM2: IO = 100 µA
0.6
V
VOL5
DO: IO = 1 mA
0.5
V
VMID1
COM1, COM2: VDD = 6.0 V, IO = ±100 µA
2.4
3.0
3.6
V
VMID2
COM1, COM2: VDD = 4.5 V, IO = ±100 µA
1.65
2.25
2.85
V
5
µA
1.4
2.5
mA
IDD1
Sleep mode, Ta = 25°C
IDD2
VDD = 6.0 V, output open, Ta = 25°C, fOSC = 50 kHz
0.4
1.0
0.1
No. 4828-2/16
LC75852E, 75852W
1. When stopped with CL at the low level
2. When stopped with CL at the high level
Figure 1
Pin Assignment
No. 4828-3/16
LC75852E, 75852W
Block Diagram
Pin Functions
Pin
S1/P1 to S4/P4
S5 to S43
COM1
COM2
Active
I/O
Handling when
unused
Segment outputs: Used to output the display data that is transmitted over the
serial data input. Pins S1/P1 to S4/P4 can be used as general-purpose outputs
according to control data specification.
—
O
Open
Common driver outputs. The frame frequency fO is (fOSC/512) Hz.
—
O
Open
Pin No.
1 to 4
5 to 43
44
45
Function
KS1/S44,
KS2/S45,
KS3 to KS6
46
47
48 to 51
Key scan outputs. When a key matrix is formed, normally a diode will be
attached to the key scan timing line to prevent shorts. However, since the
output transistor impedance is an unbalanced CMOS output, it will not be
damaged if shorted. Pins KS1/S44 and KS2/S45 can be used as segment
outputs according to control data specification.
—
O
Open
KI1 to KI5
52 to 56
Key scan inputs: Pins with a built-in pull-down resistor.
H
I
GND
Oscillator connection: Oscillator circuit can be formed by connecting the pin to
a resistor and a capacitor.
—
I/O
VDD
H
I
—
I
—
O
Open
OSC
57
CE
62
Serial data interface: Connected
to the controller. Since DO is an
open-drain output, it requires a
pull-up resistor.
CE: Chip enable
CL: Synchronization clock
DI: Transfer data
DO: Output data
GND
CL
63
DI
64
DO
61
RES
59
Reset input that re-initializes the LSI internal states. During a reset, the display
segments are turned off forcibly regardless of the internal display data. All
internal key data is reset to low and the key scan operation is disabled.
However, serial data can be input during a reset.
L
I
GND
VDD
60
Power supply connection. A supply voltage of between 4.5 and 6.0 V must be
provided.
—
—
—
VSS
58
Power supply ground connection. Must be connected to GND.
—
—
—
I
No. 4828-4/16
LC75852E, 75852W
Serial Data Input
1. When stopped with CL at the low level
2. When stopped with CL at the high level
CCB address......................[42H]
D1 to D90 ...........................Display data
S0, S1 ................................Sleep control data
K0, K1 ................................Key scan output/segment output selection data
P0, P1 ................................Segment output port/general-purpose output port selection data
SC ......................................Segment on/off control data
No. 4828-5/16
LC75852E, 75852W
Control Data Functions
1. S0, S1 .................Sleep control data
This control data switches the LSI between normal mode and sleep mode. It also sets the key scan output standby
states for pins KS1 to KS6.
Control data
Mode
Segment outputs
Common outputs
Oscillator
S0
S1
0
0
Normal
Oscillator
0
1
Sleep
1
0
1
1
Key scan standby mode output pin states
KS1
KS2
KS3
KS4
KS5
KS6
Operation
H
H
H
H
H
H
Stopped
L
L
L
L
L
L
H
Sleep
Stopped
L
L
L
L
L
H
H
Sleep
Stopped
L
H
H
H
H
H
H
Note: The KS1/S44 and KS2/S45 output pins are set to the key scan output state.
2. K0, K1................Key scan output/segment output selection data
This control data switches the KS1/S44 and KS2/S45 output pins between the key scan output and segment output
functions.
Control data
Output pin states
KS2/S45
Maximum number
of key inputs
KS1
KS2
30
S44
KS2
25
S44
S45
20
K0
K1
KS1/S44
0
0
0
1
1
X
X: don’t care
3. P0, P1 .................Segment output port/general-purpose output port selection data
This control data switches the S1/P1 to S4/P4 output pins between the segment output port and the general-purpose
output port functions.
Control data
Output pin states
P0
P1
S1/P1
S2/P2
S3/P3
S4/P4
0
0
S1
S2
S3
S4
0
1
P1
P2
S3
S4
1
0
P1
P2
P3
S4
1
1
P1
P2
P3
P4
The table below lists the correspondence between the display data and the output pins when the general-purpose
output port function is selected.
Output
pin
Corresponding
display data
S1/P1
D1
S2/P2
D3
S3/P3
D5
S4/P4
D7
For example, if the output pin S4/P4 is set for use as a general-purpose output port, the output pin S4/P4 will output a
high level when the display data D7 is 1.
4. SC.......................Segment on/off control data
This control data controls the segment on/off states.
SC
Display state
0
On
1
Off
No. 4828-6/16
LC75852E, 75852W
Display Data and Output Pin Correspondences
Output pin
COM1
COM2
S1/P1
D1
D2
S2/P2
D3
D4
S3/P3
D5
D6
S4/P4
D7
D8
S5
D9
D10
S6
D11
D12
S7
D13
D14
S8
D15
D16
S9
D17
D18
S10
D19
D20
S11
D21
D22
S12
D23
D24
S13
D25
D26
S14
D27
D28
S15
D29
D30
S16
D31
D32
S17
D33
D34
S18
D35
D36
S19
D37
D38
S20
D39
D40
S21
D41
D42
S22
D43
D44
S23
D45
D46
S24
D47
D48
S25
D49
D50
S26
D51
D52
S27
D53
D54
S28
D55
D56
S29
D57
D58
S30
D59
D60
S31
D61
D62
S32
D63
D64
S33
D65
D66
S34
D67
D68
S35
D69
D70
S36
D71
D72
S37
D73
D74
S38
D75
D76
S39
D77
D78
S40
D79
D80
S41
D81
D82
S42
D83
D84
S43
D85
D86
KS1/S44
D87
D88
KS2/S45
D89
D90
For example, the output states of output pin S11 are listed in the table below.
Display data
Output pin state
D21
D22
0
0
Segment off for both COM1 and COM2
S11
0
1
Segment on for COM2
1
0
Segment on for COM1
1
1
Segments on for both COM1 and COM2
No. 4828-7/16
LC75852E, 75852W
Serial Data Output
1. When stopped with CL at the low level
2. When stopped with CL at the high level
CCB address......................[43H]
KD1 to KD30 ......................Key data
SA ......................................Sleep acknowledge data
Note: If key data is read when DO is high, the key data (KD1 to KD30) and sleep acknowledge data (SA) will be
invalid.
Output Data
1. KD1 to KD30.....Key data
When a key matrix with up to 30 keys is formed using the KS1 to KS6 output pins and the KI1 to KI5 input pins, the
key data corresponding to a given key will be 1 if that key is pressed. The table below lists that correspondence.
Item
KI1
KI2
KI3
KI4
KI5
KS1/S44
KD1
KD2
KD3
KD4
KD5
KS2/S45
KD6
KD7
KD8
KD9
KD10
KS3
KD11
KD12
KD13
KD14
KD15
KS4
KD16
KD17
KD18
KD19
KD20
KS5
KD21
KD22
KD23
KD24
KD25
KS6
KD26
KD27
KD28
KD29
KD30
When the output pins KS1/S44 and KS2/S45 are selected for segment output by the control data K0 and K1, the key
data items KD1 to KD10 will be 0.
2. SA ......................Sleep acknowledge data
This output data is set according to the state when the key was pressed. If the LSI was in sleep mode, SA will be 1,
and if the LSI was in normal mode, SA will be 0.
Sleep Mode
When S0 or S1 in the control data is set to 1, the oscillator at the OSC pin will stop (it will restart if a key is pressed) and
the segment and common outputs will all go to the low level. This reduces the LSI power dissipation. However, the
S1/P1 to S4/P4 output pins can be used as general-purpose output ports even in sleep mode if selected for such use by
the P0 and P1 control data bits.
No. 4828-8/16
LC75852E, 75852W
Key Scan Operation
1. Key Scan Timing
The key scan period is 375T [s]. The key scan is performed twice to reliably determine the key on/off states, and the
LSI detects key data agreement. When the key data agrees, the LSI determines that a key has been pressed, and outputs
a key read request (by setting DO low) 800T [s] after the key scan started. If a key is pressed again without the key data
agreeing, a key scan is performed once more. Thus key on/off operations shorter than 800T [s] cannot be detected.
*1 The high or low states of these signals in sleep mode are determined by the S0 and S1 control data bits.
2. Key Scan during Normal Mode
• The pins KS1 to KS6 are set high.
• A key scan starts if any key is pressed, and the scan continues until all keys have been released. Multiple key
presses can be recognized by determining if multiple key data bits have been set.
• When a key has been pressed for 800T [s] (where T = 1/fOSC) or longer, a key data read request (DO is set to low)
is output to the controller. The controller acknowledges this request and reads the key data. However, DO will go
high when CE is high during a serial data transfer.
• After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high)
and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1 and 10 kΩ
is required.
No. 4828-9/16
LC75852E, 75852W
3. Key Scan during Sleep Mode
• The pins KS1 to KS6 are set high or low according to the S0 and S1 control data bits.
(See the description of the control data function for details.)
• If a key for a line corresponding to one of the pins KS1 to KS6 which is high is pressed, the oscillator at the OSC
pin starts and a key scan is performed. The key scan continues until all keys have been released. Multiple key
presses can be recognized by determining if multiple key data bits have been set.
• When a key has been pressed for 800T [s] (where T = 1/fOSC) or longer, a key data read request (DO is set to low)
is output to the controller. The controller acknowledges this request and reads the key data. However, DO will go
high when CE is high during a serial data transfer.
• After the controller has finished reading the key data, the LSI clears the key data read request (by setting DO high)
and performs another key scan. Note that since DO is an open drain output, a pull-up resistor of between 1 and 10 kΩ
is required.
• Key scan example in sleep mode
Example: Here S0 = 0 and S1 = 1 (This is a sleep in which only KS6 is high.)
Multiple Key Presses
Without the insertion of additional diodes, the LC75852 supports key scan for double key presses in general, triple key
presses of keys on the lines for input pins KI1 to KI5, and multiple key presses of keys on the lines for the output pins
KS1 to KS6. However, if multiple key presses in excess of these limits occur, the LC75852 may recognize keys that
were not pressed as having been pressed. Therefore, series diodes must be connected to each key.
No. 4828-10/16
LC75852E, 75852W
1/2 Duty - 1/2 Bias LCD Drive Scheme
COM1
COM2
S1 to S45 outputs for segments on
COM1 side being lit
S1 to S45 outputs for segments on
COM2 side being lit
S1 to S45 outputs for segments on
COM1,COM2 sides being lit
S1 to S45 outputs for segments on
COM1,COM2 sides not being lit
RES and the Display Controller
Since the LSI internal data (D1 to D90 and the control data) is undefined when power is first applied, the output pins
S1/P1 to S4/P4, S5 to S43, COM1, COM2, KS1/S44 and KS2/S45 should be held low by setting the RES pin low at the
same time as power is applied. Then, meaningless displays at power on can be prevented by transferring data from the
controller and setting RES high when that transfer has completed.
Figure 2
No. 4828-11/16
LC75852E, 75852W
Internal Block States during the Reset Period (when RES is low)
1. CLOCK GENERATOR
Reset is applied and the basic clock stops. However, the state of the OSC pin (the normal or sleep state) is
determined after the control data S0 and S1 has been sent.
2. COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the LATCH.
3. KEY SCAN
Reset is applied and at the same time as the internal states are set to their initial states, the key scan operation is
disabled.
4. KEY BUFFER
Reset is applied and all the key data is set to the low level.
5. CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
To allow serial data transfers, reset is not applied to these circuits.
Output Pin States during the Reset Period (when RES is low)
Output pin
State during reset
S1/P1 to S4/P4
L*3
S5 to S43
L
COM1, COM2
L
KS1/S44, KS2/S45
L*3
KS3 to KS5
X*4
KS6
H
DO
H*5
X: don’t care
Note: 3. These output pins are forcibly set to the segment output mode and held low.
4. Immediately following power on, these output pins are undefined until the control data S0 and S1 has been sent.
5. Since this output pin is an open-drain output, a pull-up resistor of between 1 and 10 kΩ is required. This pin is held high during the reset period
even if key data is read.
No. 4828-12/16
LC75852E, 75852W
Sample Application Circuit
Note: * Since DO is an open-drain output, a pull-up resistor is required. Select a value (between 1 and 10 kΩ) that is appropriate for the capacitance of the
external wiring so that the waveforms are not distorted.
Notes on Controller Display Data Transfer
The LC75852 transfers the display data (D1 to D90) in two operations. To assure visual display quality, all the display
data should be sent within a 30 ms or shorter period.
No. 4828-13/16
LC75852E, 75852W
Notes on Controller Key Data Read Techniques
1. Controller key data reading under timer control
• Flowchart
• Timing Chart
t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees
t4 ..................Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again
t5 ..................Key address (43H) transfer time
t6 ..................Key data read time
1
T=
fOSC
• Description
When determining key on/off and reading key data, the controller must confirm the state of DO output when CE is
low for each period t7. When DO is low, the controller recognizes that a key has been pressed and reads the key
data.
During this operation t7 must obey the following condition:
t7 > t5 + t6 + t4
If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) will be
invalid.
No. 4828-14/16
LC75852E, 75852W
2. Controller key data reading under interrupt control
• Flowchart
• Timing Chart
t3 ..................Key scan execution time (800T [s]) when the key scan data for two key scans agrees
t4 ..................Key scan execution time (1600T [s]) when the key scan data for two key scans does not agree and a key scan is executed again
t5 ..................Key address (43H) transfer time
t6 ..................Key data read time
1
T=
fOSC
No. 4828-15/16
LC75852E, 75852W
• Description
When determining key on/off and reading key data, the controller must confirm the state of DO output when CE is
low. When DO is low, the controller recognizes that a key has been pressed and reads the key data. After the time t8,
the next key on/off determination and reading key data must be confirmed by the state of DO output when CE is low.
During this operation t8 must obey the following condition :
t8 > t4
If key data is read when DO is high, the key data (KD1 to KD30) and the sleep acknowledge data (SA) will be invalid.
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PS No.4828-16/16