LM339S D

LM339S, LM2901S
Single Supply Quad
Comparators
These comparators are designed for use in level detection, low−level
sensing and memory applications in consumer and industrial
electronic applications.
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Features
•
•
•
•
•
•
•
•
Single or Split Supply Operation
Low Input Bias Current: 25 nA (Typ)
Low Input Offset Current: ±5.0 nA (Typ)
Low Input Offset Voltage
Input Common Mode Voltage Range to GND
Low Output Saturation Voltage: 130 mV (Typ) @ 4.0 mA
TTL and CMOS Compatible
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
MARKING DIAGRAMS
14
LM339SN
AWLYYWWG
1
14
1
PDIP−14
N SUFFIX
CASE 646
LM2901SN
AWLYYWWG
1
LMxxxx = Specific Device Code
A
= Assembly Location
WL
= Wafer Lot
Y, YY
= Year
WW
= Work Week
G
= Pb−Free Package
PIN CONNECTIONS
Output 2
1
14
Output 3
Output 1
2
13
Output 4
VCC
3
12
GND
- Input 1
4
11
+ Input 4
10
- Input 4
9
+ Input 3
8
- Input 3
+ Input 1
5
- Input 2
6
+ Input 2
7
*
1
)
4
*2
)
3
(Top View)
)
*
)
*
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2014
October, 2014 − Rev. 0
1
Publication Order Number:
LM339S/D
LM339S, LM2901S
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply Voltage
Rating
VCC
+36 or ±18
Vdc
Input Differential Voltage Range
VIDR
36
Vdc
VICMR
−0.3 to VCC
Vdc
ISC
Continuous
Input Common Mode Voltage Range
Output Short Circuit to Ground (Note 1)
Power Dissipation @ TA = 25°C
PD
Plastic Package
Derate above 25°C
1/RqJA
1.0
8.0
W
mW/°C
TJ
150
°C
Junction Temperature
Operating Ambient Temperature Range
°C
TA
LM2901S
LM339S
Storage Temperature Range
−40 to +105
0 to +70
Tstg
−65 to +150
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The maximum output current may be as high as 20 mA, independent of the magnitude of VCC. Output short circuits to VCC can cause excessive
heating and eventual destruction.
VCC
- Input
+ Input
GND
NOTE: Diagram shown is for 1 comparator.
Figure 1. Circuit Schematic
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2
Output
LM339S, LM2901S
ELECTRICAL CHARACTERISTICS (VCC = +5.0 Vdc, TA = +25°C, unless otherwise noted)
LM339S
LM2901S
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset Voltage (Note 2)
VIO
−
±2.0
±5.0
−
±2.0
±7.0
mVdc
Input Bias Current (Notes 2, 3)
(Output in Analog Range)
IIB
−
25
250
−
25
250
nA
Input Offset Current (Note 2)
IIO
−
±5.0
±50
−
±5.0
±50
nA
VICMR
0
−
VCC
−1.5
0
−
VCC
−1.5
V
Characteristic
Input Common Mode Voltage Range
ICC
Supply Current
mA
RL = ∞ (For All Comparators)
−
0.8
2.0
−
0.8
2.0
RL = ∞, VCC = 30 Vdc
−
1.0
2.5
−
1.0
2.5
AVOL
50
200
−
25
100
−
V/mV
Large Signal Response Time
VI = TTL Logic Swing, Vref = 1.4 Vdc, VRL = 5.0 Vdc,
RL = 5.1 kW
−
−
200
−
−
200
−
ns
Response Time (Note 4)
VRL = 5.0 Vdc, RL = 5.1 kW
−
−
1.0
−
−
1.0
−
ms
Output Sink Current
VI (−) ≥ +1.0 Vdc, VI(+) = 0, VO ≤ 1.5 Vdc
ISink
6.0
16
−
6.0
16
−
mA
Saturation Voltage
VI(−) ≥ +1.0 Vdc, VI(+) = 0, Isink ≤ 4.0 mA
Vsat
−
130
400
−
130
400
mV
Output Leakage Current
VI(+) ≥ +1.0 Vdc, VI(−) = 0, VO = +5.0 Vdc
IOL
−
0.1
−
−
0.1
−
nA
Voltage Gain
RL ≥ 15 kW, VCC = 15 Vdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. At the output switch point, VO ] 1.4 Vdc, RS ≤ 100 W 5.0 Vdc ≤ VCC ≤ 30 Vdc, with the inputs over the full common mode range
(0 Vdc to VCC −1.5 Vdc).
3. The bias current flows out of the inputs due to the PNP input stage. This current is virtually constant, independent of the output state.
4. The response time specified is for a 100 mV input step with 5.0 mV overdrive. For larger signals, 300 ns is typical.
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3
LM339S, LM2901S
PERFORMANCE CHARACTERISTICS (VCC = +5.0 Vdc, TA = Tlow to Thigh (Note 5))
LM339S
LM2901S
Symbol
Min
Typ
Max
Min
Typ
Max
Unit
Input Offset Voltage (Note 6)
VIO
−
−
±9.0
−
−
±15
mVdc
Input Bias Current (Notes 6, 7)
(Output in Analog Range)
IIB
−
−
400
−
−
500
nA
Input Offset Current (Note 6)
IIO
−
−
±150
−
−
±200
nA
VICMR
0
−
VCC −2.0
0
−
VCC −2.0
V
Saturation Voltage
VI(−) ≥ +1.0 Vdc, VI(+) = 0, Isink ≤ 4.0 mA
Vsat
−
−
700
−
−
700
mV
Output Leakage Current
VI(+) ≥ +1.0 Vdc, VI(−) = 0, VO = 30 Vdc
IOL
−
−
1.0
−
−
1.0
mA
Differential Input Voltage
All VI ≥ 0 Vdc
VID
−
−
VCC
−
−
VCC
Vdc
Characteristic
Input Common Mode Voltage Range
5. (LM339S) Tlow = 0°C, Thigh = +70°C
(LM2901S) Tlow = −40°C, Thigh = +105°C
6. At the output switch point, VO ] 1.4 Vdc, RS ≤ 100 W 5.0 Vdc ≤ VCC ≤ 30 Vdc, with the inputs over the full common mode range
(0 Vdc to VCC −1.5 Vdc).
7. The bias current flows out of the inputs due to the PNP input stage. This current is virtually constant, independent of the output state.
+ VCC
+ VCC
R3
10 k
Vin
Rref
+ VCC
Rref
10 k
-
Vref
VO
+
10 k
R1
R2
Vref
10k
R1
Vin
1.0 M
Vref [
R2
VO
+
10 k
VCC R1
R3
Rref + R1
1.0 M
R3 ] R1 / / Rref / / R2
R1 / / Rref
VH =
R1/ / Rref + R2
Amount of Hysteresis VH
R2
VH =
[(V
-V
]
R2 + R3 O(max) O(min)
Figure 2. Inverting Comparator
with Hysteresis
Figure 3. Noninverting Comparator
with Hysteresis
VCC
Vin
Vref
VCC ≥ 4.0 V
+
-
VCC
RS = Source Resistance
R1 ] RS
RL
kW
1/4 MC14001
+15
100
1/4 MC7400
+5.0
10
TTL
R1
VO
+
R2
R3
330 k
330 k
R4
VCC
(V)
CMOS
-
+
C
R1
Device
10 k
100 k
RL
Logic
VCC R1
Rref + R1
R2 [ R1 / / Rref
[VO(max) - VO(min)]
R2 ơ Rref / / R1
RS
Vref =
330 k
VCC
T1
T2
T1 = T2 = 0.69 RC
7.2
f[
C(mF)
R2 = R3 = R4
R1 [ R2 // R3 // R4
Figure 4. Driving Logic
Figure 5. Squarewave Oscillator
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4
LM339S, LM2901S
APPLICATIONS INFORMATION
addition of positive feedback (< 10 mV) is also
recommended. It is good design practice to ground all
unused input pins.
Differential input voltages may be larger than supply
voltages without damaging the comparator’s inputs.
Voltages more negative than −300 mV should not be used.
These quad comparators feature high gain, wide
bandwidth characteristics. This gives the device oscillation
tendencies if the outputs are capacitively coupled to the
inputs via stray capacitance. This oscillation manifests itself
during output transitions (VOL to VOH). To alleviate this
situation input resistors < 10 kW should be used. The
+15 V
R1
8.2 k
R4
220 k
D1
6.8 k
R2
Vin
R5
220 k
10 k
*
)
Vin(min) ≈ 0.4 V peak for 1% phase distortion (Dq).
VO
Vin(min)
Vin
VCC
15 k
R3
q
10 M
*
Vin
D1 prevents input from going negative by more than 0.6 V.
R1 + R2 = R3
R5
for small error in zero crossing
R3 ≤
10
+
VEE
10 k
VO
VCC
q
VO
VEE
Figure 6. Zero Crossing Detector
(Single Supply)
Dq
Figure 7. Zero Crossing Detector
(Split Supplies)
ORDERING INFORMATION
Package
Shipping†
LM339SNG
PDIP−14
(Pb−Free)
25 Units / Rail
LM2901SNG
PDIP−14
(Pb−Free)
25 Units / Rail
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
LM339S, LM2901S
PACKAGE DIMENSIONS
PDIP−14
CASE 646−06
ISSUE R
D
14
A
8
E
H
E1
1
NOTE 8
7
b2
c
B
TOP VIEW
END VIEW
WITH LEADS CONSTRAINED
NOTE 5
A2
A
NOTE 3
L
SEATING
PLANE
A1
C
M
D1
eB
END VIEW
e
14X b
SIDE VIEW
0.010
M
C A
M
B
M
NOTE 6
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCHES.
3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3.
4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH
OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE
NOT TO EXCEED 0.10 INCH.
5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM
PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR
TO DATUM C.
6. DIMENSION E3 IS MEASURED AT THE LEAD TIPS WITH THE
LEADS UNCONSTRAINED.
7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE
LEADS, WHERE THE LEADS EXIT THE BODY.
8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE
CORNERS).
DIM
A
A1
A2
b
b2
C
D
D1
E
E1
e
eB
L
M
INCHES
MIN
MAX
−−−−
0.210
0.015
−−−−
0.115 0.195
0.014 0.022
0.060 TYP
0.008 0.014
0.735 0.775
0.005
−−−−
0.300 0.325
0.240 0.280
0.100 BSC
−−−−
0.430
0.115 0.150
−−−−
10 °
MILLIMETERS
MIN
MAX
−−−
5.33
0.38
−−−
2.92
4.95
0.35
0.56
1.52 TYP
0.20
0.36
18.67 19.69
0.13
−−−
7.62
8.26
6.10
7.11
2.54 BSC
−−−
10.92
2.92
3.81
−−−
10 °
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
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reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
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PUBLICATION ORDERING INFORMATION
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6
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For additional information, please contact your local
Sales Representative
LM339S/D