CAT13001 D

CAT130xx
Voltage Supervisor with
Microwire Serial CMOS
EEPROM
Description
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The CAT130xx (see table below) are memory and supervisory
solutions for microcontroller based systems. A CMOS serial
EEPROM memory and a system power supervisor with brown−out
protection are integrated together. Memory interface is via Microwire
serial protocol.
The CAT130xx provides a precision VCC sense circuit with two reset
output options: CMOS active low output or CMOS active high. The
RESET output is active whenever VCC is below the reset threshold or
falls below the reset threshold voltage.
The power supply monitor and reset circuit protect system
controllers during power up/down and against brownout conditions.
Seven reset threshold voltages support 5 V, 3.3 V, 3 V and 2.5 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
peripherals from operating. Reset signals become inactive typically
240 ms after the supply voltage exceeds the reset threshold level.
SOIC−8
CASE 751BD
PIN CONFIGURATION
SOIC (W)
CS
1
8
VCC
SK
2
7
RST/RST
DI
3
6
ORG
DO
4
5
GND
Features
PIN FUNCTION
• Precision Power Supply Voltage Monitor
•
•
•
•
•
•
•
•
•
5 V, 3.3 V, 3 V and 2.5 V Systems
7 Threshold Voltage Options
Active High or Low Reset
♦ Valid Reset Guaranteed at VCC = 1 V
High Speed Operation
Selectable x8 or x16 Memory Organization
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial Temperature Range
RoHS−Compliant 8−Pin SOIC Package
These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
♦
Pin Name
♦
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
Threshold Suffix
Designation
4.63 V
L
4.38 V
M
4.00 V
J
3.08 V
T
2.93 V
S
2.63 V
R
2.32 V
Z
© Semiconductor Components Industries, LLC, 2011
November, 2011 − Rev. 3
GND
Ground
ORG
Memory Organization
RST/RST
Reset Output
VCC
Power Supply
NOTE:
When the ORG pin is connected to VCC, the x16
organization is selected. When it is connected to
ground, the x8 pin is selected. If the ORG pin is left
unconnected, then an internal pullup device will
select the x16 organization.
THRESHOLD SUFFIX SELECTOR
Nominal Threshold Voltage
Function
MEMORY SIZE SELECTOR
Product
13001
Memory Density
1−Kbit
13004
4−Kbit
13008
8−Kbit
13016
16−Kbit
ORDERING INFORMATION
For Ordering Information details, see page 10.
1
Publication Order Number:
CAT13001/D
CAT130xx
BLOCK DIAGRAM
VCC
DO
ORG
VOLTAGE
DETECTOR
EEPROM
CS
RST or RST
SK
DI
VSS
SPECIFICATIONS
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
NEND (Note 3)
TDR
Parameter
Endurance
Min
Units
1,000,000
Program/ Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS
VCC = +2.5 V to +5.5 V, unless otherwise specified.
Symbol
Parameter
Test Conditions
ICC
Supply Current
Read or Write at 1 MHz
ISB
Standby Current
VCC < 5.5 V; All I/O Pins at VSS or VCC
VCC < 3.6 V; All I/O Pins at VSS or VCC
IL
I/O Pin Leakage
VIL
Input Low Voltage
Min
Pin at GND or VCC
VIH
Input High Voltage
VOL
Output Low Voltage
VCC ≥ 2.5 V, IOL = 2.1 mA
VOH
Output High Voltage
VCC ≥ 4.5 V, IOL = −0.4 mA
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2
Typ
Max
Units
3
mA
12
25
mA
10
20
2
mA
−0.5
0.8
V
2.0
VCC + 0.5
V
0.4
V
2.4
V
CAT130xx
Table 4. A.C. CHARACTERISTICS (MEMORY) (Note 1)
VCC = +2.5 V to 5.5 V, TA = −40°C to 85°C, unless otherwise specified.
Parameter
Symbol
Min
Max
Units
2000
kHz
fSK
Clock Frequency
DC
tCSS
CS Setup Time
50
ns
tCSH
CS Hold Time
0
ns
tCSMIN
Minimum CS Low Time
0.25
ms
tSKHI
Minimum SK High Time
0.25
ms
tSKLOW
Minimum SK Low Time
0.25
ms
tDIS
DI Setup Time
100
ns
tDIH
DI Hold Time
100
ns
tPD1
Output Delay to 1
0.25
ms
tPD0
Output Delay to 0
0.25
ms
ns
tHZ (Note 1)
Output Delay to High−Z
100
tSV
Output Delay to Status Valid
0.25
ms
tEW
Program/Erase Pulse Width
5
ms
Power−up to Ready Mode
1
ms
tPU
(Notes 2 & 3)
1. Test conditions according to “A.C. Test Conditions” table.
2. Tested initially and after a design or process change that affects this parameter.
3. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 5. A.C. TEST CONDITIONS
Parameter
Test Conditions
Input Rise and Fall Times
≤50 ns
Input Levels
0.4 V to 2.4 V (4.5 V < VCC < 5.5 V)
Input Levels
0.2 VCC to 0.7 VCC (2.5 V < VCC < 4.5 V)
Timing Reference Levels
Timing Reference Levels
Output Load
0.8 V, 2.0 V (4.5 V < VCC < 5.5 V)
0.5 VCC (2.5 V < VCC < 4.5 V)
Current Source: IOL max / IOH max; CL = 100 pF
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3
CAT130xx
Table 6. ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION)
VCC = Full range, TA = −40°C to +85°C unless otherwise noted. Typical values at TA = +25°C and VCC = 5 V for L/M/J versions,
VCC = 3.3 V for T/S versions, VCC = 3 V for R version and VCC = 2.5 V for Z version.
Symbol
Parameter
Threshold
VTH
Reset Threshold
Voltage
L
M
J
T
S
R
Z
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TA = +25°C
4.56
4.63
4.70
V
TA = −40°C to +85°C
4.50
TA = +25°C
4.31
TA = −40°C to +85°C
4.25
TA = +25°C
3.93
TA = −40°C to +85°C
3.89
TA = +25°C
3.04
TA = −40°C to +85°C
3.00
TA = +25°C
2.89
TA = −40°C to +85°C
2.85
TA = +25°C
2.59
TA = −40°C to +85°C
2.55
TA = +25°C
2.28
TA = −40°C to +85°C
2.25
Conditions
Min
Reset Threshold Tempco
tRPD
VCC to Reset Delay (Note 2)
VCC = VTH to (VTH −100 mV)
tPURST
Reset Active Timeout Period
TA = −40°C to +85°C
VOL
RESET Output Voltage Low
(Push−pull, Active LOW,
CAT130xx9)
VOH
VOL
VOH
140
4.75
4.38
4.45
4.50
4.00
4.06
4.10
3.08
3.11
3.15
2.93
2.96
3.00
2.63
2.66
2.70
2.32
2.35
2.38
Typ
(Note 1)
Max
Units
30
ppm/°C
20
ms
240
460
ms
VCC = VTH min, ISINK = 1.2 mA
R/S/T/Z
0.3
V
VCC = VTH min, ISINK = 3.2 mA
J/L/M
0.4
VCC > 1.0 V, ISINK = 50 mA
0.3
RESET Output Voltage High
(Push−pull, Active LOW,
CAT130xx9)
VCC = VTH max, ISOURCE = −500 mA
R/S/T/Z
0.8 VCC
VCC = VTH max, ISOURCE = −800 mA
J/L/M
VCC − 1.5
RESET Output Voltage Low
(Push−pull, Active HIGH,
CAT130xx1)
VCC > VTH max, ISINK = 1.2 mA
R/S/T/Z
0.3
VCC > VTH max, ISINK = 3.2 mA
J/L/M
0.4
RESET Output Voltage High
(Push−pull, Active HIGH,
CAT130xx1)
1.8 V < VCC ≤ VTH min,
ISOURCE = −150 mA
1. Production testing done at TA = +25°C; limits over temperature guaranteed by design only.
2. RESET output for the CAT130xx9; RESET output for the CAT130xx1.
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0.8 VCC
V
V
V
CAT130xx
PIN DESCRIPTION
CS: The chip select input pin is used to enable/disable the
CAT130xx. When CS is high, the device is selected and
accepts op−codes, addresses and data. Upon receiving a
Write or Erase instruction, the falling edge of CS will start
the internal write cycle to the selected memory location.
ORG: The memory organization input selects the memory
configuration as either register of 16 bits (ORG tied to VCC
or floating) or 8 bits (ORG connected to GND).
RESET/RESET: The reset output is available in two
versions: CMOS Active Low (CAT130xx9) and CMOS
Active High (CAT130xx1). Both versions are push−pull
outputs for high efficiency.
DI: The serial data input pin accepts op−codes, addresses
and data. The input data is latched on the rising edge of the
SK clock input.
SK: The serial clock input pin accepts the clock provided by
the host and used for synchronizing communication
between host and CAT130xx device.
DEVICE OPERATION
The CAT130xx products combine the accurate voltage
monitoring capabilities of a standalone voltage supervisor
with the high quality and reliability of standard EEPROMs
from ON Semiconductor.
TRANSIENT DURATION [μs]
initial voltage of 0.5 V above the threshold and drops below
it by the amplitude of the overdrive voltage (VTH − VCC).
Reset Controller Description
The reset signal is asserted LOW for the CAT130xx9 and
HIGH for the CAT130xx1 when the power supply voltage
falls below the threshold trip voltage and remains asserted
for at least 140 ms (tPURST) after the power supply voltage
has risen above the threshold. Reset output timing is shown
in Figure 2.
The CAT130xx devices protect mPs against brownout
failure. Short duration VCC transients of 4 msec or less and
100 mV amplitude typically do not generate a Reset pulse.
Figure 1 shows the maximum pulse duration of
negative−going VCC transients that do not cause a reset
condition. As the amplitude of the transient goes further
below the threshold (increasing VTH − VCC), the maximum
pulse duration decreases. In this test, the VCC starts from an
TAMB = 25ºC
CAT130xxZ
CAT130xxM
RESET OVERDRIVE VTH - VCC [mV]
Figure 1. Maximum Transient Duration without
Causing a Reset Pulse vs. Overdrive Voltage
VTH
VCC
VRVALID
t PURST
t RPD
t PURST
t RPD
RESET
CAT130xx9
RESET
CAT130xx1
Figure 2. RESET Output Timing
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CAT130xx
EMBEDDED EEPROM OPERATION
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 6−bit (13001)
/ 8−bit (13004) / 9−bit (13008) / 10−bit (13016) address (an
additional bit when organized as x8) and for write operations
a 16−bit data field (8−bit for x8 organization). The
instruction format is shown in Instruction Set Table.
The CAT130xx has a nonvolatile embedded memory
intended for use with industry standard microprocessors.
The memory can be organized as either registers of 16 bits
or 8 bits. The CAT130xx operates on a single power supply
and will generate on chip the high voltage required during
any write operation.
Table 7. INSTRUCTION SET
Address
Data
Instruction
Device
Start Bit
Opcode
x8
x 16
READ
13001
1
10
A6−A0
A5−A0
13004
1
10
A8−A0
A7−A0
13008
1
10
A9−A0
A8−A0
13016
1
10
A10−A0
A9−A0
13001
1
11
A6−A0
A5−A0
13004
1
11
A8−A0
A7−A0
13008
1
11
A9−A0
A8−A0
13016
1
11
A10−A0
A9−A0
13001
1
01
A6−A0
A5−A0
D7−D0
D15−D0
13004
1
01
A8−A0
A7−A0
D7−D0
D15−D0
13008
1
01
A9−A0
A8−A0
D7−D0
D15−D0
13016
1
01
A10−A0
A9−A0
D7−D0
D15−D0
13001
1
00
11xxxxx
11xxxx
13004
1
00
11xxxxxxx
11xxxxxx
13008
1
00
11xxxxxxxx
11xxxxxxx
13016
1
00
11xxxxxxxxx
11xxxxxxxx
13001
1
00
00xxxxx
00xxxx
13004
1
00
00xxxxxxx
00xxxxxx
13008
1
00
00xxxxxxxx
00xxxxxxx
13016
1
00
00xxxxxxxxx
00xxxxxxxx
13001
1
00
10xxxxx
10xxxx
13004
1
00
10xxxxxxx
10xxxxxx
13008
1
00
10xxxxxxxx
10xxxxxxx
13016
1
00
10xxxxxxxxx
10xxxxxxxx
13001
1
00
01xxxxx
01xxxx
D7−D0
D15−D0
13004
1
00
01xxxxxxx
01xxxxxx
D7−D0
D15−D0
13008
1
00
01xxxxxxxx
01xxxxxxx
D7−D0
D15−D0
13016
1
00
01xxxxxxxxx
01xxxxxxxx
D7−D0
D15−D0
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
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6
x8
x 16
Comments
Read Address AN−A0
Clear Address AN−A0
Write Address AN−A0
Write Enable
Write Disable
Clear All Addresses
Write All Address
CAT130xx
Read
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
during a write operation. The serial communication protocol
follows the timing shown in Figure 3.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin. The Ready/Busy flag can be disabled only in Ready
state; no change is allowed in Busy state.
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT130xx will
come out of the high impedance state and, after sending an
initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1). The READ instruction
timing is illustrated in Figure 4.
For the CAT13004/08/16, after the initial data word has
been shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial data
word is preceeded by a dummy zero bit. All subsequent data
words will follow without a dummy zero bit.
tSKLOW
tSKHI
tCSH
SK
tDIS
tDIH
VALIDVALID
DI
tCSS
CS
tDIS
tPD0,tPD1
DO
tCSMIN
DATA VALID
Figure 3. Synchronous Data Timing
SK
tCSMIN
CS
STANDBY
AN
DI
DO
1
1
AN-1
A0
0
HIGH-Z
tPD0
tHZ
HIGH-Z
0
DN
DN-1
Figure 4. Read Instruction Timing
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D1
D0
CAT130xx
Erase/Write Enable and Disable
Write
The CAT130xx powers up in the write disable state. Any
writing after power−up or after an EWDS (write disable)
instruction must first be preceded by the EWEN (write
enable) instruction. Once the write instruction is enabled, it
will remain enabled until power to the device is removed, or
the EWDS instruction is sent. The EWDS instruction can be
used to disable all CAT130xx write and erase instructions,
and will prevent any accidental writing or clearing of the
device. Data can be read normally from the device
regardless of the write enable/disable status. The EWEN and
EWDS instructions timing is shown in Figure 5.
After receiving a WRITE command (Figure 6), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start the
self clocking for auto−clear and data store cycles on the
memory location specified in the instruction. The clocking
of the SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the CAT130xx
can be determined by selecting the device and polling the
DO pin. Since this device features Auto−Clear before write,
it is NOT necessary to erase a memory location before it is
written into.
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE=11
DISABLE=00
Figure 5. EWEN/EWDS Instruction Timing
SK
tCSMIN
AN
DI
1
0
AN-1
A0
DN
D0
1
tSV
DO
STANDBY
STATUS
VERIFY
CS
tHZ
BUSY
HIGH-Z
READY
HIGH-Z
tEW
Figure 6. Write Instruction Timing
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CAT130xx
Erase
Erase All
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN (Figure 7). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT130xx can be determined by selecting the device and
polling the DO pin. Once cleared, the content of a cleared
location returns to a logical “1” state.
Upon receiving an ERAL command (Figure 8), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT130xx can be determined by selecting the device and
polling the DO pin. Once cleared, the contents of all memory
bits return to a logical “1” state.
SK
STATUS VERIFY
CS
AN
DI
1
1
tCS
A0
AN-1
STANDBY
1
tSV
tHZ
HIGH-Z
DO
BUSY READY
HIGH-Z
tEW
Figure 7. Erase Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
0
0
1
0
tSV
DO
tHZ
HIGH-Z
BUSY READY
HIGH-Z
tEW
Figure 8. ERAL Instruction Timing
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CAT130xx
Write All
The ready/busy status of the CAT130xx can be
determined by selecting the device and polling the DO pin.
It is not necessary for all memory locations to be cleared
before the WRAL command is executed.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 9). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode.
SK
CS
STATUS VERIFY
STANDBY
tCSMIN
DI
1
0
0
0
DN
1
D0
tSV
tHZ
DO
BUSY READY
HIGH-Z
tEW
Figure 9. WRAL Instruction Timing
ORDERING INFORMATION
Orderable Part Numbers − CAT130xx Series
(See Notes 1 − 5)
Device
Reset Threshold
Voltage
CAT130019SWI−GT3
2.85 to 3.00 V
CAT130019TWI−GT3
3.00 to 3.15 V
CAT130019SWI−G
2.85 to 3.00 V
Package−Pins
SOIC−8
Shipping
3000 Tape & Reel
100 Tube
1. All packages are RoHS−compliant (Lead−free, Halogen−free).
2. The standard lead finish is NiPdAu.
3. For additional package and temperature options, please contact your nearest
ON Semiconductor Sales office.
4. For 8−Kb and 16−Kb embedded EEPROM option availability please contact your
nearest ON Semiconductor Sales office.
5. For detailed information and a breakdown of device nomenclature and numbering
systems, please see the ON Semiconductor Device Nomenclature document,
TND310/D, available at www.onsemi.com
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10
CAT130xx
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
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PUBLICATION ORDERING INFORMATION
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For additional information, please contact your local
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CAT13001/D
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