CAT93C56 D

CAT93C56, CAT93C57
2-Kb Microwire Serial
CMOS EEPROM
CAT93C57 Not Recommended for New
Designs: Replace with CAT93C56
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Description
The CAT93C56/57 is a 2−kb CMOS Serial EEPROM device which
is organized as either 128 registers of 16 bits (ORG pin at VCC) or 256
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C56/57 features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
SOIC−8
V or W SUFFIX
CASE 751BD
TDFN−8
VP2 SUFFIX
CASE 511AK
SOIC−8 EIAJ
X SUFFIX
CASE 751BE
Features
•
•
•
•
•
•
•
•
•
•
•
•
High Speed Operation: 2 MHz
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
CS
1
8 VCC
NC
1
8 ORG
SK
2
7 NC
VCC
2
7 GND
DI
3
6 ORG
CS
3
6 DO
DO
4
5 GND
SK
4
5 DI
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)
SOIC (W*)
* SOIC (W) rotated pin−out package
not recommended for new designs
PIN FUNCTION
VCC
Pin Name
ORG
CS
SK
CAT93C56
CAT93C57
DO
DI
Function
CS
Chip Select
SK
Clock Input
DI
Serial Data Input
DO
Serial Data Output
VCC
Power Supply
GND
Ground
ORG
Memory Organization
GND
Figure 1. Functional Symbol
NC
NOTE: When the ORG pin is connected to VCC, the x16 organization is selected.
When it is connected to ground, the x8 pin is selected. If the ORG pin is left
unconnected, then an internal pullup device will select the x16 organization.
© Semiconductor Components Industries, LLC, 2014
May, 2014 − Rev. 19
1
No Connection
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Publication Order Number:
CAT93C56/D
CAT93C56, CAT93C57
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on Any Pin with Respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
NEND (Note 3)
TDR
Endurance
Data Retention
Min
Units
1,000,000
Program / Erase Cycles
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, VCC = 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS, CAT93C56
(VCC = +1.8 V to +5.5 V, TA=−40°C to +125°C unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
Units
ICC1
Power Supply
Current (Write)
fSK = 1 MHz, VCC = 5.0 V
1
mA
ICC2
Power Supply
Current (Read)
fSK = 1 MHz, VCC = 5.0 V
500
mA
ISB1
Power Supply
Current (Standby)
(x8 Mode)
VIN = GND or VCC,
CS = GND ORG = GND
TA = −40°C to +85°C
2
mA
TA = −40°C to +125°C
4
Power Supply
Current (Standby)
(x16 Mode)
VIN = GND or VCC, CS =
GND ORG = Float or VCC
TA = −40°C to +85°C
1
TA = −40°C to +125°C
2
TA = −40°C to +85°C
1
TA = −40°C to +125°C
2
TA = −40°C to +85°C
1
TA = −40°C to +125°C
2
ISB2
ILI
ILO
Input Leakage
Current
VIN = GND to VCC
Output Leakage
Current
VOUT = GND to VCC,
CS = GND
VIL1
Input Low Voltage
4.5 V v VCC < 5.5 V
−0.1
VIH1
Input High Voltage
4.5 V v VCC < 5.5 V
VIL2
Input Low Voltage
1.8 V v VCC < 4.5 V
VIH2
Input High Voltage
1.8 V v VCC < 4.5 V
VOL1
Output Low Voltage
4.5 V v VCC < 5.5 V,
IOL = 2.1 mA
VOH1
Output High Voltage
4.5 V v VCC < 5.5 V,
IOH = −400 mA
VOL2
Output Low Voltage
1.8 V v VCC < 4.5 V,
IOL = 1 mA
VOH2
Output High Voltage
1.8 V v VCC < 4.5 V,
IOH = −100 mA
mA
mA
mA
0.8
V
2
VCC + 1
V
0
VCC x 0.2
V
VCC x 0.7
VCC + 1
V
0.4
V
2.4
V
0.2
VCC − 0.2
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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CAT93C56, CAT93C57
Table 4. D.C. OPERATING CHARACTERISTICS, CAT93C57, Die Rev. E – Mature Product
(NOT RECOMMENDED FOR NEW DESIGNS) (VCC = +1.8 V to +5.5 V, TA=−40°C to +125°C unless otherwise specified.)
Parameter
Symbol
Test Conditions
Min
Max
Units
ICC1
Power Supply Current (Write)
fSK = 1 MHz, VCC = 5.0 V
3
mA
ICC2
Power Supply Current (Read)
fSK = 1 MHz, VCC = 5.0 V
500
mA
ISB1
Power Supply Current (Standby)
(x8 Mode)
VIN = GND or VCC, CS = GND
ORG = GND
10
mA
ISB2
Power Supply Current (Standby)
(x16 Mode)
VIN = GND or VCC, CS = GND
ORG = Float or VCC
10
mA
VIN = GND to VCC
1
mA
VOUT = GND to VCC, CS = GND
1
mA
ILI
Input Leakage Current
ILO
Output Leakage Current
VIL1
Input Low Voltage
4.5 V v VCC < 5.5 V
−0.1
0.8
V
VIH1
Input High Voltage
4.5 V v VCC < 5.5 V
2
VCC + 1
V
VIL2
Input Low Voltage
1.8 V v VCC < 4.5 V
0
VCC x 0.2
V
VCC x 0.7
VCC + 1
V
0.4
V
VIH2
Input High Voltage
1.8 V v VCC < 4.5 V
VOL1
Output Low Voltage
4.5 V v VCC < 5.5 V, IOL = 2.1 mA
VOH1
Output High Voltage
4.5 V v VCC < 5.5 V, IOH = −400 mA
VOL2
Output Low Voltage
1.8 V v VCC < 4.5 V, IOL = 1 mA
VOH2
Output High Voltage
1.8 V v VCC < 4.5 V, IOH = −100 mA
2.4
V
0.2
VCC − 0.2
V
V
Table 5. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V)
Symbol
COUT (Note 4)
CIN (Note 4)
Test
Conditions
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Max
Units
VOUT = 0 V
Min
Typ
5
pF
VIN = 0 V
5
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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CAT93C56, CAT93C57
Table 6. A.C. CHARACTERISTICS (Note 5), CAT93C56
(VCC = +1.8V to +5.5V, TA = −40°C to +125°C, unless otherwise specified.)
Limits
Symbol
Min
Parameter
tCSS
CS Setup Time
tCSH
tDIS
Max
Units
50
ns
CS Hold Time
0
ns
DI Setup Time
100
ns
tDIH
DI Hold Time
100
ns
tPD1
Output Delay to 1
0.25
ms
tPD0
Output Delay to 0
0.25
ms
Output Delay to High−Z
100
ns
5
ms
tHZ (Note 6)
tEW
Program/Erase Pulse Width
tCSMIN
Minimum CS Low Time
0.25
ms
tSKHI
Minimum SK High Time
0.25
ms
tSKLOW
Minimum SK Low Time
0.25
ms
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
DC
0.25
ms
2000
kHz
Table 7. A.C. CHARACTERISTICS (Note 5), CAT93C57, Die Rev. E – Mature Product
(NOT RECOMMENDED FOR NEW DESIGNS)
Limits
VCC = 1.8 V − 5.5 V
Symbol
Parameter
Min
VCC = 2.5 V − 5.5 V
Max
Min
Max
VCC = 4.5 V − 5.5 V
Min
Max
Units
tCSS
CS Setup Time
200
100
50
ns
tCSH
CS Hold Time
0
0
0
ns
tDIS
DI Setup Time
400
200
100
ns
400
tDIH
DI Hold Time
tPD1
Output Delay to 1
1
0.5
0.25
ms
tPD0
Output Delay to 0
1
0.5
0.25
ms
Output Delay to High−Z
400
200
100
ns
Program/Erase Pulse Width
10
10
10
ms
tHZ
(Note 6)
tEW
200
100
ns
tCSMIN
Minimum CS Low Time
1
0.5
0.25
ms
tSKHI
Minimum SK High Time
1
0.5
0.25
ms
tSKLOW
Minimum SK Low Time
1
0.5
0.25
ms
tSV
Output Delay to Status Valid
SKMAX
Maximum Clock Frequency
1
DC
250
0.5
DC
500
DC
0.25
ms
1000
kHz
Table 8. POWER−UP TIMING (Notes 6 and 7)
Symbol
Parameter
Max
Units
tPUR
Power−up to Read Operation
1
ms
tPUW
Power−up to Write Operation
1
ms
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
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CAT93C56, CAT93C57
Table 9. A.C. TEST CONDITIONS
Input Rise and Fall Times
≤ 50 ns
Input Pulse Voltages
0.4 V to 2.4 V
4.5 V v VCC v 5.5 V
Timing Reference Voltages
0.8 V, 2.0 V
4.5 V v VCC v 5.5 V
Input Pulse Voltages
0.2 VCC to 0.7 VCC
1.8 V v VCC v 4.5 V
Timing Reference Voltages
0.5 VCC
1.8 V v VCC v 4.5 V
Output Load
Current Source IOLmax/IOHmax; CL=100 pF
Device Operation
The CAT93C56/57 is a 2048−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C56/57 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 10−bit
instructions for 93C57 or seven 11−bit instructions for
93C56 control the reading, writing and erase operations of
the device. When organized as X8, seven 11−bit instructions
for 93C57 or seven 12−bit instructions for 93C56 control the
reading, writing and erase operations of the device. The
CAT93C56/57 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
tSKHI
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
tSKLOW
tCSH
SK
tDIH
tDIS
VALID
VALID
DI
tCSS
CS
tDIS
tPD0, tPD1
DO
DATA VALID
Figure 2. Synchronous Data Timing
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5
tCSMN
CAT93C56, CAT93C57
The format for all instructions sent to the device is a
logical “1” start bit, a 2−bit (or 4−bit) opcode, 7−bit address
(CAT93C57) / 8−bit address (CAT93C56) (an additional bit
when organized X8) and for write operations a 16−bit data
field (8−bit for X8 organizations). The instruction format is
shown in Instruction Set table.
Table 10. INSTRUCTION SET
Address
Data
Instruction
Device Type
Start
Bit
READ
93C56 (Note 8)
1
10
A8−A0
A7−A0
93C57
1
10
A7−A0
A6−A0
93C56 (Note 8)
1
11
A8−A0
A7−A0
93C57
1
11
A7−A0
A6−A0
93C56 (Note 8)
1
01
A8−A0
A7−A0
D7−D0
D15−D0
93C57
1
01
A7−A0
A6−A0
D7−D0
D15−D0
93C56 (Note 8)
1
00
11XXXXXXX
11XXXXXX
93C57
1
00
11XXXXXX
11XXXXX
93C56 (Note 8)
1
00
00XXXXXXX
00XXXXXX
93C57
1
00
00XXXXXX
00XXXXX
93C56 (Note 8)
1
00
10XXXXXXX
10XXXXXX
93C57
1
00
10XXXXXX
10XXXXX
93C56 (Note 8)
1
00
01XXXXXXX
01XXXXXX
D7−D0
D15−D0
93C57
1
00
01XXXXXX
01XXXXX
D7−D0
D15−D0
ERASE
WRITE
EWEN
EWDS
ERAL
WRAL
Opcode
x8
x16
x8
x16
Comments
Read Address
AN–A0
Clear Address
AN–A0
Write Address
AN–A0
Write Enable
Write Disable
Clear All
Addresses
Write All
Addresses
8. Address bit A8 for 256x8 organization and A7 for 128x16 organization are “Don’t Care” bits, but must be kept at either a “1” or “0” for READ,
WRITE and ERASE commands.
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CAT93C56, CAT93C57
Read
data word is preceeded by a dummy zero bit. All subsequent
data words will follow without a dummy zero bit. The
READ instruction timing is illustrated in Figure 3.
Upon receiving a READ command and an address
(clocked into the DI pin), the DO pin of the CAT93C56/57
will come out of the high impedance state and, after sending
an initial dummy zero bit, will begin shifting out the data
addressed (MSB first). The output data bits will toggle on
the rising edge of the SK clock and are stable after the
specified time delay (tPD0 or tPD1).
For the CAT93C56/57, after the initial data word has been
shifted out and CS remains asserted with the SK clock
continuing to toggle, the device will automatically
increment to the next address and shift out the next data word
in a sequential READ mode. As long as CS is continuously
asserted and SK continues to toggle, the device will keep
incrementing to the next address automatically until it
reaches to the end of the address space, then loops back to
address 0. In the sequential READ mode, only the initial
Erase/Write Enable and Disable
The CAT93C56/57 powers up in the write disable state.
Any writing after power−up or after an EWDS (erase/write
disable) instruction must first be preceded by the EWEN
(erase/write enable) instruction. Once the write instruction
is enabled, it will remain enabled until power to the device
is removed, or the EWDS instruction is sent. The EWDS
instruction can be used to disable all CAT93C56/57 write
and erase instructions, and will prevent any accidental
writing or clearing of the device. Data can be read normally
from the device regardless of the write enable/disable status.
The EWEN and EWDS instructions timing is shown in
Figure 4.
SK
CS
Don’t Care
AN
DI
1
1
AN−1
A0
0
tPD0
HIGH−Z
DO
Dummy 0
D15 . . . D0
or
D7 . . . D0
Address + 1
D15 . . . D0
or
D7 . . . D0
Address + 2
D15 . . . D0
or
D7 . . . D0
Figure 3. READ Instruction Timing
SK
STANDBY
CS
DI
1
0
0
*
* ENABLE = 11
DISABLE = 00
Figure 4. EWEN/EWDS Instruction Timing
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7
Address + n
D15 . . .
or
D7 . . .
CAT93C56, CAT93C57
Write
Erase
After receiving a WRITE command (Figure 5), address
and the data, the CS (Chip Select) pin must be deselected for
a minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the SK
pin is not necessary after the device has entered the self
clocking mode. The ready/busy status of the CAT93C56/57
can be determined by selecting the device and polling the
DO pin. Since this device features Auto−Clear before write,
it is NOT necessary to erase a memory location before it is
written into.
Upon receiving an ERASE command and address, the CS
(Chip Select) pin must be deasserted for a minimum of
tCSMIN (Figure 6). The falling edge of CS will start the self
clocking clear cycle of the selected memory location. The
clocking of the SaK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the content of a
cleared location returns to a logical “1” state.
SK
tCSMIN
CS
STATUS
VERIFY
AN
DI
1
0
AN−1
A0
DN
STANDBY
D0
1
tSV
BUSY
HIGH−Z
DO
tHZ
READY
HIGH−Z
tEW
Figure 5. Write Instruction Timing
SK
CS
STATUS VERIFY
AN
DI
1
1
AN−1
tCS
A0
1
tSV
DO
STANDBY
HIGH−Z
tHZ
BUSY
READY
HIGH−Z
tEW
Figure 6. Erase Instruction Timing
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CAT93C56, CAT93C57
Erase All
Write All
Upon receiving an ERAL command (Figure 7), the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN. The falling edge of CS will start the self clocking
clear cycle of all memory locations in the device. The
clocking of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of the
CAT93C56/57 can be determined by selecting the device
and polling the DO pin. Once cleared, the contents of all
memory bits return to a logical “1” state.
Upon receiving a WRAL command and data, the CS
(Chip Select) pin must be deselected for a minimum of
tCSMIN (Figure 8). The falling edge of CS will start the self
clocking data write to all memory locations in the device.
The clocking of the SK pin is not necessary after the device
has entered the self clocking mode. The ready/busy status of
the CAT93C56/57 can be determined by selecting the device
and polling the DO pin. It is not necessary for all memory
locations to be cleared before the WRAL command is
executed.
SK
CS
STATUS VERIFY
STANDBY
tCS
DI
1
0
1
0
0
tSV
tHZ
HIGH−Z
DO
BUSY
READY
HIGH−Z
tEW
Figure 7. ERAL Instruction Timing
SK
CS
STATUS VERIFY
STANDBY
tCSMIN
DI
1
0
0
0
1
DN
D0
tSV
tHZ
BUSY
DO
READY
HIGH−Z
tEW
Figure 8. WRAL Instruction Timing
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CAT93C56, CAT93C57
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA−01
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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CAT93C56, CAT93C57
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
MAX
4.00
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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CAT93C56, CAT93C57
PACKAGE DIMENSIONS
SOIC−8, 208 mils
CASE 751BE−01
ISSUE O
SYMBOL
MIN
NOM
2.03
A
E1 E
MAX
A1
0.05
0.25
b
0.36
0.48
c
0.19
0.25
D
5.13
5.33
E
7.75
8.26
E1
5.13
5.38
1.27 BSC
e
L
0.51
0.76
θ
0º
8º
PIN#1 IDENTIFICATION
TOP VIEW
D
A
e
b
q
L
A1
SIDE VIEW
c
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with EIAJ EDR-7320.
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CAT93C56, CAT93C57
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL−01
ISSUE O
b
SYMBOL
MIN
NOM
1.20
A
E1
E
MAX
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
0.20
0.65 BSC
e
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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CAT93C56, CAT93C57
PACKAGE DIMENSIONS
TDFN8, 2x3
CASE 511AK−01
ISSUE A
D
A
e
b
E2
E
PIN#1
IDENTIFICATION
A1
PIN#1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
A2
0.45
0.55
0.65
A3
A2
A3
0.20
0.25
0.30
D
1.90
2.00
2.10
D2
1.30
1.40
1.50
E
2.90
3.00
3.10
E2
1.20
1.30
1.40
L
BOTTOM VIEW
0.20 REF
b
e
FRONT VIEW
0.50 TYP
0.20
0.30
L
0.40
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MO-229.
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14
CAT93C56, CAT93C57
Example of Ordering Information
OPN
Specific
Device Marking
Pkg Type
Temperature Range
Lead Finish
Shipping
CAT93C56LI−G
CSI*4G /
93C56LI
PDIP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 50 Units / Tube
CAT93C56VE−G
CSI*4G /
93C56LE
SOIC−8, JEDEC
E = Extended
(−40°C to +125°C)
NiPdAu
Tube, 100 Units / Tube
CAT93C56VE−GT3
CSI*4G /
93C56VE
SOIC−8, JEDEC
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C56VI−G
CSI*4G /
93C56VI
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT93C56VI−GT3
CSI*4G /
93C56VI
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
HB
TDFN−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C56WI−G
CSI*4G /
93C56WI
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT93C56WI−GT3
93C56W
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C56XI
CSI*3G /
93C56XI
SOIC−8, EIAJ
I = Industrial
(−40°C to +85°C)
Matte−Tin
Tube, 94 Units / Tube
CAT93C56XI−T2
CSI*3G /
93C56XI
SOIC−8, EIAJ
I = Industrial
(−40°C to +85°C)
Matte−Tin
Tape & Reel,
2000 Units / Reel
CAT93C56YI−G
M56
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT93C56YI−GT3
M56
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C57LI−G
CSI*4E/
93C57LI
PDIP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 50 Units / Tube
CAT93C57VI−G
CSI*4E /
93C57VI
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT93C57VI−GT3
CSI*4E /
93C57VI
SOIC−8, JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C57XI
CSI*3E /
93C57X
SOIC−8, EIAJ
I = Industrial
(−40°C to +85°C)
Matte−Tin
Tube, 94 Units / Tube
CAT93C57XI−T2
CSI*3E /
93C57X
SOIC−8, EIAJ
I = Industrial
(−40°C to +85°C)
Matte−Tin
Tape & Reel,
2000 Units / Reel
M57
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel,
3000 Units / Reel
CAT93C56VP2I−GT3
CAT93C57YI−GT3
9. All packages are RoHS−compliant (Lead−free, Halogen−free).
10. The standard lead finish is NiPdAu.
11. CAT93C57 NOT recommended for new designs.
12. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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15
CAT93C56, CAT93C57
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks,
copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC
reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications
and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC
does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where
personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture
of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
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16
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
CAT93C56/D
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