MC100LVEL30 D

MC100LVEL30
3.3VECL Triple D Flip−Flop
with Set and Reset
Description
The MC100LVEL30 is a triple master−slave D flip−flop with
differential outputs. Data enters the master latch when the clock input
is LOW and transfers to the slave upon a positive transition on the
clock input.
In addition to a common Set input individual Reset inputs are
provided for each flip−flop. Both the Set and Reset inputs function
asynchronous and overriding with respect to the clock inputs.
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Features
•
•
•
•
•
•
1200 MHz Minimum Toggle Frequency
450 ps Typical Propagation Delays
SO−20 WB
DW SUFFIX
CASE 751D
ESD Protection: >2 kV Human Body Model
The 100 Series Contains Temperature Compensation.
PECL Mode Operating Range:
VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range:
VCC = 0 V with VEE = −3.0 V to −3.8 V
Internal Input 75 kW Pulldown Resistors
MARKING DIAGRAM*
•
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity:
•
Pb Pkg
Level 1,
Pb−Free Pkg
Level 3
For Additional Information, see Application Note AND8003/D
Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
Transistor Count = 347 devices
•
• Pb−Free Packages are Available*
20
100LVEL30
AWLYYWWG
1
A
WL
YY
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
© Semiconductor Components Industries, LLC, 2006
November, 2006 − Rev. 7
1
Publication Order Number:
MC100LVEL30/D
MC100LVEL30
VCC
Q0
Q0 VCC
Q1
Q1
VCC Q2
Q2
VEE
20
19
18
16
15
14
13
12
11
Q
Q
Q
Q
Q
Q
S
17
R
S
D
1
S012
2
R
S
D
4
5
R0
D1
3
D0 CLK0
R
D
6
7
8
CLK1 R1
9
D2
10
CLK2 R2
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
Figure 1. Logic Diagram and Pinout: 20-Lead SOIC (Top View)
Table 2. PIN DESCRIPTION
Table 1. TRUTH TABLE
PIN
FUNCTION
D0−D2
R0−R2
CLK0−CLK2
S012
Q0−Q2; Q0−Q2
VCC
VEE
ECL Data Inputs
ECL Reset Inputs
ECL Clock Inputs
ECL Common Set Input
ECL Differential Data Outputs
Positive Supply
Negative Supply
R
S
D
CLK
Q
Q
L
L
H
L
H
L
L
L
H
H
L
H
X
X
X
Z
Z
X
X
X
L
H
L
H
Undef
H
L
H
L
Undef
Z = LOW to HIGH Transition
X = Don’t Care
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC
PECL Mode Power Supply
VEE = 0 V
8 to 0
V
VEE
NECL Mode Power Supply
VCC = 0 V
−8 to 0
V
VI
PECL Mode Input Voltage
NECL Mode Input Voltage
VEE = 0 V
VCC = 0 V
6 to 0
−6 to 0
V
V
Iout
Output Current
Continuous
Surge
50
100
mA
mA
TA
Operating Temperature Range
−40 to +85
°C
Tstg
Storage Temperature Range
−65 to +150
°C
qJA
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
SOIC−20
SOIC−20
90
60
°C/W
°C/W
qJC
Thermal Resistance (Junction−to−Case)
Standard Board
SOIC−20
30 to 35
°C/W
Tsol
Wave Solder
<2 to 3 sec @ 248°C
265
°C
VI VCC
VI VEE
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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2
MC100LVEL30
Table 4. LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 1)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
62
Min
85°C
Typ
Max
55
62
Min
Typ
Max
Unit
55
64
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 2)
2215
2295
2420
2275
2345
2420
2275
2345
2420
mV
VOL
Output LOW Voltage (Note 2)
1470
1605
1745
1490
1595
1680
1490
1595
1680
mV
VIH
Input HIGH Voltage
2135
2420
2135
2420
2135
2420
mV
VIL
Input LOW Voltage
1490
1825
1490
1825
1490
1825
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
Table 5. LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = −3.3 V (Note 3)
−40°C
Symbol
Characteristic
Min
25°C
Typ
Max
55
62
Min
85°C
Typ
Max
55
62
Min
Typ
Max
Unit
55
64
mA
IEE
Power Supply Current
VOH
Output HIGH Voltage (Note 4)
−1085
−1005
−880
−1025
−955
−880
−1025
−955
−880
mV
VOL
Output LOW Voltage (Note 4)
−1830
−1695
−1555
−1810
−1705
−1620
−1810
−1705
−1620
mV
VIH
Input HIGH Voltage
−1165
−880
−1165
−880
−1165
−880
mV
VIL
Input LOW Voltage
−1810
−1475
−1810
−1475
−1810
−1475
mV
IIH
Input HIGH Current
150
mA
IIL
Input LOW Current
150
0.5
150
0.5
0.5
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with VCC. VEE can vary ±0.3 V.
4. Outputs are terminated through a 50 W resistor to VCC − 2.0 V.
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3
MC100LVEL30
Table 6. AC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V or VCC = 0.0 V; VEE = −3.3 V (Note 5)
−40°C
Symbol
Characteristic
Min
Typ
25°C
Max
Min
85°C
Typ
Max
Typ
Max
Maximum Toggle Frequency
1.2
tPLH
tPHL
Propagation Delay to Output CLK, S, R
550
tS
tH
Setup Time
Hold Time
150
200
0
100
150
200
0
100
150
200
0
100
ps
tRR
Set/Reset Recovery
400
200
400
200
400
200
ps
tPW
Minimum Pulse Width
tJITTER
Cycle−to−Cycle Jitter
tr
tf
Output Rise/Fall Times Q
(20% − 80%)
800
400
650
1.2
Unit
fmax
CLK
Set, Reset
1.2
Min
570
820
400
650
TBD
590
550
280
840
TBD
450
550
280
ps
ps
400
650
TBD
280
GHz
ps
550
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. VEE can vary ±0.3 V.
Q
Zo = 50 W
D
Receiver
Device
Driver
Device
Q
D
Zo = 50 W
50 W
50 W
VTT
VTT = VCC − 2.0 V
Figure 2. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
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4
MC100LVEL30
ORDERING INFORMATION
Package
Package†
MC100LVEL30DW
SOIC−20
38 Units / Rail
MC100LVEL30DWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC100LVEL30DWR2
SOIC−20
1000 / Tape & Reel
MC100LVEL30DWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
− ECL Clock Distribution Techniques
AN1406/D
− Designing with PECL (ECL at +5.0 V)
AN1503/D
− ECLinPS I/O SPiCE Modeling Kit
AN1504/D
− Metastability and the ECLinPS Family
AN1568/D
− Interfacing Between LVDS and ECL
AN1672/D
− The ECL Translator Guide
AND8001/D
− Odd Number Counters Design
AND8002/D
− Marking and Date Codes
AND8020/D
− Termination of ECL Logic Devices
AND8066/D
− Interfacing with ECLinPS
AND8090/D
− AC Characteristics of ECL Devices
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5
MC100LVEL30
PACKAGE DIMENSIONS
SO−20 WB
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
q
X 45 _
E
h
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
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operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC100LVEL30/D