ESD5205 D

ESD5205
Transient Voltage
Suppressors
Low Capacitance ESD Protection Diode
for High Speed Data Line
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The ESD5205 transient voltage suppressor is designed to protect
high speed data lines from ESD. Low capacitance and low ESD
clamping voltage make this device an ideal solution for protecting
voltage sensitive high speed data lines.
MARKING
DIAGRAM
SOT−963
CASE 527AD
Features
• Protection for the Following IEC Standards:
IEC 61000−4−2 (Level 4)
X
M
• Low ESD Clamping Voltage
• This is a Pb−Free Device
Typical Applications
XM
1
= Specific Device Code
= Month Code
PIN CONFIGURATION
AND SCHEMATIC
• mSD Connector
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
PPK
18
W
Operating Junction Temperature Range
TJ
−55 to +125
°C
Storage Temperature Range
Tstg
−55 to +150
°C
Lead Solder Temperature −
Maximum (10 Seconds)
TL
260
°C
ESD
ESD
±15
±15
kV
kV
Peak Power Dissipation,
8 x 20 ms
IEC 61000−4−2 Contact (ESD)
IEC 61000−4−2 Air (ESD)
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1
6
2
5
3
4
ORDERING INFORMATION
Device
ESD5205P6T6G
Package
Shipping
SOT−963
(Pb−Free)
8000 / Tape &
Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of
survivability specs.
© Semiconductor Components Industries, LLC, 2012
December, 2012 − Rev. 0
1
Publication Order Number:
ESD5205/D
ESD5205
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage
Symbol
VRWM
VBR
Conditions
Min
Typ
Max
Unit
5.0
V
I/O Pin to GND
IT = 1 mA, I/O Pin to GND
5.5
V
Reverse Leakage Current
IR
VRWM = 5 V, I/O Pin to GND
1.0
mA
Clamping Voltage (Note 1)
VC
IPP = 1 A, I/O Pin to GND (8 x 20 ms pulse)
IPP = 2 A, I/O Pin to GND (8 x 20 ms pulse)
9
10
V
Clamping Voltage (Note 2)
VC
IEC61000−4−2, ±8 KV Contact
Clamping Voltage
TLP (Note 3)
VC
IPP = 8 A
IPP = 16 A
IPP = −8 A
IPP = −16 A
Junction Capacitance
CJ
VR = 0 V, f = 1 MHz between I/O Pins and GND
See Figures 1 and 2
V
11.4
15.6
−4.5
−8.1
9.0
1. Surge current waveform per Figure 5.
2. For test procedure see Figures 3 and 4 and application note AND8307/D.
3. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z0 = 50 W, tp = 100 ns, tr = 4 ns, averaging window; t1 = 30 ns to t2 = 60 ns.
Figure 1. IEC61000−4−2 +8 KV Contact ESD
Clamping Voltage
Figure 2. IEC61000−4−2 −8 KV Contact
Clamping Voltage
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2
pF
ESD5205
IEC61000−4−2 Waveform
IEC 61000−4−2 Spec.
Ipeak
Level
Test
Voltage
(kV)
First Peak
Current
(A)
Current at
30 ns (A)
Current at
60 ns (A)
1
2
7.5
4
2
2
4
15
8
4
3
6
22.5
12
6
4
8
30
16
8
100%
90%
I @ 30 ns
I @ 60 ns
10%
tP = 0.7 ns to 1 ns
Figure 3. IEC61000−4−2 Spec
ESD Gun
Oscilloscope
TVS
50 W
Cable
50 W
Figure 4. Diagram of ESD Clamping Voltage Test Setup
The following is taken from Application Note
AND8308/D − Interpretation of Datasheet Parameters
for ESD Devices.
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
% OF PEAK PULSE CURRENT
100
PEAK VALUE IRSM @ 8 ms
tr
90
PULSE WIDTH (tP) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8 ms
80
70
60
HALF VALUE IRSM/2 @ 20 ms
50
40
30
tP
20
10
0
0
20
40
t, TIME (ms)
60
Figure 5. 8 X 20 ms Pulse Waveform
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3
80
ESD5205
PACKAGE DIMENSIONS
SOT−963
CASE 527AD
ISSUE E
D
X
Y
6
5
4
1
2
3
A
HE
E
C
SIDE VIEW
TOP VIEW
e
6X L2
6X
6X
BOTTOM VIEW
L
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS OF
BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH, PROTRUSIONS, OR GATE BURRS.
MILLIMETERS
MIN
NOM
MAX
0.34
0.37
0.40
0.10
0.15
0.20
0.07
0.12
0.17
0.95
1.00
1.05
0.75
0.80
0.85
0.35 BSC
0.95
1.00
1.05
0.19 REF
0.05
0.10
0.15
DIM
A
b
C
D
E
e
HE
L
L2
RECOMMENDED
MOUNTING FOOTPRINT
b
6X
6X
0.08 X Y
0.35
0.20
PACKAGE
OUTLINE
1.20
0.35
PITCH
DIMENSIONS: MILLIMETERS
ON Semiconductor and
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4
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ESD5205/D
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