NB6L72M D

NB6L72M
2.5V / 3.3V Differential 2 X 2
Crosspoint Switch with
CML Outputs
Multi- Level Inputs w/ Internal Termination
http://onsemi.com
Description
The NB6L72M is a clock or data high-bandwidth fully differential
2 x 2 Crosspoint Switch with internal source termination and CML
output structure, optimized for low skew and minimal jitter. The
differential inputs incorporate internal 50 W termination resistors and
will accept LVPECL, CML, LVDS, LVCMOS, or LVTTL logic levels.
The SELECT inputs are single-ended and can be driven with
LVCMOS/LVTTL.
The 16 mA differential CML outputs provide matching internal
50 W terminations and 400 mV output swings when externally
terminated with a 50 W resistor to VCC.
The device is offered in a small 3 mm x 3 mm 16-pin QFN package.
The NB6L72M is a member of the ECLinPS MAX™ family of
high performance clock and data management products.
Features
•Input Clock Frequency > 3.0 GHz
•Input Data Rate > 3 Gb/s
•360 ps Typical Propagation Delay
•65 ps Typical Rise and Fall Times
•Differential CML Outputs, 380 mV peak-to-peak, typical
•Operating Range: VCC = 2.375 V to 3.63 V with GND = 0 V
•Internal Input and Output Termination Resistors, 50 W
•Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,
MARKING
DIAGRAM*
16
1
1
QFN-16
MN SUFFIX
CASE 485G
NB6L
72M
ALYWG
G
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb-Free Package
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
EP, and SG Devices
•-40 °C to +85°C Ambient Operating Temperature
•These are Pb-Free Devices
© Semiconductor Components Industries, LLC, 2007
June, 2007 - Rev. 3
1
Publication Order Number:
NB6L72M/D
NB6L72M
VTD0
50 W
50 W
D0
2
2
D0
2
D1
2
Q0
2
Q0
D1
+
50 W
VTD1
50 W
VCC
+
75 kW
SEL0
GND
2
2
2
2
+
75 kW
SEL1
Q1
Q1
2
Figure 1. Logic/Block Diagram
http://onsemi.com
2
NB6L72M
SEL0
D0
GND
Q0
Q0
VCC
16
15
14
13
1
Exposed Pad (EP)
12
2
Table 1. INPUT/OUTPUT SELECT TRUTH TABLE
SEL0*
SEL1*
Q0
Q1
L
L
D0
D0
H
L
D1
D0
L
H
D0
D1
H
H
D1
D1
VCC
11
Q1
NB6L72M
D0
3
10
Q1
VTD0
4
9
GND
*Defaults HIGH when left open
5
VTD1
6
7
8
D1
D1
SEL1
Figure 2. Pin Configuration (Top View)
Table 2. PIN DESCRIPTION
Pin
Name
I/O
1
SEL0
LVTTL,LVCMOS
Input
Select Logic Input control that selects D0 or D1 to output Q0. See Table 1, Select Input
Function Table. Pin defaults HIGH when left open
Description
2
D0
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Noninverted Differential Input. Note 1
3
D0
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Inverted Differential Input. Note 1
4
VTD0
-
Internal 50 W Termination Pin. Note 1.
5
VTD1
-
Internal 50 W termination pin. Note 1.
6
D1
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Noninverted Differential Input. Note 1.
7
D1
LVPECL, CML,
LVDS, LVTTL,
LVCMOS, Input
Inverted Differential Input. Note 1
8
SEL1
LVTTL,LVCMOS
Input
Select Logic Input control that selects D0 or D1 to output Q1. See Table 1, Select Input
Function Table. Pin defaults HIGH when left open
9
GND
-
10
Q1
CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
11
Q1
CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to VCC.
12
VCC
-
Positive Supply Voltage
13
VCC
-
Positive Supply Voltage
14
Q0
CML Output
Inverted Differential Reset Input. Typically Terminated with 50 W Resistor to VCC.
15
Q0
CML Output
Noninverted Differential Reset Input. Typically Terminated with 50 W Resistor to VCC.
16
GND
-
Negative Supply Voltage
-
EP
-
The Exposed Pad (EP) on the QFN-16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat-sinking
conduit. The pad is not electrically connected to the die, but is recommended to be
electrically and thermally connected to GND on the PC board.
Negative Supply Voltage
1. In the differential configuration when the input termination pin (VTDn) are connected to a common termination voltage or left open, and if
no signal is applied on Dn/Dn input, then the device will be susceptible to self-oscillation.
2. All VCC and GND pins must be externally connected to a power supply for proper operation.
http://onsemi.com
3
NB6L72M
Table 3. ATTRIBUTES
Characteristics
Value
Interval Input Pulldown Resistor
75 kW
ESD Protection
Human Body Model
Machine Model
Moisture Sensitivity
16-QFN
Flammability Rating
Oxygen Index: 28 to 34
> 2 kV
> 200V
Level 1
UL 94 V-0 @ 0.125 in
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Table 4. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
4.0
V
4.5
V
VCC - GND
V
45
80
mA
mA
-40 to +85
°C
-65 to +150
°C
VCC
Positive Power Supply
GND = 0 V
VIO
Positive Input/Output Voltage
GND = 0 V
VINPP
Differential Input Voltage
IIN
Input Current Through RT (50 W Resistor)
Static
Surge
TA
Operating Temperature Range
QFN-16
Tstg
Storage Temperature Range
qJA
Thermal Resistance
(Junction-to-Ambient) (Note 3)
0 lfpm
500 lfpm
QFN-16
QFN-16
42
35
°C/W
°C/W
qJC
Thermal Resistance (Junction-to-Case)
(Note 3)
QFN-16
4
°C/W
Tsol
Wave Solder Pb-Free
265
°C
-0.5 v VIO v VCC + 0.5
|D - D|
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board - 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
http://onsemi.com
4
NB6L72M
Table 5. DC CHARACTERISTICS, Multi-Level Inputs VCC = 2.375 V to 3.63 V, GND = 0 V, TA = -40°C to +85°C
Characteristic
Symbol
Min
Typ
Max
Unit
60
80
105
mA
VCC - 40
3260
2460
VCC - 10
3290
2490
VCC
3300
2500
mV
VCC = 3.3 V
VCC = 2.5 V
VCC - 500
2800
2000
VCC - 400
2900
2100
VCC - 300
3000
2200
mV
VCC = 3.3 V
VCC = 2.5 V
1050
VCC - 150
mV
POWER SUPPLY CURRENT
ICC
Power Supply Current (Inputs and Outputs Open)
CML OUTPUTS (Notes 5 and 6)
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
DIFFERENTIAL INPUT DRIVEN SINGLE-ENDED (see Figures 6 and 8)
Vth
Input Threshold Reference Voltage Range (Note 7)
VIH
Single-Ended Input HIGH Voltage
Vth + 150
VCC
mV
VIL
Single-Ended Input LOW Voltage
GND
Vth - 150
mV
VISE
Single-Ended Input Voltage Amplitude (VIH - VIL)
300
VCC - VEE
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 7 and 9) (Note 8)
VIHD
Differential Input HIGH Voltage
1200
VCC
mV
VILD
Differential Input LOW Voltage
GND
VCC - 150
mV
VID
Differential Input Voltage Swing (Dn, Dn) (VIHD - VILD) (Note 15)
150
VCC - VEE
mV
VCMR
Input Common Mode Range (Differential Configuration) (Note 9)
950
VCC – 75
mV
IIH
Input HIGH Current Dn/Dn, (VTDn/VTDn Open)
-150
+150
mA
IIL
Input LOW Current Dn/Dn, (VTDn/VTDn Open)
-150
+150
mA
SINGLE-ENDED LVCMOS/LVTTL CONTROL INPUTS
VIH
Single-Ended Input HIGH Voltage
2000
VCC
mV
VIL
Single-Ended Input LOW Voltage
GND
800
mV
IIH
Input HIGH Current
-150
+150
mA
IIL
Input LOW Current
-150
+150
mA
TERMINATION RESISTORS
RTIN
Internal Input Termination Resistor
40
50
60
W
RTOUT
Internal Output Termination Resistor
40
50
60
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs loaded with 50 W to VCC for proper operation.
5. Input and output parameters vary 1:1 with VCC.
6. Vth, VIH, VIL,, and VISE parameters must be complied with simultaneously.
7. Vth is applied to the complementary input when operating in single-ended mode.
8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
9. VCMR minimum varies 1:1 with GND, VCMR max varies 1:1 with VCC. The VCMR range is referenced to the most positive side of the differential
input signal.
http://onsemi.com
5
NB6L72M
Table 6. AC CHARACTERISTICS VCC = 2.375 V to 3.63 V, GND = 0 V, or VCC = 0 V, GND = -2.375 V to -3.63 V,
TA = -40°C to +85°C; (Note 10)
Symbol
Characteristic
VOUTPP
Output Voltage Amplitude (@ VINPPmin)
(Note 15) (See Figure 15)
fDATA
Maximum Operating Data Rate
tPLH,
tPHL
Propagation Delay (@0.5GHz)
tSKEW
Duty Cycle Skew (Note 11)
Within Device Skew
Device to Device Skew (Note 12)
fin ≤ 3 GHz
Min
Typ
250
380
Max
mV
3
Dn to Qn
SELn to Qn
fin ≤ 3.0 GHz
tDC
Output Clock Duty Cycle
(Reference Duty Cycle = 50%)
tJITTER
RMS Random Clock Jitter (Note 13)
Peak-to-Peak Data Dependent Jitter
(Note 14)
VINPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
tr, tf
Output Rise/Fall Times @ 0.5 GHz, (20% - 80%),
230
40
fin ≤ 3.0 GHz
fDATA = 2.5 Gb/s
fDATA = 3.0 Gb/s
Gb/s
360
480
ps
20
25
85
ps
6.0
50
60
%
0.2
5.0
8.0
0.5
15
25
ps
2800
mV
120
ps
150
Q, Q
Unit
65
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10. Measured by forcing VINPP (minimum) from a 50% duty cycle clock source. All loading with an external RL = 50 W to VCC. Input edge rates
40 ps (20% - 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw- and Tpw+ @ 0.5GHz.
12. Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13. Additive RMS jitter with 50% duty cycle clock signal.
14. Additive peak-to-peak data dependent jitter with input NRZ data at PRBS23.
15. Input and output voltage swing is a single-ended measurement operating in differential mode.
http://onsemi.com
6
NB6L72M
VTD
VCC
50 W
RC
RC
D
I
D
50 W
VTD
Figure 3. Input Structure
VCC
Vthmax
D
VIH
VIHmax
VILmax
Vth
VIH
Vth
VIL
Vth
VIL
Vthmin
D
VILmin
GND
Vth
Figure 4. Differential Input Driven
Single-Ended
Figure 5. Vth Diagram
D
D
D
D
Figure 6. Differential Inputs
Driven Differentially
VCC
VIHmin
VID = |VIHD(D) - VILD(D)|
VIHD
VILD
Figure 7. Differential Inputs Driven Differentially
VIHD(MAX)
D
VILD(MAX)
VINPP = VIH(D) - VIL(D)
D
VCMR
VIHD
VID = VIHD - VILD
Q
VILD
VOUTPP = VOH(Q) - VOL(Q)
Q
VIHD(MIN)
GND
tPD
tPD
VILD(MIN)
Figure 8. VCMR Diagram
Figure 9. AC Reference Measurement
http://onsemi.com
7
NB6L72M
VCC
VCC
VCC
NB6L72M
ZO = 50 W
LVPECL
Driver
VCC
ZO = 50 W
D
50 W
VT = VCC - 2 V
ZO = 50 W
LVDS
Driver
50 W
NB6L72M
D
50 W
VT = Open
ZO = 50 W
D
50 W
D
GND
GND
GND
GND
Figure 10. LVPECL Interface
Figure 11. LVDS Interface
VCC
VCC
NB6L72M
ZO = 50 W
CML
Driver
D
50 W
VT = VCC
ZO = 50 W
50 W
D
GND
GND
Figure 12. Standard 50 W Load CML Interface
VCC
VCC
ZO = 50 W
Differential
Driver
VCC
VCC
NB6L72M
ZO = 50 W
D
50 W
VT = VREFAC*
ZO = 50 W
Single-Ended
Driver
50 W
D
GND
NB6L72M
D
50 W
VT = VREFAC*
50 W
D
GND
GND
Figure 13. Capacitor-Coupled
Differential Interface
(VT Connected to VREFAC)
GND
Figure 14. Capacitor-Coupled
Single-Ended Interface
(VT Connected to VREFAC)
*VREFAC bypassed to ground with a 0.01 mF capacitor
http://onsemi.com
8
(Open)
NB6L72M
VOUTPP OUTPUT VOLTAGE AMPLITUDE (mV)
(TYPICAL)
VCC
400
300
50 W
50 W
Q
Q
200
100
0
0
1
2
16 mA
3
fout, CLOCK OUTPUT FREQUENCY (GHz)
GND
Figure 15. Output Voltage Amplitude (VOUTPP) versus Output
Frequency at Ambient Temperature (Typical)
Figure 16. CML Output Structure
VTT
50 W
Z = 50 W
DUT
Driver
Device
50 W
Q
D
Receiver
Device
Z = 50 W
Q
D
Figure 17. Typical CML Termination for Output Driver and Device Evaluation
ORDERING INFORMATION
Package
Shipping†
NB6L72MMNG
QFN-16
(Pb-free)
123 Units / Rail
NB6L72MMNR2G
QFN-16
(Pb-free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
9
NB6L72M
PACKAGE DIMENSIONS
D
PIN 1
LOCATION
16 PIN QFN
MN SUFFIX
CASE 485G-01
ISSUE C
A
B
ÇÇ
ÇÇ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. Lmax CONDITION CAN NOT VIOLATE 0.2 MM
MINIMUM SPACING BETWEEN LEAD TIP
AND FLAG
E
0.15 C
TOP VIEW
0.15 C
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
(A3)
0.10 C
A
16 X
SEATING
PLANE
0.08 C
SIDE VIEW
A1
C
SOLDERING FOOTPRINT*
D2
16X
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
1.65
1.85
3.00 BSC
1.65
1.85
0.50 BSC
0.18 TYP
0.30
0.50
e
L
5
NOTE 5
EXPOSED PAD
8
4
0.575
0.022
9
3.25
0.128
0.30
0.012
EXPOSED PAD
E2
16X
K
12
1
16
16X
13
1.50
0.059
3.25
0.128
b
0.10 C A B
0.05 C
e
BOTTOM VIEW
NOTE 3
0.50
0.02
0.30
0.012
SCALE 10:1
mm Ǔ
ǒinches
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ECLinPS MAX is a trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800-282-9855 Toll Free
USA/Canada
ON Semiconductor Website: http://onsemi.com
Order Literature: http://www.onsemi.com/litorder
Japan: ON Semiconductor, Japan Customer Focus Center
2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051
Phone: 81-3-5773-3850
http://onsemi.com
10
For additional information, please contact your
local Sales Representative.
NB6L72M/D