INTERSIL ISL54055IRUZ-T

ISL54054, ISL54055
®
Data Sheet
March 21, 2007
Ultra Low ON-Resistance, Low Voltage,
Single Supply, Single SPST/1:2
Distribution Analog Switch
The Intersil ISL54054 and ISL54055 devices consist of low
ON-resistance, low voltage, bi-directional SPST analog
switches designed to operate from a single +1.8V to +5.5V
supply. These devices have an unique architecture. They
have two signal pins (pin 1 and pin 3) that are
simultaneously connected or disconnected to a common pin
(pin 4) under the control of a single logic control pin (pin 6).
The ISL54054 switches are OFF when the logic is low and
ON when the logic is high. The ISL54055 switches are ON
when the logic is low and OFF when the logic is high. This
architecture allows these devices to be used as a single
SPST switch or as a distribution switch to distribute a single
source to two different loads.
SPST operation is achieved by using one of the signal pins
while floating the other signal pin or by externally connecting
the two signal pins together. When both signal pins are tied
together, the rON of the SPST is reduced by half, from 1Ω to
0.5Ω (when operated with a 5V supply).
Targeted applications include battery powered equipment
that benefit from low rON resistance, excellent rON flatness,
and fast switching speeds (tON = 12ns, tOFF = 12ns). The
digital logic input is 1.8V logic compatible when using a
single 2.7V to +3.6V supply and TTL compatible when the
supply is > +3.6V.
The ISL54054 and the ISL54055 are offered in a 6 Ld
1.2mmx1.0mmx0.5mm μTDFN package, alleviating board
space limitations.
The ISL54054 has two normally open (NO) switches and the
ISL54055 has two normally closed (NC) switches.
TABLE 1. FEATURES AT A GLANCE
ISL54054
ISL54055
Number of Switches
1
1
SW
NO
NC
1.8V rON
1.1Ω
1.1Ω
1.8V tON/tOFF
115ns/90ns
115ns/90ns
3V rON
0.51Ω
0.51Ω
3V tON/tOFF
22ns/17ns
22ns/17ns
5V rON
0.34Ω
0.34Ω
5V tON/tOFF
12ns/12ns
12ns/12ns
FN6461.0
Features
• ON-resistance (rON) (Signal Pins Connected)
- VCC = +5.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.34Ω
- VCC = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.51Ω
- VCC = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1Ω
• rON flatness (+4.5V Supply) . . . . . . . . . . . . . . . . . . . . . 0.13Ω
• Single supply operation . . . . . . . . . . . . . . . . . +1.8V to +5.5V
• Fast switching action (+4.5V Supply)
- tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
- tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12ns
• ESD HBM rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >6kV
• 1.8V logic compatible (+3V supply)
• Available in 6 lead μTDFN Package
• Pb-free plus anneal available (RoHS compliant)
Applications
• Battery powered, handheld and portable equipment
- Cellular/mobile phones
- Pagers
- Laptops, notebooks, palmtops
• Portable test and measurement
• Medical equipment
• Audio and video switching
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Ordering Information
PART
NUMBER
(Note)
PART
MARKING
TEMP.
RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL54054IRUZ-T D
-40 to +85 6 Ld μTDFN
L6.1.2x1.0A
Tape and Reel
ISL54055IRUZ-T E
-40 to +85 6 Ld μTDFN
L6.1.2x1.0A
Tape and Reel
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and compatible with
both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
6 Ld μTDFN
Packages
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL54054, ISL54055
Pinouts
(Note 1)
ISL54055
(6 LD μTDFN)
TOP VIEW
ISL54054
(6 LD μTDFN)
TOP VIEW
NO
1
6
IN
NC
1
6
IN
GND
2
5
V+
GND
2
5
V+
NO
3
4
COM
NC
3
4
COM
NOTE:
1. Switches Shown for Logic “0” Input.
Truth Table
Pin Descriptions
LOGIC
ISL54054
Both NO Switches
ISL54055
Both NC Switches
0
Off
On
1
On
Off
PIN
V+
NOTE:
Logic “0” ≤0.5V. Logic “1” ≥1.4V with a 3V supply.
System Power Supply Input (+1.8V to +5.5V)
GND
Ground Connection
IN
Digital Control Input
COM
2
FUNCTION
Analog Switch Common Pin
NO
Analog Switch Normally Open Pin
NC
Analog Switch Normally Closed Pin
FN6461.0
March 21, 2007
ISL54054, ISL54055
Absolute Maximum Ratings
Thermal Information
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 6.0V
Input Voltages
NO, NC, IN (Note 2). . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Output Voltages
COM (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V)
Continuous Current NO, NC, or COM . . . . . . . . . . . . . . . . . ±300mA
Peak Current NO, NC, or COM
(Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . . .±600mA
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . .>6kV
Machine Model (Per EIAJ ED-4701 Method C-111) . . . . . . .>200V
Charged Device Model (Per EOS/ESD DS5.3, 4/14/93) . .>1000V
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
6 Ld μTDFN Package . . . . . . . . . . . . . . . . . . . . . . .
175
Maximum Junction Temperature (Plastic Package). . . . . . . +150°C
Maximum Storage Temperature Range . . . . . . . . . . . -65°C to +150°C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300°C
(Lead Tips Only)
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
V+ (Positive DC Supply Voltage) . . . . . . . . . . . . . . . . . 1.8V to 5.5V
Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to V+
VIN (Digital Logic Input Voltage (IN). . . . . . . . . . . . . . . . . . 0V to V+
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
2. Signals on NC, NO, IN, or COM exceeding V+ or GND are clamped by internal diodes. Limit forward diode current to maximum current ratings.
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
(Nx Inputs Connected)
V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
25
-
0.36
-
Ω
Full
-
0.49
-
Ω
rON Flatness, rFLAT(ON)
(Nx Inputs Connected)
V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
25
-
0.12
-
Ω
Full
-
0.13
-
Ω
ON-Resistance, rON
(Single Nx Input)
V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
25
-
0.85
-
Ω
Full
-
1.1
-
Ω
rON Flatness, rFLAT(ON)
(Single Nx Input)
V+ = 4.5V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
25
-
0.25
-
Ω
Full
-
0.25
-
Ω
NO or NC OFF Leakage Current,
INO(OFF) or INC(OFF)
V+ = 5.5V, VCOM = 0.3V, 5V, VNO or VNC = 5V, 0.3V
25
-10
5
10
nA
Full
-150
-
150
nA
COM ON Leakage Current,
ICOM(ON)
V+ = 5.5V, VCOM = 0.3V, 5V, or VNO or VNC = 0.3V, 5V,
or floating
25
-20
9
20
nA
Full
-300
-
300
nA
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1)
25
-
12
-
ns
Full
-
15
-
ns
25
-
12
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
Turn-OFF Time, tOFF
V+ = 4.5V, VNO or VNC = 3.0V, RL = 50Ω, CL = 35pF
(See Figure 1)
Full
-
15
-
ns
Charge Injection, Q
VG = 0V, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
71
-
pC
OFF Isolation
(Nx Inputs Connected)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 3)
25
-
74
-
dB
OFF Isolation
(Single Nx Input)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 3)
25
-
83
-
dB
3
FN6461.0
March 21, 2007
ISL54054, ISL54055
Electrical Specifications - 5V Supply
PARAMETER
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VINH = 2.4V, VINL = 0.8V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
-3dB Bandwidth
(Nx Inputs Connected)
RL = 50Ω
25
-
72
-
MHz
-3dB Bandwidth
(Single Nx Input)
RL = 50Ω
25
-
138
-
MHz
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
(Nx Inputs Connected)
25
-
30
-
pF
COM ON Capacitance, CCOM(ON)
(Nx Inputs Connected)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
62
-
pF
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
(Single Nx Input)
25
-
16
-
pF
COM ON Capacitance, CCOM(ON)
(Single Nx Input)
25
-
89
-
pF
Full
1.8
-
5.5
V
25
-
-
0.5
μA
Full
-
-
1.0
μA
Full
-
-
0.8
V
Full
2.4
-
-
V
Full
-1
-
1
μA
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
POWER SUPPLY CHARACTERISTICS
Power Supply Range
Positive Supply Current, I+
V+ = 5.5V, VIN = 0V or V+
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 5.5V, VIN = 0V or V+
Electrical Specifications - 3V Supply
PARAMETER
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
TYP
(NOTE 5)
MAX
UNITS
Full
0
-
V+
V
25
-
0.57
0.65
Ω
Full
-
0.73
1.0
Ω
25
-
0.2
0.4
Ω
Full
-
0.2
0.5
Ω
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
(Nx Inputs Connected)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
rON Flatness, rFLAT(ON)
(Nx Inputs Connected)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
ON-Resistance, rON
(Single Nx Input)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(See Figure 4)
rON Flatness, rFLAT(ON)
(Single Nx Input)
V+ = 2.7V, ICOM = 100mA, VNO or VNC = 0V to V+,
(Note 7)
25
-
1.3
1.7
Ω
Full
-
1.6
2.0
Ω
25
-
0.4
0.6
Ω
Full
-
0.4
0.7
Ω
25
-
22
-
ns
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1)
Turn-OFF Time, tOFF
V+ = 2.7V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1)
Full
-
25
-
ns
25
-
17
-
ns
Full
-
20
-
ns
Charge Injection, Q
VG = 0V, RG = 0Ω, CL = 1.0nF (See Figure 2)
25
-
42
-
pC
OFF Isolation
(Nx Inputs Connected)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 3)
25
-
74
-
dB
OFF Isolation
(Single Nx Input)
RL = 50Ω, CL = 5pF, f = 100kHz, VCOM = 1VRMS
(See Figure 3)
25
-
83
-
dB
25
-
30
-
pF
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
(Nx Inputs Connected)
4
FN6461.0
March 21, 2007
ISL54054, ISL54055
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.6V, GND = 0V, VINH = 1.4V, VINL = 0.5V (Notes 4, 6),
Unless Otherwise Specified (Continued)
TEMP
(°C)
(NOTE 5)
MIN
TYP
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
25
-
62
-
pF
NO or NC OFF Capacitance, COFF f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
(Single Nx Input)
25
-
16
-
pF
COM ON Capacitance, CCOM(ON)
(Single Nx Input)
25
-
89
-
pF
Full
-
-
0.5
V
Full
1.4
-
-
V
Full
-1
-
1
μA
PARAMETER
TEST CONDITIONS
COM ON Capacitance, CCOM(ON)
(Nx Inputs Connected)
f = 1MHz, VNO or VNC = VCOM = 0V
(See Figure 5)
(NOTE 5)
MAX
UNITS
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VINL
Input Voltage High, VINH
Input Current, IINH, IINL
V+ = 3.6V, VIN = 0V or V+
Electrical Specifications - 1.8V Supply
PARAMETER
Test Conditions: V+ = +1.8V, GND = 0V, VINH = 1.8V, VINL = 0V (Notes 4, 6),
Unless Otherwise Specified
TEST CONDITIONS
TEMP
(°C)
(NOTE 5)
MIN
Full
0
-
V+
V
25
-
1.1
-
Ω
TYP
(NOTE 5)
MAX
UNITS
ANALOG SWITCH CHARACTERISTICS
Analog Signal Range, VANALOG
ON-Resistance, rON
(Nx Inputs Connected)
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+,
Pins 1 and 3 connected, (See Figure 4)
ON-Resistance, rON
(Single Nx Input)
V+ = 1.8V, ICOM = 100mA, VNO or VNC = 0V to V+
(See Figure 4)
Full
-
1.3
-
Ω
25
-
2.3
-
Ω
Full
-
2.53
-
Ω
25
-
115
-
ns
Full
DYNAMIC CHARACTERISTICS
Turn-ON Time, tON
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1)
-
246
-
ns
Turn-OFF Time, tOFF
V+ = 1.8V, VNO or VNC = 1.5V, RL = 50Ω, CL = 35pF
(See Figure 1)
25
-
90
-
ns
Full
-
192
-
ns
VG = 0V, RG = 0Ω,CL = 1.0nF (See Figure 2)
25
-
22
-
pC
Charge Injection, Q
NOTES:
4. VIN = input voltage to perform proper function.
5. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
6. Parts are 100% tested at +25°C. Limits across the full temperature range are guaranteed by design and correlation.
7. Flatness is defined as the difference between maximum and minimum value of on-resistance over the specified analog signal range.
5
FN6461.0
March 21, 2007
ISL54054, ISL54055
Test Circuits and Waveforms
VINH
LOGIC
INPUT
V+
tr < 20ns
tf < 20ns
50%
C
VINL
tOFF
COM
VOUT
IN
90%
SWITCH
OUTPUT
VOUT
NO or NC
SWITCH
INPUT
SWITCH
INPUT VNO
90%
0V
LOGIC
INPUT
CL
35pF
RL
50Ω
GND
tON
Logic input waveform is inverted for switches that have the opposite
logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
RL
V OUT = V (NO or NC) ---------------------------R L + r ( ON )
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
V+
SWITCH
OUTPUT
VOUT
ΔVOUT
RG
C
VOUT
COM
NO or NC
VINH
ON
ON
LOGIC
INPUT
VG
OFF
GND
IN
CL
VINL
LOGIC
INPUT
Q = ΔVOUT x CL
FIGURE 2A. MEASUREMENT POINTS
FIGURE 2B. TEST CIRCUIT
FIGURE 2. CHARGE INJECTION
V+
V+
C
C
rON = V1/100mA
SIGNAL
GENERATOR
NO or NC
NO or NC
VNX
100mA
IN
0V or V+
VINL or VINH
COM
COM
ANALYZER
IN
V1
GND
GND
RL
FIGURE 3. OFF ISOLATION TEST CIRCUIT
6
FIGURE 4. rON TEST CIRCUIT
FN6461.0
March 21, 2007
ISL54054, ISL54055
Test Circuits and Waveforms (Continued)
V+
C
NO or NC
IN
VINL or VINH
IMPEDANCE
ANALYZER
COM
GND
FIGURE 5. CAPACITANCE TEST CIRCUIT
Detailed Description
The Intersil ISL54054 and ISL54055 devices consist of low
ON-resistance, low voltage, bi-directional analog switches
designed to operate from a single +1.8V to +5.5V supply.
With a single supply of 5V the typical on-resistance is only
0.34Ω, with a typical turn-on and turn-off time of: tON = 12ns,
tOFF = 12ns. The devices are especially well suited for
portable battery powered equipment due to its low operating
supply voltage (1.8V), low power consumption (5.5μW), low
leakage currents (300nA max) and the tiny μTDFN package.
These devices have an unique architecture. They have two
signal pins (pin 1 and pin 3) that are simultaneously
connected or disconnected to a single common pin (pin 4)
under the control of a single logic control pin (pin 6). The
ISL54054 switches are OFF when the logic is low and ON
when the logic is high. The ISL54055 are ON when the logic
is low and OFF when the logic is high. This architecture
allows these devices to be used as a single SPST switch or
as a distribution switch to distribute a single source to two
different loads.
SPST operation is achieved by using one of the Nx signal
pins while floating the other Nx signal pin or by externally
connecting the two Nx signal pins together. When both
signal pins are tied together, the rON of the SPST is reduced
by half, from 1Ω to 0.5Ω (when operated with a 5V supply).
The ISL54054 is a normally open (NO) SPST analog switch.
The ISL54055 is a normally closed (NC) SPST analog
switch.
Supply Sequencing and Overvoltage Protection
conditions cannot be guaranteed, then one of the following
two protection methods should be employed.
Logic inputs can easily be protected by adding a 1kΩ
resistor in series with the input (see Figure 6). The resistor
limits the input current below the threshold that produces
permanent damage, and the sub-microamp input current
produces an insignificant voltage drop during normal
operation.
This method is not acceptable for the signal path inputs.
Adding a series resistor to the switch input defeats the
purpose of using a low rON switch. Connecting schottky
diodes to the signal pins (as shown in Figure 6) will shunt the
fault current to the supply or to ground, thereby protecting
the switch. These schottky diodes must be sized to handle
the expected fault current.
OPTIONAL
SCHOTTKY
DIODE
V+
OPTIONAL
PROTECTION
RESISTOR
INX
VNX
VCOM
GND
OPTIONAL
SCHOTTKY
DIODE
FIGURE 6. OVERVOLTAGE PROTECTION
With any CMOS device, proper power supply sequencing is
required to protect the device from excessive input currents,
which might permanently damage the IC. All I/O pins contain
ESD protection diodes from the pin to V+ and to GND (see
Figure 6). To prevent forward biasing these diodes, V+ must
be applied before any input signals, and the input signal
voltages must remain between V+ and GND. If these
7
FN6461.0
March 21, 2007
ISL54054, ISL54055
Power-Supply Considerations
High-Frequency Performance
The construction of the ISL54054 and the ISL54055 is
typical of most single supply CMOS analog switches in that
they have two supply pins: V+ and GND. V+ and GND drive
the internal CMOS switches and set their analog voltage
limits. Unlike switches with a 4.5V maximum supply voltage,
the ISL54054 and the ISL54055’s 5.5V maximum supply
voltage provides plenty of room for the 10% tolerance of
4.5V supplies, as well as room for overshoot and noise
spikes.
In 50Ω systems, the ISL54054 and the ISL54055 have a 3dB bandwidth of 72MHz with Nx pins connected and
138MHz for a single Nx input (see Figure 20). The frequency
response is very consistent over a wide V+ range, and for
varying analog signal levels.
The minimum recommended supply voltage is 1.8V. It is
important to note that the input signal range, switching times,
and on-resistance degrade at lower supply voltages. Refer
to the electrical specification tables and Typical Performance
Curves on page for details.
V+ and GND also power the internal logic and level shiftier.
The level shiftier converts the input logic levels to switched
V+ and GND signals to drive the analog switch gate
terminals.
This family of switches cannot be operated with bipolar
supplies, because the input switching point becomes
negative in this configuration.
Logic-Level Thresholds
This switch family is 1.8V logic compatible (0.5V and 1.4V)
over a supply range of 2.5V to 5V (see Figure 19). At 5V the
VIH level is about 1.38V. This is still below the 1.8V CMOS
guaranteed high output minimum level of 1.4V, but noise
margin is reduced. At 1.8V operation the VIL level is around
0.1V and can only be used in 1.8V applications with minimal
ground bounce.
The digital input stages draw supply current whenever the
digital input voltage is not at one of the supply rails. Driving
the digital input signals from GND to V+ with a fast transition
time minimizes power dissipation.
An OFF switch acts like a capacitor and passes higher
frequencies with less attenuation, resulting in signal
feedthrough from a switch’s input to its output. Off isolation is
the resistance to this feedthrough. Figure 21 details the high
off isolation rejection provided by this family. At 100kHz, off
isolation in 50Ω systems is about 74dB with Nx pins
connected and 83dB with a single Nx input, decreasing
approximately 20dB per decade as frequency increases.
Higher load impedances decrease off isolation rejection due
to the voltage divider action of the switch OFF impedance
and the load impedance.
Leakage Considerations
Reverse ESD protection diodes are internally connected
between each analog-signal pin and both V+ and GND. One of
these diodes conducts if any analog signal exceeds V+ or
GND.
Virtually all the analog leakage current comes from the ESD
diodes to V+ or GND. Although the ESD diodes on a given
signal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by either
V+ or GND and the analog signal. This means their leakages
will vary as the signal varies. The difference in the two diode
leakages to the V+ and GND pins constitutes the analogsignal-path leakage current. All analog leakage current flows
between each pin and one of the supply terminals, not to the
other switch terminal. This is why both sides of a given
switch can show leakage currents of the same or opposite
polarity. There is no connection between the analog signal
paths and V+ or GND.
Typical Performance Curves TA = +25°C, Unless Otherwise Specified
1.4
1.2
V+ = 1.8V
ICOM = 100mA
ICOM = 100mA
1.1
1.2
1.0
0.9
1.0
rON (Ω)
rON (Ω)
V+ = 1.8V
0.8
0.7
0.6
+85°C
0.8
+25°C
0.6
0.5
V+ = 2.7V
-40°C
0.4
V+ = 3V
0.4
V+ = 4.5V
0.3
V+ = 5V
0.2
0
1
2
3
4
VCOM (V)
FIGURE 7. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE (NX PINS CONNECTED)
8
5
0.2
0
0.5
1.0
VCOM (V)
1.5
1.8
FIGURE 8. ON-RESISTANCE vs SWITCH VOLTAGE
(NX PINS CONNECTED)
FN6461.0
March 21, 2007
ISL54054, ISL54055
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
0.7
0.45
V+ = 3V
ICOM = 100mA
0.6
+85°C
V+ = 5V
ICOM = 100mA
0.35
+85°C
0.30
0.4
rON (Ω)
rON (Ω)
0.5
0.40
+25°C
0.25
+25°C
0.20
0.3
0.15
-40°C
0.2
0.10
0.1
0
0.5
1.0
1.5
2.0
2.5
0.05
3.0
-40°C
0
1
2
3
VCOM (V)
VCOM (V)
FIGURE 9. ON-RESISTANCE VS SWITCH VOLTAGE
(NX PINS CONNECTED)
4
5
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
(NX PINS CONNECTED)
3.0
2.3
V+ = 1.8V
ICOM = 100mA
ICOM = 100mA
2.1
2.5
1.9
V+ = 1.8V
rON (Ω)
rON (Ω)
1.7
1.5
1.3
1.1
2.0
+85°C
1.5
+25°C
V+ = 2.7V
-40°C
V+ = 3V
V+ = 4.5V
0.9
1.0
0.7
0.5
V+ = 5V
0
1
2
3
4
0.5 0
5
0.5
VCOM (V)
FIGURE 11. ON-RESISTANCE vs SUPPLY VOLTAGE vs
SWITCH VOLTAGE (SINGLE NX INPUT)
1.5
1.8
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
1.1
1.6
V+ = 3V
ICOM = 100mA
1.4
1.0
VCOM (V)
V+ = 5V
ICOM = 100mA
1.0
0.9
+85°C
0.8
rON (Ω)
rON (Ω)
1.2
1.0
+25°C
+85°C
0.7
+25°C
0.6
0.8
0.5
-40°C
0.6
0.4
0.4
0
0.5
1.0
1.5
VCOM (V)
2.0
2.5
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
9
3.0
0.3
-40°C
0
1
2
3
VCOM (V)
4
5
FIGURE 14. ON-RESISTANCE vs SWITCH VOLTAGE
(SINGLE NX INPUT)
FN6461.0
March 21, 2007
ISL54054, ISL54055
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
200
30
180
-40°C
160
25
tOFF (ns)
tON (ns)
140
20
+85°C
15
120
100 +25°C
80
+25°C
60
40
10
-40°C
5
1.5
2.0
2.5
+85°C
20
3.0
3.5
V+ (V)
4.0
4.5
5.0
0
1.5
5.5
FIGURE 15. TURN ON TIME vs SUPPLY VOLTAGE (ISL54054)
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
FIGURE 16. TURN OFF TIME vs SUPPLY VOLTAGE (ISL54054)
250
30
-40°C
200
25
150
20
tON (ns)
tOFF (ns)
+85°C
25°C
100
+25°C
15
-40°C
50
85°C
0
1.5
2.0
10
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5
1.5
5.5
FIGURE 17. TURN ON TIME vs SUPPLY VOLTAGE (ISL54055)
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
FIGURE 18. TURN OFF TIME vs SUPPLY VOLTAGE (ISL54055)
V+ = 5V
1.6
VINH AND VINL (V)
1.2
NORMALIZED GAIN (dB)
1.4
VINH
1.0
0.8
VINL
0.6
0.4
-3
NX PINS CONNECTED
-6
-9
0.2
0
1.5
SINGLE NX INPUT
0
RL = 50Ω
VIN = 0.2VP-P to 2.8VP-P
2.0
2.5
3.0
3.5
V+ (V)
4.0
4.5
5.0
5.5
FIGURE 19. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
10
0.1k
1M
10M
100M
FREQUENCY (Hz)
500M
FIGURE 20. FREQUENCY RESPONSE
FN6461.0
March 21, 2007
ISL54054, ISL54055
Typical Performance Curves TA = +25°C, Unless Otherwise Specified (Continued)
10
140
120
V+ = 5V
40
100
50
80
60
Q (pC)
OFF ISOLATION (dB)
V+ = 1.8V to 5.5V
20 RL = 50Ω
VIN = 1VP-P
30
Nx PINS CONNECTED
70
60
V+ = 3V
80
40
SINGLE Nx INPUT
90
20
100
110
1k
V+ = 1.8V
0
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 21. OFF ISOLATION
100M 500M
0
0.5
1.0
1.5
2.0 2.5 3.0
VCOM (V)
3.5
4.0
4.5
5.0
FIGURE 22. CHARGE INJECTION vs SWITCH VOLTAGE
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND
TRANSISTOR COUNT:
57
PROCESS:
Submicron CMOS
11
FN6461.0
March 21, 2007
ISL54054, ISL54055
Ultra Thin Dual Flat No-Lead Plastic Package (UTDFN)
A
E
L6.1.2x1.0A
B
6 LEAD ULTRA THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
MILLIMETERS
PIN 1
REFERENCE
2X
0.10 C
2X
D
0.10 C
SYMBOL
MIN
NOMINAL
MAX
NOTES
A
0.45
0.50
0.55
-
A1
-
-
0.05
-
A
0.08 C
0.15
0.20
0.25
5
D
0.95
1.00
1.05
-
E
1.15
1.20
1.25
-
0.40 BSC
e
A1 A3
SIDE VIEW
C
SEATING
PLANE
4X
e
DETAIL B
1
5X
L
3
-
b
DETAIL A
0.10 C
7X
0.127 REF
A3
TOP VIEW
-
L
0.30
0.35
0.40
-
L1
0.40
0.45
0.50
-
N
6
2
Ne
3
3
θ
0
-
12
4
L1
Rev. 2 8/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
6
4
BOTTOM VIEW
b 6X
0.10 C A B
0.05 C NOTE 3
2. N is the number of terminals.
3. Ne refers to the number of terminals on E side.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
0.1x45°
CHAMFER
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
A3
A1
DETAIL A
DETAIL B PIN 1 LEAD
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.
1.00
1.40
0.20
0.30
0.45
0.35
0.20
0.40
LAND PATTERN
10
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12
FN6461.0
March 21, 2007