74LVC540A D

74LVC540A
Low-Voltage CMOS
Octal Buffer
Flow Through Pinout
With 5 V−Tolerant Inputs and Outputs
(3−State, Inverting)
The 74LVC540A is a high performance, inverting octal buffer
operating from a 1.2 to 3.6 V supply. This device is similar in function
to the MC74LCX240, while providing flow through architecture.
High impedance TTL compatible inputs significantly reduce current
loading to input drivers while TTL compatible outputs offer improved
switching noise performance. A VI specification of 5.5 V allows
74LVC540A inputs to be safely driven from 5 V devices. The
74LVC540A is suitable for memory address driving and all TTL level
bus oriented transceiver applications.
Current drive capability is 24 mA at the outputs. The Output Enable
(OE1, OE2) inputs, when HIGH, disables the outputs by placing them
in a HIGH Z condition.
Features
•
•
•
•
•
•
•
•
•
Designed for 1.2 to 3.6 V VCC Operation
5 V Tolerant − Interface Capability With 5 V TTL Logic
Supports Live Insertion and Withdrawal
IOFF Specification Guarantees High Impedance When VCC = 0 V
24 mA Output Sink and Source Capability
Near Zero Static Supply Current in All Three Logic States (10 mA)
Substantially Reduces System Power Requirements
Latchup Performance Exceeds 250 mA
ESD Performance:
♦ Human Body Model > 2000 V
♦ Machine Model > 200 V
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 0
1
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MARKING
DIAGRAMS
20
20
1
SOIC−20 WB
DW SUFFIX
CASE 751D
LVC540A
AWLYYWWG
1
20
20
LVC
540A
ALYW G
G
1
TSSOP−20
DT SUFFIX
CASE 948E
A
L, WL
Y, YY
W, WW
G or G
1
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 7 of this data sheet.
Publication Order Number:
74LVC540A/D
74LVC540A
OE1
OE2
VCC
OE2
O0
O1
O2
O3
O4
O5
O6
O7
20
19
18
17
16
15
14
13
12
11
1
19
D0
D1
D2
1
2
3
4
5
6
7
8
9
10
OE1
D0
D1
D2
D3
D4
D5
D6
D7
GND
D3
D4
Figure 1. Pinout: 20−Lead (Top View)
D5
PIN NAMES
D6
Pins
Function
OEn
Output Enable Inputs
Dn
Data Inputs
On
3−State Outputs
D7
18
3
17
4
16
5
15
6
14
7
13
8
12
9
11
O0
O1
O2
O3
O4
O5
O6
O7
Figure 2. Logic Diagram
TRUTH TABLE
Inputs
2
Outputs
OE1
OE2
Dn
On
L
L
L
H
L
L
H
L
X
H
X
Z
H
X
X
Z
H = High Voltage Level
L = Low Voltage Level
Z = High Impedance State
X = High or Low Voltage Level and Transitions are Acceptable
For ICC reasons, DO NOT FLOAT Inputs
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2
74LVC540A
MAXIMUM RATINGS
Symbol
VCC
Parameter
Value
DC Supply Voltage
Condition
Unit
−0.5 to +6.5
V
V
VI
DC Input Voltage
−0.5 ≤ VI ≤ +6.5
VO
DC Output Voltage
−0.5 ≤ VO ≤ +6.5
Output in 3−State
V
−0.5 ≤ VO ≤ VCC + 0.5
Output in HIGH or LOW State
(Note 1)
V
IIK
DC Input Diode Current
−50
VI < GND
mA
IOK
DC Output Diode Current
−50
VO < GND
mA
+50
VO > VCC
mA
IO
DC Output Source/Sink Current
±50
mA
ICC
DC Supply Current Per Supply Pin
±100
mA
IGND
DC Ground Current Per Ground Pin
±100
mA
TSTG
Storage Temperature Range
−65 to +150
°C
TL
Lead Temperature, 1 mm from Case for
10 Seconds
TL = 260
°C
TJ
Junction Temperature Under Bias
TJ = 135
°C
qJA
Thermal Resistance (Note 2)
SOIC = 65.8
TSSOP = 110.7
°C/W
MSL
ILATCHUP
Moisture Sensitivity
Level 1
±250
Latch−up Performance at VCC = 3.6 V
and 125°C (Note 3)
mA
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. IO absolute maximum rating must be observed.
2. Measured with minimum pad spacing on an FR4 board, using 10 mm−by−1 inch, 2 ounce copper trace no air flow.
3. Tested to EIA/JES078.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Parameter
Min
Supply Voltage
Operating
Functional
Typ
Max
V
1.65
1.2
3.6
3.6
VI
Input Voltage
0
5.5
VO
Output Voltage
HIGH or LOW State
3−State
0
0
VCC
5.5
IOH
IOL
TA
Dt/DV
Units
V
V
HIGH Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
−24
−12
mA
LOW Level Output Current
VCC = 3.0 V − 3.6 V
VCC = 2.7 V − 3.0 V
24
12
mA
Operating Free−Air Temperature
Input Transition Rise or Fall Rate, VIN from 0.8 V to 2.0 V, VCC = 3.0 V
−40
+125
°C
0
10
ns/V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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3
74LVC540A
DC ELECTRICAL CHARACTERISTICS
−405C to +855C
Symbol
VIH
VIL
VOH
VOL
−405C to +1255C
Parameter
Conditions
Min
Typ
(Note 4)
Max
Min
Typ
(Note 4)
Max
Unit
HIGH−level input
voltage
VCC = 1.2 V
1.08
−
−
1.08
−
−
V
VCC = 1.65 V to 1.95 V
0.65 x
VCC
−
−
0.65 x
VCC
−
−
VCC = 2.3 V to 2.7 V
1.7
−
−
1.7
−
−
VCC = 2.7 V to 3.6 V
2.0
−
−
2.0
−
−
VCC = 1.2 V
−
−
0.12
−
−
0.12
VCC = 1.65 V to 1.95 V
−
−
0.35 x
VCC
−
−
0.35 x
VCC
VCC = 2.3 V to 2.7 V
−
−
0.7
−
−
0.7
VCC = 2.7 V to 3.6 V
−
−
0.8
−
−
0.8
LOW−level input
voltage
HIGH−level output
voltage
LOW−level output
voltage
V
V
VI = VIH or VIL
IO = −100 mA;
VCC = 1.65 V to 3.6 V
VCC −
0.2
−
−
VCC −
0.3
−
−
IO = −4 mA; VCC = 1.65 V
1.2
−
−
1.05
−
−
IO = −8 mA; VCC = 2.3 V
1.8
−
−
1.65
−
−
IO = −12 mA; VCC = 2.7 V
2.2
−
−
2.05
−
−
IO = −18 mA; VCC = 3.0 V
2.4
−
−
2.25
−
−
IO = −24 mA; VCC = 3.0 V
2.2
−
−
2.0
−
−
V
VI = VIH or VIL
IO = 100 mA;
VCC = 1.65 V to 3.6 V
−
−
0.2
−
−
0.3
IO = 4 mA; VCC = 1.65 V
−
−
0.45
−
−
0.65
IO = 8 mA; VCC = 2.3 V
−
−
0.6
−
−
0.8
IO = 12 mA; VCC = 2.7 V
−
−
0.4
−
−
0.6
IO = −24 mA; VCC = 3.0 V
−
−
0.55
−
−
0.8
VI = 5.5V or GND VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOZ
OFF−state output
current
VI = VIH or VIL;
VO = 5.5 V or GND; VCC = 3.6 V
−
±0.1
±5
−
±0.1
±20
mA
IOFF
Power−off leakage
current
VI or VO = 5.5 V; VCC = 0.0 V
−
±0.1
±10
−
±0.1
±20
mA
ICC
Supply current
VI = VCC or GND; IO = 0 A;
VCC = 3.6 V
−
0.1
10
−
0.1
40
mA
Additional supply
current
per input pin;
VI = VCC − 0.6 V; IO = 0 A;
VCC = 2.7 V to 3.6 V
−
5
500
−
5
5000
mA
II
DICC
Input leakage current
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. All typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
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4
74LVC540A
AC ELECTRICAL CHARACTERISTICS (tR = tF = 2.5 ns)
−405C to +855C
Symbol
tpd
ten
tdis
tsk(0)
Parameter
Propagation Delay (Note 6)
nDn to nOn
Enable Time (Note 7)
nOE to nOn
Disable Time (Note 8)
nOE to nOn
−405C to +1255C
Conditions
Min
Typ5
Max
Unit
VCC = 1.2 V
−
18.0
−
−
−
−
ns
VCC = 1.65 V to 1.95 V
1.0
−
16.4
1.0
−
16.4
VCC = 2.3 V to 2.7 V
1.0
−
7.8
1.0
−
7.8
VCC = 2.7 V
1.0
−
7.1
1.0
−
7.1
VCC = 3.0 V to 3.6 V
1.0
−
5.3
1.0
−
5.3
VCC = 1.2 V
−
20.0
−
−
−
−
VCC = 1.65 V to 1.95 V
1.0
−
16.5
1.0
−
16.5
VCC = 2.3 V to 2.7 V
1.0
−
10.5
1.0
−
10.5
VCC = 2.7 V
1.0
−
8.0
1.0
−
8.0
VCC = 3.0 V to 3.6 V
1.0
−
6.6
1.0
−
6.6
VCC = 1.2 V
−
18.0
−
−
−
−
VCC = 1.65 V to 1.95 V
1.0
−
15.9
1.0
−
15.9
VCC = 2.3 V to 2.7 V
1.0
−
9.0
1.0
−
9.0
VCC = 2.7 V
1.0
−
8.2
1.0
−
8.2
VCC = 3.0 V to 3.6 V
1.0
−
7.4
1.0
−
7.4
−
−
1.0
−
−
1.5
Output Skew Time (Note 9)
Max
Min
Typ5
ns
ns
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Typical values are measured at TA = 25°C and VCC = 3.3 V, unless stated otherwise.
6. tpd is the same as tPLH and tPHL.
7. ten is the same as tPZL and tPZH.
8. tdis is the same as tPLZ and tPHZ.
9. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
DYNAMIC SWITCHING CHARACTERISTICS
TA = +25°C
Min
Typ
Max
Symbol
Characteristic
Condition
Unit
VOLP
Dynamic LOW Peak Voltage (Note 10)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
0.8
0.6
V
VOLV
Dynamic LOW Valley Voltage (Note
10)
VCC = 3.3 V, CL = 50 pF, VIH = 3.3 V, VIL = 0 V
VCC = 2.5 V, CL = 30 pF, VIH = 2.5 V, VIL = 0 V
−0.8
−0.6
V
10. Number of outputs defined as “n”. Measured with “n−1” outputs switching from HIGH−to−LOW or LOW−to−HIGH. The remaining output is
measured in the LOW state.
CAPACITIVE CHARACTERISTICS
Symbol
CIN
COUT
CPD
Parameter
Condition
Typical
Unit
Input Capacitance
VCC = 3.3 V, VI = 0 V or VCC
5.0
pF
Output Capacitance
VCC = 3.3 V, VI = 0 V or VCC
7.0
pF
Power Dissipation Capacitance
(Note 11)
pF
Per input; VI = GND or VCC
VCC = 1.65 V to 1.95 V
7.7
VCC = 2.3 V to 2.7 V
11.3
VCC = 3.0 V to 3.6 V
14.4
11. CPD is used to determine the dynamic power dissipation (PD in mW).
PD = CPD * VCC2 x fi * N + S (CL x VCC2 x fo) where:
fi = input frequency in MHz; fo = output frequency in MHz
CL = output load capacitance in pF VCC = supply voltage in Volts
N = number of outputs switching
S(CL * VCC2 x fo) = sum of the outputs.
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5
74LVC540A
2.7 V
Dn
1.5 V
1.5 V
0V
tPHL
tPLH
VOH
1.5 V
On
1.5 V
VOL
WAVEFORM 1 - PROPAGATION DELAYS
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
2.7 V
1.5 V
OEn
0V
tPZH
tPHZ
VCC
VOH - 0.3 V
1.5 V
On
≈0V
tPZL
tPLZ
≈ 3.0 V
1.5 V
On
VOL + 0.3 V
GND
WAVEFORM 2 - OUTPUT ENABLE AND DISABLE TIMES
tR = tF = 2.5 ns, 10% to 90%; f = 1 MHz; tW = 500 ns
Figure 3. AC Waveforms
VCC
Symbol
3.3 V ± 0.3 V
2.7 V
Vmi
1.5 V
1.5 V
VCC/2
Vmo
1.5 V
1.5 V
VCC/2
VCC < 2.7 V
VHZ
VOL + 0.3 V
VOL + 0.3 V
VOL + 0.15 V
VLZ
VOH − 0.3 V
VOH − 0.3 V
VOH − 015 V
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6
74LVC540A
VCC
VI
VO
PULSE
GENERATOR
R1
DUT
RT
CL
VEXT
OPEN
GND
RL
CL includes jig and probe capacitance
RT = ZOUT of pulse generator (typically 50 W)
R1 = RL
Supply Voltage
Input
Load
VEXT
VCC (V)
VI
tr, tf
CL
RL
tPLH, tPHL
tPLZ, tPZL
tPHZ, tPZH
1.2
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
1.65 − 1.95
VCC
≤ 2 ns
30 pF
1 kW
Open
2 x VCC
GND
2.3 − 2.7
VCC
≤ 2 ns
30 pF
500 W
Open
2 x VCC
GND
2.7
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
3 − 3.6
2.7 V
≤ 2.5 ns
50 pF
500 W
Open
2 x VCC
GND
Figure 4. Test Circuit
ORDERING INFORMATION
Package
Shipping†
74LVC540ADWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
74LVC540ADTR2G
TSSOP−20
(Pb−Free)
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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7
74LVC540A
PACKAGE DIMENSIONS
TSSOP−20
CASE 948E−02
ISSUE C
20X
0.15 (0.006) T U
2X
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
K
K1
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
L
SECTION N−N
−U−
PIN 1
IDENT
0.25 (0.010)
N
1
10
M
0.15 (0.006) T U
S
A
−V−
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
N
F
DETAIL E
−W−
C
G
D
H
DETAIL E
0.100 (0.004)
−T− SEATING
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
PLANE
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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8
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
74LVC540A
PACKAGE DIMENSIONS
SOIC−20 WB
CASE 751D−05
ISSUE G
q
A
20
X 45 _
h
H
M
E
0.25
10X
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
11
B
M
D
1
10
20X
B
B
0.25
M
T A
S
B
S
L
A
18X
e
A1
SEATING
PLANE
C
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
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9
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For additional information, please contact your local
Sales Representative
74LVC540A/D
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