AK5381VT

ASAHI KASEI
[AK5381]
AK5381
24Bit 96kHz ∆Σ ADC
GENERAL DESCRIPTION
The AK5381 is a stereo A/D Converter with wide sampling rate of 4kHz ∼ 96kHz and is suitable for
High-end audio system. The AK5381 achieves high accuracy and low cost by using Enhanced dual bit ∆Σ
techniques. The AK5381 requires no external components because the analog inputs are single-ended.
The audio interface has two formats (MSB justified, I2S) and can correspond to many systems like music
instrument and AV receiver.
FEATURES
† Stereo ∆Σ ADC
† On-Chip Digital Anti-Alias Filtering
† Single-ended Input
† Digital HPF for DC-Offset cancel
† S/(N+D): [email protected] for 48kHz
† DR:
[email protected] for 48kHz
† S/N:
[email protected] for 48kHz
† Sampling Rate Ranging from 4kHz to 96kHz
† Master Clock:
256fs/384fs/512fs/768fs (∼ 48kHz)
256fs/384fs
(∼ 96kHz)
† Audio Interface: Master or Slave Mode selectable
† Input level: TTL/CMOS selectable
AK5381 does not support TTL level mode at fs=48kHz to 96kHz.
† Output format: 24bit MSB justified / I2S selectable
† Power Supply: 4.5 ∼ 5.5V (VA)
2.7 ∼ 5.5V (VD at 48kHz)
3.0 ∼ 5.5V (VD at 96kHz)
† Ta = −40 ∼ 85°C (VT), −20 ∼ 85°C (ET)
† Small 16pin TSSOP Package
† AK5380 Pin-compatible
VA AGND
VD DGND
MCLK
Clock Divider
AINL
AINR
VCOM
∆Σ
Modulator
Decimation
Filter
∆Σ
Modulator
Decimation
Filter
LRCK
SCLK
Serial I/O
Interface
Voltage Reference
CKS2 CKS1 CKS0
PDN
MS0200-E-02
SDTO
DIF
2006/01
-1-
ASAHI KASEI
[AK5381]
„ Ordering Guide
AK5381ET
AK5381VT
AKD5381
−20 ∼ +85°C
16pin TSSOP (0.65mm pitch)
−40 ∼ +85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK5381
„ Pin Layout
AINR
1
16
CKS0
AINL
2
15
CKS2
CKS1
3
14
DIF
VCOM
4
13
PDN
AGND
5
12
SCLK
VA
6
11
MCLK
VD
7
10
LRCK
DGND
8
9
SDTO
Top View
„ Compatibility with AK5380
Master Mode
HPF OFF
TTL Level Mode
[email protected] Level Mode
VD (Digital Supply)
Pin #3
Pin #15
Pin #16
AK5380
Not Available
Not Available
4kHz to 96kHz
2.2V
4.5 to [email protected]=96kHz
NC
TTL
TST
MS0200-E-02
AK5381
Available
Available
4kHz to 48kHz
2.4V
3.0 to [email protected]=96kHz
CKS1
CKS2
CKS0
2006/01
-2-
ASAHI KASEI
[AK5381]
PIN / FUNCTION
No.
I/O
Function
1
2
3
AINR
AINL
CKS1
Pin Name
I
I
I
4
VCOM
O
5
6
7
8
AGND
VA
VD
DGND
-
9
SDTO
O
10
LRCK
I/O
11
MCLK
I
12
SCLK
I/O
13
PDN
I
14
DIF
I
15
16
CKS2
CKS0
I
I
Rch Analog Input Pin
Lch Analog Input Pin
Mode Select 1 Pin
Common Voltage Output Pin, VA/2
Bias voltage of ADC input.
Analog Ground Pin
Analog Power Supply Pin, 4.5 ∼ 5.5V
Digital Power Supply Pin, 2.7 ∼ 5.5V(fs=4k ∼ 48kHz), 3.0 ∼ 5.5V(fs=48k ∼ 96kHz)
Digital Ground Pin
Audio Serial Data Output Pin
“L” Output at Power-down mode.
Output Channel Clock Pin
“L” Output in Master Mode at Power-down mode.
Master Clock Input Pin
Audio Serial Data Clock Pin
“L” Output in Master Mode at Power-down mode.
Power Down Mode Pin
“H”: Power up, “L”: Power down
Audio Interface Format Pin
“H” : 24bit I2S Compatible, “L” : 24bit MSB justified
Mode Select 2 Pin
Mode Select 0 Pin
Note: All digital input pins should not be left floating.
MS0200-E-02
2006/01
-3-
ASAHI KASEI
[AK5381]
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND=0V; Note 1)
Parameter
Symbol
Power Supplies:
Analog
VA
Digital
VD
|AGND – DGND|
(Note 1)
∆GND
Input Current, Any Pin Except Supplies
IIN
Analog Input Voltage (AINL, AINR, CKS1 pins)
VINA
Digital Input Voltage (All digital input pins except CKS1 pin)
VIND
Ambient Temperature (powered applied)
AK5381ET
Ta
AK5381VT
Ta
Storage Temperature
Tstg
min
−0.3
−0.3
−0.3
−0.3
−20
-40
−65
max
6.0
6.0
0.3
±10
VA+0.3
VD+0.3
85
85
150
Units
V
V
V
mA
V
V
°C
°C
°C
Note 1. All voltages with respect to ground.
Note 2. AGND and DGND must be connected to the same analog ground plane.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AGND, DGND=0V; Note 1)
Parameter
Symbol
min
typ
Power Supplies Analog
VA
4.5
5.0
(Note 3)
Digital (fs=4kHz to 48kHz)
VD
2.7
5.0
Digital (fs=48kHz to 96kHz)
VD
3.0
5.0
max
5.5
VA
VA
Units
V
V
V
Note 1. All voltages with respect to ground.
Note 3. The power up sequence between VA and VD is not critical.
WARNING: AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
MS0200-E-02
2006/01
-4-
ASAHI KASEI
[AK5381]
ANALOG CHARACTERISTICS
(Ta=25°C; VA=VD=5.0V; AGND=DGND=0V; fs=48kHz, 96kHz; SCLK=64fs; Signal Frequency=1kHz; 24bit Data;
Measurement frequency=20Hz ∼ 20kHz at fs=48kHz, 40Hz ∼ 40kHz at fs=96kHz; unless otherwise specified)
Parameter
min
typ
max
Units
ADC Analog Input Characteristics:
Resolution
24
Bits
Input Voltage
(Note 4)
2.7
3.0
3.3
Vpp
S/(N+D)
(−1dBFS)
fs=48kHz
88
96
dB
fs=96kHz
82
90
dB
DR
(−60dBFS)
fs=48kHz, A-weighted
100
106
dB
fs=96kHz
94
102
dB
S/N
fs=48kHz, A-weighted
100
106
dB
fs=96kHz
94
102
dB
Input Resistance
fs=48kHz
10
15
kΩ
fs=96kHz
6
9
kΩ
Interchannel Isolation
90
110
dB
Interchannel Gain Mismatch
0.1
0.5
dB
Gain Drift
100
150
ppm/°C
Power Supply Rejection
(Note 5)
50
dB
Power Supplies
Power Supply Current
Normal Operation (PDN pin = “H”)
VA
VD
(fs=48kHz)
VD
(fs=96kHz)
Power down mode (PDN pin = “L”)
VA+VD
16
8
14
24
12
21
mA
mA
mA
10
100
µA
(Note 6)
Note 4. This value is the full scale (0dB) of the input voltage. Input voltage is proportional to VA voltage.
Vin = 0.6 x VA (Vpp).
Note 5. PSR is applied to VA and VD with 1kHz, 50mVpp.
Note 6. All digital input pins are held VD or DGND.
MS0200-E-02
2006/01
-5-
ASAHI KASEI
[AK5381]
FILTER CHARACTERISTICS (fs=48kHz)
(Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 7)
±0.005dB
PB
0
±0.02dB
21.768
−0.06dB
22.0
−6.0dB
24.0
Stopband
SB
26.5
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay Distortion
∆GD
0
Group Delay
(Note 8)
GD
27.6
ADC Digital Filter (HPF):
Frequency Response (Note 7)
−3dB
FR
1.0
−0.5dB
2.9
−0.1dB
6.5
FILTER CHARACTERISTICS (fs=96kHz)
(Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V)
Parameter
Symbol
min
typ
ADC Digital Filter (Decimation LPF):
Passband
(Note 7)
±0.005dB
PB
0
±0.02dB
43.536
−0.06dB
44.0
−6.0dB
48.0
Stopband
SB
53.0
Passband Ripple
PR
Stopband Attenuation
SA
80
Group Delay Distortion
∆GD
0
Group Delay
(Note 8)
GD
27.6
ADC Digital Filter (HPF):
Frequency Response (Note 7)
−3dB
FR
2.0
−0.5dB
5.8
−0.1dB
13.0
max
Units
21.5
-
kHz
kHz
kHz
kHz
kHz
dB
dB
µs
1/fs
±0.005
Hz
Hz
Hz
max
Units
43.0
-
kHz
kHz
kHz
kHz
kHz
dB
dB
µs
1/fs
±0.005
Hz
Hz
Hz
Note 7. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz.
Note 8. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the
setting of 24bit data both channels to the ADC output register for ADC.
MS0200-E-02
2006/01
-6-
ASAHI KASEI
[AK5381]
DC CHARACTERISTICS (CMOS Level Mode)
(Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=2.7 ∼ [email protected]=4kHz ∼ 48kHz, VD=3.0 ∼ [email protected]=∼96kHz)
Parameter
Symbol
min
typ
max
High-Level Input Voltage
VIH
70%VD
Low-Level Input Voltage
VIL
30%VD
High-Level Output Voltage
(Iout=−100µA)
VOH
VD-0.5
Low-Level Output Voltage
(Iout=100µA)
VOL
0.5
Input Leakage Current
Iin
±10
Units
V
V
V
V
µA
DC CHARACTERISTICS (TTL Level Mode)
(Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=4.5 ∼ [email protected]=4kHz ∼ 48kHz)
Parameter
Symbol
min
typ
High-Level Input Voltage
(CKS2-0 pins)
VIH
70%VD
(All pins except CKS2-0 pins)
VIH
2.4
Low-Level Input Voltage
(CKS2-0 pins)
VIL
(All pins except CKS2-0 pins)
VIL
High-Level Output Voltage
(Iout=−100µA)
VOH
VD-0.5
Low-Level Output Voltage
(Iout=100µA)
VOL
Input Leakage Current
Iin
-
Units
V
V
V
V
V
V
µA
MS0200-E-02
max
30%VD
0.8
0.5
±10
2006/01
-7-
ASAHI KASEI
[AK5381]
SWITCHING CHARACTERISTICS (fs=4kHz ∼ 48kHz)
(Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=2.7 ∼ 5.5V; CL=20pF)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
1.024
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK Frequency
fs
4
Duty Cycle
Slave mode
45
Master mode
50
Audio Interface Timing
Slave mode
SCLK Period
tSCK
160
SCLK Pulse Width Low
tSCKL
65
Pulse Width High
tSCKH
65
LRCK Edge to SCLK “↑”
(Note 9)
tLRSH
30
SCLK “↑” to LRCK Edge
(Note 9)
tSHLR
30
LRCK to SDTO (MSB) (Except I2S mode)
tLRS
SCLK “↓” to SDTO
tSSD
Master mode
SCLK Frequency
fSCK
64fs
SCLK Duty
dSCK
50
SCLK “↓” to LRCK
tMSLR
−20
SCLK “↓” to SDTO
tSSD
Reset Timing
PDN Pulse Width
(Note 10)
PDN “↑” to SDTO valid at Slave Mode (Note 11)
PDN “↑” to SDTO valid at Master Mode (Note 11)
tPD
tPDV
tPDV
150
4132
4129
max
Units
36.864
MHz
ns
ns
48
55
kHz
%
%
35
35
ns
ns
ns
ns
ns
ns
ns
20
35
Hz
%
ns
ns
ns
1/fs
1/fs
Note 9. SCLK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK5381 can be reset by bringing the PDN pin = “L”.
Note 11. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
MS0200-E-02
2006/01
-8-
ASAHI KASEI
[AK5381]
SWITCHING CHARACTERISTICS (fs=48kHz ∼ 96kHz)
(Ta=Tmin ∼ Tmax; VA=4.5 ∼ 5.5V; VD=3.0 ∼ 5.5V; CL=20pF; CMOS Level Mode only)
Parameter
Symbol
min
typ
Master Clock Timing
Frequency
fCLK
12.288
Pulse Width Low
tCLKL
0.4/fCLK
Pulse Width High
tCLKH
0.4/fCLK
LRCK Frequency
fs
48
Duty Cycle
Slave mode
45
Master mode
50
Audio Interface Timing
Slave mode
SCLK Period
tSCK
160
SCLK Pulse Width Low
tSCKL
65
Pulse Width High
tSCKH
65
LRCK Edge to SCLK “↑”
(Note 9)
tLRSH
30
SCLK “↑” to LRCK Edge
(Note 9)
tSHLR
30
LRCK to SDTO (MSB) (Except I2S mode)
tLRS
SCLK “↓” to SDTO
tSSD
Master mode
SCLK Frequency
fSCK
64fs
SCLK Duty
dSCK
50
SCLK “↓” to LRCK
tMSLR
−20
SCLK “↓” to SDTO
tSSD
Reset Timing
tPD
PDN Pulse Width
(Note 10)
150
tPDV
4132
PDN “↑” to SDTO valid at Slave Mode (Note 11)
tPDV
4129
PDN “↑” to SDTO valid at Master Mode (Note 11)
max
Units
36.864
MHz
ns
ns
96
55
kHz
%
%
35
35
ns
ns
ns
ns
ns
ns
ns
20
35
Hz
%
ns
ns
ns
1/fs
1/fs
Note 9. SCLK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK5381 can be reset by bringing the PDN pin = “L”.
Note 11. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
MS0200-E-02
2006/01
-9-
ASAHI KASEI
[AK5381]
„ Timing Diagram
1/fCLK
VIH
MCLK
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tSCK
VIH
SCLK
VIL
tSCKH
tSCKL
Clock Timing
VIH
LRCK
VIL
tSHLR
tLRSH
VIH
SCLK
VIL
tSSD
tLRS
SDTO
50%VD
Audio Interface Timing (Slave mode)
MS0200-E-02
2006/01
- 10 -
ASAHI KASEI
[AK5381]
LRCK
50%VD
tMSLR
dSCK
SCLK
50%VD
tSSD
SDTO
50%VD
Audio Interface Timing (Master mode)
VIH
PDN
VIL
tPDV
SDTO
50%VD
tPD
PDN
VIL
Power Down & Reset Timing
MS0200-E-02
2006/01
- 11 -
ASAHI KASEI
[AK5381]
OPERATION OVERVIEW
„ System Clock
MCLK (256fs/384fs/512fs), SCLK and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be
synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency
and the system clock frequency. MCLK frequency, SCLK frequency, HPF (ON or OFF), the input level (CMOS or TTL)
and master/slave are selected by CKS2-0 pins as shown in Table 2.
All external clocks (MCLK, SCLK and LRCK) must be present unless PDN pin = “L”. If these clocks are not provided,
the AK5381 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not
present, place the AK5381 in power-down mode (PDN pin = “L”). In master mode, the master clock (MCLK) must be
provided unless PDN pin = “L”.
fs
32kHz
44.1kHz
48kHz
96kHz
MCLK
256fs
384fs
512fs
8.192MHz
12.288MHz
16.384MHz
11.2896MHz
16.9344MHz
22.5792MHz
12.288MHz
18.432MHz
24.576MHz
24.576MHz
36.864MHz
N/A
Table 1. System Clock Example
CKS2
CKS1
CKS0
Input Level
L
L
L
CMOS
L
L
H
CMOS
L
L
H
H
L
H
CMOS
CMOS
H
L
L
TTL*
H
H
H
L
H
H
H
L
H
CMOS
CMOS
HPF
768fs
24.576MHz
33.8688MHz
36.864MHz
N/A
Master/Slave
MCLK
256/384fs (∼ 96kHz)
ON
Slave
512/768fs (∼ 48kHz)
256/384fs (∼ 96kHz)
OFF
Slave
512/768fs (∼ 48kHz)
ON
Master
256fs (∼ 96kHz)
ON
Master
512fs (∼ 48kHz)
256fs/384/512/768fs
ON
Slave
(∼ 48kHz)
Reserved
ON
Master
384fs (∼ 96kHz)
ON
Master
768fs (∼ 48kHz)
Table 2. Mode Select
SCLK
≥ 48fs or 32fs
≥ 48fs or 32fs
64fs
64fs
≥ 48fs or 32fs
64fs
64fs
Note: SDTO outputs 16bit data at SCLK=32fs.
Note: The AK5381 does not support TTL interface at 96kHz.
„ Audio Interface Format
Two kinds of data formats can be chosen with the DIF pin (Table 3). In both modes, the serial data is in MSB first, 2’s
compliment format. The SDTO is clocked out on the falling edge of SCLK. The audio interface supports both master and
slave modes. In master mode, SCLK and LRCK are output with the SCLK frequency fixed to 64fs and the LRCK
frequency fixed to 1fs.
Mode
0
1
DIF pin
L
H
SDTO
LRCK
SCLK
24bit, MSB justified
H/L
≥ 48fs or 32fs
24bit, I2S Compatible
L/H
≥ 48fs or 32fs
Table 3. Audio Interface Format
MS0200-E-02
Figure
Figure 1
Figure 2
2006/01
- 12 -
ASAHI KASEI
[AK5381]
LRCK
0 1 2
31 0 1 2
20 21 22 23 24
20 21 22 23 24
31 0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 1. Mode 0 Timing
LRCK
0 1 2 3
21 22 23 24 25
0 1 2
21 22 23 24 25
0 1
BICK(64fs)
SDTO(o)
23 22
4 3 2 1 0
23 22
4 3 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
„ Digital High Pass Filter
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz
(@fs=48kHz) and scales with sampling rate (fs).
HPF is controlled by CKS2-0 pins (Table 2). If HPF setting (ON/OFF) is changed at operating, click noise occurs by
changing DC offset. It is recommended that HPF setting is changed at PDN pin = “L”.
MS0200-E-02
2006/01
- 13 -
ASAHI KASEI
[AK5381]
„ Power down
The AK5381 is placed in the power-down mode by bringing PDN pin “L” and the digital filter is also reset at the same
time. This reset should always be done after power-up. In the power-down mode, the VCOM are AGND level. An analog
initialization cycle starts after exiting the power-down mode. Therefore, the output data SDTO becomes available after
4129 cycles of LRCK clock in master mode or 4132 cycles of LRCK clock in slave mode. During initialization, the ADC
digital data outputs of both channels are forced to a 2’s complement “0”. The ADC outputs settle in the data
corresponding to the input signals after the end of initialization (Settling approximately takes the group delay time).
(1)
PDN
Internal
State
Normal Operation
Power-down
Initialize
Normal Operation
GD (2)
GD
A/D In
(Analog)
A/D Out
(Digital)
Clock In
MCLK,LRCK,SCLK
(3)
“0”data
Idle Noise
“0”data
Idle Noise
(4)
Notes:
(1) 4132/fs in slave mode and 4129/fs in master mode.
(2) Digital output corresponding to analog input has the group delay (GD).
(3) A/D output is “0” data at the power-down state.
(4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5381 should be in the power-down state.
Figure 3. Power-down/up sequence example
„ System Reset
The AK5381 should be reset once by bringing PDN pin “L” after power-up. In slave mode, the internal timing starts
clocking by the rising edge (falling edge at mode 1) of LRCK after exiting from reset and power down state by MCLK.
The AK5381 is power down state until LRCK is input. In master mode, the internal timing starts when MCLK is input.
MS0200-E-02
2006/01
- 14 -
ASAHI KASEI
[AK5381]
SYSTEM DESIGN
Figure 4 shows the system connection diagram. An evaluation board is available which demonstrates application circuits,
the optimum layout, power supply arrangements and measurement results.
Rch In
10u
+
Lch In
+
1 AINR
CKS0 16
2 AINL
CKS2 15
10u
3 CKS1
2.2u 0.1u
4 VCOM
+
5 AGND
Analog 5V
+
10u
0.1u
+
10u
0.1u
Mode
Control
DIF 14
AK5381
Reset
PDN 13
SCLK 12
6 VA
MCLK 11
7 VD
LRCK 10
8 DGND
SDTO 9
Audio
Controller
Analog Ground
System Ground
Note:
- AGND and DGND of the AK5381 should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All input pins except pull-down pin should not be left floating.
- The CKS1 pin should be connected VA or AGND.
Figure 4. Typical Connection Diagram
Digital Ground
Analog Ground
System
Controller
1
AINR
CKS0 16
2
AINL
CKS2 15
3
CKS1
4
VCOM
DIF 14
AK5381
PDN 13
5
AGND
SCLK 12
6
VA
MCLK 11
7
VD
LRCK 10
8
DGND
SDTO
9
Figure 5. Ground Layout
Note:
- AGND and DGND must be connected to the same analog ground plane.
MS0200-E-02
2006/01
- 15 -
ASAHI KASEI
[AK5381]
1. Grounding and Power Supply Decoupling
The AK5381 requires careful attention to power supply and grounding arrangements. VA and VD are usually supplied
from the analog supply in the system. Alternatively if VA and VD are supplied separately, the power up sequence is not
critical. AGND and DGND of the AK5381 must be connected to analog ground plane. System analog ground and
digital ground should be connected together near to where the supplies are brought onto the printed circuit board.
Decoupling capacitors should be as near to the AK5381 as possible, with the small value ceramic capacitor being the
nearest.
2. Voltage Reference
The voltage input to VA sets the analog input range. VCOM are 50%VA and normally connected to AGND with a 0.1µF
ceramic capacitor. An electrolytic capacitor 2.2µF parallel with a 0.1µF ceramic capacitor attached to VCOM pin
eliminates the effects of high frequency noise. No load current may be drawn from these pins. All signals, especially
clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5381.
3. Analog Inputs
The ADC inputs are single-ended and internally biased to the common voltage (50%VA) with 15kΩ(typ) resistance. The
input signal range scales with the supply voltage and nominally 0.6xVA Vpp(typ). The ADC output data format is 2’s
complement. The DC offset is removed by the internal HPF.
The AK5381 samples the analog inputs at 64fs. The digital filter rejects noise above the stop band except for multiples of
64fs. The AK5381 includes an anti-aliasing filter (RC filter) to attenuate a noise around 64fs.
MS0200-E-02
2006/01
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ASAHI KASEI
[AK5381]
PACKAGE
16pin TSSOP (Unit: mm)
*5.0±0.1
9
A
8
1
0.13 M
6.4±0.2
*4.4±0.1
16
1.05±0.05
0.22±0.1
0.65
0.17±0.05
Detail A
0.5±0.2
0.1±0.1
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Material & Lead finish
Package molding compound:
Lead frame material:
Lead frame surface treatment:
Epoxy
Cu
Solder (Pb free) plate
MS0200-E-02
2006/01
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ASAHI KASEI
[AK5381]
MARKING (AK5381VT)
AKM
5381VT
XXYYY
1)
2)
3)
Pin #1 indication
Date Code : XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code : 5381VT
MS0200-E-02
2006/01
- 18 -
ASAHI KASEI
[AK5381]
MARKING (AK5381ET)
AKM
5381ET
XXYYY
4)
5)
6)
Pin #1 indication
Date Code: XXYYY (5 digits)
XX:
Lot#
YYY: Date Code
Marketing Code: 5381ET
MS0200-E-02
2006/01
- 19 -
ASAHI KASEI
[AK5381]
Revision History
Date (YY/MM/DD)
03/01/24
04/04/19
06/01/11
Revision
00
01
02
Reason
First Edition
Added
Explanation
Page
Contents
P.4
Error Correct
P.7
Spec Addition
P.2
ABSOLUTE MAXIMUM RATINGS
Analog Input Voltage (AINL, AINR pins)
→ Analog Input Voltage (AINL, AINR, CKS1 pins)
Digital Input Voltage (All digital input pins)
→ Digital Input Voltage (All digital input pins except
CKS1 pin)
DC CHARACTERISTICS (CMOS Level Mode)
High-Level Output Voltage (Iout=−20µA)
→ High-Level Output Voltage (Iout=−100µA)
Low-Level Output Voltage (Iout=20µA)
→ Low-Level Output Voltage (Iout=100µA)
Ordering Guide
AK5381ET was added.
MARKING
AK5381ET was added.
P.19
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any
use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized
distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to customs
and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to any
such use, except with the express written consent of the Representative Director of AKM. As used
here:
a. A hazard related device or system is one designed or intended for life support or maintenance of
safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
b. A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content and
conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for
and hold AKM harmless from any and all claims arising from the use of said product in the absence
of such notification.
MS0200-E-02
2006/01
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