52076a.pdf

16-bit CPU Self-Test Library
User’s Guide
 2012 Microchip Technology Inc.
DS52076A
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2012, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-62076-338-4
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS52076A-page 2
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
 2012 Microchip Technology Inc.
16-BIT CPU SELF-TEST LIBRARY
USER’S GUIDE
Table of Contents
Preface ........................................................................................................................... 5
Chapter 1. Introduction
1.1 Key Requirements ........................................................................................ 11
1.2 Software Package Files ................................................................................ 13
Chapter 2. Algorithm Flow
Chapter 3. Test Software Subsets
3.1 Test Subset Results ..................................................................................... 17
3.2 Test Subset Descriptions ............................................................................. 18
3.3 Computational Resource Requirements ...................................................... 21
Chapter 4. Functional Test Coverage
4.1 Instruction Set .............................................................................................. 25
4.2 Addressing Modes ........................................................................................ 33
4.3 CPU Registers .............................................................................................. 35
4.4 Bus Structures .............................................................................................. 40
4.5 CPU Hardware Units .................................................................................... 47
Worldwide Sales and Service .................................................................................... 52
 2012 Microchip Technology Inc.
DS52076A-page 3
16-bit CPU Self-test Library User’s Guide
NOTES:
DS52076A-page 4
 2012 Microchip Technology Inc.
16-BIT CPU SELF-TEST LIBRARY
USER’S GUIDE
Preface
NOTICE TO CUSTOMERS
All documentation becomes dated, and this manual is no exception. Microchip tools and
documentation are constantly evolving to meet customer needs, so some actual dialogs
and/or tool descriptions may differ from those in this document. Please refer to our web site
(www.microchip.com) to obtain the latest documentation available.
Documents are identified with a “DS” number. This number is located on the bottom of each
page, in front of the page number. The numbering convention for the DS number is
“DSXXXXXA”, where “XXXXX” is the document number and “A” is the revision level of the
document.
For the most up-to-date information on development tools, see the MPLAB® IDE online help.
Select the Help menu, and then Topics to open a list of available online help files.
INTRODUCTION
This chapter contains general information that will be useful to know before you use the
16-bit CPU Self-test Library. Items discussed in this chapter include:
•
•
•
•
•
•
•
•
Document Layout
Conventions Used in this Guide
Warranty Registration
Recommended Reading
The Microchip Web Site
Development Systems Customer Change Notification Service
Customer Support
Document Revision History
DOCUMENT LAYOUT
This document describes how to use the 16-bit CPU Self-test Library as a development
and demonstration tool for dsPIC33F, dsPIC33E, PIC24H, and PIC24E device
capabilities and features. The document layout is as follows:
• Chapter 1. Introduction – This chapter introduces the 16-bit CPU Self-test Library
and provides an overview of its features.
• Chapter 2. Algorithm Flow – This chapter describes the general execution flow
of the 16-bit CPU Self-test Library algorithm.
• Chapter 3. “Test Software Subsets” – This appendix provides an overview and
the computational resource requirements of the test subsets that are provided
with the 16-bit CPU Self-test Library.
• Chapter 4. Functional Test Coverage – This chapter describes the instruction
classes that are supported by the 16-bit CPU Self-test Library.
 2012 Microchip Technology Inc.
DS52076A-page 5
16-bit CPU Self-test Library User’s Guide
CONVENTIONS USED IN THIS GUIDE
This manual uses the following documentation conventions:
DOCUMENTATION CONVENTIONS
Description
Represents
Examples
Arial font:
Italic characters
Initial caps
Referenced books
MPLAB® IDE User’s Guide
Emphasized text
...is the only compiler...
A window
the Output window
A dialog
the Settings dialog
A menu selection
select Enable Programmer
Quotes
A field name in a window or
dialog
“Save project before build”
Underlined, italic text with
right angle bracket
A menu path
File>Save
Bold characters
A dialog button
Click OK
A tab
Click the Power tab
A key on the keyboard
Press <Enter>, <F1>
Sample source code
#define START
Filenames
autoexec.bat
File paths
c:\mcc18\h
Keywords
_asm, _endasm, static
Command-line options
-Opa+, -Opa-
Bit values
0, 1
Constants
0xFF, ‘A’
Italic Courier New
A variable argument
file.o, where file can be
any valid filename
Square brackets [ ]
Optional arguments
mcc18 [options] file
[options]
Curly brackets and pipe
character: { | }
Choice of mutually exclusive
arguments; an OR selection
errorlevel {0|1}
Ellipses...
Replaces repeated text
var_name [,
var_name...]
Represents code supplied by
user
void main (void)
{ ...
}
Text in angle brackets < >
Courier New font:
Plain Courier New
DS52076A-page 6
 2012 Microchip Technology Inc.
Preface
WARRANTY REGISTRATION
Please complete the enclosed Warranty Registration Card and mail it promptly.
Sending in the Warranty Registration Card entitles you to receive new product updates.
Interim software releases are available at the Microchip web site.
RECOMMENDED READING
This user’s guide describes how to use the 16-bit CPU Self-test Library. Other useful
documents are listed below. The following Microchip documents are available and
recommended as supplemental reference resources. The latest documentation is
available from the Microchip web site (www.microchip.com).
Readme Files
For the latest information on using other tools, read the tool-specific Readme files in
the Readme subdirectory of the MPLAB® IDE installation directory. The Readme files
contain update information and known issues that may not be included in this user’s
guide.
Family Reference Manual Sections
Family Reference Manual sections are available, which explain the operation of the
dsPIC33F/PIC24H and dsPIC33E/PIC24H device architecture and peripheral modules. The specifics of each device family are discussed in the individual family’s device
data sheet.
Device Data Sheets and Flash Programming Specifications
Refer to the appropriate device data sheet for device-specific information and
specifications. Also, refer to the appropriate device Flash Programming Specification
for information on instruction sets and firmware development. These documents may
be obtained from the Microchip web site or your local sales office.
16-bit MCU and DSC Programmer’s Reference Manual (DS70157)
This manual is a software developer’s reference for the 16-bit PIC24E, PIC24F, and
PIC24H MCU, and 16-bit dsPIC30F, dsPIC33E, and dsPIC33F DSC families of
devices. It describes the instruction set in detail and also provides general information
to assist in developing software for these device families.
MPLAB® Assembler Linker and Utilities for PIC24 MCUs and dsPIC®
DSCs User’s Guide (DS51317)
This document details Microchip Technology’s language tools for dsPIC® DSC devices
based on GNU technology. The language tools discussed are:
•
•
•
•
MPLAB Assembler PIC24 MCUs and dsPIC® DSCs
MPLAB Linker PIC24 MCUs and dsPIC® DSCs
MPLAB Archiver/Librarian PIC24 MCUs and dsPIC® DSCs
Other utilities
MPLAB® C Compiler for PIC24 MCUs and dsPIC® DSCs User’s Guide
(DS51284)
This document details the use of Microchip’s MPLAB C Compiler for PIC24 MCUs and
dsPIC DSC devices to develop an application. The MPLAB C Compiler is a
GNU-based language tool, based on source code from the Free Software Foundation
(FSF). For more information about the FSF, see www.fsf.org.
 2012 Microchip Technology Inc.
DS52076A-page 7
16-bit CPU Self-test Library User’s Guide
MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide (DS51616)
This document describes how to use the MPLAB REAL ICE in-circuit emulator as a
development tool to emulate and debug firmware on a target board, as well as how to
program devices.
MPLAB® IDE User’s Guide (DS51519)
This document describes how to use the MPLAB IDE Integrated Development Environment, as well as the MPLAB project manager, MPLAB editor and MPLAB SIM simulator.
Use these development tools to help you develop and debug application code.
DS52076A-page 8
 2012 Microchip Technology Inc.
Preface
THE MICROCHIP WEB SITE
Microchip provides online support through our web site at www.microchip.com. This
web site is used as a means to make files and information easily available to
customers. Accessible by using your favorite Internet browser, the web site contains
the following information:
• Product Support – Data sheets and errata, application notes and sample
programs, design resources, user’s guides and hardware support documents,
latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQs), technical
support requests, online discussion groups, Microchip consultant program
member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip
press releases, listing of seminars and events, listings of Microchip sales offices,
distributors and factory representatives
DEVELOPMENT SYSTEMS CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip
products. Subscribers will receive e-mail notification whenever there are changes,
updates, revisions or errata related to a specified product family or development tool of
interest.
To register, access the Microchip web site at http://www.microchip.com, click
Customer Change Notification and follow the registration instructions.
The Development Systems product group categories are:
• Compilers – The latest information on Microchip C compilers and other language
tools. These include the MPLAB® C compiler; MPASM™ and MPLAB 16-bit
assemblers; MPLINK™ and MPLAB 16-bit object linkers; and MPLIB™ and
MPLAB 16-bit object librarians.
• Emulators – The latest information on the Microchip MPLAB REAL ICE™
in-circuit emulator.
• In-Circuit Debuggers – The latest information on the Microchip in-circuit
debugger, MPLAB ICD 3.
• MPLAB IDE – The latest information on Microchip MPLAB IDE, the Windows®
Integrated Development Environment for development systems tools. This list is
focused on the MPLAB IDE, MPLAB SIM simulator, MPLAB IDE Project Manager
and general editing and debugging features.
• Programmers – The latest information on Microchip programmers. These include
the MPLAB PM3 device programmer and the PICkit™ 3 development
programmers.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or FAE for support. Local
sales offices are also available to help customers. A listing of sales offices and
locations is included in the back of this document.
Technical support is available through our web site at: http://support.microchip.com
 2012 Microchip Technology Inc.
DS52076A-page 9
16-bit CPU Self-test Library User’s Guide
DOCUMENT REVISION HISTORY
Revision A (June 2012)
This is the initial released version of the document.
DS52076A-page 10
 2012 Microchip Technology Inc.
16-BIT CPU SELF-TEST LIBRARY
USER’S GUIDE
Chapter 1. Introduction
The 16-bit CPU Self-test Library is intended to periodically verify during run-time, that
all CPU core features are functioning correctly. This library supports the dsPIC33F,
PIC24H, dsPIC33E and PIC24E device families.
The 16-bit CPU Self-test Library functions will simply generate some computed results
that can either be logged or transmitted through any communication interface to a
secondary processor in the system. The interpretation of these results that are used to
determine whether the CPU is functioning correctly (and to shut down the system if a
failure is detected), is the responsibility of this secondary processor. The 16-bit CPU
Self-test Library test suite is not meant to test peripheral functionality, but simply that of
the CPU core.
1.1
KEY REQUIREMENTS
The 16-bit CPU Self-test Library functions are executed by the CPU during application
program execution and has been designed to satisfy the following general
requirements:
• The 16-bit CPU Self-test Library has been implemented using the MPLAB®
ASM30 assembly language programs; however, each function in the library is
Callable.
• Each execution of the self-test algorithm must perform a series of computations
on an original “seed” value, generating a unique 16-bit result at the end of the
execution. Intermediate results based on the seed must not be overwritten by a
constant value, as this would end up eliminating part of the self-test coverage.
• Each result may either be logged by the application or transmitted to a secondary
processor using an available communication interface such as SPI.
• The functions in the 16-bit CPU Self-test Library may be called by the application
program or real-time operating system at regular intervals. For example, the
application can call each function of the 16-bit CPU Self-test Library every
2 microseconds.
• The self-test algorithm is designed to provide at least 95% test coverage of CPU
functionality, which includes all available instruction opcodes, addressing modes,
bus structures, bits of CPU registers, math hardware, and any special features
unique to the supplier’s processor that can impact the data computation. The
functional test coverage is explained in detail in Chapter 4. “Functional Test
Coverage”.
In addition, the algorithm has been designed to satisfy the following timing and
computational resource constraints:
• The minimum (worst-case) CPU clock frequency that is assumed for calculating the
algorithm execution time requirements is 20 MIPS.
Note:
 2012 Microchip Technology Inc.
This minimum frequency is used solely for determining the library’s
real-time execution characteristics, and does not in any way limit the application’s execution requirements (e.g., an application might need to run at
lower speeds at certain times in order to minimize power consumption).
DS52076A-page 11
16-bit CPU Self-test Library User’s Guide
• Each individual function call in the 16-bit CPU Self-test Library must not inhibit or
delay the scheduled execution of the primary control loop of the application by
more than 10 microseconds. This limit represents the maximum time for which
interrupts can be disabled in the application. For a minimum CPU clock frequency
of 20 MIPS, this translates to 200 instruction cycles per function.
• A minimum of eight independent test results are computed every 16 ms. For a
minimum CPU clock frequency of 20 MIPS, the entire test-suite is completed within
16 ms and each individual test result is generated at 2 ms intervals, which meets and
exceeds the requirement. This is accomplished by partitioning the self-test algorithm
into eight “test subsets”, as described in Chapter 3. “Test Software Subsets”.
• No more than 2.5% of the overall CPU bandwidth may be utilized by the self-test
routines over any 16 ms time window. For a 20 MIPS CPU clock frequency, this
translates to 8000 instruction cycles (20000000 * 0.025 * 0.01)for the entire CPU
test-suite. In the 16-bit CPU Self-test Library, eight test subsets are executed during each 16 ms window, and each test subset is designed to execute within only
100 instruction cycles. This implies that the execution of the entire test suite
requires only 800 instruction cycles, which meets and greatly exceeds the
maximum CPU bandwidth usage requirement.
• The 16-bit CPU Self-test Library must use less than 2 KB of Program Flash Memory. The library software meets this limit. The actual Program Memory usage is
listed in Chapter 3.3 “Computational Resource Requirements”.
• The 16-bit CPU Self-test Library must use less than 200 bytes of RAM. The
library software meets this limit. The actual Program Memory usage is listed in
Chapter 3.3 “Computational Resource Requirements”. A common RAM block
has been defined for the entire test suite, and varying portions of this block will be
utilized by the eight test subsets.
• The 16-bit CPU Self-test Library task may have lower priority than other
application tasks. Therefore, each test subset has been designed to include
context save and restore of all Special Function Registers (SFRs) used by the
function. Some of these registers, W0-W7, are “caller-saved”, meaning these
SFRs are automatically saved by the C compiler if the function being called uses
any of them.
DS52076A-page 12
 2012 Microchip Technology Inc.
Introduction
1.2
SOFTWARE PACKAGE FILES
The files in the 16-bit CPU Self-test Library software package are:
1.2.1
CpuTestSubsets.s
This is the main assembly language source file that contains all eight test subset
functions. Each function is defined as a C-callable Assembly subroutine with no input
parameters and a 16-bit return value.
1.2.2
CpuTestISR.s
This Assembly language source file contains all interrupt and trap service routines used
by the test subset functions to test some interrupt-related features such as math error
traps and the DISI instruction. These handlers are utilized by multiple test subset
routines, and are defined to use the Alternate Interrupt Vector Table (AIVT).
1.2.3
CPUverification.inc
This Assembler include file contains several definitions that are shared by all of the test
subset functions:
• Definitions for program Flash memory and data RAM sizes. The correct memory
sizes must be defined by the user based on the device being tested. In the
example application projects for the five devices included in the software package,
the device memory size is predefined in this file.
• Definitions of constants stored in program Flash memory, for testing Program
Space Visibility (PSV) and table reads in test subset 2.
• Definitions of RAM variables and arrays used by all of the test subset functions
• Definitions of various constants used by various test subsets.
Note:
1.2.4
If the device being tested has a program Flash memory size and/or RAM
size that is different from the options provided in this file, the addresses of
the constants and/or variables in this file would need to be customized by
the user.
Application.c
This file is an example user application demonstrating how the test subset functions
can be executed by an application in real-time. A 16-bit general-purpose timer (Timer2)
and a case-switching statement are utilized by the application to call a different test
subset every 2 ms. This sequence ensures that the entire test-suite has been
completely executed within a 16 ms window. The returned test results (6 or 8,
depending on whether a PIC24H/PIC24E or a dsPIC33F/dsPIC33E device is being
used) are stored in an array named TestResults, and may be inspected in a Watch
window using debugging tools such as MPLAB ICD 3 or MPLAB REAL ICE™. The
user application logs the results in an array.
1.2.5
Example Application Projects
MPLAB IDE project files are included in the software package for the following five
devices:
•
•
•
•
•
dsPIC33FJ256GP710A
dsPIC33EP64MC506
dsPIC33EP512MU810
PIC24HJ256GP610A
PIC24EP512GU810
 2012 Microchip Technology Inc.
DS52076A-page 13
16-bit CPU Self-test Library User’s Guide
NOTES:
DS52076A-page 14
 2012 Microchip Technology Inc.
16-BIT CPU SELF-TEST LIBRARY
USER’S GUIDE
Chapter 2. Algorithm Flow
The general execution flow of the CPU Self-Test Library is illustrated in Figure 2-1.
FIGURE 2-1:
CPU SELF-TEST LIBRARY ALGORITHM EXECUTION FLOW
Start
Outer Loop
(executed every 16 ms)
Eight independent
results per iteration
Execute a Test Subset
~200 cycles (10 µs) maximum;
Send or log test result
Inner Loop
(executed every 2 ms)
One independent
result per iteration
No
Yes
No
Has 2 ms elapsed?
Has 16 ms elapsed?
Yes
Restart Test Subsets
The overall test suite is sub-divided into eight test subset functions, which are executed
in a cyclic manner. A different test subset function is called by the application every
2 ms, thereby completing the entire test suite every 16 ms. Since each test subset
generates a unique 16-bit data result, eight such test results (each representing a
different subset of CPU functionality) are generated during the 16 ms window.
A separate C-callable function is provided for each test subset. Also, all functionality
specific to dsPIC33F/dsPIC33E (i.e., features that are not present in the
PIC24H/PIC24E architecture) is tested only in test subsets 7 and 8, making the test
suite highly modular.
An overview of each test suite is provided in Chapter 3. “Test Software Subsets”.
 2012 Microchip Technology Inc.
DS52076A-page 15
16-bit CPU Self-test Library User’s Guide
NOTES:
DS52076A-page 16
 2012 Microchip Technology Inc.
16-BIT CPU SELF-TEST LIBRARY
USER’S GUIDE
Chapter 3. Test Software Subsets
The 16-bit CPU Self-test Library software is divided into eight test subsets. Each of the
test subsets validates several features and components of the CPU. Each subset is
designed in such a way that the result of one operation is used as a source operand for
the next instruction. In some cases, different sets of operations on the same original
seed value yield different intermediate results, which are then combined within the
same test subset function using arithmetic operations such as ADD and logical
operations such as XOR. Therefore, there is a sequential dependency between various
operations tested with a test subset, and a failure of any feature tested in a test subset
is manifested by the generation of an incorrect final 16-bit result generated by that test
subset (and interpreted by the secondary processor as being incorrect).
3.1
TEST SUBSET RESULTS
Each test subset is a C-callable Assembly function, and returns the 16-bit result
generated by the test subset. The calling function can then either log this 16-bit value
or transmit it to a secondary processor through a suitable communication interface
such as SPI. The expected 16-bit results that would indicate correct CPU functionality
are listed in Table 3-1 for two representative devices from the PIC24H and dsPIC33F,
and also for three representative devices from the PIC24E and dsPIC33E families.
Note that test subset 2 and subset 7 results depend on the specific device on which the
test is being executed, for two reasons:
1. Device ID reads are used to test reads of Configuration memory space
(test subset 2 only).
2. Some of the program Flash and data RAM read/writes tests include some
accesses of memory addresses that are not present on all devices. The include
file CPUverification.inc contains preprocessor definitions for Flash and RAM
sizes, that the user can customize based on the specific device used.
TABLE 3-1:
EXPECTED 16-BIT CPU FUNCTIONALITY RESULTS
Expected Result
Test
Subset
PIC24HJ256GP610A
dsPIC33FJ256GP710A
dsPIC33EP64MC506
PIC24EP512GU810
dsPIC33EP512MU810
1
0x694D
0x694D
0x694D
0x694D
0x694D
2
0x5F7F
0x6003
0xCE7E
0x743A
0x7476
3
0xC2A7
0xC2A7
0xC2AB
0xC2AB
0xC2AB
4
0x00F8
0x00F8
0x00F8
0x00F8
0x00F8
5
0x1BD2
0x1BD2
0x1BD2
0x1BD2
0x1BD2
6
0xAE40
0xAE40
0xAE40
0xAE40
0xAE40
7
N/A
0xE340
0xABA4
N/A
0x7222
8
N/A
0x1D7D
0x1D7D
N/A
0x1D7D
 2012 Microchip Technology Inc.
DS52076A-page 17
16-bit CPU Self-test Library User’s Guide
3.2
TEST SUBSET DESCRIPTIONS
This section provides a brief description of the key features tested in each of the eight
test subsets.
3.2.1
Subset 1
Test Subset 1 performs the following basic operations:
• All of the Move instructions are tested
• The addressing modes tested are:
- Immediate
- File register
- Register direct and indirect (with pre-increment, post-increment, pre-decrement,
post-decrement, literal offset, and register offset)
• SWAP and EXCH instructions are tested
• All bit-manipulation, bit-test and bit-compare-skip operations are tested
• Single-word and double-word instructions are tested
• Byte move instructions are also checked
3.2.2
Subset 2
Test Subset 2 performs the following basic operations:
•
•
•
•
•
PSV and table accesses from different sections (four locations) of program memory
All bits of the program memory Address Bus are toggled
All bits of the data memory Address Bus are toggled
All bits of the X Data Read and Write Buses are toggled
CPU registers tested for read/write operations are:
- W0-W15
- SPLIM
- TBLPAG
- PSVPAG or DSRPAG
• Tested Read after Write (RAW) dependency
• Tested NOP and NOPR instructions
3.2.3
Subset 3
Test Subset 3 performs the following basic operations:
•
•
•
•
•
•
All conditional branch and GOTO instructions with alternative conditions
Program Counter (PC) behavior during above program flow change operations
All Call and Return operations
Automatic context save on stack
All Stack and Shadow operations
DISI instruction.
3.2.4
Subset 4
Test Subset 4 performs the following basic operations:
•
•
•
•
•
•
DS52076A-page 18
Branch instructions tested for false condition are NOV, Z, NN, NC, and NZ
All logic instructions: AND, CLR, COM, IOR, NEG, SETM and XOR Instructions
All data rotate and shift instructions
All compare and compare-skip instructions
The Z, OV, DC, N, and C bits of the status register are checked for their behavior
Some byte-mode logic instructions are tested
 2012 Microchip Technology Inc.
Test Software Subsets
3.2.5
Subset 5
Test Subset 5 performs the following basic operations:
• The following instructions are tested:
-
ADD
ADDC
SUB
SUBB
SUBBR
INC
INC2
DEC
DEC2
SE
- ZE
• The addressing modes tested here are:
- Immediate
- File register
- Register direct
• Byte instructions are also checked
• Branch instructions tested for true condition are:
-
GT
GTU
LE
LEU
NC
NN
- OV
• Branch instructions tested for false condition are:
-
C
GE
GEU
LT
LTU
N
- NOV
• Divide Unsigned Double (DIV.UD) instruction is tested
3.2.6
Subset 6
Test Subset 6 performs the following basic operations:
•
•
•
•
All MUL instruction variants
All DIV instruction variants except DIVF and DIV.UD
REPEAT loop
Math error trap generation (divide-by-zero error)
 2012 Microchip Technology Inc.
DS52076A-page 19
16-bit CPU Self-test Library User’s Guide
3.2.7
Subset 7
Test Subset 7 performs the following basic operations:
• All DSP accumulator operations, including different bit states of the individual bits
of both accumulators
• All DSP multiplier-based instructions
• All DSP MAC register indirect addressing modes
• All DSP shift instructions
• Math error trap generation due to accumulator-related events (accumulator overflow
and catastrophic overflow)
• CORCON bit behavior
3.2.8
Subset 8
Test Subset 8 performs the following basic operations:
•
•
•
•
DS52076A-page 20
Modulo Addressing (both byte and word modes)
Bit-reversed Addressing
DO loop
Fractional Divide (DIVF) instruction
 2012 Microchip Technology Inc.
Test Software Subsets
3.3
COMPUTATIONAL RESOURCE REQUIREMENTS
The instruction cycle counts, RAM requirements and program Flash memory
requirements of all eight Test Subset functions for five devices are listed in Table 3-2
through Table 3-6.
All RAM and Flash requirements are within the targeted maximum limits of 200 bytes
and 2 KB (2048 bytes), respectively.
TABLE 3-2:
RESOURCE REQUIREMENTS FOR THE PIC24HJ256GP610A DEVICE
Test Subset
2:
3:
4:
RAM (bytes)
Flash (bytes)
1
98
6
246
2
105
34
273
3
114
80
300
4
98
4
279
5
104
2
249
6
116
14
156(4)
7
N/A
N/A
N/A
8
N/A
N/A
N/A
Total
Note 1:
Instruction Cycles(3)
635
(1,2)
1503
120
In addition, a minimum stack size of 98 bytes must be specified in the Linker settings, to support the
execution of the 16-bit CPU Self-test Library routines.
A total (non-contiguous) RAM space of up to 26 bytes is reserved for all constants and variables, and the
stack used by all the CPU-self test routines.
The instruction cycle counts listed here include the instruction cycles required by the CALL and RETURN
instructions for each function call, as well as the cycles needed to save and restore the registers used in
these functions.
The Flash memory usage listed for this test subset includes an Interrupt Service Routine that is shared
between test subsets 6 and 7.
TABLE 3-3:
RESOURCE REQUIREMENTS FOR THE PIC24EP512GU810 DEVICE
Test Subset
Instruction Cycles(3)
RAM (bytes)
Flash (bytes)
1
105
6
246
2
131
34
267
3
173
78
300
4
105
4
279
5
125
2
249
6
135
12
147(4)
7
N/A
N/A
N/A
Note 1:
2:
3:
4:
8
N/A
N/A
N/A
Total
774
118(1,2)
1488
In addition, a minimum stack size of 98 bytes must be specified in the Linker settings, to support the
execution of the 16-bit CPU Self-test Library routines.
A total (non-contiguous) RAM space of up to 26 bytes is reserved for all constants and variables, and the
stack used by all the CPU-self test routines.
The instruction cycle counts listed here include the instruction cycles required by the CALL and RETURN
instructions for each function call, as well as the cycles needed to save and restore the registers used in
these functions.
The Flash memory usage listed for this test subset includes an Interrupt Service Routine that is shared
between test subsets 6 and 7.
 2012 Microchip Technology Inc.
DS52076A-page 21
16-bit CPU Self-test Library User’s Guide
TABLE 3-4:
RESOURCE REQUIREMENTS FOR THE dsPIC33FJ256GP710A DEVICE
Test Subset
Instruction Cycles(3)
RAM (bytes)
Flash (bytes)
1
98
6
246
2
105
34
273
3
114
80
300
Note 1:
2:
3:
4:
4
98
4
279
5
104
2
249
6
116
14
156(4)
7
130
44
288
8
131
42
246
Total
896
124(1,2)
2037
In addition, a minimum stack size of 98 bytes must be specified in the Linker settings, to support the
execution of the 16-bit CPU Self-test Library routines.
A total (non-contiguous) RAM space of up to 26 bytes is reserved for all constants and variables, and the
stack used by all the CPU-self test routines.
The instruction cycle counts listed here include the instruction cycles required by the CALL and RETURN
instructions for each function call, as well as the cycles needed to save and restore the registers used in
these functions.
The Flash memory usage listed for this test subset includes an Interrupt Service Routine that is shared
between test subsets 6 and 7.
TABLE 3-5:
RESOURCE REQUIREMENTS FOR THE dsPIC33EP512MU810 DEVICE
Test Subset
Instruction Cycles(3)
RAM (bytes)
Flash (bytes)
1
105
6
246
2
131
34
267
3
173
78
300
4
105
4
279
5
125
2
249
6
135
12
147(4)
7
177
44
279
Note 1:
2:
3:
4:
8
144
42
246
Total
1095
124(1,2)
2013
In addition, a minimum stack size of 98 bytes must be specified in the Linker settings, to support the
execution of the 16-bit CPU Self-test Library routines.
A total (non-contiguous) RAM space of up to 26 bytes is reserved for all constants and variables, and the
stack used by all the CPU-self test routines.
The instruction cycle counts listed here include the instruction cycles required by the CALL and RETURN
instructions for each function call, as well as the cycles needed to save and restore the registers used in
these functions.
The Flash memory usage listed for this test subset includes an Interrupt Service Routine that is shared
between test subsets 6 and 7.
DS52076A-page 22
 2012 Microchip Technology Inc.
Test Software Subsets
TABLE 3-6:
RESOURCE REQUIREMENTS FOR THE dsPIC33EP64MC506 DEVICE
Test Subset
Instruction Cycles(3)
RAM (bytes)
Flash (bytes)
1
105
6
246
2
111
30
219
3
173
78
300
4
105
4
279
5
125
2
249
6
135
12
147(4)
7
177
44
279
Note 1:
2:
3:
4:
8
144
42
246
Total
1075
120(1,2)
1965
In addition, a minimum stack size of 98 bytes must be specified in the Linker settings, to support the
execution of the 16-bit CPU Self-test Library routines.
A total (non-contiguous) RAM space of up to 26 bytes is reserved for all constants and variables, and the
stack used by all the CPU-self test routines.
The instruction cycle counts listed here include the instruction cycles required by the CALL and RETURN
instructions for each function call, as well as the cycles needed to save and restore the registers used in
these functions.
The Flash memory usage listed for this test subset includes an Interrupt Service Routine that is shared
between test subsets 6 and 7.
 2012 Microchip Technology Inc.
DS52076A-page 23
16-bit CPU Self-test Library User’s Guide
NOTES:
DS52076A-page 24
 2012 Microchip Technology Inc.
16-BIT CPU SELF-TEST LIBRARY
USER’S GUIDE
Chapter 4. Functional Test Coverage
4.1
INSTRUCTION SET
The instruction classes tested by the CPU Self-Test Library include the types of
instructions:
•
•
•
•
•
•
•
•
•
Data Move
Program Flow Change
Stack/Shadow
Control
Math
Logic
Rotate/Shift
Compare/Skip
DSP
Table 4-1 lists all of the instruction variants (each having its own op code) supported by
the 16-bit instruction set, along with the index of the first test subset that exercised and
tested the functionality of the instruction.
Note:
 2012 Microchip Technology Inc.
All instructions tested in test subsets 7 and 8 are those that are supported
by the dsPIC33F/dsPIC33E only, and are not supported by the PIC24H/
PIC24E devices. These DSP operations have been listed under various
other instruction classes based on their functionality.
DS52076A-page 25
16-bit CPU Self-test Library User’s Guide
TABLE 4-1:
SUPPORTED 16-BIT INSTRUCTION SET
Applies To:
Instruction Set
PIC24H/PIC24E
Test Subset
dsPIC33F/dsPIC33E Coverage
Instruction Class – MOVE
EXCH
Wns, Wnd
X
X
1
MOV
f
X
X
1
MOV
f, Wreg
X
X
1
MOV
Wreg, f
X
X
1
MOV
f, Wnd
X
X
1
MOV
Wns, f
X
X
1
MOV.b
#Lit8, Wnd
X
X
1
MOV
#Lit16, Wnd
X
X
1
MOV
[Ws+Slit10], Wnd
X
X
1
MOV
Wns, [Ws+SLit10]
X
X
1
MOV
Ws, Wd
X
X
1
MOV.D
Ws, Wnd
X
X
1
MOV.D
Wns, Wd
X
X
1
MOVPAG
#lit0, DSRPAG
(1)
X
X(1)
2
MOVPAG
#lit7, DSWPAG
X(1)
X(1)
2
MOVPAG
#lit8, TBLPAG
(1)
X
X(1)
2
MOVPAG
Wn, DSRPAG
X(1)
X(1)
2
MOVPAG
Wn, DSWPAG
X(1)
X(1)
2
MOVPAG
Wn, TBLPAG
X(1)
X(1)
2
SWAP
Wn
X
X
1
TBLRDH
Ws, Wd
X
X
2
TBLRDL
Ws, Wd
X
X
2
TBLWTH
Ws, Wd
X
X
N/A
TBLWTL
Ws, Wd
X
X
N/A
MOVAC
Acc, Wx, Wxd, Wy, Wyd, AWB
N/A
X
7
SAC
Acc, #SLit4, Wdo
N/A
X
7
SAC.R
Acc, #SLit4, Wdo
N/A
X
7
LAC
Wso, #SLit4, Acc
N/A
X
7
Instruction Class – BIT
BCLR
f, #bit4
X
X
3
BCLR
Ws, #bit4
X
X
1
BSET
f, #bit4
X
X
1
BSET
Ws, #bit4
X
X
1
BSW.C
Ws, Wb
X
X
1
BSW
Ws, Wb
X
X
1
BTG
f, #bit4
X
X
1
BTG
Ws, #bit4
X
X
1
BTST
f, #bit4
X
X
1
BTST.C
Ws, #bit4
X
X
1
Ws, #bit4
X
X
1
BTST.Z
Note 1:
2:
This instruction is available in dsPIC33E and PIC24E devices only.
Accumulator A or B can used as the destination register in dsPIC33E devices only.
DS52076A-page 26
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-1:
SUPPORTED 16-BIT INSTRUCTION SET (CONTINUED)
Applies To:
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subset
Coverage
Instruction Set
BTST.C
Ws, Wb
X
X
1
BTST.Z
Ws, Wb
X
X
1
BTSTS
f, #bit4
X
X
1
BTSTS.C
Ws, #bit4
X
X
1
BTSTS.Z
Ws, #bit4
X
X
1
FBCL
Ws, Wnd
X
X
1
FFIL
Ws, Wnd
X
X
1
FFIR
Ws, Wnd
X
X
1
Instruction Class – MATH
ADD
f, Wreg
X
X
3
ADD
f
X
X
5
ADD
#Lit10, Wn
X
X
3
ADD
Wb, #Lit5, Wd
X
X
5
ADD
Wb, Ws, Wd
X
X
3
ADD
Acc
N/A
X
7
ADD
Wso, #SLit4, Acc
N/A
X
7
ADDC
f, Wreg
X
X
5
ADDC
f
X
X
5
ADDC
#Lit10, Wn
X
X
5
ADDC
Wb, Ws, Wd
X
X
5
ADDC
Wb, #Lit5, Wd
X
X
5
DAW.B
Wn
X
X
5
DEC
f
X
X
5
DEC
f, Wreg
X
X
5
DEC
Ws, Wd
X
X
3
DEC2
f
X
X
5
DEC2
f, Wreg
X
X
5
DEC2
Ws, Wd
X
X
5
DIV.S
Wm, Wn
X
X
6
DIV.SD
Wm, Wn
X
X
6
DIV.U
Wm, Wn
X
X
6
DIV.UD
Wm, Wn
X
X
5
DIVF
Wm, Wn
X
X
8
INC
f
X
X
5
INC
f, Wreg
X
X
5
INC
Ws, Wd
X
X
5
INC2
f
X
X
5
INC2
f, Wreg
X
X
5
INC2
Ws, Wd
X
X
5
MUL
f
X
X
6
MUL.SS
Wb, Ws, Wd/Acc(2)
X
X
5
X
X
5
MUL.SU
Note 1:
2:
Wb,#Lit5, Wnd/Acc
(2)
This instruction is available in dsPIC33E and PIC24E devices only.
Accumulator A or B can used as the destination register in dsPIC33E devices only.
 2012 Microchip Technology Inc.
DS52076A-page 27
16-bit CPU Self-test Library User’s Guide
TABLE 4-1:
SUPPORTED 16-BIT INSTRUCTION SET (CONTINUED)
Applies To:
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subset
Coverage
Instruction Set
MUL.SU
Wb, Ws, Wnd/Acc(2)
X
X
5
MUL.US
(2)
Wb, Ws, Wnd/Acc
X
X
5
MUL.UU
Wb,#Lit5, Wnd/Acc(2)
X
X
5
(2)
MUL.UU
Wb, Ws, Wnd/Acc
X
X
5
MULW.SS
Wb, Ws, Wnd
X(1)
X(1)
—
MULW.SU
Wb, Ws, Wnd
X(1)
X(1)
—
(1)
X(1)
—
(1)
(1)
MULW.SU
Wb, #lit5, Wnd
X
MULW.US
Wb, Ws, Wnd
X
X
—
MULW.UU
Wb, Ws, Wnd
X(1)
X(1)
—
(1)
(1)
—
MULW.UU
Wb, #lit5, Wnd
X
MPY
Wm*Wn, Acc, Wxd, Wy, Wyd
N/A
X
X
7
MPY
Wm*Wm, Acc, Wxd, Wy, Wyd
N/A
X
7
MPY.N
Wm*Wn, Acc, Wxd, Wy, Wyd
N/A
X
7
MSC
Wm*Wm, Acc, Wxd, Wy, Wyd, AWB
N/A
X
7
MAC
Wm*Wm, Acc, Wxd, Wy, Wyd, AWB
N/A
X
7
MAC
Wm*Wn, Acc, Wxd, Wy, Wyd, AWB
N/A
X
7
SE
Ws, Wnd
X
X
5
SUB
f, Wreg
X
X
5
SUB
#Lit10, Wn
X
X
5
SUB
Wb, #Lit5, Wd
X
X
5
SUB
Wb, Ws, Wd
X
X
4
SUB
Acc
N/A
X
7
SUB
f
X
X
5
SUBB
f, Wreg
X
X
5
SUBB
#Lit10, Wn
X
X
5
SUBB
Wb, #Lit5, Wd
X
X
5
SUBB
Wb, Ws, Wd
X
X
5
SUBB
f
X
X
5
SUBBR
f, Wreg
X
X
5
SUBBR
Wb, #Lit5, Wd
X
X
5
SUBBR
Wb, Ws, Wd
X
X
5
SUBBR
f
X
X
5
SUBR
f, Wreg
X
X
5
SUBR
Wb, #Lit5, Wd
X
X
5
SUBR
Wb, Ws, Wd
X
X
5
SUBR
f
X
X
5
ZE
Ws, Wnd
X
X
5
ED
Wm*Wm, Acc, Wx, Wy, Wxd
N/A
X
7
EDAC
Wm*Wm, Acc, Wx, Wy, Wxd
N/A
X
7
Note 1:
2:
This instruction is available in dsPIC33E and PIC24E devices only.
Accumulator A or B can used as the destination register in dsPIC33E devices only.
DS52076A-page 28
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-1:
SUPPORTED 16-BIT INSTRUCTION SET (CONTINUED)
Applies To:
dsPIC33F/dsPIC33E
Test Subset
Coverage
Instruction Set
PIC24H/PIC24E
Instruction Class – LOGIC
AND
f, Wreg
X
X
3
AND
#Lit10, Wn
X
X
4
AND
Wb, #Lit5, Wd
X
X
4
AND
Wb, Ws, Wd
X
X
4
AND
f
X
X
1
CLR
f
X
X
4
CLR
Wreg
X
X
3
CLR
Wd
X
X
4
CLR
Acc, Wx, Wxd, Wy, Wyd, AWB
N/A
X
7
COM
f
X
X
4
COM
f, Wreg
X
X
4
COM
Ws, Wd
X
X
4
IOR
f
X
X
4
IOR
f, Wreg
X
X
4
IOR
#Lit10, Wn
X
X
4
IOR
Wb, #Lit5, Wd
X
X
4
IOR
Wb, Ws, Wd
X
X
4
NEG
f
X
X
4
NEG
f, Wreg
X
X
4
NEG
Ws, Wd
X
X
4
NEG
Acc
N/A
X
7
SETM
f
X
X
4
SETM
Wreg
X
X
4
SETM
Wd
X
X
4
XOR
f
X
X
4
XOR
f, Wreg
X
X
4
XOR
#Lit10, Wn
X
X
4
XOR
Wb, #Lit5, Wd
X
X
4
XOR
Wb, Ws, Wd
X
X
4
Instruction Class – ROTATE/SHIFT
ASR
f, Wreg
X
X
4
ASR
Ws, Wd
X
X
4
ASR
Wb, #Lit4, Wnd
X
X
4
ASR
Wb, Wns, Wnd
X
X
4
ASR
f
X
X
4
LSR
f, Wreg
X
X
4
LSR
Ws, Wd
X
X
4
LSR
Wb, #Lit4, Wnd
X
X
4
LSR
Wb, Wns, Wnd
X
X
4
LSR
f
X
X
4
Note 1:
2:
This instruction is available in dsPIC33E and PIC24E devices only.
Accumulator A or B can used as the destination register in dsPIC33E devices only.
 2012 Microchip Technology Inc.
DS52076A-page 29
16-bit CPU Self-test Library User’s Guide
TABLE 4-1:
SUPPORTED 16-BIT INSTRUCTION SET (CONTINUED)
Applies To:
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subset
Coverage
Instruction Set
RLC
f, Wreg
X
X
4
RLC
Ws, Wd
X
X
4
RLC
f
X
X
4
RLNC
f, Wreg
X
X
4
RLNC
Ws, Wd
X
X
4
RLNC
f
X
X
4
RRC
f, Wreg
X
X
4
RRC
Ws, Wd
X
X
4
RRC
f
X
X
4
RRNC
f, Wreg
X
X
4
RRNC
Ws, Wd
X
X
4
RRNC
f
X
X
4
SL
f, Wreg
X
X
4
SL
Ws,Wd
X
X
4
SL
Wb, #Lit4, Wnd
X
X
4
SL
Wb, Wns, Wnd
X
X
4
SL
f
X
X
4
SFTAC
Acc, Wn
N/A
X
7
SFTAC
Acc, #SLit6
N/A
X
7
Instruction Class – COMPARE/SKIP
BTSC
f, #bit4
X
X
1
BTSC
Ws, #bit4
X
X
1
BTSS
f, #bit4
X
X
1
BTSS
Ws, #bit4
X
X
1
CP
f
X
X
4
CP
Wb, #Lit5
X
X
4
CP
Wb, Ws
X
X
4
CP0
f
X
X
4
CP0
Ws
X
X
4
CPB
f
X
X
4
CPB
Wb, #Lit5
X
X
4
CPB
Wb, Ws
X
X
4
CPBEQ
Wb, Wn, Expr
X(1)
X(1)
—
CPBGT
Wb, Wn, Expr
X(1)
X(1)
—
Wb, Wn, Expr
X(1)
X(1)
—
CPBNE
Wb, Wn, Expr
(1)
X(1)
—
CPSEQ
Wb, Ws
X
X
4
CPSGT
Wb, Wn
X
X
4
CPSLT
Wb, Wn
X
X
4
Wb, Wn
X
X
4
CPBLT
CPSNE
Note 1:
2:
X
This instruction is available in dsPIC33E and PIC24E devices only.
Accumulator A or B can used as the destination register in dsPIC33E devices only.
DS52076A-page 30
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-1:
SUPPORTED 16-BIT INSTRUCTION SET (CONTINUED)
Applies To:
dsPIC33F/dsPIC33E
Test Subset
Coverage
Instruction Set
PIC24H/PIC24E
Instruction Class – PROGRAM FLOW
BRA
Expr
X
X
3
BRA
Wn
X
X
3
BRA
C, Expr
X
X
3
BRA
GE, Expr
X
X
3
BRA
GEU, Expr
X
X
3
BRA
GT, Expr
X
X
3
BRA
GTU, Expr
X
X
3
BRA
LE, Expr
X
X
3
BRA
LEU, Expr
X
X
3
BRA
LT, Expr
X
X
3
BRA
LTU, Expr
X
X
3
BRA
N, Expr
X
X
3
BRA
NC, Expr
X
X
3
BRA
NN, Expr
X
X
3
BRA
NOV, Expr
X
X
3
BRA
NZ, Expr
X
X
3
BRA
OA, Expr
N/A
X
7
BRA
OB, Expr
N/A
X
7
BRA
OV, Expr
X
X
3
BRA
SA, Expr
N/A
X
7
BRA
SB, Expr
N/A
X
7
BRA
Z, Expr
X
X
3
CALL
Expr
X
X
3
CALL
Wn
X
X
3
CALL.L
Wn
(1)
X(1)
—
GOTO
Expr
X
3
X
X
GOTO
Wn
X
X
3
GOTO.L
Wn
X(1)
X(1)
—
RCALL
Expr
X
X
3
RCALL
Wn
X
X
3
REPEAT
#Lit14
X
X
5
REPEAT
Wn
X
X
6
X
X
3
X
X
3
X
X
3
RETFIE
RETLW
#Lit10, Wn
RETURN
Instruction Class – SHADOW/STACK
LNK
#Lit14
X
X
3
POP
f
X
X
3
POP
Wd
X
X
3
POP.D
Wnd
X
X
3
Note 1:
2:
This instruction is available in dsPIC33E and PIC24E devices only.
Accumulator A or B can used as the destination register in dsPIC33E devices only.
 2012 Microchip Technology Inc.
DS52076A-page 31
16-bit CPU Self-test Library User’s Guide
TABLE 4-1:
SUPPORTED 16-BIT INSTRUCTION SET (CONTINUED)
Applies To:
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subset
Coverage
X
X
3
Instruction Set
POP.S
PUSH
f
X
X
3
PUSH
Ws
X
X
3
PUSH.D
Wns
X
X
3
PUSH.S
X
X
3
ULNK
X
X
3
X
X
N/A
X
X
3
NOP
X
X
3
NOPR
X
X
3
X
X
N/A
X
X
N/A
Instruction Class – CONTROL
CLRWDT
DISI
PWRSAV
#Lit14
#Lit1
RESET
DO
#Lit4, Expr
N/A
X
8
DO
Wn, Expr
N/A
X
7
Note 1:
2:
This instruction is available in dsPIC33E and PIC24E devices only.
Accumulator A or B can used as the destination register in dsPIC33E devices only.
DS52076A-page 32
 2012 Microchip Technology Inc.
Functional Test Coverage
4.1.1
Methodology for Assessing the Functional Test Coverage for
CPU Instructions
The entire set of instruction variants were listed in the matrix in Table 4-1 and counted.
Then, the instructions tested by at least one test subset were counted based on code
inspection. The percentage test coverage is then given by:
[(Tested Instructions / Available Instructions)] * 100
The only instructions that are not tested are those that disrupt the real-time nature of
the application, such as operations that cause a device Reset (CLRWDT and RESET),
reprogram Flash Memory (TBLWTL and TBLWTH), or put the device in Sleep or Idle mode
(PWRSAV).
If these five instructions are excluded from the assessment of instruction test coverage,
the test coverage for CPU instructions is 100% for dsPIC33F/PIC24H devices and
95.1% for dsPIC33E/PIC24E devices.
4.2
ADDRESSING MODES
The addressing modes tested by the 16-bit CPU Self-test Library include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Register Direct Addressing
File Register (Memory Direct) Addressing
Register Indirect Addressing
Register Indirect Addressing with pre-increment
Register Indirect Addressing with post-increment
Register Indirect Addressing with pre-decrement
Register Indirect Addressing with post-decrement
Register Indirect Addressing with literal offset
Register Indirect Addressing with register offset
Immediate Addressing
Program Space Visibility (PSV)
Table Addressing
DSP Register Indirect with special post-increment/post-decrement and register
offset modes (dsPIC33F/dsPIC33E only)
• Modulo Addressing (dsPIC33F/dsPIC33E only)
• Bit-reversed Addressing (dsPIC33F/dsPIC33E only)
Data widths that are supported by the CPU are Byte (8 bits), Word (16 bits), and
Double-word (32 bits). Each of these have been explicitly tested.
Table 4-2 lists all of the addressing modes supported by the 16-bit architecture, along
with the index of the first test subset that exercised and tested the functionality of the
instruction.
Note:
 2012 Microchip Technology Inc.
All addressing modes tested in test subsets 7 and 8 are those that are supported by dsPIC33F/dsPIC33E devices only and are not supported by
PIC24H/PIC24E devices.
DS52076A-page 33
16-bit CPU Self-test Library User’s Guide
TABLE 4-2:
SUPPORTED 16-BIT ADDRESSING MODES
Applies to:
Addressing Mode
PIC24H/PIC24E
Test Subset
dsPIC33F/dsPIC33E Coverage
Register Direct
X
X
1
Memory Direct
X
X
1
Register Indirect
Pre-Increment
X
X
1
Post-Increment
X
X
1
Pre-Decrement
X
X
1
Post-Decrement
X
X
1
Register Offset
X
X
1
Literal Offset
X
X
1
No Modification
X
X
1
Immediate
X
X
1
Byte Addressing
X
X
1
Double-word Addressing
X
X
1
PSV
X
X
2
Table
X
X
2
Post-Increment by 2
N/A
X
7
Post-Increment by 4
N/A
X
7
Post-Increment by 6
N/A
X
7
Post-Decrement by 2
N/A
X
7
Post-Decrement by 4
N/A
X
7
Post-Decrement by 6
N/A
X
7
Register Offset (Indexed)
N/A
X
7
No Modification
N/A
X
7
Direct Addressing
N/A
X
7
Indirect with Post-Increment
N/A
X
7
MAC Register Indirect
Accumulator Write Back
Modulo Addressing (Byte Mode)
N/A
X
8
Modulo Addressing (Word Mode)
N/A
X
8
Bit Reversed Addressing
N/A
X
8
DS52076A-page 34
 2012 Microchip Technology Inc.
Functional Test Coverage
4.2.1
Methodology for Assessing the Functional Test Coverage for
CPU Addressing Modes
The entire set of addressing mode variants were listed in the matrix in Table 4-1 and
counted. Then, the addressing modes tested by at least one test subset were counted
based on code inspection. The percentage test coverage is then given by:
[(Tested Addressing Modes / Available Addressing Modes)] * 100
The test coverage for CPU addressing modes is 100% ( [(27/27)*100] ).
4.3
CPU REGISTERS
The SFRs tested by the 16-bit CPU Self-test Library include:
•
•
•
•
•
•
•
•
•
•
•
•
•
Working Registers (W0 through W15)
Stack Pointer Limit Register (SPLIM)
Table Page Register (TBLPAG)
Program Space Visibility Page Register (PSVPAG) (dsPIC33F/PIC24H only) or
Data Space Read Page Register (DSRPAG) (dsPIC33E/PIC24E only)
Core Control Register (CORCON)
CPU Status Register (SR)
Interrupt Control Register 2 (INTCON2)
Modulo Addressing Control Register (MODCON) (dsPIC33F/dsPIC33E only)
X-RAM Modulo Buffer Start Address Register (dsPIC33F/dsPIC33E only)
X-RAM Modulo Buffer End Address Register (dsPIC33F/dsPIC33E only)
Y-RAM Modulo Buffer Start Address Register (dsPIC33F/dsPIC33E only)
Y-RAM Modulo Buffer End Address Register (dsPIC33F/dsPIC33E only)
Bit-reversed Addressing Control Register (XBREV) (dsPIC33F/dsPIC33E only)
Each control bit present in the above registers has been exercised and tested for both
set (‘1’) and clear (‘0’) states.
Table 4-3 lists all of the CPU-related registers in the 16-bit architecture, including the
bits present therein, along with the test subset that first exercised each.
Note:
 2012 Microchip Technology Inc.
All registers or bits tested in test subsets 7 and 8 are those that are supported by dsPIC33F/dsPIC33E devices only and are not supported by
PIC24H/PIC24E devices.
DS52076A-page 35
16-bit CPU Self-test Library User’s Guide
TABLE 4-3:
SUPPORTED 16-BIT CPU REGISTERS
Applies To:
Test
Subset
dsPIC33F/dsPIC33E Coverage
Bit
Number
Bit Name
W0
—
—
X
X
1
W1
—
—
X
X
1
W2
—
—
X
X
1
W3
—
—
X
X
1
W4
—
—
X
X
1
W5
—
—
X
X
1
W6
—
—
X
X
1
W7
—
—
X
X
1
W8
—
—
X
X
2
W9
—
—
X
X
2
W10
—
—
X
X
2
W11
—
—
X
X
2
W12
—
—
X
X
2
W13
—
—
X
X
2
W14
—
—
X
X
2
W15
—
—
X
X
2
Register Name
PIC24H/PIC24E
SPLIM
—
—
X
X
2
TBLPAG
—
—
X
X
2
PSVPAG or DSRPAG
—
—
X
X
2
DSWPAG (dsPIC33E/PIC24E)
—
—
X
X
-
CORCON
DS52076A-page 36
bit 0
IF
N/A
X
7
bit 1
RND
N/A
X
7
bit 2
PSV or SFA
X
X
2
(PSV only)
bit 3
IPL3
X
X
6
bit 4
ACCSAT
N/A
X
7
bit 5
SATDW
N/A
X
7
bit 6
SATB
N/A
X
7
bit 7
SATA
N/A
X
7
bit 8-10
DL
N/A
X
7
bit 11
EDT
N/A
X
7
bit 12
US
N/A
X
7
bit 13-15
Unimplemented
N/A
N/A
N/A
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-3:
SUPPORTED 16-BIT CPU REGISTERS (CONTINUED)
Register Name
SR
INTCON2
MODCON
Applies To:
Bit
Number
bit 0
Bit Name
PIC24H/PIC24E
C
X
Test
Subset
dsPIC33F/dsPIC33E Coverage
X
2
bit 1
Z
X
X
2
bit 2
OV
X
X
2
bit 3
N
X
X
2
bit 4
RA
X
X
5
bit 7-5
IPL
X
X
3
bit 8
DC
X
X
5
bit 9
DA
N/A
X
7
bit 10
SAB
N/A
X
7
bit 11
OAB
N/A
X
7
bit 12
SB
N/A
X
7
bit 13
SA
N/A
X
7
bit 14
OB
N/A
X
7
bit 15
OA
N/A
X
7
bit 0
INT0EP
X
X
N/A
bit 1
INT1EP
X
X
N/A
bit 2
INT2EP
X
X
N/A
bit 3
INT3EP
X
X
N/A
bit 4
INT4EP
X
X
N/A
bit 5-13
Unimplemented
N/A
N/A
N/A
bit 14
DISI
X
X
3
bit 15
ALTIVT
X
X
3
bits 0-3
XWM
X
X
8
bits 4-7
YWM
N/A
X
8
bits 8-11
BWM
N/A
X
8
bits 12-13 Unimplemented
N/A
N/A
N/A
bit 14
YMODEN
N/A
X
8
bit 15
XMODEN
X
X
8
X
X
8
XMODSRT
—
—
XMODEND
—
—
X
X
8
YMODSRT
—
—
N/A
X
8
YMODEND
XBREV
ACCA
 2012 Microchip Technology Inc.
—
—
bits 0-14
BWM
bit 15
BREN
N/A
X
8
N/A
X
8
N/A
X
8
bit 39
—
N/A
X
7
bit 38
—
N/A
X
7
bit 37
—
N/A
X
7
bit 36
—
N/A
X
7
bit 35
—
N/A
X
7
bit 34
—
N/A
X
7
bit 33
—
N/A
X
7
bit 32
—
N/A
X
7
bit 31
—
N/A
X
7
DS52076A-page 37
16-bit CPU Self-test Library User’s Guide
TABLE 4-3:
SUPPORTED 16-BIT CPU REGISTERS (CONTINUED)
Register Name
ACCA
ACCB
DS52076A-page 38
Bit
Number
Applies To:
Bit Name
PIC24H/PIC24E
Test
Subset
dsPIC33F/dsPIC33E Coverage
bit 30
—
N/A
X
7
bit 29
—
N/A
X
7
bit 28
—
N/A
X
7
bit 27
—
N/A
X
7
bit 26
—
N/A
X
7
bit 25
—
N/A
X
7
bit 24
—
N/A
X
7
bit 23
—
N/A
X
7
bit 22
—
N/A
X
7
bit 21
—
N/A
X
7
bit 20
—
N/A
X
7
bit 19
—
N/A
X
7
bit 18
—
N/A
X
7
bit 17
—
N/A
X
7
bit 16
—
N/A
X
7
bit 15
—
N/A
X
7
bit 14
—
N/A
X
7
bit 13
—
N/A
X
7
bit 12
—
N/A
X
7
bit 11
—
N/A
X
7
bit 10
—
N/A
X
7
bit 9
—
N/A
X
7
bit 8
—
N/A
X
7
bit 7
—
N/A
X
7
bit 6
—
N/A
X
7
bit 5
—
N/A
X
7
bit 4
—
N/A
X
7
bit 3
—
N/A
X
7
bit 2
—
N/A
X
7
bit 1
—
N/A
X
7
bit 0
—
N/A
X
7
bit 39
—
N/A
X
7
bit 38
—
N/A
X
7
bit 37
—
N/A
X
7
bit 36
—
N/A
X
7
bit 35
—
N/A
X
7
bit 34
—
N/A
X
7
bit 33
—
N/A
X
7
bit 32
—
N/A
X
7
bit 31
—
N/A
X
7
bit 30
—
N/A
X
7
bit 29
—
N/A
X
7
bit 28
—
N/A
X
7
bit 27
—
N/A
X
7
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-3:
SUPPORTED 16-BIT CPU REGISTERS (CONTINUED)
Bit
Number
Register Name
ACCB
4.3.1
Applies To:
Bit Name
PIC24H/PIC24E
Test
Subset
dsPIC33F/dsPIC33E Coverage
bit 26
—
N/A
X
7
bit 25
—
N/A
X
7
bit 24
—
N/A
X
7
bit 23
—
N/A
X
7
bit 22
—
N/A
X
7
bit 21
—
N/A
X
7
bit 20
—
N/A
X
7
bit 19
—
N/A
X
7
bit 18
—
N/A
X
7
bit 17
—
N/A
X
7
bit 16
—
N/A
X
7
bit 15
—
N/A
X
7
bit 14
—
N/A
X
7
bit 13
—
N/A
X
7
bit 12
—
N/A
X
7
bit 11
—
N/A
X
7
bit 10
—
N/A
X
7
bit 9
—
N/A
X
7
bit 8
—
N/A
X
7
bit 7
—
N/A
X
7
bit 6
—
N/A
X
7
bit 5
—
N/A
X
7
bit 4
—
N/A
X
7
bit 3
—
N/A
X
7
bit 2
—
N/A
X
7
bit 1
—
N/A
X
7
bit 0
—
N/A
X
—
Methodology for Assessing the Functional Test Coverage for
CPU Registers and Bits
The entire set of CPU-related registers, and any individual bits therein, were listed in
the matrix and counted. For registers such as XMODSRT, for which the individual bits
are not relevant, only the registers are listed and counted. Then, the registers (or
wherever applicable, register bits) tested by at least one test subset were counted
based on code inspection. The percentage test coverage is then given by:
[(Tested Registers or Bits / Available Registers or Bits)] * 100
The test coverage for CPU registers is 99.3% ( [(134/135)*100] )for dsPIC33F/PIC24H
devices and 98.5% ( [(133/135)*100] ) for dsPIC33E/PIC24E devices.
 2012 Microchip Technology Inc.
DS52076A-page 39
16-bit CPU Self-test Library User’s Guide
4.4
BUS STRUCTURES
The bus structures tested by the 16-bit CPU Self-test Library include:
•
•
•
•
•
•
•
•
Program Memory Address
Program Memory Data Read
X Data Memory Read Address
X Data Memory Read Data
X Data Memory Write Address
X Data Memory Write Data
Y Data Memory Read Address
Y Data Memory Read Data
Each bit present in the buses listed above has been exercised and tested for both set
(‘1’) and clear (‘0’) states.
Table 4-4 lists all of the bus structures in the 16-bit architecture, including all of the bits
present therein, along with the test subset that first exercised each.
Note:
TABLE 4-4:
All buses tested in test subsets 7 and 8 are those that are supported by
dsPIC33F/dsPIC33E devices only and are not supported by PIC24H/
PIC24E devices.
SUPPORTED 16-BIT BUS STRUCTURES
Applies To:
Bus Structure
Program Memory Address Bus
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
DS52076A-page 40
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subject
Coverage
0
X
X
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
X
X
2
State
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-4:
SUPPORTED 16-BIT BUS STRUCTURES (CONTINUED)
Applies To:
Bus Structure
Program Memory Address Bus
Bit #
12
13
14
15
16
17
18
19
20
21
22
23
Program Memory Data Read Bus
0
1
2
3
4
5
6
7
8
9
 2012 Microchip Technology Inc.
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subject
Coverage
0
X
X
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
X
X
2
State
DS52076A-page 41
16-bit CPU Self-test Library User’s Guide
TABLE 4-4:
SUPPORTED 16-BIT BUS STRUCTURES (CONTINUED)
Applies To:
Bus Structure
Program Memory Data Read Bus
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subject
Coverage
0
X
X
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
N/A
X
N/A
X
N/A
2
N/A
0
0
1
X
X
X
X
2
2
1
0
1
X
X
X
X
2
2
2
0
1
X
X
X
X
2
2
3
0
1
X
X
X
X
2
2
4
0
1
X
X
X
X
2
2
5
0
1
X
X
X
X
2
2
6
0
1
X
X
X
X
2
2
7
0
1
X
X
X
X
2
2
8
0
1
X
X
X
X
2
2
9
0
1
X
X
X
X
2
2
10
0
1
X
X
X
X
2
2
11
0
1
X
X
X
X
2
2
12
0
1
X
X
X
X
2
2
13
0
1
X
X
X
X
2
2
14
0
1
X
X
X
X
2
2
15
0
1
X
X
X
X
2
2
Bit #
10
11
12
13
14
15
Program Memory Data Write Bus
X Data Memory Read Address Bus
DS52076A-page 42
N/A
State
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-4:
SUPPORTED 16-BIT BUS STRUCTURES (CONTINUED)
Applies To:
Bus Structure
X Data Memory Read Data Bus
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subject
Coverage
0
X
X
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
0
1
0
X
X
X
X
2
2
1
1
0
X
X
X
X
2
2
2
1
0
X
X
X
X
2
2
3
1
0
X
X
X
X
2
2
4
1
0
X
X
X
X
2
2
5
1
0
X
X
X
X
2
2
6
1
0
X
X
X
X
2
2
1
X
X
2
Bit #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
X Data Memory Write Address Bus
 2012 Microchip Technology Inc.
State
DS52076A-page 43
16-bit CPU Self-test Library User’s Guide
TABLE 4-4:
SUPPORTED 16-BIT BUS STRUCTURES (CONTINUED)
Applies To:
Bus Structure
X Data Memory Write Address Bus
Bit #
7
8
9
10
11
12
13
14
15
X Data Memory Write Data Bus
0
1
2
3
4
5
6
7
8
9
10
11
12
13
DS52076A-page 44
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subject
Coverage
0
X
X
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
0
X
X
X
X
2
2
1
X
X
2
State
 2012 Microchip Technology Inc.
Functional Test Coverage
TABLE 4-4:
SUPPORTED 16-BIT BUS STRUCTURES (CONTINUED)
Applies To:
Bus Structure
X Data Memory Write Data Bus
Bit #
14
15
Y Data Memory Read Address Bus
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Y Data Memory Read Data Bus
0
1
2
3
4
 2012 Microchip Technology Inc.
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subject
Coverage
0
X
X
2
1
0
X
X
X
X
2
2
1
0
X
N/A
X
X
2
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
N/A
X
7
State
DS52076A-page 45
16-bit CPU Self-test Library User’s Guide
TABLE 4-4:
SUPPORTED 16-BIT BUS STRUCTURES (CONTINUED)
Applies To:
Bus Structure
Bit #
Y Data Memory Read Data Bus
5
6
7
8
9
10
11
12
13
14
15
4.4.1
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subject
Coverage
0
N/A
X
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
0
N/A
N/A
X
X
7
7
1
N/A
X
7
State
Methodology for Assessing the Functional Test Coverage for
Bus Structures and Bus Bit-lines
The entire set of bus structures, and any individual bits therein, were listed in the matrix
and counted for both ‘0’ and ‘1’ conditions. The Program Memory Write Bus was not
included in the count as program Flash memory reprogramming operations cannot be
exercised due to real-time application constraints. Then, the bus bit-lines tested by at
least one test subset were counted based on code inspection. The percentage test
coverage is then given by:
[(Tested Bus Bit States / Available Bus Bit States)] * 100.
The test coverage for bus structures is 100% ( [(256/256)*100] ).
DS52076A-page 46
 2012 Microchip Technology Inc.
Functional Test Coverage
4.5
CPU HARDWARE UNITS
The CPU hardware units tested by the CPU Self-Test Library include:
• Arithmetic and Logic Unit (ALU)
• Multiplier
• Divider
• Data Shifter
• Stack Control
• Interrupt Controller
• Trap Controller
• Program Memory Control
• Data Memory Control
• Instruction Decoding and Control
• X Read Address Generator Unit
• X Write Address Generator Unit
• Y Read Address Generator Unit (dsPIC33F/dsPIC33E only)
• DSP Adder/Subtractor (dsPIC33F/dsPIC33E only)
• DSP Saturation Logic (dsPIC33F/dsPIC33E only)
• DSP Overflow Logic (dsPIC33F/dsPIC33E only)
• DSP Rounding Logic (dsPIC33F/dsPIC33E only)
Table 4-5 lists each of the CPU hardware modules in the 16-bit architecture, along with
all the test subsets that tested them.
Note:
TABLE 4-5:
All hardware modules tested in test subsets 7 and 8 are those that are
supported by dsPIC33F/dsPIC33E devices only and are not supported by
PIC24H/PIC24E devices.
SUPPORTED 16-BIT CPU HARDWARE MODULES
Hardware Module
Item Number
(see Figure 4-1
and Figure 4-2)
Module Name
Applies To:
PIC24H/PIC24E
dsPIC33F/dsPIC33E
Test Subset
Coverage
5, 6
1
Arithmetic and Logic Unit (ALU)
X
X
2
Multiplier
X
X
6, 7
3
Divider
X
X
5, 6, 8
4
Data Shifter
X
X
4, 7
5
DSP Adder/Subtractor
N/A
X
7
6
DSP Saturation Logic
N/A
X
7
7
DSP Overflow Logic
N/A
X
7
8
DSP Rounding Logic
N/A
X
7
9
Stack Control Logic
X
X
3
10
Interrupt Controller
X
X
3
11
Trap Controller
X
X
6
12
Program Memory Control
X
X
2, 3
13
Data Memory Control
X
X
1, 2
14
Program Memory Data Access
X
X
2
15
Instruction Decoding and Control
X
X
All
16
X Read Address Generator Unit
X
X
2
17
X Write Address Generator Unit
X
X
2
18
Y Read Address Generator Unit
N/A
X
7
 2012 Microchip Technology Inc.
DS52076A-page 47
16-bit CPU Self-test Library User’s Guide
4.5.1
Methodology for Assessing the Functional Test Coverage for
CPU Hardware Modules
The entire set of CPU hardware modules were listed in the matrix and counted. Then,
the hardware units tested by at least one test subset were counted based on code
inspection. The percentage test coverage is then given by:
[(Tested CPU Hardware Modules / Available CPU Hardware Modules)] * 100.
The test coverage for bus structures is 100% ( [(17/17)*100] ).
Figure 4-1 and Figure 4-2 provide CPU block diagrams from the
“dsPIC33FJXXXGPX06/X08/X10 Data Sheet” (DS70286) and the
“PIC24HJXXXGPX06/X08/X10 Data Sheet” (DS70175), with labels correlating to the
item numbers listed in Table 4-5.
FIGURE 4-1:
14
dsPIC33FJXXXGPX06/X08/X10 CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
10 11
23
23
8
16
16
16
16
Data Latch
Data Latch
X RAM
Y RAM
Address
Latch
Address
Latch 13
12 PCU
9
PCH PCL
Program Counter
Loop
Stack
Control 12
Control
Logic
Logic
13
DMA
RAM
(see Note 1)
16
23
16
16
DMA
Controller
(see Note 1)
Address Generator Units
Address Latch
16 17
12
18
Program Memory
EA MUX
13
15
Data Latch
ROM Latch
24
Instruction
Decode &
Control
15 Instruction Reg
2
Control Signals
to Various Blocks
4
Literal Data
15
16
16
16
5
DSP Engine
(see Note 3)
6
3
7
8
Divide Support
16 x 16
W Register Array
(see Note 2)
1
16
16-bit ALU
16
Note
1:
2:
3:
DS52076A-page 48
DMA is linked to peripherals and is not tested.
W registers are tested as part of the register and instruction tests.
The Multiplier logic, though represented as a part of the DSP Engine, is present on both
dsPIC33F/dsPIC33E and PIC24H/PIC24E devices.
To Peripheral Modules
 2012 Microchip Technology Inc.
Functional Test Coverage
FIGURE 4-2:
14
PIC24HJXXXGPX06/X08/X10 CPU CORE BLOCK DIAGRAM
PSV & Table
Data Access
Control Block
X Data Bus
Interrupt
Controller
10 11
8
16
16
16
Data Latch
23
23
12 PCU
9
PCH PCL
Program Counter
Loop
Stack
Control 12
Control
Logic
Logic
DMA
RAM
(see Note 1)
X RAM
13
16
Address
Latch
23
16
DMA
Controller
(see Note 1)
Address Generator Units
Address Latch
16 17
12
Program Memory
EA MUX
13
15
Data Latch
ROM Latch
24
Instruction
Decode &
Control
15 Instruction Reg
2
Control Signals
to Various Blocks
Literal Data
15
16
16
16
4
17 x 17
Multiplier
3
Divide Support
16 x 16
W Register Array
(see Note 2)
1
16
16-bit ALU
16
Note
1:
2:
DMA is linked to peripherals and is not tested.
W registers are tested as part of the register and instruction tests.
 2012 Microchip Technology Inc.
To Peripheral Modules
DS52076A-page 49
16-bit CPU Self-test Library User’s Guide
NOTES:
DS52076A-page 50
 2012 Microchip Technology Inc.
NOTES:
 2012 Microchip Technology Inc.
DS52076A-page 51
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Osaka
Tel: 81-66-152-7160
Fax: 81-66-152-9310
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Santa Clara
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
DS52076A-page 52
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
11/29/11
 2012 Microchip Technology Inc.
Similar pages