AK4145ET

[AKD4145-A]
AKD4145-A
Evaluation board Rev.3 for AK4145
GENERAL DESCRIPTION
The AKD4145 is an evaluation board for the AK4145, BTSC Encoder with D/A Converter, which is
optimized for Digital AV application. The AKD4145 has the analog/digital audio interface and can
achieve the interface with analog/digital audio systems via BNC/OPT-connector.
„ Ordering guide
AKD4145-A
---
Evaluation board for AK4145
(Cable for connecting with printer port of IBM-AT,compatible PC and control software are
packed with this. This control software does not support Windows NT.)
FUNCTION
• ADC with analog input
• DIR with optical input
• 10pin Header for digital audio I/F and serial control I/F
12V
Logic1
Logic2
DGND
(3.3V) (3.3V~1.8V) (0V)
5V
AGND
(0V)
AVDD
(3.3V)
DVDD
TVDD
(1.8V) (3.3V~1.8V)
T1:5V=>3.3V
T2:3.3V=>1.8V
T3:12V=>5V
Regulator
For
74AVC8T245
74HC14
74LVC07
AK4114
For OP-Amp
AINL
AK5357
(ADC)
OP-Amp
AK4145
AINR
Composite
Audio
(Encoder)
Video / 27M
Opt In
AK4114
(DIR)
X’tal
COAX
PORT1
PORT2
DSP
DATA
Serial
Control
Figure. 1 AKD4145 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual
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Evaluation Board Manual
„ Operation sequence
1) Set up the power supply lines.
(1-1) In case of using the regulator.<Default>
Set up the jumper pins.
JP
JP13
AVDD-SEL
JP14
DVDD-SEL
JP15
TVDD-SEL
JP17
Logic2-SEL
JP18
Logic1-SEL
JP22
5V-REG
JP23
3.3V-REG
State
REG(3.3V)
REG(1.8V)
REG(3.3V)
TVDD
REG(3.3V)
Short
REG(3.3V)
Set up the power supply lines.
[REG(12V)] (red)
= +12V
: for regulator and OP-Amp
[REG(5V)] (red)
= open
: “5V” is supplied from Regulator (T3)
[AVDD] (orange)
= open
: “3.3V” is supplied from Regulator (T1)
[DVDD] (orange)
= open
: “1.8V” is supplied from Regulator (T2)
[TVDD] (orange)
= open
: “3.3V” is supplied from Regulator (T1)
[Logic1] (orange)
= open
: “3.3V” is supplied from Regulator (T1)
[Logic2] (orange)
= open
: “3.3V” is supplied from Regulator (T1)
[AGND] (black)
= 0V
: analog ground
[DGND] (black)
= 0V
: digital ground
(Note) VA and VD of AK5357 (ADC) is supplied “3.3V” from regulator (T1).
(1-2) In case of using the power supply connectors.
Set up the jumper pins.
JP
JP13
AVDD-SEL
JP14
DVDD-SEL
JP15
TVDD-SEL
JP17
Logic2-SEL
JP18
Logic1-SEL
JP22
5V-REG
JP23
3.3V-REG
State
TM
TM
TM
TM
TM
Open
TM
Set up the power supply lines.
[REG(12V)] (red)
= +12V
: for OP-Amp
[REG(5V)] (red)
= +5V
: for regulator (T1, T2)
[AVDD] (orange)
= +2.7~3.6V : for AVDD of AK4145 (typ. 3.3V)
[DVDD] (orange)
= +1.7~1.9V : for DVDD of AK4145 (typ. 1.8V)
[TVDD] (orange)
= +1.7~3.6V : for TVDD of AK4145 (typ. 3.3V)
[Logic1] (orange)
= +2.7~3.6V : for logic (typ. 3.3V)
[Logic2] (orange)
= +1.7~3.6V : for logic of I/F (typ. 3.3V : the voltage same as TVDD)
[AGND] (black)
= 0V
: analog ground
[DGND] (black)
= 0V
: digital ground
(Note) VA and VD of AK5357 (ADC) is supplied “3.3V” from regulator (T1).
2) Set up the jumper pins and switches. (See the followings.)
3) Power on.
SW1 (AK4145), SW2 (ADC) and SW3 (DIR) should be reset once bringing toggle SW “L” upon
power-up. Please refer to Talble.1 on page.3 about setting of toggle SW.
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„ Setting of the toggle SW
No.
Name
Function
SW1
PDN-AK4145
SW2
PDN-ADC
SW3
PDN-DIR
PDN SW of AK4145 (U2).
Keep “H” during normal operation.
PDN SW of AK5357 (U1).
Keep “H” during normal operation.
Keep “L” when AK5357 is not used.
PDN SW of AK4114 (U4).
Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
Table. 1 Setting of the toggle SW
„ Indication for LED
[LED1] (INT) : Monitor INT0 pin of the DIR (AK4114). LED turns on when PLL of the AK4114 is unlocked.
„ Setting of jumper pins
No
Name
1
Serial
2
AMP
3
CA
4
I2S
6
RX
7
DIF/SCL
8
FS/SDA
9
DIR-SDTI
10
DIR-LRCK
Function
AK4145 Control Mode
Open : Parallel Control. <Default>
Short : Serial Control.
Output of OP-Amp
Open : Out of use.
Short : Connected. <Default>
Output of CA
THR : Out of use.
AMP : Amplify CA with OP-Amp <Default>
Audio I/F of AK5357 (ADC)
Open : 24bit MSB justified.
Short : 24bit I2S Compatible. <Default>
RX input of AK4114 (DIR)
OPT : Optical (PORT1). <Default>
BNC : BNC RX (J6).
Selection of AK4145’s DIF/SCL pin
DIF: DIF in parallel mode. <Default>
SCL:SCL in serial mode.
Selection of AK4145’s FS/SDA pin
FS: FS in parallel mode. <Default>
SDA : SDA in serial mode.
Input of AK4145’s SDTI
Open : PORT2.
SDTI : DIR. <Default>
Input of AK4145’s LRCK
Open : PORT2.
Short : DIR. <Default>
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11
DIR-BICK
12
DIR-MCLK
13
AVDD-SEL
14
DVDD-SEL
15
TVDD-SEL
16
GND
17
Logic2-SEL
18
Logic1-SEL
22
5V-REG
23
3.3V-REG
Input of AK4145’s BICK
Open : PORT2.
Short : DIR. <Default>
Input of AK4145’s MCLK
Open : PORT2.
Short : DIR. <Default>
Power supply of AK4145’s AVDD
REG(3.3V) : AVDD is supplied from regulator (T1). <Default>
TM : AVDD is supplied from “AVDD” connector.
Power supply of AK4145’s DVDD
REG(1.8V) : DVDD is supplied from regulator (T2). <Default>
TM : DVDD is supplied from “DVDD” connector.
Power supply of AK4145’s TVDD
DVDD : TVDD is supplied from DVDD. <Default>
REG(3.3V) : TVDD is supplied from regulator (T1).
TM : TVDD is supplied from “TVDD” connector.
Analog GND and Digital GND
Open : Separated.
Short : Common. <Default>
Power supply of logic2
TVDD: Logic2 is supplied from TVDD. <Default>
TM : Logic2 is supplied from “Logic2” connector.
Power supply of logic1
REG(3.3V) : Logic1 is supplied from regulator (T1). <Default>
TM : Logic1 is supplied from “Logic1” connector.
Power supply of regulator (T1)
Open : It is supplied from “REG-5V” connector.
Short : It is supplied from regulator (T3). <Default>
Power supply of regulator (T2)
REG(3.3V) : It is supplied from regulator (T3). <Default>
TM : It is supplied from “REG-5V” connector.
Table. 2 Setting of jumper pins
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„ Evaluation mode
Control Mode
The supporting control mode is as follows.
1.
2.
Parallel Mode <Default>
Serial Mode
1. Parallel Mode <Default>
(1-1) Set up the jumper pins.
JP1
Serial
JP8
FS/SDA
JP7
SCL/DIF
SCL
DIF
FS
SDA
(1-2) Set up the DIP SW (S3).
S3
DIF ( Audio I/F )
FS ( Sampling Rate )
L
24bit MSB Justified
32kHz
H
16/24bit I2S Compatible <Default>
48kHz <Default>
Table. 3 Setting of AK4145’s Parallel Mode
2. Serial Mode
(2-1) Set up the jumper pins.
JP1
Serial
JP8
FS/SDA
JP7
SCL/DIF
SCL
DIF
FS
SDA
(2-2) Connect of the 10 wire flat cable.
GND
GND
GND
10
GND
PORT3
uP I/F
GND
The AK4145 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3
(CTRL) with PC by 10 wire flat cable packed with the AKD4145.
6
CCLK
CSN
CDTI
CDTO
1
NC
Red
5
Figure. 2 Connect of 10 wire flat cable
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Measurement Mode
The supporting measurement mode is as follows.
1.
2.
3.
Evaluation using DIR of AK4114 <Default>
Evaluation using ADC of AK5357
All interface signals are fed externally
1. Evaluation using DIR of AK4114 <Default>
Measurement path :
Optical connector (PORT1) or BNC (J6) → DIR (AK4114) → AK4145
Please supply biphase signal to Optical connector (PORT1) or BNC connector (J6). DIR generates MCLK, BICK,
LRCK, and SDTI from received data.
(1-1) Set up the jumper pins.
JP6 (RX) should be set according to the RX input. Follow is setting example in Optical connector.
JP6
RX
OPT
JP9
DIR-SDTI
JP10
DIR-LRCK
JP11
DIR-BICK
JP12
DIR-MCLK
BNC
(1-2) Set up the DIP SW (S2).
In case of the AK4145 evaluation using the AK4114, it is necessary to correspond to the audio interface format
for AK4145 (SDTI) and AK4114 (SDTO). About AK4145’s audio interface format, refer to datasheet of
AK4145. About AK4114’s audio interface format, refer to Table. 6 on page 8.
(Note) AK4145’s default setting of Audio interface format is I2S Compatible in parallel mode.
S2
DIR-Setting
H
L DIF0 DIF1 DIF2 OCKS1 CM0
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2. Evaluation using ADC of AK5357
Measurement path :
AINL(J3) / AINR (J2) → ADC (AK5357) → DIR (AK4114) → AK4145
Please supply analog signal to AINL (J3) / AINR (J2). DIR generates MCLK, BICK, LRCK, and SDTI from
received data via AK5357’s ADC. X’tal (12.288MHz) on the board is used as AK4114’s reference clock.
(2-1) Set up the jumper pins.
JP4 is setting of AK5357‘s Audio interface format. In case of the AK5357 evaluation using the AK4114, it is
necessary to correspond to the audio interface format for AK5357 (SDTO) and AK4114 (DAUX).
About AK5357’s audio interface format, refer to Table. 4 on this page. About AK4114’s audio interface
format, refer to Table. 6 on page 8.
(Note) AK5357’s default setting of Audio interface format is I2S Compatible.
JP6
RX
OPT
JP9
DIR-SDTI
JP10
DIR-LRCK
JP11
DIR-BICK
JP12
DIR-MCLK
JP4
I2S
BNC
JP4 I2S
Open
Short
24bit MSB Justified
I2S Compatible
<Default>
Table. 4 ADC Output Audio Interface Format Setting
(2-2) Set up the DIP SW (S2).
In case of the AK4145 evaluation using the AK4114, it is necessary to correspond to the audio interface format
for AK4145 (SDTI) and AK4114 (SDTO). About AK4145’s audio interface format, refer to datasheet of
AK4145. About AK4114’s audio interface format, refer to Table. 6 on page 8.
(Note) AK4145’s default setting of Audio interface format is I2S Compatible in parallel mode.
S2
DIR-Setting
H
L DIF0 DIF1 DIF2 OCKS1 CM0
3. All interface signals are fed externally
Measurement path :
PORT2 → AK4145
Please supply MCLK, BICK, LRCK and SDTI to PORT2.
(3-1) Set up the jumper pins.
JP9
DIR-SDTI
JP10
DIR-LRCK
JP11
DIR-BICK
JP12
DIR-MCLK
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„ Setting of DIP SW
No.
Name
1
2
3
4
5
ON (“H”)
DIF0
DIF1
DIF2
OCKS1
CM0
OFF (“L”)
Output Audio Interface Format : refer to Table. 6
Master Clock Frequency Setting : refer to Table. 7
Clock Mode Setting : refer to Table. 8
Default
H
L
H
L
L
Table. 5 AK4114 Mode Setting
DIF2
DIF1
DIF0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
DAUX
SDTO
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
LRCK
BICK
H/L
H/L
H/L
H/L
H/L
L/H
64fs
64fs
64fs
64fs
64fs
64fs
Table. 6 AK4114 Audio Data Format
OCKS1
MCKO1
L
H
256fs
512fs
Table. 7 AK4114 Master Clock Output Frequency
CM0
PLL
Clock Souce
SDTO
L
H
ON
OFF
PLL
X’tal
RX
DAUX
Table. 8 AK4114 Clock Operation Mode
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„ Baseband Composite Audio signal output circuit
12V
R37
47k
C58 22u
+
C59
0.1u
C57
0.1u
C56+
10u
R38
47k
3
C60
10u
+
VR1
50k
2
8
1
7
6
5
C3 22u
JP3
Baseband Composite Audio
CA
AMP
R36 10k
U10
+VP
AOUT
BOUT
-AIN
-BIN
+AIN
+BIN
-VP
1
2
3
JP2
AMP
R2
220
4
NJM4580
THR
R46
47k
J4
CA
C4
open
Figure. 3 Baseband Composite Audio signal output circuit
1. In case of amplification using the OP-Amp. <Default>
The stereo separation can be maximized by adjusting the variable resistor (VR1).
The jumper pins should be set as follows.
JP2
AMP
JP3
CA
AMP
THR
2. In case of through.
This mode is out of use.
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Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4145-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4145-A by 10-line type flat cable (packed with AKD4145-A).
Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software
is used on Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device
control software”. In case of Windows95/98/ME, this installation is not needed. This control software does not
operate on Windows NT.)
3. Insert the CD-ROM labeled “AK4145-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “akd4145.exe” to set up the control program.
5. Then please evaluate according to the follows.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
3. Click “Write default” button
„ Explanation of each buttons
[Port Reset] :
[Write default] :
[All Write] :
[All Read] :
[Function1] :
[Function2] :
[Function3] :
[Function4] :
[Function5]:
[SAVE] :
[OPEN] :
[Write] :
[Read]:
Set up the USB interface board (AKDUSBIF-A) .
Initialize the register of AK4145.
Write all registers that is currently displayed.
Read all registers of the AK4145.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
Dialog to read data by mouse operation.
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”.
Blank is the part that is not defined in the datasheet.
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„ Explanation of each dialog
1. [Write Dialog] : Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4145, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4145, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DVOL
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to AK4145 by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4145, click [OK] button. If not, click [Cancel] button.
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4. [Save] and [Open]
4-1. [Save]
Save the current register setting data. The extension of file name is “akr”.
<Operation flow>
(1) Click [Save] Button.
(2) Set the file name and push [Save] Button. The extension of file name is “akr”.
4-2. [Open]
The register setting data saved by [Save] is written to AK4145. The file type is the same as [Save].
<Operation flow>
(1) Click [Open] Button.
(2) Select the file (*.akr) and Click [Open] Button.
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5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be
paused.
(3) Click [Start] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused
step.
This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of
file name is “aks”.
Figure. 4 Window of [F3]
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6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked,
the window as shown in Figure. 5 opens.
Figure. 5 [F4] window
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6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks).
The sequence file name is displayed as shown in Figure. 6
Figure. 6 [F4] window (2)
(2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4.
[OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
6-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
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7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed.
When [F5] button is clicked, the following window as shown in Figure. 7 opens.
Figure. 7 [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure. 8
(2) Click [WRITE] button, then the register setting is executed.
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Figure. 8 [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5.
[OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in
order to reflect the change.
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MEASUREMENT RESULTS
[Measurement condition]
• Measurement unit
• MCLK
• BICK
• fs
• Bit
• Power Supply
• Temperature
: Audio Precision, System Two Cascade
BELAR TV DIGITAL SETEREO MONITOR TVM-230
: 256fs
: 64fs
: 48kHz
: 24bit
: AVDD = TVDD = 3.3V, DVDD = 1.8V
: Room
[Measurement Results]
Parameter
S/(N+D)
(−1dB Input, 1kHz)
S/N
(Input off, A-weighting)
Stereo Separation
(-1dB Input, 1kHz)
Result (Lch / Rch)
Mono
Stereo
Mono
Stereo
-79.5
-77.9 / -78.5
-80.9
-81.3 / -81.3
Stereo
49.4 / 48.5
Unit
dB
dB
dB
[Performance Plots]
Stereo :
Figure. 9
Figure. 10
Figure. 11
Figure. 12
Figure. 13
Figure. 14
Figure. 15
:
:
:
:
:
:
:
THD+N vs. Input Level (1kHz)
THD+N vs. Input Frequency (-15dB)
Linearity (1kHz)
Frequency Response (-15dB)
Separation (Left Channel = Off, Right Channel = -15dB)
FFT Plot (-1dB)
FFT Plot (No Signal)
:
:
:
:
:
:
THD+N vs. Input Level (1kHz)
THD+N vs. Input Frequency (-15dB)
Linearity (1kHz)
Frequency Response (-15dB)
FFT Plot (-1dB)
FFT Plot (No Signal)
Mono :
Figure. 16
Figure. 17
Figure. 18
Figure. 19
Figure. 20
Figure. 21
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[Stereo]
THD + N vs Input Level
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure. 9 Stereo mode
THD + N vs.
Input Level (fin=1kHz)
THD + N vs Input Frequency
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
20
50
100
200
500
1k
2k
5k
10k
Hz
Figure. 10 Stereo mode
THD + N vs. Input Frequency (-15dB)
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Linearity
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure. 11 Stereo mode Linearity (fin=1kHz)
AKM
Frequency Response
-10
-11
-12
-13
d
B
r
-14
A
-16
-15
-17
-18
-19
-20
20
50
100
200
500
1k
2k
5k
10k
Hz
Figure. 12 Stereo mode
Frequency Response (-15dB)
< KM090003>
2008/08
- 20 -
[AKD4145-A]
AKM
Stereo Separation (Lch Off, Rch -15dB)
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
20
50
100
200
500
1k
2k
5k
10k
Hz
Figure. 13 Stereo Separation (Lch Off, Rch -15dB)
FFT (-1dB)
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure. 14 Stereo mode
< KM090003>
FFT Plot (-1dB)
2008/08
- 21 -
[AKD4145-A]
FFT (No Signal)
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure. 15 Stereo mode
FFT Plot (No Signal)
< KM090003>
2008/08
- 22 -
[AKD4145-A]
[Mono]
THD + N vs Input Level
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure. 16
Mono mode THD + N vs. Input Level (fin=1kHz)
THD + N vs Input Frequency
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
20
50
100
200
500
1k
2k
5k
10k
Hz
Figure. 17
Mono mode THD + N vs. Input Frequency (-15dB)
< KM090003>
2008/08
- 23 -
[AKD4145-A]
Linearity
+0
-10
-20
-30
d
B
r
-40
A
-60
-50
-70
-80
-90
-100
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBr
Figure. 18
AKM
Mono mode Linearity (fin=1kHz)
Frequency Response
-10
-11
-12
-13
d
B
r
-14
A
-16
-15
-17
-18
-19
-20
20
50
100
200
500
1k
2k
5k
10k
Hz
Figure. 19
Mono mode Frequency Response (-15dB)
< KM090003>
2008/08
- 24 -
[AKD4145-A]
FFT (-1dB)
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
5k
10k
20k
5k
10k
20k
Hz
Figure. 20
Mono mode FFT Plot (-1dB)
FFT (No Signal)
+0
-20
-40
-60
d
B
r
-80
-100
A
-120
-140
-160
-180
20
50
100
200
500
1k
2k
Hz
Figure. 21
Mono mode FFT Plot (No Signal)
< KM090003>
2008/08
- 25 -
[AKD4145-A]
Revision History
Date
(yy/mm/dd)
07/09/07
Manual
Board
Revision
Revision
KM090000
0
Reason
KM090001
1
Change
08/06/05
KM090002
2
Change
Change
Change
Change
KM090003
3
Contents
First Edition
08/03/10
08/08/18
Page
Change
Change
Device revision was changed. Rev.A → Rev.B
18-25 Table data and Plot data were changed.
Device revision was changed. Rev.B → Rev.C
18-25 Table data and Plot data were changed.
Default setting of Audio I/F was changed.
3-8
MSB Justified → I2S Compatible
Circuit diagram was changed.
27
R47 was added. (P/S pin Pull up)
18-25 Table data and Plot data were changed.
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application
or use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support,
or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the
use approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or
perform may reasonably be expected to result in loss of life or in significant injury or damage to person or
property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and
the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless
from any and all claims arising from the use of said product in the absence of such notification.
< KM090003>
2008/08
- 26 -
A
B
C
U1
+
J3
AINL
AINR
CKS0
16
CKS2
15
DIF
14
12V
JP4
I2S
2
AINL
3
CKS1
C59 0.1u
AGND
SCLK
12
VA
MCLK
11
AK5357
R32 51
JP1
Serial
VD
10
SDTO
9
DGND
R10
+
OPT
5
JP3 CA
THR
R36
10k
E
R2
220
J4
CA
R46
47k
C4
open
AMP
C9
4.7n
22u
1
1
FILT
2
2
3
K
A
R4
16
16
P/S
AVDD
15
15
CV27M
VCOM
14
L
C17
0.1u
H
R7
SW1
PDN-4145
4145-MCLK
5
4145-LRCK
6
4145-BICK
7
VSS
13
10u+
C13
AVDD
14
D
DVDD
13
C16
0.1u
AK4145
5
MCLK
DVDD
12
6
LRCK
TVDD
11
11
7
BICK
DIF/SCL
10
10
8
SDTI
FS/SDA
9
9
12
C18
0.1u
51
R9
DIR-AVDD
PDN
51
R8
C12
0.1u
C14
0.1u
4
CN2
C3
CA
51
4
74HC14
TVDD
51
R11 51
AK4114
INT0
OCKS0/CSN
OCKS1/CCLK
CM1/CDTI
CM0/CDTO
PDN
XTI
XTO
DAUX
MCKO2
BICK
SDTO
36
35
34
33
32
31
30
29
28
27
26
25
OCKS1
A
CM0
K
K
LED1
INT
XTI
XTO
R15
1k
14
Vcc
C27
0.1u
7
L
R40
100k
16pin_R
H
8
9
10
11
12
13
SCL
R16
10k
DIF
D3
HSU119
GND
C30
10u
+
C31
0.1u
74HC14
C29
0.1u
SW2
PDN-ADC
L
H
47k
Logic2
S3
C
4
3
4145-Pararel
SW3
PDN-DIR
SDA
FS
JP8
R29
47k
R30
47k
FS/SDA
C32
0.1u
+
OCKS1
CM0
JP7
DIF/SCL
DIF 1
FS 2
13
14
15
16
17
18
19
20
21
22
23
24
2
C28
0.1u
4Y
4A
5Y
5A
6Y
6A
K
U4
TVDD
DVSS
TX0
TX1
BOUT
COUT
UOUT
VOUT
DVDD
DVSS
MCKO1
LRCK
DIR-Setting
IPS0/RX4
AVSS
DIF0/RX5
TEST2
DIF1/RX6
AVSS
DIF2/RX7
IPS1/IIC
P/SN
XTL0
XTL1
VIN
1A
1Y
2A
2Y
3A
3Y
A
10
9
8
7
6
16pin_L
U5
1
2
3
4
5
6
1
1
2
3
4
5
6
7
8
9
10
11
12
S2
8
R14
10k
A
RX3
AVSS
RX2
TEST1
RX1
AVSS
RX0
AVSS
VCOM
R
AVDD
INT1
48
47
46
45
44
43
42
41
40
39
38
37
D2
HSU119
3
C26
10u
4145-SDTI
2
C25
0.1u
+
R12
18k
Logic1
0.1u
5
4
3
2
1
VR1
50k
2
U2
3
D1
HSU119
1
2
GND
X1
12.288MHz
JP6
RX
Logic1
C
+BIN
C22
0.47u
C24
DIF0 1
DIF1 2
DIF2 3
OCKS14
CM0 5
-BIN
-VP
C11 0.1u
R5
10k
3
7
C15
0.1u
BNC
R13
75
Vcc
8
9
10
11
12
13
1
XTO
2
C20
+ 10u
470
RX
14
4Y
4A
5Y
5A
6Y
6A
C23 5p
TORX141
J6
BNC RX
1A
1Y
2A
2Y
3A
3Y
2
1
C19
0.1u
XTI
1
2
3
4
5
6
1
3
2
1
+AIN
R47
47k
3
VCC
4
1
+
Logic1
JP2
AMP
TVDD
C21 5p
GND
OUT
7
6
CN1
R41 51
U3
L1 47u
BOUT
-AIN
+
LRCK
C10
0.1u
8
PORT1
3
Logic2
R34 51
7
R38
47k
C58 22u
R33 51
6
R3
5.1
D
+VP
NJM4580
C7
0.1u
C8
open +
AOUT
8
3
+
5
C6
10u
13
C5
0.47u
+
ADC-VA
PDN
VCOM
C56
10u+
U10
1
2
4
RP2
C57
0.1u
R39 47k
C2
10u
R1
75
R37
47k
C60 10u
+
E
J1
CV27M
C1
10u
1
E
+
J2
AINR
D
ADC-VA
C33
10u
Logic1
Logic2
U7
Logic1
Logic2
U8
R42 51
DIR
PORT
JP9
3
DIR-SDTI
B
R43 51
DIR
PORT
DIR
PORT
JP11
DIR
PORT
JP12
PORT2
MCLK 1
BICK 3
LRCK 5
SDTI 7
VCC 9
2
4
6
8
10
B2
20
5
A3
B3
19
6
A4
B4
18
7
A5
B5
17
8
A6
B6
16
DIR-BICK
9
A7
B7
15
10
A8
B8
14
2
DIR
OE
22
DIR-MCLK
DSP
C35
0.1u
Logic1
10k
Logic1
PORT3
A
10
8
6
4
2
9
7
5
3
1
4145-SDTI
4145-LRCK
4145-BICK
R18
10k
SCL
SDA
SDA (ACK) R23
51
R19
10k
R21
R22
CTRL
Logic1
1A
2A
3A
4A
5A
6A
14
GND
12
GND
24
VCCB
23
GND
13
21
B2
20
A3
B3
19
6
A4
B4
18
7
A5
B5
17
8
B
A6
B6
16
9
A7
B7
15
10
A8
B8
14
2
DIR
OE
22
1
VCCA
VCCB
24
SCL
C34
0.1u
C37
0.1u
11
GND
12
GND
VCCB
23
GND
13
C36
0.1u
74AVC8T245
1Y
2Y
3Y
4Y
5Y
6Y
2
4
6
8
10
12
A
Vcc
C38
0.1u
7
Title
GND
74LVC07
A
B1
A2
5
R20
1k
U9
1
3
5
9
11
13
11
VCCB
A1
4
74AVC8T245
Logic2
470
470
VCCA
3
4145-MCLK
GND
GND
1
R17
21
A2
DIR-LRCK
R45 51
B1
4
JP10
R44 51
A1
B
Size
C
- 27 -
D
AKD4145-A
Document Number
A2
Main
Date:
Monday, August 18, 2008
E
Rev
3
Sheet
1
of
2
A
B
C
D
E
12V
2
+
C39
47u
1
ADC-VA
C41+
0.1u
GND
IN
OUT
(short)
C42
47u
3
C45
0.1u
2
C44
0.1u
TM
REG(3.3V)
2
+
1
2
+
JP14
REG(1.8V)
C48
47u
TM
DVDD-SEL
2
(short)
JP15
DVDD
REG(3.3V)
TM
L4
1
1
1
+
2
B
C49
47u
JP16
GND
+
2
T45_OR
2
TVDD-SEL
(short)
JP17
TVDD
L5
C50
47u
TM
2
(short)
+
2
A
1
1
T45_OR
C51
47u
R25
DVDD
(short)
R26
TVDD
(short)
TM
Logic1-SEL
2
(short)
R27
Logic2
Logic2-SEL
JP18
REG(3.3V)
L6
1
C
AVDD
(short)
B
1
1
1
R24
C47
47u
1
1
47u
TM
AVDD-SEL
1
1
2
+ C46
JP13
REG(3.3V)
L3
T45_OR
DGND1
R31
D
1
T45_OR
LOGIC1
5V-->3.3V
2
L2
(short)
T45_OR
LOGIC2
OUT
E
JP23
T2
3.3V-REG LT1963AEST-1.8 3.3V-->1.8V
1
TVDD1
2
C40
0.1u
+C43
47u
DVDD1
IN
+C52
47u
C54
0.1u
1
D
AVDD1
3
2
1
T45_BK
C
OUT
T1
TA48M033F
JP22
5V-REG
1
T45_RED
AGND1
IN
C55
0.1u
GND
C53 +
47u
3
E
REG(5V)1
1
1
T45_RED
1
REG(12V)1
GND
T3
NJM78M05FA 12V-->5V
(short)
R28
Logic1
(short)
R35
A
DIR-AVDD
1
(short)
T45_BK
Title
Size
A3
Date:
A
B
C
- 28 -
D
AKD4145-A
Document Number
Rev
Main-Power Supply
Monday, August 18, 2008
Sheet
E
2
3
of
2
- 29 -
- 30 -
- 31 -
- 32 -
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