AK4647VQ

ASAHI KASEI
[AKD4647-A]
AKD4647-A
Evaluation board Rev.0 for AK4647
GENERAL DESCRIPTION
AKD4647 is an evaluation board for the AK4647, stereo CODEC with built-in MIC/HP amplifier. The
AKD4647 can evaluate A/D converter and D/A converter separately in addition to loopback mode (A/D →
D/A). The AKD4647 also has the digital audio interface and can achieve the interface with digital audio
systems via opt-connector.
„ Ordering guide
AKD4647
---
Evaluation board for AK4647
(Cable for connecting with printer port of IBM-AT,compatible PC and control
software are packed with this. This control software does not support Windows NT.)
FUNCTION
• DIT/DIR with optical input/output
• BNC connector for an external clock input
• 10pin Header for serial control mode
2.6 ~ 3.6V 2.6 ~ 3.6V 2.6 ~ 5.25V
AVDD
DVDD
GND
PORT4
HVDD
Control Data
MIC
10pin Header
MIN
PORT3
LineIn
DSP
AK4647
10pin Header
HP
PORT1
Opt In
AK4114
LINE
OUT
Opt out
PORT2
LVC_VDD VD_VDD
Clock
Gen
1.6 ~ 3.6V
2.7 ~ 3.6V
Figure 1. AKD4647 Block Diagram
* Circuit diagram and PCB layout are attached at the end of this manual
<KM098600>
2009/1
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ASAHI KASEI
[AKD4647-A]
Board Outline Chart
„ Outline Chart
DGND
VD_IN
LVC_IN
10 9 8 7 6
PORT1
TORX141
TVDD
DVDD
AVDD
AGND
REG
PORT4
CDTO/SDA(ACK)
SW1
L
CSN
SW2
CDTI/SDA
H
L
T1
JP1
TA48033F
S1
L
H
H
CCLK/SCL
1 2 3 4 5
DIR
J9
LIN1/RIN1
7
PDN
1
CN2
37
48
1
10
BICK 2
9
LRCK 3
8
SDTI 4
7
VCC 5
U5
AK4114
12
13
1
25
24
J3
LIN
48
14
1
6
PORT3
12
13
36
8
MCLK 1
U8
74LVC07
U1
AK4647
J5
RIN
20
CN4
U7
24
25
37
36
74LVC541
J7
MIN
No Used
11
DGND
J6
LOUT
AGND
(GND)
(SPN)
(SPP)
10
CN1
CN3
J8
ROUT
1 3 2
PORT2
TOTX141
J10
SPK
J11
EXT
J4
HPR
J2
HPL/R
J1
HPL
HVDD
No Used
Figure 1. AKD4647-A Outline Chart
„ Comment
(1) J2, J9 (3.5 mini-JACK)
J2 (HPL/HPR) : It is analog signal output mini-Jack. The signal is output from HPL/HPR pins.
J9 (LIN1/RIN1) : It is analog signal input mini-Jack. The signal is input to LIN1/RIN1 pins via J2 mini-JACK.
(2) J1, J3, J4, J5, J7, J6, J8, J11 (BNC-JACK)
J1/J4 (HPL/HPR) : It is analog signal output Jack. The signal is output from HPL/HPR pins.
J3/J5 (LIN/RIN) : It is analog signal input Jack. The signal is input to LIN2/RIN2 pins via J3/J5 BNC-JACK.
J6/J8 (LOUT/ROUT) : It is analog signal output Jack. The signal is output from LOUT/ROUT pins.
J7(MIN) : No used.
J11(EXT) : It is supplied an external clock through Jack.
(3) J10 (XLR connector)
J10 (SPK) : No used.
(4) PORT1, PORT2, PORT3 (Digital signal connector)
PORT1 (Optical Connecter): Optical digital signal is input to the AK4114.
PORT2 (Optical Connecter): Optical digital signal is output to the AK4114.
PORT3 (10 pin header): The clock and data can be input and output with this connector.
(5) PORT4 (10 pin header)
Control port. Connect the bundled cable into this port.
<KM098600>
2009/1
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ASAHI KASEI
[AKD4647-A]
(6) REG, AVDD, DVDD, TVDD, HVDD, LVC_IN, VD_IN, AGND, DGND
These are the power supply connectors. Connect power supply with these pins.
As for the detail comments, refer to the setup of power supply on the next page.
(7) SW1, SW2, S1 (Switch)
SW1: Reset of AK4114. Keep “H” during normal operation.
SW2: Reset of AK4647. Keep “H” during normal operation.
S1: Setting of audio serial interface format and frequency of MCKO that is output from AK4114.
<KM098600>
2009/1
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ASAHI KASEI
[AKD4647-A]
„ Operation sequence
1) Set up the power supply lines.
1-1) AVDD, DVDD and HVDD are supplied from the regulator. (AVDD,DVDD and PVDD jacks should be
opened.). See “Other jumper pins set up (page 10)”. <default>
Name
of jack
REG
Color
of jack
Red
Voltage
Range
+5V
AVDD
Orange
DVDD
Orange
HVDD
Orange +2.6∼+5.25V HVDD of AK4647
TVDD
Orange
Using
Default Setting
Should be connected.
+5V
+2.6∼+3.6V
Regulator :
AVDD, DVDD and
HVDD for AK4647.
AVDD of AK4647
Should not be connected. It is must be short of
JP3(AVDD_SEL)
open
+2.6∼+3.6V
DVDD of AK4647
open
AGND
Black
0V
Ground
Should not be connected. It is must be short of
JP6(DVDD_SEL)
Should not be connected. It is must be short of
JP7(REG)
Should not be connected. It is must be open of
JP8(TVDD_SEL)
Should be connected.
Should not be connected. It is must be selected
“VD” of JP10(LVC_SEL)
Should be connected.
DGND
Black
0V
Ground
Should be connected.
LVC_IN Orange
VD_IN Orange
Default
-
No used.
+1.6∼+3.6V
+1.6∼+3.6V
for logic
for AK4114 and logic
open
open
+3.3V
+3.3V
0V
0V
Table 1.Set up of power supply lines
(AVDD, DVDD and HVDD are supplied from the regulator.)
1-2) AVDD, DVDD and HVDD are not supplied from the regulator. (The power is supplied from AVDD, DVDD
and jacks.) See “Other jumper pins set up (page 10)”.
Name
of jack
REG
Color
of jack
Red
Voltage
Range
+5V
AVDD
Orange
DVDD
Orange
HVDD
Orange +2.6∼+5.25V HVDD of AK4647
TVDD
Orange
Using
Default Setting
Should be no connected.
open
+2.6∼+3.6V
Regulator :
AVDD, DVDD and
HVDD for AK4647.
AVDD of AK4647
Should be connected. It is must be open of
JP3(AVDD_SEL)
+3.3V
+2.6∼+3.6V
DVDD of AK4647
+3.3V
AGND
Black
0V
Ground
Should be connected. It is must be open of
JP6(DVDD_SEL)
Should be connected. It is must be open of
JP7(REG)
Should not be connected. It is must be open of
JP8(TVDD_SEL)
Should be connected.
Should not be connected. It is must be selected
“VD” of JP10(LVC_SEL)
Should be connected.
DGND
Black
0V
Ground
Should be connected.
LVC_IN Orange
VD_IN Orange
Default
+1.6∼+3.6V
+1.6∼+3.6V
No used.
for logic
for AK4114 and logic
+3.3V
open
+3.3V
+3.3V
0V
0V
Table 2.Set up of power supply lines
(AVDD, DVDD and HVDD are not supplied from the regulator.)
Each supply line should be distributed from the power supply unit.
<KM098600>
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ASAHI KASEI
[AKD4647-A]
2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.)
3) Power on.
The AK4647 and AK4114 should be reset once bringing SW1 and SW2 “L” upon power-up.
„ Evaluation mode
(1) External Slave Mode
In case of AK4647 evaluation using AK4114, it is necessary to correspond to audio interface format for
AK4647 and AK4114. About AK4647’s audio interface format, refer to datasheet of AK4647. About
AK4114’s audio interface format, refer to Table 2 in this manual.
(1-1) Evaluation of Recording block (MIC, ADC) using DIT of AK4114
(1-2) Evaluation of Playback block (HP, LINEOUT) using DIR of AK4114
(1-3) Evaluation of Loop-back using AK4114 <default>
(1-4) All interface signals including master clock are fed externally.
(1-1) Evaluation of Recording block (MIC, ADC) using DIT of AK4114
PORT2 (DIT) and X1 (X’tal) are used. DIT generates audio bi-phase signal from received data and which is
output through optical connector (TOTX141). Nothing should be connected to PORT1 (DIR) and PORT3 (DSP)
and J11 (EXT). The jumper pins should be set to the following.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
JP21
BICK
State
Short
Open
Open
Open
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
JP29
LRCK
JP30
SDTI
JP19
PHASE
State
Short
Short
Open
Open
JP20
PHASE
DIR
EXT
DIR
4040
DIR
4040
DIR
4040
THR
INV
THR
INV
When AK4114 is used, JP22 (MKFS) and JP23 (BCFS) are not used. Therefore, JP22 (MKFS) should be set to
“x1” and JP23 (BCFS) should be set to “64fs”.
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used.
<KM098600>
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ASAHI KASEI
[AKD4647-A]
(1-2) Evaluation of Playback block (HP, LINEOUT) using DIR of AK4114
PORT1 (DIR) is used. Nothing should be connected to PORT2 (DIT), PORT3 (DSP) and J11 (EXT). The jumper
pins should be set to the following.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
JP21
BICK
State
Short
Open
Open
Open
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
JP29
LRCK
JP30
SDTI
State
Short
Short
Open
Open
JP19
PHASE
JP20
PHASE
DIR
EXT
DIR
4040
DIR
4040
DIR
4040
THR
INV
THR
INV
When AK4114 is used, JP22 (MKFS) and JP23 (BCFS) are not used. Therefore, JP22 (MKFS) should be set to
“x1” and JP23 (BCFS) should be set to “64fs”.
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used.
(1-3) Evaluation of Loop-back using AK4114 <Default>
X’tal oscillator (X1) is used. Nothing should be connected to PORT1 (DIR), PORT3 (DSP) and J11 (EXT). The
jumper pins should be set to the following.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
JP21
BICK
State
Short
Open
Open
Open
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
JP29
LRCK
JP30
SDTI
State
Short
Short
Open
Open
JP19
PHASE
JP20
PHASE
DIR
EXT
DIR
4040
DIR
4040
DIR
4040
THR
INV
THR
INV
When AK4114 is used, JP22 (MKFS) and JP23 (BCFS) are not used. Therefore, JP22 (MKFS) should be set to
“x1” and JP23 (BCFS) should be set to “64fs”.
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used.
<KM098600>
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ASAHI KASEI
[AKD4647-A]
(1-4) All interface signals including master clock are fed externally.
PORT3 (ROM) is used. Nothing should be connected to PORT1 (DIR), PORT2 (DIT), and J11 (EXT). The
jumper pins should be set to the following.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
DIR
EXT
State
Short
Open
Open
Open
4040
JP30
SDTI
JP29
LRCK
JP21
BICK
DIR
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
DIR
4040
DIR
4040
State
Short
Short
Open
Open
JP20
PHASE
JP19
PHASE
THR
INV
THR
INV
When AK4114 is used, JP22 (MKFS) and JP23 (BCFS) are not used. Therefore, JP22 (MKFS) should be set to
“x1” and JP23 (BCFS) should be set to “64fs”.
JP20 (PHASE) is jumper which decides polarity of BICK, “THR” or “INV” should be selected according to the
audio interface format.
(2) PLL Slave Mode
(2-1) Evaluation using MCLK of AK4114
J11 is used. Nothing should be connected to PORT3 (DSP). X’tal oscillator should be removed from X1.
The jumper pins should be set to the following.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
DIR
EXT
JP21
BICK
DIR
4040
State
Open
Short
Open
Open
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
JP30
SDTI
JP29
LRCK
DIR
4040
DIR
4040
State
Short
Short
Open
Open
JP20
PHASE
JP19
PHASE
THR
INV
THR
INV
When AK4114 is used, JP22 (MKFS) and JP23 (BCFS) are not used. Therefore, JP22 (MKFS) should be set to
“x1” and JP23 (BCFS) should be set to “64fs”.
* The AK4114 operates at fs of 32kHz or more. If the fs is slower than 32kHz, this evaluation mode can’t be used.
(3) PLL Master Mode
(3-1) Evaluation of Loop-back using MCLK of AK4114
(3-2) Evaluation of Loop-back using clock fed externally.
(3-3) Evaluation of Internal Loop-back using clock fed externally.(AK4114 is not used)
<KM098600>
2009/1
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ASAHI KASEI
[AKD4647-A]
(3-1) Evaluation of Loop-back using MCLK of AK4114
X’tal oscillator (X1) is used. Nothing should be connected to PORT1 (DIR), PORT3 (DSP) and JP11. The
jumper pins should be set to the following.
Using the AK4647’s internal PLL it is possible to evaluate various sampling frequencies.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
DIR
EXT
JP21
BICK
DIR
4040
State
Short
Open
Short
Short
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
JP30
SDTI
JP29
LRCK
DIR
4040
DIR
4040
State
Open
Open
Short
Short
JP19
PHASE
THR
INV
JP20
PHASE
THR
INV
(3-2) Evaluation of Loop-back using clock is fed externally.
JP11 is used. Nothing should be connected to PORT1(DIR) and PORT3 (DSP). Exclude X’tal oscillator from
X1. The jumper pins should be set to the following.
Using the AK4647’s internal PLL it is possible to evaluate various sampling frequencies.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
DIR
EXT
JP21
BICK
DIR
4040
State
Open
Short
Short
Short
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
JP30
SDTI
JP29
LRCK
DIR
4040
DIR
4040
State
Open
Open
Short
Short
JP19
PHASE
THR
INV
JP20
PHASE
THR
INV
(3-3) Evaluation of Internal Loop-back using clock is fed externally.(AK4114 is not used)
JP11 is used. Nothing should be connected to PORT3 (DSP). The jumper pins should be set to the following.
It can be evaluated at internal loop-back mode (LOOP bit = “1”).
Using the AK4647’s internal PLL it is possible to evaluate various sampling frequencies.
JP name
JP25(EXT)
JP26(4114_MCKI_IN)
JP27(4114BICK_SEL)
JP28(4114LRCK_SEL)
JP24
MCLK
DIR
EXT
JP21
BICK
DIR
4040
State
Open
Open
Open
Open
JP name
JP32(BICK_SEL)
JP33(LRCK_SEL)
JP35(LRCK_MODE)
JP36(BICK_MODE)
JP29
LRCK
DIR
JP30
SDTI
4040
DIR
<KM098600>
4040
State
Open
Open
Open
Open
JP19
PHASE
THR
INV
JP20
PHASE
THR
INV
2009/1
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ASAHI KASEI
[AKD4647-A]
„ DIP Switch set up
[S1] : Mode Setting of AK4114 and AK4647
ON is “H”, OFF is “L”.
No.
1
2
3
Name
DIF0
DIF1
DIF2
ON (“H”)
OFF (“L”)
4
OCKS1
AK4114 Master Clock Setting
See Table 5
OFF
5
6
CAD0
I2C
See Page 11
OFF
OFF
AK4114 Audio Format Setting
See Table 4
default
OFF
OFF
ON
Table 3. Mode Setting for AK4647 and AK4114
DIF2
DIF1
DIF0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AK4114DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
AK4114SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
I/O
O
O
O
O
O
O
I
I
default
Table 4. Setting for AK4114 Audio Interface Format
OCKS1
0
1
MCKO1
256fs
512fs
X’tal
256fs
512fs
default
Table 5. AK4114 Master Clock Setting
<KM098600>
2009/1
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ASAHI KASEI
[AKD4647-A]
„ Other jumper pins set up
[JP1] (GND) : Analog ground and Digital ground
OPEN : Separated.
SHORT : Common. (The connector “DGND” can be open.) <default>
[JP2, 3] on the sub-board : Selection of using MIC-power supply for L/RIN1 path
SHORT : MIC-power is supplied.
OPEN : MIC-power is not supplied.
[JP22] (MKFS) : MCLK Frequency
x1 : 256fs <default>
x2 : 512fs
x4 : 1024fs
[JP23] (BCFS) : BICK Frequency
32fs : 32fs frequency
64fs : 64fs frequency <default>
[JP31] (MODE_SEL) : Serial Control Interface
3-WIRE : 3-WIRE Serial Control Mode <default>
I2C :
I2C-bus Control Mode
[JP34] (DAUX_SEL): Presence of external device connection via PORT3(DSP)
SHORT : connection
OPEN : non-connection <default>
„ The function of the toggle SW
[SW1] (PDN): Power down of AK4647. Keep “H” during normal operation.
[SW2] (DIR):
Power down of AK4114. Keep “H” during normal operation.
Keep “L” when AK4114 is not used.
„ Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114.
<KM098600>
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ASAHI KASEI
[AKD4647-A]
„ Serial Control
The AK4647 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT4
(CTRL) with PC by 10 wire flat cable packed with the AKD4647.Table 3 shows switch and jumper settings for
serial control.
CSN
CCLK/SCI
CDTI/SDA
SDA/(ACK)
Connect
PC
AKD4647
10 wire
flat cable
10pin
Connector
10pin Header
Figure 3. Connect of 10 wire flat cable
S1
Mode
I2C
OFF
ON
ON
3-WIRE
CAD0=0
I2C
CAD0=1
CAD0
OFF
OFF
ON
Table 6. Serial Control Setting
Note. This control software does not support the I2C bus.
<KM098600>
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ASAHI KASEI
[AKD4647-A]
„ Analog Input/Output Circuits
(1) Input Circuits
LIN1/RIN1, LIN2/RIN2 Input Circuit
J9
LIN1/RIN1
C1
1u
C2
1u
RIN1
6
4
3
LIN1
JP2
RIN1
JP3
LIN1
R1
2.2k
R3
2.2k
MPWR
R14
short
JP12
1
C25
1u
LIN3
LIN2
LIN4
LIN2
LIN_SEL
1
TP32
RIN
C27
1u
R17
short
JP14
1
J5
RIN
+
2
3
4
5
1
TP31
LIN
+
2
3
4
5
J3
LIN
RIN3
RIN2
RIN4
RIN2
RIN_SEL
Figure 4. LIN1/RIN1, LIN2/RIN2 Input Circuit
LIN2/RIN2 shares J3/J5.
JP12(LIN_SEL) and JP14(RIN_SEL) select LIN2 and RIN2.
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ASAHI KASEI
[AKD4647-A]
(2) Output Circuits
(2-1)
HP Output Circuit
1
+
BNC
R12
C24
47u
6.8
JP11
HPL
R13
16
2
3
4
5
HP
HPL
J1
HPL
6
J2
HP/LINE
R15
C26
47u
6.8
HP
+
4
3
JP13
HPR
HPR
1
BNC
R16
16
J4
HPR
2
3
4
5
Figure 5. HP Output Circuit
(2-1-1) In case that signal is output from J1 and J4.
JP13
HPR
JP11
HPL
BNC
HP
BNC
HP
(2-1-2) In case that signal is output from J2.
JP13
HPR
JP11
HPL
BNC
HP
BNC
<KM098600>
HP
2009/1
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ASAHI KASEI
(2-2)
[AKD4647-A]
LOUT/ROUT Output Circuit
6
J2
HP/LINE
4
3
R18
open
Mini-Jack
C28
1u
JP15
LOUT_SEL
R19
220
+
BNC
LOUT
1
R20
20k
Mini-Jack
J6
LOUT
2
3
4
5
JP16
ROUT_SEL
C30
1u
R22
220
+
BNC
ROUT
R23
20k
1
J8
ROUT
2
3
4
5
Figure 6. LOUT/ROUT Output Circuit
(2-1-1) In case that signal is output from J6 and J8.
JP16
JP15
LOUT_SEL
BNC
ROUT_SEL
Mini-Jack BNC Mini-Jack
(2-1-1) In case that signal is output from J2.
JP15
LOUT_SEL
BNC
JP16
ROUT_SEL
Mini-Jack BNC Mini-Jack
∗ AKM assumes no responsibility for the trouble when using the above circuit examples.
<KM098600>
2009/1
- 14 -
ASAHI KASEI
[AKD4647-A]
Control Software Manual
„ Set-up of evaluation board and control software
1. Set up the AKD4647-A according to previous term.
2. Connect IBM-AT compatible PC with AKD4647-A by 10-line type flat cable (packed with AKD4647-A). Take care
of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on
Windows 2000/XP. Please refer “Installation Manual of Control Software Driver by AKM device control software”.
In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows
NT.)
3. Insert the CD-ROM labeled “AK4647-A Evaluation Kit” into the CD-ROM drive.
4. Access the CD-ROM drive and double-click the icon of “AKD4647.exe” to set up the control program.
5. Then please evaluate according to the follows.
Note. This control software does not support the I2C bus.
„ Operation flow
Keep the following flow.
1. Set up the control program according to explanation above.
2. Click “Port Reset” button.
„ Explanation of each buttons
[Port Reset] :
[Write default] :
[All Write] :
[Function1] :
[Function2] :
[Function3] :
[Function4] :
[Function5]:
[SAVE] :
[OPEN] :
[Write] :
Set up the USB interface board (AKDUSBIF-A) .
Initialize the register of AK4647.
Write all registers that is currently displayed.
Dialog to write data by keyboard operation.
Dialog to write data by keyboard operation.
The sequence of register setting can be set and executed.
The sequence that is created on [Function3] can be assigned to buttons and executed.
The register setting that is created by [SAVE] function on main window can be assigned to
buttons and executed.
Save the current register setting.
Write the saved values to all register.
Dialog to write data by mouse operation.
„ Indication of data
Input data is indicated on the register map. Red letter indicates “H” or “1” and blue one indicates “L” or “0”. Blank is the
part that is not defined in the datasheet.
<KM098600>
2009/1
- 15 -
ASAHI KASEI
[AKD4647-A]
„ Explanation of each dialog
1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register.
Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data
becomes “H” or “1”. If not, “L” or “0”.
If you want to write the input data to AK4647, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box:
Data Box:
Input registers address in 2 figures of hexadecimal.
Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4647, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate IVOL and DVOL
Address Box:
Input registers address in 2 figures of hexadecimal.
Start Data Box:
Input starts data in 2 figures of hexadecimal.
End Data Box:
Input end data in 2 figures of hexadecimal.
Interval Box:
Data is written to AK4647 by this interval.
Step Box:
Data changes by this step.
Mode Select Box:
If you check this check box, data reaches end data, and returns to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00
If you do not check this check box, data reaches end data, but does not return to start data.
[Example] Start Data = 00, End Data = 09
Data flow: 00 01 02 03 04 05 06 07 08 09
If you want to write the input data to AK4647, click [OK] button. If not, click [Cancel] button.
<KM098600>
2009/1
- 16 -
ASAHI KASEI
[AKD4647-A]
4. [Save] and [Open]
4-1. [Save]
Save the current register setting data. The extension of file name is “akr”.
(Operation flow)
(1) Click [Save] Button.
(2) Set the file name and push [Save] Button. The extension of file name is “akr”.
4-2. [Open]
The register setting data saved by [Save] is written to AK4647. The file type is the same as [Save].
(Operation flow)
(1) Click [Open] Button.
(2) Select the file (*.akr) and Click [Open] Button.
<KM098600>
2009/1
- 17 -
ASAHI KASEI
[AKD4647-A]
5. [Function3 Dialog]
The sequence of register setting can be set and executed.
(1) Click [F3] Button.
(2) Set the control sequence.
Set the address, Data and Interval time. Set “-1” to the address of the step where the sequence should be paused.
(3) Click [Start] button. Then this sequence is executed.
The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step.
This sequence can be saved and opened by [Save] and [Open] button on the Function3 window. The extension of file
name is “aks”.
Figure 7. Window of [F3]
<KM098600>
2009/1
- 18 -
ASAHI KASEI
[AKD4647-A]
6. [Function4 Dialog]
The sequence that is created on [Function3] can be assigned to buttons and executed. When [F4] button is clicked, the
window as shown in Figure opens.
Figure 8. [F4] window
<KM098600>
2009/1
- 19 -
ASAHI KASEI
[AKD4647-A]
6-1. [OPEN] buttons on left side and [START] buttons
(1) Click [OPEN] button and select the sequence file (*.aks).
The sequence file name is displayed as shown in Figure .
Figure 9. [F4] window(2)
(2) Click [START] button, then the sequence is executed.
3-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The sequence file names can assign be saved. The file name is *.ak4.
[OPEN] : The sequence file names assign that are saved in *.ak4 are loaded.
3-3. Note
(1) This function doesn't support the pause function of sequence function.
(2) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(3) When the sequence is changed in [Function3], the file should be loaded again in order to reflect the change.
<KM098600>
2009/1
- 20 -
ASAHI KASEI
[AKD4647-A]
7. [Function5 Dialog]
The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. When
[F5] button is clicked, the following window as shown in Figure opens.
Figure 10. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button
(1) Click [OPEN] button and select the register setting file (*.akr).
The register setting file name is displayed as shown in Figure .
(2) Click [WRITE] button, then the register setting is executed.
<KM098600>
2009/1
- 21 -
ASAHI KASEI
[AKD4647-A]
Figure 11. [F5] windows(2)
7-2. [SAVE] and [OPEN] buttons on right side
[SAVE] : The register setting file names assign can be saved. The file name is *.ak5.
[OPEN] : The register setting file names assign that are saved in *.ak5 are loaded.
7-3. Note
(1) All files need to be in same folder used by [SAVE] and [OPEN] function on right side.
(2) When the register setting is changed by [Save] Button in main window, the file should be loaded again in order to
reflect the change.
<KM098600>
2009/1
- 22 -
ASAHI KASEI
[AKD4647-A]
REVISION HISTORY
Date
Manual
Board
Reason
(yy/mm/dd) Revision Revision
09/01/09 KM098600
0
First Edition
Page
Contents
IMPORTANT NOTICE
z These products and their specifications are subject to change without notice.
When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei
EMD Corporation (AKEMD) or authorized distributors as to current status of the products.
z AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or
use of any information contained herein.
z Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange,
or strategic materials.
z AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or
other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use
approved with the express written consent by Representative Director of AKEMD. As used here:
Note1) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and
which must therefore meet very high standards of performance and reliability.
Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or
for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform
may reasonably be expected to result in loss of life or in significant injury or damage to person or property.
z It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise
places the product with a third party, to notify such third party in advance of the above content and conditions, and the
buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any
and all claims arising from the use of said product in the absence of such notification.
<KM098600>
2009/1
- 23 -
LOUT
ROUT
41
40
LIN2
LIN1
D
BEEP
C
RIN2
B
RIN1
A
E
37
38
39
42
43
44
45
46
47
48
CN1
E
E
TP1
RIN1
1
TP2
LIN1
1
TP3
LIN2
TP4
RIN2
1
1
TP5
TP7
BEEP TP6 ROUT/LON
1
1
1
LOUT / LPO
3
NC
37
NC
38
39
ROUT
NC
LOUT
40
41
42
BEEP
43
NC
45
46
44
RIN2/IN2-
2
MUTET
36
VCOM
HPL
35
AVSS
HPR
34
D
36
+
R3
2.2k
LIN2/IN2+
NC
C3
1u
1
R1
2.2k
1
CN3
TP8
MUTET
1
TP9
MPWR
3
JP3
LIN1
R2
open
C2
1u
LIN1/IN1-
D
MPWR
U1
JP2
RIN1
2
RIN1/IN1+
1
47
C1
1u
48
CN2
4
1
TP12
HPL
10
1
33
HPL
32
HPR
31
HVDD
TP14
HPR
32
6
VCOC
VCOC
TEST2
AK4647
31
C
TP17
HVSS
7
I2C
TEST1
30
8
NC
NC
29
9
PDN
NC
28
30
29
SPP
28
SPN
27
4647_MCKO
26
EXT_MCLK
1
TP18
PDN
TP20
MCKO
10
NC
MCKO
27
1
R5
1
51
NC
NC
25
24
DVSS
23
22
BICK
21
20
NC
19
18
13
B
25
NC
12
DVDD
26
LRCK
MCKI
SDTO
NC
NC
B
11
1
TP21
MCKI
SDTI
TP19
CSN
17
11
12
C7
TP16
HVDD
CDTI/SDA
9
HVDD
16
4647_CSN/CAD0
C10
4.7n
AVDD
CCLK/SCL
8
C8
TP15
15
4647_PDN
R4
10k
CSN/CAD0
C
33
1
5
7
HVSS
0.1u 10u
1
4647_I2C
NC
C9
0.1u
1
C6
10u
1
1
4
TP13
AVDD
+
6
34
+C5
0.1u
C4
2.2u
1
TP11
AVSS
14
5
+
AVDD
35
TP10
VCOM
C11
R9
51
+
10u
R10
51
24
R8
51
1
23
18
R7
51
17
16
15
14
13
R6
51
1
0.1u
C12
22
1
21
1
TP25 TP26
LRCK BICK
19
1
TP24
SDTI
20
TP22 TP23
CCLK CDTI
CN4
4647_DVDD
4647_BICK
4647_LRCK
4647_SDTO
4647_SDTI
4647_CDTI/SDA
A
4647_CCLK/SCL
A
Title
Size
A3
Date:
A
B
C
D
AKD4647 SUB 48LQFP
Document Number
Rev
AK4647
Friday, April 07, 2006
A
Sheet
E
1
of
1
D
E
1
1
1
1
C4
1u
LVC_IN
VD_IN
DGND
AGND
T45_BK
T45_BK
5
NMT
VCOC/RIN3
1
21
1
HPR
JP9
VCOC
HVDD
20
C14
0.1u
6
I2C
HVSS
19
7
PDN
MCKO
18
8
CSN/CAD0
MCKI
17
10u
+C15
1
1
1
HVDD
C
L3
2
31
1
(short)
30
29
SPP
28
SPN
27
4645_MCKO
26
EXT_MCLK
TP24
MCKO
+
C16
47u
16
15
14
.13
12
TP25
MCKI
1
R7
51
LVC
(short)
11
10
9
JP10
TVDD LVC_SEL
R8
51
R9
51
R10
51
R11
51
C18
B
25
0.1u
VD
10u
+
2
47u
+
JP7
REG
TP27
TP26 CDTI TP28
CCLK1
SDTI
1
TP29
LRCK TP30
BICK
1
1
C20
C21
0.1u
1
C22
10u
+
C19
HPR
TP21
HVSS
1
51
B
2
32
TP19
HVDD
12
L5
HPL
R6
1
11
1
33
1
1
22
TVDD
TP23
CSN
(short)
LVC_IN
1
37
38
39
25
1
ROUT/LON
LIN4/IN4+
26
27
MIN/LIN3
LOUT/LOP
28
29
30
AVDD
DVDD
10
2
HPL
BICK
4645_TVDD
AVSS
REG_OUT
2
RIN3
1
2
34
TP16
HPL
TP22
PDN
L4
1
RIN4
35
1
TP20
VCOC
1
R5
10k
9
HVDD
TP18
HPR
4
C13
4.7n
23
C12
0.1u
LRCK
8
MUTET
SDTO
4645_PDN
24
1
C11
10u
1
7
RIN4/IN4-
VCOM
SDTI
2
1
3
TP17
AVDD
+
4645_I2C
4645_CSN/CAD0
TVDD
1
T45_OR
36
+ C9
0.1u
C7
2.2u
JP8
+
HVDD
T45_OR
TP13
RIN4
+
TP15
AVSS
6
TVDD_SEL
47u
VD_IN
T45_OR
E
TP11 C8
MUTET 1u
2
5
4645_DVDD
(short)
MPWR
CCLK/SCL
2
C
C17
LVC_IN
TVDD
D
TP14
VCOM
1
L2
1
4
DVDD_SEL
1
47u
DVDD
CN3
RIN2/IN2-
1
+
AVDD
R2
open
LIN2/IN2+
1
R3
2.2k
31
U1
LIN1/IN1-
TP12 R4
MPWR 2.2k
3
JP6
DVDD
C10
LOUT / LOP
C5
1u
CDTI/SDA
R1
10
JP5
LIN1
32
JP4
RIN1
2
2
47u
REG
2
(short)
RIN1/IN1+
1
1
+
T45_OR
1
1
L1
C6
TVDD
T45_OR
1
JP2
LIN3
CN2
AVDD
D
40
TP7
TP9
MIN
ROUT/LON TP10
TP6
RIN2 1
LIN4
TP8
1
MIN
JP3
AVDD_SEL
41
42
43
TP5
LIN2
TP4
LIN1 1
DVDD
T45_OR
1
TP3
RIN1
TP2
LIN3 1
44
45
46
47
48
CN1
TP1
RIN3
AVDD
T45_RED
1
E
1
REG
LIN4
ROUT
LOUT
MIN
RIN2
LIN2
LIN1
C2
0.1u
RIN1
1
C1
0.1u
JP1
GND
C3
+
47u
LIN3
REG_OUT
OUT
2
IN
RIN3
GND
T1
TA48033F
REG
1
C
1
B
1
A
24
23
22
21
20
19
18
17
16
CN4
4645_TVDD
4645_DVDD
4645_BICK
4645_LRCK
4645_SDTO
A
4645_SDTI
47u
VD
2
A
2
(short)
4645_CDTI/SDA
+
4645_CCLK/SCL
1
C23
15
L6
1
14
13
VD_IN
Title
Size
A3
Date:
A
B
C
D
AKD4647-A
Document Number
Rev
AK4647
Friday, January 09, 2009
Sheet
E
0
1
of
5
A
B
C
D
E
J1
HPL
+
BNC
R12
C24
47u
6.8
JP11
HPL
R13
16
J2
HP/LINE
4
3
JP12
LIN3
LIN2
LIN4
LIN2
LIN4
+
LIN_SEL
R15
C26
47u
6.8
HP
R14
short
1
1
C25
1u
+
2
3
4
5
TP31
LIN
E
6
LIN3
J3
LIN
2
3
4
5
HP
HPL
E
1
JP13
HPR
HPR
J4
HPR
1
2
3
4
5
BNC
R16
16
D
D
RIN3
TP32
RIN
1
C27
1u
R17
short
1
J5
RIN
+
2
3
4
5
R18
open
JP14
RIN3
RIN2
RIN4
RIN2
RIN_SEL
RIN4
Mini-Jack
JP15
LOUT_SEL
R19
220
BNC
+
C28
1u
J6
LOUT
1
LOUT
J7
MIN
C
1
+
2
3
4
5
C29
1u
R21
20k
2
3
4
5
R20
20k
Mini-Jack
JP16
ROUT_SEL
C30
1u
R22
220
+
BNC
J8
ROUT
1
ROUT
2
3
4
5
R23
20k
B
J9
LIN1/RIN1
C
MIN
RIN1
B
6
LIN1
(open)
C31
+
JP17
SPP
2
SPP
2
3
3
1
(short)
R27
short
C32
+
R26
(open)
J10
SPK
R24 R25
short
1
4
3
SPN
JP18
SPN
A
(short)
R28
(open)
A
Title
Size
A3
Date:
A
B
C
D
AKD4647
Document Number
Rev
Input/Output
Friday, January 09, 2009
Sheet
E
0
2
of
5
A
B
C
D
E
E
E
THR
JP19
PHASE
EXT_BICK
INV
EXT_MCLK
THR
D
U2
4114_MCLK_OUT
JP24
MCLK
DIR
EXT
1
2
3
4
5
6
x1
x2
x4
MCKO
13
12
11
10
9
8
1CLR 2CLR
1D
2D
1CK
2CK
1PR
2PR
1Q
2Q
1Q
2Q
JP22
MKFS
U3
10
CLK
11
RST
J11
EXT
2
3
4
5
1
14
7
VD
R29
51
C33
0.1u
MCKO
Vcc
GND
16
8
VD
C53
0.1u
74AC74
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
VD
Q11
DGND Q12
JP23
BCFS
9
7
6
5
3
2
4
13
12
14
15
1
JP20
PHASE
DIR
4114_BICK_OUT
JP21
BICK
64fs
32fs
D
INV
4040
U4
X_LRCK
1
2
3
4
5
6
74HC4040
JP25
EXT
BICK
14
7
VD
VD
C34
0.1u
C
1A
1Y
2A
2Y
3A
3Y
4Y
4A
5Y
5A
6Y
6A
8
9
10
11
12
13
4114_PDN
Vcc
GND
74HC14
C
1
2
VD
D1
HSU119
R30
10k
2
PDN
1
D2
HSU119
C35
0.1u
H
1
L
3
2
SW1
PDN
1
R31
10k
H
3
L
C36
0.1u
B
2
B
SW2
DIR
A
A
Title
Size
A3
Date:
A
B
C
D
AKD4647-A
Document Number
Rev
CLOCK
Friday, January 09, 2009
Sheet
E
0
3
of
5
A
B
C
D
E
C37
0.1u
L7
short
E
2
E
C38
0.1u
1
VD
PORT1
C39
0.1u
C40
10u
R32
470
C41
0.1u
1
R
37
INT1
40
39
R33
18k
VCOM
41
AVSS
42
RX0
43
NC
44
RX1
46
45
TEST1
NC
RX2
12
11
10
9
8
7
47
U5
S1
1
2
3
4
5
6
RX3
DIF0
DIF1
DIF2
OCKS1
CAD0
I2C
48
C42
0.47u
D
VD
+
TORX141
38
3
2
1
AVDD
VCC
GND
OUT
IPS0
D
R34
1k
INT0
LED1
ERF
2
36
1
VD
U6
SW DIP-6
2
NC
OCKS0
35
3
DIF0
OCKS1
34
OCKS1
4
TEST2
CM1
33
VD
1
2
3
4
5
6
RP1
OCKS1
CAD0
I2C
47k
5
DIF1
CM0
32
6
NC
PDN
31
7
DIF2
XTI
30
8
IPS1
XTO
29
9
P/SN
DAUX
28
10
XTL0
MCKO2
27
11
XTL1
BICK
26
SDTO
25
AK4114
C
14
7
VD
JP26
4114_MCKI_IN
MCKO
C43
0.1u
C44
5p
C48
10u
C49
10u
VD
2
C45
5p
DAUX
OUT
VD
A
IN
VCC
GND
1
4114_BICK_OUT
JP27
4114BICK_SEL
B
IN
LRCK
4114_BICK_IN
24
MCKO1
4114_SDTI
OUT
4114_LRCK_IN
PORT2
3
2
23
22
DVSS
DVDD
+
21
VOUT
20
UOUT
19
COUT
18
BOUT
17
TX1
16
TX0
15
14
+
13
DVSS
TVDD
VIN
C47
0.1u
Vcc
GND
74HC04
C
B
C46
0.1u
8
9
10
11
12
13
4114_PDN
X1
11.2896MHz
12
4Y
4A
5Y
5A
6Y
6A
1
7
6
5
4
3
2
1
1A
1Y
2A
2Y
3A
3Y
4114_LRCK_OUT
JP28
4114LRCK_SEL
IN
4114_MCLK_OUT
VD
C50
0.1u
A
TOTX141
Title
Size
A3
Date:
A
B
C
D
AKD4647-A
Document Number
Rev
DIR/DIT
Friday, January 09, 2009
Sheet
E
0
4
of
5
A
B
C
D
E
U7
11
Y8
A8
9
12
Y7
A7
8
13
Y6
A6
7
BICK
E
E
4645_SDTI
DIR
JP29
LRCK
4114_LRCK_OUT
4645_I2C
14
4645_CCLK/SCL
15
4645_CSN/CAD0
16
4645_PDN
17
Y5
A5
6
Y4
A4
5
Y3
A3
4
Y2
A2
3
I2C
X_LRCK
4040
EXT_MCLK
MCLK
BICK
LRCK
SDTI
VCC
EXT_BICK
Y1
A1
2
10
GND
G2
19
20
VCC
G1
1
10
9
8
7
6
DSP
PDN
D
18
PORT3
1
2
3
4
5
D
R35
VD
10k
C51
0.1u
4040
DAUX
JP30
SDTI
IN
OUT
JP34
DAUX_SEL
74LVC541
JP33
LRCK_SEL
4114_SDTI
DIR
LVC
4645_LRCK
3-WIRE
C
IN
OUT
4645_BICK
JP32
BICK_SEL
C
MODE_SEL
VD
JP31
R36
R38
R40
10k
10k
10k
R37
R39
R41
CAD0
470
470
470
I2C
PORT4
6
7
8
9
10
5
4
3
2
1
CSN
CCLK/SCI
CDTI/SDA
CDTO/SDA(ACK)
CTRL
RP2
1
2
3
4
5
B
VD
R44
1k
B
R42
1k
330
U8
2
4
6
8
10
12
DAUX
1Y
2Y
3Y
4Y
5Y
6Y
1A
2A
3A
4A
5A
6A
1
3
5
9
11
13
Vcc
GND
14
7
4645_SDTO
4645_MCKO
MCKO
JP35
4114_LRCK_IN
LRCK_MODE
74LVC07
LVC
C52
0.1u
R43
1.8k
JP36
A
4114_BICK_IN
A
BICK_MODE
Title
4645_CDTI/SDA
Size
A3
Date:
A
B
C
D
AKD4647-A
Document Number
Rev
LOGIC
Friday, January 09, 2009
0
Sheet
E
5
of
5
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