AK4490EQ

[AKD4490-A]
AKD4490-A
AK4490 Evaluation Board Rev.0
1. General Description
The AKD4490-A is an evaluation board for the AK4490 (Premium 32-bit 2ch DAC) that supports
DVD-Audios. It integrates differential output low pass filters, allowing quick evaluation with digital audio
interface.
■ Ordering Guide
AKD4490-A -- Evaluation Board for the AK4490
(A USB I/F board for IBM-AT compatible computers and control software are
included in this package.)
2. Function
 10-pin Header for Serial Control
 Low Pass Filters (LPF) for Pre-amplifier Outputs
 Digital Audio Interface (AK4115)
2nd Order LPF
Lch
DIR
COAX In
AK4115
AK4490
Opt In
Rch
Figure 1. AKD4490-A Block Diagram (Note 1)
Note 1. Circuit schematics are attached at the end of this document.
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3. Table of Contents
1. General Description ................................................................................................................................................ 1
■ Ordering Guide .......................................................................................................................................................... 1
2. Function .................................................................................................................................................................. 1
3. Table of Contents ................................................................................................................................................... 2
4. Board Appearance .................................................................................................................................................. 3
■ Appearance Diagram ................................................................................................................................................. 3
■ Description................................................................................................................................................................. 3
5. Operation Sequence................................................................................................................................................ 5
■ Power Supply Connections ........................................................................................................................................ 5
■ Evaluation Mode ........................................................................................................................................................ 6
■ Jumper Pin and DIP Switch Settings ......................................................................................................................... 7
■ Power-up .................................................................................................................................................................. 10
■ Serial Control Mode (PSN pin = “L”) ..................................................................................................................... 11
■ Capacitance between the VREFH pin and the VREFL pin ...................................................................................... 13
6. Control Software Manual ..................................................................................................................................... 14
■ Evaluation Board and Control Software Manual ..................................................................................................... 14
■ Operation Overview ................................................................................................................................................. 15
■ Tab Functions .......................................................................................................................................................... 16
■ Dialog Box ............................................................................................................................................................... 18
7. Measurement Results............................................................................................................................................ 23
8. Revision History ................................................................................................................................................... 39
IMPORTANT NOTICE ....................................................................................................................................... 40
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4. Board Appearance
■ Appearance Diagram
Figure 2. AKD4490-A Outline View
■ Description
(1) Connectors for Power Supply and GND
(REG(+15V), REG(-15V), AVDD, DVDD, VDDL, VDDR, VREFHL, VREFHR, AGND, DGND)
Connectors for power supply and the ground
Refer to the “■ Power Supply Connection” for details.
(2) SPDIF Input Connectors (J9/BNC Connector, PORT4/Optical Connector)
Input a SPDIF signal to the AK4115.
Set the JP9 jumper pin to “BNC” side when using the J9 (BNC Connector) jack.
Set the JP9 jumper pin to “OPT” side when using the PORT4 (Optical Connector).
(3) Analog Output Terminals (J1 / J3, BNC Connector)
Single-ended Analog Output Connector
(4) Analog Differential Output Terminals (J12 / J13, XLR Connector)
Differential Analog Output Connector
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(5) EXT PORT (PORT2)
10-pin Header for External Interfacing
External digital audio devices are interfaced to this port.
Set the JP5, JP6, JP7 and JP8 jumper pins to “EXT” side when using the PORT2 (EXT).
Pi
n
1
3
5
7
9
I/O
I
I
I
I
I
Function
pin
I/O
Function
MCLK
BICK
SDTO
LRCK
2
P
GND
4
P
GND
6
P
GND
8
P
GND
10
P
GND
Table 1. PORT2 (EXT) Pin Assignments
(6) AK4115 (U7)
The AK4115 is a digital audio transceiver.
It is used when evaluating sound quality of the AK4490 by SPDIF signals.
(7) µP-IF PORT (PORT3)
10-pin Header for the USB I/F board
Connect the USB I/F board for IBM-AT compatible computers to this port for a connection to a USB port of
a PC. Refer to the “■ Serial Control Mode” for details
(8) Slide Switches (SW1 / SW2 / SW10)
Setting Switches for the AK4490 and the AK4115.
Upside is “H” (ON) and Downside is “L” (OFF).
Refer to “■ Jumper Pin and DIP Switch Settings” for details.
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5. Operation Sequence
■ Power Supply Connections
This jack is always needed.
-10 to -15V
MVDD (AK4490),
Op-Amp
Op-Amp
Default
Setting
+15V
This jack is always needed.
-15V
Green
+10 to +15V
VREFHL (AK4490)
This jack is always needed.
+15V
VREFHR
Green
+10 to +15V
VREFHR (AK4490)
This jack is always needed.
+15V
DVDD
Orange
+2.7 to +3.6V
DVDD (AK4490)
Open
AVDD
Orange
+2.7 to +3.6V
AVDD (AK4490)
VDDL
Orange
+4.75 to +5.25V
VDDL (AK4490)
VDDR
Orange
+4.75 to +5.25V
VDDR (AK4490)
AGND
Black
0V
Analog Ground
These are used when supplying
DVDD, AVDD, VDDL and
VDDR from a +5V connector
without a regulator.
Set the JP1 and JP2 jumper pins
to “+5V” and the JP3 and JP4
jumper pins to “+3V” side.
This jack is always needed.
DGND
Black
0V
Digital Ground
This jack is always needed.
Name
Color
Voltage
REG
(+15V)
REG
(-15V)
VREFHL
Red
+10 to +15V
Blue
Content
Note
Open
Open
Open
0V
0V
Table 2. Power Supply Connections (Note 2)
Note 2. Each power supply line should be distributed separately from the power supply unit.
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■ Evaluation Mode
(1) Evaluation with a DIR (COAX) < Default >
The J9 (COAX) jack is used in this mode. The DIR (AK4115) generates MCLK, BICK, LRCK and
SDATA from the input data of the J9 (COAX) connector.
Set the JP9 (RX-SEL) jumper pin to “BNC”, and set the JP5 (MCLK), JP6 (BICK), JP8 (LRCK) and JP7
(SDTO) jumper pins to “DIR”.
JP5
MCLK
JP6
JP8
JP7
BICK
LRCK
SDTO
JP9
RX-SEL
DIR
DIR
DIR
DIR
BNC
EXT
EXT
EXT
EXT
OPT
Figure 3. Jumper Pin Settings with DIR
(2) Evaluation with a DIR (OPTICAL)
The PORT4 (OPTICAL) is used in this mode. The DIR (AK4115) generates MCLK, BICK, LRCK and
SDATA from the input data of the PORT4 (OPTICAL) connector.
Set the JP9 jumper pin to “OPT”, and set the JP5 (MCLK), JP6 (BICK), JP8 (LRCK) and JP7 (SDTO)
jumper pins to “DIR”.
JP5
MCLK
JP6
JP8
JP7
BICK
LRCK
SDTO
JP9
RX-SEL
DIR
DIR
DIR
DIR
BNC
EXT
EXT
EXT
EXT
OPT
Figure 4. Jumper Pin Settings with DIR
(3) In the case that all interface clocks including the master clock are input externally. (PORT1)
Input all interface clocks including the master clock to the PORT2 (DSP).
Set JP5 (MCLK), JP6 (BICK), JP8 (LRCK) and JP7 (SDTO) jumper pins to “EXT”.
JP5
MCLK
JP6
JP8
JP7
BICK
LRCK
SDTO
DIR
DIR
DIR
DIR
EXT
EXT
EXT
EXT
Figure 5. Jumper Pin Settings with External Clocks
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■ Jumper Pin and DIP Switch Settings
(1) Jumper Pin Settings
Main Board
[JP1 (VDDL)]: VDDL pin input select
REG: The VDDL pin is supplied from the T1 regulator. < Default >
+5V: The VDDL pin is supplied from the J4 (VDDL) connector.
[JP2 (VDDR)]: VDDR pin input select
REG: The VDDR pin is supplied from the T2 regulator. < Default >
+5V: The VDDR pin is supplied from the J5 (VDDR) connector.
[JP3 (AVDD)]: AVDD pin input select
REG: The AVDD pin is supplied from the T3 regulator. < Default >
+3V: The AVDD pin is supplied from the J6 (AVDD) connector.
[JP4 (DVDD)]: DVDD pin input select
REG: The DVDD pin is supplied from the T4 regulator. < Default >
+3V: The DVDD pin is supplied from the J7 (DVDD) connector.
[JP5 (MCLK)]: MCLK pin input select
DIR: MCLK signal is supplied from the DIR (AK4115). < Default >
EXT: MCLK signal is supplied from the PORT2.
[JP6 (BICK)]: BICK pin input select
DIR: BICK signal is supplied from the DIR (AK4115). < Default >
EXT: BICK signal is supplied from the PORT2.
[JP7 (SDTO)]: SDATA pin input select
DIR: SDATA signal is supplied from the DIR (AK4115). < Default >
EXT: SDATA signal is supplied from the PORT2.
[JP8 (LRCK)]: LRCK pin input select
DIR: LRCK signal is supplied from the DIR (AK4115). < Default >
EXT: LRCK signal is supplied from the PORT2.
[JP9 (RX-SEL)]: SPDIF signal for AK4115
BNC: SPDIF signal is supplied from the J9 (COAX) connector. < Default >
OPT: SPDIF signal is supplied from the PORT4.
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Sub Board
[JP10 (PS1)]: SMUTE/CSN pin input select
SMUTE: This setting is for Parallel Control Mode. < Default >
CSN: This setting is for Serial Control Mode.
[JP11 (PS2)]: SD/CCLK/SCL pin input select
SD: This setting is for Parallel Control Mode. < Default >
CCLK/SCL: This setting is for Serial Control Mode.
[JP12 (PS3)]: SLOW/CDTI/SDA pin input select
SLOW: This setting is for Parallel Control Mode. < Default >
CDTI/SDA: This setting is for Serial Control Mode.
[JP13 (PS4)]: SSLOW/WCK pin input select
H: The SSLOW pin is set to “H” in Parallel Control Mode.
L: The SSLOW pin is set to “L” in Parallel Control Mode. < Default >
OPEN: It can be an input pin header for a WCK signal when the AK4490 is in Serial Control
Mode and the external digital filter I/F is used.
[JP14 (DZFL)]: DIF0/DZFL pin connection select
SHORT: This setting is for Parallel Control Mode. < Default >
OPEN: This setting is for Serial Control Mode.
[JP15 (DZFR)]: DIF1/DZFR pin connection select
SHORT: This setting is for Parallel Control Mode. < Default >
OPEN: This setting is for Serial Control Mode.
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(2) DIP Switch Setting
Upside is ON (“H”), and Downside is OFF (“L”).
Main Board
[SW1]: Setting of the AK4115
No.
Name
ON (“H”)
OFF (“L”)
1
OCKS1
Master Clock setting for AK4115
Refer to Table 6
2
OCKS0
Table 3. SW1 Setting
[SW2]: Setting of the AK4490-1
No.
Name
ON (“H”)
OFF (“L”)
Default
H
L
Not Used
Should always be OFF (“L”) side.
I2C
I2C-Bus
3-wire
2
(Note 3)
Control Mode
Serial Control Mode
Table 4. SW2 Setting
Note 3. The I2C pin is valid when SW10 (7 pin/PSN) is set to “L” (Serial Control Mode).
1
-
Default
L
L
Sub Board
[SW10]: Setting of the AK4490-2
No.
Name
ON (“H”)
OFF (“L”)
1
SMUTE
Mute “ON”
Mute “OFF”
2
SD
Digital Filter Setting
Refer to Table 7
3
SLOW
4
DIF0
Audio I/F Format for AK4490
5
DIF1
Refer to Table 8
DIF2
6
/CAD0
CAD0 pin= “H”
CAD0 pin= “L”
7
PSN
Parallel Control Mode
Serial Control Mode
8
DEM0
De-emphasis Control
Refer to Table 9
9
DEM1
Auto Setting Mode
Manual Setting Mode
ACKS
10
/CAD1
CAD1 pin= “H”
CAD1 pin= “L”
Table 5. SW10 Setting
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Default
L
H
L
L
H
L
H
H
L
L
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Mode
0
1
2
3
SD
L
L
H
H
Mode
0
1
2
3
4
5
6
7
DEM1
L
L
H
H
OCKS1
OCKS0
MCKO1
L
L
256fs
L
H
256fs
H
L
512fs
H
H
128fs
Table 6. Master Clock Setting
SLOW
Mode
L
Sharp roll-off filter
H
Slow roll-off filter
L
Short delay sharp roll-off filter
H
Short delay slow roll-off filter
Table 7. Digital Filter Setting
DIF2
pin
L
L
L
L
H
H
H
H
DIF1 DIF0
Input Format
pin
pin
L
L
16bit LSB justified
L
H
20bit LSB justified
H
L
24bit MSB justified
H
H
24bit I2S Compatible
L
L
24bit LSB justified
L
H
32bit LSB justified
H
L
32bit MSB justified
H
H
32bit I2 Compatible
Table 8. AK4414 Audio I/F Format
fs (max)
96 kHz
96 kHz
48 kHz
192 kHz
< Default >
< Default >
BICK
 32fs
 48fs
 48fs
 48fs
 48fs
 64fs
 64fs
 64fs
< Default >
DEM0
Mode
L
44.1kHz
H
OFF
< Default >
L
48kHz
H
32kHz
Table 9. De-emphasis Control
■ Power-up
Upside is ON (“H”), and Downside is OFF (“L”).
[SW3](PDN): DAC Reset control. It must be set to “H” during operation.
After power-up, the AKD4490-A must be reset once.
To reset the AKD4490-A, set the SW3 toggle switch to “L” and power down the AK4490
and the AK4115. Then, release the power-down by setting back the SW3 to “H”.
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■ Serial Control Mode (PSN pin = “L”)
When using this evaluation board in serial control mode, settings of the CAD1 pin and the CAD2 pin on the
board must match the Chip Address settings of the control software.
(1) 3-wire Serial Control Mode (I2C pin= “L”)
The AKD4490-A should be connected to a PC (IBM-AT compatible) via a USB control box
(AKDUSBIF-B) included in this package. The USB control box is connected to a PC with a USB cable and
the AKD4490-A with a 10-pin flat cable. (Note 4, Note 5)
Note 4. The AKD4490-A accepts only one AKDUSBIF-B at one time. It does not operate if two or more
AKDUSBIF-Bs are connected.
Note 5. Connect the 10pin Flat Cable as the red line of the cable is connected to the 1 pin of the 10pin Header
of the board.
Evaluation Board
AKDXXXX-YY
10pin Flat Cable
AKDUSBIF-B
PC
Device
AKXXXX
USB Cable
USB
Connector
Set Red line to No.1 pin side.
10pin
Connector
Figure 6. AKDUSBIF-B Connection
PC
Evaluation Board
AKDUSBIF-B
Figure 7. AKDUSBIF-B
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(2) I2C Bus Control Mode (I2C pin= “H”)
When controlling the AKD4490-A by a PC in I2C bus control mode, connect a PC (IBM-AT compatible) to
the AKDUSBIF-B with a USB cable and connect the AKDUSBIF-B to JP11 (PS2) and JP12 (PS3) on the
sub board of the AKD4490-A by a 10-pin flat cable. This connection of 10-pin flat cable to jumper pins
should be made by using a clip or similar things. (Note 6)
Note 6. Do not connect anything to the PORT3 when the AK4490 is in I2C bus control mode.
Name
SCL
SDA
GND
AKDUSBIF-B Side Connection Sub Board Side Connection
7 pin
JP11 (2 pin)
5 pin
JP12 (2 pin)
6 pin, 8pin
JP11 (4pin), JP12 (4pin)
Table 10. I2C Setting
CCLK/SCL SD
10pin Flat Cable
JP11
PS2
GND
AKDUSBIF-B
PC
USB Cable
CDTI/SDA SLOW
JP12
PS3
GND
USB
Connector
Figure 8. Connection Image
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■ Capacitance between the VREFH pin and the VREFL pin
Distortion at lower frequency can be improved by increasing the capacitance of a capacitor between the VREFH
pin and the VREFL pin. (Figure 9) Applicable capacitors are C207 and C210 in the circuit schematic.
AKM
THD+N vs. Input Frequency
-90
-92
C=470uF
-94
C=220uF
C=100uF
C=10uF
-96
-98
-100
d
B
r
A
-102
-104
-106
-108
-110
-112
-114
C=2200uF
C=1000uF
-116
-118
-120
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 9. THD+N vs. Input Frequency Comparison by Capacitance
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6. Control Software Manual
■ Evaluation Board and Control Software Manual
1. Set up the evaluation board as needed, according to the previous terms.
2. Connect the evaluation board to a PC with USB cable.
3. USB control is recognized as HID (Human Interface Device) on PC. When it is not recognized properly, please
reconnect the evaluation board to PC.
4. Insert the CD-ROM labeled “AKD4490-A Evaluation Kit” into the CD-ROM drive.
5. Access the CD-ROM drive and double-click the icon “akd4490-A.exe” to open the control program.
6. Begin evaluation by following the procedure below.
[Supported OS]
Windows XP / Vista / 7 (32bit) (XP compatible mode is recommended for Vista / 7)
64bit OS is not supported.
Figure 10. Control Program Window
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■ Operation Overview
Register map is controlled by this control software.
Frequently used buttons, such as the register initializing button “Write Default”, are located outside of the
switching tab window. Refer to the “■ Dialog Box” section for details of each dialog box setting.
1.[Port Reset]: Reset connection to PC
Click this button after the control software starts up and the evaluation board is connected to
the PC via USB cable.
2.[Write Default]: Register Initialization
Use this button to initialize the registers when the device is reset by a hardware reset.
3.[All Write]: Execute write command for all registers displayed.
4.[All Read]: Execute read command for all registers displayed. (Note 7)
5.[Save]: Save current register settings to a file.
6.[Load]: Execute data write from a saved file.
7.[All Reg Write]: [All Reg Write] dialog box pops up.
8.[Data R/W]: [Data R/W] dialog box pops up.
9.[Sequence]: [Sequence] dialog box pops up.
10.[Sequence(File)]: [Sequence(File)] dialog box pops up.
Note 7. The [All Read] button is only valid when the interface mode for register control is in I2C bus control
mode.
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■ Tab Functions
1. [REG] Tab: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray)
Grayed out registers are Read-Only registers. They cannot be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 11. REG Window
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[Write] button: Data Write Dialog
Select the [Write] button located on the right of the each corresponding address when changing two or more bits
on the same address simultaneously.
Click the [Write] button for the register pop-up dialog box shown below.
When the checkbox next to the register is checked, the data will become “1”. When the checkbox is not
checked, the data will become “0”. Click [OK] to write the set values to the registers, or click [Cancel] to cancel
this setting.
Figure 12. Register Set Window
[Read] button: Data Read (Only in I2C-bus Control Mode)
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “1” and the bit name is shown in red (when read only the bit name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read only the bit name is shown in gray)
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■ Dialog Box
1. [All Reg Write]: All Register Write dialog box
Click [All Reg Write] button in the main window to open register setting file window shown below.
Register setting files saved by [SAVE] button may be applied.
Figure 13. [All Reg Write] Window
[Open (left)]: Select a register setting file (*.akr).
[Write]: Execute register write with selected setting file.
[Write All]: Execute register write with all selected setting files.
Selected files are executed in descending order.
[Help]: Open help window.
[Save]: Save register setting file assignment. File name is “*.mar”.
[Open (right)]: Open saved register setting file assignment “*. mar”.
[Close]: Close dialog box and finish process.
~ Operating Suggestions ~
1. Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
2. When register settings are changed by [Save] button in the main window, re-read the file to reflect new
register settings.
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2. [Data R/W]: Data R/W Dialog Box
Click the [Data R/W] button in the main window for data read/write dialog box.
Data is written to the specified address.
Figure 14. [Data R/W] Window
[Address] Box: Input data write address in hexadecimal numbers.
[Data] Box: Input write data in hexadecimal numbers.
[Mask] Box: Input mask data in hexadecimal numbers.
This value “ANDed” with the write data becomes the input data.
[Write]: Write data generated from Data and Mask value is written to the address specified in “Address” box.
(Note 8)
[Read]: Read data from the address specified in “Address” box. (Note 9)
[Close]: Close dialog box and finish process.
Data write will not be executed unless [Write] is clicked.
Note 8. The register map will be updated after executing the [Write] command.
Note 9. The [Read] button is only valid when the interface mode for register control is in I2C bus control mode.
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3. [Sequence]: Sequence Dialog Box
Click the [Sequence] button in the main window for Sequence dialog box.
Register sequence may be set and executed.
Figure 15. [Sequence] Window
~ Sequence Setting ~
Set register sequence according to the following process.
1.
Select a command
Use [Select] pull-down box to choose commands.
Corresponding input boxes will be valid.
<Combo Box>
• No_use: Not using this address
• Register: Register write
• Reg(Mask): Register write (Masked)
• Interval: Take an interval
• Stop: Pause the sequence
• End: End the sequence
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2. Input Sequence
[Address]: Data Address
[Data]: Write Data
[Mask]: Mask
This value “ANDed” with the write data becomes the input data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask = 0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
[Interval]: Interval Time
Valid boxes for each process command are shown below.
・No_use
: None
・Register
: [Address], [Data], [Interval]
・Reg(Mask)
: [Address], [Data], [Mask], [Interval]
・Interval
: [Interval]
・Stop
: None
・End
: None
~ Control Buttons ~
Functions of Control Buttons are shown below.
[Start] button
[Help] button
[Save] button
[Open] button
[Close] button
: Execute the sequence.
: Open a help window.
: Save sequence settings as a file. The file name is “*.aks”.
: Open a sequence setting file “*.aks”.
: Close the dialog box and finishes the process.
Stop Sequence
When “Stop” command is selected in the sequence, the process is paused at this step. It is resumed by
clicking the [Start] button. The process starts from the step shown in [Start Step] box. This step number
returns to “1” when the sequence is executed until the end. Input arbitrary step number to the [Start Step]
box to start the process from the middle of sequence.
The process sequence can be restarted from the beginning by writing “1” to the [Start Step] box and
click the [Start] button during the process.
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4. [Sequence(File)]: Sequence(File) Dialog
Click the [Sequence(File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 16. [Sequence (File)] Window
[Open (left)] button: Select a sequence setting file (*.aks)
[Start ] button: Execute the sequence by the setting of selected file.
[Start All] button: Execute sequence with all selected setting files.
Selected files are executed in descending order.
[Help] button: Open help window.
[Save] button: Save register setting file assignment. File name is “*.mas”.
[Open (right)] button: Open saved sequence setting file assignment “*. mas”.
[Close] button: Close dialog box and finish process.
~ Operating Suggestions ~
1. Files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mas” should be
stored in the same folder.
2. When “Stop” command is selected in the sequence, the process is paused at this step and a message shown
below pops up. The sequence is resumed by clicking “OK” button.
Figure 17. Sequence Pause Window
<KM115900>
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- 22 -
[AKD4490-A]
7. Measurement Results
[Measurement condition]
 Measurement unit
 MCLK
 BICK
 fs
 Bit
 Power Supply
 Pass
 Interface
 Temperature
 Operational Amplifiers
: Audio Precision System two Cascade (AP2)
: 512fs (44.1 kHz), 256fs (96 kHz), 128fs (192 kHz)
: 64fs
: 44.1kHz, 96kHz, 192kHz
: 24bit
: AVDD= DVDD=3.3V, VDDL/R=VREFHL/R=5V
: DIR → AK4490 → Cannon Connector
: Internal DIR (44.1 kHz, 96 kHz, 192 kHz)
: Room Temperature
: LME49710NA
fs=44.1kHz
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Measurement filter
20kHz LPF
A-weighted
20kHz LPF
A-weighted
Lch
111.3 dB
117.5 dB
120.3 dB
117.8 dB
120.2 dB
Results
/
/
/
/
/
/
Rch
111.4 dB
117.8 dB
120.2 dB
117.9 dB
120.2 dB
Lch
109.3 dB
115.0 dB
120.3 dB
115.0 dB
120.3 dB
Results
/
/
/
/
/
/
Rch
109.5 dB
114.8 dB
120.1 dB
114.9 dB
120.1 dB
Lch
109.3 dB
115.0 dB
120.3 dB
115.0 dB
120.3 dB
Results
/
/
/
/
/
/
Rch
109.4 dB
114.9 dB
120.0 dB
114.6 dB
120.0 dB
fs=96kHz
Measurement filter
40kHz LPF
A-weighted
40kHz LPF
A-weighted
fs=192kHz
Measurement filter
40kHz LPF
A-weighted
40kHz LPF
A-weighted
<KM115900>
2014/01
- 23 -
[AKD4490-A]
[Plots]
fs = 44.1 kHz
AKM
d
B
r
A
AK4490 THD+N vs. Input Level
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-122
-124
-126
-128
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 18. THD+N vs. Input Level
AKM
d
B
r
A
AK4490 THD+N vs. Input Frequency
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-122
-124
-126
-128
-130
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 19. THD+N vs. Input Frequency
<KM115900>
2014/01
- 24 -
[AKD4490-A]
fs = 44.1 kHz
AKM
AK4490 Linearity
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 20. Linearity
AKM
AK4490 Frequency Response
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0.5
+0.5
+0.4
+0.4
+0.3
+0.3
+0.2
+0.2
d
B
r
+0.1
+0.1
+0
+0
d
B
r
A
-0.1
-0.1
B
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
-0.5
Hz
Figure 21. Frequency Response
<KM115900>
2014/01
- 25 -
[AKD4490-A]
fs = 44.1 kHz
AKM
AK4490 Crosstalk
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
-90
-95
-100
-105
-110
-115
d
B
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 22. Crosstalk
AKM
AK4490 FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 23. FFT (0dBFS Input)
<KM115900>
2014/01
- 26 -
[AKD4490-A]
fs = 44.1 kHz
AKM
AK4490 FFT (-60dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 24. FFT (-60dBFS Input)
AKM
AK4490 FFT (No Signal Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 25. FFT (No Signal Input)
<KM115900>
2014/01
- 27 -
[AKD4490-A]
fs = 44.1 kHz
AKM
AK4490 Out of Band Noise
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 26. Out of Band Noise
<KM115900>
2014/01
- 28 -
[AKD4490-A]
fs = 96 kHz
AKM
d
B
r
A
AK4490 THD+N vs. Input Level
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-122
-124
-126
-128
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 27. THD+N vs. Input Level
AKM
d
B
r
A
AK4490 THD+N vs. Input Frequency
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-122
-124
-126
-128
-130
40
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 28. THD+N vs. Input Frequency
<KM115900>
2014/01
- 29 -
[AKD4490-A]
fs = 96 kHz
AKM
AK4490 Linearity
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 29. Linearity
AKM
AK4490 Frequency Response
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0.5
+0.5
+0.4
+0.4
+0.3
+0.3
+0.2
+0.2
d
B
r
+0.1
+0.1
+0
+0
d
B
r
A
-0.1
-0.1
B
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
22.5k
25k
27.5k
30k
32.5k
35k
37.5k
40k
-0.5
Hz
Figure 30. Frequency Response
<KM115900>
2014/01
- 30 -
[AKD4490-A]
fs = 96 kHz
AKM
AK4490 Crosstalk
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
-90
-95
-100
-105
-110
-115
d
B
-120
-125
-130
-135
-140
-145
-150
40
50
100
200
500
1k
2k
5k
10k
20k
40k
20k
40k
Hz
Figure 31. Crosstalk
AKM
AK4490 FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
Hz
Figure 32. FFT (0dBFS Input)
<KM115900>
2014/01
- 31 -
[AKD4490-A]
fs = 96 kHz
AKM
AK4490 FFT (-60dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
20k
40k
20k
40k
Hz
Figure 33. FFT (-60dBFS Input)
AKM
AK4490 FFT (No Signal Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
Hz
Figure 34. FFT (No Signal Input)
<KM115900>
2014/01
- 32 -
[AKD4490-A]
fs = 96 kHz
AKM
AK4490 FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 35. FFT (Notch)
<KM115900>
2014/01
- 33 -
[AKD4490-A]
fs = 192 kHz
AKM
d
B
r
A
AK4490 THD+N vs. Input Level
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-122
-124
-126
-128
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
50k
80k
dBFS
Figure 36. THD+N vs. Input Level
AKM
d
B
r
A
AK4490 THD+N vs. Input Frequency
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
-90
-92
-94
-96
-98
-100
-102
-104
-106
-108
-110
-112
-114
-116
-118
-120
-122
-124
-126
-128
-130
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 37. THD+N vs. Input Frequency
<KM115900>
2014/01
- 34 -
[AKD4490-A]
fs = 192 kHz
AKM
AK4490 Linearity
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 38. Linearity
AKM
AK4490 Frequency Response
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0.4
+0.4
+0.2
+0.2
+0
+0
-0.2
-0.2
-0.4
-0.4
d
B
r
-0.6
-0.6
-0.8
-0.8
d
B
r
A
-1
-1
B
-1.2
-1.2
-1.4
-1.4
-1.6
-1.6
-1.8
-1.8
-2
5k
10k
15k
20k
25k
30k
35k
40k
45k
50k
55k
60k
65k
70k
75k
80k
-2
Hz
Figure 39. Frequency Response
<KM115900>
2014/01
- 35 -
[AKD4490-A]
fs = 192 kHz
AKM
AK4490 Crosstalk
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
-90
-95
-100
-105
-110
-115
d
B
-120
-125
-130
-135
-140
-145
-150
90
200
500
1k
2k
5k
10k
20k
50k
80k
50k
80k
Hz
Figure 40. Crosstalk
AKM
AK4490 FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 41. FFT (0dBFS Input)
<KM115900>
2014/01
- 36 -
[AKD4490-A]
fs = 192 kHz
AKM
AK4490 FFT (-60dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
50k
80k
Hz
Figure 42. FFT (-60dBFS Input)
AKM
AK4490 FFT (No Signal Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 43. FFT (No Signal Input)
<KM115900>
2014/01
- 37 -
[AKD4490-A]
fs = 192 kHz
AKM
AK4490 FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
d
B
r
A
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 44. FFT (Notch)
<KM115900>
2014/01
- 38 -
[AKD4490-A]
8. Revision History
Date
(y/m/d)
14/01/14
Manual
Revision
KM115900
Board
Revision
0
Reason
Page
Contents
First Edition
<KM115900>
2014/01
- 39 -
[AKD4490-A]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application of
AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants any
license to any intellectual property rights or any other rights of AKM or any third party with respect
to the information in this document. You are fully responsible for use of such information contained
in this document in your product design or applications. AKM ASSUMES NO LIABILITY FOR
ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH
INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including
but not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry,
medical equipment, equipment used for automobiles, trains, ships and other transportation, traffic
signaling equipment, equipment used to control combustions or explosions, safety devices, elevators
and escalators, devices related to electric power, and equipment used in finance-related fields. Do
not use Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible
for complying with safety standards and for providing adequate designs and safeguards for your
hardware, software and systems which minimize risk and avoid situations in which a malfunction or
failure of the Product could cause loss of human life, bodily injury or damage to property, including
data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and regulations.
The Products and related technology may not be used for or incorporated into any products or
systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws
or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation,
the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth
in this document shall immediately void any warranty granted by AKM for the Product and shall not
create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
<KM115900>
2014/01
- 40 -
5
4
3
2
1
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
CN1
92pin_1
CN2
VSSR
46
10
0
VSSL VSSR
0
10
0
70
0
VSSL
VDDL
VDDR
CN3
(short)
(short)
R204
R203
25
AOUTRP
+
20
19
18
17
16
15
14
13
12
11
DIF2/CAD0
31
SW 10
12
1
2
3
4
5
6
7
8
9
10
SMUTE
SD
SLOW
DIF0
DIF1
DIF2/CAD0
PSN
DEM0
DEM1
ACKS/CAD1
100
100
100
100
100
JP12
PS3
29
28
CDTI/SDA
GND
SLOW
27
R225
R226
100
100
R227
10k
26
10k
10k
10k
10k
10k
10k
10k
10k
10k
10K
DIF1/DZFR
32
25
R228
R229
R230
R231
R232
R233
R234
R235
R236
R237
DIF0/DZFL/TSTO
11
10
SLOW/CDTI/SDA
SD/CCLK/SCL
0
B
ON
100
9
R215
R238
C215
92
13
PSN
CDTI/SDA
DVSS
14
JP14
DZFL
CCLK/SCL
0
91
33
15
30
R223
100
R222
JP10
PS1
SDATA1/DSDL
H
TP1
PDN
90
AOUTRP
AOUTRN
R210
VREFHR
26
VDDR
AOUTRN
27
28
VSSR
VDDR
29
30
JP13
PS4
34
16
JP15
DZFR
CCLK/SCL
GND
SD
TP4
DVSS
35
VREFHR
17
I2C
JP11
PS2
L
89
0
SMUTE
R239
R221
100
R220
88
8
SMUTE/CSN
NC
1
DVSS
87
A
VSSR
VSSL
31
32
VSSL
VDDL
33
34
VDDL
35
DVDD
DVSS
85
86
DVSS
48
C214
0.1u
WCK/SSLOW
+
B
C213
10u(A)
DEM0
7
MCLK
84
DEM1
MCLK
100
47
AVSS
6
46
R214
1M
18
NC
LRCK/DSDR/DINR
AVDD
83
36
C210
220u(A)
19
ACKS/CAD1
SDATA/DSDL/DINL
45
VREFLR
C209
0.1u
20
VREFHR
AVDD
5
AVSS
C212
0.1u
37
10u(A)
21
VREFHR
NC
44
C211
10u(A)
4
+
BICK/DCLK/BCK
AVSS
U1
AK4490
VREFHL
43
82
VREFLR
VREFHL
42
VREFHL
VREFLR
VREFLL
C206
22
R224
R216
R217
R218
R219
41
VREFLL
3
C208
0.1u
+
TP5
AVSS
81
C207
220u(A)
23
VCOMR
24
0.1u
40
R213
1M
24
NC
PDN
VREFLL
80
C
38
VCOML
39
40
39
NC
38
2
+
10u(A)
AOUTLN
36
AOUTLP
37
C205
C204 0.1u
R202
R201
78
41
VSSR
+
77
C
79
R207
R208
C202 10u(A)
C203 0.1u
76
VREFLR
0
C201 10u(A)
+
VSSL
CSN
75
43
42
(short)
(short)
74
44
TP3
VSSR
R212
0
R211
VREFHL
73
VREFLL
R209
AOUTLP
TP2
VSSL
AOUTLN
72
45
VSSR
+
VSSL
R206
D
71
R205
D
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
92pin_2
1
92pin_3
A
Title
CN4
92pin_4
DVSS
5
4
Size
A3
- 41 3
Date:
2
AKD4490-A
Document Number
AKD4490-A-48QFP
Thursday, December 05, 2013
Sheet
1
Rev
0
1
of
1
B
C
D
E
J4
VDDL
+5V
+5V
VCC_R
IN
+
C50
10u
+
2
1
36
EMCK
LRCK
ELRCK
SDTO
INT0
BICK
INT1
OVSS
37
CM0/CDTO/CAD1
OVDD
+
C54
470u
GND
AOUTRP
AOUTRN
VREFHR
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
C55
0.1u
16
CN3
CN2
CN1
92pin_3
15
70
46
71
45
72
44
73
43
74
42
75
41
76
40
77
39
78
38
79
37
R55
80
36
5.1
81
35
82
34
83
33
84
32
85
31
86
30
87
29
88
28
89
27
90
26
91
25
14
13
12
4
MCKO1
U7
OCKS0/CSN/CAD0
DVSS
AK4115
2
46
47
IPS1/IIC
XSEL/RX7
PSEL
PDN
XTL0
DIF1/RX6
XTL1
TEST
FILT
DIF0/RX5
9
2
VCC_R
8
7
C61
0.1u
6
PORT1
1
2
3
4
5
5
10
9
8
7
6
EXT
4
R56
3
(short)
R46
2
R57
1
(short)
DIR
JP5
MCLK
R47
100
SW2
I2C
5.1
EXT
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
3
4
R
AVSS
48
DVDD
10
IPS0/RX4
45
VIN
BVSS
AVDD
44
VCC_R
DVSS
RX3
43
AVSS
42
DAUX
RX2
C59
10u
DVDD
AVDD
C60
0.1u
RXN0
+
ACKS
41
VCC_R
P/SN
47k
AVDD
R51
47k
VCOM
R50
11
2
1
OCKS1/CCLK/SCL
RX1
40
MCKO2
AVSS
39
CM1/CDTI/SDA
RXP0
38
OCKS1
OCKS0 3
VREFHL
OUT
69
C56 C57
470u 0.1u
SW1
L
C53
0.1u
1
TEST2
H
C49
0.1u
AOUTLPAOUTLN
TEST1
35
IN
REG
5.1
34
C48
0.1u
67
17
18
19
+
C58
0.1u
B
C
21
20
U
VOUT
22
TVDD
24
25
26
27
28
29
23
TX0
TXP1
TXN1
TVSS
XTI1
XTO1
XTI2
30
OVDD
XTO2
31
32
OVSS
EBICK
C46 C47
470u 0.1u
OUT
JP3
AVDD
MVDD
IN
33
REG
OUT
68
C52
0.1u
T3
R45
MVDD
REG
+3V
C51
0.1u
VCC_R
JP2
VDDR
T2
T1
J6
AVDD
1
JP1
VDDL
MVDD
VCC_R
GND
VCC_R
J5
VDDR
GND
A
C65
0.1u
R60
10k
+
C67
4.7u
3
C68
10u
1M
R66
VCC_R
1M
R49
open
VCC_R
+
R63
3
R48
10k
C66
0.1u
C70
0.1u
+
C71
10u
92
R67
R68
+ C77
L
10u
JP9
RX-SEL
H
J9
COAX
C79
0.1u
R72
75
1
0.1u
1
3
5
9
11
13
14
7
SW3
PDN
C78
0.1u
1A
2A
3A
4A
5A
6A
VCC
GND
1Y
2Y
3Y
4Y
5Y
6Y
23
22
21
20
19
18
17
16
15
14
10
9
8
7
6
5
4
3
2
4
6
8
10
12
DIR
74HC14
JP6
BICK
C80
0.1u
DIR
R52
EXT
R53
JP7
SDTO
JP8
LRCK
4
DIR
R54
EXT
REG
51
J7
DVDD
+3V
JP4
DVDD
51
MVDD
51
4
T4
VCC_R
EXT
OUT
R58
10k
PORT3
10
8
6
4
2
PORT2
10
MCLK 1
9
BICK 2
8
SDTO 3
7
LRCK 4
5
9
7
5
3
1
uP-I/F
CSN
CCLK
CDTI
R59
10k
GND
A
U9
2
C76
3
2
1
2
1
10k
D1
2
GND
OUT
3
13
K
R69
47u
VCC
92pin_2
12
short
1
L1
PORT4
24
CN4
92pin_1
92pin_4
11
(short)
IN
C62
0.1u
C64
0.1u
R61
10k
+
C63
470u
U8
R64
470
R62
470
R65
470
2
3
5
6
11
10
14
13
1
15
6
1A
1B
2A
2B
3A
3B
4A
4B
A/B
G
1Y
2Y
3Y
4Y
VCC
GND
74LVC157
EXT
4
7
9
12
16
8
C69
0.1u
J8
REG(+15V)
OUT
C72
0.1u
GND
T5
MVDD
IN
C73
0.1u
C74
47u
+
+
C75
470u
5
5
- 42 -
Title
AKD4490-A
Document Number
Size
A1
A
B
C
D
Rev
Under the Sub-board
Date:
Thursday, December 05, 2013
E
0
Sheet
1
of
3
A
B
C
D
E
C1
6.8n
R5
10k
-
1
6
LME49710NA
C5
6.8n
R6
620
J12
Lch
C10
100p
3
3
+
3
AOUTLN
LME49710NA
R11
100
J1
LOUT
R13
open
C12
1n
C11
open
-
2
U3
+
2
C15
100p
R18
10k
6
6
LME49710NA
R19
4
C14
100u
3
100
R17
220
7
R16
220
C8
short
U2
2
1
R84
R15
short
2
R14
560
2
2
C7
open
R10
short
1
C13
6.8n
R9
620
100
R12
330
R83
C9
100p
R7
short
C6
open
R8
300
C4
1n
+
2
C3
100p
4
C2
100u
R4
560
U1
+
4
7
3
7
+
R3
220
+
R2
220
AOUTLP
-
R1
short
C16
6.8n
MVDD
R20
5.1
5.1
C21
100p
R22
330
C17
0.1u
+
C18 C19
10u 0.1u
+
R21
300
J2
-15V
C20
10u
C22
100p
C23
470u
3
C24
6.8n
7
3
AOUTRP
-
6
C31
6.8n
100
+
7
R40
220
3
AOUTRN
5
R42
10k
+
2
C42
100p
-
R34
short
R35
620
U6
6
C43
6.8n
C44
100p
R41
560
3
6
LME49710NA
C41
1n
R36
100
R37
open
J3
ROUT
C39
open
LME49710NA
R44
330
R43
300
5
C45
100p
Title
Size
A3
- 43 A
2
C38
short
U5
4
C40
100u
C35
open
C36
open
7
R86
4
2
+
2
R33
short
4
3
1
3
R32
620
100
C33
100p
C37
6.8n
R39
220
5.1
C30
10u
C34
1n
J13
Rch
R31
330
R85
C32
100p
R38
short
C28 C29
10u 0.1u
R29
560
R30
300
4
+
C27
0.1u
LME49710NA
1
R28
10k
+
2
C26
100p
4
C25
100u
MVDD
R23
5.1
U4
+
+
R27
220
-
R26
220
3
R24
+
R25
short
+
1
B
C
Date:
D
AKD4490-A
Document Number
Rev
0
External LPF
Thursday, December 05, 2013
Sheet
E
2
of
3
A
B
C
D
E
J10
1
1
VREFHL
Q1
BCP 56
R73
VREFHL
+
R74
270 +
C82
0.1u
+
200
R75
3.83k
C83
0.1u
C81
100u
D2
U10
R76
510
2
1
2
3
+
C84
100u
NC
-IN
V+
+IN
4
+
NC
OUT
V-
NC
8
2
7
6
Q2
SB1188 CSC
5
AD817A/AD
D3
C86
470u
+
C85
100u
R77
3.6k
3
3
+
+
2
3
4
R79
510
NC
NC
-IN
V+
+IN
OUT
V-
NC
AD817A/AD
8
7
6
5
Q3
SB1188 CSC
D5
270
+
R80
C90
0.1u
R78
3.6k
U11
D4
1
4
C87
100u
R81
4
C91
0.1u
R82
3.83k
200
+
C89
100u
+
+
470u
C88
C92
100u
VREFHR
Q4
BCP 56
VREFHR
J11
5
5
Title
Size
A3
- 44 A
B
C
Date:
D
AKD4490-A
Document Number
Rev
0
Puwer Supply Unit
Thursday, December 05, 2013
Sheet
E
3
of
3
- 45 -
- 46 -
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