AK4495SEQ

[AKD4495-SA]
AKD4495-SA
AK4495 Sound Quality Evaluation Board Rev.0
1. GENERAL DESCRIPTION
The AKD4495-SA is a sound quality evaluation board for AK4495. The AKD4495-SA has digital audio
interfaces, enabling to interface to digital audio systems via optical or coaxial connector.
 Ordering Guide
AKD4495-SA
---
AK4495 Sound Quality Evaluation Board
(Control software and USB cable are included in this package.)
2. FUNCTION
 Three digital audio interfaces
- Coaxial Input
- Optical Input
- 10pin Header for serial control mode
 USB control port
 On-board Analog output buffer and LPF circuit
+VOP
to D3V
[+3.3V ← +15V]
Power Circuit
Regulator (T1)
[+5V → +3.3V]
USB
(CTRL)
-VOP
Power Circuit
[+5V ← +15V]
to AVDD
and DVDD
Power Circuit
[+5V ← +15V]
to VDDL/R to VREFHL/R
PIC18F4550
from D3V
LOUT
COAX In
AK4118A
AK4495
ROUT
Opt In
1st Order LPF
10pin Header
(DSP)
Figure 1. AKD4495-SA Block Diagram (Note 1)
Note 1. Circuit diagram and PCB layout are attached at the end of this manual.
Coaxial connection is recommended when evaluating the sound quality.
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3. Table of Contents
1. GENERAL DESCRIPTION..................................................................................................................1
 Ordering Guide ..................................................................................................................................1
2. FUNCTION ..........................................................................................................................................1
3. Table of Contents .................................................................................................................................2
4. Evaluation Board Diagram ...................................................................................................................3
 Board Diagram ..................................................................................................................................3
 Description.........................................................................................................................................3
5. Operation Sequence ............................................................................................................................5
 Set up the Power Supply Lines .........................................................................................................5
 Evaluation Mode................................................................................................................................5
 Switch Setting....................................................................................................................................6
 Power ON ..........................................................................................................................................8
 Board Control ....................................................................................................................................8
6. CONTROL SOFTWARE MANUAL ......................................................................................................9
 Evaluation Board and Control Software Settings..............................................................................9
 Operation Overview.........................................................................................................................10
 Tab Descriptions..............................................................................................................................11
 Dialog Boxes....................................................................................................................................13
7. Measurement Results .......................................................................................................................18
8. Revision History.................................................................................................................................34
IMPORTANT NOTICE............................................................................................................................35
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4. Evaluation Board Diagram
 Board Diagram
Figure 2. Board Diagram
 Description
(1) Power Supply and GND connector (+VOP, GND, -VOP)
Refer to the “ Set up the power supply lines“.
(2) SPDIF input connector (J6 / BNC connector, PORT2 / Optical connector)
SPDIF signal Input to the AK4118A.
When using J6 (BNC connector), Set to R32 = “0 ohm” and R31 = “open”.
When using PORT2 (Optical connector), Set to R32 = “open” and R31 = “0 ohm”.
(3) Analog output connector (J4 / J5, BNC connector)
Single-ended output connector.
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(4) DSP PORT (PORT1)
10 pin header for interfacing with external data sources, enabling to connect other audio systems.
When using PORT1 (DSP), Set to R14, R18, R22, R28 = “open” and R13, R16, R21, R24, R23 = “0 ohm”.
Pin
1
3
5
7
9
I/O
I
I
I
I
I
Function
MCLK
BICK/DCLK
LRCK/DSDR
SDATA/DSDL
WCK
pin
2
4
6
8
10
I/O
P
P
P
P
P
Function
GND
GND
GND
GND
GND
Table 1. Pin Assignment of DSP PORT
(5) AK4118A (U2)
AK4118A has Digital Audio I/F Transceiver.
When evaluating the sound quality, Using AK4118A with SPDIF signal.
(6) PIC18F4550 (U4)
USB control chip.
Control registers of the AK4495 can be set by a PC via USB port.
(7) Slide switch (SW3 / SW4)
Mode setting switch for AK4118A and AK4495.
Upper-side is “ON (H)” and lower-side is “OFF (L)”.
Refer to “ Switch Setting”.
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5. Operation Sequence
 Set up the Power Supply Lines
Name
Color
Voltage
+VOP
Red
+12+15V
-VOP
Blue
-12-15V
GND
Black
0V
Breakdown
Power circuit,
Input / Output Buffer (OP Amp.)
Note
Must be connected.
Input / Output Buffer (OP Amp.)
Must be connected.
Ground
Must be connected.
Table 2. Power Supply Lines (Note 2)
Note 2. Each supply line should be distributed separately from the power supply unit
 Evaluation Mode
(1) D/A Evaluation using the AK4118A (DIR) (Coaxial connectior) < default >
The AK4118A generates MCLK, BICK, LRCK, SDATA from the data from the BNC connector (J6).
Evalutations using a test CD and etc. are available(Note 3).
Setting: R31 = “open”, R32 = “0 ohm”
Note 3. Coaxial connection is recommended when evaluating the sound quality.
(2) D/A Evaluation using the AK4118 (DIR) (Optical connectior)
The AK4118A generates MCLK, BICK. LRCK, SDATA from the data from the optical connector (PORT2).
Evalutations using a test CD and etc. are available.
Setting: R31 = “0 ohm”, R32 = “open”
(3) All interface signals including the master clock are supplied externally (PORT1)
Setting: R18, R22, R25, R28 = “open”, R16, R21, R24, R23 = “0 ohm”
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 Switch Setting
(1) Parallel / Serial Control Mode select switch.
[SW5] (P/S): Mode selects to “Parallel Control Mode” or “Serial Control Mode”.
(a) Select Parallel Control Mode < Default >
(b) Select Serial Control Mode
SW5
P/S
Parallel
Control Mode
SW5
P/S
Serial
Control Mode
Parallel
Control Mode
Serial
Control Mode
Figure 3. P/S Setting (Note 4)
Note 4. When using “Serial Control Mode”, SW4 [No.5] is assignment by CAD0 pin and SW4 [No.9] is
assignment by CAD1 pin.
In addition, Except for SW4 [No.5 and No.9] is disabled.
(2) Other switch setting
Upper-side is “ON (H)” and lower-side is “OFF (L)”.
[SW2] (SMUTE): Soft-mute setting of AK4495. Keep “L” during normal operation.
[SW3] (SW DIP-2): AK4118A Setting
No.
Name
1
2
OCKS1
OCKS0
ON (“H”)
OFF (“L”)
Master Clock setting for AK4118A
Refer to Table 5
Default
ON
OFF
Table 3. AK4118A Mode Setting
[SW4] (SW DIP-10): AK4495 Setting
No.
Name
1
2
3
4
SD
SLOW
DIF0
DIF1
5
DIF2
/ CAD0
I2C
DEM0
DEM1
6
7
8
9
ACKS
/ CAD1
10
DFP
ON (“H”)
OFF (“L”)
Digital Filter Setting
Refer to Table 8
Audio I/F Format Setting for AK4495
Refer to Table 6
CAD0pin=”H”
CAD0pin=”L”
I2C-bus Control Mode 3-wire Serial Control Mode
De-emphasis Control
Refer to Table 7
Auto Setting Mode
Manual Setting Mode
CAD1pin=”H”
CAD1pin=”L”
Super Slow roll-off Filter Super Slow roll-off Filter
ON
OFF
Table 4. AK4495 Mode Setting
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Default
ON
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
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OCKS1
L
H
H
OCKS0
L
L
H
MCKO1
256fs
512fs
128fs
<Default>
Table 5. AK4118A Master Clock Setting
Mode
0
1
2
3
4
5
6
7
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
Input Format
16-bit LSB justified
20-bit LSB justified
24-bit MSB justified
24-bit I2S compatible
24-bit LSB justified
32-bit LSB justified
32-bit MSB justified
32-bit I2S compatible
LRCK
H/L
H/L
H/L
L/H
H/L
H/L
H/L
L/H
BICK
32fs
48fs
48fs
48fs
48fs
64fs
64fs
64fs
< Default >
Table 6. AK4495 Audio I/F Format
DEM1
0
0
1
1
DEM0
0
1
0
1
Mode
44.1kHz
OFF
48kHz
32kHz
< Default >
Table 7. De-emphasis Control
SD
0
0
1
1
SLOW
0
1
0
1
Mode
Sharp roll-off filter
Slow roll-off filter
Short delay sharp roll-off filter
Short delay slow roll-off filter
< Default >
Table 8. Digital Filter Setting
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 Power ON
Upper-side is “ON (H)” and lower-side is “OFF (L)”.
Power-down reset by SW1(PDN) must be made once after power up the evaluation board. Put the SW1 to “L”
for power-down reset of the AK4495 and AK4118A, and the return them to “H” to release the power-down
states.
[SW1] (PDN): Resets the AK4495 and AK4118A (Keep “H” during normal operation).
This switch must be set to “L” once upon power up the evaluation board to reset the AK4495
and AK4118A.
 Board Control
The AKD4495-SA can be controlled via a USB port with a PC. Connect J7 (USB) connector to a PC with USB
cable. The control software is included in the AK4495-SA package. Refer to the “Control Software Manual”
paragraph for operational sequence of the control software.
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6. CONTROL SOFTWARE MANUAL
 Evaluation Board and Control Software Settings
1. Set up the evaluation board as needed. According to the previous terms.
2. Connect the evaluation board and a PC with USB cable.
3. USB control is recognized as HID (Human Interface Device) on PC. When it is not recognized properly, please
disconnect the evaluation board once and reconnect it to the PC.
4. Insert the CD-ROM labeled “AKD4495 Evaluation Kit” into the CD-ROM drive.
5. Access the CD-ROM drive and double-click the icon “akd4495-sa.exe” to open the control program.
6. Begin evaluation by following the procedure below.
Figure 4. Control Software Window
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 Operation Overview
Register map is controlled by this control software.
Frequently used buttons such as the register initializing button “Write Default”, are located outside of the tab
window. Refer to the “■ Dialog Boxes” section for details of each dialog box setting.
1. [Port Reset]: Resets the USB port of the main board.
Click this button after the control software starts up when a PC is connected to J7 (USB) port
of the AKD4495-SA.
2. [Write Default]: Initializes register values.
Use this button to initialize the registers after the device is reset by hardware reset.
3. [All Write]: Executes all write commands of displayed registers.
4. [All Read]: Executes read commands for all registers displayed (Note 5).
5. [Save]: Saves current register settings as a file.
6. [Load]: Executes data write from a saved file.
7. [All Reg Write]: “All Reg Write” dialog box pops up.
8. [Data R/W]: “Data R/W” dialog box pops up.
9. [Sequence]: “Sequence” dialog box pops up.
10. [Sequence(File)]: “Sequence(File)” dialog box pops up.
11. [Read]: Reads current register settings and displays to the register area (on the right of the main window).
This is different from [All Read] button as it does not reflect to the register map. It only displays
register values in hexadecimal numbers (Note 5).
Note 5. [All Read] button and [Read] button are only available for “I2C-bus Control Mode” setting.
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 Tab Descriptions
1. [REG]: Register Map
This tab is for register read and write.
Each bit on the register map is a push-button switch.
Button Down indicates “1” and the bit name is shown in red (when read-only, the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only, the name is shown in gray)
Grayed out registers are read-only registers. They cannot be controlled.
The registers which are not defined on the datasheet are indicated as “---”.
Figure 5. REG Window
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1-1. [Write]: Data Write Dialog Box
Select the [Write] button located on the right of the each corresponding address when changing two or more
bits on the same address simultaneously.
Click the [Write] button for the register pop-up dialog box shown below.
When the checkbox next to the register name is checked, the data will become “1”. When the checkbox is
not checked, the data will become “0”. Click [OK] to write the set values to the registers, or click [Cancel] to
cancel this setting.
Figure 6. Register Set Window
1-2. [Read]: Data Read Dialog Box (I2C-bus Control Mode Only)
Click the [Read] button located on the right of the each corresponding address to execute a register read.
The current register value will be displayed in the register window as well as in the upper right hand DEBUG
window.
Button Down indicates “1” and the bit name is shown in red (when read-only the name is shown in dark red).
Button Up indicates “0” and the bit name is shown in blue (when read-only the name is shown in gray).
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 Dialog Boxes
1. [All Req Write] : [All Register Write] Dialog Box
Click [All Reg Write] button in the main window to open register setting files.
Register setting files saved by [SAVE] button can be applied.
Figure 7. All Reg Write Window
[Open (left)]
[Write]
[Write All]
[Help]
[Save]
[Open (right)]
[Close]
: Open a register setting file (*.akr).
: Executes register writing.
: Executes all register writings.
Writings are executed in descending order.
: A help window pops up.
: Saves register setting file assignment. The file name is “*.mar”.
: Open a register setting assignment file that is saved as “*. mar”.
: Closes the dialog box and finishes this process.
Operating Suggestions
(1) Those files saved by [Save] button and opened by [Open] button on the right of the dialog “*.mar” should be
stored in the same folder.
(2) When register settings are changed by [Save] button in the main window, re-read the file to reflect new
register settings.
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2. [Data R/W]: [Data R/W] Dialog Box
Click the [Data R/W] button in the main window to open the data read/write dialog box shown below.
A data write is executed to specified address.
Figure 8. Data R/W Window
[Address] Box : Input write data address in hexadecimal numbers for data writing.
[Data] Box
: Input start data in hexadecimal numbers.
[Mask] Box : Input mask data in hexadecimal numbers.
This value “ANDed” with the write data becomes the input data.
[Write]
: Writes data to the address specified in “Address” box (Note 6).
[Read]
: Reads data from the address specified by “Address” box.
The result will be shown in the Read Data Box in hexadecimal numbers (Note 7).
[Close] Button : Closes the dialog box.
Data write can be cancelled by this button instead of [Write] button.
Note 6. The register map will be updated after executing the [Write] command.
Note 7. [Read] button is only available for “I2C-bus Control Mode” setting.
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3. [Sequence]: [Sequence] Dialog Box
Click the [Sequence] button to open register sequence setting dialog box shown below.
Register sequence can be set in this dialog box.
Figure 9. Sequence Window
Sequence Setting
Set register sequence according to the following process bellow.
(1) Select a command
Use [Select] pull-down box to choose commands.
Corresponding boxes will be valid.
< Select Pull-down menu >
· No_use
: Not using this address
· Register
: Register write
· Reg(Mask) : Register write (Masked)
· Interval
: Takes an interval
· Stop
: Pauses the sequence
· End
: Ends the sequence
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(2) Input sequence
[Address]
[Data]
[Mask]
[ Interval ]
: Data address
: Write data
: Mask
The value in the [Data] box is ANDed with the value in the [Mask] box. This data
becomes the actual input data.
When Mask = 0x00, current setting is hold.
When Mask = 0xFF, the 8bit data which is set in the [Data] box is written.
When Mask =0x0F, lower 4bit data which is set in the [Data] box is written.
Upper 4bit is hold to current setting.
: Interval time
Valid boxes for each process command are shown below.
· No_use
· Register
· Reg(Mask)
· Interval
· Stop
· End
: None
: [Address], [Data], [Interval]
: [Address], [Data], [Mask], [Interval]
: [Interval]
: None
: None
Control Buttons
Functions of Control Buttons are shown below.
[Start] Button
[Help] Button
[Save] Button
[Open] Button
[Close] Button
: Executes the sequence
: A help window pops up.
: Saves sequence settings as a file. The file name is “*.aks”.
: Open a sequence setting file “*.aks”.
: Closes the dialog box and finish the process.
Stop of the sequence
When “Stop” is selected in the sequence, the process is paused. It starts again when the [Start] button is
clicked. Restart step number is shown in the “Start Step” box. When executing the process until the end of
sequence, the “Start Step” value will return to “1”.
The sequence can be started from any step by writing the step number to the “Start Step” box.
Write “1” to the “Start Step” box and click [Start] button, when restarting the process from the beginning.
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4. [Sequence(File)]: [Sequence by *.aks file] Dialog Box
Click the [Sequence(File)] button to open sequence setting file dialog box shown below.
Files saved in the “Sequence setting dialog” can be applied in this dialog.
Figure 10. Sequence(File) Window
[Open (left)] : Open a sequence setting file (*.aks).
[Start]
: Executes the sequence setting.
[Start All]
: Executes all sequence settings.
Sequences are executed in descending order.
[Help]
: A help window pops up.
[Save]
: Saves a sequence setting file assignment. The file name is “*.mas”.
[Open(right)] : Open a saved sequence setting file assignment “*. mas”.
[Close]
: Closes the dialog box and finish the process.
Operating Suggestions
(1) Files saved by the [Save] button and opened by the [Open] button on the right of the dialog “*.mas”
should be stored in the same folder.
(2) When “Stop” is selected in the sequence the process will be paused and the message box shown below
pops up. Click “OK” to continue the process.
Figure 11. Sequence Pause Window
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7. Measurement Results
[Measurement condition]
 Measurement unit
 MCLK
 BICK
 fs
 Bit
 Power Supply
 Interface
 Temperature
 Operational Amplifiers
: Audio Precision System two Cascade (AP2)
: 512fs (44.1kHz), 256fs (96kHz), 128fs (192kHz)
: 64fs
: 44.1kHz, 96kHz, 192kHz
: 24bit
: AVDD= DVDD=3.3V, VDDL/R=VREFHL/R=5V
: Internal DIR (44.1kHz, 96kHz, 192kHz)
: Room
: OPA604
fs=44.1kHz
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Parameter
Input signal
S/(N+D)
1kHz, 0dB
DR
1kHz, -60dB
S/N
“0” data
Measurement filter
20kHz LPF
A-weighted
20kHz LPF
A-weighted
Lch
97.5 dB
113.3 dB
115.7 dB
113.1 dB
115.6 dB
Results
/
/
/
/
/
/
Rch
97.4 dB
113.4 dB
115.8 dB
113.2 dB
115.6 dB
Lch
95.6 dB
105.9 dB
110.9 dB
108.9 dB
115.2 dB
Results
/
/
/
/
/
/
Rch
96.1 dB
106.3 dB
111.8 dB
108.9 dB
115.6 dB
Lch
94.3 dB
106.5 dB
112.2 dB
108.8 dB
115.2 dB
Results
/
/
/
/
/
/
Rch
95.7 dB
105.9 dB
111.6 dB
108.9 dB
115.4 dB
fs=96kHz
Measurement filter
40kHz LPF
A-weighted
40kHz LPF
A-weighted
fs=192kHz
Measurement filter
40kHz LPF
A-weighted
40kHz LPF
A-weighted
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Plots
(fs=44.1kHz)
AKM
AK4339TEST FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
10k
20k
Hz
Figure 12. FFT (0dBFS Input)
AKM
AK4339TEST FFT (-60dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
Hz
Figure 13. FFT (-60dBFS Input)
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(fs=44.1kHz)
AKM
AK4339TEST FFT (No Signal Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 14. FFT (No Signal Input)
AKM
AK4339TEST Out of Band Noise
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
20
50
100
200
500
1k
2k
5k
10k
20k
50k
100k
Hz
Figure 15. Out of Band Noise
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(fs=44.1kHz)
AKM
AK4339TEST THD+N vs. Input Level
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
-80
-85
-90
-95
d
B
r
A
-100
-105
-110
-115
-120
-125
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 16. THD+N vs. Input Level
AKM
AK4339TEST THD+N vs. Input Frequency
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
-80
-85
-90
-95
d
B
r
A
-100
-105
-110
-115
-120
-125
-130
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 17. THD+N vs. Input Frequency
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(fs=44.1kHz)
AKM
AK4339TEST Linearity
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 18. Linearity
AKM
d
B
r
A
AK4339TEST Frequency Response
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
+0.5
+0.5
+0.4
+0.4
+0.3
+0.3
+0.2
+0.2
+0.1
+0.1
+0
+0
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
2k
4k
6k
8k
10k
12k
14k
16k
18k
20k
d
B
r
B
-0.5
Hz
Figure 19. Frequency Response
[KM113800]
2013/09
- 22 -
[AKD4495-SA]
(fs=44.1kHz)
AKM
AK4339TEST Crosstalk
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=512fs, fs=44.1kHz
-80
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
20
50
100
200
500
1k
2k
5k
10k
20k
Hz
Figure 20. Crosstalk
[KM113800]
2013/09
- 23 -
[AKD4495-SA]
(fs=96kHz)
AKM
AK4339TEST FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
20k
40k
20k
40k
Hz
Figure 21. FFT (0dBFS Input)
AKM
AK4339TEST FFT (-60dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
Hz
Figure 22. FFT (-60dBFS Input)
[KM113800]
2013/09
- 24 -
[AKD4495-SA]
(fs=96kHz)
AKM
AK4339TEST FFT (No Signal Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
20k
40k
20k
40k
Hz
Figure 23. FFT (No Signal Input)
AKM
AK4339TEST FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
40
50
100
200
500
1k
2k
5k
10k
Hz
Figure 24. FFT (0dBFS Input, Notch)
[KM113800]
2013/09
- 25 -
[AKD4495-SA]
(fs=96kHz)
AKM
AK4339TEST THD+N vs. Input Level
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
-80
-85
-90
-95
d
B
r
A
-100
-105
-110
-115
-120
-125
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 25. THD+N vs. Input Level
AKM
AK4339TEST THD+N vs. Input Frequency
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
-80
-85
-90
-95
d
B
r
A
-100
-105
-110
-115
-120
-125
-130
40
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 26. THD+N vs. Input Frequency
[KM113800]
2013/09
- 26 -
[AKD4495-SA]
(fs=96kHz)
AKM
AK4339TEST Linearity
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 27. Linearity
AKM
d
B
r
A
AK4339TEST Frequency Response
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
+0.5
+0.5
+0.4
+0.4
+0.3
+0.3
+0.2
+0.2
+0.1
+0.1
+0
+0
-0.1
-0.1
-0.2
-0.2
-0.3
-0.3
-0.4
-0.4
-0.5
2.5k
5k
7.5k
10k
12.5k
15k
17.5k
20k
22.5k
25k
27.5k
30k
32.5k
35k
37.5k 40k
d
B
r
B
-0.5
Hz
Figure 28. Frequency Response
[KM113800]
2013/09
- 27 -
[AKD4495-SA]
(fs=96kHz)
AKM
AK4339TEST Crosstalk
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=256fs, fs=96kHz
-80
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
40
50
100
200
500
1k
2k
5k
10k
20k
40k
Hz
Figure 29. Crosstalk
[KM113800]
2013/09
- 28 -
[AKD4495-SA]
(fs=192kHz)
AKM
AK4339TEST FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
50k
80k
Hz
Figure 30. FFT (0dBFS Input)
AKM
AK4339TEST FFT (-60dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 31. FFT (-60dBFS Input)
[KM113800]
2013/09
- 29 -
[AKD4495-SA]
AKM
AK4339TEST FFT (No Signal Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
50k
80k
50k
80k
Hz
Figure 32. FFT (No Signal Input)
AKM
AK4339TEST FFT (0dBFS Input)
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
-60
-70
d
B
r
A
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 33. FFT (0dBFS Input, Notch)
[KM113800]
2013/09
- 30 -
[AKD4495-SA]
AKM
AK4339TEST THD+N vs. Input Level
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
-80
-85
-90
-95
d
B
r
A
-100
-105
-110
-115
-120
-125
-130
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
50k
80k
dBFS
Figure 34. THD+N vs. Input Level
AKM
AK4339TEST THD+N vs. Input Frequency
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
-80
-85
-90
-95
d
B
r
A
-100
-105
-110
-115
-120
-125
-130
90
200
500
1k
2k
5k
10k
20k
Hz
Figure 35. THD+N vs. Input Frequency
[KM113800]
2013/09
- 31 -
[AKD4495-SA]
AKM
AK4339TEST Linearity
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0
-10
-20
-30
-40
-50
d
B
r
A
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-150
-140
-130
-120
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
+0
dBFS
Figure 36. Linearity
AKM
d
B
r
AK4339TEST Frequency Response
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
+0.4
+0.4
+0.2
+0.2
+0
+0
-0.2
-0.2
-0.4
-0.4
-0.6
-0.6
-0.8
-0.8
-1
d
B
r
-1
A
B
-1.2
-1.2
-1.4
-1.4
-1.6
-1.6
-1.8
-1.8
-2
-2.2
-2
5k
10k
15k
20k
25k
30k
35k
40k
45k
50k
55k
60k
65k
70k
75k
80k
-2.2
Hz
Figure 37. Frequency Response
[KM113800]
2013/09
- 32 -
[AKD4495-SA]
AKM
AK4339TEST Crosstalk
AVDD=DVDD=3.3V, VDDL/R=VREFHL/R=5V, MCLK=128fs, fs=192kHz
-80
-85
-90
-95
-100
-105
-110
d
B
-115
-120
-125
-130
-135
-140
-145
-150
90
200
500
1k
2k
5k
10k
20k
50k
80k
Hz
Figure 38. Crosstalk
[KM113800]
2013/09
- 33 -
[AKD4495-SA]
8.Revision History
Date
(YY/MM/DD)
13/09/13
Manual
Revision
KM113800
Board
Revision
0
Reason
Page
First edition
-
[KM113800]
Contents
2013/09
- 34 -
[AKD4495-SA]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the information
contained in this document without notice. When you consider any use or application of AKM product
stipulated in this document (“Product”), please make inquiries the sales office of AKM or authorized
distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and application
examples of AKM Products. AKM neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of AKM or any third party with respect to the information
in this document. You are fully responsible for use of such information contained in this document in
your product design or applications. AKM ASSUMES NO LIABILITY FOR ANY LOSSES
INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE USE OF SUCH INFORMATION
IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact, including but
not limited to, equipment used in nuclear facilities, equipment used in the aerospace industry, medical
equipment, equipment used for automobiles, trains, ships and other transportation, traffic signaling
equipment, equipment used to control combustions or explosions, safety devices, elevators and
escalators, devices related to electric power, and equipment used in finance-related fields. Do not use
Product for the above use unless specifically agreed by AKM in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are responsible for
complying with safety standards and for providing adequate designs and safeguards for your hardware,
software and systems which minimize risk and avoid situations in which a malfunction or failure of the
Product could cause loss of human life, bodily injury or damage to property, including data loss or
corruption.
4. Do not use or otherwise make available the Product or related technology or any information contained
in this document for any military purposes, including without limitation, for the design, development,
use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or missile technology
products (mass destruction weapons). When exporting the Products or related technology or any
information contained in this document, you should comply with the applicable export control laws and
regulations and follow the procedures required by such laws and regulations. The Products and related
technology may not be used for or incorporated into any products or systems whose manufacture, use, or
sale is prohibited under any applicable domestic or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the RoHS
compatibility of the Product. Please use the Product in compliance with all applicable laws and
regulations that regulate the inclusion or use of controlled substances, including without limitation, the
EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a result of
noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set forth in
this document shall immediately void any warranty granted by AKM for the Product and shall not create
or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
[KM113800]
2013/09
- 35 -
5
4
3
DVDD
AVSS
AVDD
2
VREF
1
VREFGND
D
D
MCLK
VREF_EX
VREFGND_EX
R1
(open)
R4
PDN
51
1
R3
2M
34
AOUTLP
AOUTLN
AOUTLP
35
VCOML
VREFLL
C6
100u(A)
36
0.01u(F)
VREFLL
+
38
39
VREFHL
40
C5
AVDD
41
AVSS
42
MCLK
43
220u(A)
VREFHL
+
C8
100p(F)
DVSS
44
DVDD
DVSS
C4
0.01u(F)
1M
C3
+
C7
0.01u(F)
R2
37
C1
100u(A)
+
C2
100u(A)
PDN
AOUTLN
33
C
C
2
SDATA/DSDL/DINL
3
LRCK/DSDR/DINR
4
W CK
5
SMUTE/CSN
6
SD/CCLK/SCL
7
SLOW /CDTI/SDA
8
BICK/DCLK/BCK
VDDL
SDATA/DSDL/DINL
VDDL
LRCK/DSDR/DINR
VSSL
U1
WCK
VSSL
AK4495
SMUTE/CSN
NC
SD/CCLK/SCL
VSSR
SLOW/CDTI/SDA
VSSR
DIF0/DZFL/TSTO
VDDR
DIF1/DZFR
VDDR
DIF2/CAD0
AOUTRN
32
31
30
220u(A)
28
1M
27
VDD
26
25
C11
0.01u(F)
C12
100u(A)
R6
1M
B
24
23
AOUTRP
VCOMR
VREFLR
VDDGND
AOUTRN
AOUTRP
C14
100u(A)
R9
2M
R10
R11
R5
1M
22
C15
21
0.01u(F)
20
19
VREFLR
VREFHR
18
10k
C13
C10
100u(A)
+
PSN
+
VREFHR
17
PSN
12
ACKS/CAD1
11
DIF2/CAD0
16
10
DEM1
0
15
R8
DEM0
DIF1
14
9
I2C
0
13
R7
+
29
B
DIF0
C9
0.01u(F)
+
BICK/DCLK/BCK
A
A
I2C
DVSS
DEM1
DEM0
VREF_EX
VREFGND_EX
ACKS/CAD1
Title
Size
A3
- 36 5
4
3
Date:
2
AKD4495-SA
Document Number
AK4495
Tuesday, September 10, 2013
Rev
0
Sheet
1
1
of
5
4
3
OCKS1
OCKS0
5
R12
PDN
10
8
6
4
2
51
4
3
D
2
H
SW3
9
7
5
3
1
OCKS
L
1
2
2
3
4
5
(open)
1
C26
0.1u
R32
0
0
DSP-BICK/DCLK/BCK
R16
(open)
DIR-BICK
R18
51
DSP-SDATA/DSDL/DINL
R21
(open)
DIR-SDATA
R22
51
DSP-LRCK/DSDR/DINR
R23
(open)
DIR-LRCK
R28
51
DSP-MCLK
R24
(open)
DIR-MCLK
R25
5.1
D
WCK
48
RX3
SDATA/DSDL/DINL
25
SDTO
26
BICK
27
DAUX
MCKO2
28
29
XTI
XTO
30
31
PDN
32
33
34
BICK/DCLK/BCK
TVDD
24
23
22
LRCK/DSDR/DINR
C
MCLK
C16
100p(F)
DIRVDD
21
20
+
C20
0.01u(F)
19
C21
10u(A)
18
17
16
B
C22
10u(A)
C23
0.01u(F)
15
14
13
VIN/GP0
R31
(open)
R14
12
51
NC/GP1
1
J6
COAX
R30
VSS4
XTL1
47
11
+ C25
10u(A)
TX0/GP2
XTL0
C24
0.1u
OPT
RX2
10
46
2
1
TX1/GP3
P/SN
3
TEST1
9
45
DIRVDD
BOUT/GP4
IPS1/IIC
GND
OUT
2
RX1
8
VCC
10u
COUT/GP5
DIF2/RX7
PORT2
L1
UOUT/GP6
NC
7
1
AK4118A
RX0
VSS1
44
VOUT/GP7
U2
6
43
VSS3
DIF1/RX6
42
DVDD
5
41
VCOM
TEST2
40
4
C19
10u(A)
DIF0/RX5
+
(open)
VSS2
3
R29
R
NC
R27
10k
MCKO1
2
39
C18
0.01u(F)
(open)
LRCK
AVDD
IPS0/RX4
38
D3V
CM0/CDTO/CAD1
C
CM1/CDTI/SDA
INT1
OCKS1/CCLK/SCL
35
OCKS0/CSN/CAD0
36
INT0
37
DIRVDD
R20
100
+
R19
100
R26
R13
DFP
PORT1
DSP
10k
R17
B
WCK
SDATA/DSDL/DINL
LRCK/DSDR/DINR
BICK/DCLK/BCK
MCLK
10k
R15
+
C17
10u(A)
1
R33
75
R34
100
A
R35
100
R36
100
R37
100
A
DIRVDD
Title
Size
A3
- 37 5
4
3
Date:
2
AKD4495-SA
Document Number
DIR
Tuesday, September 10, 2013
Rev
0
Sheet
1
2
of
5
5
4
3
2
1
SW5 Silk-Screen
D3V
R38
K
D
51
A
1
3
1
2
3
4
5
6
H
C27
0.01u(F)
14
2
SW 1
PDN
K
C28
10u(A)
+
7
C29
0.01u(F)
0
R43
10k
1A
1Y
2A
2Y
3A
3Y
4Y
4A
5Y
5A
6Y
6A
8
9
10
11
12
13
Vcc
GND
U3 74HC14
PICGND
SW 5
P/S
1
SMUTE
CSN
3
SD
4
CCLK/SCL
6
SLOW
7
CDTI/SDA
9
10
A
D2
1
3
12
L
R40
100
5
R41
100
8
R42
100
11
R44
100
SMUTE/CSN
SD/CCLK/SCL
SLOW /CDTI/SDA
PSN
PICGND
D3V
C30
0.01u(F)
C
20
19
18
17
16
15
14
13
12
11
2
C
2
0
H
SW 2
SMUTE
D
R39
10k
D1
L
[1-2,4-5,7-8,10-11]Side:"Parallel Control Mode"
[2-3,5-6,8-9,11-12]Side:"Serial Control Mode"
PDN
0
R45
R46
R47
PICGND
R48
H ON
10K
10K
10K
SW 4
Function
0
38
39
40
41
2
3
4
5
0
PICGND
32
35
36
1u
J7
VUSB
DD+
GND
USB
1
2
3
4
R78
R79
0
0
42
43
44
1
PIC18F4550
TQFP 44-PIN
RD0/SPP0
RD1/SPP1
RD2/SPP2
RD3/SPP3
RD4/SPP4
RD5/SPP5/P1B
RD6/SPP6/P1C
RD7/SPP7/P1D
U4
RC0/T1OSO/T13CKI
RC1/T1OSI/CCP2/UOE_N
RC2/CCP1/P1A
RC4/D-/VM
RC5/D+/VP
RC6/TX/CK
RC7/RX/DT/SDO
10K
10K
10K
10K
10K
10K
10K
10K
10K
10K
0
7
VDD0
NC/ICCK/ICPGC
NC/ICDT/ICPGD
NC/ICRST_N/ICVpp
NC/ICPORTS
OSC1/CLKI
OSC2/CLKO/RA6
RE0/AN5/CK1SPP
RE1/AN6/CK2SPP
RE2/AN7/OESPP
VUSB
RA0/AN0
RA1/AN1
RA2/AN2/Vref-/CVref
RA3/AN3/Vref+
RA4/T0CKI/C1OUT/RCV
RA5/AN4/SS_N/HLVDIN/C2OUT
USB-RST
C37
C36
0.1u
12
13
33
34
30
31
R73
100k
0
PICGND
1
C38
0.01u(F) 2
25
26
27
C39
19
20
21
22
23
24
0
PICGND
VCC_A
VCC_B
GND
DIR
A
22p
X1
20MHz
C40
22p
B
C41
R75
R76
R77
6
5
4
SN74LVC1T45DRLR
U6
5
0
37
0.01u(F)
U5
3
XTI
XTO
R63
R64
R65
R66
R67
R68
R69
R70
R71
R72
MCLR_N/Vpp/RE3
18
R62
6
28
VSS0
B
9
C42
A
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/AN11/KBI0/CSSPP
RB3/AN9/CPP2/VPO
RB2/AN8/INT2/VMO
RB1/AN10/INT1/SCK/SCL
RB0/AN12/INT0/FLT0/SDI/SDA
470n
SDA2
SDA1
SCL2
SCL1
4
PICGND
6
7
51
51
51
VREF2
8
EN
C44
0.01u(F)
VREF1
GND
3
2
1
C43
0.01u(F)
A
PCA9306DP1
0
0
Title
PICGND
PICGND
PIC18F4550
Size
A3
- 38 5
DFP
DIF0
DIF1
DIF2/CAD0
I2C
DEM0
DEM1
ACKS/CAD1
0
EP
C34
0.1u
100
100
100
100
100
100
100
100
R74
NC
GND
Vcont PCL
Vin
Vout
NC
NC
5V => 3.3V
4
3
2
1
0
PICGND
17
16
15
14
11
10
9
8
VDD1
VSS1
GND
200k
0
PICGND
C33
0.1u
29
2.2u
5
6
7
8
T1 TK73633AME
C35
VDD
R54
R55
R56
R57
R58
R59
R60
R61
SLOW
SD
C32
10u(A)
0
PICGND
1
2
3
4
5
R50
R51
R52
+
+
C31
10u(A)
B
4.7k
R53
R49
10k
10k
10k
USBVDD
SD 1
SLOW 2
DIF0 3
DIF1 4
DIF2/CAD0 5
I2C 6
DEM0 7
DEM1 8
ACKS/CAD1 9
DFP 10
L
4
3
Date:
2
AKD4495-SA
Document Number
PIC & SW
Tuesday, September 10, 2013
Rev
0
Sheet
1
3
of
5
5
4
3
2
1
D
D
R81
5.6k
C47
AOUTLP
R82
10
R83
3.6k
C49
R85
10
R88
30
+
220
R89
3.3n(F)
C51
2.2n(F)
C53
6.8n(F)
1.2k
2
C50
100p(F)
R87
1.8k
R90
C45
0.01u(F)
U7
1
C48
100p(F)
AOUTLN
R84
330p(F)
3
C54
1n(F)
4
75
NC
NC
-IN
V+
+IN
V-
OUT
NC
(short)
C46
220u(A)
8
7
6
C52
+
R80
R86
100
1
(short)
J4
LOUT
5
R91
(open)
OPA604
+
2
3
4
5
C55
(open)
R92
(short)
VOP-
C
C
C56
0.01u(F)
+
R94
5.6k
C60
B
AOUTRN
R95
30
R96
3.6k
C64
100p(F)
AOUTRP
10
+
220
R102
1.2k
C61
3.3n(F)
C63
2.2n(F)
C65
6.8n(F)
2
C62
100p(F)
R100
1.8k
R103
C58
0.01u(F)
U8
1
R98
10
R101
R97
330p(F)
3
C67
1n(F)
4
75
NC
NC
-IN
V+
+IN
OUT
V-
NC
(short)
VOP+
B
C59
220u(A)
8
7
6
C66
+
R93
C57
220u(A)
R99
100
1
(short)
J5
ROUT
5
R104
(open)
OPA604
+
C68
(open)
R105
C69
0.01u(F)
2
3
4
5
(short)
C70
220u(A)
+
A
A
Title
Size
A3
- 39 5
4
3
Date:
2
AKD4495-SA
Document Number
External LPF
Tuesday, September 10, 2013
Rev
0
Sheet
1
4
of
5
5
4
3
2
1
J1
+15V
J3
-15V
VOP+
VOPR106
(short)
R107
10
R111
10
AVDD
C71
100u(A)
Q1
D
R108
6.8k
R109
R110
3k
5.6k
R112
(short)
C75
0.01u(F)
C77
470u(A)
R113
6.8k
C81
100u(A)
+
2
C78
100p(F)
+
3
4
D4
HZ2ALL
C82
220p(F)
U9
NC
NC
-IN
V+
+IN
V-
OUT
NC
C72
100u(A)
D
DVDD
C73
100u(A)
D3V
C74
C76
100p(F)
0.01u(F)
D3
HZ2ALL
1
+
BCP 56
+
+
J2
GND
8
7
6
5
Q2
SB1188 CSC
C79
470u(A)
+
C80
100u(A)
+
R114
3.3k
AVSS
C83
100p(F)
DVSS
AD817A/AN
C
C
R115
Q3
R116
R117
6.8k
5.6k
R118
3k
R119
(short)
C86
0.01u(F)
C88
470u(A)
D5
HZ2ALL
1
+
R120
1k
C92
100u(A)
2
C89
100p(F)
+
3
4
D6
HZ2C2
BCP 56
C93
220p(F)
U10
NC
NC
-IN
V+
+IN
V-
OUT
NC
+
(short)
VREF
C84
100u(A)
C85
C87
100p(F)
0.01u(F)
R200
1k
8
7
6
5
Q4
2SB1188 CSC
C90
470u(A)
+
C91
100u(A)
+
R121
3.3k
C94
100p(F)
VREFGND
AD817A/AN
B
B
R122
Q5
R123
6.8k
R124
R125
3k
5.6k
R126
(short)
C97
0.01u(F)
C99
470u(A)
+
BCP 56
D7
HZ2ALL
1
R127
1k
A
C103
100u(A)
2
C100
100p(F)
+
3
4
D8
HZ2C2
C104
220p(F)
U11
NC
NC
-IN
V+
+IN
V-
OUT
NC
+
(short)
VDD
C95
100u(A)
C96
C98
100p(F)
0.01u(F)
R201
1k
8
7
6
5
Q6
2SB1188 CSC
C101
470u(A)
+
C102
100u(A)
C105
100p(F)
+
A
R128
3.3k
VDDGND
AD817A/AN
Title
Size
A3
- 40 5
4
3
Date:
2
AKD4495-SA
Document Number
Power Supply
Tuesday, September 10, 2013
Rev
0
Sheet
1
5
of
5
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