AGB2N0CS-GEVK Evaluation Board User's Manual

AGB2N0CS-GEVK
AGB2N0CS-GEVK
Evaluation Board
User's Manual
Adapter Board Overview
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The AGB2N0CS Adapter Board helps connect Demo 2×
headboards to the Demo 3 Baseboard, the AGB1N0CS−GEVK.
The Demo 3 uses a high-bandwidth USB 3.0 interface and HDMI®
connector to send sensor image data to the host computer. It supports
single/double/quad MIPI interface, dual/quad lanes of HiSPi interface,
CCP, and parallel interface. Since the Demo 2× Headboards do not use
the same connector as the Demo 3, the AGB2N0CS provides
communication between the headboard parallel and serial connectors
to communicate with the Demo 3 Baseboard interface connection.
EVAL BOARD USER’S MANUAL
Features
•
•
•
•
Demo 2× Headboard Connectors
Parallel Data Buffer Option
MIPI/HiSPi Connectors
Demo 3 Baseboard Connector
Block Diagram
Power
Distribution
Parallel Data
Parallel Data
Buffer/Driver
Pixel Clock
Frame Valid
Pixel Clock
Output
Enable
Control Signals
6
Master Clock
Demo 2x Headboard
13-pin Connector
Demo 3 Baseboard 52-pin Connector
Top View
16
Line Valid
Demo 2x Headboard
26-pin Connector
16
Line Valid
Frame Valid
5 V from Demo 3
Connector
Reset
I2C Data
I2C Clock
Serial Data
Demo 2x
Headboard
MIPI/HiSPi
Connectors
4
Serial Clock
Bottom View
Figure 1. AGB2N0CS Evaluation Board
Figure 2. Block Diagram of AGB2N0CS−GEVK
© Semiconductor Components Industries, LLC, 2015
September, 2015 − Rev. 0
1
Publication Order Number:
EVBUM2311/D
AGB2N0CS−GEVK
Top View
Parallel Data Buffer
Selector P1
Demo 2× Headboard
Demo 2× Headboard
Connector J1
Figure 3. Top View of Adapter Board with Default Jumpers, Test Pins and Connectors
Bottom View
MIPI/HiSPi Connector J5
MIPI/HiSPi Connector J6
Demo 3 Baseboard
Connector J8
Figure 4. Bottom View of Adapter Board with Connectors
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2
AGB2N0CS−GEVK
Jumper Pin Location
The jumpers on headboards start with Pin 1 on the
leftmost side of the pin. Grouped jumpers increase in pin
size with each jumper added.
Pin 1
Pins 1−4
Figure 5. Pin Locations for a Single Jumper. Pin 1 is Located at the Leftmost Side
Headboard Connectors
The Demo 2× headboard connectors are described in the
pinouts in Tables 1 and 2. The headboard connector has a
14-pin and 26-pin connector, as well as two MIPI/HiSPi
connectors.
Jumper/Header Functions & Default Positions
The P1 jumper/header configuration allows configuration
of parallel data. Its default position shorts pins 2−3, which
enables the parallel data buffer to pass parallel data signals.
When pins 1−2 are shorted, the parallel data buffer is
disabled.
Baseboard Connector
The Demo 3 Baseboard connector is shown in the pinout
in Table 3. The Demo 3 connector has a serial sensor data
input, I2C control interface, headboard power, and parallel
image data interface.
AGB2N0CS−GEVK Connectors
The evaluation board supports has various different
connectors on-board, including a Demo 3 connector, two
MIPI/HiSPi connectors for the Demo 2× headboard, the
14-pin Demo 2× headboard connector, and 26-pin Demo 2×
headboard connector.
Table 1. 26-PIN DEMO 2X HEADBOARD CONNECTOR FUNCTION DESCRIPTION (J1)
Pin
Name
Description
DIR
1
S_DATA8
Parallel Data8
I/O
Parallel Data Bit
Comment
2
S_DATA9
Parallel Data9
I/O
Parallel Data Bit
3
S_DATA10
Parallel Data10
I/O
Parallel Data Bit
4
S_DATA11
Parallel Data11
I/O
Parallel Data Bit
5
S_DATA12
Parallel Data12
I/O
Parallel Data Bit
6
S_DATA13
Parallel Data13
I/O
Parallel Data Bit
7
S_DATA14
Parallel Data14
I/O
Parallel Data Bit
8
S_DATA15
Parallel Data15
I/O
Parallel Data Bit
9
S_DATA6
Parallel Data6
I/O
Parallel Data Bit
10
S_DATA7
Parallel Data7
I/O
Parallel Data Bit
11
GND
Ground
PWR
12
GND
Ground
PWR
13
S_LINE_VALID
Parallel Line Valid
Out
Check Line Valid Signal
14
S_SP5
General Control Signal 5
Out
Signal @ +3.3 V Level
15
NOT USED
Not Used
NA
16
HEAD_RESET_L
Reset Signal to Sensor
In
17
S_FRAME_VALID
Parallel Frame Valid
Out
Check Frame Valid Signal
Reset to Headboard Sensor
18
HEAD_SDA
I2C
Data to Sensor
I/O
Signal @ +3.3 V Level
19
HEAD_SCL
I2C Clock to Sensor
I/O
Signal @ +3.3 V Level
20
NOT USED
Not Used
NA
21
+5V0_HEAD
+5V0 Power Input
PWR
For Powering Up the Headboard
22
+5V0_HEAD
+5V0 Power Input
PWR
For Powering Up the Headboard
23
S_PIXCLK
Parallel Pixel Clock
In
24
GND
Ground
PWR
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3
Parallel Data Pixel Clock
AGB2N0CS−GEVK
Table 1. 26-PIN DEMO 2X HEADBOARD CONNECTOR FUNCTION DESCRIPTION (J1) (continued)
Pin
Name
Description
DIR
25
GND
Ground
PWR
26
MCLK
Master Clock
In
Comment
Master Clock from Demo 3 Board
Table 2. 14-PIN DEMO 2X HEADBOARD CONNECTOR FUNCTION DESCRIPTION (J2)
Pin
Name
Description
DIR
1
GND
Ground
PWR
2
S_DATA4
Parallel Data4
I/O
Parallel Data Bit
3
S_DATA5
Parallel Data5
I/O
Parallel Data Bit
4
S_DATA2
Parallel Data2
I/O
Parallel Data Bit
5
S_DATA3
Parallel Data3
I/O
Parallel Data Bit
6
S_DATA0
Parallel Data0
I/O
Parallel Data Bit
7
S_DATA1
Parallel Data1
I/O
Parallel Data Bit
8
S_SP0
General Control Signal 0
Out
Signal @ +3.3 V Level
9
S_SP1
General Control Signal 1
Out
Signal @ +3.3 V Level
10
S_SP2
General Control Signal 2
Out
Signal @ +3.3 V Level
11
S_SP3
General Control Signal 3
Out
Signal @ +3.3 V Level
12
S_SP4
General Control Signal 4
Out
Signal @ +3.3 V Level
13
+3V3_HEAD
+3.3 V to Headboard
PWR
14
GND
Ground
PWR
Shorted Jumper for Power Measurement
Different supplies to the headboard are provided by trace
shorted jumper, for any voltage and power measurements.
To conduct current for current measurement on a given
power rail, cut the trace between the two pins of their
respective JP, and insert an ammeter prior to powering up the
system. The figure below shows where the trace to cut is
located.
Comment
For Powering Up the Headboard
Table 3. SHORTED JUMPERS FOR POWER
MEASUREMENT
Jumper
Voltage (V)
JP1 (+5V0 HEAD)
5.0
JP2 (+3V3 HEAD)
3.3
Cut Here
Figure 6. Top and Bottom View of Shorted Jumper. The Bottom View Shows the Trace Location
to Cut for Current Measurement
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